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util: remove LIST_IS_EMPTY macro
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
33
34 #include "ac_debug.h"
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 /**
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
66 *
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
69 */
70 static void si_emit_derived_tess_state(struct si_context *sctx,
71 const struct pipe_draw_info *info,
72 unsigned *num_patches)
73 {
74 struct radeon_cmdbuf *cs = sctx->gfx_cs;
75 struct si_shader *ls_current;
76 struct si_shader_selector *ls;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector *tcs =
80 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
81 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
82 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
83 sctx->screen->info.max_se == 1;
84 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
85 unsigned num_tcs_input_cp = info->vertices_per_patch;
86 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
87 unsigned num_tcs_patch_outputs;
88 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
89 unsigned input_patch_size, output_patch_size, output_patch0_offset;
90 unsigned perpatch_output_offset, lds_size;
91 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
92 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
93
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx->chip_class >= GFX9) {
96 if (sctx->tcs_shader.cso)
97 ls_current = sctx->tcs_shader.current;
98 else
99 ls_current = sctx->fixed_func_tcs_shader.current;
100
101 ls = ls_current->key.part.tcs.ls;
102 } else {
103 ls_current = sctx->vs_shader.current;
104 ls = sctx->vs_shader.cso;
105 }
106
107 if (sctx->last_ls == ls_current &&
108 sctx->last_tcs == tcs &&
109 sctx->last_tes_sh_base == tes_sh_base &&
110 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
111 (!has_primid_instancing_bug ||
112 (sctx->last_tess_uses_primid == tess_uses_primid))) {
113 *num_patches = sctx->last_num_patches;
114 return;
115 }
116
117 sctx->last_ls = ls_current;
118 sctx->last_tcs = tcs;
119 sctx->last_tes_sh_base = tes_sh_base;
120 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
121 sctx->last_tess_uses_primid = tess_uses_primid;
122
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs = util_last_bit64(ls->outputs_written);
126
127 if (sctx->tcs_shader.cso) {
128 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
129 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
130 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
131 } else {
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs = num_tcs_inputs;
134 num_tcs_output_cp = num_tcs_input_cp;
135 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
136 }
137
138 input_vertex_size = ls->lshs_vertex_stride;
139 output_vertex_size = num_tcs_outputs * 16;
140
141 input_patch_size = num_tcs_input_cp * input_vertex_size;
142
143 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
144 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
145
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
149 */
150 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
151 *num_patches = 256 / max_verts_per_patch;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 *
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
159 */
160 hardware_lds_size = 32768;
161 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
162 output_patch_size));
163
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches = MIN2(*num_patches,
166 (sctx->screen->tess_offchip_block_dw_size * 4) /
167 output_patch_size);
168
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
171 * limited to 6 bits.
172 */
173 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
174
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
177 */
178 if (!sctx->screen->info.has_distributed_tess && sctx->screen->info.max_se > 1)
179 *num_patches = MIN2(*num_patches, 16); /* recommended */
180
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
184 */
185 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
186 unsigned wave_size = sctx->screen->ge_wave_size;
187
188 if (temp_verts_per_tg > wave_size && temp_verts_per_tg % wave_size < wave_size*3/4)
189 *num_patches = (temp_verts_per_tg & ~(wave_size - 1)) / max_verts_per_patch;
190
191 if (sctx->chip_class == GFX6) {
192 /* GFX6 bug workaround, related to power management. Limit LS-HS
193 * threadgroups to only one wave.
194 */
195 unsigned one_wave = wave_size / max_verts_per_patch;
196 *num_patches = MIN2(*num_patches, one_wave);
197 }
198
199 /* The VGT HS block increments the patch ID unconditionally
200 * within a single threadgroup. This results in incorrect
201 * patch IDs when instanced draws are used.
202 *
203 * The intended solution is to restrict threadgroups to
204 * a single instance by setting SWITCH_ON_EOI, which
205 * should cause IA to split instances up. However, this
206 * doesn't work correctly on GFX6 when there is no other
207 * SE to switch to.
208 */
209 if (has_primid_instancing_bug && tess_uses_primid)
210 *num_patches = 1;
211
212 sctx->last_num_patches = *num_patches;
213
214 output_patch0_offset = input_patch_size * *num_patches;
215 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
216
217 /* Compute userdata SGPRs. */
218 assert(((input_vertex_size / 4) & ~0xff) == 0);
219 assert(((output_vertex_size / 4) & ~0xff) == 0);
220 assert(((input_patch_size / 4) & ~0x1fff) == 0);
221 assert(((output_patch_size / 4) & ~0x1fff) == 0);
222 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
223 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
224 assert(num_tcs_input_cp <= 32);
225 assert(num_tcs_output_cp <= 32);
226
227 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
228 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
229
230 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
231 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
232 tcs_out_layout = (output_patch_size / 4) |
233 (num_tcs_input_cp << 13) |
234 ring_va;
235 tcs_out_offsets = (output_patch0_offset / 16) |
236 ((perpatch_output_offset / 16) << 16);
237 offchip_layout = *num_patches |
238 (num_tcs_output_cp << 6) |
239 (pervertex_output_patch_size * *num_patches << 12);
240
241 /* Compute the LDS size. */
242 lds_size = output_patch0_offset + output_patch_size * *num_patches;
243
244 if (sctx->chip_class >= GFX7) {
245 assert(lds_size <= 65536);
246 lds_size = align(lds_size, 512) / 512;
247 } else {
248 assert(lds_size <= 32768);
249 lds_size = align(lds_size, 256) / 256;
250 }
251
252 /* Set SI_SGPR_VS_STATE_BITS. */
253 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
254 C_VS_STATE_LS_OUT_VERTEX_SIZE;
255 sctx->current_vs_state |= tcs_in_layout;
256
257 /* We should be able to support in-shader LDS use with LLVM >= 9
258 * by just adding the lds_sizes together, but it has never
259 * been tested. */
260 assert(ls_current->config.lds_size == 0);
261
262 if (sctx->chip_class >= GFX9) {
263 unsigned hs_rsrc2 = ls_current->config.rsrc2;
264
265 if (sctx->chip_class >= GFX10)
266 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(lds_size);
267 else
268 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(lds_size);
269
270 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
271
272 /* Set userdata SGPRs for merged LS-HS. */
273 radeon_set_sh_reg_seq(cs,
274 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
275 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
276 radeon_emit(cs, offchip_layout);
277 radeon_emit(cs, tcs_out_offsets);
278 radeon_emit(cs, tcs_out_layout);
279 } else {
280 unsigned ls_rsrc2 = ls_current->config.rsrc2;
281
282 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
283 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
284
285 /* Due to a hw bug, RSRC2_LS must be written twice with another
286 * LS register written in between. */
287 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
288 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
289 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
290 radeon_emit(cs, ls_current->config.rsrc1);
291 radeon_emit(cs, ls_rsrc2);
292
293 /* Set userdata SGPRs for TCS. */
294 radeon_set_sh_reg_seq(cs,
295 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
296 radeon_emit(cs, offchip_layout);
297 radeon_emit(cs, tcs_out_offsets);
298 radeon_emit(cs, tcs_out_layout);
299 radeon_emit(cs, tcs_in_layout);
300 }
301
302 /* Set userdata SGPRs for TES. */
303 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
304 radeon_emit(cs, offchip_layout);
305 radeon_emit(cs, ring_va);
306
307 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
308 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
309 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
310
311 if (sctx->last_ls_hs_config != ls_hs_config) {
312 if (sctx->chip_class >= GFX7) {
313 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
314 ls_hs_config);
315 } else {
316 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
317 ls_hs_config);
318 }
319 sctx->last_ls_hs_config = ls_hs_config;
320 sctx->context_roll = true;
321 }
322 }
323
324 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
325 enum pipe_prim_type prim)
326 {
327 switch (prim) {
328 case PIPE_PRIM_PATCHES:
329 return info->count / info->vertices_per_patch;
330 case PIPE_PRIM_POLYGON:
331 return info->count >= 3;
332 case SI_PRIM_RECTANGLE_LIST:
333 return info->count / 3;
334 default:
335 return u_decomposed_prims_for_vertices(prim, info->count);
336 }
337 }
338
339 static unsigned
340 si_get_init_multi_vgt_param(struct si_screen *sscreen,
341 union si_vgt_param_key *key)
342 {
343 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
344 unsigned max_primgroup_in_wave = 2;
345
346 /* SWITCH_ON_EOP(0) is always preferable. */
347 bool wd_switch_on_eop = false;
348 bool ia_switch_on_eop = false;
349 bool ia_switch_on_eoi = false;
350 bool partial_vs_wave = false;
351 bool partial_es_wave = false;
352
353 if (key->u.uses_tess) {
354 /* SWITCH_ON_EOI must be set if PrimID is used. */
355 if (key->u.tess_uses_prim_id)
356 ia_switch_on_eoi = true;
357
358 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
359 if ((sscreen->info.family == CHIP_TAHITI ||
360 sscreen->info.family == CHIP_PITCAIRN ||
361 sscreen->info.family == CHIP_BONAIRE) &&
362 key->u.uses_gs)
363 partial_vs_wave = true;
364
365 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
366 if (sscreen->info.has_distributed_tess) {
367 if (key->u.uses_gs) {
368 if (sscreen->info.chip_class == GFX8)
369 partial_es_wave = true;
370 } else {
371 partial_vs_wave = true;
372 }
373 }
374 }
375
376 /* This is a hardware requirement. */
377 if (key->u.line_stipple_enabled ||
378 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
379 ia_switch_on_eop = true;
380 wd_switch_on_eop = true;
381 }
382
383 if (sscreen->info.chip_class >= GFX7) {
384 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
385 * 4 shader engines. Set 1 to pass the assertion below.
386 * The other cases are hardware requirements.
387 *
388 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
389 * for points, line strips, and tri strips.
390 */
391 if (sscreen->info.max_se <= 2 ||
392 key->u.prim == PIPE_PRIM_POLYGON ||
393 key->u.prim == PIPE_PRIM_LINE_LOOP ||
394 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
395 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
396 (key->u.primitive_restart &&
397 (sscreen->info.family < CHIP_POLARIS10 ||
398 (key->u.prim != PIPE_PRIM_POINTS &&
399 key->u.prim != PIPE_PRIM_LINE_STRIP &&
400 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
401 key->u.count_from_stream_output)
402 wd_switch_on_eop = true;
403
404 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
405 * We don't know that for indirect drawing, so treat it as
406 * always problematic. */
407 if (sscreen->info.family == CHIP_HAWAII &&
408 key->u.uses_instancing)
409 wd_switch_on_eop = true;
410
411 /* Performance recommendation for 4 SE Gfx7-8 parts if
412 * instances are smaller than a primgroup.
413 * Assume indirect draws always use small instances.
414 * This is needed for good VS wave utilization.
415 */
416 if (sscreen->info.chip_class <= GFX8 &&
417 sscreen->info.max_se == 4 &&
418 key->u.multi_instances_smaller_than_primgroup)
419 wd_switch_on_eop = true;
420
421 /* Required on GFX7 and later. */
422 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
423 ia_switch_on_eoi = true;
424
425 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
426 * to work around a GS hang.
427 */
428 if (key->u.uses_gs &&
429 (sscreen->info.family == CHIP_TONGA ||
430 sscreen->info.family == CHIP_FIJI ||
431 sscreen->info.family == CHIP_POLARIS10 ||
432 sscreen->info.family == CHIP_POLARIS11 ||
433 sscreen->info.family == CHIP_POLARIS12 ||
434 sscreen->info.family == CHIP_VEGAM))
435 partial_vs_wave = true;
436
437 /* Required by Hawaii and, for some special cases, by GFX8. */
438 if (ia_switch_on_eoi &&
439 (sscreen->info.family == CHIP_HAWAII ||
440 (sscreen->info.chip_class == GFX8 &&
441 (key->u.uses_gs || max_primgroup_in_wave != 2))))
442 partial_vs_wave = true;
443
444 /* Instancing bug on Bonaire. */
445 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
446 key->u.uses_instancing)
447 partial_vs_wave = true;
448
449 /* This only applies to Polaris10 and later 4 SE chips.
450 * wd_switch_on_eop is already true on all other chips.
451 */
452 if (!wd_switch_on_eop && key->u.primitive_restart)
453 partial_vs_wave = true;
454
455 /* If the WD switch is false, the IA switch must be false too. */
456 assert(wd_switch_on_eop || !ia_switch_on_eop);
457 }
458
459 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
460 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
461 partial_es_wave = true;
462
463 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
464 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
465 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
466 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
467 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
468 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
469 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
470 max_primgroup_in_wave : 0) |
471 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
472 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
473 }
474
475 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
476 {
477 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
478 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
479 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
480 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
481 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
482 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
483 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
484 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
485 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
486 union si_vgt_param_key key;
487
488 key.index = 0;
489 key.u.prim = prim;
490 key.u.uses_instancing = uses_instancing;
491 key.u.multi_instances_smaller_than_primgroup = multi_instances;
492 key.u.primitive_restart = primitive_restart;
493 key.u.count_from_stream_output = count_from_so;
494 key.u.line_stipple_enabled = line_stipple;
495 key.u.uses_tess = uses_tess;
496 key.u.tess_uses_prim_id = tess_uses_primid;
497 key.u.uses_gs = uses_gs;
498
499 sctx->ia_multi_vgt_param[key.index] =
500 si_get_init_multi_vgt_param(sctx->screen, &key);
501 }
502 }
503
504 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
505 const struct pipe_draw_info *info,
506 enum pipe_prim_type prim,
507 unsigned num_patches,
508 unsigned instance_count,
509 bool primitive_restart)
510 {
511 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
512 unsigned primgroup_size;
513 unsigned ia_multi_vgt_param;
514
515 if (sctx->tes_shader.cso) {
516 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
517 } else if (sctx->gs_shader.cso) {
518 primgroup_size = 64; /* recommended with a GS */
519 } else {
520 primgroup_size = 128; /* recommended without a GS and tess */
521 }
522
523 key.u.prim = prim;
524 key.u.uses_instancing = info->indirect || instance_count > 1;
525 key.u.multi_instances_smaller_than_primgroup =
526 info->indirect ||
527 (instance_count > 1 &&
528 (info->count_from_stream_output ||
529 si_num_prims_for_vertices(info, prim) < primgroup_size));
530 key.u.primitive_restart = primitive_restart;
531 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
532
533 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
534 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
535
536 if (sctx->gs_shader.cso) {
537 /* GS requirement. */
538 if (sctx->chip_class <= GFX8 &&
539 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
540 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
541
542 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
543 * The hw doc says all multi-SE chips are affected, but Vulkan
544 * only applies it to Hawaii. Do what Vulkan does.
545 */
546 if (sctx->family == CHIP_HAWAII &&
547 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
548 (info->indirect ||
549 (instance_count > 1 &&
550 (info->count_from_stream_output ||
551 si_num_prims_for_vertices(info, prim) <= 1))))
552 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
553 }
554
555 return ia_multi_vgt_param;
556 }
557
558 static unsigned si_conv_prim_to_gs_out(unsigned mode)
559 {
560 static const int prim_conv[] = {
561 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
562 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
563 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
564 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
565 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
566 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
567 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
568 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
569 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
570 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
571 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
572 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
573 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
574 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
575 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
576 [SI_PRIM_RECTANGLE_LIST] = V_028A6C_VGT_OUT_RECT_V0,
577 };
578 assert(mode < ARRAY_SIZE(prim_conv));
579
580 return prim_conv[mode];
581 }
582
583 /* rast_prim is the primitive type after GS. */
584 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
585 {
586 struct radeon_cmdbuf *cs = sctx->gfx_cs;
587 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
588 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
589 bool use_ngg = sctx->screen->use_ngg;
590
591 if (likely(rast_prim == sctx->last_rast_prim &&
592 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple &&
593 (!use_ngg ||
594 rs->flatshade_first == sctx->last_flatshade_first)))
595 return;
596
597 if (util_prim_is_lines(rast_prim)) {
598 /* For lines, reset the stipple pattern at each primitive. Otherwise,
599 * reset the stipple pattern at each packet (line strips, line loops).
600 */
601 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
602 rs->pa_sc_line_stipple |
603 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
604 sctx->context_roll = true;
605 }
606
607 unsigned gs_out = si_conv_prim_to_gs_out(sctx->current_rast_prim);
608
609 if (rast_prim != sctx->last_rast_prim &&
610 (sctx->ngg || sctx->gs_shader.cso)) {
611 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
612 sctx->context_roll = true;
613
614 if (use_ngg) {
615 sctx->current_vs_state &= C_VS_STATE_OUTPRIM;
616 sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out);
617 }
618 }
619
620 if (use_ngg) {
621 unsigned vtx_index = rs->flatshade_first ? 0 : gs_out;
622 sctx->current_vs_state &= C_VS_STATE_PROVOKING_VTX_INDEX;
623 sctx->current_vs_state |= S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
624 }
625
626 sctx->last_rast_prim = rast_prim;
627 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
628 sctx->last_flatshade_first = rs->flatshade_first;
629 }
630
631 static void si_emit_vs_state(struct si_context *sctx,
632 const struct pipe_draw_info *info)
633 {
634 sctx->current_vs_state &= C_VS_STATE_INDEXED;
635 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
636
637 if (sctx->num_vs_blit_sgprs) {
638 /* Re-emit the state after we leave u_blitter. */
639 sctx->last_vs_state = ~0;
640 return;
641 }
642
643 if (sctx->current_vs_state != sctx->last_vs_state) {
644 struct radeon_cmdbuf *cs = sctx->gfx_cs;
645
646 /* For the API vertex shader (VS_STATE_INDEXED, LS_OUT_*). */
647 radeon_set_sh_reg(cs,
648 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
649 SI_SGPR_VS_STATE_BITS * 4,
650 sctx->current_vs_state);
651
652 /* Set CLAMP_VERTEX_COLOR and OUTPRIM in the last stage
653 * before the rasterizer.
654 *
655 * For TES or the GS copy shader without NGG:
656 */
657 if (sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
658 R_00B130_SPI_SHADER_USER_DATA_VS_0) {
659 radeon_set_sh_reg(cs,
660 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
661 SI_SGPR_VS_STATE_BITS * 4,
662 sctx->current_vs_state);
663 }
664
665 /* For NGG: */
666 if (sctx->screen->use_ngg &&
667 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
668 R_00B230_SPI_SHADER_USER_DATA_GS_0) {
669 radeon_set_sh_reg(cs,
670 R_00B230_SPI_SHADER_USER_DATA_GS_0 +
671 SI_SGPR_VS_STATE_BITS * 4,
672 sctx->current_vs_state);
673 }
674
675 sctx->last_vs_state = sctx->current_vs_state;
676 }
677 }
678
679 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
680 bool primitive_restart,
681 unsigned restart_index)
682 {
683 return primitive_restart &&
684 (restart_index != sctx->last_restart_index ||
685 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
686 }
687
688 static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
689 const struct pipe_draw_info *info,
690 enum pipe_prim_type prim,
691 unsigned num_patches,
692 unsigned instance_count,
693 bool primitive_restart)
694 {
695 struct radeon_cmdbuf *cs = sctx->gfx_cs;
696 unsigned ia_multi_vgt_param;
697
698 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
699 instance_count, primitive_restart);
700
701 /* Draw state. */
702 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
703 if (sctx->chip_class == GFX9)
704 radeon_set_uconfig_reg_idx(cs, sctx->screen,
705 R_030960_IA_MULTI_VGT_PARAM, 4,
706 ia_multi_vgt_param);
707 else if (sctx->chip_class >= GFX7)
708 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
709 else
710 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
711
712 sctx->last_multi_vgt_param = ia_multi_vgt_param;
713 }
714 }
715
716 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
717 * We overload last_multi_vgt_param.
718 */
719 static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
720 {
721 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
722 unsigned ge_cntl;
723
724 if (sctx->ngg) {
725 if (sctx->tes_shader.cso) {
726 ge_cntl = S_03096C_PRIM_GRP_SIZE(num_patches) |
727 S_03096C_VERT_GRP_SIZE(0) |
728 S_03096C_BREAK_WAVE_AT_EOI(key.u.tess_uses_prim_id);
729 } else {
730 ge_cntl = si_get_vs_state(sctx)->ge_cntl;
731 }
732 } else {
733 unsigned primgroup_size;
734 unsigned vertgroup_size;
735
736 if (sctx->tes_shader.cso) {
737 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
738 vertgroup_size = 0;
739 } else if (sctx->gs_shader.cso) {
740 unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
741 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
742 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
743 } else {
744 primgroup_size = 128; /* recommended without a GS and tess */
745 vertgroup_size = 0;
746 }
747
748 ge_cntl = S_03096C_PRIM_GRP_SIZE(primgroup_size) |
749 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
750 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
751 }
752
753 ge_cntl |= S_03096C_PACKET_TO_ONE_PA(key.u.line_stipple_enabled);
754
755 if (ge_cntl != sctx->last_multi_vgt_param) {
756 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
757 sctx->last_multi_vgt_param = ge_cntl;
758 }
759 }
760
761 static void si_emit_draw_registers(struct si_context *sctx,
762 const struct pipe_draw_info *info,
763 enum pipe_prim_type prim,
764 unsigned num_patches,
765 unsigned instance_count,
766 bool primitive_restart)
767 {
768 struct radeon_cmdbuf *cs = sctx->gfx_cs;
769 unsigned vgt_prim = si_conv_pipe_prim(prim);
770
771 if (sctx->chip_class >= GFX10)
772 gfx10_emit_ge_cntl(sctx, num_patches);
773 else
774 si_emit_ia_multi_vgt_param(sctx, info, prim, num_patches,
775 instance_count, primitive_restart);
776
777 if (vgt_prim != sctx->last_prim) {
778 if (sctx->chip_class >= GFX10)
779 radeon_set_uconfig_reg(cs, R_030908_VGT_PRIMITIVE_TYPE, vgt_prim);
780 else if (sctx->chip_class >= GFX7)
781 radeon_set_uconfig_reg_idx(cs, sctx->screen,
782 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
783 else
784 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
785
786 sctx->last_prim = vgt_prim;
787 }
788
789 /* Primitive restart. */
790 if (primitive_restart != sctx->last_primitive_restart_en) {
791 if (sctx->chip_class >= GFX9)
792 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
793 primitive_restart);
794 else
795 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
796 primitive_restart);
797
798 sctx->last_primitive_restart_en = primitive_restart;
799
800 }
801 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
802 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
803 info->restart_index);
804 sctx->last_restart_index = info->restart_index;
805 sctx->context_roll = true;
806 }
807 }
808
809 static void si_emit_draw_packets(struct si_context *sctx,
810 const struct pipe_draw_info *info,
811 struct pipe_resource *indexbuf,
812 unsigned index_size,
813 unsigned index_offset,
814 unsigned instance_count,
815 bool dispatch_prim_discard_cs,
816 unsigned original_index_size)
817 {
818 struct pipe_draw_indirect_info *indirect = info->indirect;
819 struct radeon_cmdbuf *cs = sctx->gfx_cs;
820 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
821 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
822 uint32_t index_max_size = 0;
823 uint64_t index_va = 0;
824
825 if (info->count_from_stream_output) {
826 struct si_streamout_target *t =
827 (struct si_streamout_target*)info->count_from_stream_output;
828
829 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
830 t->stride_in_dw);
831 si_cp_copy_data(sctx, sctx->gfx_cs,
832 COPY_DATA_REG, NULL,
833 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
834 COPY_DATA_SRC_MEM, t->buf_filled_size,
835 t->buf_filled_size_offset);
836 }
837
838 /* draw packet */
839 if (index_size) {
840 if (index_size != sctx->last_index_size) {
841 unsigned index_type;
842
843 /* index type */
844 switch (index_size) {
845 case 1:
846 index_type = V_028A7C_VGT_INDEX_8;
847 break;
848 case 2:
849 index_type = V_028A7C_VGT_INDEX_16 |
850 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
851 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
852 break;
853 case 4:
854 index_type = V_028A7C_VGT_INDEX_32 |
855 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
856 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
857 break;
858 default:
859 assert(!"unreachable");
860 return;
861 }
862
863 if (sctx->chip_class >= GFX9) {
864 radeon_set_uconfig_reg_idx(cs, sctx->screen,
865 R_03090C_VGT_INDEX_TYPE, 2,
866 index_type);
867 } else {
868 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
869 radeon_emit(cs, index_type);
870 }
871
872 sctx->last_index_size = index_size;
873 }
874
875 if (original_index_size) {
876 index_max_size = (indexbuf->width0 - index_offset) /
877 original_index_size;
878 /* Skip draw calls with 0-sized index buffers.
879 * They cause a hang on some chips, like Navi10-14.
880 */
881 if (!index_max_size)
882 return;
883
884 index_va = si_resource(indexbuf)->gpu_address + index_offset;
885
886 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
887 si_resource(indexbuf),
888 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
889 }
890 } else {
891 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
892 * so the state must be re-emitted before the next indexed draw.
893 */
894 if (sctx->chip_class >= GFX7)
895 sctx->last_index_size = -1;
896 }
897
898 if (indirect) {
899 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
900
901 assert(indirect_va % 8 == 0);
902
903 si_invalidate_draw_sh_constants(sctx);
904
905 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
906 radeon_emit(cs, 1);
907 radeon_emit(cs, indirect_va);
908 radeon_emit(cs, indirect_va >> 32);
909
910 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
911 si_resource(indirect->buffer),
912 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
913
914 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
915 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
916
917 assert(indirect->offset % 4 == 0);
918
919 if (index_size) {
920 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
921 radeon_emit(cs, index_va);
922 radeon_emit(cs, index_va >> 32);
923
924 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
925 radeon_emit(cs, index_max_size);
926 }
927
928 if (!sctx->screen->has_draw_indirect_multi) {
929 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
930 : PKT3_DRAW_INDIRECT,
931 3, render_cond_bit));
932 radeon_emit(cs, indirect->offset);
933 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
934 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
935 radeon_emit(cs, di_src_sel);
936 } else {
937 uint64_t count_va = 0;
938
939 if (indirect->indirect_draw_count) {
940 struct si_resource *params_buf =
941 si_resource(indirect->indirect_draw_count);
942
943 radeon_add_to_buffer_list(
944 sctx, sctx->gfx_cs, params_buf,
945 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
946
947 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
948 }
949
950 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
951 PKT3_DRAW_INDIRECT_MULTI,
952 8, render_cond_bit));
953 radeon_emit(cs, indirect->offset);
954 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
955 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
956 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
957 S_2C3_DRAW_INDEX_ENABLE(1) |
958 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
959 radeon_emit(cs, indirect->draw_count);
960 radeon_emit(cs, count_va);
961 radeon_emit(cs, count_va >> 32);
962 radeon_emit(cs, indirect->stride);
963 radeon_emit(cs, di_src_sel);
964 }
965 } else {
966 int base_vertex;
967
968 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
969 sctx->last_instance_count != instance_count) {
970 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
971 radeon_emit(cs, instance_count);
972 sctx->last_instance_count = instance_count;
973 }
974
975 /* Base vertex and start instance. */
976 base_vertex = original_index_size ? info->index_bias : info->start;
977
978 if (sctx->num_vs_blit_sgprs) {
979 /* Re-emit draw constants after we leave u_blitter. */
980 si_invalidate_draw_sh_constants(sctx);
981
982 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
983 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
984 sctx->num_vs_blit_sgprs);
985 radeon_emit_array(cs, sctx->vs_blit_sh_data,
986 sctx->num_vs_blit_sgprs);
987 } else if (base_vertex != sctx->last_base_vertex ||
988 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
989 info->start_instance != sctx->last_start_instance ||
990 info->drawid != sctx->last_drawid ||
991 sh_base_reg != sctx->last_sh_base_reg) {
992 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
993 radeon_emit(cs, base_vertex);
994 radeon_emit(cs, info->start_instance);
995 radeon_emit(cs, info->drawid);
996
997 sctx->last_base_vertex = base_vertex;
998 sctx->last_start_instance = info->start_instance;
999 sctx->last_drawid = info->drawid;
1000 sctx->last_sh_base_reg = sh_base_reg;
1001 }
1002
1003 if (index_size) {
1004 if (dispatch_prim_discard_cs) {
1005 index_va += info->start * original_index_size;
1006 index_max_size = MIN2(index_max_size, info->count);
1007
1008 si_dispatch_prim_discard_cs_and_draw(sctx, info,
1009 original_index_size,
1010 base_vertex,
1011 index_va, index_max_size);
1012 return;
1013 }
1014
1015 index_va += info->start * index_size;
1016
1017 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1018 radeon_emit(cs, index_max_size);
1019 radeon_emit(cs, index_va);
1020 radeon_emit(cs, index_va >> 32);
1021 radeon_emit(cs, info->count);
1022 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
1023 } else {
1024 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
1025 radeon_emit(cs, info->count);
1026 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1027 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
1028 }
1029 }
1030 }
1031
1032 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
1033 unsigned cp_coher_cntl)
1034 {
1035 bool compute_ib = !sctx->has_graphics ||
1036 cs == sctx->prim_discard_compute_cs;
1037
1038 assert(sctx->chip_class <= GFX9);
1039
1040 if (sctx->chip_class == GFX9 || compute_ib) {
1041 /* Flush caches and wait for the caches to assert idle. */
1042 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
1043 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1044 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1045 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1046 radeon_emit(cs, 0); /* CP_COHER_BASE */
1047 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1048 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1049 } else {
1050 /* ACQUIRE_MEM is only required on a compute ring. */
1051 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
1052 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1053 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1054 radeon_emit(cs, 0); /* CP_COHER_BASE */
1055 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1056 }
1057
1058 /* ACQUIRE_MEM has an implicit context roll if the current context
1059 * is busy. */
1060 if (!compute_ib)
1061 sctx->context_roll = true;
1062 }
1063
1064 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
1065 {
1066 if (!si_compute_prim_discard_enabled(sctx))
1067 return;
1068
1069 if (!sctx->barrier_buf) {
1070 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
1071 &sctx->barrier_buf_offset,
1072 (struct pipe_resource**)&sctx->barrier_buf);
1073 }
1074
1075 /* Emit a placeholder to signal the next compute IB to start.
1076 * See si_compute_prim_discard.c for explanation.
1077 */
1078 uint32_t signal = 1;
1079 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset,
1080 4, V_370_MEM, V_370_ME, &signal);
1081
1082 sctx->last_pkt3_write_data =
1083 &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
1084
1085 /* Only the last occurence of WRITE_DATA will be executed.
1086 * The packet will be enabled in si_flush_gfx_cs.
1087 */
1088 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
1089 }
1090
1091 void gfx10_emit_cache_flush(struct si_context *ctx)
1092 {
1093 struct radeon_cmdbuf *cs = ctx->gfx_cs;
1094 uint32_t gcr_cntl = 0;
1095 unsigned cb_db_event = 0;
1096 unsigned flags = ctx->flags;
1097
1098 if (!ctx->has_graphics) {
1099 /* Only process compute flags. */
1100 flags &= SI_CONTEXT_INV_ICACHE |
1101 SI_CONTEXT_INV_SCACHE |
1102 SI_CONTEXT_INV_VCACHE |
1103 SI_CONTEXT_INV_L2 |
1104 SI_CONTEXT_WB_L2 |
1105 SI_CONTEXT_INV_L2_METADATA |
1106 SI_CONTEXT_CS_PARTIAL_FLUSH;
1107 }
1108
1109 /* We don't need these. */
1110 assert(!(flags & (SI_CONTEXT_VGT_STREAMOUT_SYNC |
1111 SI_CONTEXT_FLUSH_AND_INV_DB_META)));
1112
1113 if (flags & SI_CONTEXT_VGT_FLUSH) {
1114 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1115 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1116 }
1117
1118 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1119 ctx->num_cb_cache_flushes++;
1120 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1121 ctx->num_db_cache_flushes++;
1122
1123 if (flags & SI_CONTEXT_INV_ICACHE)
1124 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1125 if (flags & SI_CONTEXT_INV_SCACHE) {
1126 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1127 * to FORWARD when both L1 and L2 are written out (WB or INV).
1128 */
1129 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1130 }
1131 if (flags & SI_CONTEXT_INV_VCACHE)
1132 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1133
1134 /* The L2 cache ops are:
1135 * - INV: - invalidate lines that reflect memory (were loaded from memory)
1136 * - don't touch lines that were overwritten (were stored by gfx clients)
1137 * - WB: - don't touch lines that reflect memory
1138 * - write back lines that were overwritten
1139 * - WB | INV: - invalidate lines that reflect memory
1140 * - write back lines that were overwritten
1141 *
1142 * GLM doesn't support WB alone. If WB is set, INV must be set too.
1143 */
1144 if (flags & SI_CONTEXT_INV_L2) {
1145 /* Writeback and invalidate everything in L2. */
1146 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
1147 S_586_GLM_INV(1) | S_586_GLM_WB(1);
1148 ctx->num_L2_invalidates++;
1149 } else if (flags & SI_CONTEXT_WB_L2) {
1150 gcr_cntl |= S_586_GL2_WB(1) |
1151 S_586_GLM_WB(1) | S_586_GLM_INV(1);
1152 } else if (flags & SI_CONTEXT_INV_L2_METADATA) {
1153 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
1154 }
1155
1156 if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1157 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1158 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1159 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1160 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1161 EVENT_INDEX(0));
1162 }
1163 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1164 /* Flush HTILE. Will wait for idle later. */
1165 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1166 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1167 EVENT_INDEX(0));
1168 }
1169
1170 /* First flush CB/DB, then L1/L2. */
1171 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1172
1173 if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
1174 (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1175 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1176 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1177 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1178 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1179 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1180 } else {
1181 assert(0);
1182 }
1183 } else {
1184 /* Wait for graphics shaders to go idle if requested. */
1185 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1186 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1187 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1188 /* Only count explicit shader flushes, not implicit ones. */
1189 ctx->num_vs_flushes++;
1190 ctx->num_ps_flushes++;
1191 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1192 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1193 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1194 ctx->num_vs_flushes++;
1195 }
1196 }
1197
1198 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
1199 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1200 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1201 ctx->num_cs_flushes++;
1202 ctx->compute_is_busy = false;
1203 }
1204
1205 if (cb_db_event) {
1206 /* CB/DB flush and invalidate (or possibly just a wait for a
1207 * meta flush) via RELEASE_MEM.
1208 *
1209 * Combine this with other cache flushes when possible; this
1210 * requires affected shaders to be idle, so do it after the
1211 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1212 * implied).
1213 */
1214 uint64_t va;
1215
1216 /* Do the flush (enqueue the event and wait for it). */
1217 va = ctx->wait_mem_scratch->gpu_address;
1218 ctx->wait_mem_number++;
1219
1220 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1221 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1222 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1223 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1224 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1225 assert(G_586_GL2_US(gcr_cntl) == 0);
1226 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1227 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1228 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1229 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1230 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1231
1232 gcr_cntl &= C_586_GLM_WB &
1233 C_586_GLM_INV &
1234 C_586_GLV_INV &
1235 C_586_GL1_INV &
1236 C_586_GL2_INV &
1237 C_586_GL2_WB; /* keep SEQ */
1238
1239 si_cp_release_mem(ctx, cs, cb_db_event,
1240 S_490_GLM_WB(glm_wb) |
1241 S_490_GLM_INV(glm_inv) |
1242 S_490_GLV_INV(glv_inv) |
1243 S_490_GL1_INV(gl1_inv) |
1244 S_490_GL2_INV(gl2_inv) |
1245 S_490_GL2_WB(gl2_wb) |
1246 S_490_SEQ(gcr_seq),
1247 EOP_DST_SEL_MEM,
1248 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1249 EOP_DATA_SEL_VALUE_32BIT,
1250 ctx->wait_mem_scratch, va,
1251 ctx->wait_mem_number, SI_NOT_QUERY);
1252 si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff,
1253 WAIT_REG_MEM_EQUAL);
1254 }
1255
1256 /* Ignore fields that only modify the behavior of other fields. */
1257 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1258 /* Flush caches and wait for the caches to assert idle.
1259 * The cache flush is executed in the ME, but the PFP waits
1260 * for completion.
1261 */
1262 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1263 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1264 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1265 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1266 radeon_emit(cs, 0); /* CP_COHER_BASE */
1267 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1268 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1269 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1270 } else if (cb_db_event ||
1271 (flags & (SI_CONTEXT_VS_PARTIAL_FLUSH |
1272 SI_CONTEXT_PS_PARTIAL_FLUSH |
1273 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1274 /* We need to ensure that PFP waits as well. */
1275 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1276 radeon_emit(cs, 0);
1277 }
1278
1279 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1280 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1281 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1282 EVENT_INDEX(0));
1283 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1284 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1285 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1286 EVENT_INDEX(0));
1287 }
1288
1289 ctx->flags = 0;
1290 }
1291
1292 void si_emit_cache_flush(struct si_context *sctx)
1293 {
1294 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1295 uint32_t flags = sctx->flags;
1296
1297 if (!sctx->has_graphics) {
1298 /* Only process compute flags. */
1299 flags &= SI_CONTEXT_INV_ICACHE |
1300 SI_CONTEXT_INV_SCACHE |
1301 SI_CONTEXT_INV_VCACHE |
1302 SI_CONTEXT_INV_L2 |
1303 SI_CONTEXT_WB_L2 |
1304 SI_CONTEXT_INV_L2_METADATA |
1305 SI_CONTEXT_CS_PARTIAL_FLUSH;
1306 }
1307
1308 uint32_t cp_coher_cntl = 0;
1309 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1310 SI_CONTEXT_FLUSH_AND_INV_DB);
1311 const bool is_barrier = flush_cb_db ||
1312 /* INV_ICACHE == beginning of gfx IB. Checking
1313 * INV_ICACHE fixes corruption for DeusExMD with
1314 * compute-based culling, but I don't know why.
1315 */
1316 flags & (SI_CONTEXT_INV_ICACHE |
1317 SI_CONTEXT_PS_PARTIAL_FLUSH |
1318 SI_CONTEXT_VS_PARTIAL_FLUSH) ||
1319 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1320 sctx->compute_is_busy);
1321
1322 assert(sctx->chip_class <= GFX9);
1323
1324 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1325 sctx->num_cb_cache_flushes++;
1326 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1327 sctx->num_db_cache_flushes++;
1328
1329 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1330 * bit is set. An alternative way is to write SQC_CACHES, but that
1331 * doesn't seem to work reliably. Since the bug doesn't affect
1332 * correctness (it only does more work than necessary) and
1333 * the performance impact is likely negligible, there is no plan
1334 * to add a workaround for it.
1335 */
1336
1337 if (flags & SI_CONTEXT_INV_ICACHE)
1338 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1339 if (flags & SI_CONTEXT_INV_SCACHE)
1340 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1341
1342 if (sctx->chip_class <= GFX8) {
1343 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1344 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1345 S_0085F0_CB0_DEST_BASE_ENA(1) |
1346 S_0085F0_CB1_DEST_BASE_ENA(1) |
1347 S_0085F0_CB2_DEST_BASE_ENA(1) |
1348 S_0085F0_CB3_DEST_BASE_ENA(1) |
1349 S_0085F0_CB4_DEST_BASE_ENA(1) |
1350 S_0085F0_CB5_DEST_BASE_ENA(1) |
1351 S_0085F0_CB6_DEST_BASE_ENA(1) |
1352 S_0085F0_CB7_DEST_BASE_ENA(1);
1353
1354 /* Necessary for DCC */
1355 if (sctx->chip_class == GFX8)
1356 si_cp_release_mem(sctx, cs,
1357 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1358 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1359 EOP_DATA_SEL_DISCARD, NULL,
1360 0, 0, SI_NOT_QUERY);
1361 }
1362 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1363 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1364 S_0085F0_DB_DEST_BASE_ENA(1);
1365 }
1366
1367 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1368 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1369 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1370 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1371 }
1372 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
1373 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1374 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1375 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1376 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1377 }
1378
1379 /* Wait for shader engines to go idle.
1380 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1381 * for everything including CB/DB cache flushes.
1382 */
1383 if (!flush_cb_db) {
1384 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1385 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1386 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1387 /* Only count explicit shader flushes, not implicit ones
1388 * done by SURFACE_SYNC.
1389 */
1390 sctx->num_vs_flushes++;
1391 sctx->num_ps_flushes++;
1392 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1393 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1394 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1395 sctx->num_vs_flushes++;
1396 }
1397 }
1398
1399 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1400 sctx->compute_is_busy) {
1401 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1402 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1403 sctx->num_cs_flushes++;
1404 sctx->compute_is_busy = false;
1405 }
1406
1407 /* VGT state synchronization. */
1408 if (flags & SI_CONTEXT_VGT_FLUSH) {
1409 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1410 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1411 }
1412 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1413 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1414 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1415 }
1416
1417 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1418 * wait for idle on GFX9. We have to use a TS event.
1419 */
1420 if (sctx->chip_class == GFX9 && flush_cb_db) {
1421 uint64_t va;
1422 unsigned tc_flags, cb_db_event;
1423
1424 /* Set the CB/DB flush event. */
1425 switch (flush_cb_db) {
1426 case SI_CONTEXT_FLUSH_AND_INV_CB:
1427 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1428 break;
1429 case SI_CONTEXT_FLUSH_AND_INV_DB:
1430 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1431 break;
1432 default:
1433 /* both CB & DB */
1434 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1435 }
1436
1437 /* These are the only allowed combinations. If you need to
1438 * do multiple operations at once, do them separately.
1439 * All operations that invalidate L2 also seem to invalidate
1440 * metadata. Volatile (VOL) and WC flushes are not listed here.
1441 *
1442 * TC | TC_WB = writeback & invalidate L2 & L1
1443 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1444 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1445 * TC | TC_NC = invalidate L2 for MTYPE == NC
1446 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1447 * TCL1 = invalidate L1
1448 */
1449 tc_flags = 0;
1450
1451 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1452 tc_flags = EVENT_TC_ACTION_ENA |
1453 EVENT_TC_MD_ACTION_ENA;
1454 }
1455
1456 /* Ideally flush TC together with CB/DB. */
1457 if (flags & SI_CONTEXT_INV_L2) {
1458 /* Writeback and invalidate everything in L2 & L1. */
1459 tc_flags = EVENT_TC_ACTION_ENA |
1460 EVENT_TC_WB_ACTION_ENA;
1461
1462 /* Clear the flags. */
1463 flags &= ~(SI_CONTEXT_INV_L2 |
1464 SI_CONTEXT_WB_L2 |
1465 SI_CONTEXT_INV_VCACHE);
1466 sctx->num_L2_invalidates++;
1467 }
1468
1469 /* Do the flush (enqueue the event and wait for it). */
1470 va = sctx->wait_mem_scratch->gpu_address;
1471 sctx->wait_mem_number++;
1472
1473 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1474 EOP_DST_SEL_MEM,
1475 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1476 EOP_DATA_SEL_VALUE_32BIT,
1477 sctx->wait_mem_scratch, va,
1478 sctx->wait_mem_number, SI_NOT_QUERY);
1479 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1480 WAIT_REG_MEM_EQUAL);
1481 }
1482
1483 /* Make sure ME is idle (it executes most packets) before continuing.
1484 * This prevents read-after-write hazards between PFP and ME.
1485 */
1486 if (sctx->has_graphics &&
1487 (cp_coher_cntl ||
1488 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1489 SI_CONTEXT_INV_VCACHE |
1490 SI_CONTEXT_INV_L2 |
1491 SI_CONTEXT_WB_L2)))) {
1492 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1493 radeon_emit(cs, 0);
1494 }
1495
1496 /* GFX6-GFX8 only:
1497 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1498 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1499 *
1500 * cp_coher_cntl should contain all necessary flags except TC flags
1501 * at this point.
1502 *
1503 * GFX6-GFX7 don't support L2 write-back.
1504 */
1505 if (flags & SI_CONTEXT_INV_L2 ||
1506 (sctx->chip_class <= GFX7 &&
1507 (flags & SI_CONTEXT_WB_L2))) {
1508 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1509 * WB must be set on GFX8+ when TC_ACTION is set.
1510 */
1511 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1512 S_0085F0_TC_ACTION_ENA(1) |
1513 S_0085F0_TCL1_ACTION_ENA(1) |
1514 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1515 cp_coher_cntl = 0;
1516 sctx->num_L2_invalidates++;
1517 } else {
1518 /* L1 invalidation and L2 writeback must be done separately,
1519 * because both operations can't be done together.
1520 */
1521 if (flags & SI_CONTEXT_WB_L2) {
1522 /* WB = write-back
1523 * NC = apply to non-coherent MTYPEs
1524 * (i.e. MTYPE <= 1, which is what we use everywhere)
1525 *
1526 * WB doesn't work without NC.
1527 */
1528 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1529 S_0301F0_TC_WB_ACTION_ENA(1) |
1530 S_0301F0_TC_NC_ACTION_ENA(1));
1531 cp_coher_cntl = 0;
1532 sctx->num_L2_writebacks++;
1533 }
1534 if (flags & SI_CONTEXT_INV_VCACHE) {
1535 /* Invalidate per-CU VMEM L1. */
1536 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1537 S_0085F0_TCL1_ACTION_ENA(1));
1538 cp_coher_cntl = 0;
1539 }
1540 }
1541
1542 /* If TC flushes haven't cleared this... */
1543 if (cp_coher_cntl)
1544 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1545
1546 if (is_barrier)
1547 si_prim_discard_signal_next_compute_ib_start(sctx);
1548
1549 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1550 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1551 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1552 EVENT_INDEX(0));
1553 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1554 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1555 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1556 EVENT_INDEX(0));
1557 }
1558
1559 sctx->flags = 0;
1560 }
1561
1562 static void si_get_draw_start_count(struct si_context *sctx,
1563 const struct pipe_draw_info *info,
1564 unsigned *start, unsigned *count)
1565 {
1566 struct pipe_draw_indirect_info *indirect = info->indirect;
1567
1568 if (indirect) {
1569 unsigned indirect_count;
1570 struct pipe_transfer *transfer;
1571 unsigned begin, end;
1572 unsigned map_size;
1573 unsigned *data;
1574
1575 if (indirect->indirect_draw_count) {
1576 data = pipe_buffer_map_range(&sctx->b,
1577 indirect->indirect_draw_count,
1578 indirect->indirect_draw_count_offset,
1579 sizeof(unsigned),
1580 PIPE_TRANSFER_READ, &transfer);
1581
1582 indirect_count = *data;
1583
1584 pipe_buffer_unmap(&sctx->b, transfer);
1585 } else {
1586 indirect_count = indirect->draw_count;
1587 }
1588
1589 if (!indirect_count) {
1590 *start = *count = 0;
1591 return;
1592 }
1593
1594 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1595 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1596 indirect->offset, map_size,
1597 PIPE_TRANSFER_READ, &transfer);
1598
1599 begin = UINT_MAX;
1600 end = 0;
1601
1602 for (unsigned i = 0; i < indirect_count; ++i) {
1603 unsigned count = data[0];
1604 unsigned start = data[2];
1605
1606 if (count > 0) {
1607 begin = MIN2(begin, start);
1608 end = MAX2(end, start + count);
1609 }
1610
1611 data += indirect->stride / sizeof(unsigned);
1612 }
1613
1614 pipe_buffer_unmap(&sctx->b, transfer);
1615
1616 if (begin < end) {
1617 *start = begin;
1618 *count = end - begin;
1619 } else {
1620 *start = *count = 0;
1621 }
1622 } else {
1623 *start = info->start;
1624 *count = info->count;
1625 }
1626 }
1627
1628 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1629 enum pipe_prim_type prim, unsigned instance_count,
1630 bool primitive_restart, unsigned skip_atom_mask)
1631 {
1632 unsigned num_patches = 0;
1633
1634 si_emit_rasterizer_prim_state(sctx);
1635 if (sctx->tes_shader.cso)
1636 si_emit_derived_tess_state(sctx, info, &num_patches);
1637
1638 /* Emit state atoms. */
1639 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1640 while (mask)
1641 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1642
1643 sctx->dirty_atoms &= skip_atom_mask;
1644
1645 /* Emit states. */
1646 mask = sctx->dirty_states;
1647 while (mask) {
1648 unsigned i = u_bit_scan(&mask);
1649 struct si_pm4_state *state = sctx->queued.array[i];
1650
1651 if (!state || sctx->emitted.array[i] == state)
1652 continue;
1653
1654 si_pm4_emit(sctx, state);
1655 sctx->emitted.array[i] = state;
1656 }
1657 sctx->dirty_states = 0;
1658
1659 /* Emit draw states. */
1660 si_emit_vs_state(sctx, info);
1661 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count,
1662 primitive_restart);
1663 }
1664
1665 static bool
1666 si_all_vs_resources_read_only(struct si_context *sctx,
1667 struct pipe_resource *indexbuf)
1668 {
1669 struct radeon_winsys *ws = sctx->ws;
1670 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1671
1672 /* Index buffer. */
1673 if (indexbuf &&
1674 ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf,
1675 RADEON_USAGE_WRITE))
1676 goto has_write_reference;
1677
1678 /* Vertex buffers. */
1679 struct si_vertex_elements *velems = sctx->vertex_elements;
1680 unsigned num_velems = velems->count;
1681
1682 for (unsigned i = 0; i < num_velems; i++) {
1683 if (!((1 << i) & velems->first_vb_use_mask))
1684 continue;
1685
1686 unsigned vb_index = velems->vertex_buffer_index[i];
1687 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1688 if (!res)
1689 continue;
1690
1691 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1692 RADEON_USAGE_WRITE))
1693 goto has_write_reference;
1694 }
1695
1696 /* Constant and shader buffers. */
1697 struct si_descriptors *buffers =
1698 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1699 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1700 unsigned index = buffers->first_active_slot + i;
1701 struct pipe_resource *res =
1702 sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1703 if (!res)
1704 continue;
1705
1706 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1707 RADEON_USAGE_WRITE))
1708 goto has_write_reference;
1709 }
1710
1711 /* Samplers. */
1712 struct si_shader_selector *vs = sctx->vs_shader.cso;
1713 if (vs->info.samplers_declared) {
1714 unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
1715
1716 for (unsigned i = 0; i < num_samplers; i++) {
1717 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1718 if (!view)
1719 continue;
1720
1721 if (ws->cs_is_buffer_referenced(cs,
1722 si_resource(view->texture)->buf,
1723 RADEON_USAGE_WRITE))
1724 goto has_write_reference;
1725 }
1726 }
1727
1728 /* Images. */
1729 if (vs->info.images_declared) {
1730 unsigned num_images = util_last_bit(vs->info.images_declared);
1731
1732 for (unsigned i = 0; i < num_images; i++) {
1733 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1734 if (!res)
1735 continue;
1736
1737 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1738 RADEON_USAGE_WRITE))
1739 goto has_write_reference;
1740 }
1741 }
1742
1743 return true;
1744
1745 has_write_reference:
1746 /* If the current gfx IB has enough packets, flush it to remove write
1747 * references to buffers.
1748 */
1749 if (cs->prev_dw + cs->current.cdw > 2048) {
1750 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1751 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1752 return true;
1753 }
1754 return false;
1755 }
1756
1757 static ALWAYS_INLINE bool pd_msg(const char *s)
1758 {
1759 if (SI_PRIM_DISCARD_DEBUG)
1760 printf("PD failed: %s\n", s);
1761 return false;
1762 }
1763
1764 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1765 {
1766 struct si_context *sctx = (struct si_context *)ctx;
1767 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1768 struct pipe_resource *indexbuf = info->index.resource;
1769 unsigned dirty_tex_counter, dirty_buf_counter;
1770 enum pipe_prim_type rast_prim, prim = info->mode;
1771 unsigned index_size = info->index_size;
1772 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1773 unsigned instance_count = info->instance_count;
1774 bool primitive_restart = info->primitive_restart &&
1775 (!sctx->screen->options.prim_restart_tri_strips_only ||
1776 (prim != PIPE_PRIM_TRIANGLE_STRIP &&
1777 prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1778
1779 if (likely(!info->indirect)) {
1780 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1781 * no workaround for indirect draws, but we can at least skip
1782 * direct draws.
1783 */
1784 if (unlikely(!instance_count))
1785 return;
1786
1787 /* Handle count == 0. */
1788 if (unlikely(!info->count &&
1789 (index_size || !info->count_from_stream_output)))
1790 return;
1791 }
1792
1793 if (unlikely(!sctx->vs_shader.cso ||
1794 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1795 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1796 assert(0);
1797 return;
1798 }
1799
1800 /* Recompute and re-emit the texture resource states if needed. */
1801 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1802 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1803 sctx->last_dirty_tex_counter = dirty_tex_counter;
1804 sctx->framebuffer.dirty_cbufs |=
1805 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1806 sctx->framebuffer.dirty_zsbuf = true;
1807 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1808 si_update_all_texture_descriptors(sctx);
1809 }
1810
1811 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1812 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1813 sctx->last_dirty_buf_counter = dirty_buf_counter;
1814 /* Rebind all buffers unconditionally. */
1815 si_rebind_buffer(sctx, NULL);
1816 }
1817
1818 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1819
1820 /* Set the rasterization primitive type.
1821 *
1822 * This must be done after si_decompress_textures, which can call
1823 * draw_vbo recursively, and before si_update_shaders, which uses
1824 * current_rast_prim for this draw_vbo call. */
1825 if (sctx->gs_shader.cso) {
1826 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1827 rast_prim = sctx->gs_shader.cso->rast_prim;
1828 } else if (sctx->tes_shader.cso) {
1829 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1830 rast_prim = sctx->tes_shader.cso->rast_prim;
1831 } else if (util_rast_prim_is_triangles(prim)) {
1832 rast_prim = PIPE_PRIM_TRIANGLES;
1833 } else {
1834 /* Only possibilities, POINTS, LINE*, RECTANGLES */
1835 rast_prim = prim;
1836 }
1837
1838 if (rast_prim != sctx->current_rast_prim) {
1839 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1840 util_prim_is_points_or_lines(rast_prim))
1841 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1842
1843 sctx->current_rast_prim = rast_prim;
1844 sctx->do_update_shaders = true;
1845 }
1846
1847 if (sctx->tes_shader.cso &&
1848 sctx->screen->info.has_ls_vgpr_init_bug) {
1849 /* Determine whether the LS VGPR fix should be applied.
1850 *
1851 * It is only required when num input CPs > num output CPs,
1852 * which cannot happen with the fixed function TCS. We should
1853 * also update this bit when switching from TCS to fixed
1854 * function TCS.
1855 */
1856 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1857 bool ls_vgpr_fix =
1858 tcs &&
1859 info->vertices_per_patch >
1860 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1861
1862 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1863 sctx->ls_vgpr_fix = ls_vgpr_fix;
1864 sctx->do_update_shaders = true;
1865 }
1866 }
1867
1868 if (sctx->chip_class <= GFX9 && sctx->gs_shader.cso) {
1869 /* Determine whether the GS triangle strip adjacency fix should
1870 * be applied. Rotate every other triangle if
1871 * - triangle strips with adjacency are fed to the GS and
1872 * - primitive restart is disabled (the rotation doesn't help
1873 * when the restart occurs after an odd number of triangles).
1874 */
1875 bool gs_tri_strip_adj_fix =
1876 !sctx->tes_shader.cso &&
1877 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1878 !primitive_restart;
1879
1880 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1881 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1882 sctx->do_update_shaders = true;
1883 }
1884 }
1885
1886 if (index_size) {
1887 /* Translate or upload, if needed. */
1888 /* 8-bit indices are supported on GFX8. */
1889 if (sctx->chip_class <= GFX7 && index_size == 1) {
1890 unsigned start, count, start_offset, size, offset;
1891 void *ptr;
1892
1893 si_get_draw_start_count(sctx, info, &start, &count);
1894 start_offset = start * 2;
1895 size = count * 2;
1896
1897 indexbuf = NULL;
1898 u_upload_alloc(ctx->stream_uploader, start_offset,
1899 size,
1900 si_optimal_tcc_alignment(sctx, size),
1901 &offset, &indexbuf, &ptr);
1902 if (!indexbuf)
1903 return;
1904
1905 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1906 index_offset + start,
1907 count, ptr);
1908
1909 /* info->start will be added by the drawing code */
1910 index_offset = offset - start_offset;
1911 index_size = 2;
1912 } else if (info->has_user_indices) {
1913 unsigned start_offset;
1914
1915 assert(!info->indirect);
1916 start_offset = info->start * index_size;
1917
1918 indexbuf = NULL;
1919 u_upload_data(ctx->stream_uploader, start_offset,
1920 info->count * index_size,
1921 sctx->screen->info.tcc_cache_line_size,
1922 (char*)info->index.user + start_offset,
1923 &index_offset, &indexbuf);
1924 if (!indexbuf)
1925 return;
1926
1927 /* info->start will be added by the drawing code */
1928 index_offset -= start_offset;
1929 } else if (sctx->chip_class <= GFX7 &&
1930 si_resource(indexbuf)->TC_L2_dirty) {
1931 /* GFX8 reads index buffers through TC L2, so it doesn't
1932 * need this. */
1933 sctx->flags |= SI_CONTEXT_WB_L2;
1934 si_resource(indexbuf)->TC_L2_dirty = false;
1935 }
1936 }
1937
1938 bool dispatch_prim_discard_cs = false;
1939 bool prim_discard_cs_instancing = false;
1940 unsigned original_index_size = index_size;
1941 unsigned direct_count = 0;
1942
1943 if (info->indirect) {
1944 struct pipe_draw_indirect_info *indirect = info->indirect;
1945
1946 /* Add the buffer size for memory checking in need_cs_space. */
1947 si_context_add_resource_size(sctx, indirect->buffer);
1948
1949 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1950 if (sctx->chip_class <= GFX8) {
1951 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1952 sctx->flags |= SI_CONTEXT_WB_L2;
1953 si_resource(indirect->buffer)->TC_L2_dirty = false;
1954 }
1955
1956 if (indirect->indirect_draw_count &&
1957 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1958 sctx->flags |= SI_CONTEXT_WB_L2;
1959 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1960 }
1961 }
1962 } else {
1963 /* Multiply by 3 for strips and fans to get an approximate vertex
1964 * count as triangles. */
1965 direct_count = info->count * instance_count *
1966 (prim == PIPE_PRIM_TRIANGLES ? 1 : 3);
1967 }
1968
1969 /* Determine if we can use the primitive discard compute shader. */
1970 if (si_compute_prim_discard_enabled(sctx) &&
1971 (direct_count > sctx->prim_discard_vertex_count_threshold ?
1972 (sctx->compute_num_verts_rejected += direct_count, true) : /* Add, then return true. */
1973 (sctx->compute_num_verts_ineligible += direct_count, false)) && /* Add, then return false. */
1974 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1975 (primitive_restart ?
1976 /* Supported prim types with primitive restart: */
1977 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1978 /* Disallow instancing with primitive restart: */
1979 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart")) :
1980 /* Supported prim types without primitive restart + allow instancing: */
1981 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1982 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1983 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1984 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1985 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1986 (instance_count == 1 ||
1987 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1988 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1989 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1990 (!sctx->render_cond || pd_msg("render condition")) &&
1991 /* Forced enablement ignores pipeline statistics queries. */
1992 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
1993 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
1994 pd_msg("pipestat or primgen query")) &&
1995 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
1996 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
1997 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
1998 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
1999 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
2000 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
2001 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
2002 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
2003 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
2004 !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2005 !sctx->vs_shader.cso->so.num_outputs &&
2006 #else
2007 (sctx->vs_shader.cso->prim_discard_cs_allowed || pd_msg("VS shader uses unsupported features")) &&
2008 #endif
2009 /* Check that all buffers are used for read only, because compute
2010 * dispatches can run ahead. */
2011 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) || pd_msg("write reference"))) {
2012 switch (si_prepare_prim_discard_or_split_draw(sctx, info, primitive_restart)) {
2013 case SI_PRIM_DISCARD_ENABLED:
2014 original_index_size = index_size;
2015 prim_discard_cs_instancing = instance_count > 1;
2016 dispatch_prim_discard_cs = true;
2017
2018 /* The compute shader changes/lowers the following: */
2019 prim = PIPE_PRIM_TRIANGLES;
2020 index_size = 4;
2021 instance_count = 1;
2022 primitive_restart = false;
2023 sctx->compute_num_verts_rejected -= direct_count;
2024 sctx->compute_num_verts_accepted += direct_count;
2025 break;
2026 case SI_PRIM_DISCARD_DISABLED:
2027 break;
2028 case SI_PRIM_DISCARD_DRAW_SPLIT:
2029 sctx->compute_num_verts_rejected -= direct_count;
2030 goto return_cleanup;
2031 }
2032 }
2033
2034 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
2035 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
2036 sctx->do_update_shaders = true;
2037 }
2038
2039 if (sctx->do_update_shaders && !si_update_shaders(sctx))
2040 goto return_cleanup;
2041
2042 si_need_gfx_cs_space(sctx);
2043
2044 if (sctx->bo_list_add_all_gfx_resources)
2045 si_gfx_resources_add_all_to_bo_list(sctx);
2046
2047 /* Since we've called si_context_add_resource_size for vertex buffers,
2048 * this must be called after si_need_cs_space, because we must let
2049 * need_cs_space flush before we add buffers to the buffer list.
2050 */
2051 if (!si_upload_vertex_buffer_descriptors(sctx))
2052 goto return_cleanup;
2053
2054 /* Vega10/Raven scissor bug workaround. When any context register is
2055 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
2056 * registers must be written too.
2057 */
2058 unsigned masked_atoms = 0;
2059
2060 if (sctx->screen->info.has_gfx9_scissor_bug) {
2061 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2062
2063 if (info->count_from_stream_output ||
2064 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
2065 sctx->dirty_states & si_states_that_always_roll_context())
2066 sctx->context_roll = true;
2067 }
2068
2069 /* Use optimal packet order based on whether we need to sync the pipeline. */
2070 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
2071 SI_CONTEXT_FLUSH_AND_INV_DB |
2072 SI_CONTEXT_PS_PARTIAL_FLUSH |
2073 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
2074 /* If we have to wait for idle, set all states first, so that all
2075 * SET packets are processed in parallel with previous draw calls.
2076 * Then draw and prefetch at the end. This ensures that the time
2077 * the CUs are idle is very short.
2078 */
2079 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
2080 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
2081
2082 if (!si_upload_graphics_shader_descriptors(sctx))
2083 goto return_cleanup;
2084
2085 /* Emit all states except possibly render condition. */
2086 si_emit_all_states(sctx, info, prim, instance_count,
2087 primitive_restart, masked_atoms);
2088 sctx->emit_cache_flush(sctx);
2089 /* <-- CUs are idle here. */
2090
2091 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
2092 sctx->atoms.s.render_cond.emit(sctx);
2093
2094 if (sctx->screen->info.has_gfx9_scissor_bug &&
2095 (sctx->context_roll ||
2096 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2097 sctx->atoms.s.scissors.emit(sctx);
2098
2099 sctx->dirty_atoms = 0;
2100
2101 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2102 instance_count, dispatch_prim_discard_cs,
2103 original_index_size);
2104 /* <-- CUs are busy here. */
2105
2106 /* Start prefetches after the draw has been started. Both will run
2107 * in parallel, but starting the draw first is more important.
2108 */
2109 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2110 cik_emit_prefetch_L2(sctx, false);
2111 } else {
2112 /* If we don't wait for idle, start prefetches first, then set
2113 * states, and draw at the end.
2114 */
2115 if (sctx->flags)
2116 sctx->emit_cache_flush(sctx);
2117
2118 /* Only prefetch the API VS and VBO descriptors. */
2119 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2120 cik_emit_prefetch_L2(sctx, true);
2121
2122 if (!si_upload_graphics_shader_descriptors(sctx))
2123 goto return_cleanup;
2124
2125 si_emit_all_states(sctx, info, prim, instance_count,
2126 primitive_restart, masked_atoms);
2127
2128 if (sctx->screen->info.has_gfx9_scissor_bug &&
2129 (sctx->context_roll ||
2130 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2131 sctx->atoms.s.scissors.emit(sctx);
2132
2133 sctx->dirty_atoms = 0;
2134
2135 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2136 instance_count, dispatch_prim_discard_cs,
2137 original_index_size);
2138
2139 /* Prefetch the remaining shaders after the draw has been
2140 * started. */
2141 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2142 cik_emit_prefetch_L2(sctx, false);
2143 }
2144
2145 /* Clear the context roll flag after the draw call. */
2146 sctx->context_roll = false;
2147
2148 if (unlikely(sctx->current_saved_cs)) {
2149 si_trace_emit(sctx);
2150 si_log_draw_state(sctx, sctx->log);
2151 }
2152
2153 /* Workaround for a VGT hang when streamout is enabled.
2154 * It must be done after drawing. */
2155 if ((sctx->family == CHIP_HAWAII ||
2156 sctx->family == CHIP_TONGA ||
2157 sctx->family == CHIP_FIJI) &&
2158 si_get_strmout_en(sctx)) {
2159 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2160 }
2161
2162 if (unlikely(sctx->decompression_enabled)) {
2163 sctx->num_decompress_calls++;
2164 } else {
2165 sctx->num_draw_calls++;
2166 if (sctx->framebuffer.state.nr_cbufs > 1)
2167 sctx->num_mrt_draw_calls++;
2168 if (primitive_restart)
2169 sctx->num_prim_restart_calls++;
2170 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
2171 sctx->num_spill_draw_calls++;
2172 }
2173
2174 return_cleanup:
2175 if (index_size && indexbuf != info->index.resource)
2176 pipe_resource_reference(&indexbuf, NULL);
2177 }
2178
2179 static void
2180 si_draw_rectangle(struct blitter_context *blitter,
2181 void *vertex_elements_cso,
2182 blitter_get_vs_func get_vs,
2183 int x1, int y1, int x2, int y2,
2184 float depth, unsigned num_instances,
2185 enum blitter_attrib_type type,
2186 const union blitter_attrib *attrib)
2187 {
2188 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2189 struct si_context *sctx = (struct si_context*)pipe;
2190
2191 /* Pack position coordinates as signed int16. */
2192 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
2193 ((uint32_t)(y1 & 0xffff) << 16);
2194 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
2195 ((uint32_t)(y2 & 0xffff) << 16);
2196 sctx->vs_blit_sh_data[2] = fui(depth);
2197
2198 switch (type) {
2199 case UTIL_BLITTER_ATTRIB_COLOR:
2200 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
2201 sizeof(float)*4);
2202 break;
2203 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2204 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2205 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
2206 sizeof(attrib->texcoord));
2207 break;
2208 case UTIL_BLITTER_ATTRIB_NONE:;
2209 }
2210
2211 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2212
2213 struct pipe_draw_info info = {};
2214 info.mode = SI_PRIM_RECTANGLE_LIST;
2215 info.count = 3;
2216 info.instance_count = num_instances;
2217
2218 /* Don't set per-stage shader pointers for VS. */
2219 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
2220 sctx->vertex_buffer_pointer_dirty = false;
2221
2222 si_draw_vbo(pipe, &info);
2223 }
2224
2225 void si_trace_emit(struct si_context *sctx)
2226 {
2227 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2228 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
2229
2230 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
2231 0, 4, V_370_MEM, V_370_ME, &trace_id);
2232
2233 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2234 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
2235
2236 if (sctx->log)
2237 u_log_flush(sctx->log);
2238 }
2239
2240 void si_init_draw_functions(struct si_context *sctx)
2241 {
2242 sctx->b.draw_vbo = si_draw_vbo;
2243
2244 sctx->blitter->draw_rectangle = si_draw_rectangle;
2245
2246 si_init_ia_multi_vgt_param_table(sctx);
2247 }