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[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "radeon/r600_cs.h"
29 #include "sid.h"
30
31 #include "util/u_index_modify.h"
32 #include "util/u_upload_mgr.h"
33 #include "util/u_prim.h"
34
35 static unsigned si_conv_pipe_prim(unsigned mode)
36 {
37 static const unsigned prim_conv[] = {
38 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
39 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
40 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
41 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
42 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
43 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
44 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
45 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
46 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
47 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
48 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
49 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
50 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
51 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
52 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
53 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
54 };
55 assert(mode < ARRAY_SIZE(prim_conv));
56 return prim_conv[mode];
57 }
58
59 static unsigned si_conv_prim_to_gs_out(unsigned mode)
60 {
61 static const int prim_conv[] = {
62 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
63 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
64 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
65 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
67 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
68 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
73 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
74 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
75 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
76 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
77 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
78 };
79 assert(mode < ARRAY_SIZE(prim_conv));
80
81 return prim_conv[mode];
82 }
83
84 /**
85 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
86 * LS.LDS_SIZE is shared by all 3 shader stages.
87 *
88 * The information about LDS and other non-compile-time parameters is then
89 * written to userdata SGPRs.
90 */
91 static void si_emit_derived_tess_state(struct si_context *sctx,
92 const struct pipe_draw_info *info,
93 unsigned *num_patches)
94 {
95 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
96 struct si_shader_ctx_state *ls = &sctx->vs_shader;
97 /* The TES pointer will only be used for sctx->last_tcs.
98 * It would be wrong to think that TCS = TES. */
99 struct si_shader_selector *tcs =
100 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
101 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
102 unsigned num_tcs_input_cp = info->vertices_per_patch;
103 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
104 unsigned num_tcs_patch_outputs;
105 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
106 unsigned input_patch_size, output_patch_size, output_patch0_offset;
107 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
108 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
109 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
110
111 if (sctx->last_ls == ls->current &&
112 sctx->last_tcs == tcs &&
113 sctx->last_tes_sh_base == tes_sh_base &&
114 sctx->last_num_tcs_input_cp == num_tcs_input_cp) {
115 *num_patches = sctx->last_num_patches;
116 return;
117 }
118
119 sctx->last_ls = ls->current;
120 sctx->last_tcs = tcs;
121 sctx->last_tes_sh_base = tes_sh_base;
122 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
123
124 /* This calculates how shader inputs and outputs among VS, TCS, and TES
125 * are laid out in LDS. */
126 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
127
128 if (sctx->tcs_shader.cso) {
129 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
130 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
131 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
132 } else {
133 /* No TCS. Route varyings from LS to TES. */
134 num_tcs_outputs = num_tcs_inputs;
135 num_tcs_output_cp = num_tcs_input_cp;
136 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
137 }
138
139 input_vertex_size = num_tcs_inputs * 16;
140 output_vertex_size = num_tcs_outputs * 16;
141
142 input_patch_size = num_tcs_input_cp * input_vertex_size;
143
144 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
145 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
146
147 /* Ensure that we only need one wave per SIMD so we don't need to check
148 * resource usage. Also ensures that the number of tcs in and out
149 * vertices per threadgroup are at most 256.
150 */
151 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 */
156 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
157 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
158 output_patch_size));
159
160 /* Make sure the output data fits in the offchip buffer */
161 *num_patches = MIN2(*num_patches,
162 (sctx->screen->tess_offchip_block_dw_size * 4) /
163 output_patch_size);
164
165 /* Not necessary for correctness, but improves performance. The
166 * specific value is taken from the proprietary driver.
167 */
168 *num_patches = MIN2(*num_patches, 40);
169
170 /* SI bug workaround - limit LS-HS threadgroups to only one wave. */
171 if (sctx->b.chip_class == SI) {
172 unsigned one_wave = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp);
173 *num_patches = MIN2(*num_patches, one_wave);
174 }
175
176 sctx->last_num_patches = *num_patches;
177
178 output_patch0_offset = input_patch_size * *num_patches;
179 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
180
181 lds_size = output_patch0_offset + output_patch_size * *num_patches;
182 ls_rsrc2 = ls->current->config.rsrc2;
183
184 if (sctx->b.chip_class >= CIK) {
185 assert(lds_size <= 65536);
186 lds_size = align(lds_size, 512) / 512;
187 } else {
188 assert(lds_size <= 32768);
189 lds_size = align(lds_size, 256) / 256;
190 }
191 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
192 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
193
194 /* Due to a hw bug, RSRC2_LS must be written twice with another
195 * LS register written in between. */
196 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
197 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
198 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
199 radeon_emit(cs, ls->current->config.rsrc1);
200 radeon_emit(cs, ls_rsrc2);
201
202 /* Compute userdata SGPRs. */
203 assert(((input_vertex_size / 4) & ~0xff) == 0);
204 assert(((output_vertex_size / 4) & ~0xff) == 0);
205 assert(((input_patch_size / 4) & ~0x1fff) == 0);
206 assert(((output_patch_size / 4) & ~0x1fff) == 0);
207 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
208 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
209 assert(num_tcs_input_cp <= 32);
210 assert(num_tcs_output_cp <= 32);
211
212 tcs_in_layout = (input_patch_size / 4) |
213 ((input_vertex_size / 4) << 13);
214 tcs_out_layout = (output_patch_size / 4) |
215 ((output_vertex_size / 4) << 13);
216 tcs_out_offsets = (output_patch0_offset / 16) |
217 ((perpatch_output_offset / 16) << 16);
218 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
219 (num_tcs_output_cp << 9) | *num_patches;
220
221 /* Set them for LS. */
222 radeon_set_sh_reg(cs,
223 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
224 tcs_in_layout);
225
226 /* Set them for TCS. */
227 radeon_set_sh_reg_seq(cs,
228 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
229 radeon_emit(cs, offchip_layout);
230 radeon_emit(cs, tcs_out_offsets);
231 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
232 radeon_emit(cs, tcs_in_layout);
233
234 /* Set them for TES. */
235 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
236 radeon_emit(cs, offchip_layout);
237
238 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
239 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
240 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
241
242 if (sctx->b.chip_class >= CIK)
243 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
244 ls_hs_config);
245 else
246 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
247 ls_hs_config);
248 }
249
250 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
251 {
252 switch (info->mode) {
253 case PIPE_PRIM_PATCHES:
254 return info->count / info->vertices_per_patch;
255 case R600_PRIM_RECTANGLE_LIST:
256 return info->count / 3;
257 default:
258 return u_prims_for_vertices(info->mode, info->count);
259 }
260 }
261
262 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
263 const struct pipe_draw_info *info,
264 unsigned num_patches)
265 {
266 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
267 unsigned prim = info->mode;
268 unsigned primgroup_size = 128; /* recommended without a GS */
269 unsigned max_primgroup_in_wave = 2;
270
271 /* SWITCH_ON_EOP(0) is always preferable. */
272 bool wd_switch_on_eop = false;
273 bool ia_switch_on_eop = false;
274 bool ia_switch_on_eoi = false;
275 bool partial_vs_wave = false;
276 bool partial_es_wave = false;
277
278 if (sctx->gs_shader.cso)
279 primgroup_size = 64; /* recommended with a GS */
280
281 if (sctx->tes_shader.cso) {
282 /* primgroup_size must be set to a multiple of NUM_PATCHES */
283 primgroup_size = num_patches;
284
285 /* SWITCH_ON_EOI must be set if PrimID is used. */
286 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
287 sctx->tes_shader.cso->info.uses_primid)
288 ia_switch_on_eoi = true;
289
290 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
291 if ((sctx->b.family == CHIP_TAHITI ||
292 sctx->b.family == CHIP_PITCAIRN ||
293 sctx->b.family == CHIP_BONAIRE) &&
294 sctx->gs_shader.cso)
295 partial_vs_wave = true;
296
297 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
298 if (sctx->screen->has_distributed_tess) {
299 if (sctx->gs_shader.cso) {
300 partial_es_wave = true;
301
302 /* GPU hang workaround. */
303 if (sctx->b.family == CHIP_TONGA ||
304 sctx->b.family == CHIP_FIJI ||
305 sctx->b.family == CHIP_POLARIS10 ||
306 sctx->b.family == CHIP_POLARIS11)
307 partial_vs_wave = true;
308 } else {
309 partial_vs_wave = true;
310 }
311 }
312 }
313
314 /* This is a hardware requirement. */
315 if ((rs && rs->line_stipple_enable) ||
316 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
317 ia_switch_on_eop = true;
318 wd_switch_on_eop = true;
319 }
320
321 if (sctx->b.chip_class >= CIK) {
322 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
323 * 4 shader engines. Set 1 to pass the assertion below.
324 * The other cases are hardware requirements.
325 *
326 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
327 * for points, line strips, and tri strips.
328 */
329 if (sctx->b.screen->info.max_se < 4 ||
330 prim == PIPE_PRIM_POLYGON ||
331 prim == PIPE_PRIM_LINE_LOOP ||
332 prim == PIPE_PRIM_TRIANGLE_FAN ||
333 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
334 (info->primitive_restart &&
335 (sctx->b.family < CHIP_POLARIS10 ||
336 (prim != PIPE_PRIM_POINTS &&
337 prim != PIPE_PRIM_LINE_STRIP &&
338 prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
339 info->count_from_stream_output)
340 wd_switch_on_eop = true;
341
342 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
343 * We don't know that for indirect drawing, so treat it as
344 * always problematic. */
345 if (sctx->b.family == CHIP_HAWAII &&
346 (info->indirect || info->instance_count > 1))
347 wd_switch_on_eop = true;
348
349 /* Performance recommendation for 4 SE Gfx7-8 parts if
350 * instances are smaller than a primgroup.
351 * Assume indirect draws always use small instances.
352 * This is needed for good VS wave utilization.
353 */
354 if (sctx->b.chip_class <= VI &&
355 sctx->b.screen->info.max_se >= 4 &&
356 (info->indirect ||
357 (info->instance_count > 1 &&
358 si_num_prims_for_vertices(info) < primgroup_size)))
359 wd_switch_on_eop = true;
360
361 /* Required on CIK and later. */
362 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
363 ia_switch_on_eoi = true;
364
365 /* Required by Hawaii and, for some special cases, by VI. */
366 if (ia_switch_on_eoi &&
367 (sctx->b.family == CHIP_HAWAII ||
368 (sctx->b.chip_class == VI &&
369 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
370 partial_vs_wave = true;
371
372 /* Instancing bug on Bonaire. */
373 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
374 (info->indirect || info->instance_count > 1))
375 partial_vs_wave = true;
376
377 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
378 * The hw doc says all multi-SE chips are affected, but Vulkan
379 * only applies it to Hawaii. Do what Vulkan does.
380 */
381 if (sctx->b.family == CHIP_HAWAII &&
382 sctx->gs_shader.cso &&
383 ia_switch_on_eoi &&
384 (info->indirect ||
385 (info->instance_count > 1 &&
386 si_num_prims_for_vertices(info) <= 1)))
387 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
388
389
390 /* If the WD switch is false, the IA switch must be false too. */
391 assert(wd_switch_on_eop || !ia_switch_on_eop);
392 }
393
394 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
395 if (ia_switch_on_eoi)
396 partial_es_wave = true;
397
398 /* GS requirement. */
399 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
400 partial_es_wave = true;
401
402 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
403 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
404 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
405 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
406 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
407 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
408 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
409 max_primgroup_in_wave : 0);
410 }
411
412 static void si_emit_scratch_reloc(struct si_context *sctx)
413 {
414 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
415
416 if (!sctx->emit_scratch_reloc)
417 return;
418
419 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
420 sctx->spi_tmpring_size);
421
422 if (sctx->scratch_buffer) {
423 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
424 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
425 RADEON_PRIO_SCRATCH_BUFFER);
426
427 }
428 sctx->emit_scratch_reloc = false;
429 }
430
431 /* rast_prim is the primitive type after GS. */
432 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
433 {
434 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
435 unsigned rast_prim = sctx->current_rast_prim;
436 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
437
438 /* Skip this if not rendering lines. */
439 if (rast_prim != PIPE_PRIM_LINES &&
440 rast_prim != PIPE_PRIM_LINE_LOOP &&
441 rast_prim != PIPE_PRIM_LINE_STRIP &&
442 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
443 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
444 return;
445
446 if (rast_prim == sctx->last_rast_prim &&
447 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
448 return;
449
450 /* For lines, reset the stipple pattern at each primitive. Otherwise,
451 * reset the stipple pattern at each packet (line strips, line loops).
452 */
453 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
454 rs->pa_sc_line_stipple |
455 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
456
457 sctx->last_rast_prim = rast_prim;
458 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
459 }
460
461 static void si_emit_draw_registers(struct si_context *sctx,
462 const struct pipe_draw_info *info)
463 {
464 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
465 unsigned prim = si_conv_pipe_prim(info->mode);
466 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
467 unsigned ia_multi_vgt_param, num_patches = 0;
468
469 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
470 * whether the "fractional odd" tessellation spacing is used.
471 */
472 if (sctx->b.family >= CHIP_POLARIS10) {
473 struct si_shader_selector *tes = sctx->tes_shader.cso;
474 unsigned vtx_reuse_depth = 30;
475
476 if (tes &&
477 tes->info.properties[TGSI_PROPERTY_TES_SPACING] ==
478 PIPE_TESS_SPACING_FRACTIONAL_ODD)
479 vtx_reuse_depth = 14;
480
481 if (vtx_reuse_depth != sctx->last_vtx_reuse_depth) {
482 radeon_set_context_reg(cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
483 vtx_reuse_depth);
484 sctx->last_vtx_reuse_depth = vtx_reuse_depth;
485 }
486 }
487
488 if (sctx->tes_shader.cso)
489 si_emit_derived_tess_state(sctx, info, &num_patches);
490
491 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
492
493 /* Draw state. */
494 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
495 if (sctx->b.chip_class >= CIK)
496 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
497 else
498 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
499
500 sctx->last_multi_vgt_param = ia_multi_vgt_param;
501 }
502 if (prim != sctx->last_prim) {
503 if (sctx->b.chip_class >= CIK)
504 radeon_set_uconfig_reg_idx(cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
505 else
506 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
507
508 sctx->last_prim = prim;
509 }
510
511 if (gs_out_prim != sctx->last_gs_out_prim) {
512 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
513 sctx->last_gs_out_prim = gs_out_prim;
514 }
515
516 /* Primitive restart. */
517 if (info->primitive_restart != sctx->last_primitive_restart_en) {
518 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
519 sctx->last_primitive_restart_en = info->primitive_restart;
520
521 }
522 if (info->primitive_restart &&
523 (info->restart_index != sctx->last_restart_index ||
524 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
525 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
526 info->restart_index);
527 sctx->last_restart_index = info->restart_index;
528 }
529 }
530
531 static void si_emit_draw_packets(struct si_context *sctx,
532 const struct pipe_draw_info *info,
533 const struct pipe_index_buffer *ib)
534 {
535 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
536 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
537 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
538 uint32_t index_max_size = 0;
539 uint64_t index_va = 0;
540
541 if (info->count_from_stream_output) {
542 struct r600_so_target *t =
543 (struct r600_so_target*)info->count_from_stream_output;
544 uint64_t va = t->buf_filled_size->gpu_address +
545 t->buf_filled_size_offset;
546
547 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
548 t->stride_in_dw);
549
550 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
551 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
552 COPY_DATA_DST_SEL(COPY_DATA_REG) |
553 COPY_DATA_WR_CONFIRM);
554 radeon_emit(cs, va); /* src address lo */
555 radeon_emit(cs, va >> 32); /* src address hi */
556 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
557 radeon_emit(cs, 0); /* unused */
558
559 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
560 t->buf_filled_size, RADEON_USAGE_READ,
561 RADEON_PRIO_SO_FILLED_SIZE);
562 }
563
564 /* draw packet */
565 if (info->indexed) {
566 if (ib->index_size != sctx->last_index_size) {
567 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
568
569 /* index type */
570 switch (ib->index_size) {
571 case 1:
572 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
573 break;
574 case 2:
575 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
576 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
577 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
578 break;
579 case 4:
580 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
581 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
582 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
583 break;
584 default:
585 assert(!"unreachable");
586 return;
587 }
588
589 sctx->last_index_size = ib->index_size;
590 }
591
592 index_max_size = (ib->buffer->width0 - ib->offset) /
593 ib->index_size;
594 index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
595
596 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
597 (struct r600_resource *)ib->buffer,
598 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
599 } else {
600 /* On CI and later, non-indexed draws overwrite VGT_INDEX_TYPE,
601 * so the state must be re-emitted before the next indexed draw.
602 */
603 if (sctx->b.chip_class >= CIK)
604 sctx->last_index_size = -1;
605 }
606
607 if (!info->indirect) {
608 int base_vertex;
609
610 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
611 radeon_emit(cs, info->instance_count);
612
613 /* Base vertex and start instance. */
614 base_vertex = info->indexed ? info->index_bias : info->start;
615
616 if (base_vertex != sctx->last_base_vertex ||
617 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
618 info->start_instance != sctx->last_start_instance ||
619 info->drawid != sctx->last_drawid ||
620 sh_base_reg != sctx->last_sh_base_reg) {
621 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
622 radeon_emit(cs, base_vertex);
623 radeon_emit(cs, info->start_instance);
624 radeon_emit(cs, info->drawid);
625
626 sctx->last_base_vertex = base_vertex;
627 sctx->last_start_instance = info->start_instance;
628 sctx->last_drawid = info->drawid;
629 sctx->last_sh_base_reg = sh_base_reg;
630 }
631 } else {
632 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
633
634 assert(indirect_va % 8 == 0);
635
636 si_invalidate_draw_sh_constants(sctx);
637
638 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
639 radeon_emit(cs, 1);
640 radeon_emit(cs, indirect_va);
641 radeon_emit(cs, indirect_va >> 32);
642
643 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
644 (struct r600_resource *)info->indirect,
645 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
646 }
647
648 if (info->indirect) {
649 unsigned di_src_sel = info->indexed ? V_0287F0_DI_SRC_SEL_DMA
650 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
651
652 assert(info->indirect_offset % 4 == 0);
653
654 if (info->indexed) {
655 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
656 radeon_emit(cs, index_va);
657 radeon_emit(cs, index_va >> 32);
658
659 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
660 radeon_emit(cs, index_max_size);
661 }
662
663 if (!sctx->screen->has_draw_indirect_multi) {
664 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT
665 : PKT3_DRAW_INDIRECT,
666 3, render_cond_bit));
667 radeon_emit(cs, info->indirect_offset);
668 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
669 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
670 radeon_emit(cs, di_src_sel);
671 } else {
672 uint64_t count_va = 0;
673
674 if (info->indirect_params) {
675 struct r600_resource *params_buf =
676 (struct r600_resource *)info->indirect_params;
677
678 radeon_add_to_buffer_list(
679 &sctx->b, &sctx->b.gfx, params_buf,
680 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
681
682 count_va = params_buf->gpu_address + info->indirect_params_offset;
683 }
684
685 radeon_emit(cs, PKT3(info->indexed ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
686 PKT3_DRAW_INDIRECT_MULTI,
687 8, render_cond_bit));
688 radeon_emit(cs, info->indirect_offset);
689 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
690 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
691 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
692 S_2C3_DRAW_INDEX_ENABLE(1) |
693 S_2C3_COUNT_INDIRECT_ENABLE(!!info->indirect_params));
694 radeon_emit(cs, info->indirect_count);
695 radeon_emit(cs, count_va);
696 radeon_emit(cs, count_va >> 32);
697 radeon_emit(cs, info->indirect_stride);
698 radeon_emit(cs, di_src_sel);
699 }
700 } else {
701 if (info->indexed) {
702 index_va += info->start * ib->index_size;
703
704 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
705 radeon_emit(cs, index_max_size);
706 radeon_emit(cs, index_va);
707 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
708 radeon_emit(cs, info->count);
709 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
710 } else {
711 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
712 radeon_emit(cs, info->count);
713 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
714 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
715 }
716 }
717 }
718
719 static void si_emit_surface_sync(struct r600_common_context *rctx,
720 unsigned cp_coher_cntl)
721 {
722 struct radeon_winsys_cs *cs = rctx->gfx.cs;
723
724 /* ACQUIRE_MEM is only required on a compute ring. */
725 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
726 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
727 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
728 radeon_emit(cs, 0); /* CP_COHER_BASE */
729 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
730 }
731
732 void si_emit_cache_flush(struct si_context *sctx)
733 {
734 struct r600_common_context *rctx = &sctx->b;
735 struct radeon_winsys_cs *cs = rctx->gfx.cs;
736 uint32_t cp_coher_cntl = 0;
737
738 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_FRAMEBUFFER)
739 sctx->b.num_fb_cache_flushes++;
740
741 /* SI has a bug that it always flushes ICACHE and KCACHE if either
742 * bit is set. An alternative way is to write SQC_CACHES, but that
743 * doesn't seem to work reliably. Since the bug doesn't affect
744 * correctness (it only does more work than necessary) and
745 * the performance impact is likely negligible, there is no plan
746 * to add a workaround for it.
747 */
748
749 if (rctx->flags & SI_CONTEXT_INV_ICACHE)
750 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
751 if (rctx->flags & SI_CONTEXT_INV_SMEM_L1)
752 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
753
754 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
755 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
756 S_0085F0_CB0_DEST_BASE_ENA(1) |
757 S_0085F0_CB1_DEST_BASE_ENA(1) |
758 S_0085F0_CB2_DEST_BASE_ENA(1) |
759 S_0085F0_CB3_DEST_BASE_ENA(1) |
760 S_0085F0_CB4_DEST_BASE_ENA(1) |
761 S_0085F0_CB5_DEST_BASE_ENA(1) |
762 S_0085F0_CB6_DEST_BASE_ENA(1) |
763 S_0085F0_CB7_DEST_BASE_ENA(1);
764
765 /* Necessary for DCC */
766 if (rctx->chip_class == VI)
767 r600_gfx_write_event_eop(rctx, V_028A90_FLUSH_AND_INV_CB_DATA_TS,
768 0, 0, NULL, 0, 0, 0);
769 }
770 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
771 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
772 S_0085F0_DB_DEST_BASE_ENA(1);
773 }
774
775 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
776 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
777 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
778 /* needed for wait for idle in SURFACE_SYNC */
779 assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
780 }
781 if (rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
782 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
783 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
784 /* needed for wait for idle in SURFACE_SYNC */
785 assert(rctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
786 }
787
788 /* Wait for shader engines to go idle.
789 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
790 * for everything including CB/DB cache flushes.
791 */
792 if (!(rctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
793 SI_CONTEXT_FLUSH_AND_INV_DB))) {
794 if (rctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
795 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
796 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
797 /* Only count explicit shader flushes, not implicit ones
798 * done by SURFACE_SYNC.
799 */
800 rctx->num_vs_flushes++;
801 rctx->num_ps_flushes++;
802 } else if (rctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
803 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
804 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
805 rctx->num_vs_flushes++;
806 }
807 }
808
809 if (rctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
810 sctx->compute_is_busy) {
811 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
812 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
813 rctx->num_cs_flushes++;
814 sctx->compute_is_busy = false;
815 }
816
817 /* VGT state synchronization. */
818 if (rctx->flags & SI_CONTEXT_VGT_FLUSH) {
819 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
820 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
821 }
822 if (rctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
823 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
824 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
825 }
826
827 /* Make sure ME is idle (it executes most packets) before continuing.
828 * This prevents read-after-write hazards between PFP and ME.
829 */
830 if (cp_coher_cntl ||
831 (rctx->flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
832 SI_CONTEXT_INV_VMEM_L1 |
833 SI_CONTEXT_INV_GLOBAL_L2 |
834 SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
835 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
836 radeon_emit(cs, 0);
837 }
838
839 /* When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
840 * waits for idle. Therefore, it should be last. SURFACE_SYNC is done
841 * in PFP.
842 *
843 * cp_coher_cntl should contain all necessary flags except TC flags
844 * at this point.
845 *
846 * SI-CIK don't support L2 write-back.
847 */
848 if (rctx->flags & SI_CONTEXT_INV_GLOBAL_L2 ||
849 (rctx->chip_class <= CIK &&
850 (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
851 /* Invalidate L1 & L2. (L1 is always invalidated)
852 * WB must be set on VI+ when TC_ACTION is set.
853 */
854 si_emit_surface_sync(rctx, cp_coher_cntl |
855 S_0085F0_TC_ACTION_ENA(1) |
856 S_0301F0_TC_WB_ACTION_ENA(rctx->chip_class >= VI));
857 cp_coher_cntl = 0;
858 sctx->b.num_L2_invalidates++;
859 } else {
860 /* L1 invalidation and L2 writeback must be done separately,
861 * because both operations can't be done together.
862 */
863 if (rctx->flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
864 /* WB = write-back
865 * NC = apply to non-coherent MTYPEs
866 * (i.e. MTYPE <= 1, which is what we use everywhere)
867 *
868 * WB doesn't work without NC.
869 */
870 si_emit_surface_sync(rctx, cp_coher_cntl |
871 S_0301F0_TC_WB_ACTION_ENA(1) |
872 S_0301F0_TC_NC_ACTION_ENA(1));
873 cp_coher_cntl = 0;
874 sctx->b.num_L2_writebacks++;
875 }
876 if (rctx->flags & SI_CONTEXT_INV_VMEM_L1) {
877 /* Invalidate per-CU VMEM L1. */
878 si_emit_surface_sync(rctx, cp_coher_cntl |
879 S_0085F0_TCL1_ACTION_ENA(1));
880 cp_coher_cntl = 0;
881 }
882 }
883
884 /* If TC flushes haven't cleared this... */
885 if (cp_coher_cntl)
886 si_emit_surface_sync(rctx, cp_coher_cntl);
887
888 if (rctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
889 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
890 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
891 EVENT_INDEX(0));
892 } else if (rctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
893 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
894 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
895 EVENT_INDEX(0));
896 }
897
898 rctx->flags = 0;
899 }
900
901 static void si_get_draw_start_count(struct si_context *sctx,
902 const struct pipe_draw_info *info,
903 unsigned *start, unsigned *count)
904 {
905 if (info->indirect) {
906 struct r600_resource *indirect =
907 (struct r600_resource*)info->indirect;
908 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
909 indirect, PIPE_TRANSFER_READ);
910 data += info->indirect_offset/sizeof(int);
911 *start = data[2];
912 *count = data[0];
913 } else {
914 *start = info->start;
915 *count = info->count;
916 }
917 }
918
919 void si_ce_pre_draw_synchronization(struct si_context *sctx)
920 {
921 if (sctx->ce_need_synchronization) {
922 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
923 radeon_emit(sctx->ce_ib, 1);
924
925 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
926 radeon_emit(sctx->b.gfx.cs, 1);
927 }
928 }
929
930 void si_ce_post_draw_synchronization(struct si_context *sctx)
931 {
932 if (sctx->ce_need_synchronization) {
933 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
934 radeon_emit(sctx->b.gfx.cs, 0);
935
936 sctx->ce_need_synchronization = false;
937 }
938 }
939
940 static void cik_prefetch_shader_async(struct si_context *sctx,
941 struct si_pm4_state *state)
942 {
943 if (state) {
944 struct pipe_resource *bo = &state->bo[0]->b.b;
945 assert(state->nbo == 1);
946
947 cik_prefetch_TC_L2_async(sctx, bo, 0, bo->width0);
948 }
949 }
950
951 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
952 {
953 struct si_context *sctx = (struct si_context *)ctx;
954 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
955 struct pipe_index_buffer ib = {};
956 unsigned mask, dirty_fb_counter, dirty_tex_counter, rast_prim;
957
958 if (likely(!info->indirect)) {
959 /* SI-CI treat instance_count==0 as instance_count==1. There is
960 * no workaround for indirect draws, but we can at least skip
961 * direct draws.
962 */
963 if (unlikely(!info->instance_count))
964 return;
965
966 /* Handle count == 0. */
967 if (unlikely(!info->count &&
968 (info->indexed || !info->count_from_stream_output)))
969 return;
970 }
971
972 if (unlikely(!sctx->vs_shader.cso)) {
973 assert(0);
974 return;
975 }
976 if (unlikely(!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard))) {
977 assert(0);
978 return;
979 }
980 if (unlikely(!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES))) {
981 assert(0);
982 return;
983 }
984
985 /* Re-emit the framebuffer state if needed. */
986 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
987 if (unlikely(dirty_fb_counter != sctx->b.last_dirty_fb_counter)) {
988 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
989 sctx->framebuffer.dirty_cbufs |=
990 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
991 sctx->framebuffer.dirty_zsbuf = true;
992 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
993 }
994
995 /* Invalidate & recompute texture descriptors if needed. */
996 dirty_tex_counter = p_atomic_read(&sctx->b.screen->dirty_tex_descriptor_counter);
997 if (unlikely(dirty_tex_counter != sctx->b.last_dirty_tex_descriptor_counter)) {
998 sctx->b.last_dirty_tex_descriptor_counter = dirty_tex_counter;
999 si_update_all_texture_descriptors(sctx);
1000 }
1001
1002 si_decompress_graphics_textures(sctx);
1003
1004 /* Set the rasterization primitive type.
1005 *
1006 * This must be done after si_decompress_textures, which can call
1007 * draw_vbo recursively, and before si_update_shaders, which uses
1008 * current_rast_prim for this draw_vbo call. */
1009 if (sctx->gs_shader.cso)
1010 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1011 else if (sctx->tes_shader.cso)
1012 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1013 else
1014 rast_prim = info->mode;
1015
1016 if (rast_prim != sctx->current_rast_prim) {
1017 sctx->current_rast_prim = rast_prim;
1018 sctx->do_update_shaders = true;
1019 }
1020
1021 if (sctx->gs_shader.cso) {
1022 /* Determine whether the GS triangle strip adjacency fix should
1023 * be applied. Rotate every other triangle if
1024 * - triangle strips with adjacency are fed to the GS and
1025 * - primitive restart is disabled (the rotation doesn't help
1026 * when the restart occurs after an odd number of triangles).
1027 */
1028 bool gs_tri_strip_adj_fix =
1029 !sctx->tes_shader.cso &&
1030 info->mode == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1031 !info->primitive_restart;
1032
1033 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1034 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1035 sctx->do_update_shaders = true;
1036 }
1037 }
1038
1039 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1040 return;
1041
1042 if (!si_upload_graphics_shader_descriptors(sctx))
1043 return;
1044
1045 if (info->indexed) {
1046 /* Initialize the index buffer struct. */
1047 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
1048 ib.user_buffer = sctx->index_buffer.user_buffer;
1049 ib.index_size = sctx->index_buffer.index_size;
1050 ib.offset = sctx->index_buffer.offset;
1051
1052 /* Translate or upload, if needed. */
1053 /* 8-bit indices are supported on VI. */
1054 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
1055 struct pipe_resource *out_buffer = NULL;
1056 unsigned out_offset, start, count, start_offset;
1057 void *ptr;
1058
1059 si_get_draw_start_count(sctx, info, &start, &count);
1060 start_offset = start * ib.index_size;
1061
1062 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
1063 &out_offset, &out_buffer, &ptr);
1064 if (!out_buffer) {
1065 pipe_resource_reference(&ib.buffer, NULL);
1066 return;
1067 }
1068
1069 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
1070 ib.offset + start_offset,
1071 count, ptr);
1072
1073 pipe_resource_reference(&ib.buffer, NULL);
1074 ib.user_buffer = NULL;
1075 ib.buffer = out_buffer;
1076 /* info->start will be added by the drawing code */
1077 ib.offset = out_offset - start_offset;
1078 ib.index_size = 2;
1079 } else if (ib.user_buffer && !ib.buffer) {
1080 unsigned start, count, start_offset;
1081
1082 si_get_draw_start_count(sctx, info, &start, &count);
1083 start_offset = start * ib.index_size;
1084
1085 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
1086 256, (char*)ib.user_buffer + start_offset,
1087 &ib.offset, &ib.buffer);
1088 if (!ib.buffer)
1089 return;
1090 /* info->start will be added by the drawing code */
1091 ib.offset -= start_offset;
1092 }
1093 }
1094
1095 /* VI reads index buffers through TC L2. */
1096 if (info->indexed && sctx->b.chip_class <= CIK &&
1097 r600_resource(ib.buffer)->TC_L2_dirty) {
1098 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1099 r600_resource(ib.buffer)->TC_L2_dirty = false;
1100 }
1101
1102 if (info->indirect && r600_resource(info->indirect)->TC_L2_dirty) {
1103 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1104 r600_resource(info->indirect)->TC_L2_dirty = false;
1105 }
1106
1107 if (info->indirect_params &&
1108 r600_resource(info->indirect_params)->TC_L2_dirty) {
1109 sctx->b.flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1110 r600_resource(info->indirect_params)->TC_L2_dirty = false;
1111 }
1112
1113 /* Add buffer sizes for memory checking in need_cs_space. */
1114 if (sctx->emit_scratch_reloc && sctx->scratch_buffer)
1115 r600_context_add_resource_size(ctx, &sctx->scratch_buffer->b.b);
1116 if (info->indirect)
1117 r600_context_add_resource_size(ctx, info->indirect);
1118
1119 si_need_cs_space(sctx);
1120
1121 /* Since we've called r600_context_add_resource_size for vertex buffers,
1122 * this must be called after si_need_cs_space, because we must let
1123 * need_cs_space flush before we add buffers to the buffer list.
1124 */
1125 if (!si_upload_vertex_buffer_descriptors(sctx))
1126 return;
1127
1128 /* Flushed caches prior to prefetching shaders. */
1129 if (sctx->b.flags)
1130 si_emit_cache_flush(sctx);
1131
1132 /* Prefetch shaders and VBO descriptors to TC L2. */
1133 if (sctx->b.chip_class >= CIK) {
1134 if (si_pm4_state_changed(sctx, ls))
1135 cik_prefetch_shader_async(sctx, sctx->queued.named.ls);
1136 if (si_pm4_state_changed(sctx, hs))
1137 cik_prefetch_shader_async(sctx, sctx->queued.named.hs);
1138 if (si_pm4_state_changed(sctx, es))
1139 cik_prefetch_shader_async(sctx, sctx->queued.named.es);
1140 if (si_pm4_state_changed(sctx, gs))
1141 cik_prefetch_shader_async(sctx, sctx->queued.named.gs);
1142 if (si_pm4_state_changed(sctx, vs))
1143 cik_prefetch_shader_async(sctx, sctx->queued.named.vs);
1144
1145 /* Vertex buffer descriptors are uploaded uncached, so prefetch
1146 * them right after the VS binary. */
1147 if (sctx->vertex_buffers.pointer_dirty) {
1148 cik_prefetch_TC_L2_async(sctx, &sctx->vertex_buffers.buffer->b.b,
1149 sctx->vertex_buffers.buffer_offset,
1150 sctx->vertex_elements->count * 16);
1151 }
1152 if (si_pm4_state_changed(sctx, ps))
1153 cik_prefetch_shader_async(sctx, sctx->queued.named.ps);
1154 }
1155
1156 /* Emit states. */
1157 mask = sctx->dirty_atoms;
1158 while (mask) {
1159 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
1160
1161 atom->emit(&sctx->b, atom);
1162 }
1163 sctx->dirty_atoms = 0;
1164
1165 si_pm4_emit_dirty(sctx);
1166 si_emit_scratch_reloc(sctx);
1167 si_emit_rasterizer_prim_state(sctx);
1168 si_emit_draw_registers(sctx, info);
1169
1170 si_ce_pre_draw_synchronization(sctx);
1171
1172 si_emit_draw_packets(sctx, info, &ib);
1173
1174 si_ce_post_draw_synchronization(sctx);
1175
1176 if (sctx->trace_buf)
1177 si_trace_emit(sctx);
1178
1179 /* Workaround for a VGT hang when streamout is enabled.
1180 * It must be done after drawing. */
1181 if ((sctx->b.family == CHIP_HAWAII ||
1182 sctx->b.family == CHIP_TONGA ||
1183 sctx->b.family == CHIP_FIJI) &&
1184 r600_get_strmout_en(&sctx->b)) {
1185 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1186 }
1187
1188 /* Set the depth buffer as dirty. */
1189 if (sctx->framebuffer.state.zsbuf) {
1190 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
1191 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
1192
1193 if (!rtex->tc_compatible_htile)
1194 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1195
1196 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
1197 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
1198 }
1199 if (sctx->framebuffer.compressed_cb_mask) {
1200 struct pipe_surface *surf;
1201 struct r600_texture *rtex;
1202 unsigned mask = sctx->framebuffer.compressed_cb_mask;
1203
1204 do {
1205 unsigned i = u_bit_scan(&mask);
1206 surf = sctx->framebuffer.state.cbufs[i];
1207 rtex = (struct r600_texture*)surf->texture;
1208
1209 if (rtex->fmask.size)
1210 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
1211 if (rtex->dcc_gather_statistics)
1212 rtex->separate_dcc_dirty = true;
1213 } while (mask);
1214 }
1215
1216 pipe_resource_reference(&ib.buffer, NULL);
1217 sctx->b.num_draw_calls++;
1218 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1219 sctx->b.num_spill_draw_calls++;
1220 }
1221
1222 void si_trace_emit(struct si_context *sctx)
1223 {
1224 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1225
1226 sctx->trace_id++;
1227 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
1228 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
1229 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
1230 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
1231 S_370_WR_CONFIRM(1) |
1232 S_370_ENGINE_SEL(V_370_ME));
1233 radeon_emit(cs, sctx->trace_buf->gpu_address);
1234 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
1235 radeon_emit(cs, sctx->trace_id);
1236 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1237 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
1238 }