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radeonsi: put up to 5 VBO descriptors into user SGPRs
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
33
34 #include "ac_debug.h"
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 /**
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
66 *
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
69 */
70 static void si_emit_derived_tess_state(struct si_context *sctx,
71 const struct pipe_draw_info *info,
72 unsigned *num_patches)
73 {
74 struct radeon_cmdbuf *cs = sctx->gfx_cs;
75 struct si_shader *ls_current;
76 struct si_shader_selector *ls;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector *tcs =
80 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
81 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
82 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
83 sctx->screen->info.max_se == 1;
84 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
85 unsigned num_tcs_input_cp = info->vertices_per_patch;
86 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
87 unsigned num_tcs_patch_outputs;
88 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
89 unsigned input_patch_size, output_patch_size, output_patch0_offset;
90 unsigned perpatch_output_offset, lds_size;
91 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
92 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
93
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx->chip_class >= GFX9) {
96 if (sctx->tcs_shader.cso)
97 ls_current = sctx->tcs_shader.current;
98 else
99 ls_current = sctx->fixed_func_tcs_shader.current;
100
101 ls = ls_current->key.part.tcs.ls;
102 } else {
103 ls_current = sctx->vs_shader.current;
104 ls = sctx->vs_shader.cso;
105 }
106
107 if (sctx->last_ls == ls_current &&
108 sctx->last_tcs == tcs &&
109 sctx->last_tes_sh_base == tes_sh_base &&
110 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
111 (!has_primid_instancing_bug ||
112 (sctx->last_tess_uses_primid == tess_uses_primid))) {
113 *num_patches = sctx->last_num_patches;
114 return;
115 }
116
117 sctx->last_ls = ls_current;
118 sctx->last_tcs = tcs;
119 sctx->last_tes_sh_base = tes_sh_base;
120 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
121 sctx->last_tess_uses_primid = tess_uses_primid;
122
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs = util_last_bit64(ls->outputs_written);
126
127 if (sctx->tcs_shader.cso) {
128 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
129 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
130 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
131 } else {
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs = num_tcs_inputs;
134 num_tcs_output_cp = num_tcs_input_cp;
135 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
136 }
137
138 input_vertex_size = ls->lshs_vertex_stride;
139 output_vertex_size = num_tcs_outputs * 16;
140
141 input_patch_size = num_tcs_input_cp * input_vertex_size;
142
143 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
144 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
145
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
149 */
150 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
151 *num_patches = 256 / max_verts_per_patch;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 *
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
159 */
160 hardware_lds_size = 32768;
161 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
162 output_patch_size));
163
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches = MIN2(*num_patches,
166 (sctx->screen->tess_offchip_block_dw_size * 4) /
167 output_patch_size);
168
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
171 * limited to 6 bits.
172 */
173 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
174
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
177 */
178 if (!sctx->screen->info.has_distributed_tess && sctx->screen->info.max_se > 1)
179 *num_patches = MIN2(*num_patches, 16); /* recommended */
180
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
184 */
185 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
186 unsigned wave_size = sctx->screen->ge_wave_size;
187
188 if (temp_verts_per_tg > wave_size && temp_verts_per_tg % wave_size < wave_size*3/4)
189 *num_patches = (temp_verts_per_tg & ~(wave_size - 1)) / max_verts_per_patch;
190
191 if (sctx->chip_class == GFX6) {
192 /* GFX6 bug workaround, related to power management. Limit LS-HS
193 * threadgroups to only one wave.
194 */
195 unsigned one_wave = wave_size / max_verts_per_patch;
196 *num_patches = MIN2(*num_patches, one_wave);
197 }
198
199 /* The VGT HS block increments the patch ID unconditionally
200 * within a single threadgroup. This results in incorrect
201 * patch IDs when instanced draws are used.
202 *
203 * The intended solution is to restrict threadgroups to
204 * a single instance by setting SWITCH_ON_EOI, which
205 * should cause IA to split instances up. However, this
206 * doesn't work correctly on GFX6 when there is no other
207 * SE to switch to.
208 */
209 if (has_primid_instancing_bug && tess_uses_primid)
210 *num_patches = 1;
211
212 sctx->last_num_patches = *num_patches;
213
214 output_patch0_offset = input_patch_size * *num_patches;
215 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
216
217 /* Compute userdata SGPRs. */
218 assert(((input_vertex_size / 4) & ~0xff) == 0);
219 assert(((output_vertex_size / 4) & ~0xff) == 0);
220 assert(((input_patch_size / 4) & ~0x1fff) == 0);
221 assert(((output_patch_size / 4) & ~0x1fff) == 0);
222 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
223 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
224 assert(num_tcs_input_cp <= 32);
225 assert(num_tcs_output_cp <= 32);
226
227 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
228 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
229
230 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
231 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
232 tcs_out_layout = (output_patch_size / 4) |
233 (num_tcs_input_cp << 13) |
234 ring_va;
235 tcs_out_offsets = (output_patch0_offset / 16) |
236 ((perpatch_output_offset / 16) << 16);
237 offchip_layout = *num_patches |
238 (num_tcs_output_cp << 6) |
239 (pervertex_output_patch_size * *num_patches << 12);
240
241 /* Compute the LDS size. */
242 lds_size = output_patch0_offset + output_patch_size * *num_patches;
243
244 if (sctx->chip_class >= GFX7) {
245 assert(lds_size <= 65536);
246 lds_size = align(lds_size, 512) / 512;
247 } else {
248 assert(lds_size <= 32768);
249 lds_size = align(lds_size, 256) / 256;
250 }
251
252 /* Set SI_SGPR_VS_STATE_BITS. */
253 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
254 C_VS_STATE_LS_OUT_VERTEX_SIZE;
255 sctx->current_vs_state |= tcs_in_layout;
256
257 /* We should be able to support in-shader LDS use with LLVM >= 9
258 * by just adding the lds_sizes together, but it has never
259 * been tested. */
260 assert(ls_current->config.lds_size == 0);
261
262 if (sctx->chip_class >= GFX9) {
263 unsigned hs_rsrc2 = ls_current->config.rsrc2;
264
265 if (sctx->chip_class >= GFX10)
266 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(lds_size);
267 else
268 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(lds_size);
269
270 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
271
272 /* Set userdata SGPRs for merged LS-HS. */
273 radeon_set_sh_reg_seq(cs,
274 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
275 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
276 radeon_emit(cs, offchip_layout);
277 radeon_emit(cs, tcs_out_offsets);
278 radeon_emit(cs, tcs_out_layout);
279 } else {
280 unsigned ls_rsrc2 = ls_current->config.rsrc2;
281
282 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
283 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
284
285 /* Due to a hw bug, RSRC2_LS must be written twice with another
286 * LS register written in between. */
287 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
288 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
289 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
290 radeon_emit(cs, ls_current->config.rsrc1);
291 radeon_emit(cs, ls_rsrc2);
292
293 /* Set userdata SGPRs for TCS. */
294 radeon_set_sh_reg_seq(cs,
295 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
296 radeon_emit(cs, offchip_layout);
297 radeon_emit(cs, tcs_out_offsets);
298 radeon_emit(cs, tcs_out_layout);
299 radeon_emit(cs, tcs_in_layout);
300 }
301
302 /* Set userdata SGPRs for TES. */
303 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
304 radeon_emit(cs, offchip_layout);
305 radeon_emit(cs, ring_va);
306
307 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
308 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
309 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
310
311 if (sctx->last_ls_hs_config != ls_hs_config) {
312 if (sctx->chip_class >= GFX7) {
313 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
314 ls_hs_config);
315 } else {
316 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
317 ls_hs_config);
318 }
319 sctx->last_ls_hs_config = ls_hs_config;
320 sctx->context_roll = true;
321 }
322 }
323
324 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
325 enum pipe_prim_type prim)
326 {
327 switch (prim) {
328 case PIPE_PRIM_PATCHES:
329 return info->count / info->vertices_per_patch;
330 case PIPE_PRIM_POLYGON:
331 return info->count >= 3;
332 case SI_PRIM_RECTANGLE_LIST:
333 return info->count / 3;
334 default:
335 return u_decomposed_prims_for_vertices(prim, info->count);
336 }
337 }
338
339 static unsigned
340 si_get_init_multi_vgt_param(struct si_screen *sscreen,
341 union si_vgt_param_key *key)
342 {
343 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
344 unsigned max_primgroup_in_wave = 2;
345
346 /* SWITCH_ON_EOP(0) is always preferable. */
347 bool wd_switch_on_eop = false;
348 bool ia_switch_on_eop = false;
349 bool ia_switch_on_eoi = false;
350 bool partial_vs_wave = false;
351 bool partial_es_wave = false;
352
353 if (key->u.uses_tess) {
354 /* SWITCH_ON_EOI must be set if PrimID is used. */
355 if (key->u.tess_uses_prim_id)
356 ia_switch_on_eoi = true;
357
358 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
359 if ((sscreen->info.family == CHIP_TAHITI ||
360 sscreen->info.family == CHIP_PITCAIRN ||
361 sscreen->info.family == CHIP_BONAIRE) &&
362 key->u.uses_gs)
363 partial_vs_wave = true;
364
365 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
366 if (sscreen->info.has_distributed_tess) {
367 if (key->u.uses_gs) {
368 if (sscreen->info.chip_class == GFX8)
369 partial_es_wave = true;
370 } else {
371 partial_vs_wave = true;
372 }
373 }
374 }
375
376 /* This is a hardware requirement. */
377 if (key->u.line_stipple_enabled ||
378 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
379 ia_switch_on_eop = true;
380 wd_switch_on_eop = true;
381 }
382
383 if (sscreen->info.chip_class >= GFX7) {
384 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
385 * 4 shader engines. Set 1 to pass the assertion below.
386 * The other cases are hardware requirements.
387 *
388 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
389 * for points, line strips, and tri strips.
390 */
391 if (sscreen->info.max_se <= 2 ||
392 key->u.prim == PIPE_PRIM_POLYGON ||
393 key->u.prim == PIPE_PRIM_LINE_LOOP ||
394 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
395 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
396 (key->u.primitive_restart &&
397 (sscreen->info.family < CHIP_POLARIS10 ||
398 (key->u.prim != PIPE_PRIM_POINTS &&
399 key->u.prim != PIPE_PRIM_LINE_STRIP &&
400 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
401 key->u.count_from_stream_output)
402 wd_switch_on_eop = true;
403
404 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
405 * We don't know that for indirect drawing, so treat it as
406 * always problematic. */
407 if (sscreen->info.family == CHIP_HAWAII &&
408 key->u.uses_instancing)
409 wd_switch_on_eop = true;
410
411 /* Performance recommendation for 4 SE Gfx7-8 parts if
412 * instances are smaller than a primgroup.
413 * Assume indirect draws always use small instances.
414 * This is needed for good VS wave utilization.
415 */
416 if (sscreen->info.chip_class <= GFX8 &&
417 sscreen->info.max_se == 4 &&
418 key->u.multi_instances_smaller_than_primgroup)
419 wd_switch_on_eop = true;
420
421 /* Required on GFX7 and later. */
422 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
423 ia_switch_on_eoi = true;
424
425 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
426 * to work around a GS hang.
427 */
428 if (key->u.uses_gs &&
429 (sscreen->info.family == CHIP_TONGA ||
430 sscreen->info.family == CHIP_FIJI ||
431 sscreen->info.family == CHIP_POLARIS10 ||
432 sscreen->info.family == CHIP_POLARIS11 ||
433 sscreen->info.family == CHIP_POLARIS12 ||
434 sscreen->info.family == CHIP_VEGAM))
435 partial_vs_wave = true;
436
437 /* Required by Hawaii and, for some special cases, by GFX8. */
438 if (ia_switch_on_eoi &&
439 (sscreen->info.family == CHIP_HAWAII ||
440 (sscreen->info.chip_class == GFX8 &&
441 (key->u.uses_gs || max_primgroup_in_wave != 2))))
442 partial_vs_wave = true;
443
444 /* Instancing bug on Bonaire. */
445 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
446 key->u.uses_instancing)
447 partial_vs_wave = true;
448
449 /* This only applies to Polaris10 and later 4 SE chips.
450 * wd_switch_on_eop is already true on all other chips.
451 */
452 if (!wd_switch_on_eop && key->u.primitive_restart)
453 partial_vs_wave = true;
454
455 /* If the WD switch is false, the IA switch must be false too. */
456 assert(wd_switch_on_eop || !ia_switch_on_eop);
457 }
458
459 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
460 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
461 partial_es_wave = true;
462
463 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
464 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
465 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
466 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
467 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
468 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
469 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
470 max_primgroup_in_wave : 0) |
471 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
472 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
473 }
474
475 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
476 {
477 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
478 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
479 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
480 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
481 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
482 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
483 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
484 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
485 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
486 union si_vgt_param_key key;
487
488 key.index = 0;
489 key.u.prim = prim;
490 key.u.uses_instancing = uses_instancing;
491 key.u.multi_instances_smaller_than_primgroup = multi_instances;
492 key.u.primitive_restart = primitive_restart;
493 key.u.count_from_stream_output = count_from_so;
494 key.u.line_stipple_enabled = line_stipple;
495 key.u.uses_tess = uses_tess;
496 key.u.tess_uses_prim_id = tess_uses_primid;
497 key.u.uses_gs = uses_gs;
498
499 sctx->ia_multi_vgt_param[key.index] =
500 si_get_init_multi_vgt_param(sctx->screen, &key);
501 }
502 }
503
504 static bool si_is_line_stipple_enabled(struct si_context *sctx)
505 {
506 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
507
508 return rs->line_stipple_enable &&
509 sctx->current_rast_prim != PIPE_PRIM_POINTS &&
510 (rs->polygon_mode_is_lines ||
511 util_prim_is_lines(sctx->current_rast_prim));
512 }
513
514 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
515 const struct pipe_draw_info *info,
516 enum pipe_prim_type prim,
517 unsigned num_patches,
518 unsigned instance_count,
519 bool primitive_restart)
520 {
521 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
522 unsigned primgroup_size;
523 unsigned ia_multi_vgt_param;
524
525 if (sctx->tes_shader.cso) {
526 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
527 } else if (sctx->gs_shader.cso) {
528 primgroup_size = 64; /* recommended with a GS */
529 } else {
530 primgroup_size = 128; /* recommended without a GS and tess */
531 }
532
533 key.u.prim = prim;
534 key.u.uses_instancing = info->indirect || instance_count > 1;
535 key.u.multi_instances_smaller_than_primgroup =
536 info->indirect ||
537 (instance_count > 1 &&
538 (info->count_from_stream_output ||
539 si_num_prims_for_vertices(info, prim) < primgroup_size));
540 key.u.primitive_restart = primitive_restart;
541 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
542 key.u.line_stipple_enabled = si_is_line_stipple_enabled(sctx);
543
544 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
545 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
546
547 if (sctx->gs_shader.cso) {
548 /* GS requirement. */
549 if (sctx->chip_class <= GFX8 &&
550 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
551 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
552
553 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
554 * The hw doc says all multi-SE chips are affected, but Vulkan
555 * only applies it to Hawaii. Do what Vulkan does.
556 */
557 if (sctx->family == CHIP_HAWAII &&
558 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
559 (info->indirect ||
560 (instance_count > 1 &&
561 (info->count_from_stream_output ||
562 si_num_prims_for_vertices(info, prim) <= 1))))
563 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
564 }
565
566 return ia_multi_vgt_param;
567 }
568
569 static unsigned si_conv_prim_to_gs_out(unsigned mode)
570 {
571 static const int prim_conv[] = {
572 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
573 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
574 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
575 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
576 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
577 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
578 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
579 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
580 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
581 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
582 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
583 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
584 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
585 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
586 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
587 [SI_PRIM_RECTANGLE_LIST] = V_028A6C_VGT_OUT_RECT_V0,
588 };
589 assert(mode < ARRAY_SIZE(prim_conv));
590
591 return prim_conv[mode];
592 }
593
594 /* rast_prim is the primitive type after GS. */
595 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
596 {
597 struct radeon_cmdbuf *cs = sctx->gfx_cs;
598 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
599 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
600 unsigned initial_cdw = cs->current.cdw;
601
602 if (unlikely(si_is_line_stipple_enabled(sctx))) {
603 /* For lines, reset the stipple pattern at each primitive. Otherwise,
604 * reset the stipple pattern at each packet (line strips, line loops).
605 */
606 unsigned value = rs->pa_sc_line_stipple |
607 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2);
608
609 radeon_opt_set_context_reg(sctx, R_028A0C_PA_SC_LINE_STIPPLE,
610 SI_TRACKED_PA_SC_LINE_STIPPLE, value);
611 }
612
613 unsigned gs_out_prim = si_conv_prim_to_gs_out(rast_prim);
614 if (unlikely(gs_out_prim != sctx->last_gs_out_prim &&
615 (sctx->ngg || sctx->gs_shader.cso))) {
616 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
617 sctx->last_gs_out_prim = gs_out_prim;
618 }
619
620 if (initial_cdw != cs->current.cdw)
621 sctx->context_roll = true;
622
623 if (sctx->ngg) {
624 unsigned vtx_index = rs->flatshade_first ? 0 : gs_out_prim;
625
626 sctx->current_vs_state &= C_VS_STATE_OUTPRIM &
627 C_VS_STATE_PROVOKING_VTX_INDEX;
628 sctx->current_vs_state |= S_VS_STATE_OUTPRIM(gs_out_prim) |
629 S_VS_STATE_PROVOKING_VTX_INDEX(vtx_index);
630 }
631 }
632
633 static void si_emit_vs_state(struct si_context *sctx,
634 const struct pipe_draw_info *info)
635 {
636 sctx->current_vs_state &= C_VS_STATE_INDEXED;
637 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
638
639 if (sctx->num_vs_blit_sgprs) {
640 /* Re-emit the state after we leave u_blitter. */
641 sctx->last_vs_state = ~0;
642 return;
643 }
644
645 if (sctx->current_vs_state != sctx->last_vs_state) {
646 struct radeon_cmdbuf *cs = sctx->gfx_cs;
647
648 /* For the API vertex shader (VS_STATE_INDEXED, LS_OUT_*). */
649 radeon_set_sh_reg(cs,
650 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
651 SI_SGPR_VS_STATE_BITS * 4,
652 sctx->current_vs_state);
653
654 /* Set CLAMP_VERTEX_COLOR and OUTPRIM in the last stage
655 * before the rasterizer.
656 *
657 * For TES or the GS copy shader without NGG:
658 */
659 if (sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
660 R_00B130_SPI_SHADER_USER_DATA_VS_0) {
661 radeon_set_sh_reg(cs,
662 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
663 SI_SGPR_VS_STATE_BITS * 4,
664 sctx->current_vs_state);
665 }
666
667 /* For NGG: */
668 if (sctx->screen->use_ngg &&
669 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] !=
670 R_00B230_SPI_SHADER_USER_DATA_GS_0) {
671 radeon_set_sh_reg(cs,
672 R_00B230_SPI_SHADER_USER_DATA_GS_0 +
673 SI_SGPR_VS_STATE_BITS * 4,
674 sctx->current_vs_state);
675 }
676
677 sctx->last_vs_state = sctx->current_vs_state;
678 }
679 }
680
681 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
682 bool primitive_restart,
683 unsigned restart_index)
684 {
685 return primitive_restart &&
686 (restart_index != sctx->last_restart_index ||
687 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
688 }
689
690 static void si_emit_ia_multi_vgt_param(struct si_context *sctx,
691 const struct pipe_draw_info *info,
692 enum pipe_prim_type prim,
693 unsigned num_patches,
694 unsigned instance_count,
695 bool primitive_restart)
696 {
697 struct radeon_cmdbuf *cs = sctx->gfx_cs;
698 unsigned ia_multi_vgt_param;
699
700 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
701 instance_count, primitive_restart);
702
703 /* Draw state. */
704 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
705 if (sctx->chip_class == GFX9)
706 radeon_set_uconfig_reg_idx(cs, sctx->screen,
707 R_030960_IA_MULTI_VGT_PARAM, 4,
708 ia_multi_vgt_param);
709 else if (sctx->chip_class >= GFX7)
710 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
711 else
712 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
713
714 sctx->last_multi_vgt_param = ia_multi_vgt_param;
715 }
716 }
717
718 /* GFX10 removed IA_MULTI_VGT_PARAM in exchange for GE_CNTL.
719 * We overload last_multi_vgt_param.
720 */
721 static void gfx10_emit_ge_cntl(struct si_context *sctx, unsigned num_patches)
722 {
723 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
724 unsigned ge_cntl;
725
726 if (sctx->ngg) {
727 if (sctx->tes_shader.cso) {
728 ge_cntl = S_03096C_PRIM_GRP_SIZE(num_patches) |
729 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
730 S_03096C_BREAK_WAVE_AT_EOI(key.u.tess_uses_prim_id);
731 } else {
732 ge_cntl = si_get_vs_state(sctx)->ge_cntl;
733 }
734 } else {
735 unsigned primgroup_size;
736 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */;
737
738 if (sctx->tes_shader.cso) {
739 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
740 } else if (sctx->gs_shader.cso) {
741 unsigned vgt_gs_onchip_cntl = sctx->gs_shader.current->ctx_reg.gs.vgt_gs_onchip_cntl;
742 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
743 } else {
744 primgroup_size = 128; /* recommended without a GS and tess */
745 }
746
747 ge_cntl = S_03096C_PRIM_GRP_SIZE(primgroup_size) |
748 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
749 S_03096C_BREAK_WAVE_AT_EOI(key.u.uses_tess && key.u.tess_uses_prim_id);
750 }
751
752 ge_cntl |= S_03096C_PACKET_TO_ONE_PA(si_is_line_stipple_enabled(sctx));
753
754 if (ge_cntl != sctx->last_multi_vgt_param) {
755 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, ge_cntl);
756 sctx->last_multi_vgt_param = ge_cntl;
757 }
758 }
759
760 static void si_emit_draw_registers(struct si_context *sctx,
761 const struct pipe_draw_info *info,
762 enum pipe_prim_type prim,
763 unsigned num_patches,
764 unsigned instance_count,
765 bool primitive_restart)
766 {
767 struct radeon_cmdbuf *cs = sctx->gfx_cs;
768 unsigned vgt_prim = si_conv_pipe_prim(prim);
769
770 if (sctx->chip_class >= GFX10)
771 gfx10_emit_ge_cntl(sctx, num_patches);
772 else
773 si_emit_ia_multi_vgt_param(sctx, info, prim, num_patches,
774 instance_count, primitive_restart);
775
776 if (vgt_prim != sctx->last_prim) {
777 if (sctx->chip_class >= GFX10)
778 radeon_set_uconfig_reg(cs, R_030908_VGT_PRIMITIVE_TYPE, vgt_prim);
779 else if (sctx->chip_class >= GFX7)
780 radeon_set_uconfig_reg_idx(cs, sctx->screen,
781 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
782 else
783 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
784
785 sctx->last_prim = vgt_prim;
786 }
787
788 /* Primitive restart. */
789 if (primitive_restart != sctx->last_primitive_restart_en) {
790 if (sctx->chip_class >= GFX9)
791 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
792 primitive_restart);
793 else
794 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
795 primitive_restart);
796
797 sctx->last_primitive_restart_en = primitive_restart;
798
799 }
800 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
801 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
802 info->restart_index);
803 sctx->last_restart_index = info->restart_index;
804 sctx->context_roll = true;
805 }
806 }
807
808 static void si_emit_draw_packets(struct si_context *sctx,
809 const struct pipe_draw_info *info,
810 struct pipe_resource *indexbuf,
811 unsigned index_size,
812 unsigned index_offset,
813 unsigned instance_count,
814 bool dispatch_prim_discard_cs,
815 unsigned original_index_size)
816 {
817 struct pipe_draw_indirect_info *indirect = info->indirect;
818 struct radeon_cmdbuf *cs = sctx->gfx_cs;
819 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
820 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
821 uint32_t index_max_size = 0;
822 uint64_t index_va = 0;
823
824 if (info->count_from_stream_output) {
825 struct si_streamout_target *t =
826 (struct si_streamout_target*)info->count_from_stream_output;
827
828 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
829 t->stride_in_dw);
830 si_cp_copy_data(sctx, sctx->gfx_cs,
831 COPY_DATA_REG, NULL,
832 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
833 COPY_DATA_SRC_MEM, t->buf_filled_size,
834 t->buf_filled_size_offset);
835 }
836
837 /* draw packet */
838 if (index_size) {
839 if (index_size != sctx->last_index_size) {
840 unsigned index_type;
841
842 /* index type */
843 switch (index_size) {
844 case 1:
845 index_type = V_028A7C_VGT_INDEX_8;
846 break;
847 case 2:
848 index_type = V_028A7C_VGT_INDEX_16 |
849 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
850 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
851 break;
852 case 4:
853 index_type = V_028A7C_VGT_INDEX_32 |
854 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
855 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
856 break;
857 default:
858 assert(!"unreachable");
859 return;
860 }
861
862 if (sctx->chip_class >= GFX9) {
863 radeon_set_uconfig_reg_idx(cs, sctx->screen,
864 R_03090C_VGT_INDEX_TYPE, 2,
865 index_type);
866 } else {
867 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
868 radeon_emit(cs, index_type);
869 }
870
871 sctx->last_index_size = index_size;
872 }
873
874 if (original_index_size) {
875 index_max_size = (indexbuf->width0 - index_offset) /
876 original_index_size;
877 /* Skip draw calls with 0-sized index buffers.
878 * They cause a hang on some chips, like Navi10-14.
879 */
880 if (!index_max_size)
881 return;
882
883 index_va = si_resource(indexbuf)->gpu_address + index_offset;
884
885 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
886 si_resource(indexbuf),
887 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
888 }
889 } else {
890 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
891 * so the state must be re-emitted before the next indexed draw.
892 */
893 if (sctx->chip_class >= GFX7)
894 sctx->last_index_size = -1;
895 }
896
897 if (indirect) {
898 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
899
900 assert(indirect_va % 8 == 0);
901
902 si_invalidate_draw_sh_constants(sctx);
903
904 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
905 radeon_emit(cs, 1);
906 radeon_emit(cs, indirect_va);
907 radeon_emit(cs, indirect_va >> 32);
908
909 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
910 si_resource(indirect->buffer),
911 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
912
913 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
914 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
915
916 assert(indirect->offset % 4 == 0);
917
918 if (index_size) {
919 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
920 radeon_emit(cs, index_va);
921 radeon_emit(cs, index_va >> 32);
922
923 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
924 radeon_emit(cs, index_max_size);
925 }
926
927 if (!sctx->screen->has_draw_indirect_multi) {
928 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
929 : PKT3_DRAW_INDIRECT,
930 3, render_cond_bit));
931 radeon_emit(cs, indirect->offset);
932 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
933 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
934 radeon_emit(cs, di_src_sel);
935 } else {
936 uint64_t count_va = 0;
937
938 if (indirect->indirect_draw_count) {
939 struct si_resource *params_buf =
940 si_resource(indirect->indirect_draw_count);
941
942 radeon_add_to_buffer_list(
943 sctx, sctx->gfx_cs, params_buf,
944 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
945
946 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
947 }
948
949 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
950 PKT3_DRAW_INDIRECT_MULTI,
951 8, render_cond_bit));
952 radeon_emit(cs, indirect->offset);
953 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
954 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
955 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
956 S_2C3_DRAW_INDEX_ENABLE(1) |
957 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
958 radeon_emit(cs, indirect->draw_count);
959 radeon_emit(cs, count_va);
960 radeon_emit(cs, count_va >> 32);
961 radeon_emit(cs, indirect->stride);
962 radeon_emit(cs, di_src_sel);
963 }
964 } else {
965 int base_vertex;
966
967 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
968 sctx->last_instance_count != instance_count) {
969 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
970 radeon_emit(cs, instance_count);
971 sctx->last_instance_count = instance_count;
972 }
973
974 /* Base vertex and start instance. */
975 base_vertex = original_index_size ? info->index_bias : info->start;
976
977 if (sctx->num_vs_blit_sgprs) {
978 /* Re-emit draw constants after we leave u_blitter. */
979 si_invalidate_draw_sh_constants(sctx);
980
981 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
982 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
983 sctx->num_vs_blit_sgprs);
984 radeon_emit_array(cs, sctx->vs_blit_sh_data,
985 sctx->num_vs_blit_sgprs);
986 } else if (base_vertex != sctx->last_base_vertex ||
987 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
988 info->start_instance != sctx->last_start_instance ||
989 info->drawid != sctx->last_drawid ||
990 sh_base_reg != sctx->last_sh_base_reg) {
991 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
992 radeon_emit(cs, base_vertex);
993 radeon_emit(cs, info->start_instance);
994 radeon_emit(cs, info->drawid);
995
996 sctx->last_base_vertex = base_vertex;
997 sctx->last_start_instance = info->start_instance;
998 sctx->last_drawid = info->drawid;
999 sctx->last_sh_base_reg = sh_base_reg;
1000 }
1001
1002 if (index_size) {
1003 if (dispatch_prim_discard_cs) {
1004 index_va += info->start * original_index_size;
1005 index_max_size = MIN2(index_max_size, info->count);
1006
1007 si_dispatch_prim_discard_cs_and_draw(sctx, info,
1008 original_index_size,
1009 base_vertex,
1010 index_va, index_max_size);
1011 return;
1012 }
1013
1014 index_va += info->start * index_size;
1015
1016 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
1017 radeon_emit(cs, index_max_size);
1018 radeon_emit(cs, index_va);
1019 radeon_emit(cs, index_va >> 32);
1020 radeon_emit(cs, info->count);
1021 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
1022 } else {
1023 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
1024 radeon_emit(cs, info->count);
1025 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
1026 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
1027 }
1028 }
1029 }
1030
1031 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
1032 unsigned cp_coher_cntl)
1033 {
1034 bool compute_ib = !sctx->has_graphics ||
1035 cs == sctx->prim_discard_compute_cs;
1036
1037 assert(sctx->chip_class <= GFX9);
1038
1039 if (sctx->chip_class == GFX9 || compute_ib) {
1040 /* Flush caches and wait for the caches to assert idle. */
1041 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
1042 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1043 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1044 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1045 radeon_emit(cs, 0); /* CP_COHER_BASE */
1046 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1047 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1048 } else {
1049 /* ACQUIRE_MEM is only required on a compute ring. */
1050 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
1051 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
1052 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1053 radeon_emit(cs, 0); /* CP_COHER_BASE */
1054 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1055 }
1056
1057 /* ACQUIRE_MEM has an implicit context roll if the current context
1058 * is busy. */
1059 if (!compute_ib)
1060 sctx->context_roll = true;
1061 }
1062
1063 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
1064 {
1065 if (!si_compute_prim_discard_enabled(sctx))
1066 return;
1067
1068 if (!sctx->barrier_buf) {
1069 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
1070 &sctx->barrier_buf_offset,
1071 (struct pipe_resource**)&sctx->barrier_buf);
1072 }
1073
1074 /* Emit a placeholder to signal the next compute IB to start.
1075 * See si_compute_prim_discard.c for explanation.
1076 */
1077 uint32_t signal = 1;
1078 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset,
1079 4, V_370_MEM, V_370_ME, &signal);
1080
1081 sctx->last_pkt3_write_data =
1082 &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
1083
1084 /* Only the last occurence of WRITE_DATA will be executed.
1085 * The packet will be enabled in si_flush_gfx_cs.
1086 */
1087 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
1088 }
1089
1090 void gfx10_emit_cache_flush(struct si_context *ctx)
1091 {
1092 struct radeon_cmdbuf *cs = ctx->gfx_cs;
1093 uint32_t gcr_cntl = 0;
1094 unsigned cb_db_event = 0;
1095 unsigned flags = ctx->flags;
1096
1097 if (!ctx->has_graphics) {
1098 /* Only process compute flags. */
1099 flags &= SI_CONTEXT_INV_ICACHE |
1100 SI_CONTEXT_INV_SCACHE |
1101 SI_CONTEXT_INV_VCACHE |
1102 SI_CONTEXT_INV_L2 |
1103 SI_CONTEXT_WB_L2 |
1104 SI_CONTEXT_INV_L2_METADATA |
1105 SI_CONTEXT_CS_PARTIAL_FLUSH;
1106 }
1107
1108 /* We don't need these. */
1109 assert(!(flags & (SI_CONTEXT_VGT_STREAMOUT_SYNC |
1110 SI_CONTEXT_FLUSH_AND_INV_DB_META)));
1111
1112 if (flags & SI_CONTEXT_VGT_FLUSH) {
1113 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1114 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1115 }
1116
1117 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1118 ctx->num_cb_cache_flushes++;
1119 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1120 ctx->num_db_cache_flushes++;
1121
1122 if (flags & SI_CONTEXT_INV_ICACHE)
1123 gcr_cntl |= S_586_GLI_INV(V_586_GLI_ALL);
1124 if (flags & SI_CONTEXT_INV_SCACHE) {
1125 /* TODO: When writing to the SMEM L1 cache, we need to set SEQ
1126 * to FORWARD when both L1 and L2 are written out (WB or INV).
1127 */
1128 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLK_INV(1);
1129 }
1130 if (flags & SI_CONTEXT_INV_VCACHE)
1131 gcr_cntl |= S_586_GL1_INV(1) | S_586_GLV_INV(1);
1132
1133 /* The L2 cache ops are:
1134 * - INV: - invalidate lines that reflect memory (were loaded from memory)
1135 * - don't touch lines that were overwritten (were stored by gfx clients)
1136 * - WB: - don't touch lines that reflect memory
1137 * - write back lines that were overwritten
1138 * - WB | INV: - invalidate lines that reflect memory
1139 * - write back lines that were overwritten
1140 *
1141 * GLM doesn't support WB alone. If WB is set, INV must be set too.
1142 */
1143 if (flags & SI_CONTEXT_INV_L2) {
1144 /* Writeback and invalidate everything in L2. */
1145 gcr_cntl |= S_586_GL2_INV(1) | S_586_GL2_WB(1) |
1146 S_586_GLM_INV(1) | S_586_GLM_WB(1);
1147 ctx->num_L2_invalidates++;
1148 } else if (flags & SI_CONTEXT_WB_L2) {
1149 gcr_cntl |= S_586_GL2_WB(1) |
1150 S_586_GLM_WB(1) | S_586_GLM_INV(1);
1151 } else if (flags & SI_CONTEXT_INV_L2_METADATA) {
1152 gcr_cntl |= S_586_GLM_INV(1) | S_586_GLM_WB(1);
1153 }
1154
1155 if (flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1156 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1157 /* Flush CMASK/FMASK/DCC. Will wait for idle later. */
1158 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1159 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) |
1160 EVENT_INDEX(0));
1161 }
1162 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1163 /* Flush HTILE. Will wait for idle later. */
1164 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1165 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) |
1166 EVENT_INDEX(0));
1167 }
1168
1169 /* First flush CB/DB, then L1/L2. */
1170 gcr_cntl |= S_586_SEQ(V_586_SEQ_FORWARD);
1171
1172 if ((flags & (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) ==
1173 (SI_CONTEXT_FLUSH_AND_INV_CB | SI_CONTEXT_FLUSH_AND_INV_DB)) {
1174 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1175 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1176 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1177 } else if (flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
1178 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1179 } else {
1180 assert(0);
1181 }
1182 } else {
1183 /* Wait for graphics shaders to go idle if requested. */
1184 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1185 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1186 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1187 /* Only count explicit shader flushes, not implicit ones. */
1188 ctx->num_vs_flushes++;
1189 ctx->num_ps_flushes++;
1190 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1191 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1192 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1193 ctx->num_vs_flushes++;
1194 }
1195 }
1196
1197 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH && ctx->compute_is_busy) {
1198 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1199 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
1200 ctx->num_cs_flushes++;
1201 ctx->compute_is_busy = false;
1202 }
1203
1204 if (cb_db_event) {
1205 /* CB/DB flush and invalidate (or possibly just a wait for a
1206 * meta flush) via RELEASE_MEM.
1207 *
1208 * Combine this with other cache flushes when possible; this
1209 * requires affected shaders to be idle, so do it after the
1210 * CS_PARTIAL_FLUSH before (VS/PS partial flushes are always
1211 * implied).
1212 */
1213 uint64_t va;
1214
1215 /* Do the flush (enqueue the event and wait for it). */
1216 va = ctx->wait_mem_scratch->gpu_address;
1217 ctx->wait_mem_number++;
1218
1219 /* Get GCR_CNTL fields, because the encoding is different in RELEASE_MEM. */
1220 unsigned glm_wb = G_586_GLM_WB(gcr_cntl);
1221 unsigned glm_inv = G_586_GLM_INV(gcr_cntl);
1222 unsigned glv_inv = G_586_GLV_INV(gcr_cntl);
1223 unsigned gl1_inv = G_586_GL1_INV(gcr_cntl);
1224 assert(G_586_GL2_US(gcr_cntl) == 0);
1225 assert(G_586_GL2_RANGE(gcr_cntl) == 0);
1226 assert(G_586_GL2_DISCARD(gcr_cntl) == 0);
1227 unsigned gl2_inv = G_586_GL2_INV(gcr_cntl);
1228 unsigned gl2_wb = G_586_GL2_WB(gcr_cntl);
1229 unsigned gcr_seq = G_586_SEQ(gcr_cntl);
1230
1231 gcr_cntl &= C_586_GLM_WB &
1232 C_586_GLM_INV &
1233 C_586_GLV_INV &
1234 C_586_GL1_INV &
1235 C_586_GL2_INV &
1236 C_586_GL2_WB; /* keep SEQ */
1237
1238 si_cp_release_mem(ctx, cs, cb_db_event,
1239 S_490_GLM_WB(glm_wb) |
1240 S_490_GLM_INV(glm_inv) |
1241 S_490_GLV_INV(glv_inv) |
1242 S_490_GL1_INV(gl1_inv) |
1243 S_490_GL2_INV(gl2_inv) |
1244 S_490_GL2_WB(gl2_wb) |
1245 S_490_SEQ(gcr_seq),
1246 EOP_DST_SEL_MEM,
1247 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1248 EOP_DATA_SEL_VALUE_32BIT,
1249 ctx->wait_mem_scratch, va,
1250 ctx->wait_mem_number, SI_NOT_QUERY);
1251 si_cp_wait_mem(ctx, ctx->gfx_cs, va, ctx->wait_mem_number, 0xffffffff,
1252 WAIT_REG_MEM_EQUAL);
1253 }
1254
1255 /* Ignore fields that only modify the behavior of other fields. */
1256 if (gcr_cntl & C_586_GL1_RANGE & C_586_GL2_RANGE & C_586_SEQ) {
1257 /* Flush caches and wait for the caches to assert idle.
1258 * The cache flush is executed in the ME, but the PFP waits
1259 * for completion.
1260 */
1261 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 6, 0));
1262 radeon_emit(cs, 0); /* CP_COHER_CNTL */
1263 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
1264 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
1265 radeon_emit(cs, 0); /* CP_COHER_BASE */
1266 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
1267 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
1268 radeon_emit(cs, gcr_cntl); /* GCR_CNTL */
1269 } else if (cb_db_event ||
1270 (flags & (SI_CONTEXT_VS_PARTIAL_FLUSH |
1271 SI_CONTEXT_PS_PARTIAL_FLUSH |
1272 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1273 /* We need to ensure that PFP waits as well. */
1274 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1275 radeon_emit(cs, 0);
1276 }
1277
1278 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1279 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1280 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1281 EVENT_INDEX(0));
1282 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1283 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1284 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1285 EVENT_INDEX(0));
1286 }
1287
1288 ctx->flags = 0;
1289 }
1290
1291 void si_emit_cache_flush(struct si_context *sctx)
1292 {
1293 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1294 uint32_t flags = sctx->flags;
1295
1296 if (!sctx->has_graphics) {
1297 /* Only process compute flags. */
1298 flags &= SI_CONTEXT_INV_ICACHE |
1299 SI_CONTEXT_INV_SCACHE |
1300 SI_CONTEXT_INV_VCACHE |
1301 SI_CONTEXT_INV_L2 |
1302 SI_CONTEXT_WB_L2 |
1303 SI_CONTEXT_INV_L2_METADATA |
1304 SI_CONTEXT_CS_PARTIAL_FLUSH;
1305 }
1306
1307 uint32_t cp_coher_cntl = 0;
1308 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1309 SI_CONTEXT_FLUSH_AND_INV_DB);
1310 const bool is_barrier = flush_cb_db ||
1311 /* INV_ICACHE == beginning of gfx IB. Checking
1312 * INV_ICACHE fixes corruption for DeusExMD with
1313 * compute-based culling, but I don't know why.
1314 */
1315 flags & (SI_CONTEXT_INV_ICACHE |
1316 SI_CONTEXT_PS_PARTIAL_FLUSH |
1317 SI_CONTEXT_VS_PARTIAL_FLUSH) ||
1318 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1319 sctx->compute_is_busy);
1320
1321 assert(sctx->chip_class <= GFX9);
1322
1323 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
1324 sctx->num_cb_cache_flushes++;
1325 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1326 sctx->num_db_cache_flushes++;
1327
1328 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
1329 * bit is set. An alternative way is to write SQC_CACHES, but that
1330 * doesn't seem to work reliably. Since the bug doesn't affect
1331 * correctness (it only does more work than necessary) and
1332 * the performance impact is likely negligible, there is no plan
1333 * to add a workaround for it.
1334 */
1335
1336 if (flags & SI_CONTEXT_INV_ICACHE)
1337 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
1338 if (flags & SI_CONTEXT_INV_SCACHE)
1339 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
1340
1341 if (sctx->chip_class <= GFX8) {
1342 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1343 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1344 S_0085F0_CB0_DEST_BASE_ENA(1) |
1345 S_0085F0_CB1_DEST_BASE_ENA(1) |
1346 S_0085F0_CB2_DEST_BASE_ENA(1) |
1347 S_0085F0_CB3_DEST_BASE_ENA(1) |
1348 S_0085F0_CB4_DEST_BASE_ENA(1) |
1349 S_0085F0_CB5_DEST_BASE_ENA(1) |
1350 S_0085F0_CB6_DEST_BASE_ENA(1) |
1351 S_0085F0_CB7_DEST_BASE_ENA(1);
1352
1353 /* Necessary for DCC */
1354 if (sctx->chip_class == GFX8)
1355 si_cp_release_mem(sctx, cs,
1356 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1357 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1358 EOP_DATA_SEL_DISCARD, NULL,
1359 0, 0, SI_NOT_QUERY);
1360 }
1361 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1362 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1363 S_0085F0_DB_DEST_BASE_ENA(1);
1364 }
1365
1366 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1367 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1368 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1369 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1370 }
1371 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
1372 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1373 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1374 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1375 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1376 }
1377
1378 /* Wait for shader engines to go idle.
1379 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1380 * for everything including CB/DB cache flushes.
1381 */
1382 if (!flush_cb_db) {
1383 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1384 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1385 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1386 /* Only count explicit shader flushes, not implicit ones
1387 * done by SURFACE_SYNC.
1388 */
1389 sctx->num_vs_flushes++;
1390 sctx->num_ps_flushes++;
1391 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1392 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1393 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1394 sctx->num_vs_flushes++;
1395 }
1396 }
1397
1398 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1399 sctx->compute_is_busy) {
1400 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1401 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1402 sctx->num_cs_flushes++;
1403 sctx->compute_is_busy = false;
1404 }
1405
1406 /* VGT state synchronization. */
1407 if (flags & SI_CONTEXT_VGT_FLUSH) {
1408 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1409 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1410 }
1411 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1412 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1413 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1414 }
1415
1416 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1417 * wait for idle on GFX9. We have to use a TS event.
1418 */
1419 if (sctx->chip_class == GFX9 && flush_cb_db) {
1420 uint64_t va;
1421 unsigned tc_flags, cb_db_event;
1422
1423 /* Set the CB/DB flush event. */
1424 switch (flush_cb_db) {
1425 case SI_CONTEXT_FLUSH_AND_INV_CB:
1426 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1427 break;
1428 case SI_CONTEXT_FLUSH_AND_INV_DB:
1429 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1430 break;
1431 default:
1432 /* both CB & DB */
1433 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1434 }
1435
1436 /* These are the only allowed combinations. If you need to
1437 * do multiple operations at once, do them separately.
1438 * All operations that invalidate L2 also seem to invalidate
1439 * metadata. Volatile (VOL) and WC flushes are not listed here.
1440 *
1441 * TC | TC_WB = writeback & invalidate L2 & L1
1442 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1443 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1444 * TC | TC_NC = invalidate L2 for MTYPE == NC
1445 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1446 * TCL1 = invalidate L1
1447 */
1448 tc_flags = 0;
1449
1450 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1451 tc_flags = EVENT_TC_ACTION_ENA |
1452 EVENT_TC_MD_ACTION_ENA;
1453 }
1454
1455 /* Ideally flush TC together with CB/DB. */
1456 if (flags & SI_CONTEXT_INV_L2) {
1457 /* Writeback and invalidate everything in L2 & L1. */
1458 tc_flags = EVENT_TC_ACTION_ENA |
1459 EVENT_TC_WB_ACTION_ENA;
1460
1461 /* Clear the flags. */
1462 flags &= ~(SI_CONTEXT_INV_L2 |
1463 SI_CONTEXT_WB_L2 |
1464 SI_CONTEXT_INV_VCACHE);
1465 sctx->num_L2_invalidates++;
1466 }
1467
1468 /* Do the flush (enqueue the event and wait for it). */
1469 va = sctx->wait_mem_scratch->gpu_address;
1470 sctx->wait_mem_number++;
1471
1472 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1473 EOP_DST_SEL_MEM,
1474 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1475 EOP_DATA_SEL_VALUE_32BIT,
1476 sctx->wait_mem_scratch, va,
1477 sctx->wait_mem_number, SI_NOT_QUERY);
1478 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1479 WAIT_REG_MEM_EQUAL);
1480 }
1481
1482 /* Make sure ME is idle (it executes most packets) before continuing.
1483 * This prevents read-after-write hazards between PFP and ME.
1484 */
1485 if (sctx->has_graphics &&
1486 (cp_coher_cntl ||
1487 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1488 SI_CONTEXT_INV_VCACHE |
1489 SI_CONTEXT_INV_L2 |
1490 SI_CONTEXT_WB_L2)))) {
1491 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1492 radeon_emit(cs, 0);
1493 }
1494
1495 /* GFX6-GFX8 only:
1496 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1497 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1498 *
1499 * cp_coher_cntl should contain all necessary flags except TC flags
1500 * at this point.
1501 *
1502 * GFX6-GFX7 don't support L2 write-back.
1503 */
1504 if (flags & SI_CONTEXT_INV_L2 ||
1505 (sctx->chip_class <= GFX7 &&
1506 (flags & SI_CONTEXT_WB_L2))) {
1507 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1508 * WB must be set on GFX8+ when TC_ACTION is set.
1509 */
1510 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1511 S_0085F0_TC_ACTION_ENA(1) |
1512 S_0085F0_TCL1_ACTION_ENA(1) |
1513 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1514 cp_coher_cntl = 0;
1515 sctx->num_L2_invalidates++;
1516 } else {
1517 /* L1 invalidation and L2 writeback must be done separately,
1518 * because both operations can't be done together.
1519 */
1520 if (flags & SI_CONTEXT_WB_L2) {
1521 /* WB = write-back
1522 * NC = apply to non-coherent MTYPEs
1523 * (i.e. MTYPE <= 1, which is what we use everywhere)
1524 *
1525 * WB doesn't work without NC.
1526 */
1527 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1528 S_0301F0_TC_WB_ACTION_ENA(1) |
1529 S_0301F0_TC_NC_ACTION_ENA(1));
1530 cp_coher_cntl = 0;
1531 sctx->num_L2_writebacks++;
1532 }
1533 if (flags & SI_CONTEXT_INV_VCACHE) {
1534 /* Invalidate per-CU VMEM L1. */
1535 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1536 S_0085F0_TCL1_ACTION_ENA(1));
1537 cp_coher_cntl = 0;
1538 }
1539 }
1540
1541 /* If TC flushes haven't cleared this... */
1542 if (cp_coher_cntl)
1543 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1544
1545 if (is_barrier)
1546 si_prim_discard_signal_next_compute_ib_start(sctx);
1547
1548 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1549 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1550 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1551 EVENT_INDEX(0));
1552 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1553 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1554 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1555 EVENT_INDEX(0));
1556 }
1557
1558 sctx->flags = 0;
1559 }
1560
1561 static void si_get_draw_start_count(struct si_context *sctx,
1562 const struct pipe_draw_info *info,
1563 unsigned *start, unsigned *count)
1564 {
1565 struct pipe_draw_indirect_info *indirect = info->indirect;
1566
1567 if (indirect) {
1568 unsigned indirect_count;
1569 struct pipe_transfer *transfer;
1570 unsigned begin, end;
1571 unsigned map_size;
1572 unsigned *data;
1573
1574 if (indirect->indirect_draw_count) {
1575 data = pipe_buffer_map_range(&sctx->b,
1576 indirect->indirect_draw_count,
1577 indirect->indirect_draw_count_offset,
1578 sizeof(unsigned),
1579 PIPE_TRANSFER_READ, &transfer);
1580
1581 indirect_count = *data;
1582
1583 pipe_buffer_unmap(&sctx->b, transfer);
1584 } else {
1585 indirect_count = indirect->draw_count;
1586 }
1587
1588 if (!indirect_count) {
1589 *start = *count = 0;
1590 return;
1591 }
1592
1593 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1594 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1595 indirect->offset, map_size,
1596 PIPE_TRANSFER_READ, &transfer);
1597
1598 begin = UINT_MAX;
1599 end = 0;
1600
1601 for (unsigned i = 0; i < indirect_count; ++i) {
1602 unsigned count = data[0];
1603 unsigned start = data[2];
1604
1605 if (count > 0) {
1606 begin = MIN2(begin, start);
1607 end = MAX2(end, start + count);
1608 }
1609
1610 data += indirect->stride / sizeof(unsigned);
1611 }
1612
1613 pipe_buffer_unmap(&sctx->b, transfer);
1614
1615 if (begin < end) {
1616 *start = begin;
1617 *count = end - begin;
1618 } else {
1619 *start = *count = 0;
1620 }
1621 } else {
1622 *start = info->start;
1623 *count = info->count;
1624 }
1625 }
1626
1627 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1628 enum pipe_prim_type prim, unsigned instance_count,
1629 bool primitive_restart, unsigned skip_atom_mask)
1630 {
1631 unsigned num_patches = 0;
1632
1633 si_emit_rasterizer_prim_state(sctx);
1634 if (sctx->tes_shader.cso)
1635 si_emit_derived_tess_state(sctx, info, &num_patches);
1636
1637 /* Emit state atoms. */
1638 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1639 while (mask)
1640 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1641
1642 sctx->dirty_atoms &= skip_atom_mask;
1643
1644 /* Emit states. */
1645 mask = sctx->dirty_states;
1646 while (mask) {
1647 unsigned i = u_bit_scan(&mask);
1648 struct si_pm4_state *state = sctx->queued.array[i];
1649
1650 if (!state || sctx->emitted.array[i] == state)
1651 continue;
1652
1653 si_pm4_emit(sctx, state);
1654 sctx->emitted.array[i] = state;
1655 }
1656 sctx->dirty_states = 0;
1657
1658 /* Emit draw states. */
1659 si_emit_vs_state(sctx, info);
1660 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count,
1661 primitive_restart);
1662 }
1663
1664 static bool
1665 si_all_vs_resources_read_only(struct si_context *sctx,
1666 struct pipe_resource *indexbuf)
1667 {
1668 struct radeon_winsys *ws = sctx->ws;
1669 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1670
1671 /* Index buffer. */
1672 if (indexbuf &&
1673 ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf,
1674 RADEON_USAGE_WRITE))
1675 goto has_write_reference;
1676
1677 /* Vertex buffers. */
1678 struct si_vertex_elements *velems = sctx->vertex_elements;
1679 unsigned num_velems = velems->count;
1680
1681 for (unsigned i = 0; i < num_velems; i++) {
1682 if (!((1 << i) & velems->first_vb_use_mask))
1683 continue;
1684
1685 unsigned vb_index = velems->vertex_buffer_index[i];
1686 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1687 if (!res)
1688 continue;
1689
1690 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1691 RADEON_USAGE_WRITE))
1692 goto has_write_reference;
1693 }
1694
1695 /* Constant and shader buffers. */
1696 struct si_descriptors *buffers =
1697 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1698 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1699 unsigned index = buffers->first_active_slot + i;
1700 struct pipe_resource *res =
1701 sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1702 if (!res)
1703 continue;
1704
1705 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1706 RADEON_USAGE_WRITE))
1707 goto has_write_reference;
1708 }
1709
1710 /* Samplers. */
1711 struct si_shader_selector *vs = sctx->vs_shader.cso;
1712 if (vs->info.samplers_declared) {
1713 unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
1714
1715 for (unsigned i = 0; i < num_samplers; i++) {
1716 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1717 if (!view)
1718 continue;
1719
1720 if (ws->cs_is_buffer_referenced(cs,
1721 si_resource(view->texture)->buf,
1722 RADEON_USAGE_WRITE))
1723 goto has_write_reference;
1724 }
1725 }
1726
1727 /* Images. */
1728 if (vs->info.images_declared) {
1729 unsigned num_images = util_last_bit(vs->info.images_declared);
1730
1731 for (unsigned i = 0; i < num_images; i++) {
1732 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1733 if (!res)
1734 continue;
1735
1736 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1737 RADEON_USAGE_WRITE))
1738 goto has_write_reference;
1739 }
1740 }
1741
1742 return true;
1743
1744 has_write_reference:
1745 /* If the current gfx IB has enough packets, flush it to remove write
1746 * references to buffers.
1747 */
1748 if (cs->prev_dw + cs->current.cdw > 2048) {
1749 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1750 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1751 return true;
1752 }
1753 return false;
1754 }
1755
1756 static ALWAYS_INLINE bool pd_msg(const char *s)
1757 {
1758 if (SI_PRIM_DISCARD_DEBUG)
1759 printf("PD failed: %s\n", s);
1760 return false;
1761 }
1762
1763 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1764 {
1765 struct si_context *sctx = (struct si_context *)ctx;
1766 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1767 struct pipe_resource *indexbuf = info->index.resource;
1768 unsigned dirty_tex_counter, dirty_buf_counter;
1769 enum pipe_prim_type rast_prim, prim = info->mode;
1770 unsigned index_size = info->index_size;
1771 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1772 unsigned instance_count = info->instance_count;
1773 bool primitive_restart = info->primitive_restart &&
1774 (!sctx->screen->options.prim_restart_tri_strips_only ||
1775 (prim != PIPE_PRIM_TRIANGLE_STRIP &&
1776 prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1777
1778 if (likely(!info->indirect)) {
1779 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1780 * no workaround for indirect draws, but we can at least skip
1781 * direct draws.
1782 */
1783 if (unlikely(!instance_count))
1784 return;
1785
1786 /* Handle count == 0. */
1787 if (unlikely(!info->count &&
1788 (index_size || !info->count_from_stream_output)))
1789 return;
1790 }
1791
1792 struct si_shader_selector *vs = sctx->vs_shader.cso;
1793 if (unlikely(!vs ||
1794 sctx->num_vertex_elements < vs->num_vs_inputs ||
1795 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1796 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1797 assert(0);
1798 return;
1799 }
1800
1801 /* Recompute and re-emit the texture resource states if needed. */
1802 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1803 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1804 sctx->last_dirty_tex_counter = dirty_tex_counter;
1805 sctx->framebuffer.dirty_cbufs |=
1806 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1807 sctx->framebuffer.dirty_zsbuf = true;
1808 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1809 si_update_all_texture_descriptors(sctx);
1810 }
1811
1812 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1813 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1814 sctx->last_dirty_buf_counter = dirty_buf_counter;
1815 /* Rebind all buffers unconditionally. */
1816 si_rebind_buffer(sctx, NULL);
1817 }
1818
1819 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1820
1821 /* Set the rasterization primitive type.
1822 *
1823 * This must be done after si_decompress_textures, which can call
1824 * draw_vbo recursively, and before si_update_shaders, which uses
1825 * current_rast_prim for this draw_vbo call. */
1826 if (sctx->gs_shader.cso) {
1827 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1828 rast_prim = sctx->gs_shader.cso->rast_prim;
1829 } else if (sctx->tes_shader.cso) {
1830 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
1831 rast_prim = sctx->tes_shader.cso->rast_prim;
1832 } else if (util_rast_prim_is_triangles(prim)) {
1833 rast_prim = PIPE_PRIM_TRIANGLES;
1834 } else {
1835 /* Only possibilities, POINTS, LINE*, RECTANGLES */
1836 rast_prim = prim;
1837 }
1838
1839 if (rast_prim != sctx->current_rast_prim) {
1840 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1841 util_prim_is_points_or_lines(rast_prim))
1842 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1843
1844 sctx->current_rast_prim = rast_prim;
1845 sctx->do_update_shaders = true;
1846 }
1847
1848 if (sctx->tes_shader.cso &&
1849 sctx->screen->info.has_ls_vgpr_init_bug) {
1850 /* Determine whether the LS VGPR fix should be applied.
1851 *
1852 * It is only required when num input CPs > num output CPs,
1853 * which cannot happen with the fixed function TCS. We should
1854 * also update this bit when switching from TCS to fixed
1855 * function TCS.
1856 */
1857 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1858 bool ls_vgpr_fix =
1859 tcs &&
1860 info->vertices_per_patch >
1861 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1862
1863 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1864 sctx->ls_vgpr_fix = ls_vgpr_fix;
1865 sctx->do_update_shaders = true;
1866 }
1867 }
1868
1869 if (sctx->chip_class <= GFX9 && sctx->gs_shader.cso) {
1870 /* Determine whether the GS triangle strip adjacency fix should
1871 * be applied. Rotate every other triangle if
1872 * - triangle strips with adjacency are fed to the GS and
1873 * - primitive restart is disabled (the rotation doesn't help
1874 * when the restart occurs after an odd number of triangles).
1875 */
1876 bool gs_tri_strip_adj_fix =
1877 !sctx->tes_shader.cso &&
1878 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1879 !primitive_restart;
1880
1881 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1882 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1883 sctx->do_update_shaders = true;
1884 }
1885 }
1886
1887 if (index_size) {
1888 /* Translate or upload, if needed. */
1889 /* 8-bit indices are supported on GFX8. */
1890 if (sctx->chip_class <= GFX7 && index_size == 1) {
1891 unsigned start, count, start_offset, size, offset;
1892 void *ptr;
1893
1894 si_get_draw_start_count(sctx, info, &start, &count);
1895 start_offset = start * 2;
1896 size = count * 2;
1897
1898 indexbuf = NULL;
1899 u_upload_alloc(ctx->stream_uploader, start_offset,
1900 size,
1901 si_optimal_tcc_alignment(sctx, size),
1902 &offset, &indexbuf, &ptr);
1903 if (!indexbuf)
1904 return;
1905
1906 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1907 index_offset + start,
1908 count, ptr);
1909
1910 /* info->start will be added by the drawing code */
1911 index_offset = offset - start_offset;
1912 index_size = 2;
1913 } else if (info->has_user_indices) {
1914 unsigned start_offset;
1915
1916 assert(!info->indirect);
1917 start_offset = info->start * index_size;
1918
1919 indexbuf = NULL;
1920 u_upload_data(ctx->stream_uploader, start_offset,
1921 info->count * index_size,
1922 sctx->screen->info.tcc_cache_line_size,
1923 (char*)info->index.user + start_offset,
1924 &index_offset, &indexbuf);
1925 if (!indexbuf)
1926 return;
1927
1928 /* info->start will be added by the drawing code */
1929 index_offset -= start_offset;
1930 } else if (sctx->chip_class <= GFX7 &&
1931 si_resource(indexbuf)->TC_L2_dirty) {
1932 /* GFX8 reads index buffers through TC L2, so it doesn't
1933 * need this. */
1934 sctx->flags |= SI_CONTEXT_WB_L2;
1935 si_resource(indexbuf)->TC_L2_dirty = false;
1936 }
1937 }
1938
1939 bool dispatch_prim_discard_cs = false;
1940 bool prim_discard_cs_instancing = false;
1941 unsigned original_index_size = index_size;
1942 unsigned direct_count = 0;
1943
1944 if (info->indirect) {
1945 struct pipe_draw_indirect_info *indirect = info->indirect;
1946
1947 /* Add the buffer size for memory checking in need_cs_space. */
1948 si_context_add_resource_size(sctx, indirect->buffer);
1949
1950 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1951 if (sctx->chip_class <= GFX8) {
1952 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1953 sctx->flags |= SI_CONTEXT_WB_L2;
1954 si_resource(indirect->buffer)->TC_L2_dirty = false;
1955 }
1956
1957 if (indirect->indirect_draw_count &&
1958 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1959 sctx->flags |= SI_CONTEXT_WB_L2;
1960 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1961 }
1962 }
1963 } else {
1964 /* Multiply by 3 for strips and fans to get an approximate vertex
1965 * count as triangles. */
1966 direct_count = info->count * instance_count *
1967 (prim == PIPE_PRIM_TRIANGLES ? 1 : 3);
1968 }
1969
1970 /* Determine if we can use the primitive discard compute shader. */
1971 if (si_compute_prim_discard_enabled(sctx) &&
1972 (direct_count > sctx->prim_discard_vertex_count_threshold ?
1973 (sctx->compute_num_verts_rejected += direct_count, true) : /* Add, then return true. */
1974 (sctx->compute_num_verts_ineligible += direct_count, false)) && /* Add, then return false. */
1975 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1976 (primitive_restart ?
1977 /* Supported prim types with primitive restart: */
1978 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1979 /* Disallow instancing with primitive restart: */
1980 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart")) :
1981 /* Supported prim types without primitive restart + allow instancing: */
1982 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1983 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1984 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1985 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1986 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1987 (instance_count == 1 ||
1988 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1989 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1990 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1991 (!sctx->render_cond || pd_msg("render condition")) &&
1992 /* Forced enablement ignores pipeline statistics queries. */
1993 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
1994 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
1995 pd_msg("pipestat or primgen query")) &&
1996 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
1997 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
1998 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
1999 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
2000 !rs->polygon_mode_enabled &&
2001 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
2002 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
2003 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
2004 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
2005 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
2006 !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2007 !sctx->vs_shader.cso->so.num_outputs &&
2008 #else
2009 (sctx->vs_shader.cso->prim_discard_cs_allowed || pd_msg("VS shader uses unsupported features")) &&
2010 #endif
2011 /* Check that all buffers are used for read only, because compute
2012 * dispatches can run ahead. */
2013 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) || pd_msg("write reference"))) {
2014 switch (si_prepare_prim_discard_or_split_draw(sctx, info, primitive_restart)) {
2015 case SI_PRIM_DISCARD_ENABLED:
2016 original_index_size = index_size;
2017 prim_discard_cs_instancing = instance_count > 1;
2018 dispatch_prim_discard_cs = true;
2019
2020 /* The compute shader changes/lowers the following: */
2021 prim = PIPE_PRIM_TRIANGLES;
2022 index_size = 4;
2023 instance_count = 1;
2024 primitive_restart = false;
2025 sctx->compute_num_verts_rejected -= direct_count;
2026 sctx->compute_num_verts_accepted += direct_count;
2027 break;
2028 case SI_PRIM_DISCARD_DISABLED:
2029 break;
2030 case SI_PRIM_DISCARD_DRAW_SPLIT:
2031 sctx->compute_num_verts_rejected -= direct_count;
2032 goto return_cleanup;
2033 }
2034 }
2035
2036 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
2037 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
2038 sctx->do_update_shaders = true;
2039 }
2040
2041 if (sctx->do_update_shaders && !si_update_shaders(sctx))
2042 goto return_cleanup;
2043
2044 si_need_gfx_cs_space(sctx);
2045
2046 if (sctx->bo_list_add_all_gfx_resources)
2047 si_gfx_resources_add_all_to_bo_list(sctx);
2048
2049 /* Since we've called si_context_add_resource_size for vertex buffers,
2050 * this must be called after si_need_cs_space, because we must let
2051 * need_cs_space flush before we add buffers to the buffer list.
2052 */
2053 if (!si_upload_vertex_buffer_descriptors(sctx))
2054 goto return_cleanup;
2055
2056 /* Vega10/Raven scissor bug workaround. When any context register is
2057 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
2058 * registers must be written too.
2059 */
2060 unsigned masked_atoms = 0;
2061
2062 if (sctx->screen->info.has_gfx9_scissor_bug) {
2063 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
2064
2065 if (info->count_from_stream_output ||
2066 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
2067 sctx->dirty_states & si_states_that_always_roll_context())
2068 sctx->context_roll = true;
2069 }
2070
2071 /* Use optimal packet order based on whether we need to sync the pipeline. */
2072 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
2073 SI_CONTEXT_FLUSH_AND_INV_DB |
2074 SI_CONTEXT_PS_PARTIAL_FLUSH |
2075 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
2076 /* If we have to wait for idle, set all states first, so that all
2077 * SET packets are processed in parallel with previous draw calls.
2078 * Then draw and prefetch at the end. This ensures that the time
2079 * the CUs are idle is very short.
2080 */
2081 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
2082 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
2083
2084 if (!si_upload_graphics_shader_descriptors(sctx))
2085 goto return_cleanup;
2086
2087 /* Emit all states except possibly render condition. */
2088 si_emit_all_states(sctx, info, prim, instance_count,
2089 primitive_restart, masked_atoms);
2090 sctx->emit_cache_flush(sctx);
2091 /* <-- CUs are idle here. */
2092
2093 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
2094 sctx->atoms.s.render_cond.emit(sctx);
2095
2096 if (sctx->screen->info.has_gfx9_scissor_bug &&
2097 (sctx->context_roll ||
2098 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2099 sctx->atoms.s.scissors.emit(sctx);
2100
2101 sctx->dirty_atoms = 0;
2102
2103 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2104 instance_count, dispatch_prim_discard_cs,
2105 original_index_size);
2106 /* <-- CUs are busy here. */
2107
2108 /* Start prefetches after the draw has been started. Both will run
2109 * in parallel, but starting the draw first is more important.
2110 */
2111 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2112 cik_emit_prefetch_L2(sctx, false);
2113 } else {
2114 /* If we don't wait for idle, start prefetches first, then set
2115 * states, and draw at the end.
2116 */
2117 if (sctx->flags)
2118 sctx->emit_cache_flush(sctx);
2119
2120 /* Only prefetch the API VS and VBO descriptors. */
2121 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2122 cik_emit_prefetch_L2(sctx, true);
2123
2124 if (!si_upload_graphics_shader_descriptors(sctx))
2125 goto return_cleanup;
2126
2127 si_emit_all_states(sctx, info, prim, instance_count,
2128 primitive_restart, masked_atoms);
2129
2130 if (sctx->screen->info.has_gfx9_scissor_bug &&
2131 (sctx->context_roll ||
2132 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
2133 sctx->atoms.s.scissors.emit(sctx);
2134
2135 sctx->dirty_atoms = 0;
2136
2137 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
2138 instance_count, dispatch_prim_discard_cs,
2139 original_index_size);
2140
2141 /* Prefetch the remaining shaders after the draw has been
2142 * started. */
2143 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
2144 cik_emit_prefetch_L2(sctx, false);
2145 }
2146
2147 /* Mark the displayable dcc buffer as dirty in order to update
2148 * it on the next call to si_flush_resource. */
2149 if (sctx->screen->info.use_display_dcc_with_retile_blit) {
2150 /* Don't use si_update_fb_dirtiness_after_rendering because it'll
2151 * cause unnecessary texture decompressions on each draw. */
2152 unsigned displayable_dcc_cb_mask = sctx->framebuffer.displayable_dcc_cb_mask;
2153 while (displayable_dcc_cb_mask) {
2154 unsigned i = u_bit_scan(&displayable_dcc_cb_mask);
2155 struct pipe_surface *surf = sctx->framebuffer.state.cbufs[i];
2156 struct si_texture *tex = (struct si_texture*) surf->texture;
2157 tex->displayable_dcc_dirty = true;
2158 }
2159 }
2160
2161 /* Clear the context roll flag after the draw call. */
2162 sctx->context_roll = false;
2163
2164 if (unlikely(sctx->current_saved_cs)) {
2165 si_trace_emit(sctx);
2166 si_log_draw_state(sctx, sctx->log);
2167 }
2168
2169 /* Workaround for a VGT hang when streamout is enabled.
2170 * It must be done after drawing. */
2171 if ((sctx->family == CHIP_HAWAII ||
2172 sctx->family == CHIP_TONGA ||
2173 sctx->family == CHIP_FIJI) &&
2174 si_get_strmout_en(sctx)) {
2175 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
2176 }
2177
2178 if (unlikely(sctx->decompression_enabled)) {
2179 sctx->num_decompress_calls++;
2180 } else {
2181 sctx->num_draw_calls++;
2182 if (sctx->framebuffer.state.nr_cbufs > 1)
2183 sctx->num_mrt_draw_calls++;
2184 if (primitive_restart)
2185 sctx->num_prim_restart_calls++;
2186 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
2187 sctx->num_spill_draw_calls++;
2188 }
2189
2190 return_cleanup:
2191 if (index_size && indexbuf != info->index.resource)
2192 pipe_resource_reference(&indexbuf, NULL);
2193 }
2194
2195 static void
2196 si_draw_rectangle(struct blitter_context *blitter,
2197 void *vertex_elements_cso,
2198 blitter_get_vs_func get_vs,
2199 int x1, int y1, int x2, int y2,
2200 float depth, unsigned num_instances,
2201 enum blitter_attrib_type type,
2202 const union blitter_attrib *attrib)
2203 {
2204 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
2205 struct si_context *sctx = (struct si_context*)pipe;
2206
2207 /* Pack position coordinates as signed int16. */
2208 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
2209 ((uint32_t)(y1 & 0xffff) << 16);
2210 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
2211 ((uint32_t)(y2 & 0xffff) << 16);
2212 sctx->vs_blit_sh_data[2] = fui(depth);
2213
2214 switch (type) {
2215 case UTIL_BLITTER_ATTRIB_COLOR:
2216 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
2217 sizeof(float)*4);
2218 break;
2219 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
2220 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
2221 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
2222 sizeof(attrib->texcoord));
2223 break;
2224 case UTIL_BLITTER_ATTRIB_NONE:;
2225 }
2226
2227 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
2228
2229 struct pipe_draw_info info = {};
2230 info.mode = SI_PRIM_RECTANGLE_LIST;
2231 info.count = 3;
2232 info.instance_count = num_instances;
2233
2234 /* Don't set per-stage shader pointers for VS. */
2235 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
2236 sctx->vertex_buffer_pointer_dirty = false;
2237 sctx->vertex_buffer_user_sgprs_dirty = false;
2238
2239 si_draw_vbo(pipe, &info);
2240 }
2241
2242 void si_trace_emit(struct si_context *sctx)
2243 {
2244 struct radeon_cmdbuf *cs = sctx->gfx_cs;
2245 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
2246
2247 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
2248 0, 4, V_370_MEM, V_370_ME, &trace_id);
2249
2250 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
2251 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
2252
2253 if (sctx->log)
2254 u_log_flush(sctx->log);
2255 }
2256
2257 void si_init_draw_functions(struct si_context *sctx)
2258 {
2259 sctx->b.draw_vbo = si_draw_vbo;
2260
2261 sctx->blitter->draw_rectangle = si_draw_rectangle;
2262
2263 si_init_ia_multi_vgt_param_table(sctx);
2264 }