projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
amd/common: use generated register header
[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "util/u_index_modify.h"
29 #include "util/u_log.h"
30 #include "util/u_upload_mgr.h"
31 #include "util/u_prim.h"
32 #include "util/u_suballoc.h"
33
34 #include "ac_debug.h"
35
36 /* special primitive types */
37 #define SI_PRIM_RECTANGLE_LIST PIPE_PRIM_MAX
38
39 static unsigned si_conv_pipe_prim(unsigned mode)
40 {
41 static const unsigned prim_conv[] = {
42 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
43 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
44 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
45 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
46 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
47 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
48 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
49 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
50 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
51 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
52 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
53 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
54 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
55 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
56 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
57 [SI_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
58 };
59 assert(mode < ARRAY_SIZE(prim_conv));
60 return prim_conv[mode];
61 }
62
63 /**
64 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
65 * LS.LDS_SIZE is shared by all 3 shader stages.
66 *
67 * The information about LDS and other non-compile-time parameters is then
68 * written to userdata SGPRs.
69 */
70 static void si_emit_derived_tess_state(struct si_context *sctx,
71 const struct pipe_draw_info *info,
72 unsigned *num_patches)
73 {
74 struct radeon_cmdbuf *cs = sctx->gfx_cs;
75 struct si_shader *ls_current;
76 struct si_shader_selector *ls;
77 /* The TES pointer will only be used for sctx->last_tcs.
78 * It would be wrong to think that TCS = TES. */
79 struct si_shader_selector *tcs =
80 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
81 unsigned tess_uses_primid = sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id;
82 bool has_primid_instancing_bug = sctx->chip_class == GFX6 &&
83 sctx->screen->info.max_se == 1;
84 unsigned tes_sh_base = sctx->shader_pointers.sh_base[PIPE_SHADER_TESS_EVAL];
85 unsigned num_tcs_input_cp = info->vertices_per_patch;
86 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
87 unsigned num_tcs_patch_outputs;
88 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
89 unsigned input_patch_size, output_patch_size, output_patch0_offset;
90 unsigned perpatch_output_offset, lds_size;
91 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
92 unsigned offchip_layout, hardware_lds_size, ls_hs_config;
93
94 /* Since GFX9 has merged LS-HS in the TCS state, set LS = TCS. */
95 if (sctx->chip_class >= GFX9) {
96 if (sctx->tcs_shader.cso)
97 ls_current = sctx->tcs_shader.current;
98 else
99 ls_current = sctx->fixed_func_tcs_shader.current;
100
101 ls = ls_current->key.part.tcs.ls;
102 } else {
103 ls_current = sctx->vs_shader.current;
104 ls = sctx->vs_shader.cso;
105 }
106
107 if (sctx->last_ls == ls_current &&
108 sctx->last_tcs == tcs &&
109 sctx->last_tes_sh_base == tes_sh_base &&
110 sctx->last_num_tcs_input_cp == num_tcs_input_cp &&
111 (!has_primid_instancing_bug ||
112 (sctx->last_tess_uses_primid == tess_uses_primid))) {
113 *num_patches = sctx->last_num_patches;
114 return;
115 }
116
117 sctx->last_ls = ls_current;
118 sctx->last_tcs = tcs;
119 sctx->last_tes_sh_base = tes_sh_base;
120 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
121 sctx->last_tess_uses_primid = tess_uses_primid;
122
123 /* This calculates how shader inputs and outputs among VS, TCS, and TES
124 * are laid out in LDS. */
125 num_tcs_inputs = util_last_bit64(ls->outputs_written);
126
127 if (sctx->tcs_shader.cso) {
128 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
129 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
130 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
131 } else {
132 /* No TCS. Route varyings from LS to TES. */
133 num_tcs_outputs = num_tcs_inputs;
134 num_tcs_output_cp = num_tcs_input_cp;
135 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
136 }
137
138 input_vertex_size = ls->lshs_vertex_stride;
139 output_vertex_size = num_tcs_outputs * 16;
140
141 input_patch_size = num_tcs_input_cp * input_vertex_size;
142
143 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
144 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
145
146 /* Ensure that we only need one wave per SIMD so we don't need to check
147 * resource usage. Also ensures that the number of tcs in and out
148 * vertices per threadgroup are at most 256.
149 */
150 unsigned max_verts_per_patch = MAX2(num_tcs_input_cp, num_tcs_output_cp);
151 *num_patches = 256 / max_verts_per_patch;
152
153 /* Make sure that the data fits in LDS. This assumes the shaders only
154 * use LDS for the inputs and outputs.
155 *
156 * While GFX7 can use 64K per threadgroup, there is a hang on Stoney
157 * with 2 CUs if we use more than 32K. The closed Vulkan driver also
158 * uses 32K at most on all GCN chips.
159 */
160 hardware_lds_size = 32768;
161 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
162 output_patch_size));
163
164 /* Make sure the output data fits in the offchip buffer */
165 *num_patches = MIN2(*num_patches,
166 (sctx->screen->tess_offchip_block_dw_size * 4) /
167 output_patch_size);
168
169 /* Not necessary for correctness, but improves performance.
170 * The hardware can do more, but the radeonsi shader constant is
171 * limited to 6 bits.
172 */
173 *num_patches = MIN2(*num_patches, 63); /* triangles: 3 full waves except 3 lanes */
174
175 /* When distributed tessellation is unsupported, switch between SEs
176 * at a higher frequency to compensate for it.
177 */
178 if (!sctx->screen->has_distributed_tess && sctx->screen->info.max_se > 1)
179 *num_patches = MIN2(*num_patches, 16); /* recommended */
180
181 /* Make sure that vector lanes are reasonably occupied. It probably
182 * doesn't matter much because this is LS-HS, and TES is likely to
183 * occupy significantly more CUs.
184 */
185 unsigned temp_verts_per_tg = *num_patches * max_verts_per_patch;
186 if (temp_verts_per_tg > 64 && temp_verts_per_tg % 64 < 48)
187 *num_patches = (temp_verts_per_tg & ~63) / max_verts_per_patch;
188
189 if (sctx->chip_class == GFX6) {
190 /* GFX6 bug workaround, related to power management. Limit LS-HS
191 * threadgroups to only one wave.
192 */
193 unsigned one_wave = 64 / max_verts_per_patch;
194 *num_patches = MIN2(*num_patches, one_wave);
195 }
196
197 /* The VGT HS block increments the patch ID unconditionally
198 * within a single threadgroup. This results in incorrect
199 * patch IDs when instanced draws are used.
200 *
201 * The intended solution is to restrict threadgroups to
202 * a single instance by setting SWITCH_ON_EOI, which
203 * should cause IA to split instances up. However, this
204 * doesn't work correctly on GFX6 when there is no other
205 * SE to switch to.
206 */
207 if (has_primid_instancing_bug && tess_uses_primid)
208 *num_patches = 1;
209
210 sctx->last_num_patches = *num_patches;
211
212 output_patch0_offset = input_patch_size * *num_patches;
213 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
214
215 /* Compute userdata SGPRs. */
216 assert(((input_vertex_size / 4) & ~0xff) == 0);
217 assert(((output_vertex_size / 4) & ~0xff) == 0);
218 assert(((input_patch_size / 4) & ~0x1fff) == 0);
219 assert(((output_patch_size / 4) & ~0x1fff) == 0);
220 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
221 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
222 assert(num_tcs_input_cp <= 32);
223 assert(num_tcs_output_cp <= 32);
224
225 uint64_t ring_va = si_resource(sctx->tess_rings)->gpu_address;
226 assert((ring_va & u_bit_consecutive(0, 19)) == 0);
227
228 tcs_in_layout = S_VS_STATE_LS_OUT_PATCH_SIZE(input_patch_size / 4) |
229 S_VS_STATE_LS_OUT_VERTEX_SIZE(input_vertex_size / 4);
230 tcs_out_layout = (output_patch_size / 4) |
231 (num_tcs_input_cp << 13) |
232 ring_va;
233 tcs_out_offsets = (output_patch0_offset / 16) |
234 ((perpatch_output_offset / 16) << 16);
235 offchip_layout = *num_patches |
236 (num_tcs_output_cp << 6) |
237 (pervertex_output_patch_size * *num_patches << 12);
238
239 /* Compute the LDS size. */
240 lds_size = output_patch0_offset + output_patch_size * *num_patches;
241
242 if (sctx->chip_class >= GFX7) {
243 assert(lds_size <= 65536);
244 lds_size = align(lds_size, 512) / 512;
245 } else {
246 assert(lds_size <= 32768);
247 lds_size = align(lds_size, 256) / 256;
248 }
249
250 /* Set SI_SGPR_VS_STATE_BITS. */
251 sctx->current_vs_state &= C_VS_STATE_LS_OUT_PATCH_SIZE &
252 C_VS_STATE_LS_OUT_VERTEX_SIZE;
253 sctx->current_vs_state |= tcs_in_layout;
254
255 if (sctx->chip_class >= GFX9) {
256 unsigned hs_rsrc2 = ls_current->config.rsrc2 |
257 S_00B42C_LDS_SIZE(lds_size);
258
259 radeon_set_sh_reg(cs, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, hs_rsrc2);
260
261 /* Set userdata SGPRs for merged LS-HS. */
262 radeon_set_sh_reg_seq(cs,
263 R_00B430_SPI_SHADER_USER_DATA_LS_0 +
264 GFX9_SGPR_TCS_OFFCHIP_LAYOUT * 4, 3);
265 radeon_emit(cs, offchip_layout);
266 radeon_emit(cs, tcs_out_offsets);
267 radeon_emit(cs, tcs_out_layout);
268 } else {
269 unsigned ls_rsrc2 = ls_current->config.rsrc2;
270
271 si_multiwave_lds_size_workaround(sctx->screen, &lds_size);
272 ls_rsrc2 |= S_00B52C_LDS_SIZE(lds_size);
273
274 /* Due to a hw bug, RSRC2_LS must be written twice with another
275 * LS register written in between. */
276 if (sctx->chip_class == GFX7 && sctx->family != CHIP_HAWAII)
277 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
278 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
279 radeon_emit(cs, ls_current->config.rsrc1);
280 radeon_emit(cs, ls_rsrc2);
281
282 /* Set userdata SGPRs for TCS. */
283 radeon_set_sh_reg_seq(cs,
284 R_00B430_SPI_SHADER_USER_DATA_HS_0 + GFX6_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
285 radeon_emit(cs, offchip_layout);
286 radeon_emit(cs, tcs_out_offsets);
287 radeon_emit(cs, tcs_out_layout);
288 radeon_emit(cs, tcs_in_layout);
289 }
290
291 /* Set userdata SGPRs for TES. */
292 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TES_OFFCHIP_LAYOUT * 4, 2);
293 radeon_emit(cs, offchip_layout);
294 radeon_emit(cs, ring_va);
295
296 ls_hs_config = S_028B58_NUM_PATCHES(*num_patches) |
297 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
298 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
299
300 if (sctx->last_ls_hs_config != ls_hs_config) {
301 if (sctx->chip_class >= GFX7) {
302 radeon_set_context_reg_idx(cs, R_028B58_VGT_LS_HS_CONFIG, 2,
303 ls_hs_config);
304 } else {
305 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG,
306 ls_hs_config);
307 }
308 sctx->last_ls_hs_config = ls_hs_config;
309 sctx->context_roll = true;
310 }
311 }
312
313 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info,
314 enum pipe_prim_type prim)
315 {
316 switch (prim) {
317 case PIPE_PRIM_PATCHES:
318 return info->count / info->vertices_per_patch;
319 case PIPE_PRIM_POLYGON:
320 return info->count >= 3;
321 case SI_PRIM_RECTANGLE_LIST:
322 return info->count / 3;
323 default:
324 return u_decomposed_prims_for_vertices(prim, info->count);
325 }
326 }
327
328 static unsigned
329 si_get_init_multi_vgt_param(struct si_screen *sscreen,
330 union si_vgt_param_key *key)
331 {
332 STATIC_ASSERT(sizeof(union si_vgt_param_key) == 4);
333 unsigned max_primgroup_in_wave = 2;
334
335 /* SWITCH_ON_EOP(0) is always preferable. */
336 bool wd_switch_on_eop = false;
337 bool ia_switch_on_eop = false;
338 bool ia_switch_on_eoi = false;
339 bool partial_vs_wave = false;
340 bool partial_es_wave = false;
341
342 if (key->u.uses_tess) {
343 /* SWITCH_ON_EOI must be set if PrimID is used. */
344 if (key->u.tess_uses_prim_id)
345 ia_switch_on_eoi = true;
346
347 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
348 if ((sscreen->info.family == CHIP_TAHITI ||
349 sscreen->info.family == CHIP_PITCAIRN ||
350 sscreen->info.family == CHIP_BONAIRE) &&
351 key->u.uses_gs)
352 partial_vs_wave = true;
353
354 /* Needed for 028B6C_DISTRIBUTION_MODE != 0. (implies >= GFX8) */
355 if (sscreen->has_distributed_tess) {
356 if (key->u.uses_gs) {
357 if (sscreen->info.chip_class == GFX8)
358 partial_es_wave = true;
359 } else {
360 partial_vs_wave = true;
361 }
362 }
363 }
364
365 /* This is a hardware requirement. */
366 if (key->u.line_stipple_enabled ||
367 (sscreen->debug_flags & DBG(SWITCH_ON_EOP))) {
368 ia_switch_on_eop = true;
369 wd_switch_on_eop = true;
370 }
371
372 if (sscreen->info.chip_class >= GFX7) {
373 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
374 * 4 shader engines. Set 1 to pass the assertion below.
375 * The other cases are hardware requirements.
376 *
377 * Polaris supports primitive restart with WD_SWITCH_ON_EOP=0
378 * for points, line strips, and tri strips.
379 */
380 if (sscreen->info.max_se <= 2 ||
381 key->u.prim == PIPE_PRIM_POLYGON ||
382 key->u.prim == PIPE_PRIM_LINE_LOOP ||
383 key->u.prim == PIPE_PRIM_TRIANGLE_FAN ||
384 key->u.prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
385 (key->u.primitive_restart &&
386 (sscreen->info.family < CHIP_POLARIS10 ||
387 (key->u.prim != PIPE_PRIM_POINTS &&
388 key->u.prim != PIPE_PRIM_LINE_STRIP &&
389 key->u.prim != PIPE_PRIM_TRIANGLE_STRIP))) ||
390 key->u.count_from_stream_output)
391 wd_switch_on_eop = true;
392
393 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
394 * We don't know that for indirect drawing, so treat it as
395 * always problematic. */
396 if (sscreen->info.family == CHIP_HAWAII &&
397 key->u.uses_instancing)
398 wd_switch_on_eop = true;
399
400 /* Performance recommendation for 4 SE Gfx7-8 parts if
401 * instances are smaller than a primgroup.
402 * Assume indirect draws always use small instances.
403 * This is needed for good VS wave utilization.
404 */
405 if (sscreen->info.chip_class <= GFX8 &&
406 sscreen->info.max_se == 4 &&
407 key->u.multi_instances_smaller_than_primgroup)
408 wd_switch_on_eop = true;
409
410 /* Required on GFX7 and later. */
411 if (sscreen->info.max_se == 4 && !wd_switch_on_eop)
412 ia_switch_on_eoi = true;
413
414 /* HW engineers suggested that PARTIAL_VS_WAVE_ON should be set
415 * to work around a GS hang.
416 */
417 if (key->u.uses_gs &&
418 (sscreen->info.family == CHIP_TONGA ||
419 sscreen->info.family == CHIP_FIJI ||
420 sscreen->info.family == CHIP_POLARIS10 ||
421 sscreen->info.family == CHIP_POLARIS11 ||
422 sscreen->info.family == CHIP_POLARIS12 ||
423 sscreen->info.family == CHIP_VEGAM))
424 partial_vs_wave = true;
425
426 /* Required by Hawaii and, for some special cases, by GFX8. */
427 if (ia_switch_on_eoi &&
428 (sscreen->info.family == CHIP_HAWAII ||
429 (sscreen->info.chip_class == GFX8 &&
430 (key->u.uses_gs || max_primgroup_in_wave != 2))))
431 partial_vs_wave = true;
432
433 /* Instancing bug on Bonaire. */
434 if (sscreen->info.family == CHIP_BONAIRE && ia_switch_on_eoi &&
435 key->u.uses_instancing)
436 partial_vs_wave = true;
437
438 /* This only applies to Polaris10 and later 4 SE chips.
439 * wd_switch_on_eop is already true on all other chips.
440 */
441 if (!wd_switch_on_eop && key->u.primitive_restart)
442 partial_vs_wave = true;
443
444 /* If the WD switch is false, the IA switch must be false too. */
445 assert(wd_switch_on_eop || !ia_switch_on_eop);
446 }
447
448 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
449 if (sscreen->info.chip_class <= GFX8 && ia_switch_on_eoi)
450 partial_es_wave = true;
451
452 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
453 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
454 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
455 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
456 S_028AA8_WD_SWITCH_ON_EOP(sscreen->info.chip_class >= GFX7 ? wd_switch_on_eop : 0) |
457 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
458 S_028AA8_MAX_PRIMGRP_IN_WAVE(sscreen->info.chip_class == GFX8 ?
459 max_primgroup_in_wave : 0) |
460 S_030960_EN_INST_OPT_BASIC(sscreen->info.chip_class >= GFX9) |
461 S_030960_EN_INST_OPT_ADV(sscreen->info.chip_class >= GFX9);
462 }
463
464 static void si_init_ia_multi_vgt_param_table(struct si_context *sctx)
465 {
466 for (int prim = 0; prim <= SI_PRIM_RECTANGLE_LIST; prim++)
467 for (int uses_instancing = 0; uses_instancing < 2; uses_instancing++)
468 for (int multi_instances = 0; multi_instances < 2; multi_instances++)
469 for (int primitive_restart = 0; primitive_restart < 2; primitive_restart++)
470 for (int count_from_so = 0; count_from_so < 2; count_from_so++)
471 for (int line_stipple = 0; line_stipple < 2; line_stipple++)
472 for (int uses_tess = 0; uses_tess < 2; uses_tess++)
473 for (int tess_uses_primid = 0; tess_uses_primid < 2; tess_uses_primid++)
474 for (int uses_gs = 0; uses_gs < 2; uses_gs++) {
475 union si_vgt_param_key key;
476
477 key.index = 0;
478 key.u.prim = prim;
479 key.u.uses_instancing = uses_instancing;
480 key.u.multi_instances_smaller_than_primgroup = multi_instances;
481 key.u.primitive_restart = primitive_restart;
482 key.u.count_from_stream_output = count_from_so;
483 key.u.line_stipple_enabled = line_stipple;
484 key.u.uses_tess = uses_tess;
485 key.u.tess_uses_prim_id = tess_uses_primid;
486 key.u.uses_gs = uses_gs;
487
488 sctx->ia_multi_vgt_param[key.index] =
489 si_get_init_multi_vgt_param(sctx->screen, &key);
490 }
491 }
492
493 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
494 const struct pipe_draw_info *info,
495 enum pipe_prim_type prim,
496 unsigned num_patches,
497 unsigned instance_count,
498 bool primitive_restart)
499 {
500 union si_vgt_param_key key = sctx->ia_multi_vgt_param_key;
501 unsigned primgroup_size;
502 unsigned ia_multi_vgt_param;
503
504 if (sctx->tes_shader.cso) {
505 primgroup_size = num_patches; /* must be a multiple of NUM_PATCHES */
506 } else if (sctx->gs_shader.cso) {
507 primgroup_size = 64; /* recommended with a GS */
508 } else {
509 primgroup_size = 128; /* recommended without a GS and tess */
510 }
511
512 key.u.prim = prim;
513 key.u.uses_instancing = info->indirect || instance_count > 1;
514 key.u.multi_instances_smaller_than_primgroup =
515 info->indirect ||
516 (instance_count > 1 &&
517 (info->count_from_stream_output ||
518 si_num_prims_for_vertices(info, prim) < primgroup_size));
519 key.u.primitive_restart = primitive_restart;
520 key.u.count_from_stream_output = info->count_from_stream_output != NULL;
521
522 ia_multi_vgt_param = sctx->ia_multi_vgt_param[key.index] |
523 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1);
524
525 if (sctx->gs_shader.cso) {
526 /* GS requirement. */
527 if (sctx->chip_class <= GFX8 &&
528 SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
529 ia_multi_vgt_param |= S_028AA8_PARTIAL_ES_WAVE_ON(1);
530
531 /* GS hw bug with single-primitive instances and SWITCH_ON_EOI.
532 * The hw doc says all multi-SE chips are affected, but Vulkan
533 * only applies it to Hawaii. Do what Vulkan does.
534 */
535 if (sctx->family == CHIP_HAWAII &&
536 G_028AA8_SWITCH_ON_EOI(ia_multi_vgt_param) &&
537 (info->indirect ||
538 (instance_count > 1 &&
539 (info->count_from_stream_output ||
540 si_num_prims_for_vertices(info, prim) <= 1))))
541 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
542 }
543
544 return ia_multi_vgt_param;
545 }
546
547 /* rast_prim is the primitive type after GS. */
548 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
549 {
550 struct radeon_cmdbuf *cs = sctx->gfx_cs;
551 enum pipe_prim_type rast_prim = sctx->current_rast_prim;
552 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
553
554 /* Skip this if not rendering lines. */
555 if (!util_prim_is_lines(rast_prim))
556 return;
557
558 if (rast_prim == sctx->last_rast_prim &&
559 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
560 return;
561
562 /* For lines, reset the stipple pattern at each primitive. Otherwise,
563 * reset the stipple pattern at each packet (line strips, line loops).
564 */
565 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
566 rs->pa_sc_line_stipple |
567 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 : 2));
568
569 sctx->last_rast_prim = rast_prim;
570 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
571 sctx->context_roll = true;
572 }
573
574 static void si_emit_vs_state(struct si_context *sctx,
575 const struct pipe_draw_info *info)
576 {
577 sctx->current_vs_state &= C_VS_STATE_INDEXED;
578 sctx->current_vs_state |= S_VS_STATE_INDEXED(!!info->index_size);
579
580 if (sctx->num_vs_blit_sgprs) {
581 /* Re-emit the state after we leave u_blitter. */
582 sctx->last_vs_state = ~0;
583 return;
584 }
585
586 if (sctx->current_vs_state != sctx->last_vs_state) {
587 struct radeon_cmdbuf *cs = sctx->gfx_cs;
588
589 /* For the API vertex shader (VS_STATE_INDEXED). */
590 radeon_set_sh_reg(cs,
591 sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX] +
592 SI_SGPR_VS_STATE_BITS * 4,
593 sctx->current_vs_state);
594
595 /* For vertex color clamping, which is done in the last stage
596 * before the rasterizer. */
597 if (sctx->gs_shader.cso || sctx->tes_shader.cso) {
598 /* GS copy shader or TES if GS is missing. */
599 radeon_set_sh_reg(cs,
600 R_00B130_SPI_SHADER_USER_DATA_VS_0 +
601 SI_SGPR_VS_STATE_BITS * 4,
602 sctx->current_vs_state);
603 }
604
605 sctx->last_vs_state = sctx->current_vs_state;
606 }
607 }
608
609 static inline bool si_prim_restart_index_changed(struct si_context *sctx,
610 bool primitive_restart,
611 unsigned restart_index)
612 {
613 return primitive_restart &&
614 (restart_index != sctx->last_restart_index ||
615 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN);
616 }
617
618 static void si_emit_draw_registers(struct si_context *sctx,
619 const struct pipe_draw_info *info,
620 enum pipe_prim_type prim,
621 unsigned num_patches,
622 unsigned instance_count,
623 bool primitive_restart)
624 {
625 struct radeon_cmdbuf *cs = sctx->gfx_cs;
626 unsigned vgt_prim = si_conv_pipe_prim(prim);
627 unsigned ia_multi_vgt_param;
628
629 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, prim, num_patches,
630 instance_count, primitive_restart);
631
632 /* Draw state. */
633 if (ia_multi_vgt_param != sctx->last_multi_vgt_param) {
634 if (sctx->chip_class >= GFX9)
635 radeon_set_uconfig_reg_idx(cs, sctx->screen,
636 R_030960_IA_MULTI_VGT_PARAM, 4,
637 ia_multi_vgt_param);
638 else if (sctx->chip_class >= GFX7)
639 radeon_set_context_reg_idx(cs, R_028AA8_IA_MULTI_VGT_PARAM, 1, ia_multi_vgt_param);
640 else
641 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
642
643 sctx->last_multi_vgt_param = ia_multi_vgt_param;
644 }
645 if (vgt_prim != sctx->last_prim) {
646 if (sctx->chip_class >= GFX7)
647 radeon_set_uconfig_reg_idx(cs, sctx->screen,
648 R_030908_VGT_PRIMITIVE_TYPE, 1, vgt_prim);
649 else
650 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, vgt_prim);
651
652 sctx->last_prim = vgt_prim;
653 }
654
655 /* Primitive restart. */
656 if (primitive_restart != sctx->last_primitive_restart_en) {
657 if (sctx->chip_class >= GFX9)
658 radeon_set_uconfig_reg(cs, R_03092C_VGT_MULTI_PRIM_IB_RESET_EN,
659 primitive_restart);
660 else
661 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN,
662 primitive_restart);
663
664 sctx->last_primitive_restart_en = primitive_restart;
665
666 }
667 if (si_prim_restart_index_changed(sctx, primitive_restart, info->restart_index)) {
668 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
669 info->restart_index);
670 sctx->last_restart_index = info->restart_index;
671 sctx->context_roll = true;
672 }
673 }
674
675 static void si_emit_draw_packets(struct si_context *sctx,
676 const struct pipe_draw_info *info,
677 struct pipe_resource *indexbuf,
678 unsigned index_size,
679 unsigned index_offset,
680 unsigned instance_count,
681 bool dispatch_prim_discard_cs,
682 unsigned original_index_size)
683 {
684 struct pipe_draw_indirect_info *indirect = info->indirect;
685 struct radeon_cmdbuf *cs = sctx->gfx_cs;
686 unsigned sh_base_reg = sctx->shader_pointers.sh_base[PIPE_SHADER_VERTEX];
687 bool render_cond_bit = sctx->render_cond && !sctx->render_cond_force_off;
688 uint32_t index_max_size = 0;
689 uint64_t index_va = 0;
690
691 if (info->count_from_stream_output) {
692 struct si_streamout_target *t =
693 (struct si_streamout_target*)info->count_from_stream_output;
694
695 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
696 t->stride_in_dw);
697 si_cp_copy_data(sctx, sctx->gfx_cs,
698 COPY_DATA_REG, NULL,
699 R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2,
700 COPY_DATA_SRC_MEM, t->buf_filled_size,
701 t->buf_filled_size_offset);
702 }
703
704 /* draw packet */
705 if (index_size) {
706 if (index_size != sctx->last_index_size) {
707 unsigned index_type;
708
709 /* index type */
710 switch (index_size) {
711 case 1:
712 index_type = V_028A7C_VGT_INDEX_8;
713 break;
714 case 2:
715 index_type = V_028A7C_VGT_INDEX_16 |
716 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
717 V_028A7C_VGT_DMA_SWAP_16_BIT : 0);
718 break;
719 case 4:
720 index_type = V_028A7C_VGT_INDEX_32 |
721 (SI_BIG_ENDIAN && sctx->chip_class <= GFX7 ?
722 V_028A7C_VGT_DMA_SWAP_32_BIT : 0);
723 break;
724 default:
725 assert(!"unreachable");
726 return;
727 }
728
729 if (sctx->chip_class >= GFX9) {
730 radeon_set_uconfig_reg_idx(cs, sctx->screen,
731 R_03090C_VGT_INDEX_TYPE, 2,
732 index_type);
733 } else {
734 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
735 radeon_emit(cs, index_type);
736 }
737
738 sctx->last_index_size = index_size;
739 }
740
741 if (original_index_size) {
742 index_max_size = (indexbuf->width0 - index_offset) /
743 original_index_size;
744 index_va = si_resource(indexbuf)->gpu_address + index_offset;
745
746 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
747 si_resource(indexbuf),
748 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
749 }
750 } else {
751 /* On GFX7 and later, non-indexed draws overwrite VGT_INDEX_TYPE,
752 * so the state must be re-emitted before the next indexed draw.
753 */
754 if (sctx->chip_class >= GFX7)
755 sctx->last_index_size = -1;
756 }
757
758 if (indirect) {
759 uint64_t indirect_va = si_resource(indirect->buffer)->gpu_address;
760
761 assert(indirect_va % 8 == 0);
762
763 si_invalidate_draw_sh_constants(sctx);
764
765 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
766 radeon_emit(cs, 1);
767 radeon_emit(cs, indirect_va);
768 radeon_emit(cs, indirect_va >> 32);
769
770 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
771 si_resource(indirect->buffer),
772 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
773
774 unsigned di_src_sel = index_size ? V_0287F0_DI_SRC_SEL_DMA
775 : V_0287F0_DI_SRC_SEL_AUTO_INDEX;
776
777 assert(indirect->offset % 4 == 0);
778
779 if (index_size) {
780 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
781 radeon_emit(cs, index_va);
782 radeon_emit(cs, index_va >> 32);
783
784 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
785 radeon_emit(cs, index_max_size);
786 }
787
788 if (!sctx->screen->has_draw_indirect_multi) {
789 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT
790 : PKT3_DRAW_INDIRECT,
791 3, render_cond_bit));
792 radeon_emit(cs, indirect->offset);
793 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
794 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
795 radeon_emit(cs, di_src_sel);
796 } else {
797 uint64_t count_va = 0;
798
799 if (indirect->indirect_draw_count) {
800 struct si_resource *params_buf =
801 si_resource(indirect->indirect_draw_count);
802
803 radeon_add_to_buffer_list(
804 sctx, sctx->gfx_cs, params_buf,
805 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
806
807 count_va = params_buf->gpu_address + indirect->indirect_draw_count_offset;
808 }
809
810 radeon_emit(cs, PKT3(index_size ? PKT3_DRAW_INDEX_INDIRECT_MULTI :
811 PKT3_DRAW_INDIRECT_MULTI,
812 8, render_cond_bit));
813 radeon_emit(cs, indirect->offset);
814 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
815 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
816 radeon_emit(cs, ((sh_base_reg + SI_SGPR_DRAWID * 4 - SI_SH_REG_OFFSET) >> 2) |
817 S_2C3_DRAW_INDEX_ENABLE(1) |
818 S_2C3_COUNT_INDIRECT_ENABLE(!!indirect->indirect_draw_count));
819 radeon_emit(cs, indirect->draw_count);
820 radeon_emit(cs, count_va);
821 radeon_emit(cs, count_va >> 32);
822 radeon_emit(cs, indirect->stride);
823 radeon_emit(cs, di_src_sel);
824 }
825 } else {
826 int base_vertex;
827
828 if (sctx->last_instance_count == SI_INSTANCE_COUNT_UNKNOWN ||
829 sctx->last_instance_count != instance_count) {
830 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
831 radeon_emit(cs, instance_count);
832 sctx->last_instance_count = instance_count;
833 }
834
835 /* Base vertex and start instance. */
836 base_vertex = original_index_size ? info->index_bias : info->start;
837
838 if (sctx->num_vs_blit_sgprs) {
839 /* Re-emit draw constants after we leave u_blitter. */
840 si_invalidate_draw_sh_constants(sctx);
841
842 /* Blit VS doesn't use BASE_VERTEX, START_INSTANCE, and DRAWID. */
843 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_VS_BLIT_DATA * 4,
844 sctx->num_vs_blit_sgprs);
845 radeon_emit_array(cs, sctx->vs_blit_sh_data,
846 sctx->num_vs_blit_sgprs);
847 } else if (base_vertex != sctx->last_base_vertex ||
848 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
849 info->start_instance != sctx->last_start_instance ||
850 info->drawid != sctx->last_drawid ||
851 sh_base_reg != sctx->last_sh_base_reg) {
852 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 3);
853 radeon_emit(cs, base_vertex);
854 radeon_emit(cs, info->start_instance);
855 radeon_emit(cs, info->drawid);
856
857 sctx->last_base_vertex = base_vertex;
858 sctx->last_start_instance = info->start_instance;
859 sctx->last_drawid = info->drawid;
860 sctx->last_sh_base_reg = sh_base_reg;
861 }
862
863 if (index_size) {
864 if (dispatch_prim_discard_cs) {
865 index_va += info->start * original_index_size;
866 index_max_size = MIN2(index_max_size, info->count);
867
868 si_dispatch_prim_discard_cs_and_draw(sctx, info,
869 original_index_size,
870 base_vertex,
871 index_va, index_max_size);
872 return;
873 }
874
875 index_va += info->start * index_size;
876
877 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
878 radeon_emit(cs, index_max_size);
879 radeon_emit(cs, index_va);
880 radeon_emit(cs, index_va >> 32);
881 radeon_emit(cs, info->count);
882 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
883 } else {
884 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
885 radeon_emit(cs, info->count);
886 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
887 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
888 }
889 }
890 }
891
892 void si_emit_surface_sync(struct si_context *sctx, struct radeon_cmdbuf *cs,
893 unsigned cp_coher_cntl)
894 {
895 bool compute_ib = !sctx->has_graphics ||
896 cs == sctx->prim_discard_compute_cs;
897
898 if (sctx->chip_class >= GFX9 || compute_ib) {
899 /* Flush caches and wait for the caches to assert idle. */
900 radeon_emit(cs, PKT3(PKT3_ACQUIRE_MEM, 5, 0));
901 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
902 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
903 radeon_emit(cs, 0xffffff); /* CP_COHER_SIZE_HI */
904 radeon_emit(cs, 0); /* CP_COHER_BASE */
905 radeon_emit(cs, 0); /* CP_COHER_BASE_HI */
906 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
907 } else {
908 /* ACQUIRE_MEM is only required on a compute ring. */
909 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
910 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
911 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
912 radeon_emit(cs, 0); /* CP_COHER_BASE */
913 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
914 }
915
916 /* ACQUIRE_MEM has an implicit context roll if the current context
917 * is busy. */
918 if (!compute_ib)
919 sctx->context_roll = true;
920 }
921
922 void si_prim_discard_signal_next_compute_ib_start(struct si_context *sctx)
923 {
924 if (!si_compute_prim_discard_enabled(sctx))
925 return;
926
927 if (!sctx->barrier_buf) {
928 u_suballocator_alloc(sctx->allocator_zeroed_memory, 4, 4,
929 &sctx->barrier_buf_offset,
930 (struct pipe_resource**)&sctx->barrier_buf);
931 }
932
933 /* Emit a placeholder to signal the next compute IB to start.
934 * See si_compute_prim_discard.c for explanation.
935 */
936 uint32_t signal = 1;
937 si_cp_write_data(sctx, sctx->barrier_buf, sctx->barrier_buf_offset,
938 4, V_370_MEM, V_370_ME, &signal);
939
940 sctx->last_pkt3_write_data =
941 &sctx->gfx_cs->current.buf[sctx->gfx_cs->current.cdw - 5];
942
943 /* Only the last occurence of WRITE_DATA will be executed.
944 * The packet will be enabled in si_flush_gfx_cs.
945 */
946 *sctx->last_pkt3_write_data = PKT3(PKT3_NOP, 3, 0);
947 }
948
949 void si_emit_cache_flush(struct si_context *sctx)
950 {
951 struct radeon_cmdbuf *cs = sctx->gfx_cs;
952 uint32_t flags = sctx->flags;
953
954 if (!sctx->has_graphics) {
955 /* Only process compute flags. */
956 flags &= SI_CONTEXT_INV_ICACHE |
957 SI_CONTEXT_INV_SMEM_L1 |
958 SI_CONTEXT_INV_VMEM_L1 |
959 SI_CONTEXT_INV_GLOBAL_L2 |
960 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
961 SI_CONTEXT_INV_L2_METADATA |
962 SI_CONTEXT_CS_PARTIAL_FLUSH;
963 }
964
965 uint32_t cp_coher_cntl = 0;
966 const uint32_t flush_cb_db = flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
967 SI_CONTEXT_FLUSH_AND_INV_DB);
968 const bool is_barrier = flush_cb_db ||
969 /* INV_ICACHE == beginning of gfx IB. Checking
970 * INV_ICACHE fixes corruption for DeusExMD with
971 * compute-based culling, but I don't know why.
972 */
973 flags & (SI_CONTEXT_INV_ICACHE |
974 SI_CONTEXT_PS_PARTIAL_FLUSH |
975 SI_CONTEXT_VS_PARTIAL_FLUSH) ||
976 (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
977 sctx->compute_is_busy);
978
979 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB)
980 sctx->num_cb_cache_flushes++;
981 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
982 sctx->num_db_cache_flushes++;
983
984 /* GFX6 has a bug that it always flushes ICACHE and KCACHE if either
985 * bit is set. An alternative way is to write SQC_CACHES, but that
986 * doesn't seem to work reliably. Since the bug doesn't affect
987 * correctness (it only does more work than necessary) and
988 * the performance impact is likely negligible, there is no plan
989 * to add a workaround for it.
990 */
991
992 if (flags & SI_CONTEXT_INV_ICACHE)
993 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
994 if (flags & SI_CONTEXT_INV_SMEM_L1)
995 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
996
997 if (sctx->chip_class <= GFX8) {
998 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
999 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
1000 S_0085F0_CB0_DEST_BASE_ENA(1) |
1001 S_0085F0_CB1_DEST_BASE_ENA(1) |
1002 S_0085F0_CB2_DEST_BASE_ENA(1) |
1003 S_0085F0_CB3_DEST_BASE_ENA(1) |
1004 S_0085F0_CB4_DEST_BASE_ENA(1) |
1005 S_0085F0_CB5_DEST_BASE_ENA(1) |
1006 S_0085F0_CB6_DEST_BASE_ENA(1) |
1007 S_0085F0_CB7_DEST_BASE_ENA(1);
1008
1009 /* Necessary for DCC */
1010 if (sctx->chip_class == GFX8)
1011 si_cp_release_mem(sctx, cs,
1012 V_028A90_FLUSH_AND_INV_CB_DATA_TS,
1013 0, EOP_DST_SEL_MEM, EOP_INT_SEL_NONE,
1014 EOP_DATA_SEL_DISCARD, NULL,
1015 0, 0, SI_NOT_QUERY);
1016 }
1017 if (flags & SI_CONTEXT_FLUSH_AND_INV_DB)
1018 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
1019 S_0085F0_DB_DEST_BASE_ENA(1);
1020 }
1021
1022 if (flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
1023 /* Flush CMASK/FMASK/DCC. SURFACE_SYNC will wait for idle. */
1024 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1025 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
1026 }
1027 if (flags & (SI_CONTEXT_FLUSH_AND_INV_DB |
1028 SI_CONTEXT_FLUSH_AND_INV_DB_META)) {
1029 /* Flush HTILE. SURFACE_SYNC will wait for idle. */
1030 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1031 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
1032 }
1033
1034 /* Wait for shader engines to go idle.
1035 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
1036 * for everything including CB/DB cache flushes.
1037 */
1038 if (!flush_cb_db) {
1039 if (flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
1040 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1041 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1042 /* Only count explicit shader flushes, not implicit ones
1043 * done by SURFACE_SYNC.
1044 */
1045 sctx->num_vs_flushes++;
1046 sctx->num_ps_flushes++;
1047 } else if (flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
1048 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1049 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1050 sctx->num_vs_flushes++;
1051 }
1052 }
1053
1054 if (flags & SI_CONTEXT_CS_PARTIAL_FLUSH &&
1055 sctx->compute_is_busy) {
1056 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1057 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH) | EVENT_INDEX(4));
1058 sctx->num_cs_flushes++;
1059 sctx->compute_is_busy = false;
1060 }
1061
1062 /* VGT state synchronization. */
1063 if (flags & SI_CONTEXT_VGT_FLUSH) {
1064 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1065 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1066 }
1067 if (flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
1068 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1069 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
1070 }
1071
1072 /* GFX9: Wait for idle if we're flushing CB or DB. ACQUIRE_MEM doesn't
1073 * wait for idle on GFX9. We have to use a TS event.
1074 */
1075 if (sctx->chip_class >= GFX9 && flush_cb_db) {
1076 uint64_t va;
1077 unsigned tc_flags, cb_db_event;
1078
1079 /* Set the CB/DB flush event. */
1080 switch (flush_cb_db) {
1081 case SI_CONTEXT_FLUSH_AND_INV_CB:
1082 cb_db_event = V_028A90_FLUSH_AND_INV_CB_DATA_TS;
1083 break;
1084 case SI_CONTEXT_FLUSH_AND_INV_DB:
1085 cb_db_event = V_028A90_FLUSH_AND_INV_DB_DATA_TS;
1086 break;
1087 default:
1088 /* both CB & DB */
1089 cb_db_event = V_028A90_CACHE_FLUSH_AND_INV_TS_EVENT;
1090 }
1091
1092 /* These are the only allowed combinations. If you need to
1093 * do multiple operations at once, do them separately.
1094 * All operations that invalidate L2 also seem to invalidate
1095 * metadata. Volatile (VOL) and WC flushes are not listed here.
1096 *
1097 * TC | TC_WB = writeback & invalidate L2 & L1
1098 * TC | TC_WB | TC_NC = writeback & invalidate L2 for MTYPE == NC
1099 * TC_WB | TC_NC = writeback L2 for MTYPE == NC
1100 * TC | TC_NC = invalidate L2 for MTYPE == NC
1101 * TC | TC_MD = writeback & invalidate L2 metadata (DCC, etc.)
1102 * TCL1 = invalidate L1
1103 */
1104 tc_flags = 0;
1105
1106 if (flags & SI_CONTEXT_INV_L2_METADATA) {
1107 tc_flags = EVENT_TC_ACTION_ENA |
1108 EVENT_TC_MD_ACTION_ENA;
1109 }
1110
1111 /* Ideally flush TC together with CB/DB. */
1112 if (flags & SI_CONTEXT_INV_GLOBAL_L2) {
1113 /* Writeback and invalidate everything in L2 & L1. */
1114 tc_flags = EVENT_TC_ACTION_ENA |
1115 EVENT_TC_WB_ACTION_ENA;
1116
1117 /* Clear the flags. */
1118 flags &= ~(SI_CONTEXT_INV_GLOBAL_L2 |
1119 SI_CONTEXT_WRITEBACK_GLOBAL_L2 |
1120 SI_CONTEXT_INV_VMEM_L1);
1121 sctx->num_L2_invalidates++;
1122 }
1123
1124 /* Do the flush (enqueue the event and wait for it). */
1125 va = sctx->wait_mem_scratch->gpu_address;
1126 sctx->wait_mem_number++;
1127
1128 si_cp_release_mem(sctx, cs, cb_db_event, tc_flags,
1129 EOP_DST_SEL_MEM,
1130 EOP_INT_SEL_SEND_DATA_AFTER_WR_CONFIRM,
1131 EOP_DATA_SEL_VALUE_32BIT,
1132 sctx->wait_mem_scratch, va,
1133 sctx->wait_mem_number, SI_NOT_QUERY);
1134 si_cp_wait_mem(sctx, cs, va, sctx->wait_mem_number, 0xffffffff,
1135 WAIT_REG_MEM_EQUAL);
1136 }
1137
1138 /* Make sure ME is idle (it executes most packets) before continuing.
1139 * This prevents read-after-write hazards between PFP and ME.
1140 */
1141 if (sctx->has_graphics &&
1142 (cp_coher_cntl ||
1143 (flags & (SI_CONTEXT_CS_PARTIAL_FLUSH |
1144 SI_CONTEXT_INV_VMEM_L1 |
1145 SI_CONTEXT_INV_GLOBAL_L2 |
1146 SI_CONTEXT_WRITEBACK_GLOBAL_L2)))) {
1147 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
1148 radeon_emit(cs, 0);
1149 }
1150
1151 /* GFX6-GFX8 only:
1152 * When one of the CP_COHER_CNTL.DEST_BASE flags is set, SURFACE_SYNC
1153 * waits for idle, so it should be last. SURFACE_SYNC is done in PFP.
1154 *
1155 * cp_coher_cntl should contain all necessary flags except TC flags
1156 * at this point.
1157 *
1158 * GFX6-GFX7 don't support L2 write-back.
1159 */
1160 if (flags & SI_CONTEXT_INV_GLOBAL_L2 ||
1161 (sctx->chip_class <= GFX7 &&
1162 (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2))) {
1163 /* Invalidate L1 & L2. (L1 is always invalidated on GFX6)
1164 * WB must be set on GFX8+ when TC_ACTION is set.
1165 */
1166 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1167 S_0085F0_TC_ACTION_ENA(1) |
1168 S_0085F0_TCL1_ACTION_ENA(1) |
1169 S_0301F0_TC_WB_ACTION_ENA(sctx->chip_class >= GFX8));
1170 cp_coher_cntl = 0;
1171 sctx->num_L2_invalidates++;
1172 } else {
1173 /* L1 invalidation and L2 writeback must be done separately,
1174 * because both operations can't be done together.
1175 */
1176 if (flags & SI_CONTEXT_WRITEBACK_GLOBAL_L2) {
1177 /* WB = write-back
1178 * NC = apply to non-coherent MTYPEs
1179 * (i.e. MTYPE <= 1, which is what we use everywhere)
1180 *
1181 * WB doesn't work without NC.
1182 */
1183 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1184 S_0301F0_TC_WB_ACTION_ENA(1) |
1185 S_0301F0_TC_NC_ACTION_ENA(1));
1186 cp_coher_cntl = 0;
1187 sctx->num_L2_writebacks++;
1188 }
1189 if (flags & SI_CONTEXT_INV_VMEM_L1) {
1190 /* Invalidate per-CU VMEM L1. */
1191 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl |
1192 S_0085F0_TCL1_ACTION_ENA(1));
1193 cp_coher_cntl = 0;
1194 }
1195 }
1196
1197 /* If TC flushes haven't cleared this... */
1198 if (cp_coher_cntl)
1199 si_emit_surface_sync(sctx, sctx->gfx_cs, cp_coher_cntl);
1200
1201 if (is_barrier)
1202 si_prim_discard_signal_next_compute_ib_start(sctx);
1203
1204 if (flags & SI_CONTEXT_START_PIPELINE_STATS) {
1205 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1206 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
1207 EVENT_INDEX(0));
1208 } else if (flags & SI_CONTEXT_STOP_PIPELINE_STATS) {
1209 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
1210 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
1211 EVENT_INDEX(0));
1212 }
1213
1214 sctx->flags = 0;
1215 }
1216
1217 static void si_get_draw_start_count(struct si_context *sctx,
1218 const struct pipe_draw_info *info,
1219 unsigned *start, unsigned *count)
1220 {
1221 struct pipe_draw_indirect_info *indirect = info->indirect;
1222
1223 if (indirect) {
1224 unsigned indirect_count;
1225 struct pipe_transfer *transfer;
1226 unsigned begin, end;
1227 unsigned map_size;
1228 unsigned *data;
1229
1230 if (indirect->indirect_draw_count) {
1231 data = pipe_buffer_map_range(&sctx->b,
1232 indirect->indirect_draw_count,
1233 indirect->indirect_draw_count_offset,
1234 sizeof(unsigned),
1235 PIPE_TRANSFER_READ, &transfer);
1236
1237 indirect_count = *data;
1238
1239 pipe_buffer_unmap(&sctx->b, transfer);
1240 } else {
1241 indirect_count = indirect->draw_count;
1242 }
1243
1244 if (!indirect_count) {
1245 *start = *count = 0;
1246 return;
1247 }
1248
1249 map_size = (indirect_count - 1) * indirect->stride + 3 * sizeof(unsigned);
1250 data = pipe_buffer_map_range(&sctx->b, indirect->buffer,
1251 indirect->offset, map_size,
1252 PIPE_TRANSFER_READ, &transfer);
1253
1254 begin = UINT_MAX;
1255 end = 0;
1256
1257 for (unsigned i = 0; i < indirect_count; ++i) {
1258 unsigned count = data[0];
1259 unsigned start = data[2];
1260
1261 if (count > 0) {
1262 begin = MIN2(begin, start);
1263 end = MAX2(end, start + count);
1264 }
1265
1266 data += indirect->stride / sizeof(unsigned);
1267 }
1268
1269 pipe_buffer_unmap(&sctx->b, transfer);
1270
1271 if (begin < end) {
1272 *start = begin;
1273 *count = end - begin;
1274 } else {
1275 *start = *count = 0;
1276 }
1277 } else {
1278 *start = info->start;
1279 *count = info->count;
1280 }
1281 }
1282
1283 static void si_emit_all_states(struct si_context *sctx, const struct pipe_draw_info *info,
1284 enum pipe_prim_type prim, unsigned instance_count,
1285 bool primitive_restart, unsigned skip_atom_mask)
1286 {
1287 unsigned num_patches = 0;
1288
1289 si_emit_rasterizer_prim_state(sctx);
1290 if (sctx->tes_shader.cso)
1291 si_emit_derived_tess_state(sctx, info, &num_patches);
1292
1293 /* Emit state atoms. */
1294 unsigned mask = sctx->dirty_atoms & ~skip_atom_mask;
1295 while (mask)
1296 sctx->atoms.array[u_bit_scan(&mask)].emit(sctx);
1297
1298 sctx->dirty_atoms &= skip_atom_mask;
1299
1300 /* Emit states. */
1301 mask = sctx->dirty_states;
1302 while (mask) {
1303 unsigned i = u_bit_scan(&mask);
1304 struct si_pm4_state *state = sctx->queued.array[i];
1305
1306 if (!state || sctx->emitted.array[i] == state)
1307 continue;
1308
1309 si_pm4_emit(sctx, state);
1310 sctx->emitted.array[i] = state;
1311 }
1312 sctx->dirty_states = 0;
1313
1314 /* Emit draw states. */
1315 si_emit_vs_state(sctx, info);
1316 si_emit_draw_registers(sctx, info, prim, num_patches, instance_count,
1317 primitive_restart);
1318 }
1319
1320 static bool
1321 si_all_vs_resources_read_only(struct si_context *sctx,
1322 struct pipe_resource *indexbuf)
1323 {
1324 struct radeon_winsys *ws = sctx->ws;
1325 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1326
1327 /* Index buffer. */
1328 if (indexbuf &&
1329 ws->cs_is_buffer_referenced(cs, si_resource(indexbuf)->buf,
1330 RADEON_USAGE_WRITE))
1331 goto has_write_reference;
1332
1333 /* Vertex buffers. */
1334 struct si_vertex_elements *velems = sctx->vertex_elements;
1335 unsigned num_velems = velems->count;
1336
1337 for (unsigned i = 0; i < num_velems; i++) {
1338 if (!((1 << i) & velems->first_vb_use_mask))
1339 continue;
1340
1341 unsigned vb_index = velems->vertex_buffer_index[i];
1342 struct pipe_resource *res = sctx->vertex_buffer[vb_index].buffer.resource;
1343 if (!res)
1344 continue;
1345
1346 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1347 RADEON_USAGE_WRITE))
1348 goto has_write_reference;
1349 }
1350
1351 /* Constant and shader buffers. */
1352 struct si_descriptors *buffers =
1353 &sctx->descriptors[si_const_and_shader_buffer_descriptors_idx(PIPE_SHADER_VERTEX)];
1354 for (unsigned i = 0; i < buffers->num_active_slots; i++) {
1355 unsigned index = buffers->first_active_slot + i;
1356 struct pipe_resource *res =
1357 sctx->const_and_shader_buffers[PIPE_SHADER_VERTEX].buffers[index];
1358 if (!res)
1359 continue;
1360
1361 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1362 RADEON_USAGE_WRITE))
1363 goto has_write_reference;
1364 }
1365
1366 /* Samplers. */
1367 struct si_shader_selector *vs = sctx->vs_shader.cso;
1368 if (vs->info.samplers_declared) {
1369 unsigned num_samplers = util_last_bit(vs->info.samplers_declared);
1370
1371 for (unsigned i = 0; i < num_samplers; i++) {
1372 struct pipe_sampler_view *view = sctx->samplers[PIPE_SHADER_VERTEX].views[i];
1373 if (!view)
1374 continue;
1375
1376 if (ws->cs_is_buffer_referenced(cs,
1377 si_resource(view->texture)->buf,
1378 RADEON_USAGE_WRITE))
1379 goto has_write_reference;
1380 }
1381 }
1382
1383 /* Images. */
1384 if (vs->info.images_declared) {
1385 unsigned num_images = util_last_bit(vs->info.images_declared);
1386
1387 for (unsigned i = 0; i < num_images; i++) {
1388 struct pipe_resource *res = sctx->images[PIPE_SHADER_VERTEX].views[i].resource;
1389 if (!res)
1390 continue;
1391
1392 if (ws->cs_is_buffer_referenced(cs, si_resource(res)->buf,
1393 RADEON_USAGE_WRITE))
1394 goto has_write_reference;
1395 }
1396 }
1397
1398 return true;
1399
1400 has_write_reference:
1401 /* If the current gfx IB has enough packets, flush it to remove write
1402 * references to buffers.
1403 */
1404 if (cs->prev_dw + cs->current.cdw > 2048) {
1405 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
1406 assert(si_all_vs_resources_read_only(sctx, indexbuf));
1407 return true;
1408 }
1409 return false;
1410 }
1411
1412 static ALWAYS_INLINE bool pd_msg(const char *s)
1413 {
1414 if (SI_PRIM_DISCARD_DEBUG)
1415 printf("PD failed: %s\n", s);
1416 return false;
1417 }
1418
1419 static void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
1420 {
1421 struct si_context *sctx = (struct si_context *)ctx;
1422 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1423 struct pipe_resource *indexbuf = info->index.resource;
1424 unsigned dirty_tex_counter, dirty_buf_counter;
1425 enum pipe_prim_type rast_prim, prim = info->mode;
1426 unsigned index_size = info->index_size;
1427 unsigned index_offset = info->indirect ? info->start * index_size : 0;
1428 unsigned instance_count = info->instance_count;
1429 bool primitive_restart = info->primitive_restart &&
1430 (!sctx->screen->options.prim_restart_tri_strips_only ||
1431 (prim != PIPE_PRIM_TRIANGLE_STRIP &&
1432 prim != PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY));
1433
1434 if (likely(!info->indirect)) {
1435 /* GFX6-GFX7 treat instance_count==0 as instance_count==1. There is
1436 * no workaround for indirect draws, but we can at least skip
1437 * direct draws.
1438 */
1439 if (unlikely(!instance_count))
1440 return;
1441
1442 /* Handle count == 0. */
1443 if (unlikely(!info->count &&
1444 (index_size || !info->count_from_stream_output)))
1445 return;
1446 }
1447
1448 if (unlikely(!sctx->vs_shader.cso ||
1449 !rs ||
1450 (!sctx->ps_shader.cso && !rs->rasterizer_discard) ||
1451 (!!sctx->tes_shader.cso != (prim == PIPE_PRIM_PATCHES)))) {
1452 assert(0);
1453 return;
1454 }
1455
1456 /* Recompute and re-emit the texture resource states if needed. */
1457 dirty_tex_counter = p_atomic_read(&sctx->screen->dirty_tex_counter);
1458 if (unlikely(dirty_tex_counter != sctx->last_dirty_tex_counter)) {
1459 sctx->last_dirty_tex_counter = dirty_tex_counter;
1460 sctx->framebuffer.dirty_cbufs |=
1461 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
1462 sctx->framebuffer.dirty_zsbuf = true;
1463 si_mark_atom_dirty(sctx, &sctx->atoms.s.framebuffer);
1464 si_update_all_texture_descriptors(sctx);
1465 }
1466
1467 dirty_buf_counter = p_atomic_read(&sctx->screen->dirty_buf_counter);
1468 if (unlikely(dirty_buf_counter != sctx->last_dirty_buf_counter)) {
1469 sctx->last_dirty_buf_counter = dirty_buf_counter;
1470 /* Rebind all buffers unconditionally. */
1471 si_rebind_buffer(sctx, NULL);
1472 }
1473
1474 si_decompress_textures(sctx, u_bit_consecutive(0, SI_NUM_GRAPHICS_SHADERS));
1475
1476 /* Set the rasterization primitive type.
1477 *
1478 * This must be done after si_decompress_textures, which can call
1479 * draw_vbo recursively, and before si_update_shaders, which uses
1480 * current_rast_prim for this draw_vbo call. */
1481 if (sctx->gs_shader.cso)
1482 rast_prim = sctx->gs_shader.cso->gs_output_prim;
1483 else if (sctx->tes_shader.cso) {
1484 if (sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1485 rast_prim = PIPE_PRIM_POINTS;
1486 else
1487 rast_prim = sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1488 } else
1489 rast_prim = prim;
1490
1491 if (rast_prim != sctx->current_rast_prim) {
1492 if (util_prim_is_points_or_lines(sctx->current_rast_prim) !=
1493 util_prim_is_points_or_lines(rast_prim))
1494 si_mark_atom_dirty(sctx, &sctx->atoms.s.guardband);
1495
1496 sctx->current_rast_prim = rast_prim;
1497 sctx->do_update_shaders = true;
1498 }
1499
1500 if (sctx->tes_shader.cso &&
1501 sctx->screen->has_ls_vgpr_init_bug) {
1502 /* Determine whether the LS VGPR fix should be applied.
1503 *
1504 * It is only required when num input CPs > num output CPs,
1505 * which cannot happen with the fixed function TCS. We should
1506 * also update this bit when switching from TCS to fixed
1507 * function TCS.
1508 */
1509 struct si_shader_selector *tcs = sctx->tcs_shader.cso;
1510 bool ls_vgpr_fix =
1511 tcs &&
1512 info->vertices_per_patch >
1513 tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
1514
1515 if (ls_vgpr_fix != sctx->ls_vgpr_fix) {
1516 sctx->ls_vgpr_fix = ls_vgpr_fix;
1517 sctx->do_update_shaders = true;
1518 }
1519 }
1520
1521 if (sctx->gs_shader.cso) {
1522 /* Determine whether the GS triangle strip adjacency fix should
1523 * be applied. Rotate every other triangle if
1524 * - triangle strips with adjacency are fed to the GS and
1525 * - primitive restart is disabled (the rotation doesn't help
1526 * when the restart occurs after an odd number of triangles).
1527 */
1528 bool gs_tri_strip_adj_fix =
1529 !sctx->tes_shader.cso &&
1530 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY &&
1531 !primitive_restart;
1532
1533 if (gs_tri_strip_adj_fix != sctx->gs_tri_strip_adj_fix) {
1534 sctx->gs_tri_strip_adj_fix = gs_tri_strip_adj_fix;
1535 sctx->do_update_shaders = true;
1536 }
1537 }
1538
1539 if (index_size) {
1540 /* Translate or upload, if needed. */
1541 /* 8-bit indices are supported on GFX8. */
1542 if (sctx->chip_class <= GFX7 && index_size == 1) {
1543 unsigned start, count, start_offset, size, offset;
1544 void *ptr;
1545
1546 si_get_draw_start_count(sctx, info, &start, &count);
1547 start_offset = start * 2;
1548 size = count * 2;
1549
1550 indexbuf = NULL;
1551 u_upload_alloc(ctx->stream_uploader, start_offset,
1552 size,
1553 si_optimal_tcc_alignment(sctx, size),
1554 &offset, &indexbuf, &ptr);
1555 if (!indexbuf)
1556 return;
1557
1558 util_shorten_ubyte_elts_to_userptr(&sctx->b, info, 0, 0,
1559 index_offset + start,
1560 count, ptr);
1561
1562 /* info->start will be added by the drawing code */
1563 index_offset = offset - start_offset;
1564 index_size = 2;
1565 } else if (info->has_user_indices) {
1566 unsigned start_offset;
1567
1568 assert(!info->indirect);
1569 start_offset = info->start * index_size;
1570
1571 indexbuf = NULL;
1572 u_upload_data(ctx->stream_uploader, start_offset,
1573 info->count * index_size,
1574 sctx->screen->info.tcc_cache_line_size,
1575 (char*)info->index.user + start_offset,
1576 &index_offset, &indexbuf);
1577 if (!indexbuf)
1578 return;
1579
1580 /* info->start will be added by the drawing code */
1581 index_offset -= start_offset;
1582 } else if (sctx->chip_class <= GFX7 &&
1583 si_resource(indexbuf)->TC_L2_dirty) {
1584 /* GFX8 reads index buffers through TC L2, so it doesn't
1585 * need this. */
1586 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1587 si_resource(indexbuf)->TC_L2_dirty = false;
1588 }
1589 }
1590
1591 bool dispatch_prim_discard_cs = false;
1592 bool prim_discard_cs_instancing = false;
1593 unsigned original_index_size = index_size;
1594 unsigned direct_count = 0;
1595
1596 if (info->indirect) {
1597 struct pipe_draw_indirect_info *indirect = info->indirect;
1598
1599 /* Add the buffer size for memory checking in need_cs_space. */
1600 si_context_add_resource_size(sctx, indirect->buffer);
1601
1602 /* Indirect buffers use TC L2 on GFX9, but not older hw. */
1603 if (sctx->chip_class <= GFX8) {
1604 if (si_resource(indirect->buffer)->TC_L2_dirty) {
1605 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1606 si_resource(indirect->buffer)->TC_L2_dirty = false;
1607 }
1608
1609 if (indirect->indirect_draw_count &&
1610 si_resource(indirect->indirect_draw_count)->TC_L2_dirty) {
1611 sctx->flags |= SI_CONTEXT_WRITEBACK_GLOBAL_L2;
1612 si_resource(indirect->indirect_draw_count)->TC_L2_dirty = false;
1613 }
1614 }
1615 } else {
1616 /* Multiply by 3 for strips and fans to get an approximate vertex
1617 * count as triangles. */
1618 direct_count = info->count * instance_count *
1619 (prim == PIPE_PRIM_TRIANGLES ? 1 : 3);
1620 }
1621
1622 /* Determine if we can use the primitive discard compute shader. */
1623 if (si_compute_prim_discard_enabled(sctx) &&
1624 (direct_count > sctx->prim_discard_vertex_count_threshold ?
1625 (sctx->compute_num_verts_rejected += direct_count, true) : /* Add, then return true. */
1626 (sctx->compute_num_verts_ineligible += direct_count, false)) && /* Add, then return false. */
1627 (!info->count_from_stream_output || pd_msg("draw_opaque")) &&
1628 (primitive_restart ?
1629 /* Supported prim types with primitive restart: */
1630 (prim == PIPE_PRIM_TRIANGLE_STRIP || pd_msg("bad prim type with primitive restart")) &&
1631 /* Disallow instancing with primitive restart: */
1632 (instance_count == 1 || pd_msg("instance_count > 1 with primitive restart")) :
1633 /* Supported prim types without primitive restart + allow instancing: */
1634 (1 << prim) & ((1 << PIPE_PRIM_TRIANGLES) |
1635 (1 << PIPE_PRIM_TRIANGLE_STRIP) |
1636 (1 << PIPE_PRIM_TRIANGLE_FAN)) &&
1637 /* Instancing is limited to 16-bit indices, because InstanceID is packed into VertexID. */
1638 /* TODO: DrawArraysInstanced doesn't sometimes work, so it's disabled. */
1639 (instance_count == 1 ||
1640 (instance_count <= USHRT_MAX && index_size && index_size <= 2) ||
1641 pd_msg("instance_count too large or index_size == 4 or DrawArraysInstanced"))) &&
1642 (info->drawid == 0 || !sctx->vs_shader.cso->info.uses_drawid || pd_msg("draw_id > 0")) &&
1643 (!sctx->render_cond || pd_msg("render condition")) &&
1644 /* Forced enablement ignores pipeline statistics queries. */
1645 (sctx->screen->debug_flags & (DBG(PD) | DBG(ALWAYS_PD)) ||
1646 (!sctx->num_pipeline_stat_queries && !sctx->streamout.prims_gen_query_enabled) ||
1647 pd_msg("pipestat or primgen query")) &&
1648 (!sctx->vertex_elements->instance_divisor_is_fetched || pd_msg("loads instance divisors")) &&
1649 (!sctx->tes_shader.cso || pd_msg("uses tess")) &&
1650 (!sctx->gs_shader.cso || pd_msg("uses GS")) &&
1651 (!sctx->ps_shader.cso->info.uses_primid || pd_msg("PS uses PrimID")) &&
1652 #if SI_PRIM_DISCARD_DEBUG /* same as cso->prim_discard_cs_allowed */
1653 (!sctx->vs_shader.cso->info.uses_bindless_images || pd_msg("uses bindless images")) &&
1654 (!sctx->vs_shader.cso->info.uses_bindless_samplers || pd_msg("uses bindless samplers")) &&
1655 (!sctx->vs_shader.cso->info.writes_memory || pd_msg("writes memory")) &&
1656 (!sctx->vs_shader.cso->info.writes_viewport_index || pd_msg("writes viewport index")) &&
1657 !sctx->vs_shader.cso->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
1658 !sctx->vs_shader.cso->so.num_outputs &&
1659 #else
1660 (sctx->vs_shader.cso->prim_discard_cs_allowed || pd_msg("VS shader uses unsupported features")) &&
1661 #endif
1662 /* Check that all buffers are used for read only, because compute
1663 * dispatches can run ahead. */
1664 (si_all_vs_resources_read_only(sctx, index_size ? indexbuf : NULL) || pd_msg("write reference"))) {
1665 switch (si_prepare_prim_discard_or_split_draw(sctx, info, primitive_restart)) {
1666 case SI_PRIM_DISCARD_ENABLED:
1667 original_index_size = index_size;
1668 prim_discard_cs_instancing = instance_count > 1;
1669 dispatch_prim_discard_cs = true;
1670
1671 /* The compute shader changes/lowers the following: */
1672 prim = PIPE_PRIM_TRIANGLES;
1673 index_size = 4;
1674 instance_count = 1;
1675 primitive_restart = false;
1676 sctx->compute_num_verts_rejected -= direct_count;
1677 sctx->compute_num_verts_accepted += direct_count;
1678 break;
1679 case SI_PRIM_DISCARD_DISABLED:
1680 break;
1681 case SI_PRIM_DISCARD_DRAW_SPLIT:
1682 sctx->compute_num_verts_rejected -= direct_count;
1683 goto return_cleanup;
1684 }
1685 }
1686
1687 if (prim_discard_cs_instancing != sctx->prim_discard_cs_instancing) {
1688 sctx->prim_discard_cs_instancing = prim_discard_cs_instancing;
1689 sctx->do_update_shaders = true;
1690 }
1691
1692 if (sctx->do_update_shaders && !si_update_shaders(sctx))
1693 goto return_cleanup;
1694
1695 si_need_gfx_cs_space(sctx);
1696
1697 if (sctx->bo_list_add_all_gfx_resources)
1698 si_gfx_resources_add_all_to_bo_list(sctx);
1699
1700 /* Since we've called si_context_add_resource_size for vertex buffers,
1701 * this must be called after si_need_cs_space, because we must let
1702 * need_cs_space flush before we add buffers to the buffer list.
1703 */
1704 if (!si_upload_vertex_buffer_descriptors(sctx))
1705 goto return_cleanup;
1706
1707 /* Vega10/Raven scissor bug workaround. When any context register is
1708 * written (i.e. the GPU rolls the context), PA_SC_VPORT_SCISSOR
1709 * registers must be written too.
1710 */
1711 bool has_gfx9_scissor_bug = sctx->screen->has_gfx9_scissor_bug;
1712 unsigned masked_atoms = 0;
1713
1714 if (has_gfx9_scissor_bug) {
1715 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.scissors);
1716
1717 if (info->count_from_stream_output ||
1718 sctx->dirty_atoms & si_atoms_that_always_roll_context() ||
1719 sctx->dirty_states & si_states_that_always_roll_context())
1720 sctx->context_roll = true;
1721 }
1722
1723 /* Use optimal packet order based on whether we need to sync the pipeline. */
1724 if (unlikely(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
1725 SI_CONTEXT_FLUSH_AND_INV_DB |
1726 SI_CONTEXT_PS_PARTIAL_FLUSH |
1727 SI_CONTEXT_CS_PARTIAL_FLUSH))) {
1728 /* If we have to wait for idle, set all states first, so that all
1729 * SET packets are processed in parallel with previous draw calls.
1730 * Then draw and prefetch at the end. This ensures that the time
1731 * the CUs are idle is very short.
1732 */
1733 if (unlikely(sctx->flags & SI_CONTEXT_FLUSH_FOR_RENDER_COND))
1734 masked_atoms |= si_get_atom_bit(sctx, &sctx->atoms.s.render_cond);
1735
1736 if (!si_upload_graphics_shader_descriptors(sctx))
1737 goto return_cleanup;
1738
1739 /* Emit all states except possibly render condition. */
1740 si_emit_all_states(sctx, info, prim, instance_count,
1741 primitive_restart, masked_atoms);
1742 si_emit_cache_flush(sctx);
1743 /* <-- CUs are idle here. */
1744
1745 if (si_is_atom_dirty(sctx, &sctx->atoms.s.render_cond))
1746 sctx->atoms.s.render_cond.emit(sctx);
1747
1748 if (has_gfx9_scissor_bug &&
1749 (sctx->context_roll ||
1750 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
1751 sctx->atoms.s.scissors.emit(sctx);
1752
1753 sctx->dirty_atoms = 0;
1754
1755 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
1756 instance_count, dispatch_prim_discard_cs,
1757 original_index_size);
1758 /* <-- CUs are busy here. */
1759
1760 /* Start prefetches after the draw has been started. Both will run
1761 * in parallel, but starting the draw first is more important.
1762 */
1763 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1764 cik_emit_prefetch_L2(sctx, false);
1765 } else {
1766 /* If we don't wait for idle, start prefetches first, then set
1767 * states, and draw at the end.
1768 */
1769 if (sctx->flags)
1770 si_emit_cache_flush(sctx);
1771
1772 /* Only prefetch the API VS and VBO descriptors. */
1773 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1774 cik_emit_prefetch_L2(sctx, true);
1775
1776 if (!si_upload_graphics_shader_descriptors(sctx))
1777 goto return_cleanup;
1778
1779 si_emit_all_states(sctx, info, prim, instance_count,
1780 primitive_restart, masked_atoms);
1781
1782 if (has_gfx9_scissor_bug &&
1783 (sctx->context_roll ||
1784 si_is_atom_dirty(sctx, &sctx->atoms.s.scissors)))
1785 sctx->atoms.s.scissors.emit(sctx);
1786
1787 sctx->dirty_atoms = 0;
1788
1789 si_emit_draw_packets(sctx, info, indexbuf, index_size, index_offset,
1790 instance_count, dispatch_prim_discard_cs,
1791 original_index_size);
1792
1793 /* Prefetch the remaining shaders after the draw has been
1794 * started. */
1795 if (sctx->chip_class >= GFX7 && sctx->prefetch_L2_mask)
1796 cik_emit_prefetch_L2(sctx, false);
1797 }
1798
1799 /* Clear the context roll flag after the draw call. */
1800 sctx->context_roll = false;
1801
1802 if (unlikely(sctx->current_saved_cs)) {
1803 si_trace_emit(sctx);
1804 si_log_draw_state(sctx, sctx->log);
1805 }
1806
1807 /* Workaround for a VGT hang when streamout is enabled.
1808 * It must be done after drawing. */
1809 if ((sctx->family == CHIP_HAWAII ||
1810 sctx->family == CHIP_TONGA ||
1811 sctx->family == CHIP_FIJI) &&
1812 si_get_strmout_en(sctx)) {
1813 sctx->flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
1814 }
1815
1816 if (unlikely(sctx->decompression_enabled)) {
1817 sctx->num_decompress_calls++;
1818 } else {
1819 sctx->num_draw_calls++;
1820 if (sctx->framebuffer.state.nr_cbufs > 1)
1821 sctx->num_mrt_draw_calls++;
1822 if (primitive_restart)
1823 sctx->num_prim_restart_calls++;
1824 if (G_0286E8_WAVESIZE(sctx->spi_tmpring_size))
1825 sctx->num_spill_draw_calls++;
1826 }
1827
1828 return_cleanup:
1829 if (index_size && indexbuf != info->index.resource)
1830 pipe_resource_reference(&indexbuf, NULL);
1831 }
1832
1833 static void
1834 si_draw_rectangle(struct blitter_context *blitter,
1835 void *vertex_elements_cso,
1836 blitter_get_vs_func get_vs,
1837 int x1, int y1, int x2, int y2,
1838 float depth, unsigned num_instances,
1839 enum blitter_attrib_type type,
1840 const union blitter_attrib *attrib)
1841 {
1842 struct pipe_context *pipe = util_blitter_get_pipe(blitter);
1843 struct si_context *sctx = (struct si_context*)pipe;
1844
1845 /* Pack position coordinates as signed int16. */
1846 sctx->vs_blit_sh_data[0] = (uint32_t)(x1 & 0xffff) |
1847 ((uint32_t)(y1 & 0xffff) << 16);
1848 sctx->vs_blit_sh_data[1] = (uint32_t)(x2 & 0xffff) |
1849 ((uint32_t)(y2 & 0xffff) << 16);
1850 sctx->vs_blit_sh_data[2] = fui(depth);
1851
1852 switch (type) {
1853 case UTIL_BLITTER_ATTRIB_COLOR:
1854 memcpy(&sctx->vs_blit_sh_data[3], attrib->color,
1855 sizeof(float)*4);
1856 break;
1857 case UTIL_BLITTER_ATTRIB_TEXCOORD_XY:
1858 case UTIL_BLITTER_ATTRIB_TEXCOORD_XYZW:
1859 memcpy(&sctx->vs_blit_sh_data[3], &attrib->texcoord,
1860 sizeof(attrib->texcoord));
1861 break;
1862 case UTIL_BLITTER_ATTRIB_NONE:;
1863 }
1864
1865 pipe->bind_vs_state(pipe, si_get_blitter_vs(sctx, type, num_instances));
1866
1867 struct pipe_draw_info info = {};
1868 info.mode = SI_PRIM_RECTANGLE_LIST;
1869 info.count = 3;
1870 info.instance_count = num_instances;
1871
1872 /* Don't set per-stage shader pointers for VS. */
1873 sctx->shader_pointers_dirty &= ~SI_DESCS_SHADER_MASK(VERTEX);
1874 sctx->vertex_buffer_pointer_dirty = false;
1875
1876 si_draw_vbo(pipe, &info);
1877 }
1878
1879 void si_trace_emit(struct si_context *sctx)
1880 {
1881 struct radeon_cmdbuf *cs = sctx->gfx_cs;
1882 uint32_t trace_id = ++sctx->current_saved_cs->trace_id;
1883
1884 si_cp_write_data(sctx, sctx->current_saved_cs->trace_buf,
1885 0, 4, V_370_MEM, V_370_ME, &trace_id);
1886
1887 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
1888 radeon_emit(cs, AC_ENCODE_TRACE_POINT(trace_id));
1889
1890 if (sctx->log)
1891 u_log_flush(sctx->log);
1892 }
1893
1894 void si_init_draw_functions(struct si_context *sctx)
1895 {
1896 sctx->b.draw_vbo = si_draw_vbo;
1897
1898 sctx->blitter->draw_rectangle = si_draw_rectangle;
1899
1900 si_init_ia_multi_vgt_param_table(sctx);
1901 }