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[mesa.git] / src / gallium / drivers / radeonsi / si_state_draw.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 */
26
27 #include "si_pipe.h"
28 #include "si_shader.h"
29 #include "radeon/r600_cs.h"
30 #include "sid.h"
31
32 #include "util/u_index_modify.h"
33 #include "util/u_upload_mgr.h"
34 #include "util/u_prim.h"
35 #include "util/u_memory.h"
36
37 static unsigned si_conv_pipe_prim(unsigned mode)
38 {
39 static const unsigned prim_conv[] = {
40 [PIPE_PRIM_POINTS] = V_008958_DI_PT_POINTLIST,
41 [PIPE_PRIM_LINES] = V_008958_DI_PT_LINELIST,
42 [PIPE_PRIM_LINE_LOOP] = V_008958_DI_PT_LINELOOP,
43 [PIPE_PRIM_LINE_STRIP] = V_008958_DI_PT_LINESTRIP,
44 [PIPE_PRIM_TRIANGLES] = V_008958_DI_PT_TRILIST,
45 [PIPE_PRIM_TRIANGLE_STRIP] = V_008958_DI_PT_TRISTRIP,
46 [PIPE_PRIM_TRIANGLE_FAN] = V_008958_DI_PT_TRIFAN,
47 [PIPE_PRIM_QUADS] = V_008958_DI_PT_QUADLIST,
48 [PIPE_PRIM_QUAD_STRIP] = V_008958_DI_PT_QUADSTRIP,
49 [PIPE_PRIM_POLYGON] = V_008958_DI_PT_POLYGON,
50 [PIPE_PRIM_LINES_ADJACENCY] = V_008958_DI_PT_LINELIST_ADJ,
51 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_008958_DI_PT_LINESTRIP_ADJ,
52 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_008958_DI_PT_TRILIST_ADJ,
53 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_008958_DI_PT_TRISTRIP_ADJ,
54 [PIPE_PRIM_PATCHES] = V_008958_DI_PT_PATCH,
55 [R600_PRIM_RECTANGLE_LIST] = V_008958_DI_PT_RECTLIST
56 };
57 assert(mode < ARRAY_SIZE(prim_conv));
58 return prim_conv[mode];
59 }
60
61 static unsigned si_conv_prim_to_gs_out(unsigned mode)
62 {
63 static const int prim_conv[] = {
64 [PIPE_PRIM_POINTS] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
65 [PIPE_PRIM_LINES] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
66 [PIPE_PRIM_LINE_LOOP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
67 [PIPE_PRIM_LINE_STRIP] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
68 [PIPE_PRIM_TRIANGLES] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
69 [PIPE_PRIM_TRIANGLE_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
70 [PIPE_PRIM_TRIANGLE_FAN] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
71 [PIPE_PRIM_QUADS] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
72 [PIPE_PRIM_QUAD_STRIP] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
73 [PIPE_PRIM_POLYGON] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
74 [PIPE_PRIM_LINES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
75 [PIPE_PRIM_LINE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_LINESTRIP,
76 [PIPE_PRIM_TRIANGLES_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
77 [PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY] = V_028A6C_OUTPRIM_TYPE_TRISTRIP,
78 [PIPE_PRIM_PATCHES] = V_028A6C_OUTPRIM_TYPE_POINTLIST,
79 [R600_PRIM_RECTANGLE_LIST] = V_028A6C_OUTPRIM_TYPE_TRISTRIP
80 };
81 assert(mode < ARRAY_SIZE(prim_conv));
82
83 return prim_conv[mode];
84 }
85
86 /**
87 * This calculates the LDS size for tessellation shaders (VS, TCS, TES).
88 * LS.LDS_SIZE is shared by all 3 shader stages.
89 *
90 * The information about LDS and other non-compile-time parameters is then
91 * written to userdata SGPRs.
92 */
93 static void si_emit_derived_tess_state(struct si_context *sctx,
94 const struct pipe_draw_info *info,
95 unsigned *num_patches)
96 {
97 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
98 struct si_shader_ctx_state *ls = &sctx->vs_shader;
99 /* The TES pointer will only be used for sctx->last_tcs.
100 * It would be wrong to think that TCS = TES. */
101 struct si_shader_selector *tcs =
102 sctx->tcs_shader.cso ? sctx->tcs_shader.cso : sctx->tes_shader.cso;
103 unsigned tes_sh_base = sctx->shader_userdata.sh_base[PIPE_SHADER_TESS_EVAL];
104 unsigned num_tcs_input_cp = info->vertices_per_patch;
105 unsigned num_tcs_output_cp, num_tcs_inputs, num_tcs_outputs;
106 unsigned num_tcs_patch_outputs;
107 unsigned input_vertex_size, output_vertex_size, pervertex_output_patch_size;
108 unsigned input_patch_size, output_patch_size, output_patch0_offset;
109 unsigned perpatch_output_offset, lds_size, ls_rsrc2;
110 unsigned tcs_in_layout, tcs_out_layout, tcs_out_offsets;
111 unsigned offchip_layout, hardware_lds_size;
112
113 /* This calculates how shader inputs and outputs among VS, TCS, and TES
114 * are laid out in LDS. */
115 num_tcs_inputs = util_last_bit64(ls->cso->outputs_written);
116
117 if (sctx->tcs_shader.cso) {
118 num_tcs_outputs = util_last_bit64(tcs->outputs_written);
119 num_tcs_output_cp = tcs->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT];
120 num_tcs_patch_outputs = util_last_bit64(tcs->patch_outputs_written);
121 } else {
122 /* No TCS. Route varyings from LS to TES. */
123 num_tcs_outputs = num_tcs_inputs;
124 num_tcs_output_cp = num_tcs_input_cp;
125 num_tcs_patch_outputs = 2; /* TESSINNER + TESSOUTER */
126 }
127
128 input_vertex_size = num_tcs_inputs * 16;
129 output_vertex_size = num_tcs_outputs * 16;
130
131 input_patch_size = num_tcs_input_cp * input_vertex_size;
132
133 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
134 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
135
136 /* Ensure that we only need one wave per SIMD so we don't need to check
137 * resource usage. Also ensures that the number of tcs in and out
138 * vertices per threadgroup are at most 256.
139 */
140 *num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
141
142 /* Make sure that the data fits in LDS. This assumes the shaders only
143 * use LDS for the inputs and outputs.
144 */
145 hardware_lds_size = sctx->b.chip_class >= CIK ? 65536 : 32768;
146 *num_patches = MIN2(*num_patches, hardware_lds_size / (input_patch_size +
147 output_patch_size));
148
149 /* Make sure the output data fits in the offchip buffer */
150 *num_patches = MIN2(*num_patches, SI_TESS_OFFCHIP_BLOCK_SIZE /
151 output_patch_size);
152
153 /* Not necessary for correctness, but improves performance. The
154 * specific value is taken from the proprietary driver.
155 */
156 *num_patches = MIN2(*num_patches, 40);
157
158 output_patch0_offset = input_patch_size * *num_patches;
159 perpatch_output_offset = output_patch0_offset + pervertex_output_patch_size;
160
161 lds_size = output_patch0_offset + output_patch_size * *num_patches;
162 ls_rsrc2 = ls->current->config.rsrc2;
163
164 if (sctx->b.chip_class >= CIK) {
165 assert(lds_size <= 65536);
166 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 512) / 512);
167 } else {
168 assert(lds_size <= 32768);
169 ls_rsrc2 |= S_00B52C_LDS_SIZE(align(lds_size, 256) / 256);
170 }
171
172 if (sctx->last_ls == ls->current &&
173 sctx->last_tcs == tcs &&
174 sctx->last_tes_sh_base == tes_sh_base &&
175 sctx->last_num_tcs_input_cp == num_tcs_input_cp)
176 return;
177
178 sctx->last_ls = ls->current;
179 sctx->last_tcs = tcs;
180 sctx->last_tes_sh_base = tes_sh_base;
181 sctx->last_num_tcs_input_cp = num_tcs_input_cp;
182
183 /* Due to a hw bug, RSRC2_LS must be written twice with another
184 * LS register written in between. */
185 if (sctx->b.chip_class == CIK && sctx->b.family != CHIP_HAWAII)
186 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, ls_rsrc2);
187 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
188 radeon_emit(cs, ls->current->config.rsrc1);
189 radeon_emit(cs, ls_rsrc2);
190
191 /* Compute userdata SGPRs. */
192 assert(((input_vertex_size / 4) & ~0xff) == 0);
193 assert(((output_vertex_size / 4) & ~0xff) == 0);
194 assert(((input_patch_size / 4) & ~0x1fff) == 0);
195 assert(((output_patch_size / 4) & ~0x1fff) == 0);
196 assert(((output_patch0_offset / 16) & ~0xffff) == 0);
197 assert(((perpatch_output_offset / 16) & ~0xffff) == 0);
198 assert(num_tcs_input_cp <= 32);
199 assert(num_tcs_output_cp <= 32);
200
201 tcs_in_layout = (input_patch_size / 4) |
202 ((input_vertex_size / 4) << 13);
203 tcs_out_layout = (output_patch_size / 4) |
204 ((output_vertex_size / 4) << 13);
205 tcs_out_offsets = (output_patch0_offset / 16) |
206 ((perpatch_output_offset / 16) << 16);
207 offchip_layout = (pervertex_output_patch_size * *num_patches << 16) |
208 (num_tcs_output_cp << 9) | *num_patches;
209
210 /* Set them for LS. */
211 radeon_set_sh_reg(cs,
212 R_00B530_SPI_SHADER_USER_DATA_LS_0 + SI_SGPR_LS_OUT_LAYOUT * 4,
213 tcs_in_layout);
214
215 /* Set them for TCS. */
216 radeon_set_sh_reg_seq(cs,
217 R_00B430_SPI_SHADER_USER_DATA_HS_0 + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 4);
218 radeon_emit(cs, offchip_layout);
219 radeon_emit(cs, tcs_out_offsets);
220 radeon_emit(cs, tcs_out_layout | (num_tcs_input_cp << 26));
221 radeon_emit(cs, tcs_in_layout);
222
223 /* Set them for TES. */
224 radeon_set_sh_reg_seq(cs, tes_sh_base + SI_SGPR_TCS_OFFCHIP_LAYOUT * 4, 1);
225 radeon_emit(cs, offchip_layout);
226 }
227
228 static unsigned si_num_prims_for_vertices(const struct pipe_draw_info *info)
229 {
230 switch (info->mode) {
231 case PIPE_PRIM_PATCHES:
232 return info->count / info->vertices_per_patch;
233 case R600_PRIM_RECTANGLE_LIST:
234 return info->count / 3;
235 default:
236 return u_prims_for_vertices(info->mode, info->count);
237 }
238 }
239
240 static unsigned si_get_ia_multi_vgt_param(struct si_context *sctx,
241 const struct pipe_draw_info *info,
242 unsigned num_patches)
243 {
244 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
245 unsigned prim = info->mode;
246 unsigned primgroup_size = 128; /* recommended without a GS */
247 unsigned max_primgroup_in_wave = 2;
248
249 /* SWITCH_ON_EOP(0) is always preferable. */
250 bool wd_switch_on_eop = false;
251 bool ia_switch_on_eop = false;
252 bool ia_switch_on_eoi = false;
253 bool partial_vs_wave = false;
254 bool partial_es_wave = false;
255
256 if (sctx->gs_shader.cso)
257 primgroup_size = 64; /* recommended with a GS */
258
259 if (sctx->tes_shader.cso) {
260 unsigned num_cp_out =
261 sctx->tcs_shader.cso ?
262 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
263 info->vertices_per_patch;
264 unsigned max_size = 256 / MAX2(info->vertices_per_patch, num_cp_out);
265
266 primgroup_size = MIN2(primgroup_size, max_size);
267
268 /* primgroup_size must be set to a multiple of NUM_PATCHES */
269 primgroup_size = (primgroup_size / num_patches) * num_patches;
270
271 /* SWITCH_ON_EOI must be set if PrimID is used. */
272 if ((sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
273 sctx->tes_shader.cso->info.uses_primid)
274 ia_switch_on_eoi = true;
275
276 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
277 if ((sctx->b.family == CHIP_TAHITI ||
278 sctx->b.family == CHIP_PITCAIRN ||
279 sctx->b.family == CHIP_BONAIRE) &&
280 sctx->gs_shader.cso)
281 partial_vs_wave = true;
282 }
283
284 /* This is a hardware requirement. */
285 if ((rs && rs->line_stipple_enable) ||
286 (sctx->b.screen->debug_flags & DBG_SWITCH_ON_EOP)) {
287 ia_switch_on_eop = true;
288 wd_switch_on_eop = true;
289 }
290
291 if (sctx->b.chip_class >= CIK) {
292 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
293 * 4 shader engines. Set 1 to pass the assertion below.
294 * The other cases are hardware requirements. */
295 if (sctx->b.screen->info.max_se < 4 ||
296 prim == PIPE_PRIM_POLYGON ||
297 prim == PIPE_PRIM_LINE_LOOP ||
298 prim == PIPE_PRIM_TRIANGLE_FAN ||
299 prim == PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY ||
300 info->primitive_restart ||
301 info->count_from_stream_output)
302 wd_switch_on_eop = true;
303
304 /* Hawaii hangs if instancing is enabled and WD_SWITCH_ON_EOP is 0.
305 * We don't know that for indirect drawing, so treat it as
306 * always problematic. */
307 if (sctx->b.family == CHIP_HAWAII &&
308 (info->indirect || info->instance_count > 1))
309 wd_switch_on_eop = true;
310
311 /* Required on CIK and later. */
312 if (sctx->b.screen->info.max_se > 2 && !wd_switch_on_eop)
313 ia_switch_on_eoi = true;
314
315 /* Required by Hawaii and, for some special cases, by VI. */
316 if (ia_switch_on_eoi &&
317 (sctx->b.family == CHIP_HAWAII ||
318 (sctx->b.chip_class == VI &&
319 (sctx->gs_shader.cso || max_primgroup_in_wave != 2))))
320 partial_vs_wave = true;
321
322 /* Instancing bug on Bonaire. */
323 if (sctx->b.family == CHIP_BONAIRE && ia_switch_on_eoi &&
324 (info->indirect || info->instance_count > 1))
325 partial_vs_wave = true;
326
327 /* If the WD switch is false, the IA switch must be false too. */
328 assert(wd_switch_on_eop || !ia_switch_on_eop);
329 }
330
331 /* If SWITCH_ON_EOI is set, PARTIAL_ES_WAVE must be set too. */
332 if (ia_switch_on_eoi)
333 partial_es_wave = true;
334
335 /* GS requirement. */
336 if (SI_GS_PER_ES / primgroup_size >= sctx->screen->gs_table_depth - 3)
337 partial_es_wave = true;
338
339 /* Hw bug with single-primitive instances and SWITCH_ON_EOI
340 * on multi-SE chips. */
341 if (sctx->b.screen->info.max_se >= 2 && ia_switch_on_eoi &&
342 (info->indirect ||
343 (info->instance_count > 1 &&
344 si_num_prims_for_vertices(info) <= 1)))
345 sctx->b.flags |= SI_CONTEXT_VGT_FLUSH;
346
347 return S_028AA8_SWITCH_ON_EOP(ia_switch_on_eop) |
348 S_028AA8_SWITCH_ON_EOI(ia_switch_on_eoi) |
349 S_028AA8_PARTIAL_VS_WAVE_ON(partial_vs_wave) |
350 S_028AA8_PARTIAL_ES_WAVE_ON(partial_es_wave) |
351 S_028AA8_PRIMGROUP_SIZE(primgroup_size - 1) |
352 S_028AA8_WD_SWITCH_ON_EOP(sctx->b.chip_class >= CIK ? wd_switch_on_eop : 0) |
353 S_028AA8_MAX_PRIMGRP_IN_WAVE(sctx->b.chip_class >= VI ?
354 max_primgroup_in_wave : 0);
355 }
356
357 static unsigned si_get_ls_hs_config(struct si_context *sctx,
358 const struct pipe_draw_info *info,
359 unsigned num_patches)
360 {
361 unsigned num_output_cp;
362
363 if (!sctx->tes_shader.cso)
364 return 0;
365
366 num_output_cp = sctx->tcs_shader.cso ?
367 sctx->tcs_shader.cso->info.properties[TGSI_PROPERTY_TCS_VERTICES_OUT] :
368 info->vertices_per_patch;
369
370 return S_028B58_NUM_PATCHES(num_patches) |
371 S_028B58_HS_NUM_INPUT_CP(info->vertices_per_patch) |
372 S_028B58_HS_NUM_OUTPUT_CP(num_output_cp);
373 }
374
375 static void si_emit_scratch_reloc(struct si_context *sctx)
376 {
377 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
378
379 if (!sctx->emit_scratch_reloc)
380 return;
381
382 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
383 sctx->spi_tmpring_size);
384
385 if (sctx->scratch_buffer) {
386 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
387 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
388 RADEON_PRIO_SCRATCH_BUFFER);
389
390 }
391 sctx->emit_scratch_reloc = false;
392 }
393
394 /* rast_prim is the primitive type after GS. */
395 static void si_emit_rasterizer_prim_state(struct si_context *sctx)
396 {
397 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
398 unsigned rast_prim = sctx->current_rast_prim;
399 struct si_state_rasterizer *rs = sctx->emitted.named.rasterizer;
400
401 /* Skip this if not rendering lines. */
402 if (rast_prim != PIPE_PRIM_LINES &&
403 rast_prim != PIPE_PRIM_LINE_LOOP &&
404 rast_prim != PIPE_PRIM_LINE_STRIP &&
405 rast_prim != PIPE_PRIM_LINES_ADJACENCY &&
406 rast_prim != PIPE_PRIM_LINE_STRIP_ADJACENCY)
407 return;
408
409 if (rast_prim == sctx->last_rast_prim &&
410 rs->pa_sc_line_stipple == sctx->last_sc_line_stipple)
411 return;
412
413 radeon_set_context_reg(cs, R_028A0C_PA_SC_LINE_STIPPLE,
414 rs->pa_sc_line_stipple |
415 S_028A0C_AUTO_RESET_CNTL(rast_prim == PIPE_PRIM_LINES ? 1 :
416 rast_prim == PIPE_PRIM_LINE_STRIP ? 2 : 0));
417
418 sctx->last_rast_prim = rast_prim;
419 sctx->last_sc_line_stipple = rs->pa_sc_line_stipple;
420 }
421
422 static void si_emit_draw_registers(struct si_context *sctx,
423 const struct pipe_draw_info *info)
424 {
425 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
426 unsigned prim = si_conv_pipe_prim(info->mode);
427 unsigned gs_out_prim = si_conv_prim_to_gs_out(sctx->current_rast_prim);
428 unsigned ia_multi_vgt_param, ls_hs_config, num_patches = 0;
429
430 if (sctx->tes_shader.cso)
431 si_emit_derived_tess_state(sctx, info, &num_patches);
432
433 ia_multi_vgt_param = si_get_ia_multi_vgt_param(sctx, info, num_patches);
434 ls_hs_config = si_get_ls_hs_config(sctx, info, num_patches);
435
436 /* Draw state. */
437 if (prim != sctx->last_prim ||
438 ia_multi_vgt_param != sctx->last_multi_vgt_param ||
439 ls_hs_config != sctx->last_ls_hs_config) {
440 if (sctx->b.chip_class >= CIK) {
441 radeon_emit(cs, PKT3(PKT3_DRAW_PREAMBLE, 2, 0));
442 radeon_emit(cs, prim); /* VGT_PRIMITIVE_TYPE */
443 radeon_emit(cs, ia_multi_vgt_param); /* IA_MULTI_VGT_PARAM */
444 radeon_emit(cs, ls_hs_config); /* VGT_LS_HS_CONFIG */
445 } else {
446 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
447 radeon_set_context_reg(cs, R_028AA8_IA_MULTI_VGT_PARAM, ia_multi_vgt_param);
448 radeon_set_context_reg(cs, R_028B58_VGT_LS_HS_CONFIG, ls_hs_config);
449 }
450 sctx->last_prim = prim;
451 sctx->last_multi_vgt_param = ia_multi_vgt_param;
452 sctx->last_ls_hs_config = ls_hs_config;
453 }
454
455 if (gs_out_prim != sctx->last_gs_out_prim) {
456 radeon_set_context_reg(cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out_prim);
457 sctx->last_gs_out_prim = gs_out_prim;
458 }
459
460 /* Primitive restart. */
461 if (info->primitive_restart != sctx->last_primitive_restart_en) {
462 radeon_set_context_reg(cs, R_028A94_VGT_MULTI_PRIM_IB_RESET_EN, info->primitive_restart);
463 sctx->last_primitive_restart_en = info->primitive_restart;
464
465 if (info->primitive_restart &&
466 (info->restart_index != sctx->last_restart_index ||
467 sctx->last_restart_index == SI_RESTART_INDEX_UNKNOWN)) {
468 radeon_set_context_reg(cs, R_02840C_VGT_MULTI_PRIM_IB_RESET_INDX,
469 info->restart_index);
470 sctx->last_restart_index = info->restart_index;
471 }
472 }
473 }
474
475 static void si_emit_draw_packets(struct si_context *sctx,
476 const struct pipe_draw_info *info,
477 const struct pipe_index_buffer *ib)
478 {
479 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
480 unsigned sh_base_reg = sctx->shader_userdata.sh_base[PIPE_SHADER_VERTEX];
481 bool render_cond_bit = sctx->b.render_cond && !sctx->b.render_cond_force_off;
482
483 if (info->count_from_stream_output) {
484 struct r600_so_target *t =
485 (struct r600_so_target*)info->count_from_stream_output;
486 uint64_t va = t->buf_filled_size->gpu_address +
487 t->buf_filled_size_offset;
488
489 radeon_set_context_reg(cs, R_028B30_VGT_STRMOUT_DRAW_OPAQUE_VERTEX_STRIDE,
490 t->stride_in_dw);
491
492 radeon_emit(cs, PKT3(PKT3_COPY_DATA, 4, 0));
493 radeon_emit(cs, COPY_DATA_SRC_SEL(COPY_DATA_MEM) |
494 COPY_DATA_DST_SEL(COPY_DATA_REG) |
495 COPY_DATA_WR_CONFIRM);
496 radeon_emit(cs, va); /* src address lo */
497 radeon_emit(cs, va >> 32); /* src address hi */
498 radeon_emit(cs, R_028B2C_VGT_STRMOUT_DRAW_OPAQUE_BUFFER_FILLED_SIZE >> 2);
499 radeon_emit(cs, 0); /* unused */
500
501 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
502 t->buf_filled_size, RADEON_USAGE_READ,
503 RADEON_PRIO_SO_FILLED_SIZE);
504 }
505
506 /* draw packet */
507 if (info->indexed) {
508 radeon_emit(cs, PKT3(PKT3_INDEX_TYPE, 0, 0));
509
510 /* index type */
511 switch (ib->index_size) {
512 case 1:
513 radeon_emit(cs, V_028A7C_VGT_INDEX_8);
514 break;
515 case 2:
516 radeon_emit(cs, V_028A7C_VGT_INDEX_16 |
517 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
518 V_028A7C_VGT_DMA_SWAP_16_BIT : 0));
519 break;
520 case 4:
521 radeon_emit(cs, V_028A7C_VGT_INDEX_32 |
522 (SI_BIG_ENDIAN && sctx->b.chip_class <= CIK ?
523 V_028A7C_VGT_DMA_SWAP_32_BIT : 0));
524 break;
525 default:
526 assert(!"unreachable");
527 return;
528 }
529 }
530
531 if (!info->indirect) {
532 int base_vertex;
533
534 radeon_emit(cs, PKT3(PKT3_NUM_INSTANCES, 0, 0));
535 radeon_emit(cs, info->instance_count);
536
537 /* Base vertex and start instance. */
538 base_vertex = info->indexed ? info->index_bias : info->start;
539
540 if (base_vertex != sctx->last_base_vertex ||
541 sctx->last_base_vertex == SI_BASE_VERTEX_UNKNOWN ||
542 info->start_instance != sctx->last_start_instance ||
543 sh_base_reg != sctx->last_sh_base_reg) {
544 radeon_set_sh_reg_seq(cs, sh_base_reg + SI_SGPR_BASE_VERTEX * 4, 2);
545 radeon_emit(cs, base_vertex);
546 radeon_emit(cs, info->start_instance);
547
548 sctx->last_base_vertex = base_vertex;
549 sctx->last_start_instance = info->start_instance;
550 sctx->last_sh_base_reg = sh_base_reg;
551 }
552 } else {
553 si_invalidate_draw_sh_constants(sctx);
554
555 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
556 (struct r600_resource *)info->indirect,
557 RADEON_USAGE_READ, RADEON_PRIO_DRAW_INDIRECT);
558 }
559
560 if (info->indexed) {
561 uint32_t index_max_size = (ib->buffer->width0 - ib->offset) /
562 ib->index_size;
563 uint64_t index_va = r600_resource(ib->buffer)->gpu_address + ib->offset;
564
565 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx,
566 (struct r600_resource *)ib->buffer,
567 RADEON_USAGE_READ, RADEON_PRIO_INDEX_BUFFER);
568
569 if (info->indirect) {
570 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
571
572 assert(indirect_va % 8 == 0);
573 assert(index_va % 2 == 0);
574 assert(info->indirect_offset % 4 == 0);
575
576 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
577 radeon_emit(cs, 1);
578 radeon_emit(cs, indirect_va);
579 radeon_emit(cs, indirect_va >> 32);
580
581 radeon_emit(cs, PKT3(PKT3_INDEX_BASE, 1, 0));
582 radeon_emit(cs, index_va);
583 radeon_emit(cs, index_va >> 32);
584
585 radeon_emit(cs, PKT3(PKT3_INDEX_BUFFER_SIZE, 0, 0));
586 radeon_emit(cs, index_max_size);
587
588 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_INDIRECT, 3, render_cond_bit));
589 radeon_emit(cs, info->indirect_offset);
590 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
591 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
592 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
593 } else {
594 index_va += info->start * ib->index_size;
595
596 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_2, 4, render_cond_bit));
597 radeon_emit(cs, index_max_size);
598 radeon_emit(cs, index_va);
599 radeon_emit(cs, (index_va >> 32UL) & 0xFF);
600 radeon_emit(cs, info->count);
601 radeon_emit(cs, V_0287F0_DI_SRC_SEL_DMA);
602 }
603 } else {
604 if (info->indirect) {
605 uint64_t indirect_va = r600_resource(info->indirect)->gpu_address;
606
607 assert(indirect_va % 8 == 0);
608 assert(info->indirect_offset % 4 == 0);
609
610 radeon_emit(cs, PKT3(PKT3_SET_BASE, 2, 0));
611 radeon_emit(cs, 1);
612 radeon_emit(cs, indirect_va);
613 radeon_emit(cs, indirect_va >> 32);
614
615 radeon_emit(cs, PKT3(PKT3_DRAW_INDIRECT, 3, render_cond_bit));
616 radeon_emit(cs, info->indirect_offset);
617 radeon_emit(cs, (sh_base_reg + SI_SGPR_BASE_VERTEX * 4 - SI_SH_REG_OFFSET) >> 2);
618 radeon_emit(cs, (sh_base_reg + SI_SGPR_START_INSTANCE * 4 - SI_SH_REG_OFFSET) >> 2);
619 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX);
620 } else {
621 radeon_emit(cs, PKT3(PKT3_DRAW_INDEX_AUTO, 1, render_cond_bit));
622 radeon_emit(cs, info->count);
623 radeon_emit(cs, V_0287F0_DI_SRC_SEL_AUTO_INDEX |
624 S_0287F0_USE_OPAQUE(!!info->count_from_stream_output));
625 }
626 }
627 }
628
629 void si_emit_cache_flush(struct si_context *si_ctx, struct r600_atom *atom)
630 {
631 struct r600_common_context *sctx = &si_ctx->b;
632 struct radeon_winsys_cs *cs = sctx->gfx.cs;
633 uint32_t cp_coher_cntl = 0;
634
635 /* SI has a bug that it always flushes ICACHE and KCACHE if either
636 * bit is set. An alternative way is to write SQC_CACHES, but that
637 * doesn't seem to work reliably. Since the bug doesn't affect
638 * correctness (it only does more work than necessary) and
639 * the performance impact is likely negligible, there is no plan
640 * to add a workaround for it.
641 */
642
643 if (sctx->flags & SI_CONTEXT_INV_ICACHE)
644 cp_coher_cntl |= S_0085F0_SH_ICACHE_ACTION_ENA(1);
645 if (sctx->flags & SI_CONTEXT_INV_SMEM_L1)
646 cp_coher_cntl |= S_0085F0_SH_KCACHE_ACTION_ENA(1);
647
648 if (sctx->flags & SI_CONTEXT_INV_VMEM_L1)
649 cp_coher_cntl |= S_0085F0_TCL1_ACTION_ENA(1);
650 if (sctx->flags & SI_CONTEXT_INV_GLOBAL_L2) {
651 cp_coher_cntl |= S_0085F0_TC_ACTION_ENA(1);
652
653 if (sctx->chip_class >= VI)
654 cp_coher_cntl |= S_0301F0_TC_WB_ACTION_ENA(1);
655 }
656
657 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB) {
658 cp_coher_cntl |= S_0085F0_CB_ACTION_ENA(1) |
659 S_0085F0_CB0_DEST_BASE_ENA(1) |
660 S_0085F0_CB1_DEST_BASE_ENA(1) |
661 S_0085F0_CB2_DEST_BASE_ENA(1) |
662 S_0085F0_CB3_DEST_BASE_ENA(1) |
663 S_0085F0_CB4_DEST_BASE_ENA(1) |
664 S_0085F0_CB5_DEST_BASE_ENA(1) |
665 S_0085F0_CB6_DEST_BASE_ENA(1) |
666 S_0085F0_CB7_DEST_BASE_ENA(1);
667
668 /* Necessary for DCC */
669 if (sctx->chip_class >= VI) {
670 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE_EOP, 4, 0));
671 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_DATA_TS) |
672 EVENT_INDEX(5));
673 radeon_emit(cs, 0);
674 radeon_emit(cs, 0);
675 radeon_emit(cs, 0);
676 radeon_emit(cs, 0);
677 }
678 }
679 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB) {
680 cp_coher_cntl |= S_0085F0_DB_ACTION_ENA(1) |
681 S_0085F0_DB_DEST_BASE_ENA(1);
682 }
683
684 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB_META) {
685 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
686 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_CB_META) | EVENT_INDEX(0));
687 /* needed for wait for idle in SURFACE_SYNC */
688 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_CB);
689 }
690 if (sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB_META) {
691 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
692 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_AND_INV_DB_META) | EVENT_INDEX(0));
693 /* needed for wait for idle in SURFACE_SYNC */
694 assert(sctx->flags & SI_CONTEXT_FLUSH_AND_INV_DB);
695 }
696
697 /* Wait for shader engines to go idle.
698 * VS and PS waits are unnecessary if SURFACE_SYNC is going to wait
699 * for everything including CB/DB cache flushes.
700 */
701 if (!(sctx->flags & (SI_CONTEXT_FLUSH_AND_INV_CB |
702 SI_CONTEXT_FLUSH_AND_INV_DB))) {
703 if (sctx->flags & SI_CONTEXT_PS_PARTIAL_FLUSH) {
704 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
705 radeon_emit(cs, EVENT_TYPE(V_028A90_PS_PARTIAL_FLUSH) | EVENT_INDEX(4));
706 } else if (sctx->flags & SI_CONTEXT_VS_PARTIAL_FLUSH) {
707 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
708 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
709 }
710 }
711 if (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH) {
712 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
713 radeon_emit(cs, EVENT_TYPE(V_028A90_CS_PARTIAL_FLUSH | EVENT_INDEX(4)));
714 }
715
716 /* VGT state synchronization. */
717 if (sctx->flags & SI_CONTEXT_VGT_FLUSH) {
718 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
719 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
720 }
721 if (sctx->flags & SI_CONTEXT_VGT_STREAMOUT_SYNC) {
722 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
723 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_STREAMOUT_SYNC) | EVENT_INDEX(0));
724 }
725
726 /* Make sure ME is idle (it executes most packets) before continuing.
727 * This prevents read-after-write hazards between PFP and ME.
728 */
729 if (cp_coher_cntl || (sctx->flags & SI_CONTEXT_CS_PARTIAL_FLUSH)) {
730 radeon_emit(cs, PKT3(PKT3_PFP_SYNC_ME, 0, 0));
731 radeon_emit(cs, 0);
732 }
733
734 /* When one of the DEST_BASE flags is set, SURFACE_SYNC waits for idle.
735 * Therefore, it should be last. Done in PFP.
736 */
737 if (cp_coher_cntl) {
738 /* ACQUIRE_MEM is only required on a compute ring. */
739 radeon_emit(cs, PKT3(PKT3_SURFACE_SYNC, 3, 0));
740 radeon_emit(cs, cp_coher_cntl); /* CP_COHER_CNTL */
741 radeon_emit(cs, 0xffffffff); /* CP_COHER_SIZE */
742 radeon_emit(cs, 0); /* CP_COHER_BASE */
743 radeon_emit(cs, 0x0000000A); /* POLL_INTERVAL */
744 }
745
746 if (sctx->flags & R600_CONTEXT_START_PIPELINE_STATS) {
747 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
748 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_START) |
749 EVENT_INDEX(0));
750 } else if (sctx->flags & R600_CONTEXT_STOP_PIPELINE_STATS) {
751 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
752 radeon_emit(cs, EVENT_TYPE(V_028A90_PIPELINESTAT_STOP) |
753 EVENT_INDEX(0));
754 }
755
756 sctx->flags = 0;
757 }
758
759 static void si_get_draw_start_count(struct si_context *sctx,
760 const struct pipe_draw_info *info,
761 unsigned *start, unsigned *count)
762 {
763 if (info->indirect) {
764 struct r600_resource *indirect =
765 (struct r600_resource*)info->indirect;
766 int *data = r600_buffer_map_sync_with_rings(&sctx->b,
767 indirect, PIPE_TRANSFER_READ);
768 data += info->indirect_offset/sizeof(int);
769 *start = data[2];
770 *count = data[0];
771 } else {
772 *start = info->start;
773 *count = info->count;
774 }
775 }
776
777 void si_ce_pre_draw_synchronization(struct si_context *sctx)
778 {
779 if (sctx->ce_need_synchronization) {
780 radeon_emit(sctx->ce_ib, PKT3(PKT3_INCREMENT_CE_COUNTER, 0, 0));
781 radeon_emit(sctx->ce_ib, 1);
782
783 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_WAIT_ON_CE_COUNTER, 0, 0));
784 radeon_emit(sctx->b.gfx.cs, 1);
785 }
786 }
787
788 void si_ce_post_draw_synchronization(struct si_context *sctx)
789 {
790 if (sctx->ce_need_synchronization) {
791 radeon_emit(sctx->b.gfx.cs, PKT3(PKT3_INCREMENT_DE_COUNTER, 0, 0));
792 radeon_emit(sctx->b.gfx.cs, 0);
793
794 sctx->ce_need_synchronization = false;
795 }
796 }
797
798 void si_draw_vbo(struct pipe_context *ctx, const struct pipe_draw_info *info)
799 {
800 struct si_context *sctx = (struct si_context *)ctx;
801 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
802 struct pipe_index_buffer ib = {};
803 unsigned mask, dirty_fb_counter;
804
805 if (!info->count && !info->indirect &&
806 (info->indexed || !info->count_from_stream_output))
807 return;
808
809 if (!sctx->vs_shader.cso) {
810 assert(0);
811 return;
812 }
813 if (!sctx->ps_shader.cso && (!rs || !rs->rasterizer_discard)) {
814 assert(0);
815 return;
816 }
817 if (!!sctx->tes_shader.cso != (info->mode == PIPE_PRIM_PATCHES)) {
818 assert(0);
819 return;
820 }
821
822 /* Re-emit the framebuffer state if needed. */
823 dirty_fb_counter = p_atomic_read(&sctx->b.screen->dirty_fb_counter);
824 if (dirty_fb_counter != sctx->b.last_dirty_fb_counter) {
825 sctx->b.last_dirty_fb_counter = dirty_fb_counter;
826 sctx->framebuffer.dirty_cbufs |=
827 ((1 << sctx->framebuffer.state.nr_cbufs) - 1);
828 sctx->framebuffer.dirty_zsbuf = true;
829 si_mark_atom_dirty(sctx, &sctx->framebuffer.atom);
830 }
831
832 si_decompress_graphics_textures(sctx);
833
834 /* Set the rasterization primitive type.
835 *
836 * This must be done after si_decompress_textures, which can call
837 * draw_vbo recursively, and before si_update_shaders, which uses
838 * current_rast_prim for this draw_vbo call. */
839 if (sctx->gs_shader.cso)
840 sctx->current_rast_prim = sctx->gs_shader.cso->gs_output_prim;
841 else if (sctx->tes_shader.cso)
842 sctx->current_rast_prim =
843 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
844 else
845 sctx->current_rast_prim = info->mode;
846
847 if (!si_update_shaders(sctx) ||
848 !si_upload_graphics_shader_descriptors(sctx))
849 return;
850
851 if (info->indexed) {
852 /* Initialize the index buffer struct. */
853 pipe_resource_reference(&ib.buffer, sctx->index_buffer.buffer);
854 ib.user_buffer = sctx->index_buffer.user_buffer;
855 ib.index_size = sctx->index_buffer.index_size;
856 ib.offset = sctx->index_buffer.offset;
857
858 /* Translate or upload, if needed. */
859 /* 8-bit indices are supported on VI. */
860 if (sctx->b.chip_class <= CIK && ib.index_size == 1) {
861 struct pipe_resource *out_buffer = NULL;
862 unsigned out_offset, start, count, start_offset;
863 void *ptr;
864
865 si_get_draw_start_count(sctx, info, &start, &count);
866 start_offset = start * ib.index_size;
867
868 u_upload_alloc(sctx->b.uploader, start_offset, count * 2, 256,
869 &out_offset, &out_buffer, &ptr);
870 if (!out_buffer) {
871 pipe_resource_reference(&ib.buffer, NULL);
872 return;
873 }
874
875 util_shorten_ubyte_elts_to_userptr(&sctx->b.b, &ib, 0,
876 ib.offset + start_offset,
877 count, ptr);
878
879 pipe_resource_reference(&ib.buffer, NULL);
880 ib.user_buffer = NULL;
881 ib.buffer = out_buffer;
882 /* info->start will be added by the drawing code */
883 ib.offset = out_offset - start_offset;
884 ib.index_size = 2;
885 } else if (ib.user_buffer && !ib.buffer) {
886 unsigned start, count, start_offset;
887
888 si_get_draw_start_count(sctx, info, &start, &count);
889 start_offset = start * ib.index_size;
890
891 u_upload_data(sctx->b.uploader, start_offset, count * ib.index_size,
892 256, (char*)ib.user_buffer + start_offset,
893 &ib.offset, &ib.buffer);
894 if (!ib.buffer)
895 return;
896 /* info->start will be added by the drawing code */
897 ib.offset -= start_offset;
898 }
899 }
900
901 /* VI reads index buffers through TC L2. */
902 if (info->indexed && sctx->b.chip_class <= CIK &&
903 r600_resource(ib.buffer)->TC_L2_dirty) {
904 sctx->b.flags |= SI_CONTEXT_INV_GLOBAL_L2;
905 r600_resource(ib.buffer)->TC_L2_dirty = false;
906 }
907
908 /* Check flush flags. */
909 if (sctx->b.flags)
910 si_mark_atom_dirty(sctx, sctx->atoms.s.cache_flush);
911
912 si_need_cs_space(sctx);
913
914 /* Emit states. */
915 mask = sctx->dirty_atoms;
916 while (mask) {
917 struct r600_atom *atom = sctx->atoms.array[u_bit_scan(&mask)];
918
919 atom->emit(&sctx->b, atom);
920 }
921 sctx->dirty_atoms = 0;
922
923 si_pm4_emit_dirty(sctx);
924 si_emit_scratch_reloc(sctx);
925 si_emit_rasterizer_prim_state(sctx);
926 si_emit_draw_registers(sctx, info);
927
928 si_ce_pre_draw_synchronization(sctx);
929
930 si_emit_draw_packets(sctx, info, &ib);
931
932 si_ce_post_draw_synchronization(sctx);
933
934 if (sctx->trace_buf)
935 si_trace_emit(sctx);
936
937 /* Workaround for a VGT hang when streamout is enabled.
938 * It must be done after drawing. */
939 if ((sctx->b.family == CHIP_HAWAII ||
940 sctx->b.family == CHIP_TONGA ||
941 sctx->b.family == CHIP_FIJI) &&
942 r600_get_strmout_en(&sctx->b)) {
943 sctx->b.flags |= SI_CONTEXT_VGT_STREAMOUT_SYNC;
944 }
945
946 /* Set the depth buffer as dirty. */
947 if (sctx->framebuffer.state.zsbuf) {
948 struct pipe_surface *surf = sctx->framebuffer.state.zsbuf;
949 struct r600_texture *rtex = (struct r600_texture *)surf->texture;
950
951 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
952
953 if (rtex->surface.flags & RADEON_SURF_SBUFFER)
954 rtex->stencil_dirty_level_mask |= 1 << surf->u.tex.level;
955 }
956 if (sctx->framebuffer.compressed_cb_mask) {
957 struct pipe_surface *surf;
958 struct r600_texture *rtex;
959 unsigned mask = sctx->framebuffer.compressed_cb_mask;
960
961 do {
962 unsigned i = u_bit_scan(&mask);
963 surf = sctx->framebuffer.state.cbufs[i];
964 rtex = (struct r600_texture*)surf->texture;
965
966 rtex->dirty_level_mask |= 1 << surf->u.tex.level;
967 } while (mask);
968 }
969
970 pipe_resource_reference(&ib.buffer, NULL);
971 sctx->b.num_draw_calls++;
972 }
973
974 void si_trace_emit(struct si_context *sctx)
975 {
976 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
977
978 sctx->trace_id++;
979 radeon_add_to_buffer_list(&sctx->b, &sctx->b.gfx, sctx->trace_buf,
980 RADEON_USAGE_READWRITE, RADEON_PRIO_TRACE);
981 radeon_emit(cs, PKT3(PKT3_WRITE_DATA, 3, 0));
982 radeon_emit(cs, S_370_DST_SEL(V_370_MEMORY_SYNC) |
983 S_370_WR_CONFIRM(1) |
984 S_370_ENGINE_SEL(V_370_ME));
985 radeon_emit(cs, sctx->trace_buf->gpu_address);
986 radeon_emit(cs, sctx->trace_buf->gpu_address >> 32);
987 radeon_emit(cs, sctx->trace_id);
988 radeon_emit(cs, PKT3(PKT3_NOP, 0, 0));
989 radeon_emit(cs, SI_ENCODE_TRACE_POINT(sctx->trace_id));
990 }