radeonsi: remove redundant si_shader_info::shader_buffers_declared
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "ac_exp_param.h"
26 #include "ac_shader_util.h"
27 #include "compiler/nir/nir_serialize.h"
28 #include "nir/tgsi_to_nir.h"
29 #include "si_build_pm4.h"
30 #include "sid.h"
31 #include "util/crc32.h"
32 #include "util/disk_cache.h"
33 #include "util/hash_table.h"
34 #include "util/mesa-sha1.h"
35 #include "util/u_async_debug.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38 #include "tgsi/tgsi_from_mesa.h"
39
40 /* SHADER_CACHE */
41
42 /**
43 * Return the IR key for the shader cache.
44 */
45 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
46 unsigned char ir_sha1_cache_key[20])
47 {
48 struct blob blob = {};
49 unsigned ir_size;
50 void *ir_binary;
51
52 if (sel->nir_binary) {
53 ir_binary = sel->nir_binary;
54 ir_size = sel->nir_size;
55 } else {
56 assert(sel->nir);
57
58 blob_init(&blob);
59 nir_serialize(&blob, sel->nir, true);
60 ir_binary = blob.data;
61 ir_size = blob.size;
62 }
63
64 /* These settings affect the compilation, but they are not derived
65 * from the input shader IR.
66 */
67 unsigned shader_variant_flags = 0;
68
69 if (ngg)
70 shader_variant_flags |= 1 << 0;
71 if (sel->nir)
72 shader_variant_flags |= 1 << 1;
73 if (si_get_wave_size(sel->screen, sel->info.stage, ngg, es, false, false) == 32)
74 shader_variant_flags |= 1 << 2;
75 if (sel->info.stage == MESA_SHADER_FRAGMENT && sel->info.uses_derivatives && sel->info.uses_kill &&
76 sel->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
77 shader_variant_flags |= 1 << 3;
78
79 /* This varies depending on whether compute-based culling is enabled. */
80 shader_variant_flags |= sel->screen->num_vbos_in_user_sgprs << 4;
81
82 struct mesa_sha1 ctx;
83 _mesa_sha1_init(&ctx);
84 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
85 _mesa_sha1_update(&ctx, ir_binary, ir_size);
86 if (sel->info.stage == MESA_SHADER_VERTEX || sel->info.stage == MESA_SHADER_TESS_EVAL ||
87 sel->info.stage == MESA_SHADER_GEOMETRY)
88 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
89 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
90
91 if (ir_binary == blob.data)
92 blob_finish(&blob);
93 }
94
95 /** Copy "data" to "ptr" and return the next dword following copied data. */
96 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
97 {
98 /* data may be NULL if size == 0 */
99 if (size)
100 memcpy(ptr, data, size);
101 ptr += DIV_ROUND_UP(size, 4);
102 return ptr;
103 }
104
105 /** Read data from "ptr". Return the next dword following the data. */
106 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
107 {
108 memcpy(data, ptr, size);
109 ptr += DIV_ROUND_UP(size, 4);
110 return ptr;
111 }
112
113 /**
114 * Write the size as uint followed by the data. Return the next dword
115 * following the copied data.
116 */
117 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
118 {
119 *ptr++ = size;
120 return write_data(ptr, data, size);
121 }
122
123 /**
124 * Read the size as uint followed by the data. Return both via parameters.
125 * Return the next dword following the data.
126 */
127 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
128 {
129 *size = *ptr++;
130 assert(*data == NULL);
131 if (!*size)
132 return ptr;
133 *data = malloc(*size);
134 return read_data(ptr, *data, *size);
135 }
136
137 /**
138 * Return the shader binary in a buffer. The first 4 bytes contain its size
139 * as integer.
140 */
141 static void *si_get_shader_binary(struct si_shader *shader)
142 {
143 /* There is always a size of data followed by the data itself. */
144 unsigned llvm_ir_size =
145 shader->binary.llvm_ir_string ? strlen(shader->binary.llvm_ir_string) + 1 : 0;
146
147 /* Refuse to allocate overly large buffers and guard against integer
148 * overflow. */
149 if (shader->binary.elf_size > UINT_MAX / 4 || llvm_ir_size > UINT_MAX / 4)
150 return NULL;
151
152 unsigned size = 4 + /* total size */
153 4 + /* CRC32 of the data below */
154 align(sizeof(shader->config), 4) + align(sizeof(shader->info), 4) + 4 +
155 align(shader->binary.elf_size, 4) + 4 + align(llvm_ir_size, 4);
156 void *buffer = CALLOC(1, size);
157 uint32_t *ptr = (uint32_t *)buffer;
158
159 if (!buffer)
160 return NULL;
161
162 *ptr++ = size;
163 ptr++; /* CRC32 is calculated at the end. */
164
165 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
166 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
167 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
168 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
169 assert((char *)ptr - (char *)buffer == size);
170
171 /* Compute CRC32. */
172 ptr = (uint32_t *)buffer;
173 ptr++;
174 *ptr = util_hash_crc32(ptr + 1, size - 8);
175
176 return buffer;
177 }
178
179 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
180 {
181 uint32_t *ptr = (uint32_t *)binary;
182 uint32_t size = *ptr++;
183 uint32_t crc32 = *ptr++;
184 unsigned chunk_size;
185 unsigned elf_size;
186
187 if (util_hash_crc32(ptr, size - 8) != crc32) {
188 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
189 return false;
190 }
191
192 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
193 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
194 ptr = read_chunk(ptr, (void **)&shader->binary.elf_buffer, &elf_size);
195 shader->binary.elf_size = elf_size;
196 ptr = read_chunk(ptr, (void **)&shader->binary.llvm_ir_string, &chunk_size);
197
198 return true;
199 }
200
201 /**
202 * Insert a shader into the cache. It's assumed the shader is not in the cache.
203 * Use si_shader_cache_load_shader before calling this.
204 */
205 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
206 struct si_shader *shader, bool insert_into_disk_cache)
207 {
208 void *hw_binary;
209 struct hash_entry *entry;
210 uint8_t key[CACHE_KEY_SIZE];
211
212 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
213 if (entry)
214 return; /* already added */
215
216 hw_binary = si_get_shader_binary(shader);
217 if (!hw_binary)
218 return;
219
220 if (_mesa_hash_table_insert(sscreen->shader_cache, mem_dup(ir_sha1_cache_key, 20), hw_binary) ==
221 NULL) {
222 FREE(hw_binary);
223 return;
224 }
225
226 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
227 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, key);
228 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary, *((uint32_t *)hw_binary), NULL);
229 }
230 }
231
232 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
233 struct si_shader *shader)
234 {
235 struct hash_entry *entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
236
237 if (entry) {
238 if (si_load_shader_binary(shader, entry->data)) {
239 p_atomic_inc(&sscreen->num_memory_shader_cache_hits);
240 return true;
241 }
242 }
243 p_atomic_inc(&sscreen->num_memory_shader_cache_misses);
244
245 if (!sscreen->disk_shader_cache)
246 return false;
247
248 unsigned char sha1[CACHE_KEY_SIZE];
249 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, sha1);
250
251 size_t binary_size;
252 uint8_t *buffer = disk_cache_get(sscreen->disk_shader_cache, sha1, &binary_size);
253 if (buffer) {
254 if (binary_size >= sizeof(uint32_t) && *((uint32_t *)buffer) == binary_size) {
255 if (si_load_shader_binary(shader, buffer)) {
256 free(buffer);
257 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, false);
258 p_atomic_inc(&sscreen->num_disk_shader_cache_hits);
259 return true;
260 }
261 } else {
262 /* Something has gone wrong discard the item from the cache and
263 * rebuild/link from source.
264 */
265 assert(!"Invalid radeonsi shader disk cache item!");
266 disk_cache_remove(sscreen->disk_shader_cache, sha1);
267 }
268 }
269
270 free(buffer);
271 p_atomic_inc(&sscreen->num_disk_shader_cache_misses);
272 return false;
273 }
274
275 static uint32_t si_shader_cache_key_hash(const void *key)
276 {
277 /* Take the first dword of SHA1. */
278 return *(uint32_t *)key;
279 }
280
281 static bool si_shader_cache_key_equals(const void *a, const void *b)
282 {
283 /* Compare SHA1s. */
284 return memcmp(a, b, 20) == 0;
285 }
286
287 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
288 {
289 FREE((void *)entry->key);
290 FREE(entry->data);
291 }
292
293 bool si_init_shader_cache(struct si_screen *sscreen)
294 {
295 (void)simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
296 sscreen->shader_cache =
297 _mesa_hash_table_create(NULL, si_shader_cache_key_hash, si_shader_cache_key_equals);
298
299 return sscreen->shader_cache != NULL;
300 }
301
302 void si_destroy_shader_cache(struct si_screen *sscreen)
303 {
304 if (sscreen->shader_cache)
305 _mesa_hash_table_destroy(sscreen->shader_cache, si_destroy_shader_cache_entry);
306 simple_mtx_destroy(&sscreen->shader_cache_mutex);
307 }
308
309 /* SHADER STATES */
310
311 static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shader_selector *tes,
312 struct si_pm4_state *pm4)
313 {
314 const struct si_shader_info *info = &tes->info;
315 unsigned tes_prim_mode = info->base.tess.primitive_mode;
316 unsigned tes_spacing = info->base.tess.spacing;
317 bool tes_vertex_order_cw = !info->base.tess.ccw;
318 bool tes_point_mode = info->base.tess.point_mode;
319 unsigned type, partitioning, topology, distribution_mode;
320
321 switch (tes_prim_mode) {
322 case GL_LINES:
323 type = V_028B6C_TESS_ISOLINE;
324 break;
325 case GL_TRIANGLES:
326 type = V_028B6C_TESS_TRIANGLE;
327 break;
328 case GL_QUADS:
329 type = V_028B6C_TESS_QUAD;
330 break;
331 default:
332 assert(0);
333 return;
334 }
335
336 switch (tes_spacing) {
337 case TESS_SPACING_FRACTIONAL_ODD:
338 partitioning = V_028B6C_PART_FRAC_ODD;
339 break;
340 case TESS_SPACING_FRACTIONAL_EVEN:
341 partitioning = V_028B6C_PART_FRAC_EVEN;
342 break;
343 case TESS_SPACING_EQUAL:
344 partitioning = V_028B6C_PART_INTEGER;
345 break;
346 default:
347 assert(0);
348 return;
349 }
350
351 if (tes_point_mode)
352 topology = V_028B6C_OUTPUT_POINT;
353 else if (tes_prim_mode == GL_LINES)
354 topology = V_028B6C_OUTPUT_LINE;
355 else if (tes_vertex_order_cw)
356 /* for some reason, this must be the other way around */
357 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
358 else
359 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
360
361 if (sscreen->info.has_distributed_tess) {
362 if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10)
363 distribution_mode = V_028B6C_TRAPEZOIDS;
364 else
365 distribution_mode = V_028B6C_DONUTS;
366 } else
367 distribution_mode = V_028B6C_NO_DIST;
368
369 assert(pm4->shader);
370 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
371 S_028B6C_TOPOLOGY(topology) |
372 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
373 }
374
375 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
376 * whether the "fractional odd" tessellation spacing is used.
377 *
378 * Possible VGT configurations and which state should set the register:
379 *
380 * Reg set in | VGT shader configuration | Value
381 * ------------------------------------------------------
382 * VS as VS | VS | 30
383 * VS as ES | ES -> GS -> VS | 30
384 * TES as VS | LS -> HS -> VS | 14 or 30
385 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
386 *
387 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
388 */
389 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_shader_selector *sel,
390 struct si_shader *shader, struct si_pm4_state *pm4)
391 {
392 if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.chip_class >= GFX10)
393 return;
394
395 /* VS as VS, or VS as ES: */
396 if ((sel->info.stage == MESA_SHADER_VERTEX &&
397 (!shader || (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
398 /* TES as VS, or TES as ES: */
399 sel->info.stage == MESA_SHADER_TESS_EVAL) {
400 unsigned vtx_reuse_depth = 30;
401
402 if (sel->info.stage == MESA_SHADER_TESS_EVAL &&
403 sel->info.base.tess.spacing == TESS_SPACING_FRACTIONAL_ODD)
404 vtx_reuse_depth = 14;
405
406 assert(pm4->shader);
407 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
408 }
409 }
410
411 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
412 {
413 if (shader->pm4)
414 si_pm4_clear_state(shader->pm4);
415 else
416 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
417
418 if (shader->pm4) {
419 shader->pm4->shader = shader;
420 return shader->pm4;
421 } else {
422 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
423 return NULL;
424 }
425 }
426
427 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
428 unsigned num_always_on_user_sgprs)
429 {
430 struct si_shader_selector *vs =
431 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
432 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
433
434 /* 1 SGPR is reserved for the vertex buffer pointer. */
435 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
436
437 if (num_vbos_in_user_sgprs)
438 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
439
440 /* Add the pointer to VBO descriptors. */
441 return num_always_on_user_sgprs + 1;
442 }
443
444 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
445 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_shader *shader,
446 bool legacy_vs_prim_id)
447 {
448 assert(shader->selector->info.stage == MESA_SHADER_VERTEX ||
449 (shader->previous_stage_sel && shader->previous_stage_sel->info.stage == MESA_SHADER_VERTEX));
450
451 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
452 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
453 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
454 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or
455 * InstanceID)
456 */
457 bool is_ls = shader->selector->info.stage == MESA_SHADER_TESS_CTRL || shader->key.as_ls;
458
459 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
460 return 3;
461 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
462 return 2;
463 else if (is_ls || shader->info.uses_instanceid)
464 return 1;
465 else
466 return 0;
467 }
468
469 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
470 {
471 struct si_pm4_state *pm4;
472 uint64_t va;
473
474 assert(sscreen->info.chip_class <= GFX8);
475
476 pm4 = si_get_shader_pm4_state(shader);
477 if (!pm4)
478 return;
479
480 va = shader->bo->gpu_address;
481 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
482 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
483
484 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
485 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
486 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
487 S_00B528_DX10_CLAMP(1) | S_00B528_FLOAT_MODE(shader->config.float_mode);
488 shader->config.rsrc2 =
489 S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
490 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
491 }
492
493 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
494 {
495 struct si_pm4_state *pm4;
496 uint64_t va;
497
498 pm4 = si_get_shader_pm4_state(shader);
499 if (!pm4)
500 return;
501
502 va = shader->bo->gpu_address;
503
504 if (sscreen->info.chip_class >= GFX9) {
505 if (sscreen->info.chip_class >= GFX10) {
506 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
507 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
508 } else {
509 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
510 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
511 }
512
513 unsigned num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
514
515 shader->config.rsrc2 = S_00B42C_USER_SGPR(num_user_sgprs) |
516 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
517
518 if (sscreen->info.chip_class >= GFX10)
519 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
520 else
521 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
522 } else {
523 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
524 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
525
526 shader->config.rsrc2 = S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) | S_00B42C_OC_LDS_EN(1) |
527 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
528 }
529
530 si_pm4_set_reg(
531 pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
532 S_00B428_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
533 (sscreen->info.chip_class <= GFX9 ? S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8)
534 : 0) |
535 S_00B428_DX10_CLAMP(1) | S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
536 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
537 S_00B428_FLOAT_MODE(shader->config.float_mode) |
538 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9
539 ? si_get_vs_vgpr_comp_cnt(sscreen, shader, false)
540 : 0));
541
542 if (sscreen->info.chip_class <= GFX8) {
543 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2);
544 }
545 }
546
547 static void si_emit_shader_es(struct si_context *sctx)
548 {
549 struct si_shader *shader = sctx->queued.named.es->shader;
550 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
551
552 if (!shader)
553 return;
554
555 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
556 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
557 shader->selector->esgs_itemsize / 4);
558
559 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
560 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
561 shader->vgt_tf_param);
562
563 if (shader->vgt_vertex_reuse_block_cntl)
564 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
565 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
566 shader->vgt_vertex_reuse_block_cntl);
567
568 if (initial_cdw != sctx->gfx_cs->current.cdw)
569 sctx->context_roll = true;
570 }
571
572 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
573 {
574 struct si_pm4_state *pm4;
575 unsigned num_user_sgprs;
576 unsigned vgpr_comp_cnt;
577 uint64_t va;
578 unsigned oc_lds_en;
579
580 assert(sscreen->info.chip_class <= GFX8);
581
582 pm4 = si_get_shader_pm4_state(shader);
583 if (!pm4)
584 return;
585
586 pm4->atom.emit = si_emit_shader_es;
587 va = shader->bo->gpu_address;
588
589 if (shader->selector->info.stage == MESA_SHADER_VERTEX) {
590 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
591 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
592 } else if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) {
593 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
594 num_user_sgprs = SI_TES_NUM_USER_SGPR;
595 } else
596 unreachable("invalid shader selector type");
597
598 oc_lds_en = shader->selector->info.stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
599
600 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
601 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
602 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
603 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
604 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
605 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B328_DX10_CLAMP(1) |
606 S_00B328_FLOAT_MODE(shader->config.float_mode));
607 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
608 S_00B32C_USER_SGPR(num_user_sgprs) | S_00B32C_OC_LDS_EN(oc_lds_en) |
609 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
610
611 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
612 si_set_tesseval_regs(sscreen, shader->selector, pm4);
613
614 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
615 }
616
617 void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *gs,
618 struct gfx9_gs_info *out)
619 {
620 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
621 unsigned input_prim = gs->info.base.gs.input_primitive;
622 bool uses_adjacency =
623 input_prim >= PIPE_PRIM_LINES_ADJACENCY && input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
624
625 /* All these are in dwords: */
626 /* We can't allow using the whole LDS, because GS waves compete with
627 * other shader stages for LDS space. */
628 const unsigned max_lds_size = 8 * 1024;
629 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
630 unsigned esgs_lds_size;
631
632 /* All these are per subgroup: */
633 const unsigned max_out_prims = 32 * 1024;
634 const unsigned max_es_verts = 255;
635 const unsigned ideal_gs_prims = 64;
636 unsigned max_gs_prims, gs_prims;
637 unsigned min_es_verts, es_verts, worst_case_es_verts;
638
639 if (uses_adjacency || gs_num_invocations > 1)
640 max_gs_prims = 127 / gs_num_invocations;
641 else
642 max_gs_prims = 255;
643
644 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
645 * Make sure we don't go over the maximum value.
646 */
647 if (gs->gs_max_out_vertices > 0) {
648 max_gs_prims =
649 MIN2(max_gs_prims, max_out_prims / (gs->gs_max_out_vertices * gs_num_invocations));
650 }
651 assert(max_gs_prims > 0);
652
653 /* If the primitive has adjacency, halve the number of vertices
654 * that will be reused in multiple primitives.
655 */
656 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
657
658 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
659 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
660
661 /* Compute ESGS LDS size based on the worst case number of ES vertices
662 * needed to create the target number of GS prims per subgroup.
663 */
664 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
665
666 /* If total LDS usage is too big, refactor partitions based on ratio
667 * of ESGS item sizes.
668 */
669 if (esgs_lds_size > max_lds_size) {
670 /* Our target GS Prims Per Subgroup was too large. Calculate
671 * the maximum number of GS Prims Per Subgroup that will fit
672 * into LDS, capped by the maximum that the hardware can support.
673 */
674 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)), max_gs_prims);
675 assert(gs_prims > 0);
676 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
677
678 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
679 assert(esgs_lds_size <= max_lds_size);
680 }
681
682 /* Now calculate remaining ESGS information. */
683 if (esgs_lds_size)
684 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
685 else
686 es_verts = max_es_verts;
687
688 /* Vertices for adjacency primitives are not always reused, so restore
689 * it for ES_VERTS_PER_SUBGRP.
690 */
691 min_es_verts = gs->gs_input_verts_per_prim;
692
693 /* For normal primitives, the VGT only checks if they are past the ES
694 * verts per subgroup after allocating a full GS primitive and if they
695 * are, kick off a new subgroup. But if those additional ES verts are
696 * unique (e.g. not reused) we need to make sure there is enough LDS
697 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
698 */
699 es_verts -= min_es_verts - 1;
700
701 out->es_verts_per_subgroup = es_verts;
702 out->gs_prims_per_subgroup = gs_prims;
703 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
704 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup * gs->gs_max_out_vertices;
705 out->esgs_ring_size = esgs_lds_size;
706
707 assert(out->max_prims_per_subgroup <= max_out_prims);
708 }
709
710 static void si_emit_shader_gs(struct si_context *sctx)
711 {
712 struct si_shader *shader = sctx->queued.named.gs->shader;
713 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
714
715 if (!shader)
716 return;
717
718 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
719 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
720 radeon_opt_set_context_reg3(
721 sctx, R_028A60_VGT_GSVS_RING_OFFSET_1, SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
722 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1, shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
723 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
724
725 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
726 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
727 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
728 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
729
730 /* R_028B38_VGT_GS_MAX_VERT_OUT */
731 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
732 shader->ctx_reg.gs.vgt_gs_max_vert_out);
733
734 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
735 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
736 radeon_opt_set_context_reg4(
737 sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE, SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
738 shader->ctx_reg.gs.vgt_gs_vert_itemsize, shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
739 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2, shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
740
741 /* R_028B90_VGT_GS_INSTANCE_CNT */
742 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
743 shader->ctx_reg.gs.vgt_gs_instance_cnt);
744
745 if (sctx->chip_class >= GFX9) {
746 /* R_028A44_VGT_GS_ONCHIP_CNTL */
747 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
748 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
749 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
750 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
751 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
752 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
753 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
754 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
755 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
756 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
757
758 if (shader->key.part.gs.es->info.stage == MESA_SHADER_TESS_EVAL)
759 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
760 shader->vgt_tf_param);
761 if (shader->vgt_vertex_reuse_block_cntl)
762 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
763 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
764 shader->vgt_vertex_reuse_block_cntl);
765 }
766
767 if (initial_cdw != sctx->gfx_cs->current.cdw)
768 sctx->context_roll = true;
769 }
770
771 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
772 {
773 struct si_shader_selector *sel = shader->selector;
774 const ubyte *num_components = sel->info.num_stream_output_components;
775 unsigned gs_num_invocations = sel->gs_num_invocations;
776 struct si_pm4_state *pm4;
777 uint64_t va;
778 unsigned max_stream = sel->max_gs_stream;
779 unsigned offset;
780
781 pm4 = si_get_shader_pm4_state(shader);
782 if (!pm4)
783 return;
784
785 pm4->atom.emit = si_emit_shader_gs;
786
787 offset = num_components[0] * sel->gs_max_out_vertices;
788 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
789
790 if (max_stream >= 1)
791 offset += num_components[1] * sel->gs_max_out_vertices;
792 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
793
794 if (max_stream >= 2)
795 offset += num_components[2] * sel->gs_max_out_vertices;
796 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
797
798 if (max_stream >= 3)
799 offset += num_components[3] * sel->gs_max_out_vertices;
800 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
801
802 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
803 assert(offset < (1 << 15));
804
805 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
806
807 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
808 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
809 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
810 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
811
812 shader->ctx_reg.gs.vgt_gs_instance_cnt =
813 S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0);
814
815 va = shader->bo->gpu_address;
816
817 if (sscreen->info.chip_class >= GFX9) {
818 unsigned input_prim = sel->info.base.gs.input_primitive;
819 gl_shader_stage es_stage = shader->key.part.gs.es->info.stage;
820 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
821
822 if (es_stage == MESA_SHADER_VERTEX) {
823 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
824 } else if (es_stage == MESA_SHADER_TESS_EVAL)
825 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
826 else
827 unreachable("invalid shader selector type");
828
829 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
830 * VGPR[0:4] are always loaded.
831 */
832 if (sel->info.uses_invocationid)
833 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
834 else if (sel->info.uses_primid)
835 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
836 else if (input_prim >= PIPE_PRIM_TRIANGLES)
837 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
838 else
839 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
840
841 unsigned num_user_sgprs;
842 if (es_stage == MESA_SHADER_VERTEX)
843 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
844 else
845 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
846
847 if (sscreen->info.chip_class >= GFX10) {
848 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
849 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
850 } else {
851 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
852 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
853 }
854
855 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) |
856 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
857 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
858 S_00B228_FLOAT_MODE(shader->config.float_mode) |
859 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
860 uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) |
861 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
862 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL) |
863 S_00B22C_LDS_SIZE(shader->config.lds_size) |
864 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
865
866 if (sscreen->info.chip_class >= GFX10) {
867 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
868 } else {
869 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
870 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
871 }
872
873 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
874 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
875
876 if (sscreen->info.chip_class >= GFX10) {
877 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
878 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
879 }
880
881 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
882 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
883 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
884 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
885 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
886 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
887 shader->ctx_reg.gs.vgt_esgs_ring_itemsize = shader->key.part.gs.es->esgs_itemsize / 4;
888
889 if (es_stage == MESA_SHADER_TESS_EVAL)
890 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
891
892 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es, NULL, pm4);
893 } else {
894 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
895 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
896
897 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
898 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
899 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
900 S_00B228_DX10_CLAMP(1) | S_00B228_FLOAT_MODE(shader->config.float_mode));
901 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
902 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
903 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
904 }
905 }
906
907 static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
908 {
909 enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
910
911 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
912 sctx->tracked_regs.reg_value[reg] != value) {
913 struct radeon_cmdbuf *cs = sctx->gfx_cs;
914
915 if (sctx->chip_class == GFX10) {
916 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
917 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
918 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
919 }
920
921 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
922
923 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
924 sctx->tracked_regs.reg_value[reg] = value;
925 }
926 }
927
928 /* Common tail code for NGG primitive shaders. */
929 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader *shader,
930 unsigned initial_cdw)
931 {
932 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
933 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
934 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
935 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
936 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
937 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
938 shader->ctx_reg.ngg.vgt_primitiveid_en);
939 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
940 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
941 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
942 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
943 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
944 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
945 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
946 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
947 shader->ctx_reg.ngg.spi_vs_out_config);
948 radeon_opt_set_context_reg2(
949 sctx, R_028708_SPI_SHADER_IDX_FORMAT, SI_TRACKED_SPI_SHADER_IDX_FORMAT,
950 shader->ctx_reg.ngg.spi_shader_idx_format, shader->ctx_reg.ngg.spi_shader_pos_format);
951 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
952 shader->ctx_reg.ngg.pa_cl_vte_cntl);
953 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
954 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
955
956 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
957 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, shader->pa_cl_vs_out_cntl,
958 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
959
960 if (initial_cdw != sctx->gfx_cs->current.cdw)
961 sctx->context_roll = true;
962
963 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
964 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
965 }
966
967 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
968 {
969 struct si_shader *shader = sctx->queued.named.gs->shader;
970 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
971
972 if (!shader)
973 return;
974
975 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
976 }
977
978 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
979 {
980 struct si_shader *shader = sctx->queued.named.gs->shader;
981 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
982
983 if (!shader)
984 return;
985
986 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
987 shader->vgt_tf_param);
988
989 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
990 }
991
992 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
993 {
994 struct si_shader *shader = sctx->queued.named.gs->shader;
995 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
996
997 if (!shader)
998 return;
999
1000 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1001 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1002
1003 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1004 }
1005
1006 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1007 {
1008 struct si_shader *shader = sctx->queued.named.gs->shader;
1009 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1010
1011 if (!shader)
1012 return;
1013
1014 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1015 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1016 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1017 shader->vgt_tf_param);
1018
1019 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1020 }
1021
1022 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1023 {
1024 if (gs->info.stage == MESA_SHADER_GEOMETRY)
1025 return gs->info.base.gs.input_primitive;
1026
1027 if (gs->info.stage == MESA_SHADER_TESS_EVAL) {
1028 if (gs->info.base.tess.point_mode)
1029 return PIPE_PRIM_POINTS;
1030 if (gs->info.base.tess.primitive_mode == GL_LINES)
1031 return PIPE_PRIM_LINES;
1032 return PIPE_PRIM_TRIANGLES;
1033 }
1034
1035 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1036 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1037 }
1038
1039 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1040 {
1041 bool misc_vec_ena = sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1042 sel->info.writes_layer || sel->info.writes_viewport_index;
1043 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1044 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1045 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1046 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1047 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1048 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1049 }
1050
1051 /**
1052 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1053 * in NGG mode.
1054 */
1055 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1056 {
1057 const struct si_shader_selector *gs_sel = shader->selector;
1058 const struct si_shader_info *gs_info = &gs_sel->info;
1059 const gl_shader_stage gs_stage = shader->selector->info.stage;
1060 const struct si_shader_selector *es_sel =
1061 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1062 const struct si_shader_info *es_info = &es_sel->info;
1063 const gl_shader_stage es_stage = es_sel->info.stage;
1064 unsigned num_user_sgprs;
1065 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1066 uint64_t va;
1067 bool window_space = gs_info->stage == MESA_SHADER_VERTEX ?
1068 gs_info->base.vs.window_space_position : 0;
1069 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1070 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1071 unsigned input_prim = si_get_input_prim(gs_sel);
1072 bool break_wave_at_eoi = false;
1073 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1074 if (!pm4)
1075 return;
1076
1077 if (es_stage == MESA_SHADER_TESS_EVAL) {
1078 pm4->atom.emit = gs_stage == MESA_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1079 : gfx10_emit_shader_ngg_tess_nogs;
1080 } else {
1081 pm4->atom.emit = gs_stage == MESA_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1082 : gfx10_emit_shader_ngg_notess_nogs;
1083 }
1084
1085 va = shader->bo->gpu_address;
1086
1087 if (es_stage == MESA_SHADER_VERTEX) {
1088 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1089
1090 if (es_info->base.vs.blit_sgprs_amd) {
1091 num_user_sgprs =
1092 SI_SGPR_VS_BLIT_DATA + es_info->base.vs.blit_sgprs_amd;
1093 } else {
1094 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1095 }
1096 } else {
1097 assert(es_stage == MESA_SHADER_TESS_EVAL);
1098 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1099 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1100
1101 if (es_enable_prim_id || gs_info->uses_primid)
1102 break_wave_at_eoi = true;
1103 }
1104
1105 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1106 * VGPR[0:4] are always loaded.
1107 *
1108 * Vertex shaders always need to load VGPR3, because they need to
1109 * pass edge flags for decomposed primitives (such as quads) to the PA
1110 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1111 */
1112 if (gs_info->uses_invocationid ||
1113 (gs_stage == MESA_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1114 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1115 else if ((gs_stage == MESA_SHADER_GEOMETRY && gs_info->uses_primid) ||
1116 (gs_stage == MESA_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1117 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1118 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1119 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1120 else
1121 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1122
1123 unsigned wave_size = si_get_shader_wave_size(shader);
1124
1125 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1126 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1127 si_pm4_set_reg(
1128 pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1129 S_00B228_VGPRS((shader->config.num_vgprs - 1) / (wave_size == 32 ? 8 : 4)) |
1130 S_00B228_FLOAT_MODE(shader->config.float_mode) | S_00B228_DX10_CLAMP(1) |
1131 S_00B228_MEM_ORDERED(1) | S_00B228_WGP_MODE(1) |
1132 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1133 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1134 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1135 S_00B22C_USER_SGPR(num_user_sgprs) |
1136 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1137 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1138 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL) |
1139 S_00B22C_LDS_SIZE(shader->config.lds_size));
1140
1141 /* Determine LATE_ALLOC_GS. */
1142 unsigned num_cu_per_sh = sscreen->info.min_good_cu_per_sa;
1143 unsigned late_alloc_wave64; /* The limit is per SA. */
1144
1145 /* For Wave32, the hw will launch twice the number of late
1146 * alloc waves, so 1 == 2x wave32.
1147 *
1148 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1149 */
1150 if (sscreen->info.family == CHIP_NAVI14 || !sscreen->info.use_late_alloc)
1151 late_alloc_wave64 = 0;
1152 else if (num_cu_per_sh <= 6)
1153 late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
1154 else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
1155 late_alloc_wave64 = (num_cu_per_sh - 2) * 6;
1156 else
1157 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
1158
1159 /* Limit LATE_ALLOC_GS for prevent a hang (hw bug). */
1160 if (sscreen->info.chip_class == GFX10)
1161 late_alloc_wave64 = MIN2(late_alloc_wave64, 64);
1162
1163 si_pm4_set_reg(
1164 pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1165 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64));
1166
1167 nparams = MAX2(shader->info.nr_param_exports, 1);
1168 shader->ctx_reg.ngg.spi_vs_out_config =
1169 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1170 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1171
1172 shader->ctx_reg.ngg.spi_shader_idx_format =
1173 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1174 shader->ctx_reg.ngg.spi_shader_pos_format =
1175 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1176 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1177 : V_02870C_SPI_SHADER_NONE) |
1178 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1179 : V_02870C_SPI_SHADER_NONE) |
1180 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1181 : V_02870C_SPI_SHADER_NONE);
1182
1183 shader->ctx_reg.ngg.vgt_primitiveid_en =
1184 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1185 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1186 gs_sel->info.writes_primid);
1187
1188 if (gs_stage == MESA_SHADER_GEOMETRY) {
1189 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1190 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1191 } else {
1192 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1193 }
1194
1195 if (es_stage == MESA_SHADER_TESS_EVAL)
1196 si_set_tesseval_regs(sscreen, es_sel, pm4);
1197
1198 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1199 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1200 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1201 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1202 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1203 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1204 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl = S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1205 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1206 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1207 S_028B90_CNT(gs_num_invocations) | S_028B90_ENABLE(gs_num_invocations > 1) |
1208 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(shader->ngg.max_vert_out_per_gs_instance);
1209
1210 /* Always output hw-generated edge flags and pass them via the prim
1211 * export to prevent drawing lines on internal edges of decomposed
1212 * primitives (such as quads) with polygon mode = lines. Only VS needs
1213 * this.
1214 */
1215 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1216 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_stage == MESA_SHADER_VERTEX) |
1217 /* Reuse for NGG. */
1218 S_028838_VERTEX_REUSE_DEPTH(sscreen->info.chip_class >= GFX10_3 ? 30 : 0);
1219 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1220
1221 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1222 float oversub_pc_factor = 0.25;
1223
1224 if (shader->key.opt.ngg_culling) {
1225 /* Be more aggressive with NGG culling. */
1226 if (shader->info.nr_param_exports > 4)
1227 oversub_pc_factor = 1;
1228 else if (shader->info.nr_param_exports > 2)
1229 oversub_pc_factor = 0.75;
1230 else
1231 oversub_pc_factor = 0.5;
1232 }
1233
1234 unsigned oversub_pc_lines = sscreen->info.pc_lines * oversub_pc_factor;
1235 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
1236 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1237
1238 if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
1239 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1240 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims * 3);
1241 } else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP) {
1242 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1243 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims + 2);
1244 } else {
1245 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1246 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1247 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1248
1249 /* Bug workaround for a possible hang with non-tessellation cases.
1250 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1251 *
1252 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1253 */
1254 if ((sscreen->info.chip_class == GFX10) &&
1255 (es_stage == MESA_SHADER_VERTEX || gs_stage == MESA_SHADER_VERTEX) && /* = no tess */
1256 shader->ngg.hw_max_esverts != 256) {
1257 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1258
1259 if (shader->ngg.hw_max_esverts > 5) {
1260 shader->ge_cntl |= S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1261 }
1262 }
1263 }
1264
1265 if (window_space) {
1266 shader->ctx_reg.ngg.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1267 } else {
1268 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1269 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1270 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1271 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1272 }
1273 }
1274
1275 static void si_emit_shader_vs(struct si_context *sctx)
1276 {
1277 struct si_shader *shader = sctx->queued.named.vs->shader;
1278 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1279
1280 if (!shader)
1281 return;
1282
1283 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE, SI_TRACKED_VGT_GS_MODE,
1284 shader->ctx_reg.vs.vgt_gs_mode);
1285 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
1286 shader->ctx_reg.vs.vgt_primitiveid_en);
1287
1288 if (sctx->chip_class <= GFX8) {
1289 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
1290 shader->ctx_reg.vs.vgt_reuse_off);
1291 }
1292
1293 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
1294 shader->ctx_reg.vs.spi_vs_out_config);
1295
1296 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1297 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1298 shader->ctx_reg.vs.spi_shader_pos_format);
1299
1300 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1301 shader->ctx_reg.vs.pa_cl_vte_cntl);
1302
1303 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
1304 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1305 shader->vgt_tf_param);
1306
1307 if (shader->vgt_vertex_reuse_block_cntl)
1308 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1309 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1310 shader->vgt_vertex_reuse_block_cntl);
1311
1312 /* Required programming for tessellation. (legacy pipeline only) */
1313 if (sctx->chip_class >= GFX10 && shader->selector->info.stage == MESA_SHADER_TESS_EVAL) {
1314 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1315 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1316 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1317 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1318 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1319 }
1320
1321 if (sctx->chip_class >= GFX10) {
1322 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1323 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, shader->pa_cl_vs_out_cntl,
1324 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1325 }
1326
1327 if (initial_cdw != sctx->gfx_cs->current.cdw)
1328 sctx->context_roll = true;
1329
1330 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1331 if (sctx->chip_class >= GFX10)
1332 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
1333 }
1334
1335 /**
1336 * Compute the state for \p shader, which will run as a vertex shader on the
1337 * hardware.
1338 *
1339 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1340 * is the copy shader.
1341 */
1342 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1343 struct si_shader_selector *gs)
1344 {
1345 const struct si_shader_info *info = &shader->selector->info;
1346 struct si_pm4_state *pm4;
1347 unsigned num_user_sgprs, vgpr_comp_cnt;
1348 uint64_t va;
1349 unsigned nparams, oc_lds_en;
1350 bool window_space = info->stage == MESA_SHADER_VERTEX ?
1351 info->base.vs.window_space_position : 0;
1352 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1353
1354 pm4 = si_get_shader_pm4_state(shader);
1355 if (!pm4)
1356 return;
1357
1358 pm4->atom.emit = si_emit_shader_vs;
1359
1360 /* We always write VGT_GS_MODE in the VS state, because every switch
1361 * between different shader pipelines involving a different GS or no
1362 * GS at all involves a switch of the VS (different GS use different
1363 * copy shaders). On the other hand, when the API switches from a GS to
1364 * no GS and then back to the same GS used originally, the GS state is
1365 * not sent again.
1366 */
1367 if (!gs) {
1368 unsigned mode = V_028A40_GS_OFF;
1369
1370 /* PrimID needs GS scenario A. */
1371 if (enable_prim_id)
1372 mode = V_028A40_GS_SCENARIO_A;
1373
1374 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1375 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1376 } else {
1377 shader->ctx_reg.vs.vgt_gs_mode =
1378 ac_vgt_gs_mode(gs->gs_max_out_vertices, sscreen->info.chip_class);
1379 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1380 }
1381
1382 if (sscreen->info.chip_class <= GFX8) {
1383 /* Reuse needs to be set off if we write oViewport. */
1384 shader->ctx_reg.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(info->writes_viewport_index);
1385 }
1386
1387 va = shader->bo->gpu_address;
1388
1389 if (gs) {
1390 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1391 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1392 } else if (shader->selector->info.stage == MESA_SHADER_VERTEX) {
1393 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1394
1395 if (info->base.vs.blit_sgprs_amd) {
1396 num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->base.vs.blit_sgprs_amd;
1397 } else {
1398 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1399 }
1400 } else if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) {
1401 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1402 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1403 } else
1404 unreachable("invalid shader selector type");
1405
1406 /* VS is required to export at least one param. */
1407 nparams = MAX2(shader->info.nr_param_exports, 1);
1408 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1409
1410 if (sscreen->info.chip_class >= GFX10) {
1411 shader->ctx_reg.vs.spi_vs_out_config |=
1412 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1413 }
1414
1415 shader->ctx_reg.vs.spi_shader_pos_format =
1416 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1417 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1418 : V_02870C_SPI_SHADER_NONE) |
1419 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1420 : V_02870C_SPI_SHADER_NONE) |
1421 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1422 : V_02870C_SPI_SHADER_NONE);
1423 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
1424 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1425 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1426
1427 oc_lds_en = shader->selector->info.stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
1428
1429 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1430 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1431
1432 uint32_t rsrc1 =
1433 S_00B128_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1434 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B128_DX10_CLAMP(1) |
1435 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1436 S_00B128_FLOAT_MODE(shader->config.float_mode);
1437 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) | S_00B12C_OC_LDS_EN(oc_lds_en) |
1438 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1439
1440 if (sscreen->info.chip_class >= GFX10)
1441 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1442 else if (sscreen->info.chip_class == GFX9)
1443 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1444
1445 if (sscreen->info.chip_class <= GFX9)
1446 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1447
1448 if (!sscreen->use_ngg_streamout) {
1449 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1450 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1451 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1452 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1453 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1454 }
1455
1456 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1457 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1458
1459 if (window_space)
1460 shader->ctx_reg.vs.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1461 else
1462 shader->ctx_reg.vs.pa_cl_vte_cntl =
1463 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1464 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1465 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1466
1467 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
1468 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1469
1470 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1471 }
1472
1473 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1474 {
1475 struct si_shader_info *info = &ps->selector->info;
1476 unsigned num_colors = !!(info->colors_read & 0x0f) + !!(info->colors_read & 0xf0);
1477 unsigned num_interp =
1478 ps->selector->info.num_inputs + (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1479
1480 assert(num_interp <= 32);
1481 return MIN2(num_interp, 32);
1482 }
1483
1484 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1485 {
1486 unsigned spi_shader_col_format = shader->key.part.ps.epilog.spi_shader_col_format;
1487 unsigned value = 0, num_mrts = 0;
1488 unsigned i, num_targets = (util_last_bit(spi_shader_col_format) + 3) / 4;
1489
1490 /* Remove holes in spi_shader_col_format. */
1491 for (i = 0; i < num_targets; i++) {
1492 unsigned spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
1493
1494 if (spi_format) {
1495 value |= spi_format << (num_mrts * 4);
1496 num_mrts++;
1497 }
1498 }
1499
1500 return value;
1501 }
1502
1503 static void si_emit_shader_ps(struct si_context *sctx)
1504 {
1505 struct si_shader *shader = sctx->queued.named.ps->shader;
1506 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1507
1508 if (!shader)
1509 return;
1510
1511 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1512 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
1513 shader->ctx_reg.ps.spi_ps_input_ena,
1514 shader->ctx_reg.ps.spi_ps_input_addr);
1515
1516 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
1517 shader->ctx_reg.ps.spi_baryc_cntl);
1518 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
1519 shader->ctx_reg.ps.spi_ps_in_control);
1520
1521 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1522 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
1523 shader->ctx_reg.ps.spi_shader_z_format,
1524 shader->ctx_reg.ps.spi_shader_col_format);
1525
1526 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
1527 shader->ctx_reg.ps.cb_shader_mask);
1528
1529 if (initial_cdw != sctx->gfx_cs->current.cdw)
1530 sctx->context_roll = true;
1531 }
1532
1533 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1534 {
1535 struct si_shader_info *info = &shader->selector->info;
1536 struct si_pm4_state *pm4;
1537 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1538 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1539 uint64_t va;
1540 unsigned input_ena = shader->config.spi_ps_input_ena;
1541
1542 /* we need to enable at least one of them, otherwise we hang the GPU */
1543 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) || G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1544 G_0286CC_PERSP_CENTROID_ENA(input_ena) || G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1545 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) || G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1546 G_0286CC_LINEAR_CENTROID_ENA(input_ena) || G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1547 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1548 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) || G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1549 G_0286CC_PERSP_CENTER_ENA(input_ena) || G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1550 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1551
1552 /* Validate interpolation optimization flags (read as implications). */
1553 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1554 (G_0286CC_PERSP_CENTER_ENA(input_ena) && G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1555 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1556 (G_0286CC_LINEAR_CENTER_ENA(input_ena) && G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1557 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1558 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1559 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1560 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1561 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1562 (!G_0286CC_PERSP_CENTER_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1563 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1564 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1565
1566 /* Validate cases when the optimizations are off (read as implications). */
1567 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1568 !G_0286CC_PERSP_CENTER_ENA(input_ena) || !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1569 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1570 !G_0286CC_LINEAR_CENTER_ENA(input_ena) || !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1571
1572 pm4 = si_get_shader_pm4_state(shader);
1573 if (!pm4)
1574 return;
1575
1576 pm4->atom.emit = si_emit_shader_ps;
1577
1578 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1579 * Possible vaules:
1580 * 0 -> Position = pixel center
1581 * 1 -> Position = pixel centroid
1582 * 2 -> Position = at sample position
1583 *
1584 * From GLSL 4.5 specification, section 7.1:
1585 * "The variable gl_FragCoord is available as an input variable from
1586 * within fragment shaders and it holds the window relative coordinates
1587 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1588 * value can be for any location within the pixel, or one of the
1589 * fragment samples. The use of centroid does not further restrict
1590 * this value to be inside the current primitive."
1591 *
1592 * Meaning that centroid has no effect and we can return anything within
1593 * the pixel. Thus, return the value at sample position, because that's
1594 * the most accurate one shaders can get.
1595 */
1596 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1597
1598 if (info->base.fs.pixel_center_integer)
1599 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1600
1601 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1602 cb_shader_mask = ac_get_cb_shader_mask(shader->key.part.ps.epilog.spi_shader_col_format);
1603
1604 /* Ensure that some export memory is always allocated, for two reasons:
1605 *
1606 * 1) Correctness: The hardware ignores the EXEC mask if no export
1607 * memory is allocated, so KILL and alpha test do not work correctly
1608 * without this.
1609 * 2) Performance: Every shader needs at least a NULL export, even when
1610 * it writes no color/depth output. The NULL export instruction
1611 * stalls without this setting.
1612 *
1613 * Don't add this to CB_SHADER_MASK.
1614 *
1615 * GFX10 supports pixel shaders without exports by setting both
1616 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1617 * instructions if any are present.
1618 */
1619 if ((sscreen->info.chip_class <= GFX9 || info->uses_kill ||
1620 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1621 !spi_shader_col_format && !info->writes_z && !info->writes_stencil &&
1622 !info->writes_samplemask)
1623 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1624
1625 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1626 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1627
1628 /* Set interpolation controls. */
1629 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1630 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1631
1632 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1633 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1634 shader->ctx_reg.ps.spi_shader_z_format =
1635 ac_get_spi_shader_z_format(info->writes_z, info->writes_stencil, info->writes_samplemask);
1636 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1637 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1638
1639 va = shader->bo->gpu_address;
1640 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1641 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1642
1643 uint32_t rsrc1 =
1644 S_00B028_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1645 S_00B028_DX10_CLAMP(1) | S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1646 S_00B028_FLOAT_MODE(shader->config.float_mode);
1647
1648 if (sscreen->info.chip_class < GFX10) {
1649 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1650 }
1651
1652 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1653 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1654 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1655 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1656 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1657 }
1658
1659 static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader *shader)
1660 {
1661 switch (shader->selector->info.stage) {
1662 case MESA_SHADER_VERTEX:
1663 if (shader->key.as_ls)
1664 si_shader_ls(sscreen, shader);
1665 else if (shader->key.as_es)
1666 si_shader_es(sscreen, shader);
1667 else if (shader->key.as_ngg)
1668 gfx10_shader_ngg(sscreen, shader);
1669 else
1670 si_shader_vs(sscreen, shader, NULL);
1671 break;
1672 case MESA_SHADER_TESS_CTRL:
1673 si_shader_hs(sscreen, shader);
1674 break;
1675 case MESA_SHADER_TESS_EVAL:
1676 if (shader->key.as_es)
1677 si_shader_es(sscreen, shader);
1678 else if (shader->key.as_ngg)
1679 gfx10_shader_ngg(sscreen, shader);
1680 else
1681 si_shader_vs(sscreen, shader, NULL);
1682 break;
1683 case MESA_SHADER_GEOMETRY:
1684 if (shader->key.as_ngg)
1685 gfx10_shader_ngg(sscreen, shader);
1686 else
1687 si_shader_gs(sscreen, shader);
1688 break;
1689 case MESA_SHADER_FRAGMENT:
1690 si_shader_ps(sscreen, shader);
1691 break;
1692 default:
1693 assert(0);
1694 }
1695 }
1696
1697 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1698 {
1699 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1700 return sctx->queued.named.dsa->alpha_func;
1701 }
1702
1703 void si_shader_selector_key_vs(struct si_context *sctx, struct si_shader_selector *vs,
1704 struct si_shader_key *key, struct si_vs_prolog_bits *prolog_key)
1705 {
1706 if (!sctx->vertex_elements || vs->info.base.vs.blit_sgprs_amd)
1707 return;
1708
1709 struct si_vertex_elements *elts = sctx->vertex_elements;
1710
1711 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1712 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1713 prolog_key->unpack_instance_id_from_vertex_id = sctx->prim_discard_cs_instancing;
1714
1715 /* Prefer a monolithic shader to allow scheduling divisions around
1716 * VBO loads. */
1717 if (prolog_key->instance_divisor_is_fetched)
1718 key->opt.prefer_mono = 1;
1719
1720 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1721 unsigned count_mask = (1 << count) - 1;
1722 unsigned fix = elts->fix_fetch_always & count_mask;
1723 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1724
1725 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1726 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1727 while (mask) {
1728 unsigned i = u_bit_scan(&mask);
1729 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1730 unsigned vbidx = elts->vertex_buffer_index[i];
1731 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1732 unsigned align_mask = (1 << log_hw_load_size) - 1;
1733 if (vb->buffer_offset & align_mask || vb->stride & align_mask) {
1734 fix |= 1 << i;
1735 opencode |= 1 << i;
1736 }
1737 }
1738 }
1739
1740 while (fix) {
1741 unsigned i = u_bit_scan(&fix);
1742 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1743 }
1744 key->mono.vs_fetch_opencode = opencode;
1745 }
1746
1747 static void si_shader_selector_key_hw_vs(struct si_context *sctx, struct si_shader_selector *vs,
1748 struct si_shader_key *key)
1749 {
1750 struct si_shader_selector *ps = sctx->ps_shader.cso;
1751
1752 key->opt.clip_disable = sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1753 (vs->info.clipdist_writemask || vs->info.writes_clipvertex) &&
1754 !vs->info.culldist_writemask;
1755
1756 /* Find out if PS is disabled. */
1757 bool ps_disabled = true;
1758 if (ps) {
1759 bool ps_modifies_zs = ps->info.uses_kill || ps->info.writes_z || ps->info.writes_stencil ||
1760 ps->info.writes_samplemask ||
1761 sctx->queued.named.blend->alpha_to_coverage ||
1762 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1763 unsigned ps_colormask = si_get_total_colormask(sctx);
1764
1765 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1766 (!ps_colormask && !ps_modifies_zs && !ps->info.writes_memory);
1767 }
1768
1769 /* Find out which VS outputs aren't used by the PS. */
1770 uint64_t outputs_written = vs->outputs_written_before_ps;
1771 uint64_t inputs_read = 0;
1772
1773 /* Ignore outputs that are not passed from VS to PS. */
1774 outputs_written &= ~((1ull << si_shader_io_get_unique_index(VARYING_SLOT_POS, true)) |
1775 (1ull << si_shader_io_get_unique_index(VARYING_SLOT_PSIZ, true)) |
1776 (1ull << si_shader_io_get_unique_index(VARYING_SLOT_CLIP_VERTEX, true)));
1777
1778 if (!ps_disabled) {
1779 inputs_read = ps->inputs_read;
1780 }
1781
1782 uint64_t linked = outputs_written & inputs_read;
1783
1784 key->opt.kill_outputs = ~linked & outputs_written;
1785 key->opt.ngg_culling = sctx->ngg_culling;
1786 }
1787
1788 /* Compute the key for the hw shader variant */
1789 static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_shader_selector *sel,
1790 union si_vgt_stages_key stages_key,
1791 struct si_shader_key *key)
1792 {
1793 struct si_context *sctx = (struct si_context *)ctx;
1794
1795 memset(key, 0, sizeof(*key));
1796
1797 switch (sel->info.stage) {
1798 case MESA_SHADER_VERTEX:
1799 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1800
1801 if (sctx->tes_shader.cso)
1802 key->as_ls = 1;
1803 else if (sctx->gs_shader.cso) {
1804 key->as_es = 1;
1805 key->as_ngg = stages_key.u.ngg;
1806 } else {
1807 key->as_ngg = stages_key.u.ngg;
1808 si_shader_selector_key_hw_vs(sctx, sel, key);
1809
1810 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1811 key->mono.u.vs_export_prim_id = 1;
1812 }
1813 break;
1814 case MESA_SHADER_TESS_CTRL:
1815 if (sctx->chip_class >= GFX9) {
1816 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.tcs.ls_prolog);
1817 key->part.tcs.ls = sctx->vs_shader.cso;
1818
1819 /* When the LS VGPR fix is needed, monolithic shaders
1820 * can:
1821 * - avoid initializing EXEC in both the LS prolog
1822 * and the LS main part when !vs_needs_prolog
1823 * - remove the fixup for unused input VGPRs
1824 */
1825 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1826
1827 /* The LS output / HS input layout can be communicated
1828 * directly instead of via user SGPRs for merged LS-HS.
1829 * The LS VGPR fix prefers this too.
1830 */
1831 key->opt.prefer_mono = 1;
1832 }
1833
1834 key->part.tcs.epilog.prim_mode =
1835 sctx->tes_shader.cso->info.base.tess.primitive_mode;
1836 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1837 sel->info.tessfactors_are_def_in_all_invocs;
1838 key->part.tcs.epilog.tes_reads_tess_factors = sctx->tes_shader.cso->info.reads_tess_factors;
1839
1840 if (sel == sctx->fixed_func_tcs_shader.cso)
1841 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1842 break;
1843 case MESA_SHADER_TESS_EVAL:
1844 key->as_ngg = stages_key.u.ngg;
1845
1846 if (sctx->gs_shader.cso)
1847 key->as_es = 1;
1848 else {
1849 si_shader_selector_key_hw_vs(sctx, sel, key);
1850
1851 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1852 key->mono.u.vs_export_prim_id = 1;
1853 }
1854 break;
1855 case MESA_SHADER_GEOMETRY:
1856 if (sctx->chip_class >= GFX9) {
1857 if (sctx->tes_shader.cso) {
1858 key->part.gs.es = sctx->tes_shader.cso;
1859 } else {
1860 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.gs.vs_prolog);
1861 key->part.gs.es = sctx->vs_shader.cso;
1862 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1863 }
1864
1865 key->as_ngg = stages_key.u.ngg;
1866
1867 /* Merged ES-GS can have unbalanced wave usage.
1868 *
1869 * ES threads are per-vertex, while GS threads are
1870 * per-primitive. So without any amplification, there
1871 * are fewer GS threads than ES threads, which can result
1872 * in empty (no-op) GS waves. With too much amplification,
1873 * there are more GS threads than ES threads, which
1874 * can result in empty (no-op) ES waves.
1875 *
1876 * Non-monolithic shaders are implemented by setting EXEC
1877 * at the beginning of shader parts, and don't jump to
1878 * the end if EXEC is 0.
1879 *
1880 * Monolithic shaders use conditional blocks, so they can
1881 * jump and skip empty waves of ES or GS. So set this to
1882 * always use optimized variants, which are monolithic.
1883 */
1884 key->opt.prefer_mono = 1;
1885 }
1886 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1887 break;
1888 case MESA_SHADER_FRAGMENT: {
1889 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1890 struct si_state_blend *blend = sctx->queued.named.blend;
1891
1892 if (sel->info.color0_writes_all_cbufs &&
1893 sel->info.colors_written == 0x1)
1894 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1895
1896 /* Select the shader color format based on whether
1897 * blending or alpha are needed.
1898 */
1899 key->part.ps.epilog.spi_shader_col_format =
1900 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1901 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1902 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1903 sctx->framebuffer.spi_shader_col_format_blend) |
1904 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1905 sctx->framebuffer.spi_shader_col_format_alpha) |
1906 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1907 sctx->framebuffer.spi_shader_col_format);
1908 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1909
1910 /* The output for dual source blending should have
1911 * the same format as the first output.
1912 */
1913 if (blend->dual_src_blend) {
1914 key->part.ps.epilog.spi_shader_col_format |=
1915 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1916 }
1917
1918 /* If alpha-to-coverage is enabled, we have to export alpha
1919 * even if there is no color buffer.
1920 */
1921 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) && blend->alpha_to_coverage)
1922 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1923
1924 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1925 * to the range supported by the type if a channel has less
1926 * than 16 bits and the export format is 16_ABGR.
1927 */
1928 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1929 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1930 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1931 }
1932
1933 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1934 if (!key->part.ps.epilog.last_cbuf) {
1935 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1936 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1937 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1938 }
1939
1940 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1941 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1942
1943 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1944 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1945
1946 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one && rs->multisample_enable;
1947
1948 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1949 key->part.ps.epilog.poly_line_smoothing =
1950 ((is_poly && rs->poly_smooth) || (is_line && rs->line_smooth)) &&
1951 sctx->framebuffer.nr_samples <= 1;
1952 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1953
1954 if (sctx->ps_iter_samples > 1 && sel->info.reads_samplemask) {
1955 key->part.ps.prolog.samplemask_log_ps_iter = util_logbase2(sctx->ps_iter_samples);
1956 }
1957
1958 if (rs->force_persample_interp && rs->multisample_enable &&
1959 sctx->framebuffer.nr_samples > 1 && sctx->ps_iter_samples > 1) {
1960 key->part.ps.prolog.force_persp_sample_interp =
1961 sel->info.uses_persp_center || sel->info.uses_persp_centroid;
1962
1963 key->part.ps.prolog.force_linear_sample_interp =
1964 sel->info.uses_linear_center || sel->info.uses_linear_centroid;
1965 } else if (rs->multisample_enable && sctx->framebuffer.nr_samples > 1) {
1966 key->part.ps.prolog.bc_optimize_for_persp =
1967 sel->info.uses_persp_center && sel->info.uses_persp_centroid;
1968 key->part.ps.prolog.bc_optimize_for_linear =
1969 sel->info.uses_linear_center && sel->info.uses_linear_centroid;
1970 } else {
1971 /* Make sure SPI doesn't compute more than 1 pair
1972 * of (i,j), which is the optimization here. */
1973 key->part.ps.prolog.force_persp_center_interp = sel->info.uses_persp_center +
1974 sel->info.uses_persp_centroid +
1975 sel->info.uses_persp_sample >
1976 1;
1977
1978 key->part.ps.prolog.force_linear_center_interp = sel->info.uses_linear_center +
1979 sel->info.uses_linear_centroid +
1980 sel->info.uses_linear_sample >
1981 1;
1982
1983 if (sel->info.uses_persp_opcode_interp_sample ||
1984 sel->info.uses_linear_opcode_interp_sample)
1985 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1986 }
1987
1988 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1989
1990 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1991 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1992 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1993 struct pipe_resource *tex = cb0->texture;
1994
1995 /* 1D textures are allocated and used as 2D on GFX9. */
1996 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1997 key->mono.u.ps.fbfetch_is_1D =
1998 sctx->chip_class != GFX9 &&
1999 (tex->target == PIPE_TEXTURE_1D || tex->target == PIPE_TEXTURE_1D_ARRAY);
2000 key->mono.u.ps.fbfetch_layered =
2001 tex->target == PIPE_TEXTURE_1D_ARRAY || tex->target == PIPE_TEXTURE_2D_ARRAY ||
2002 tex->target == PIPE_TEXTURE_CUBE || tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2003 tex->target == PIPE_TEXTURE_3D;
2004 }
2005 break;
2006 }
2007 default:
2008 assert(0);
2009 }
2010
2011 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2012 memset(&key->opt, 0, sizeof(key->opt));
2013 }
2014
2015 static void si_build_shader_variant(struct si_shader *shader, int thread_index, bool low_priority)
2016 {
2017 struct si_shader_selector *sel = shader->selector;
2018 struct si_screen *sscreen = sel->screen;
2019 struct ac_llvm_compiler *compiler;
2020 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2021
2022 if (thread_index >= 0) {
2023 if (low_priority) {
2024 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2025 compiler = &sscreen->compiler_lowp[thread_index];
2026 } else {
2027 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2028 compiler = &sscreen->compiler[thread_index];
2029 }
2030 if (!debug->async)
2031 debug = NULL;
2032 } else {
2033 assert(!low_priority);
2034 compiler = shader->compiler_ctx_state.compiler;
2035 }
2036
2037 if (!compiler->passes)
2038 si_init_compiler(sscreen, compiler);
2039
2040 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2041 PRINT_ERR("Failed to build shader variant (type=%u)\n", sel->info.stage);
2042 shader->compilation_failed = true;
2043 return;
2044 }
2045
2046 if (shader->compiler_ctx_state.is_debug_context) {
2047 FILE *f = open_memstream(&shader->shader_log, &shader->shader_log_size);
2048 if (f) {
2049 si_shader_dump(sscreen, shader, NULL, f, false);
2050 fclose(f);
2051 }
2052 }
2053
2054 si_shader_init_pm4_state(sscreen, shader);
2055 }
2056
2057 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2058 {
2059 struct si_shader *shader = (struct si_shader *)job;
2060
2061 assert(thread_index >= 0);
2062
2063 si_build_shader_variant(shader, thread_index, true);
2064 }
2065
2066 static const struct si_shader_key zeroed;
2067
2068 static bool si_check_missing_main_part(struct si_screen *sscreen, struct si_shader_selector *sel,
2069 struct si_compiler_ctx_state *compiler_state,
2070 struct si_shader_key *key)
2071 {
2072 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2073
2074 if (!*mainp) {
2075 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2076
2077 if (!main_part)
2078 return false;
2079
2080 /* We can leave the fence as permanently signaled because the
2081 * main part becomes visible globally only after it has been
2082 * compiled. */
2083 util_queue_fence_init(&main_part->ready);
2084
2085 main_part->selector = sel;
2086 main_part->key.as_es = key->as_es;
2087 main_part->key.as_ls = key->as_ls;
2088 main_part->key.as_ngg = key->as_ngg;
2089 main_part->is_monolithic = false;
2090
2091 if (!si_compile_shader(sscreen, compiler_state->compiler, main_part,
2092 &compiler_state->debug)) {
2093 FREE(main_part);
2094 return false;
2095 }
2096 *mainp = main_part;
2097 }
2098 return true;
2099 }
2100
2101 /**
2102 * Select a shader variant according to the shader key.
2103 *
2104 * \param optimized_or_none If the key describes an optimized shader variant and
2105 * the compilation isn't finished, don't select any
2106 * shader and return an error.
2107 */
2108 int si_shader_select_with_key(struct si_screen *sscreen, struct si_shader_ctx_state *state,
2109 struct si_compiler_ctx_state *compiler_state,
2110 struct si_shader_key *key, int thread_index, bool optimized_or_none)
2111 {
2112 struct si_shader_selector *sel = state->cso;
2113 struct si_shader_selector *previous_stage_sel = NULL;
2114 struct si_shader *current = state->current;
2115 struct si_shader *iter, *shader = NULL;
2116
2117 again:
2118 /* Check if we don't need to change anything.
2119 * This path is also used for most shaders that don't need multiple
2120 * variants, it will cost just a computation of the key and this
2121 * test. */
2122 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0)) {
2123 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2124 if (current->is_optimized) {
2125 if (optimized_or_none)
2126 return -1;
2127
2128 memset(&key->opt, 0, sizeof(key->opt));
2129 goto current_not_ready;
2130 }
2131
2132 util_queue_fence_wait(&current->ready);
2133 }
2134
2135 return current->compilation_failed ? -1 : 0;
2136 }
2137 current_not_ready:
2138
2139 /* This must be done before the mutex is locked, because async GS
2140 * compilation calls this function too, and therefore must enter
2141 * the mutex first.
2142 *
2143 * Only wait if we are in a draw call. Don't wait if we are
2144 * in a compiler thread.
2145 */
2146 if (thread_index < 0)
2147 util_queue_fence_wait(&sel->ready);
2148
2149 simple_mtx_lock(&sel->mutex);
2150
2151 /* Find the shader variant. */
2152 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2153 /* Don't check the "current" shader. We checked it above. */
2154 if (current != iter && memcmp(&iter->key, key, sizeof(*key)) == 0) {
2155 simple_mtx_unlock(&sel->mutex);
2156
2157 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2158 /* If it's an optimized shader and its compilation has
2159 * been started but isn't done, use the unoptimized
2160 * shader so as not to cause a stall due to compilation.
2161 */
2162 if (iter->is_optimized) {
2163 if (optimized_or_none)
2164 return -1;
2165 memset(&key->opt, 0, sizeof(key->opt));
2166 goto again;
2167 }
2168
2169 util_queue_fence_wait(&iter->ready);
2170 }
2171
2172 if (iter->compilation_failed) {
2173 return -1; /* skip the draw call */
2174 }
2175
2176 state->current = iter;
2177 return 0;
2178 }
2179 }
2180
2181 /* Build a new shader. */
2182 shader = CALLOC_STRUCT(si_shader);
2183 if (!shader) {
2184 simple_mtx_unlock(&sel->mutex);
2185 return -ENOMEM;
2186 }
2187
2188 util_queue_fence_init(&shader->ready);
2189
2190 shader->selector = sel;
2191 shader->key = *key;
2192 shader->compiler_ctx_state = *compiler_state;
2193
2194 /* If this is a merged shader, get the first shader's selector. */
2195 if (sscreen->info.chip_class >= GFX9) {
2196 if (sel->info.stage == MESA_SHADER_TESS_CTRL)
2197 previous_stage_sel = key->part.tcs.ls;
2198 else if (sel->info.stage == MESA_SHADER_GEOMETRY)
2199 previous_stage_sel = key->part.gs.es;
2200
2201 /* We need to wait for the previous shader. */
2202 if (previous_stage_sel && thread_index < 0)
2203 util_queue_fence_wait(&previous_stage_sel->ready);
2204 }
2205
2206 bool is_pure_monolithic =
2207 sscreen->use_monolithic_shaders || memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2208
2209 /* Compile the main shader part if it doesn't exist. This can happen
2210 * if the initial guess was wrong.
2211 *
2212 * The prim discard CS doesn't need the main shader part.
2213 */
2214 if (!is_pure_monolithic && !key->opt.vs_as_prim_discard_cs) {
2215 bool ok = true;
2216
2217 /* Make sure the main shader part is present. This is needed
2218 * for shaders that can be compiled as VS, LS, or ES, and only
2219 * one of them is compiled at creation.
2220 *
2221 * It is also needed for GS, which can be compiled as non-NGG
2222 * and NGG.
2223 *
2224 * For merged shaders, check that the starting shader's main
2225 * part is present.
2226 */
2227 if (previous_stage_sel) {
2228 struct si_shader_key shader1_key = zeroed;
2229
2230 if (sel->info.stage == MESA_SHADER_TESS_CTRL) {
2231 shader1_key.as_ls = 1;
2232 } else if (sel->info.stage == MESA_SHADER_GEOMETRY) {
2233 shader1_key.as_es = 1;
2234 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2235 } else {
2236 assert(0);
2237 }
2238
2239 simple_mtx_lock(&previous_stage_sel->mutex);
2240 ok = si_check_missing_main_part(sscreen, previous_stage_sel, compiler_state, &shader1_key);
2241 simple_mtx_unlock(&previous_stage_sel->mutex);
2242 }
2243
2244 if (ok) {
2245 ok = si_check_missing_main_part(sscreen, sel, compiler_state, key);
2246 }
2247
2248 if (!ok) {
2249 FREE(shader);
2250 simple_mtx_unlock(&sel->mutex);
2251 return -ENOMEM; /* skip the draw call */
2252 }
2253 }
2254
2255 /* Keep the reference to the 1st shader of merged shaders, so that
2256 * Gallium can't destroy it before we destroy the 2nd shader.
2257 *
2258 * Set sctx = NULL, because it's unused if we're not releasing
2259 * the shader, and we don't have any sctx here.
2260 */
2261 si_shader_selector_reference(NULL, &shader->previous_stage_sel, previous_stage_sel);
2262
2263 /* Monolithic-only shaders don't make a distinction between optimized
2264 * and unoptimized. */
2265 shader->is_monolithic =
2266 is_pure_monolithic || memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2267
2268 /* The prim discard CS is always optimized. */
2269 shader->is_optimized = (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2270 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2271
2272 /* If it's an optimized shader, compile it asynchronously. */
2273 if (shader->is_optimized && thread_index < 0) {
2274 /* Compile it asynchronously. */
2275 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority, shader, &shader->ready,
2276 si_build_shader_variant_low_priority, NULL, 0);
2277
2278 /* Add only after the ready fence was reset, to guard against a
2279 * race with si_bind_XX_shader. */
2280 if (!sel->last_variant) {
2281 sel->first_variant = shader;
2282 sel->last_variant = shader;
2283 } else {
2284 sel->last_variant->next_variant = shader;
2285 sel->last_variant = shader;
2286 }
2287
2288 /* Use the default (unoptimized) shader for now. */
2289 memset(&key->opt, 0, sizeof(key->opt));
2290 simple_mtx_unlock(&sel->mutex);
2291
2292 if (sscreen->options.sync_compile)
2293 util_queue_fence_wait(&shader->ready);
2294
2295 if (optimized_or_none)
2296 return -1;
2297 goto again;
2298 }
2299
2300 /* Reset the fence before adding to the variant list. */
2301 util_queue_fence_reset(&shader->ready);
2302
2303 if (!sel->last_variant) {
2304 sel->first_variant = shader;
2305 sel->last_variant = shader;
2306 } else {
2307 sel->last_variant->next_variant = shader;
2308 sel->last_variant = shader;
2309 }
2310
2311 simple_mtx_unlock(&sel->mutex);
2312
2313 assert(!shader->is_optimized);
2314 si_build_shader_variant(shader, thread_index, false);
2315
2316 util_queue_fence_signal(&shader->ready);
2317
2318 if (!shader->compilation_failed)
2319 state->current = shader;
2320
2321 return shader->compilation_failed ? -1 : 0;
2322 }
2323
2324 static int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state,
2325 union si_vgt_stages_key stages_key,
2326 struct si_compiler_ctx_state *compiler_state)
2327 {
2328 struct si_context *sctx = (struct si_context *)ctx;
2329 struct si_shader_key key;
2330
2331 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2332 return si_shader_select_with_key(sctx->screen, state, compiler_state, &key, -1, false);
2333 }
2334
2335 static void si_parse_next_shader_property(const struct si_shader_info *info, bool streamout,
2336 struct si_shader_key *key)
2337 {
2338 gl_shader_stage next_shader = info->base.next_stage;
2339
2340 switch (info->stage) {
2341 case MESA_SHADER_VERTEX:
2342 switch (next_shader) {
2343 case MESA_SHADER_GEOMETRY:
2344 key->as_es = 1;
2345 break;
2346 case MESA_SHADER_TESS_CTRL:
2347 case MESA_SHADER_TESS_EVAL:
2348 key->as_ls = 1;
2349 break;
2350 default:
2351 /* If POSITION isn't written, it can only be a HW VS
2352 * if streamout is used. If streamout isn't used,
2353 * assume that it's a HW LS. (the next shader is TCS)
2354 * This heuristic is needed for separate shader objects.
2355 */
2356 if (!info->writes_position && !streamout)
2357 key->as_ls = 1;
2358 }
2359 break;
2360
2361 case MESA_SHADER_TESS_EVAL:
2362 if (next_shader == MESA_SHADER_GEOMETRY || !info->writes_position)
2363 key->as_es = 1;
2364 break;
2365
2366 default:;
2367 }
2368 }
2369
2370 /**
2371 * Compile the main shader part or the monolithic shader as part of
2372 * si_shader_selector initialization. Since it can be done asynchronously,
2373 * there is no way to report compile failures to applications.
2374 */
2375 static void si_init_shader_selector_async(void *job, int thread_index)
2376 {
2377 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2378 struct si_screen *sscreen = sel->screen;
2379 struct ac_llvm_compiler *compiler;
2380 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2381
2382 assert(!debug->debug_message || debug->async);
2383 assert(thread_index >= 0);
2384 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2385 compiler = &sscreen->compiler[thread_index];
2386
2387 if (!compiler->passes)
2388 si_init_compiler(sscreen, compiler);
2389
2390 /* Serialize NIR to save memory. Monolithic shader variants
2391 * have to deserialize NIR before compilation.
2392 */
2393 if (sel->nir) {
2394 struct blob blob;
2395 size_t size;
2396
2397 blob_init(&blob);
2398 /* true = remove optional debugging data to increase
2399 * the likehood of getting more shader cache hits.
2400 * It also drops variable names, so we'll save more memory.
2401 */
2402 nir_serialize(&blob, sel->nir, true);
2403 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2404 sel->nir_size = size;
2405 }
2406
2407 /* Compile the main shader part for use with a prolog and/or epilog.
2408 * If this fails, the driver will try to compile a monolithic shader
2409 * on demand.
2410 */
2411 if (!sscreen->use_monolithic_shaders) {
2412 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2413 unsigned char ir_sha1_cache_key[20];
2414
2415 if (!shader) {
2416 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2417 return;
2418 }
2419
2420 /* We can leave the fence signaled because use of the default
2421 * main part is guarded by the selector's ready fence. */
2422 util_queue_fence_init(&shader->ready);
2423
2424 shader->selector = sel;
2425 shader->is_monolithic = false;
2426 si_parse_next_shader_property(&sel->info, sel->so.num_outputs != 0, &shader->key);
2427
2428 if (sscreen->use_ngg && (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2429 ((sel->info.stage == MESA_SHADER_VERTEX && !shader->key.as_ls) ||
2430 sel->info.stage == MESA_SHADER_TESS_EVAL || sel->info.stage == MESA_SHADER_GEOMETRY))
2431 shader->key.as_ngg = 1;
2432
2433 if (sel->nir) {
2434 si_get_ir_cache_key(sel, shader->key.as_ngg, shader->key.as_es, ir_sha1_cache_key);
2435 }
2436
2437 /* Try to load the shader from the shader cache. */
2438 simple_mtx_lock(&sscreen->shader_cache_mutex);
2439
2440 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2441 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2442 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2443 } else {
2444 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2445
2446 /* Compile the shader if it hasn't been loaded from the cache. */
2447 if (!si_compile_shader(sscreen, compiler, shader, debug)) {
2448 FREE(shader);
2449 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2450 return;
2451 }
2452
2453 simple_mtx_lock(&sscreen->shader_cache_mutex);
2454 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
2455 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2456 }
2457
2458 *si_get_main_shader_part(sel, &shader->key) = shader;
2459
2460 /* Unset "outputs_written" flags for outputs converted to
2461 * DEFAULT_VAL, so that later inter-shader optimizations don't
2462 * try to eliminate outputs that don't exist in the final
2463 * shader.
2464 *
2465 * This is only done if non-monolithic shaders are enabled.
2466 */
2467 if ((sel->info.stage == MESA_SHADER_VERTEX || sel->info.stage == MESA_SHADER_TESS_EVAL) &&
2468 !shader->key.as_ls && !shader->key.as_es) {
2469 unsigned i;
2470
2471 for (i = 0; i < sel->info.num_outputs; i++) {
2472 unsigned offset = shader->info.vs_output_param_offset[i];
2473
2474 if (offset <= AC_EXP_PARAM_OFFSET_31)
2475 continue;
2476
2477 unsigned semantic = sel->info.output_semantic[i];
2478 unsigned id;
2479
2480 if (semantic < VARYING_SLOT_MAX &&
2481 semantic != VARYING_SLOT_POS &&
2482 semantic != VARYING_SLOT_PSIZ &&
2483 semantic != VARYING_SLOT_CLIP_VERTEX &&
2484 semantic != VARYING_SLOT_EDGE) {
2485 id = si_shader_io_get_unique_index(semantic, true);
2486 sel->outputs_written_before_ps &= ~(1ull << id);
2487 }
2488 }
2489 }
2490 }
2491
2492 /* The GS copy shader is always pre-compiled. */
2493 if (sel->info.stage == MESA_SHADER_GEOMETRY &&
2494 (!sscreen->use_ngg || !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2495 sel->tess_turns_off_ngg)) {
2496 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2497 if (!sel->gs_copy_shader) {
2498 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2499 return;
2500 }
2501
2502 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2503 }
2504
2505 /* Free NIR. We only keep serialized NIR after this point. */
2506 if (sel->nir) {
2507 ralloc_free(sel->nir);
2508 sel->nir = NULL;
2509 }
2510 }
2511
2512 void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage,
2513 struct util_queue_fence *ready_fence,
2514 struct si_compiler_ctx_state *compiler_ctx_state, void *job,
2515 util_queue_execute_func execute)
2516 {
2517 util_queue_fence_init(ready_fence);
2518
2519 struct util_async_debug_callback async_debug;
2520 bool debug = (sctx->debug.debug_message && !sctx->debug.async) || sctx->is_debug ||
2521 si_can_dump_shader(sctx->screen, stage);
2522
2523 if (debug) {
2524 u_async_debug_init(&async_debug);
2525 compiler_ctx_state->debug = async_debug.base;
2526 }
2527
2528 util_queue_add_job(&sctx->screen->shader_compiler_queue, job, ready_fence, execute, NULL, 0);
2529
2530 if (debug) {
2531 util_queue_fence_wait(ready_fence);
2532 u_async_debug_drain(&async_debug, &sctx->debug);
2533 u_async_debug_cleanup(&async_debug);
2534 }
2535
2536 if (sctx->screen->options.sync_compile)
2537 util_queue_fence_wait(ready_fence);
2538 }
2539
2540 /* Return descriptor slot usage masks from the given shader info. */
2541 void si_get_active_slot_masks(const struct si_shader_info *info, uint64_t *const_and_shader_buffers,
2542 uint64_t *samplers_and_images)
2543 {
2544 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2545
2546 num_shaderbufs = info->base.num_ssbos;
2547 num_constbufs = util_last_bit(info->const_buffers_declared);
2548 /* two 8-byte images share one 16-byte slot */
2549 num_images = align(util_last_bit(info->images_declared), 2);
2550 num_msaa_images = align(util_last_bit(info->base.msaa_images), 2);
2551 num_samplers = util_last_bit(info->base.textures_used);
2552
2553 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2554 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2555 *const_and_shader_buffers = u_bit_consecutive64(start, num_shaderbufs + num_constbufs);
2556
2557 /* The layout is:
2558 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2559 * - image[last] ... image[0] go to [31-last .. 31]
2560 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2561 *
2562 * FMASKs for images are placed separately, because MSAA images are rare,
2563 * and so we can benefit from a better cache hit rate if we keep image
2564 * descriptors together.
2565 */
2566 if (num_msaa_images)
2567 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2568
2569 start = si_get_image_slot(num_images - 1) / 2;
2570 *samplers_and_images = u_bit_consecutive64(start, num_images / 2 + num_samplers);
2571 }
2572
2573 static void *si_create_shader_selector(struct pipe_context *ctx,
2574 const struct pipe_shader_state *state)
2575 {
2576 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2577 struct si_context *sctx = (struct si_context *)ctx;
2578 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2579 int i;
2580
2581 if (!sel)
2582 return NULL;
2583
2584 sel->screen = sscreen;
2585 sel->compiler_ctx_state.debug = sctx->debug;
2586 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2587
2588 sel->so = state->stream_output;
2589
2590 if (state->type == PIPE_SHADER_IR_TGSI) {
2591 sel->nir = tgsi_to_nir(state->tokens, ctx->screen, true);
2592 } else {
2593 assert(state->type == PIPE_SHADER_IR_NIR);
2594 sel->nir = state->ir.nir;
2595 }
2596
2597 si_nir_scan_shader(sel->nir, &sel->info);
2598
2599 const enum pipe_shader_type type = pipe_shader_type_from_mesa(sel->info.stage);
2600 sel->const_and_shader_buf_descriptors_index =
2601 si_const_and_shader_buffer_descriptors_idx(type);
2602 sel->sampler_and_images_descriptors_index =
2603 si_sampler_and_image_descriptors_idx(type);
2604
2605 p_atomic_inc(&sscreen->num_shaders_created);
2606 si_get_active_slot_masks(&sel->info, &sel->active_const_and_shader_buffers,
2607 &sel->active_samplers_and_images);
2608
2609 /* Record which streamout buffers are enabled. */
2610 for (i = 0; i < sel->so.num_outputs; i++) {
2611 sel->enabled_streamout_buffer_mask |= (1 << sel->so.output[i].output_buffer)
2612 << (sel->so.output[i].stream * 4);
2613 }
2614
2615 sel->num_vs_inputs =
2616 sel->info.stage == MESA_SHADER_VERTEX && !sel->info.base.vs.blit_sgprs_amd
2617 ? sel->info.num_inputs
2618 : 0;
2619 sel->num_vbos_in_user_sgprs = MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2620
2621 /* The prolog is a no-op if there are no inputs. */
2622 sel->vs_needs_prolog = sel->info.stage == MESA_SHADER_VERTEX && sel->info.num_inputs &&
2623 !sel->info.base.vs.blit_sgprs_amd;
2624
2625 sel->prim_discard_cs_allowed =
2626 sel->info.stage == MESA_SHADER_VERTEX && !sel->info.uses_bindless_images &&
2627 !sel->info.uses_bindless_samplers && !sel->info.writes_memory &&
2628 !sel->info.writes_viewport_index &&
2629 !sel->info.base.vs.window_space_position && !sel->so.num_outputs;
2630
2631 switch (sel->info.stage) {
2632 case MESA_SHADER_GEOMETRY:
2633 sel->gs_output_prim = sel->info.base.gs.output_primitive;
2634
2635 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2636 sel->rast_prim = sel->gs_output_prim;
2637 if (util_rast_prim_is_triangles(sel->rast_prim))
2638 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2639
2640 sel->gs_max_out_vertices = sel->info.base.gs.vertices_out;
2641 sel->gs_num_invocations = sel->info.base.gs.invocations;
2642 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2643 sel->max_gsvs_emit_size = sel->gsvs_vertex_size * sel->gs_max_out_vertices;
2644
2645 sel->max_gs_stream = 0;
2646 for (i = 0; i < sel->so.num_outputs; i++)
2647 sel->max_gs_stream = MAX2(sel->max_gs_stream, sel->so.output[i].stream);
2648
2649 sel->gs_input_verts_per_prim =
2650 u_vertices_per_prim(sel->info.base.gs.input_primitive);
2651
2652 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation so
2653 * we can't split workgroups. Disable ngg if any of the following conditions is true:
2654 * - num_invocations * gs_max_out_vertices > 256
2655 * - LDS usage is too high
2656 */
2657 sel->tess_turns_off_ngg = sscreen->info.chip_class >= GFX10 &&
2658 (sel->gs_num_invocations * sel->gs_max_out_vertices > 256 ||
2659 sel->gs_num_invocations * sel->gs_max_out_vertices *
2660 (sel->info.num_outputs * 4 + 1) > 6500 /* max dw per GS primitive */);
2661 break;
2662
2663 case MESA_SHADER_TESS_CTRL:
2664 /* Always reserve space for these. */
2665 sel->patch_outputs_written |=
2666 (1ull << si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_INNER)) |
2667 (1ull << si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_OUTER));
2668 /* fall through */
2669 case MESA_SHADER_VERTEX:
2670 case MESA_SHADER_TESS_EVAL:
2671 for (i = 0; i < sel->info.num_outputs; i++) {
2672 unsigned semantic = sel->info.output_semantic[i];
2673
2674 if (semantic == VARYING_SLOT_TESS_LEVEL_INNER ||
2675 semantic == VARYING_SLOT_TESS_LEVEL_OUTER ||
2676 (semantic >= VARYING_SLOT_PATCH0 && semantic < VARYING_SLOT_TESS_MAX)) {
2677 sel->patch_outputs_written |= 1ull << si_shader_io_get_unique_index_patch(semantic);
2678 } else if (semantic < VARYING_SLOT_MAX &&
2679 semantic != VARYING_SLOT_EDGE) {
2680 sel->outputs_written |= 1ull << si_shader_io_get_unique_index(semantic, false);
2681 sel->outputs_written_before_ps |= 1ull
2682 << si_shader_io_get_unique_index(semantic, true);
2683 }
2684 }
2685 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2686 sel->lshs_vertex_stride = sel->esgs_itemsize;
2687
2688 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2689 * will start on a different bank. (except for the maximum 32*16).
2690 */
2691 if (sel->lshs_vertex_stride < 32 * 16)
2692 sel->lshs_vertex_stride += 4;
2693
2694 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2695 * conflicts, i.e. each vertex will start at a different bank.
2696 */
2697 if (sctx->chip_class >= GFX9)
2698 sel->esgs_itemsize += 4;
2699
2700 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2701
2702 /* Only for TES: */
2703 if (sel->info.stage == MESA_SHADER_TESS_EVAL) {
2704 if (sel->info.base.tess.point_mode)
2705 sel->rast_prim = PIPE_PRIM_POINTS;
2706 else if (sel->info.base.tess.primitive_mode == GL_LINES)
2707 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2708 else
2709 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2710 } else {
2711 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2712 }
2713 break;
2714
2715 case MESA_SHADER_FRAGMENT:
2716 for (i = 0; i < sel->info.num_inputs; i++) {
2717 unsigned semantic = sel->info.input_semantic[i];
2718
2719 if (semantic < VARYING_SLOT_MAX &&
2720 semantic != VARYING_SLOT_PNTC) {
2721 sel->inputs_read |= 1ull << si_shader_io_get_unique_index(semantic, true);
2722 }
2723 }
2724
2725 for (i = 0; i < 8; i++)
2726 if (sel->info.colors_written & (1 << i))
2727 sel->colors_written_4bit |= 0xf << (4 * i);
2728
2729 for (i = 0; i < sel->info.num_inputs; i++) {
2730 if (sel->info.input_semantic[i] == VARYING_SLOT_COL0)
2731 sel->color_attr_index[0] = i;
2732 else if (sel->info.input_semantic[i] == VARYING_SLOT_COL1)
2733 sel->color_attr_index[1] = i;
2734 }
2735 break;
2736 default:;
2737 }
2738
2739 sel->ngg_culling_allowed =
2740 sscreen->info.chip_class >= GFX10 &&
2741 sscreen->info.has_dedicated_vram &&
2742 sscreen->use_ngg_culling &&
2743 (sel->info.stage == MESA_SHADER_VERTEX ||
2744 (sel->info.stage == MESA_SHADER_TESS_EVAL &&
2745 (sscreen->always_use_ngg_culling_all ||
2746 sscreen->always_use_ngg_culling_tess))) &&
2747 sel->info.writes_position &&
2748 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
2749 !sel->info.writes_memory && !sel->so.num_outputs &&
2750 (sel->info.stage != MESA_SHADER_VERTEX ||
2751 (!sel->info.base.vs.blit_sgprs_amd &&
2752 !sel->info.base.vs.window_space_position));
2753
2754 /* PA_CL_VS_OUT_CNTL */
2755 if (sctx->chip_class <= GFX9)
2756 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2757
2758 sel->clipdist_mask = sel->info.writes_clipvertex ? SIX_BITS : sel->info.clipdist_writemask;
2759 sel->culldist_mask = sel->info.culldist_writemask << sel->info.num_written_clipdistance;
2760
2761 /* DB_SHADER_CONTROL */
2762 sel->db_shader_control = S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2763 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2764 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2765 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2766
2767 if (sel->info.stage == MESA_SHADER_FRAGMENT) {
2768 switch (sel->info.base.fs.depth_layout) {
2769 case FRAG_DEPTH_LAYOUT_GREATER:
2770 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2771 break;
2772 case FRAG_DEPTH_LAYOUT_LESS:
2773 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2774 break;
2775 default:;
2776 }
2777
2778 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2779 *
2780 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2781 * --|-----------|------------|------------|--------------------|-------------------|-------------
2782 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2783 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2784 * 2 | false | true | n/a | LateZ | 1 | 0
2785 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2786 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2787 *
2788 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2789 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2790 *
2791 * Don't use ReZ without profiling !!!
2792 *
2793 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2794 * shaders.
2795 */
2796 if (sel->info.base.fs.early_fragment_tests) {
2797 /* Cases 3, 4. */
2798 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2799 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2800 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2801 } else if (sel->info.writes_memory) {
2802 /* Case 2. */
2803 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) | S_02880C_EXEC_ON_HIER_FAIL(1);
2804 } else {
2805 /* Case 1. */
2806 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2807 }
2808
2809 if (sel->info.base.fs.post_depth_coverage)
2810 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2811 }
2812
2813 (void)simple_mtx_init(&sel->mutex, mtx_plain);
2814
2815 si_schedule_initial_compile(sctx, sel->info.stage, &sel->ready, &sel->compiler_ctx_state,
2816 sel, si_init_shader_selector_async);
2817 return sel;
2818 }
2819
2820 static void *si_create_shader(struct pipe_context *ctx, const struct pipe_shader_state *state)
2821 {
2822 struct si_context *sctx = (struct si_context *)ctx;
2823 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2824 bool cache_hit;
2825 struct si_shader_selector *sel = (struct si_shader_selector *)util_live_shader_cache_get(
2826 ctx, &sscreen->live_shader_cache, state, &cache_hit);
2827
2828 if (sel && cache_hit && sctx->debug.debug_message) {
2829 if (sel->main_shader_part)
2830 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part, &sctx->debug);
2831 if (sel->main_shader_part_ls)
2832 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ls, &sctx->debug);
2833 if (sel->main_shader_part_es)
2834 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_es, &sctx->debug);
2835 if (sel->main_shader_part_ngg)
2836 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg, &sctx->debug);
2837 if (sel->main_shader_part_ngg_es)
2838 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg_es, &sctx->debug);
2839 }
2840 return sel;
2841 }
2842
2843 static void si_update_streamout_state(struct si_context *sctx)
2844 {