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[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * on the rights to use, copy, modify, merge, publish, distribute, sub
8 * license, and/or sell copies of the Software, and to permit persons to whom
9 * the Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
19 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
20 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
21 * USE OR OTHER DEALINGS IN THE SOFTWARE.
22 *
23 * Authors:
24 * Christian König <christian.koenig@amd.com>
25 * Marek Olšák <maraeo@gmail.com>
26 */
27
28 #include "si_pipe.h"
29 #include "si_shader.h"
30 #include "sid.h"
31 #include "radeon/r600_cs.h"
32
33 #include "tgsi/tgsi_parse.h"
34 #include "tgsi/tgsi_ureg.h"
35 #include "util/hash_table.h"
36 #include "util/u_hash.h"
37 #include "util/u_memory.h"
38 #include "util/u_prim.h"
39 #include "util/u_simple_shaders.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the TGSI binary in a buffer. The first 4 bytes contain its size as
45 * integer.
46 */
47 static void *si_get_tgsi_binary(struct si_shader_selector *sel)
48 {
49 unsigned tgsi_size = tgsi_num_tokens(sel->tokens) *
50 sizeof(struct tgsi_token);
51 unsigned size = 4 + tgsi_size + sizeof(sel->so);
52 char *result = (char*)MALLOC(size);
53
54 if (!result)
55 return NULL;
56
57 *((uint32_t*)result) = size;
58 memcpy(result + 4, sel->tokens, tgsi_size);
59 memcpy(result + 4 + tgsi_size, &sel->so, sizeof(sel->so));
60 return result;
61 }
62
63 /** Copy "data" to "ptr" and return the next dword following copied data. */
64 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
65 {
66 /* data may be NULL if size == 0 */
67 if (size)
68 memcpy(ptr, data, size);
69 ptr += DIV_ROUND_UP(size, 4);
70 return ptr;
71 }
72
73 /** Read data from "ptr". Return the next dword following the data. */
74 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
75 {
76 memcpy(data, ptr, size);
77 ptr += DIV_ROUND_UP(size, 4);
78 return ptr;
79 }
80
81 /**
82 * Write the size as uint followed by the data. Return the next dword
83 * following the copied data.
84 */
85 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
86 {
87 *ptr++ = size;
88 return write_data(ptr, data, size);
89 }
90
91 /**
92 * Read the size as uint followed by the data. Return both via parameters.
93 * Return the next dword following the data.
94 */
95 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
96 {
97 *size = *ptr++;
98 assert(*data == NULL);
99 *data = malloc(*size);
100 return read_data(ptr, *data, *size);
101 }
102
103 /**
104 * Return the shader binary in a buffer. The first 4 bytes contain its size
105 * as integer.
106 */
107 static void *si_get_shader_binary(struct si_shader *shader)
108 {
109 /* There is always a size of data followed by the data itself. */
110 unsigned relocs_size = shader->binary.reloc_count *
111 sizeof(shader->binary.relocs[0]);
112 unsigned disasm_size = strlen(shader->binary.disasm_string) + 1;
113 unsigned size =
114 4 + /* total size */
115 4 + /* CRC32 of the data below */
116 align(sizeof(shader->config), 4) +
117 align(sizeof(shader->info), 4) +
118 4 + align(shader->binary.code_size, 4) +
119 4 + align(shader->binary.rodata_size, 4) +
120 4 + align(relocs_size, 4) +
121 4 + align(disasm_size, 4);
122 void *buffer = CALLOC(1, size);
123 uint32_t *ptr = (uint32_t*)buffer;
124
125 if (!buffer)
126 return NULL;
127
128 *ptr++ = size;
129 ptr++; /* CRC32 is calculated at the end. */
130
131 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
132 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
133 ptr = write_chunk(ptr, shader->binary.code, shader->binary.code_size);
134 ptr = write_chunk(ptr, shader->binary.rodata, shader->binary.rodata_size);
135 ptr = write_chunk(ptr, shader->binary.relocs, relocs_size);
136 ptr = write_chunk(ptr, shader->binary.disasm_string, disasm_size);
137 assert((char *)ptr - (char *)buffer == size);
138
139 /* Compute CRC32. */
140 ptr = (uint32_t*)buffer;
141 ptr++;
142 *ptr = util_hash_crc32(ptr + 1, size - 8);
143
144 return buffer;
145 }
146
147 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
148 {
149 uint32_t *ptr = (uint32_t*)binary;
150 uint32_t size = *ptr++;
151 uint32_t crc32 = *ptr++;
152 unsigned chunk_size;
153
154 if (util_hash_crc32(ptr, size - 8) != crc32) {
155 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
156 return false;
157 }
158
159 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
160 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
161 ptr = read_chunk(ptr, (void**)&shader->binary.code,
162 &shader->binary.code_size);
163 ptr = read_chunk(ptr, (void**)&shader->binary.rodata,
164 &shader->binary.rodata_size);
165 ptr = read_chunk(ptr, (void**)&shader->binary.relocs, &chunk_size);
166 shader->binary.reloc_count = chunk_size / sizeof(shader->binary.relocs[0]);
167 ptr = read_chunk(ptr, (void**)&shader->binary.disasm_string, &chunk_size);
168
169 return true;
170 }
171
172 /**
173 * Insert a shader into the cache. It's assumed the shader is not in the cache.
174 * Use si_shader_cache_load_shader before calling this.
175 *
176 * Returns false on failure, in which case the tgsi_binary should be freed.
177 */
178 static bool si_shader_cache_insert_shader(struct si_screen *sscreen,
179 void *tgsi_binary,
180 struct si_shader *shader)
181 {
182 void *hw_binary = si_get_shader_binary(shader);
183
184 if (!hw_binary)
185 return false;
186
187 if (_mesa_hash_table_insert(sscreen->shader_cache, tgsi_binary,
188 hw_binary) == NULL) {
189 FREE(hw_binary);
190 return false;
191 }
192
193 return true;
194 }
195
196 static bool si_shader_cache_load_shader(struct si_screen *sscreen,
197 void *tgsi_binary,
198 struct si_shader *shader)
199 {
200 struct hash_entry *entry =
201 _mesa_hash_table_search(sscreen->shader_cache, tgsi_binary);
202 if (!entry)
203 return false;
204
205 return si_load_shader_binary(shader, entry->data);
206 }
207
208 static uint32_t si_shader_cache_key_hash(const void *key)
209 {
210 /* The first dword is the key size. */
211 return util_hash_crc32(key, *(uint32_t*)key);
212 }
213
214 static bool si_shader_cache_key_equals(const void *a, const void *b)
215 {
216 uint32_t *keya = (uint32_t*)a;
217 uint32_t *keyb = (uint32_t*)b;
218
219 /* The first dword is the key size. */
220 if (*keya != *keyb)
221 return false;
222
223 return memcmp(keya, keyb, *keya) == 0;
224 }
225
226 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
227 {
228 FREE((void*)entry->key);
229 FREE(entry->data);
230 }
231
232 bool si_init_shader_cache(struct si_screen *sscreen)
233 {
234 pipe_mutex_init(sscreen->shader_cache_mutex);
235 sscreen->shader_cache =
236 _mesa_hash_table_create(NULL,
237 si_shader_cache_key_hash,
238 si_shader_cache_key_equals);
239 return sscreen->shader_cache != NULL;
240 }
241
242 void si_destroy_shader_cache(struct si_screen *sscreen)
243 {
244 if (sscreen->shader_cache)
245 _mesa_hash_table_destroy(sscreen->shader_cache,
246 si_destroy_shader_cache_entry);
247 pipe_mutex_destroy(sscreen->shader_cache_mutex);
248 }
249
250 /* SHADER STATES */
251
252 static void si_set_tesseval_regs(struct si_shader *shader,
253 struct si_pm4_state *pm4)
254 {
255 struct tgsi_shader_info *info = &shader->selector->info;
256 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
257 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
258 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
259 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
260 unsigned type, partitioning, topology;
261
262 switch (tes_prim_mode) {
263 case PIPE_PRIM_LINES:
264 type = V_028B6C_TESS_ISOLINE;
265 break;
266 case PIPE_PRIM_TRIANGLES:
267 type = V_028B6C_TESS_TRIANGLE;
268 break;
269 case PIPE_PRIM_QUADS:
270 type = V_028B6C_TESS_QUAD;
271 break;
272 default:
273 assert(0);
274 return;
275 }
276
277 switch (tes_spacing) {
278 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
279 partitioning = V_028B6C_PART_FRAC_ODD;
280 break;
281 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
282 partitioning = V_028B6C_PART_FRAC_EVEN;
283 break;
284 case PIPE_TESS_SPACING_EQUAL:
285 partitioning = V_028B6C_PART_INTEGER;
286 break;
287 default:
288 assert(0);
289 return;
290 }
291
292 if (tes_point_mode)
293 topology = V_028B6C_OUTPUT_POINT;
294 else if (tes_prim_mode == PIPE_PRIM_LINES)
295 topology = V_028B6C_OUTPUT_LINE;
296 else if (tes_vertex_order_cw)
297 /* for some reason, this must be the other way around */
298 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
299 else
300 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
301
302 si_pm4_set_reg(pm4, R_028B6C_VGT_TF_PARAM,
303 S_028B6C_TYPE(type) |
304 S_028B6C_PARTITIONING(partitioning) |
305 S_028B6C_TOPOLOGY(topology));
306 }
307
308 static void si_shader_ls(struct si_shader *shader)
309 {
310 struct si_pm4_state *pm4;
311 unsigned vgpr_comp_cnt;
312 uint64_t va;
313
314 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
315 if (!pm4)
316 return;
317
318 va = shader->bo->gpu_address;
319 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
320
321 /* We need at least 2 components for LS.
322 * VGPR0-3: (VertexID, RelAutoindex, ???, InstanceID). */
323 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 1;
324
325 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
326 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, va >> 40);
327
328 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
329 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
330 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
331 S_00B528_DX10_CLAMP(1) |
332 S_00B528_FLOAT_MODE(shader->config.float_mode);
333 shader->config.rsrc2 = S_00B52C_USER_SGPR(SI_LS_NUM_USER_SGPR) |
334 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
335 }
336
337 static void si_shader_hs(struct si_shader *shader)
338 {
339 struct si_pm4_state *pm4;
340 uint64_t va;
341
342 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
343 if (!pm4)
344 return;
345
346 va = shader->bo->gpu_address;
347 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
348
349 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
350 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, va >> 40);
351 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
352 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
353 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) |
354 S_00B428_DX10_CLAMP(1) |
355 S_00B428_FLOAT_MODE(shader->config.float_mode));
356 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
357 S_00B42C_USER_SGPR(SI_TCS_NUM_USER_SGPR) |
358 S_00B42C_OC_LDS_EN(1) |
359 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
360 }
361
362 static void si_shader_es(struct si_shader *shader)
363 {
364 struct si_pm4_state *pm4;
365 unsigned num_user_sgprs;
366 unsigned vgpr_comp_cnt;
367 uint64_t va;
368 unsigned oc_lds_en;
369
370 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
371
372 if (!pm4)
373 return;
374
375 va = shader->bo->gpu_address;
376 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
377
378 if (shader->selector->type == PIPE_SHADER_VERTEX) {
379 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
380 num_user_sgprs = SI_ES_NUM_USER_SGPR;
381 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
382 vgpr_comp_cnt = 3; /* all components are needed for TES */
383 num_user_sgprs = SI_TES_NUM_USER_SGPR;
384 } else
385 unreachable("invalid shader selector type");
386
387 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
388
389 si_pm4_set_reg(pm4, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
390 shader->selector->esgs_itemsize / 4);
391 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
392 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
393 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
394 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
395 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
396 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
397 S_00B328_DX10_CLAMP(1) |
398 S_00B328_FLOAT_MODE(shader->config.float_mode));
399 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
400 S_00B32C_USER_SGPR(num_user_sgprs) |
401 S_00B32C_OC_LDS_EN(oc_lds_en) |
402 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
403
404 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
405 si_set_tesseval_regs(shader, pm4);
406 }
407
408 /**
409 * Calculate the appropriate setting of VGT_GS_MODE when \p shader is a
410 * geometry shader.
411 */
412 static uint32_t si_vgt_gs_mode(struct si_shader *shader)
413 {
414 unsigned gs_max_vert_out = shader->selector->gs_max_out_vertices;
415 unsigned cut_mode;
416
417 if (gs_max_vert_out <= 128) {
418 cut_mode = V_028A40_GS_CUT_128;
419 } else if (gs_max_vert_out <= 256) {
420 cut_mode = V_028A40_GS_CUT_256;
421 } else if (gs_max_vert_out <= 512) {
422 cut_mode = V_028A40_GS_CUT_512;
423 } else {
424 assert(gs_max_vert_out <= 1024);
425 cut_mode = V_028A40_GS_CUT_1024;
426 }
427
428 return S_028A40_MODE(V_028A40_GS_SCENARIO_G) |
429 S_028A40_CUT_MODE(cut_mode)|
430 S_028A40_ES_WRITE_OPTIMIZE(1) |
431 S_028A40_GS_WRITE_OPTIMIZE(1);
432 }
433
434 static void si_shader_gs(struct si_shader *shader)
435 {
436 unsigned gs_vert_itemsize = shader->selector->gsvs_vertex_size;
437 unsigned gsvs_itemsize = shader->selector->max_gsvs_emit_size >> 2;
438 unsigned gs_num_invocations = shader->selector->gs_num_invocations;
439 struct si_pm4_state *pm4;
440 uint64_t va;
441 unsigned max_stream = shader->selector->max_gs_stream;
442
443 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
444 assert(gsvs_itemsize < (1 << 15));
445
446 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
447
448 if (!pm4)
449 return;
450
451 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(shader));
452
453 si_pm4_set_reg(pm4, R_028A60_VGT_GSVS_RING_OFFSET_1, gsvs_itemsize);
454 si_pm4_set_reg(pm4, R_028A64_VGT_GSVS_RING_OFFSET_2, gsvs_itemsize * ((max_stream >= 2) ? 2 : 1));
455 si_pm4_set_reg(pm4, R_028A68_VGT_GSVS_RING_OFFSET_3, gsvs_itemsize * ((max_stream >= 3) ? 3 : 1));
456
457 si_pm4_set_reg(pm4, R_028AB0_VGT_GSVS_RING_ITEMSIZE, gsvs_itemsize * (max_stream + 1));
458
459 si_pm4_set_reg(pm4, R_028B38_VGT_GS_MAX_VERT_OUT, shader->selector->gs_max_out_vertices);
460
461 si_pm4_set_reg(pm4, R_028B5C_VGT_GS_VERT_ITEMSIZE, gs_vert_itemsize >> 2);
462 si_pm4_set_reg(pm4, R_028B60_VGT_GS_VERT_ITEMSIZE_1, (max_stream >= 1) ? gs_vert_itemsize >> 2 : 0);
463 si_pm4_set_reg(pm4, R_028B64_VGT_GS_VERT_ITEMSIZE_2, (max_stream >= 2) ? gs_vert_itemsize >> 2 : 0);
464 si_pm4_set_reg(pm4, R_028B68_VGT_GS_VERT_ITEMSIZE_3, (max_stream >= 3) ? gs_vert_itemsize >> 2 : 0);
465
466 si_pm4_set_reg(pm4, R_028B90_VGT_GS_INSTANCE_CNT,
467 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
468 S_028B90_ENABLE(gs_num_invocations > 0));
469
470 va = shader->bo->gpu_address;
471 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
472 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
473 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, va >> 40);
474
475 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
476 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
477 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
478 S_00B228_DX10_CLAMP(1) |
479 S_00B228_FLOAT_MODE(shader->config.float_mode));
480 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
481 S_00B22C_USER_SGPR(SI_GS_NUM_USER_SGPR) |
482 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
483 }
484
485 /**
486 * Compute the state for \p shader, which will run as a vertex shader on the
487 * hardware.
488 *
489 * If \p gs is non-NULL, it points to the geometry shader for which this shader
490 * is the copy shader.
491 */
492 static void si_shader_vs(struct si_shader *shader, struct si_shader *gs)
493 {
494 struct si_pm4_state *pm4;
495 unsigned num_user_sgprs;
496 unsigned nparams, vgpr_comp_cnt;
497 uint64_t va;
498 unsigned oc_lds_en;
499 unsigned window_space =
500 shader->selector->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
501 bool enable_prim_id = si_vs_exports_prim_id(shader);
502
503 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
504
505 if (!pm4)
506 return;
507
508 /* We always write VGT_GS_MODE in the VS state, because every switch
509 * between different shader pipelines involving a different GS or no
510 * GS at all involves a switch of the VS (different GS use different
511 * copy shaders). On the other hand, when the API switches from a GS to
512 * no GS and then back to the same GS used originally, the GS state is
513 * not sent again.
514 */
515 if (!gs) {
516 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE,
517 S_028A40_MODE(enable_prim_id ? V_028A40_GS_SCENARIO_A : 0));
518 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, enable_prim_id);
519 } else {
520 si_pm4_set_reg(pm4, R_028A40_VGT_GS_MODE, si_vgt_gs_mode(gs));
521 si_pm4_set_reg(pm4, R_028A84_VGT_PRIMITIVEID_EN, 0);
522 }
523
524 va = shader->bo->gpu_address;
525 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
526
527 if (gs) {
528 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
529 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
530 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
531 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
532 num_user_sgprs = SI_VS_NUM_USER_SGPR;
533 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
534 vgpr_comp_cnt = 3; /* all components are needed for TES */
535 num_user_sgprs = SI_TES_NUM_USER_SGPR;
536 } else
537 unreachable("invalid shader selector type");
538
539 /* VS is required to export at least one param. */
540 nparams = MAX2(shader->info.nr_param_exports, 1);
541 si_pm4_set_reg(pm4, R_0286C4_SPI_VS_OUT_CONFIG,
542 S_0286C4_VS_EXPORT_COUNT(nparams - 1));
543
544 si_pm4_set_reg(pm4, R_02870C_SPI_SHADER_POS_FORMAT,
545 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
546 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
547 V_02870C_SPI_SHADER_4COMP :
548 V_02870C_SPI_SHADER_NONE) |
549 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
550 V_02870C_SPI_SHADER_4COMP :
551 V_02870C_SPI_SHADER_NONE) |
552 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
553 V_02870C_SPI_SHADER_4COMP :
554 V_02870C_SPI_SHADER_NONE));
555
556 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
557
558 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
559 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, va >> 40);
560 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS,
561 S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
562 S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8) |
563 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
564 S_00B128_DX10_CLAMP(1) |
565 S_00B128_FLOAT_MODE(shader->config.float_mode));
566 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS,
567 S_00B12C_USER_SGPR(num_user_sgprs) |
568 S_00B12C_OC_LDS_EN(oc_lds_en) |
569 S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
570 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
571 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
572 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
573 S_00B12C_SO_EN(!!shader->selector->so.num_outputs) |
574 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
575 if (window_space)
576 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
577 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1));
578 else
579 si_pm4_set_reg(pm4, R_028818_PA_CL_VTE_CNTL,
580 S_028818_VTX_W0_FMT(1) |
581 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
582 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
583 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
584
585 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
586 si_set_tesseval_regs(shader, pm4);
587 }
588
589 static unsigned si_get_ps_num_interp(struct si_shader *ps)
590 {
591 struct tgsi_shader_info *info = &ps->selector->info;
592 unsigned num_colors = !!(info->colors_read & 0x0f) +
593 !!(info->colors_read & 0xf0);
594 unsigned num_interp = ps->selector->info.num_inputs +
595 (ps->key.ps.prolog.color_two_side ? num_colors : 0);
596
597 assert(num_interp <= 32);
598 return MIN2(num_interp, 32);
599 }
600
601 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
602 {
603 unsigned value = shader->key.ps.epilog.spi_shader_col_format;
604 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
605
606 /* If the i-th target format is set, all previous target formats must
607 * be non-zero to avoid hangs.
608 */
609 for (i = 0; i < num_targets; i++)
610 if (!(value & (0xf << (i * 4))))
611 value |= V_028714_SPI_SHADER_32_R << (i * 4);
612
613 return value;
614 }
615
616 static unsigned si_get_cb_shader_mask(unsigned spi_shader_col_format)
617 {
618 unsigned i, cb_shader_mask = 0;
619
620 for (i = 0; i < 8; i++) {
621 switch ((spi_shader_col_format >> (i * 4)) & 0xf) {
622 case V_028714_SPI_SHADER_ZERO:
623 break;
624 case V_028714_SPI_SHADER_32_R:
625 cb_shader_mask |= 0x1 << (i * 4);
626 break;
627 case V_028714_SPI_SHADER_32_GR:
628 cb_shader_mask |= 0x3 << (i * 4);
629 break;
630 case V_028714_SPI_SHADER_32_AR:
631 cb_shader_mask |= 0x9 << (i * 4);
632 break;
633 case V_028714_SPI_SHADER_FP16_ABGR:
634 case V_028714_SPI_SHADER_UNORM16_ABGR:
635 case V_028714_SPI_SHADER_SNORM16_ABGR:
636 case V_028714_SPI_SHADER_UINT16_ABGR:
637 case V_028714_SPI_SHADER_SINT16_ABGR:
638 case V_028714_SPI_SHADER_32_ABGR:
639 cb_shader_mask |= 0xf << (i * 4);
640 break;
641 default:
642 assert(0);
643 }
644 }
645 return cb_shader_mask;
646 }
647
648 static void si_shader_ps(struct si_shader *shader)
649 {
650 struct tgsi_shader_info *info = &shader->selector->info;
651 struct si_pm4_state *pm4;
652 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
653 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
654 uint64_t va;
655 bool has_centroid;
656 unsigned input_ena = shader->config.spi_ps_input_ena;
657
658 /* we need to enable at least one of them, otherwise we hang the GPU */
659 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
660 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
661 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
662 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
663 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
664 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
665 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
666 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
667
668 pm4 = shader->pm4 = CALLOC_STRUCT(si_pm4_state);
669
670 if (!pm4)
671 return;
672
673 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
674 * Possible vaules:
675 * 0 -> Position = pixel center
676 * 1 -> Position = pixel centroid
677 * 2 -> Position = at sample position
678 *
679 * From GLSL 4.5 specification, section 7.1:
680 * "The variable gl_FragCoord is available as an input variable from
681 * within fragment shaders and it holds the window relative coordinates
682 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
683 * value can be for any location within the pixel, or one of the
684 * fragment samples. The use of centroid does not further restrict
685 * this value to be inside the current primitive."
686 *
687 * Meaning that centroid has no effect and we can return anything within
688 * the pixel. Thus, return the value at sample position, because that's
689 * the most accurate one shaders can get.
690 */
691 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
692
693 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
694 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
695 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
696
697 spi_shader_col_format = si_get_spi_shader_col_format(shader);
698 cb_shader_mask = si_get_cb_shader_mask(spi_shader_col_format);
699
700 /* Ensure that some export memory is always allocated, for two reasons:
701 *
702 * 1) Correctness: The hardware ignores the EXEC mask if no export
703 * memory is allocated, so KILL and alpha test do not work correctly
704 * without this.
705 * 2) Performance: Every shader needs at least a NULL export, even when
706 * it writes no color/depth output. The NULL export instruction
707 * stalls without this setting.
708 *
709 * Don't add this to CB_SHADER_MASK.
710 */
711 if (!spi_shader_col_format &&
712 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
713 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
714
715 si_pm4_set_reg(pm4, R_0286CC_SPI_PS_INPUT_ENA, input_ena);
716 si_pm4_set_reg(pm4, R_0286D0_SPI_PS_INPUT_ADDR,
717 shader->config.spi_ps_input_addr);
718
719 /* Set interpolation controls. */
720 has_centroid = G_0286CC_PERSP_CENTROID_ENA(shader->config.spi_ps_input_ena) ||
721 G_0286CC_LINEAR_CENTROID_ENA(shader->config.spi_ps_input_ena);
722
723 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
724 S_0286D8_BC_OPTIMIZE_DISABLE(has_centroid);
725
726 /* Set registers. */
727 si_pm4_set_reg(pm4, R_0286E0_SPI_BARYC_CNTL, spi_baryc_cntl);
728 si_pm4_set_reg(pm4, R_0286D8_SPI_PS_IN_CONTROL, spi_ps_in_control);
729
730 si_pm4_set_reg(pm4, R_028710_SPI_SHADER_Z_FORMAT,
731 info->writes_samplemask ? V_028710_SPI_SHADER_32_ABGR :
732 info->writes_stencil ? V_028710_SPI_SHADER_32_GR :
733 info->writes_z ? V_028710_SPI_SHADER_32_R :
734 V_028710_SPI_SHADER_ZERO);
735
736 si_pm4_set_reg(pm4, R_028714_SPI_SHADER_COL_FORMAT, spi_shader_col_format);
737 si_pm4_set_reg(pm4, R_02823C_CB_SHADER_MASK, cb_shader_mask);
738
739 va = shader->bo->gpu_address;
740 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_USER_SHADER);
741 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
742 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, va >> 40);
743
744 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS,
745 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
746 S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8) |
747 S_00B028_DX10_CLAMP(1) |
748 S_00B028_FLOAT_MODE(shader->config.float_mode));
749 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
750 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
751 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
752 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
753
754 /* Prefer RE_Z if the shader is complex enough. The requirement is either:
755 * - the shader uses at least 2 VMEM instructions, or
756 * - the code size is at least 50 2-dword instructions or 100 1-dword
757 * instructions.
758 *
759 * Shaders with side effects that must execute independently of the
760 * depth test require LATE_Z.
761 */
762 if (info->writes_memory &&
763 !info->properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
764 shader->z_order = V_02880C_LATE_Z;
765 else if (info->num_memory_instructions >= 2 ||
766 shader->binary.code_size > 100*4)
767 shader->z_order = V_02880C_EARLY_Z_THEN_RE_Z;
768 else
769 shader->z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
770 }
771
772 static void si_shader_init_pm4_state(struct si_shader *shader)
773 {
774
775 if (shader->pm4)
776 si_pm4_free_state_simple(shader->pm4);
777
778 switch (shader->selector->type) {
779 case PIPE_SHADER_VERTEX:
780 if (shader->key.vs.as_ls)
781 si_shader_ls(shader);
782 else if (shader->key.vs.as_es)
783 si_shader_es(shader);
784 else
785 si_shader_vs(shader, NULL);
786 break;
787 case PIPE_SHADER_TESS_CTRL:
788 si_shader_hs(shader);
789 break;
790 case PIPE_SHADER_TESS_EVAL:
791 if (shader->key.tes.as_es)
792 si_shader_es(shader);
793 else
794 si_shader_vs(shader, NULL);
795 break;
796 case PIPE_SHADER_GEOMETRY:
797 si_shader_gs(shader);
798 si_shader_vs(shader->gs_copy_shader, shader);
799 break;
800 case PIPE_SHADER_FRAGMENT:
801 si_shader_ps(shader);
802 break;
803 default:
804 assert(0);
805 }
806 }
807
808 static unsigned si_get_alpha_test_func(struct si_context *sctx)
809 {
810 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
811 if (sctx->queued.named.dsa &&
812 !sctx->framebuffer.cb0_is_integer)
813 return sctx->queued.named.dsa->alpha_func;
814
815 return PIPE_FUNC_ALWAYS;
816 }
817
818 /* Compute the key for the hw shader variant */
819 static inline void si_shader_selector_key(struct pipe_context *ctx,
820 struct si_shader_selector *sel,
821 union si_shader_key *key)
822 {
823 struct si_context *sctx = (struct si_context *)ctx;
824 unsigned i;
825
826 memset(key, 0, sizeof(*key));
827
828 switch (sel->type) {
829 case PIPE_SHADER_VERTEX:
830 if (sctx->vertex_elements) {
831 unsigned count = MIN2(sel->info.num_inputs,
832 sctx->vertex_elements->count);
833 for (i = 0; i < count; ++i)
834 key->vs.prolog.instance_divisors[i] =
835 sctx->vertex_elements->elements[i].instance_divisor;
836 }
837 if (sctx->tes_shader.cso)
838 key->vs.as_ls = 1;
839 else if (sctx->gs_shader.cso)
840 key->vs.as_es = 1;
841
842 if (!sctx->gs_shader.cso && sctx->ps_shader.cso &&
843 sctx->ps_shader.cso->info.uses_primid)
844 key->vs.epilog.export_prim_id = 1;
845 break;
846 case PIPE_SHADER_TESS_CTRL:
847 key->tcs.epilog.prim_mode =
848 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
849
850 if (sel == sctx->fixed_func_tcs_shader.cso)
851 key->tcs.epilog.inputs_to_copy = sctx->vs_shader.cso->outputs_written;
852 break;
853 case PIPE_SHADER_TESS_EVAL:
854 if (sctx->gs_shader.cso)
855 key->tes.as_es = 1;
856 else if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
857 key->tes.epilog.export_prim_id = 1;
858 break;
859 case PIPE_SHADER_GEOMETRY:
860 break;
861 case PIPE_SHADER_FRAGMENT: {
862 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
863 struct si_state_blend *blend = sctx->queued.named.blend;
864
865 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
866 sel->info.colors_written == 0x1)
867 key->ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
868
869 if (blend) {
870 /* Select the shader color format based on whether
871 * blending or alpha are needed.
872 */
873 key->ps.epilog.spi_shader_col_format =
874 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
875 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
876 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
877 sctx->framebuffer.spi_shader_col_format_blend) |
878 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
879 sctx->framebuffer.spi_shader_col_format_alpha) |
880 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
881 sctx->framebuffer.spi_shader_col_format);
882 } else
883 key->ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
884
885 /* If alpha-to-coverage is enabled, we have to export alpha
886 * even if there is no color buffer.
887 */
888 if (!(key->ps.epilog.spi_shader_col_format & 0xf) &&
889 blend && blend->alpha_to_coverage)
890 key->ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
891
892 /* On SI and CIK except Hawaii, the CB doesn't clamp outputs
893 * to the range supported by the type if a channel has less
894 * than 16 bits and the export format is 16_ABGR.
895 */
896 if (sctx->b.chip_class <= CIK && sctx->b.family != CHIP_HAWAII)
897 key->ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
898
899 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
900 if (!key->ps.epilog.last_cbuf) {
901 key->ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
902 key->ps.epilog.color_is_int8 &= sel->info.colors_written;
903 }
904
905 if (rs) {
906 bool is_poly = (sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES &&
907 sctx->current_rast_prim <= PIPE_PRIM_POLYGON) ||
908 sctx->current_rast_prim >= PIPE_PRIM_TRIANGLES_ADJACENCY;
909 bool is_line = !is_poly && sctx->current_rast_prim != PIPE_PRIM_POINTS;
910
911 key->ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
912
913 if (sctx->queued.named.blend) {
914 key->ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
915 rs->multisample_enable &&
916 !sctx->framebuffer.cb0_is_integer;
917 }
918
919 key->ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
920 key->ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
921 (is_line && rs->line_smooth)) &&
922 sctx->framebuffer.nr_samples <= 1;
923 key->ps.epilog.clamp_color = rs->clamp_fragment_color;
924
925 key->ps.prolog.force_persample_interp =
926 rs->force_persample_interp &&
927 rs->multisample_enable &&
928 sctx->framebuffer.nr_samples > 1 &&
929 sctx->ps_iter_samples > 1 &&
930 (sel->info.uses_persp_center ||
931 sel->info.uses_persp_centroid ||
932 sel->info.uses_linear_center ||
933 sel->info.uses_linear_centroid);
934 }
935
936 key->ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
937 break;
938 }
939 default:
940 assert(0);
941 }
942 }
943
944 /* Select the hw shader variant depending on the current state. */
945 static int si_shader_select_with_key(struct pipe_context *ctx,
946 struct si_shader_ctx_state *state,
947 union si_shader_key *key)
948 {
949 struct si_context *sctx = (struct si_context *)ctx;
950 struct si_shader_selector *sel = state->cso;
951 struct si_shader *current = state->current;
952 struct si_shader *iter, *shader = NULL;
953 int r;
954
955 /* Check if we don't need to change anything.
956 * This path is also used for most shaders that don't need multiple
957 * variants, it will cost just a computation of the key and this
958 * test. */
959 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0))
960 return 0;
961
962 pipe_mutex_lock(sel->mutex);
963
964 /* Find the shader variant. */
965 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
966 /* Don't check the "current" shader. We checked it above. */
967 if (current != iter &&
968 memcmp(&iter->key, key, sizeof(*key)) == 0) {
969 state->current = iter;
970 pipe_mutex_unlock(sel->mutex);
971 return 0;
972 }
973 }
974
975 /* Build a new shader. */
976 shader = CALLOC_STRUCT(si_shader);
977 if (!shader) {
978 pipe_mutex_unlock(sel->mutex);
979 return -ENOMEM;
980 }
981 shader->selector = sel;
982 shader->key = *key;
983
984 r = si_shader_create(sctx->screen, sctx->tm, shader, &sctx->b.debug);
985 if (unlikely(r)) {
986 R600_ERR("Failed to build shader variant (type=%u) %d\n",
987 sel->type, r);
988 FREE(shader);
989 pipe_mutex_unlock(sel->mutex);
990 return r;
991 }
992 si_shader_init_pm4_state(shader);
993
994 if (!sel->last_variant) {
995 sel->first_variant = shader;
996 sel->last_variant = shader;
997 } else {
998 sel->last_variant->next_variant = shader;
999 sel->last_variant = shader;
1000 }
1001 state->current = shader;
1002 pipe_mutex_unlock(sel->mutex);
1003 return 0;
1004 }
1005
1006 static int si_shader_select(struct pipe_context *ctx,
1007 struct si_shader_ctx_state *state)
1008 {
1009 union si_shader_key key;
1010
1011 si_shader_selector_key(ctx, state->cso, &key);
1012 return si_shader_select_with_key(ctx, state, &key);
1013 }
1014
1015 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
1016 union si_shader_key *key)
1017 {
1018 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
1019
1020 switch (info->processor) {
1021 case PIPE_SHADER_VERTEX:
1022 switch (next_shader) {
1023 case PIPE_SHADER_GEOMETRY:
1024 key->vs.as_es = 1;
1025 break;
1026 case PIPE_SHADER_TESS_CTRL:
1027 case PIPE_SHADER_TESS_EVAL:
1028 key->vs.as_ls = 1;
1029 break;
1030 }
1031 break;
1032
1033 case PIPE_SHADER_TESS_EVAL:
1034 if (next_shader == PIPE_SHADER_GEOMETRY)
1035 key->tes.as_es = 1;
1036 break;
1037 }
1038 }
1039
1040 static void *si_create_shader_selector(struct pipe_context *ctx,
1041 const struct pipe_shader_state *state)
1042 {
1043 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
1044 struct si_context *sctx = (struct si_context*)ctx;
1045 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
1046 int i;
1047
1048 if (!sel)
1049 return NULL;
1050
1051 sel->tokens = tgsi_dup_tokens(state->tokens);
1052 if (!sel->tokens) {
1053 FREE(sel);
1054 return NULL;
1055 }
1056
1057 sel->so = state->stream_output;
1058 tgsi_scan_shader(state->tokens, &sel->info);
1059 sel->type = sel->info.processor;
1060 p_atomic_inc(&sscreen->b.num_shaders_created);
1061
1062 /* Set which opcode uses which (i,j) pair. */
1063 if (sel->info.uses_persp_opcode_interp_centroid)
1064 sel->info.uses_persp_centroid = true;
1065
1066 if (sel->info.uses_linear_opcode_interp_centroid)
1067 sel->info.uses_linear_centroid = true;
1068
1069 if (sel->info.uses_persp_opcode_interp_offset ||
1070 sel->info.uses_persp_opcode_interp_sample)
1071 sel->info.uses_persp_center = true;
1072
1073 if (sel->info.uses_linear_opcode_interp_offset ||
1074 sel->info.uses_linear_opcode_interp_sample)
1075 sel->info.uses_linear_center = true;
1076
1077 switch (sel->type) {
1078 case PIPE_SHADER_GEOMETRY:
1079 sel->gs_output_prim =
1080 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
1081 sel->gs_max_out_vertices =
1082 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
1083 sel->gs_num_invocations =
1084 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
1085 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
1086 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
1087 sel->gs_max_out_vertices;
1088
1089 sel->max_gs_stream = 0;
1090 for (i = 0; i < sel->so.num_outputs; i++)
1091 sel->max_gs_stream = MAX2(sel->max_gs_stream,
1092 sel->so.output[i].stream);
1093
1094 sel->gs_input_verts_per_prim =
1095 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
1096 break;
1097
1098 case PIPE_SHADER_VERTEX:
1099 case PIPE_SHADER_TESS_CTRL:
1100 case PIPE_SHADER_TESS_EVAL:
1101 for (i = 0; i < sel->info.num_outputs; i++) {
1102 unsigned name = sel->info.output_semantic_name[i];
1103 unsigned index = sel->info.output_semantic_index[i];
1104
1105 switch (name) {
1106 case TGSI_SEMANTIC_TESSINNER:
1107 case TGSI_SEMANTIC_TESSOUTER:
1108 case TGSI_SEMANTIC_PATCH:
1109 sel->patch_outputs_written |=
1110 1llu << si_shader_io_get_unique_index(name, index);
1111 break;
1112 default:
1113 sel->outputs_written |=
1114 1llu << si_shader_io_get_unique_index(name, index);
1115 }
1116 }
1117 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
1118 break;
1119
1120 case PIPE_SHADER_FRAGMENT:
1121 for (i = 0; i < 8; i++)
1122 if (sel->info.colors_written & (1 << i))
1123 sel->colors_written_4bit |= 0xf << (4 * i);
1124
1125 for (i = 0; i < sel->info.num_inputs; i++) {
1126 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
1127 int index = sel->info.input_semantic_index[i];
1128 sel->color_attr_index[index] = i;
1129 }
1130 }
1131 break;
1132 }
1133
1134 /* DB_SHADER_CONTROL */
1135 sel->db_shader_control =
1136 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
1137 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
1138 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
1139 S_02880C_KILL_ENABLE(sel->info.uses_kill);
1140
1141 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
1142 case TGSI_FS_DEPTH_LAYOUT_GREATER:
1143 sel->db_shader_control |=
1144 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
1145 break;
1146 case TGSI_FS_DEPTH_LAYOUT_LESS:
1147 sel->db_shader_control |=
1148 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
1149 break;
1150 }
1151
1152 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL])
1153 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1);
1154
1155 if (sel->info.writes_memory)
1156 sel->db_shader_control |= S_02880C_EXEC_ON_HIER_FAIL(1) |
1157 S_02880C_EXEC_ON_NOOP(1);
1158
1159 /* Compile the main shader part for use with a prolog and/or epilog. */
1160 if (sel->type != PIPE_SHADER_GEOMETRY &&
1161 !sscreen->use_monolithic_shaders) {
1162 struct si_shader *shader = CALLOC_STRUCT(si_shader);
1163 void *tgsi_binary;
1164
1165 if (!shader)
1166 goto error;
1167
1168 shader->selector = sel;
1169 si_parse_next_shader_property(&sel->info, &shader->key);
1170
1171 tgsi_binary = si_get_tgsi_binary(sel);
1172
1173 /* Try to load the shader from the shader cache. */
1174 pipe_mutex_lock(sscreen->shader_cache_mutex);
1175
1176 if (tgsi_binary &&
1177 si_shader_cache_load_shader(sscreen, tgsi_binary, shader)) {
1178 FREE(tgsi_binary);
1179 } else {
1180 /* Compile the shader if it hasn't been loaded from the cache. */
1181 if (si_compile_tgsi_shader(sscreen, sctx->tm, shader, false,
1182 &sctx->b.debug) != 0) {
1183 FREE(shader);
1184 FREE(tgsi_binary);
1185 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1186 goto error;
1187 }
1188
1189 if (tgsi_binary &&
1190 !si_shader_cache_insert_shader(sscreen, tgsi_binary, shader))
1191 FREE(tgsi_binary);
1192 }
1193 pipe_mutex_unlock(sscreen->shader_cache_mutex);
1194
1195 sel->main_shader_part = shader;
1196 }
1197
1198 /* Pre-compilation. */
1199 if (sel->type == PIPE_SHADER_GEOMETRY ||
1200 sscreen->b.debug_flags & DBG_PRECOMPILE) {
1201 struct si_shader_ctx_state state = {sel};
1202 union si_shader_key key;
1203
1204 memset(&key, 0, sizeof(key));
1205 si_parse_next_shader_property(&sel->info, &key);
1206
1207 /* Set reasonable defaults, so that the shader key doesn't
1208 * cause any code to be eliminated.
1209 */
1210 switch (sel->type) {
1211 case PIPE_SHADER_TESS_CTRL:
1212 key.tcs.epilog.prim_mode = PIPE_PRIM_TRIANGLES;
1213 break;
1214 case PIPE_SHADER_FRAGMENT:
1215 key.ps.epilog.alpha_func = PIPE_FUNC_ALWAYS;
1216 for (i = 0; i < 8; i++)
1217 if (sel->info.colors_written & (1 << i))
1218 key.ps.epilog.spi_shader_col_format |=
1219 V_028710_SPI_SHADER_FP16_ABGR << (i * 4);
1220 break;
1221 }
1222
1223 if (si_shader_select_with_key(ctx, &state, &key))
1224 goto error;
1225 }
1226
1227 pipe_mutex_init(sel->mutex);
1228 return sel;
1229
1230 error:
1231 fprintf(stderr, "radeonsi: can't create a shader\n");
1232 tgsi_free_tokens(sel->tokens);
1233 FREE(sel);
1234 return NULL;
1235 }
1236
1237 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
1238 {
1239 struct si_context *sctx = (struct si_context *)ctx;
1240 struct si_shader_selector *sel = state;
1241
1242 if (sctx->vs_shader.cso == sel)
1243 return;
1244
1245 sctx->vs_shader.cso = sel;
1246 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
1247 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1248 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1249 }
1250
1251 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
1252 {
1253 struct si_context *sctx = (struct si_context *)ctx;
1254 struct si_shader_selector *sel = state;
1255 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
1256
1257 if (sctx->gs_shader.cso == sel)
1258 return;
1259
1260 sctx->gs_shader.cso = sel;
1261 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
1262 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1263 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1264
1265 if (enable_changed)
1266 si_shader_change_notify(sctx);
1267 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1268 }
1269
1270 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
1271 {
1272 struct si_context *sctx = (struct si_context *)ctx;
1273 struct si_shader_selector *sel = state;
1274 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
1275
1276 if (sctx->tcs_shader.cso == sel)
1277 return;
1278
1279 sctx->tcs_shader.cso = sel;
1280 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
1281
1282 if (enable_changed)
1283 sctx->last_tcs = NULL; /* invalidate derived tess state */
1284 }
1285
1286 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
1287 {
1288 struct si_context *sctx = (struct si_context *)ctx;
1289 struct si_shader_selector *sel = state;
1290 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
1291
1292 if (sctx->tes_shader.cso == sel)
1293 return;
1294
1295 sctx->tes_shader.cso = sel;
1296 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
1297 si_mark_atom_dirty(sctx, &sctx->clip_regs);
1298 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
1299
1300 if (enable_changed) {
1301 si_shader_change_notify(sctx);
1302 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
1303 }
1304 r600_update_vs_writes_viewport_index(&sctx->b, si_get_vs_info(sctx));
1305 }
1306
1307 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
1308 {
1309 struct si_context *sctx = (struct si_context *)ctx;
1310 struct si_shader_selector *sel = state;
1311
1312 /* skip if supplied shader is one already in use */
1313 if (sctx->ps_shader.cso == sel)
1314 return;
1315
1316 sctx->ps_shader.cso = sel;
1317 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
1318 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
1319 }
1320
1321 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
1322 {
1323 if (shader->pm4) {
1324 switch (shader->selector->type) {
1325 case PIPE_SHADER_VERTEX:
1326 if (shader->key.vs.as_ls)
1327 si_pm4_delete_state(sctx, ls, shader->pm4);
1328 else if (shader->key.vs.as_es)
1329 si_pm4_delete_state(sctx, es, shader->pm4);
1330 else
1331 si_pm4_delete_state(sctx, vs, shader->pm4);
1332 break;
1333 case PIPE_SHADER_TESS_CTRL:
1334 si_pm4_delete_state(sctx, hs, shader->pm4);
1335 break;
1336 case PIPE_SHADER_TESS_EVAL:
1337 if (shader->key.tes.as_es)
1338 si_pm4_delete_state(sctx, es, shader->pm4);
1339 else
1340 si_pm4_delete_state(sctx, vs, shader->pm4);
1341 break;
1342 case PIPE_SHADER_GEOMETRY:
1343 si_pm4_delete_state(sctx, gs, shader->pm4);
1344 si_pm4_delete_state(sctx, vs, shader->gs_copy_shader->pm4);
1345 break;
1346 case PIPE_SHADER_FRAGMENT:
1347 si_pm4_delete_state(sctx, ps, shader->pm4);
1348 break;
1349 }
1350 }
1351
1352 si_shader_destroy(shader);
1353 free(shader);
1354 }
1355
1356 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
1357 {
1358 struct si_context *sctx = (struct si_context *)ctx;
1359 struct si_shader_selector *sel = (struct si_shader_selector *)state;
1360 struct si_shader *p = sel->first_variant, *c;
1361 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
1362 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
1363 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
1364 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
1365 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
1366 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
1367 };
1368
1369 if (current_shader[sel->type]->cso == sel) {
1370 current_shader[sel->type]->cso = NULL;
1371 current_shader[sel->type]->current = NULL;
1372 }
1373
1374 while (p) {
1375 c = p->next_variant;
1376 si_delete_shader(sctx, p);
1377 p = c;
1378 }
1379
1380 if (sel->main_shader_part)
1381 si_delete_shader(sctx, sel->main_shader_part);
1382
1383 pipe_mutex_destroy(sel->mutex);
1384 free(sel->tokens);
1385 free(sel);
1386 }
1387
1388 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
1389 struct si_shader *vs, unsigned name,
1390 unsigned index, unsigned interpolate)
1391 {
1392 struct tgsi_shader_info *vsinfo = &vs->selector->info;
1393 unsigned j, ps_input_cntl = 0;
1394
1395 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
1396 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade))
1397 ps_input_cntl |= S_028644_FLAT_SHADE(1);
1398
1399 if (name == TGSI_SEMANTIC_PCOORD ||
1400 (name == TGSI_SEMANTIC_TEXCOORD &&
1401 sctx->sprite_coord_enable & (1 << index))) {
1402 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
1403 }
1404
1405 for (j = 0; j < vsinfo->num_outputs; j++) {
1406 if (name == vsinfo->output_semantic_name[j] &&
1407 index == vsinfo->output_semantic_index[j]) {
1408 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[j]);
1409 break;
1410 }
1411 }
1412
1413 if (name == TGSI_SEMANTIC_PRIMID)
1414 /* PrimID is written after the last output. */
1415 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
1416 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
1417 /* No corresponding output found, load defaults into input.
1418 * Don't set any other bits.
1419 * (FLAT_SHADE=1 completely changes behavior) */
1420 ps_input_cntl = S_028644_OFFSET(0x20);
1421 /* D3D 9 behaviour. GL is undefined */
1422 if (name == TGSI_SEMANTIC_COLOR && index == 0)
1423 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
1424 }
1425 return ps_input_cntl;
1426 }
1427
1428 static void si_emit_spi_map(struct si_context *sctx, struct r600_atom *atom)
1429 {
1430 struct radeon_winsys_cs *cs = sctx->b.gfx.cs;
1431 struct si_shader *ps = sctx->ps_shader.current;
1432 struct si_shader *vs = si_get_vs_state(sctx);
1433 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
1434 unsigned i, num_interp, num_written = 0, bcol_interp[2];
1435
1436 if (!ps || !ps->selector->info.num_inputs)
1437 return;
1438
1439 num_interp = si_get_ps_num_interp(ps);
1440 assert(num_interp > 0);
1441 radeon_set_context_reg_seq(cs, R_028644_SPI_PS_INPUT_CNTL_0, num_interp);
1442
1443 for (i = 0; i < psinfo->num_inputs; i++) {
1444 unsigned name = psinfo->input_semantic_name[i];
1445 unsigned index = psinfo->input_semantic_index[i];
1446 unsigned interpolate = psinfo->input_interpolate[i];
1447
1448 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, name, index,
1449 interpolate));
1450 num_written++;
1451
1452 if (name == TGSI_SEMANTIC_COLOR) {
1453 assert(index < ARRAY_SIZE(bcol_interp));
1454 bcol_interp[index] = interpolate;
1455 }
1456 }
1457
1458 if (ps->key.ps.prolog.color_two_side) {
1459 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
1460
1461 for (i = 0; i < 2; i++) {
1462 if (!(psinfo->colors_read & (0xf << (i * 4))))
1463 continue;
1464
1465 radeon_emit(cs, si_get_ps_input_cntl(sctx, vs, bcol,
1466 i, bcol_interp[i]));
1467 num_written++;
1468 }
1469 }
1470 assert(num_interp == num_written);
1471 }
1472
1473 /**
1474 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
1475 */
1476 static void si_init_config_add_vgt_flush(struct si_context *sctx)
1477 {
1478 if (sctx->init_config_has_vgt_flush)
1479 return;
1480
1481 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
1482 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
1483 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
1484 si_pm4_cmd_end(sctx->init_config, false);
1485 sctx->init_config_has_vgt_flush = true;
1486 }
1487
1488 /* Initialize state related to ESGS / GSVS ring buffers */
1489 static bool si_update_gs_ring_buffers(struct si_context *sctx)
1490 {
1491 struct si_shader_selector *es =
1492 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
1493 struct si_shader_selector *gs = sctx->gs_shader.cso;
1494 struct si_pm4_state *pm4;
1495
1496 /* Chip constants. */
1497 unsigned num_se = sctx->screen->b.info.max_se;
1498 unsigned wave_size = 64;
1499 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1500 unsigned gs_vertex_reuse = 16 * num_se; /* GS_VERTEX_REUSE register (per SE) */
1501 unsigned alignment = 256 * num_se;
1502 /* The maximum size is 63.999 MB per SE. */
1503 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1504
1505 /* Calculate the minimum size. */
1506 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
1507 wave_size, alignment);
1508
1509 /* These are recommended sizes, not minimum sizes. */
1510 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1511 es->esgs_itemsize * gs->gs_input_verts_per_prim;
1512 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1513 gs->max_gsvs_emit_size * (gs->max_gs_stream + 1);
1514
1515 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1516 esgs_ring_size = align(esgs_ring_size, alignment);
1517 gsvs_ring_size = align(gsvs_ring_size, alignment);
1518
1519 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1520 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1521
1522 /* Some rings don't have to be allocated if shaders don't use them.
1523 * (e.g. no varyings between ES and GS or GS and VS)
1524 */
1525 bool update_esgs = esgs_ring_size &&
1526 (!sctx->esgs_ring ||
1527 sctx->esgs_ring->width0 < esgs_ring_size);
1528 bool update_gsvs = gsvs_ring_size &&
1529 (!sctx->gsvs_ring ||
1530 sctx->gsvs_ring->width0 < gsvs_ring_size);
1531
1532 if (!update_esgs && !update_gsvs)
1533 return true;
1534
1535 if (update_esgs) {
1536 pipe_resource_reference(&sctx->esgs_ring, NULL);
1537 sctx->esgs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1538 PIPE_USAGE_DEFAULT,
1539 esgs_ring_size);
1540 if (!sctx->esgs_ring)
1541 return false;
1542 }
1543
1544 if (update_gsvs) {
1545 pipe_resource_reference(&sctx->gsvs_ring, NULL);
1546 sctx->gsvs_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1547 PIPE_USAGE_DEFAULT,
1548 gsvs_ring_size);
1549 if (!sctx->gsvs_ring)
1550 return false;
1551 }
1552
1553 /* Create the "init_config_gs_rings" state. */
1554 pm4 = CALLOC_STRUCT(si_pm4_state);
1555 if (!pm4)
1556 return false;
1557
1558 if (sctx->b.chip_class >= CIK) {
1559 if (sctx->esgs_ring)
1560 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
1561 sctx->esgs_ring->width0 / 256);
1562 if (sctx->gsvs_ring)
1563 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
1564 sctx->gsvs_ring->width0 / 256);
1565 } else {
1566 if (sctx->esgs_ring)
1567 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
1568 sctx->esgs_ring->width0 / 256);
1569 if (sctx->gsvs_ring)
1570 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
1571 sctx->gsvs_ring->width0 / 256);
1572 }
1573
1574 /* Set the state. */
1575 if (sctx->init_config_gs_rings)
1576 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
1577 sctx->init_config_gs_rings = pm4;
1578
1579 if (!sctx->init_config_has_vgt_flush) {
1580 si_init_config_add_vgt_flush(sctx);
1581 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1582 }
1583
1584 /* Flush the context to re-emit both init_config states. */
1585 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1586 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1587
1588 /* Set ring bindings. */
1589 if (sctx->esgs_ring) {
1590 si_set_ring_buffer(&sctx->b.b, SI_ES_RING_ESGS,
1591 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1592 true, true, 4, 64, 0);
1593 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_ESGS,
1594 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
1595 false, false, 0, 0, 0);
1596 }
1597 if (sctx->gsvs_ring)
1598 si_set_ring_buffer(&sctx->b.b, SI_VS_RING_GSVS,
1599 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
1600 false, false, 0, 0, 0);
1601 return true;
1602 }
1603
1604 static void si_update_gsvs_ring_bindings(struct si_context *sctx)
1605 {
1606 unsigned gsvs_itemsize = sctx->gs_shader.cso->max_gsvs_emit_size;
1607 uint64_t offset;
1608
1609 if (!sctx->gsvs_ring || gsvs_itemsize == sctx->last_gsvs_itemsize)
1610 return;
1611
1612 sctx->last_gsvs_itemsize = gsvs_itemsize;
1613
1614 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS0,
1615 sctx->gsvs_ring, gsvs_itemsize,
1616 64, true, true, 4, 16, 0);
1617
1618 offset = gsvs_itemsize * 64;
1619 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS1,
1620 sctx->gsvs_ring, gsvs_itemsize,
1621 64, true, true, 4, 16, offset);
1622
1623 offset = (gsvs_itemsize * 2) * 64;
1624 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS2,
1625 sctx->gsvs_ring, gsvs_itemsize,
1626 64, true, true, 4, 16, offset);
1627
1628 offset = (gsvs_itemsize * 3) * 64;
1629 si_set_ring_buffer(&sctx->b.b, SI_GS_RING_GSVS3,
1630 sctx->gsvs_ring, gsvs_itemsize,
1631 64, true, true, 4, 16, offset);
1632 }
1633
1634 /**
1635 * @returns 1 if \p sel has been updated to use a new scratch buffer
1636 * 0 if not
1637 * < 0 if there was a failure
1638 */
1639 static int si_update_scratch_buffer(struct si_context *sctx,
1640 struct si_shader *shader)
1641 {
1642 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
1643 int r;
1644
1645 if (!shader)
1646 return 0;
1647
1648 /* This shader doesn't need a scratch buffer */
1649 if (shader->config.scratch_bytes_per_wave == 0)
1650 return 0;
1651
1652 /* This shader is already configured to use the current
1653 * scratch buffer. */
1654 if (shader->scratch_bo == sctx->scratch_buffer)
1655 return 0;
1656
1657 assert(sctx->scratch_buffer);
1658
1659 si_shader_apply_scratch_relocs(sctx, shader, &shader->config, scratch_va);
1660
1661 /* Replace the shader bo with a new bo that has the relocs applied. */
1662 r = si_shader_binary_upload(sctx->screen, shader);
1663 if (r)
1664 return r;
1665
1666 /* Update the shader state to use the new shader bo. */
1667 si_shader_init_pm4_state(shader);
1668
1669 r600_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
1670
1671 return 1;
1672 }
1673
1674 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
1675 {
1676 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
1677 }
1678
1679 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
1680 {
1681 return shader ? shader->config.scratch_bytes_per_wave : 0;
1682 }
1683
1684 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
1685 {
1686 unsigned bytes = 0;
1687
1688 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
1689 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
1690 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
1691 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tcs_shader.current));
1692 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
1693 return bytes;
1694 }
1695
1696 static bool si_update_spi_tmpring_size(struct si_context *sctx)
1697 {
1698 unsigned current_scratch_buffer_size =
1699 si_get_current_scratch_buffer_size(sctx);
1700 unsigned scratch_bytes_per_wave =
1701 si_get_max_scratch_bytes_per_wave(sctx);
1702 unsigned scratch_needed_size = scratch_bytes_per_wave *
1703 sctx->scratch_waves;
1704 unsigned spi_tmpring_size;
1705 int r;
1706
1707 if (scratch_needed_size > 0) {
1708 if (scratch_needed_size > current_scratch_buffer_size) {
1709 /* Create a bigger scratch buffer */
1710 pipe_resource_reference(
1711 (struct pipe_resource**)&sctx->scratch_buffer,
1712 NULL);
1713
1714 sctx->scratch_buffer =
1715 si_resource_create_custom(&sctx->screen->b.b,
1716 PIPE_USAGE_DEFAULT, scratch_needed_size);
1717 if (!sctx->scratch_buffer)
1718 return false;
1719 sctx->emit_scratch_reloc = true;
1720 }
1721
1722 /* Update the shaders, so they are using the latest scratch. The
1723 * scratch buffer may have been changed since these shaders were
1724 * last used, so we still need to try to update them, even if
1725 * they require scratch buffers smaller than the current size.
1726 */
1727 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
1728 if (r < 0)
1729 return false;
1730 if (r == 1)
1731 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
1732
1733 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
1734 if (r < 0)
1735 return false;
1736 if (r == 1)
1737 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1738
1739 r = si_update_scratch_buffer(sctx, sctx->tcs_shader.current);
1740 if (r < 0)
1741 return false;
1742 if (r == 1)
1743 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1744
1745 /* VS can be bound as LS, ES, or VS. */
1746 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
1747 if (r < 0)
1748 return false;
1749 if (r == 1) {
1750 if (sctx->tes_shader.current)
1751 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1752 else if (sctx->gs_shader.current)
1753 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1754 else
1755 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1756 }
1757
1758 /* TES can be bound as ES or VS. */
1759 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
1760 if (r < 0)
1761 return false;
1762 if (r == 1) {
1763 if (sctx->gs_shader.current)
1764 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1765 else
1766 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1767 }
1768 }
1769
1770 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
1771 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
1772 "scratch size should already be aligned correctly.");
1773
1774 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
1775 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
1776 if (spi_tmpring_size != sctx->spi_tmpring_size) {
1777 sctx->spi_tmpring_size = spi_tmpring_size;
1778 sctx->emit_scratch_reloc = true;
1779 }
1780 return true;
1781 }
1782
1783 static void si_init_tess_factor_ring(struct si_context *sctx)
1784 {
1785 unsigned offchip_blocks = sctx->b.chip_class >= CIK ? 256 : 64;
1786 assert(!sctx->tf_ring);
1787
1788 sctx->tf_ring = pipe_buffer_create(sctx->b.b.screen, PIPE_BIND_CUSTOM,
1789 PIPE_USAGE_DEFAULT,
1790 32768 * sctx->screen->b.info.max_se);
1791 if (!sctx->tf_ring)
1792 return;
1793
1794 assert(((sctx->tf_ring->width0 / 4) & C_030938_SIZE) == 0);
1795
1796 sctx->tess_offchip_ring = pipe_buffer_create(sctx->b.b.screen,
1797 PIPE_BIND_CUSTOM,
1798 PIPE_USAGE_DEFAULT,
1799 offchip_blocks *
1800 SI_TESS_OFFCHIP_BLOCK_SIZE);
1801 if (!sctx->tess_offchip_ring)
1802 return;
1803
1804 si_init_config_add_vgt_flush(sctx);
1805
1806 /* Append these registers to the init config state. */
1807 if (sctx->b.chip_class >= CIK) {
1808 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
1809 S_030938_SIZE(sctx->tf_ring->width0 / 4));
1810 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
1811 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1812 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
1813 S_03093C_OFFCHIP_BUFFERING(offchip_blocks - 1) |
1814 S_03093C_OFFCHIP_GRANULARITY(V_03093C_X_8K_DWORDS));
1815 } else {
1816 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
1817 S_008988_SIZE(sctx->tf_ring->width0 / 4));
1818 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
1819 r600_resource(sctx->tf_ring)->gpu_address >> 8);
1820 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
1821 S_0089B0_OFFCHIP_BUFFERING(offchip_blocks - 1));
1822 }
1823
1824 /* Flush the context to re-emit the init_config state.
1825 * This is done only once in a lifetime of a context.
1826 */
1827 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
1828 sctx->b.initial_gfx_cs_size = 0; /* force flush */
1829 si_context_gfx_flush(sctx, RADEON_FLUSH_ASYNC, NULL);
1830
1831 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_FACTOR, sctx->tf_ring,
1832 0, sctx->tf_ring->width0, false, false, 0, 0, 0);
1833
1834 si_set_ring_buffer(&sctx->b.b, SI_HS_RING_TESS_OFFCHIP,
1835 sctx->tess_offchip_ring, 0,
1836 sctx->tess_offchip_ring->width0, false, false, 0, 0, 0);
1837 }
1838
1839 /**
1840 * This is used when TCS is NULL in the VS->TCS->TES chain. In this case,
1841 * VS passes its outputs to TES directly, so the fixed-function shader only
1842 * has to write TESSOUTER and TESSINNER.
1843 */
1844 static void si_generate_fixed_func_tcs(struct si_context *sctx)
1845 {
1846 struct ureg_src outer, inner;
1847 struct ureg_dst tessouter, tessinner;
1848 struct ureg_program *ureg = ureg_create(PIPE_SHADER_TESS_CTRL);
1849
1850 if (!ureg)
1851 return; /* if we get here, we're screwed */
1852
1853 assert(!sctx->fixed_func_tcs_shader.cso);
1854
1855 outer = ureg_DECL_system_value(ureg,
1856 TGSI_SEMANTIC_DEFAULT_TESSOUTER_SI, 0);
1857 inner = ureg_DECL_system_value(ureg,
1858 TGSI_SEMANTIC_DEFAULT_TESSINNER_SI, 0);
1859
1860 tessouter = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSOUTER, 0);
1861 tessinner = ureg_DECL_output(ureg, TGSI_SEMANTIC_TESSINNER, 0);
1862
1863 ureg_MOV(ureg, tessouter, outer);
1864 ureg_MOV(ureg, tessinner, inner);
1865 ureg_END(ureg);
1866
1867 sctx->fixed_func_tcs_shader.cso =
1868 ureg_create_shader_and_destroy(ureg, &sctx->b.b);
1869 }
1870
1871 static void si_update_vgt_shader_config(struct si_context *sctx)
1872 {
1873 /* Calculate the index of the config.
1874 * 0 = VS, 1 = VS+GS, 2 = VS+Tess, 3 = VS+Tess+GS */
1875 unsigned index = 2*!!sctx->tes_shader.cso + !!sctx->gs_shader.cso;
1876 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[index];
1877
1878 if (!*pm4) {
1879 uint32_t stages = 0;
1880
1881 *pm4 = CALLOC_STRUCT(si_pm4_state);
1882
1883 if (sctx->tes_shader.cso) {
1884 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
1885 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
1886
1887 if (sctx->gs_shader.cso)
1888 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
1889 S_028B54_GS_EN(1) |
1890 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1891 else
1892 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
1893 } else if (sctx->gs_shader.cso) {
1894 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
1895 S_028B54_GS_EN(1) |
1896 S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
1897 }
1898
1899 si_pm4_set_reg(*pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
1900 }
1901 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
1902 }
1903
1904 static void si_update_so(struct si_context *sctx, struct si_shader_selector *shader)
1905 {
1906 struct pipe_stream_output_info *so = &shader->so;
1907 uint32_t enabled_stream_buffers_mask = 0;
1908 int i;
1909
1910 for (i = 0; i < so->num_outputs; i++)
1911 enabled_stream_buffers_mask |= (1 << so->output[i].output_buffer) << (so->output[i].stream * 4);
1912 sctx->b.streamout.enabled_stream_buffers_mask = enabled_stream_buffers_mask;
1913 sctx->b.streamout.stride_in_dw = shader->so.stride;
1914 }
1915
1916 bool si_update_shaders(struct si_context *sctx)
1917 {
1918 struct pipe_context *ctx = (struct pipe_context*)sctx;
1919 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1920 int r;
1921
1922 /* Update stages before GS. */
1923 if (sctx->tes_shader.cso) {
1924 if (!sctx->tf_ring) {
1925 si_init_tess_factor_ring(sctx);
1926 if (!sctx->tf_ring)
1927 return false;
1928 }
1929
1930 /* VS as LS */
1931 r = si_shader_select(ctx, &sctx->vs_shader);
1932 if (r)
1933 return false;
1934 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
1935
1936 if (sctx->tcs_shader.cso) {
1937 r = si_shader_select(ctx, &sctx->tcs_shader);
1938 if (r)
1939 return false;
1940 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
1941 } else {
1942 if (!sctx->fixed_func_tcs_shader.cso) {
1943 si_generate_fixed_func_tcs(sctx);
1944 if (!sctx->fixed_func_tcs_shader.cso)
1945 return false;
1946 }
1947
1948 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader);
1949 if (r)
1950 return false;
1951 si_pm4_bind_state(sctx, hs,
1952 sctx->fixed_func_tcs_shader.current->pm4);
1953 }
1954
1955 r = si_shader_select(ctx, &sctx->tes_shader);
1956 if (r)
1957 return false;
1958
1959 if (sctx->gs_shader.cso) {
1960 /* TES as ES */
1961 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
1962 } else {
1963 /* TES as VS */
1964 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
1965 si_update_so(sctx, sctx->tes_shader.cso);
1966 }
1967 } else if (sctx->gs_shader.cso) {
1968 /* VS as ES */
1969 r = si_shader_select(ctx, &sctx->vs_shader);
1970 if (r)
1971 return false;
1972 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
1973 } else {
1974 /* VS as VS */
1975 r = si_shader_select(ctx, &sctx->vs_shader);
1976 if (r)
1977 return false;
1978 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
1979 si_update_so(sctx, sctx->vs_shader.cso);
1980 }
1981
1982 /* Update GS. */
1983 if (sctx->gs_shader.cso) {
1984 r = si_shader_select(ctx, &sctx->gs_shader);
1985 if (r)
1986 return false;
1987 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
1988 si_pm4_bind_state(sctx, vs, sctx->gs_shader.current->gs_copy_shader->pm4);
1989 si_update_so(sctx, sctx->gs_shader.cso);
1990
1991 if (!si_update_gs_ring_buffers(sctx))
1992 return false;
1993
1994 si_update_gsvs_ring_bindings(sctx);
1995 } else {
1996 si_pm4_bind_state(sctx, gs, NULL);
1997 si_pm4_bind_state(sctx, es, NULL);
1998 }
1999
2000 si_update_vgt_shader_config(sctx);
2001
2002 if (sctx->ps_shader.cso) {
2003 unsigned db_shader_control;
2004
2005 r = si_shader_select(ctx, &sctx->ps_shader);
2006 if (r)
2007 return false;
2008 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
2009
2010 db_shader_control =
2011 sctx->ps_shader.cso->db_shader_control |
2012 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS) |
2013 S_02880C_Z_ORDER(sctx->ps_shader.current->z_order);
2014
2015 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
2016 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
2017 sctx->flatshade != rs->flatshade) {
2018 sctx->sprite_coord_enable = rs->sprite_coord_enable;
2019 sctx->flatshade = rs->flatshade;
2020 si_mark_atom_dirty(sctx, &sctx->spi_map);
2021 }
2022
2023 if (sctx->b.family == CHIP_STONEY && si_pm4_state_changed(sctx, ps))
2024 si_mark_atom_dirty(sctx, &sctx->cb_render_state);
2025
2026 if (sctx->ps_db_shader_control != db_shader_control) {
2027 sctx->ps_db_shader_control = db_shader_control;
2028 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2029 }
2030
2031 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing) {
2032 sctx->smoothing_enabled = sctx->ps_shader.current->key.ps.epilog.poly_line_smoothing;
2033 si_mark_atom_dirty(sctx, &sctx->msaa_config);
2034
2035 if (sctx->b.chip_class == SI)
2036 si_mark_atom_dirty(sctx, &sctx->db_render_state);
2037 }
2038 }
2039
2040 if (si_pm4_state_changed(sctx, ls) ||
2041 si_pm4_state_changed(sctx, hs) ||
2042 si_pm4_state_changed(sctx, es) ||
2043 si_pm4_state_changed(sctx, gs) ||
2044 si_pm4_state_changed(sctx, vs) ||
2045 si_pm4_state_changed(sctx, ps)) {
2046 if (!si_update_spi_tmpring_size(sctx))
2047 return false;
2048 }
2049 return true;
2050 }
2051
2052 void si_init_shader_functions(struct si_context *sctx)
2053 {
2054 si_init_atom(sctx, &sctx->spi_map, &sctx->atoms.s.spi_map, si_emit_spi_map);
2055
2056 sctx->b.b.create_vs_state = si_create_shader_selector;
2057 sctx->b.b.create_tcs_state = si_create_shader_selector;
2058 sctx->b.b.create_tes_state = si_create_shader_selector;
2059 sctx->b.b.create_gs_state = si_create_shader_selector;
2060 sctx->b.b.create_fs_state = si_create_shader_selector;
2061
2062 sctx->b.b.bind_vs_state = si_bind_vs_shader;
2063 sctx->b.b.bind_tcs_state = si_bind_tcs_shader;
2064 sctx->b.b.bind_tes_state = si_bind_tes_shader;
2065 sctx->b.b.bind_gs_state = si_bind_gs_shader;
2066 sctx->b.b.bind_fs_state = si_bind_ps_shader;
2067
2068 sctx->b.b.delete_vs_state = si_delete_shader_selector;
2069 sctx->b.b.delete_tcs_state = si_delete_shader_selector;
2070 sctx->b.b.delete_tes_state = si_delete_shader_selector;
2071 sctx->b.b.delete_gs_state = si_delete_shader_selector;
2072 sctx->b.b.delete_fs_state = si_delete_shader_selector;
2073 }