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gallium: add TGSI_PROPERTY_VS_BLIT_SGPRS_AMD for tgsi_to_nir
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 void *si_get_ir_binary(struct si_shader_selector *sel)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 unsigned size = 4 + ir_size + sizeof(sel->so);
68 char *result = (char*)MALLOC(size);
69 if (!result)
70 return NULL;
71
72 *((uint32_t*)result) = size;
73 memcpy(result + 4, ir_binary, ir_size);
74 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
75
76 if (sel->nir)
77 blob_finish(&blob);
78
79 return result;
80 }
81
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
84 {
85 /* data may be NULL if size == 0 */
86 if (size)
87 memcpy(ptr, data, size);
88 ptr += DIV_ROUND_UP(size, 4);
89 return ptr;
90 }
91
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
94 {
95 memcpy(data, ptr, size);
96 ptr += DIV_ROUND_UP(size, 4);
97 return ptr;
98 }
99
100 /**
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
103 */
104 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
105 {
106 *ptr++ = size;
107 return write_data(ptr, data, size);
108 }
109
110 /**
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
113 */
114 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
115 {
116 *size = *ptr++;
117 assert(*data == NULL);
118 if (!*size)
119 return ptr;
120 *data = malloc(*size);
121 return read_data(ptr, *data, *size);
122 }
123
124 /**
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
126 * as integer.
127 */
128 static void *si_get_shader_binary(struct si_shader *shader)
129 {
130 /* There is always a size of data followed by the data itself. */
131 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
132 strlen(shader->binary.llvm_ir_string) + 1 : 0;
133
134 /* Refuse to allocate overly large buffers and guard against integer
135 * overflow. */
136 if (shader->binary.elf_size > UINT_MAX / 4 ||
137 llvm_ir_size > UINT_MAX / 4)
138 return NULL;
139
140 unsigned size =
141 4 + /* total size */
142 4 + /* CRC32 of the data below */
143 align(sizeof(shader->config), 4) +
144 align(sizeof(shader->info), 4) +
145 4 + align(shader->binary.elf_size, 4) +
146 4 + align(llvm_ir_size, 4);
147 void *buffer = CALLOC(1, size);
148 uint32_t *ptr = (uint32_t*)buffer;
149
150 if (!buffer)
151 return NULL;
152
153 *ptr++ = size;
154 ptr++; /* CRC32 is calculated at the end. */
155
156 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
157 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
158 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
159 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
160 assert((char *)ptr - (char *)buffer == size);
161
162 /* Compute CRC32. */
163 ptr = (uint32_t*)buffer;
164 ptr++;
165 *ptr = util_hash_crc32(ptr + 1, size - 8);
166
167 return buffer;
168 }
169
170 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
171 {
172 uint32_t *ptr = (uint32_t*)binary;
173 uint32_t size = *ptr++;
174 uint32_t crc32 = *ptr++;
175 unsigned chunk_size;
176 unsigned elf_size;
177
178 if (util_hash_crc32(ptr, size - 8) != crc32) {
179 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
180 return false;
181 }
182
183 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
184 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
185 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
186 &elf_size);
187 shader->binary.elf_size = elf_size;
188 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
189
190 return true;
191 }
192
193 /**
194 * Insert a shader into the cache. It's assumed the shader is not in the cache.
195 * Use si_shader_cache_load_shader before calling this.
196 *
197 * Returns false on failure, in which case the ir_binary should be freed.
198 */
199 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
200 struct si_shader *shader,
201 bool insert_into_disk_cache)
202 {
203 void *hw_binary;
204 struct hash_entry *entry;
205 uint8_t key[CACHE_KEY_SIZE];
206
207 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
208 if (entry)
209 return false; /* already added */
210
211 hw_binary = si_get_shader_binary(shader);
212 if (!hw_binary)
213 return false;
214
215 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
216 hw_binary) == NULL) {
217 FREE(hw_binary);
218 return false;
219 }
220
221 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
222 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
223 *((uint32_t *)ir_binary), key);
224 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
225 *((uint32_t *) hw_binary), NULL);
226 }
227
228 return true;
229 }
230
231 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
232 struct si_shader *shader)
233 {
234 struct hash_entry *entry =
235 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
236 if (!entry) {
237 if (sscreen->disk_shader_cache) {
238 unsigned char sha1[CACHE_KEY_SIZE];
239 size_t tg_size = *((uint32_t *) ir_binary);
240
241 disk_cache_compute_key(sscreen->disk_shader_cache,
242 ir_binary, tg_size, sha1);
243
244 size_t binary_size;
245 uint8_t *buffer =
246 disk_cache_get(sscreen->disk_shader_cache,
247 sha1, &binary_size);
248 if (!buffer)
249 return false;
250
251 if (binary_size < sizeof(uint32_t) ||
252 *((uint32_t*)buffer) != binary_size) {
253 /* Something has gone wrong discard the item
254 * from the cache and rebuild/link from
255 * source.
256 */
257 assert(!"Invalid radeonsi shader disk cache "
258 "item!");
259
260 disk_cache_remove(sscreen->disk_shader_cache,
261 sha1);
262 free(buffer);
263
264 return false;
265 }
266
267 if (!si_load_shader_binary(shader, buffer)) {
268 free(buffer);
269 return false;
270 }
271 free(buffer);
272
273 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
274 shader, false))
275 FREE(ir_binary);
276 } else {
277 return false;
278 }
279 } else {
280 if (si_load_shader_binary(shader, entry->data))
281 FREE(ir_binary);
282 else
283 return false;
284 }
285 p_atomic_inc(&sscreen->num_shader_cache_hits);
286 return true;
287 }
288
289 static uint32_t si_shader_cache_key_hash(const void *key)
290 {
291 /* The first dword is the key size. */
292 return util_hash_crc32(key, *(uint32_t*)key);
293 }
294
295 static bool si_shader_cache_key_equals(const void *a, const void *b)
296 {
297 uint32_t *keya = (uint32_t*)a;
298 uint32_t *keyb = (uint32_t*)b;
299
300 /* The first dword is the key size. */
301 if (*keya != *keyb)
302 return false;
303
304 return memcmp(keya, keyb, *keya) == 0;
305 }
306
307 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
308 {
309 FREE((void*)entry->key);
310 FREE(entry->data);
311 }
312
313 bool si_init_shader_cache(struct si_screen *sscreen)
314 {
315 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
316 sscreen->shader_cache =
317 _mesa_hash_table_create(NULL,
318 si_shader_cache_key_hash,
319 si_shader_cache_key_equals);
320
321 return sscreen->shader_cache != NULL;
322 }
323
324 void si_destroy_shader_cache(struct si_screen *sscreen)
325 {
326 if (sscreen->shader_cache)
327 _mesa_hash_table_destroy(sscreen->shader_cache,
328 si_destroy_shader_cache_entry);
329 mtx_destroy(&sscreen->shader_cache_mutex);
330 }
331
332 /* SHADER STATES */
333
334 static void si_set_tesseval_regs(struct si_screen *sscreen,
335 const struct si_shader_selector *tes,
336 struct si_pm4_state *pm4)
337 {
338 const struct tgsi_shader_info *info = &tes->info;
339 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
340 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
341 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
342 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
343 unsigned type, partitioning, topology, distribution_mode;
344
345 switch (tes_prim_mode) {
346 case PIPE_PRIM_LINES:
347 type = V_028B6C_TESS_ISOLINE;
348 break;
349 case PIPE_PRIM_TRIANGLES:
350 type = V_028B6C_TESS_TRIANGLE;
351 break;
352 case PIPE_PRIM_QUADS:
353 type = V_028B6C_TESS_QUAD;
354 break;
355 default:
356 assert(0);
357 return;
358 }
359
360 switch (tes_spacing) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
362 partitioning = V_028B6C_PART_FRAC_ODD;
363 break;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
365 partitioning = V_028B6C_PART_FRAC_EVEN;
366 break;
367 case PIPE_TESS_SPACING_EQUAL:
368 partitioning = V_028B6C_PART_INTEGER;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 if (tes_point_mode)
376 topology = V_028B6C_OUTPUT_POINT;
377 else if (tes_prim_mode == PIPE_PRIM_LINES)
378 topology = V_028B6C_OUTPUT_LINE;
379 else if (tes_vertex_order_cw)
380 /* for some reason, this must be the other way around */
381 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
382 else
383 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
384
385 if (sscreen->has_distributed_tess) {
386 if (sscreen->info.family == CHIP_FIJI ||
387 sscreen->info.family >= CHIP_POLARIS10)
388 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
389 else
390 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
391 } else
392 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
393
394 assert(pm4->shader);
395 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
396 S_028B6C_PARTITIONING(partitioning) |
397 S_028B6C_TOPOLOGY(topology) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
399 }
400
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
403 *
404 * Possible VGT configurations and which state should set the register:
405 *
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
408 * VS as VS | VS | 30
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 *
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 */
415 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
416 struct si_shader_selector *sel,
417 struct si_shader *shader,
418 struct si_pm4_state *pm4)
419 {
420 unsigned type = sel->type;
421
422 if (sscreen->info.family < CHIP_POLARIS10 ||
423 sscreen->info.chip_class >= GFX10)
424 return;
425
426 /* VS as VS, or VS as ES: */
427 if ((type == PIPE_SHADER_VERTEX &&
428 (!shader ||
429 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
430 /* TES as VS, or TES as ES: */
431 type == PIPE_SHADER_TESS_EVAL) {
432 unsigned vtx_reuse_depth = 30;
433
434 if (type == PIPE_SHADER_TESS_EVAL &&
435 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD)
437 vtx_reuse_depth = 14;
438
439 assert(pm4->shader);
440 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
441 }
442 }
443
444 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
445 {
446 if (shader->pm4)
447 si_pm4_clear_state(shader->pm4);
448 else
449 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
450
451 if (shader->pm4) {
452 shader->pm4->shader = shader;
453 return shader->pm4;
454 } else {
455 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
456 return NULL;
457 }
458 }
459
460 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
461 {
462 /* Add the pointer to VBO descriptors. */
463 return num_always_on_user_sgprs + 1;
464 }
465
466 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
467 {
468 struct si_pm4_state *pm4;
469 unsigned vgpr_comp_cnt;
470 uint64_t va;
471
472 assert(sscreen->info.chip_class <= GFX8);
473
474 pm4 = si_get_shader_pm4_state(shader);
475 if (!pm4)
476 return;
477
478 va = shader->bo->gpu_address;
479 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
480
481 /* We need at least 2 components for LS.
482 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
483 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
484 */
485 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
486
487 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
488 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
489
490 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
491 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
492 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
493 S_00B528_DX10_CLAMP(1) |
494 S_00B528_FLOAT_MODE(shader->config.float_mode);
495 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
496 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
497 }
498
499 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
500 {
501 struct si_pm4_state *pm4;
502 uint64_t va;
503 unsigned ls_vgpr_comp_cnt = 0;
504
505 pm4 = si_get_shader_pm4_state(shader);
506 if (!pm4)
507 return;
508
509 va = shader->bo->gpu_address;
510 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
511
512 if (sscreen->info.chip_class >= GFX9) {
513 if (sscreen->info.chip_class >= GFX10) {
514 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
515 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
516 } else {
517 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
518 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
519 }
520
521 /* We need at least 2 components for LS.
522 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
523 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
524 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
525 * be loaded.
526 */
527 ls_vgpr_comp_cnt = 1;
528 if (shader->info.uses_instanceid) {
529 if (sscreen->info.chip_class >= GFX10)
530 ls_vgpr_comp_cnt = 3;
531 else
532 ls_vgpr_comp_cnt = 2;
533 }
534
535 unsigned num_user_sgprs =
536 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
537
538 shader->config.rsrc2 =
539 S_00B42C_USER_SGPR(num_user_sgprs) |
540 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
541
542 if (sscreen->info.chip_class >= GFX10)
543 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
544 else
545 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
546 } else {
547 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
548 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
549
550 shader->config.rsrc2 =
551 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
552 S_00B42C_OC_LDS_EN(1) |
553 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
554 }
555
556 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
557 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
558 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
559 (sscreen->info.chip_class <= GFX9 ?
560 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
561 S_00B428_DX10_CLAMP(1) |
562 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
563 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
564 S_00B428_FLOAT_MODE(shader->config.float_mode) |
565 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
566
567 if (sscreen->info.chip_class <= GFX8) {
568 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
569 shader->config.rsrc2);
570 }
571 }
572
573 static void si_emit_shader_es(struct si_context *sctx)
574 {
575 struct si_shader *shader = sctx->queued.named.es->shader;
576 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
577
578 if (!shader)
579 return;
580
581 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
582 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
583 shader->selector->esgs_itemsize / 4);
584
585 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
586 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
587 SI_TRACKED_VGT_TF_PARAM,
588 shader->vgt_tf_param);
589
590 if (shader->vgt_vertex_reuse_block_cntl)
591 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
592 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
593 shader->vgt_vertex_reuse_block_cntl);
594
595 if (initial_cdw != sctx->gfx_cs->current.cdw)
596 sctx->context_roll = true;
597 }
598
599 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
600 {
601 struct si_pm4_state *pm4;
602 unsigned num_user_sgprs;
603 unsigned vgpr_comp_cnt;
604 uint64_t va;
605 unsigned oc_lds_en;
606
607 assert(sscreen->info.chip_class <= GFX8);
608
609 pm4 = si_get_shader_pm4_state(shader);
610 if (!pm4)
611 return;
612
613 pm4->atom.emit = si_emit_shader_es;
614 va = shader->bo->gpu_address;
615 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
616
617 if (shader->selector->type == PIPE_SHADER_VERTEX) {
618 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
619 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
620 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
621 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
622 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
623 num_user_sgprs = SI_TES_NUM_USER_SGPR;
624 } else
625 unreachable("invalid shader selector type");
626
627 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
628
629 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
630 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
631 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
632 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
633 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
634 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
635 S_00B328_DX10_CLAMP(1) |
636 S_00B328_FLOAT_MODE(shader->config.float_mode));
637 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
638 S_00B32C_USER_SGPR(num_user_sgprs) |
639 S_00B32C_OC_LDS_EN(oc_lds_en) |
640 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
641
642 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
643 si_set_tesseval_regs(sscreen, shader->selector, pm4);
644
645 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
646 }
647
648 void gfx9_get_gs_info(struct si_shader_selector *es,
649 struct si_shader_selector *gs,
650 struct gfx9_gs_info *out)
651 {
652 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
653 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
654 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
655 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
656
657 /* All these are in dwords: */
658 /* We can't allow using the whole LDS, because GS waves compete with
659 * other shader stages for LDS space. */
660 const unsigned max_lds_size = 8 * 1024;
661 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
662 unsigned esgs_lds_size;
663
664 /* All these are per subgroup: */
665 const unsigned max_out_prims = 32 * 1024;
666 const unsigned max_es_verts = 255;
667 const unsigned ideal_gs_prims = 64;
668 unsigned max_gs_prims, gs_prims;
669 unsigned min_es_verts, es_verts, worst_case_es_verts;
670
671 if (uses_adjacency || gs_num_invocations > 1)
672 max_gs_prims = 127 / gs_num_invocations;
673 else
674 max_gs_prims = 255;
675
676 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
677 * Make sure we don't go over the maximum value.
678 */
679 if (gs->gs_max_out_vertices > 0) {
680 max_gs_prims = MIN2(max_gs_prims,
681 max_out_prims /
682 (gs->gs_max_out_vertices * gs_num_invocations));
683 }
684 assert(max_gs_prims > 0);
685
686 /* If the primitive has adjacency, halve the number of vertices
687 * that will be reused in multiple primitives.
688 */
689 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
690
691 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
692 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
693
694 /* Compute ESGS LDS size based on the worst case number of ES vertices
695 * needed to create the target number of GS prims per subgroup.
696 */
697 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
698
699 /* If total LDS usage is too big, refactor partitions based on ratio
700 * of ESGS item sizes.
701 */
702 if (esgs_lds_size > max_lds_size) {
703 /* Our target GS Prims Per Subgroup was too large. Calculate
704 * the maximum number of GS Prims Per Subgroup that will fit
705 * into LDS, capped by the maximum that the hardware can support.
706 */
707 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
708 max_gs_prims);
709 assert(gs_prims > 0);
710 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
711 max_es_verts);
712
713 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
714 assert(esgs_lds_size <= max_lds_size);
715 }
716
717 /* Now calculate remaining ESGS information. */
718 if (esgs_lds_size)
719 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
720 else
721 es_verts = max_es_verts;
722
723 /* Vertices for adjacency primitives are not always reused, so restore
724 * it for ES_VERTS_PER_SUBGRP.
725 */
726 min_es_verts = gs->gs_input_verts_per_prim;
727
728 /* For normal primitives, the VGT only checks if they are past the ES
729 * verts per subgroup after allocating a full GS primitive and if they
730 * are, kick off a new subgroup. But if those additional ES verts are
731 * unique (e.g. not reused) we need to make sure there is enough LDS
732 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
733 */
734 es_verts -= min_es_verts - 1;
735
736 out->es_verts_per_subgroup = es_verts;
737 out->gs_prims_per_subgroup = gs_prims;
738 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
739 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
740 gs->gs_max_out_vertices;
741 out->esgs_ring_size = 4 * esgs_lds_size;
742
743 assert(out->max_prims_per_subgroup <= max_out_prims);
744 }
745
746 static void si_emit_shader_gs(struct si_context *sctx)
747 {
748 struct si_shader *shader = sctx->queued.named.gs->shader;
749 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
750
751 if (!shader)
752 return;
753
754 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
755 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
756 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
757 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
758 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
759 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
760 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
761
762 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
763 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
764 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
765 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
766
767 /* R_028B38_VGT_GS_MAX_VERT_OUT */
768 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
769 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
770 shader->ctx_reg.gs.vgt_gs_max_vert_out);
771
772 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
773 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
774 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
775 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
776 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
777 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
778 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
779 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
780
781 /* R_028B90_VGT_GS_INSTANCE_CNT */
782 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
783 SI_TRACKED_VGT_GS_INSTANCE_CNT,
784 shader->ctx_reg.gs.vgt_gs_instance_cnt);
785
786 if (sctx->chip_class >= GFX9) {
787 /* R_028A44_VGT_GS_ONCHIP_CNTL */
788 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
789 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
790 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
791 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
792 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
793 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
794 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
795 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
796 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
797 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
798 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
799
800 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
801 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
802 SI_TRACKED_VGT_TF_PARAM,
803 shader->vgt_tf_param);
804 if (shader->vgt_vertex_reuse_block_cntl)
805 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
806 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
807 shader->vgt_vertex_reuse_block_cntl);
808 }
809
810 if (initial_cdw != sctx->gfx_cs->current.cdw)
811 sctx->context_roll = true;
812 }
813
814 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
815 {
816 struct si_shader_selector *sel = shader->selector;
817 const ubyte *num_components = sel->info.num_stream_output_components;
818 unsigned gs_num_invocations = sel->gs_num_invocations;
819 struct si_pm4_state *pm4;
820 uint64_t va;
821 unsigned max_stream = sel->max_gs_stream;
822 unsigned offset;
823
824 pm4 = si_get_shader_pm4_state(shader);
825 if (!pm4)
826 return;
827
828 pm4->atom.emit = si_emit_shader_gs;
829
830 offset = num_components[0] * sel->gs_max_out_vertices;
831 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
832
833 if (max_stream >= 1)
834 offset += num_components[1] * sel->gs_max_out_vertices;
835 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
836
837 if (max_stream >= 2)
838 offset += num_components[2] * sel->gs_max_out_vertices;
839 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
840
841 if (max_stream >= 3)
842 offset += num_components[3] * sel->gs_max_out_vertices;
843 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
844
845 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
846 assert(offset < (1 << 15));
847
848 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
849
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
851 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
852 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
853 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
854
855 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
856 S_028B90_ENABLE(gs_num_invocations > 0);
857
858 va = shader->bo->gpu_address;
859 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
860
861 if (sscreen->info.chip_class >= GFX9) {
862 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
863 unsigned es_type = shader->key.part.gs.es->type;
864 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
865
866 if (es_type == PIPE_SHADER_VERTEX)
867 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
868 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
869 else if (es_type == PIPE_SHADER_TESS_EVAL)
870 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
871 else
872 unreachable("invalid shader selector type");
873
874 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
875 * VGPR[0:4] are always loaded.
876 */
877 if (sel->info.uses_invocationid)
878 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
879 else if (sel->info.uses_primid)
880 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
881 else if (input_prim >= PIPE_PRIM_TRIANGLES)
882 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
883 else
884 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
885
886 unsigned num_user_sgprs;
887 if (es_type == PIPE_SHADER_VERTEX)
888 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
889 else
890 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
891
892 if (sscreen->info.chip_class >= GFX10) {
893 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
894 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
895 } else {
896 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
897 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
898 }
899
900 uint32_t rsrc1 =
901 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
902 S_00B228_DX10_CLAMP(1) |
903 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
904 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
905 S_00B228_FLOAT_MODE(shader->config.float_mode) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
907 uint32_t rsrc2 =
908 S_00B22C_USER_SGPR(num_user_sgprs) |
909 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
910 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
911 S_00B22C_LDS_SIZE(shader->config.lds_size) |
912 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
913
914 if (sscreen->info.chip_class >= GFX10) {
915 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
916 } else {
917 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
918 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
919 }
920
921 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
922 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
923
924 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
925 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
926 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
927 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
928 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
929 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
930 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
931 shader->key.part.gs.es->esgs_itemsize / 4;
932
933 if (es_type == PIPE_SHADER_TESS_EVAL)
934 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
935
936 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
937 NULL, pm4);
938 } else {
939 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
940 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
941
942 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
943 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
944 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
945 S_00B228_DX10_CLAMP(1) |
946 S_00B228_FLOAT_MODE(shader->config.float_mode));
947 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
948 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
949 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
950 }
951 }
952
953 /* Common tail code for NGG primitive shaders. */
954 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
955 struct si_shader *shader,
956 unsigned initial_cdw)
957 {
958 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
959 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
960 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
961 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
962 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
963 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
964 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
965 SI_TRACKED_VGT_PRIMITIVEID_EN,
966 shader->ctx_reg.ngg.vgt_primitiveid_en);
967 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
968 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
969 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
970 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
971 SI_TRACKED_VGT_GS_INSTANCE_CNT,
972 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
973 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
974 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
975 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
976 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
977 SI_TRACKED_SPI_VS_OUT_CONFIG,
978 shader->ctx_reg.ngg.spi_vs_out_config);
979 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
980 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
981 shader->ctx_reg.ngg.spi_shader_idx_format,
982 shader->ctx_reg.ngg.spi_shader_pos_format);
983 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
984 SI_TRACKED_PA_CL_VTE_CNTL,
985 shader->ctx_reg.ngg.pa_cl_vte_cntl);
986 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
987 SI_TRACKED_PA_CL_NGG_CNTL,
988 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
989
990 if (initial_cdw != sctx->gfx_cs->current.cdw)
991 sctx->context_roll = true;
992 }
993
994 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
995 {
996 struct si_shader *shader = sctx->queued.named.gs->shader;
997 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
998
999 if (!shader)
1000 return;
1001
1002 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1003 }
1004
1005 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1006 {
1007 struct si_shader *shader = sctx->queued.named.gs->shader;
1008 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1009
1010 if (!shader)
1011 return;
1012
1013 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1014 SI_TRACKED_VGT_TF_PARAM,
1015 shader->vgt_tf_param);
1016
1017 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1018 }
1019
1020 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1021 {
1022 struct si_shader *shader = sctx->queued.named.gs->shader;
1023 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1024
1025 if (!shader)
1026 return;
1027
1028 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1029 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1030 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1031
1032 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1033 }
1034
1035 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1036 {
1037 struct si_shader *shader = sctx->queued.named.gs->shader;
1038 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1039
1040 if (!shader)
1041 return;
1042
1043 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1044 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1045 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1046 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1047 SI_TRACKED_VGT_TF_PARAM,
1048 shader->vgt_tf_param);
1049
1050 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1051 }
1052
1053 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1054 {
1055 if (gs->type == PIPE_SHADER_GEOMETRY)
1056 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1057
1058 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1059 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1060 return PIPE_PRIM_POINTS;
1061 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1062 return PIPE_PRIM_LINES;
1063 return PIPE_PRIM_TRIANGLES;
1064 }
1065
1066 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1067 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1068 }
1069
1070 /**
1071 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1072 * in NGG mode.
1073 */
1074 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1075 {
1076 const struct si_shader_selector *gs_sel = shader->selector;
1077 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1078 enum pipe_shader_type gs_type = shader->selector->type;
1079 const struct si_shader_selector *es_sel =
1080 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1081 const struct tgsi_shader_info *es_info = &es_sel->info;
1082 enum pipe_shader_type es_type = es_sel->type;
1083 unsigned num_user_sgprs;
1084 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1085 uint64_t va;
1086 unsigned window_space =
1087 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1088 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1089 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1090 unsigned input_prim = si_get_input_prim(gs_sel);
1091 bool break_wave_at_eoi = false;
1092 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1093 if (!pm4)
1094 return;
1095
1096 if (es_type == PIPE_SHADER_TESS_EVAL) {
1097 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1098 : gfx10_emit_shader_ngg_tess_nogs;
1099 } else {
1100 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1101 : gfx10_emit_shader_ngg_notess_nogs;
1102 }
1103
1104 va = shader->bo->gpu_address;
1105 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1106
1107 if (es_type == PIPE_SHADER_VERTEX) {
1108 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1109 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1110
1111 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1112 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1113 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1114 } else {
1115 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1116 }
1117 } else {
1118 assert(es_type == PIPE_SHADER_TESS_EVAL);
1119 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1120 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1121
1122 if (es_enable_prim_id || gs_info->uses_primid)
1123 break_wave_at_eoi = true;
1124 }
1125
1126 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1127 * VGPR[0:4] are always loaded.
1128 *
1129 * Vertex shaders always need to load VGPR3, because they need to
1130 * pass edge flags for decomposed primitives (such as quads) to the PA
1131 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1132 */
1133 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1134 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1135 else if (gs_info->uses_primid)
1136 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1137 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1138 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1139 else
1140 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1141
1142 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1143 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1144 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1145 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1146 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1147 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1148 S_00B228_DX10_CLAMP(1) |
1149 S_00B228_MEM_ORDERED(1) |
1150 S_00B228_WGP_MODE(1) |
1151 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1152 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1153 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1154 S_00B22C_USER_SGPR(num_user_sgprs) |
1155 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1156 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1157 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1158 S_00B22C_LDS_SIZE(shader->config.lds_size));
1159
1160 nparams = MAX2(shader->info.nr_param_exports, 1);
1161 shader->ctx_reg.ngg.spi_vs_out_config =
1162 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1163 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1164
1165 shader->ctx_reg.ngg.spi_shader_idx_format =
1166 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1167 shader->ctx_reg.ngg.spi_shader_pos_format =
1168 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1169 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1170 V_02870C_SPI_SHADER_4COMP :
1171 V_02870C_SPI_SHADER_NONE) |
1172 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1173 V_02870C_SPI_SHADER_4COMP :
1174 V_02870C_SPI_SHADER_NONE) |
1175 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1176 V_02870C_SPI_SHADER_4COMP :
1177 V_02870C_SPI_SHADER_NONE);
1178
1179 shader->ctx_reg.ngg.vgt_primitiveid_en =
1180 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1181 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1182
1183 if (gs_type == PIPE_SHADER_GEOMETRY) {
1184 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1185 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1186 } else {
1187 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1188 }
1189
1190 if (es_type == PIPE_SHADER_TESS_EVAL)
1191 si_set_tesseval_regs(sscreen, es_sel, pm4);
1192
1193 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1194 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1195 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1196 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1197 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1198 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1199 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1200 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1201 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1202 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1203 S_028B90_CNT(gs_num_invocations) |
1204 S_028B90_ENABLE(gs_num_invocations > 1) |
1205 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1206 shader->ngg.max_vert_out_per_gs_instance);
1207
1208 /* Always output hw-generated edge flags and pass them via the prim
1209 * export to prevent drawing lines on internal edges of decomposed
1210 * primitives (such as quads) with polygon mode = lines. Only VS needs
1211 * this.
1212 */
1213 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1214 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1215
1216 shader->ge_cntl =
1217 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1218 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1219 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1220
1221 /* Bug workaround for a possible hang with non-tessellation cases.
1222 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1223 *
1224 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1225 */
1226 if ((sscreen->info.family == CHIP_NAVI10 ||
1227 sscreen->info.family == CHIP_NAVI12 ||
1228 sscreen->info.family == CHIP_NAVI14) &&
1229 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1230 shader->ngg.hw_max_esverts != 256) {
1231 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1232
1233 if (shader->ngg.hw_max_esverts > 5) {
1234 shader->ge_cntl |=
1235 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1236 }
1237 }
1238
1239 if (window_space) {
1240 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1241 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1242 } else {
1243 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1244 S_028818_VTX_W0_FMT(1) |
1245 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1246 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1247 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1248 }
1249 }
1250
1251 static void si_emit_shader_vs(struct si_context *sctx)
1252 {
1253 struct si_shader *shader = sctx->queued.named.vs->shader;
1254 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1255
1256 if (!shader)
1257 return;
1258
1259 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1260 SI_TRACKED_VGT_GS_MODE,
1261 shader->ctx_reg.vs.vgt_gs_mode);
1262 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1263 SI_TRACKED_VGT_PRIMITIVEID_EN,
1264 shader->ctx_reg.vs.vgt_primitiveid_en);
1265
1266 if (sctx->chip_class <= GFX8) {
1267 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1268 SI_TRACKED_VGT_REUSE_OFF,
1269 shader->ctx_reg.vs.vgt_reuse_off);
1270 }
1271
1272 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1273 SI_TRACKED_SPI_VS_OUT_CONFIG,
1274 shader->ctx_reg.vs.spi_vs_out_config);
1275
1276 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1277 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1278 shader->ctx_reg.vs.spi_shader_pos_format);
1279
1280 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1281 SI_TRACKED_PA_CL_VTE_CNTL,
1282 shader->ctx_reg.vs.pa_cl_vte_cntl);
1283
1284 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1285 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1286 SI_TRACKED_VGT_TF_PARAM,
1287 shader->vgt_tf_param);
1288
1289 if (shader->vgt_vertex_reuse_block_cntl)
1290 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1291 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1292 shader->vgt_vertex_reuse_block_cntl);
1293
1294 if (initial_cdw != sctx->gfx_cs->current.cdw)
1295 sctx->context_roll = true;
1296 }
1297
1298 /**
1299 * Compute the state for \p shader, which will run as a vertex shader on the
1300 * hardware.
1301 *
1302 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1303 * is the copy shader.
1304 */
1305 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1306 struct si_shader_selector *gs)
1307 {
1308 const struct tgsi_shader_info *info = &shader->selector->info;
1309 struct si_pm4_state *pm4;
1310 unsigned num_user_sgprs, vgpr_comp_cnt;
1311 uint64_t va;
1312 unsigned nparams, oc_lds_en;
1313 unsigned window_space =
1314 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1315 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1316
1317 pm4 = si_get_shader_pm4_state(shader);
1318 if (!pm4)
1319 return;
1320
1321 pm4->atom.emit = si_emit_shader_vs;
1322
1323 /* We always write VGT_GS_MODE in the VS state, because every switch
1324 * between different shader pipelines involving a different GS or no
1325 * GS at all involves a switch of the VS (different GS use different
1326 * copy shaders). On the other hand, when the API switches from a GS to
1327 * no GS and then back to the same GS used originally, the GS state is
1328 * not sent again.
1329 */
1330 if (!gs) {
1331 unsigned mode = V_028A40_GS_OFF;
1332
1333 /* PrimID needs GS scenario A. */
1334 if (enable_prim_id)
1335 mode = V_028A40_GS_SCENARIO_A;
1336
1337 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1338 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1339 } else {
1340 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1341 sscreen->info.chip_class);
1342 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1343 }
1344
1345 if (sscreen->info.chip_class <= GFX8) {
1346 /* Reuse needs to be set off if we write oViewport. */
1347 shader->ctx_reg.vs.vgt_reuse_off =
1348 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1349 }
1350
1351 va = shader->bo->gpu_address;
1352 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1353
1354 if (gs) {
1355 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1356 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1357 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1358 if (sscreen->info.chip_class >= GFX10) {
1359 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
1360 } else {
1361 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1362 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1363 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1364 */
1365 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1366 }
1367
1368 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1369 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1370 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1371 } else {
1372 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1373 }
1374 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1375 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1376 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1377 } else
1378 unreachable("invalid shader selector type");
1379
1380 /* VS is required to export at least one param. */
1381 nparams = MAX2(shader->info.nr_param_exports, 1);
1382 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1383
1384 if (sscreen->info.chip_class >= GFX10) {
1385 shader->ctx_reg.vs.spi_vs_out_config |=
1386 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1387 }
1388
1389 shader->ctx_reg.vs.spi_shader_pos_format =
1390 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1391 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1392 V_02870C_SPI_SHADER_4COMP :
1393 V_02870C_SPI_SHADER_NONE) |
1394 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1395 V_02870C_SPI_SHADER_4COMP :
1396 V_02870C_SPI_SHADER_NONE) |
1397 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1398 V_02870C_SPI_SHADER_4COMP :
1399 V_02870C_SPI_SHADER_NONE);
1400
1401 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1402
1403 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1404 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1405
1406 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1407 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1408 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1409 S_00B128_DX10_CLAMP(1) |
1410 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1411 S_00B128_FLOAT_MODE(shader->config.float_mode);
1412 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1413 S_00B12C_OC_LDS_EN(oc_lds_en) |
1414 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1415
1416 if (sscreen->info.chip_class <= GFX9)
1417 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1418
1419 if (!sscreen->use_ngg_streamout) {
1420 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1421 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1422 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1423 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1424 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1425 }
1426
1427 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1428 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1429
1430 if (window_space)
1431 shader->ctx_reg.vs.pa_cl_vte_cntl =
1432 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1433 else
1434 shader->ctx_reg.vs.pa_cl_vte_cntl =
1435 S_028818_VTX_W0_FMT(1) |
1436 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1437 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1438 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1439
1440 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1441 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1442
1443 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1444 }
1445
1446 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1447 {
1448 struct tgsi_shader_info *info = &ps->selector->info;
1449 unsigned num_colors = !!(info->colors_read & 0x0f) +
1450 !!(info->colors_read & 0xf0);
1451 unsigned num_interp = ps->selector->info.num_inputs +
1452 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1453
1454 assert(num_interp <= 32);
1455 return MIN2(num_interp, 32);
1456 }
1457
1458 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1459 {
1460 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1461 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1462
1463 /* If the i-th target format is set, all previous target formats must
1464 * be non-zero to avoid hangs.
1465 */
1466 for (i = 0; i < num_targets; i++)
1467 if (!(value & (0xf << (i * 4))))
1468 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1469
1470 return value;
1471 }
1472
1473 static void si_emit_shader_ps(struct si_context *sctx)
1474 {
1475 struct si_shader *shader = sctx->queued.named.ps->shader;
1476 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1477
1478 if (!shader)
1479 return;
1480
1481 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1482 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1483 SI_TRACKED_SPI_PS_INPUT_ENA,
1484 shader->ctx_reg.ps.spi_ps_input_ena,
1485 shader->ctx_reg.ps.spi_ps_input_addr);
1486
1487 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1488 SI_TRACKED_SPI_BARYC_CNTL,
1489 shader->ctx_reg.ps.spi_baryc_cntl);
1490 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1491 SI_TRACKED_SPI_PS_IN_CONTROL,
1492 shader->ctx_reg.ps.spi_ps_in_control);
1493
1494 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1495 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1496 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1497 shader->ctx_reg.ps.spi_shader_z_format,
1498 shader->ctx_reg.ps.spi_shader_col_format);
1499
1500 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1501 SI_TRACKED_CB_SHADER_MASK,
1502 shader->ctx_reg.ps.cb_shader_mask);
1503
1504 if (initial_cdw != sctx->gfx_cs->current.cdw)
1505 sctx->context_roll = true;
1506 }
1507
1508 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1509 {
1510 struct tgsi_shader_info *info = &shader->selector->info;
1511 struct si_pm4_state *pm4;
1512 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1513 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1514 uint64_t va;
1515 unsigned input_ena = shader->config.spi_ps_input_ena;
1516
1517 /* we need to enable at least one of them, otherwise we hang the GPU */
1518 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1519 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1520 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1521 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1522 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1523 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1524 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1525 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1526 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1527 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1528 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1529 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1530 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1531 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1532
1533 /* Validate interpolation optimization flags (read as implications). */
1534 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1535 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1536 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1537 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1538 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1539 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1540 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1541 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1542 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1543 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1544 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1545 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1546 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1547 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1548 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1549 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1550 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1551 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1552
1553 /* Validate cases when the optimizations are off (read as implications). */
1554 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1555 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1556 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1557 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1558 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1559 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1560
1561 pm4 = si_get_shader_pm4_state(shader);
1562 if (!pm4)
1563 return;
1564
1565 pm4->atom.emit = si_emit_shader_ps;
1566
1567 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1568 * Possible vaules:
1569 * 0 -> Position = pixel center
1570 * 1 -> Position = pixel centroid
1571 * 2 -> Position = at sample position
1572 *
1573 * From GLSL 4.5 specification, section 7.1:
1574 * "The variable gl_FragCoord is available as an input variable from
1575 * within fragment shaders and it holds the window relative coordinates
1576 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1577 * value can be for any location within the pixel, or one of the
1578 * fragment samples. The use of centroid does not further restrict
1579 * this value to be inside the current primitive."
1580 *
1581 * Meaning that centroid has no effect and we can return anything within
1582 * the pixel. Thus, return the value at sample position, because that's
1583 * the most accurate one shaders can get.
1584 */
1585 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1586
1587 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1588 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1589 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1590
1591 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1592 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1593
1594 /* Ensure that some export memory is always allocated, for two reasons:
1595 *
1596 * 1) Correctness: The hardware ignores the EXEC mask if no export
1597 * memory is allocated, so KILL and alpha test do not work correctly
1598 * without this.
1599 * 2) Performance: Every shader needs at least a NULL export, even when
1600 * it writes no color/depth output. The NULL export instruction
1601 * stalls without this setting.
1602 *
1603 * Don't add this to CB_SHADER_MASK.
1604 *
1605 * GFX10 supports pixel shaders without exports by setting both
1606 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1607 * instructions if any are present.
1608 */
1609 if ((sscreen->info.chip_class <= GFX9 ||
1610 info->uses_kill ||
1611 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1612 !spi_shader_col_format &&
1613 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1614 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1615
1616 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1617 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1618
1619 /* Set interpolation controls. */
1620 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1621 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1622
1623 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1624 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1625 shader->ctx_reg.ps.spi_shader_z_format =
1626 ac_get_spi_shader_z_format(info->writes_z,
1627 info->writes_stencil,
1628 info->writes_samplemask);
1629 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1630 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1631
1632 va = shader->bo->gpu_address;
1633 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1634 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1635 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1636
1637 uint32_t rsrc1 =
1638 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1639 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1640 S_00B028_DX10_CLAMP(1) |
1641 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1642 S_00B028_FLOAT_MODE(shader->config.float_mode);
1643
1644 if (sscreen->info.chip_class < GFX10) {
1645 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1646 }
1647
1648 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1649 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1650 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1651 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1652 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1653 }
1654
1655 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1656 struct si_shader *shader)
1657 {
1658 switch (shader->selector->type) {
1659 case PIPE_SHADER_VERTEX:
1660 if (shader->key.as_ls)
1661 si_shader_ls(sscreen, shader);
1662 else if (shader->key.as_es)
1663 si_shader_es(sscreen, shader);
1664 else if (shader->key.as_ngg)
1665 gfx10_shader_ngg(sscreen, shader);
1666 else
1667 si_shader_vs(sscreen, shader, NULL);
1668 break;
1669 case PIPE_SHADER_TESS_CTRL:
1670 si_shader_hs(sscreen, shader);
1671 break;
1672 case PIPE_SHADER_TESS_EVAL:
1673 if (shader->key.as_es)
1674 si_shader_es(sscreen, shader);
1675 else if (shader->key.as_ngg)
1676 gfx10_shader_ngg(sscreen, shader);
1677 else
1678 si_shader_vs(sscreen, shader, NULL);
1679 break;
1680 case PIPE_SHADER_GEOMETRY:
1681 if (shader->key.as_ngg)
1682 gfx10_shader_ngg(sscreen, shader);
1683 else
1684 si_shader_gs(sscreen, shader);
1685 break;
1686 case PIPE_SHADER_FRAGMENT:
1687 si_shader_ps(sscreen, shader);
1688 break;
1689 default:
1690 assert(0);
1691 }
1692 }
1693
1694 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1695 {
1696 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1697 return sctx->queued.named.dsa->alpha_func;
1698 }
1699
1700 void si_shader_selector_key_vs(struct si_context *sctx,
1701 struct si_shader_selector *vs,
1702 struct si_shader_key *key,
1703 struct si_vs_prolog_bits *prolog_key)
1704 {
1705 if (!sctx->vertex_elements ||
1706 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1707 return;
1708
1709 struct si_vertex_elements *elts = sctx->vertex_elements;
1710
1711 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1712 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1713 prolog_key->unpack_instance_id_from_vertex_id =
1714 sctx->prim_discard_cs_instancing;
1715
1716 /* Prefer a monolithic shader to allow scheduling divisions around
1717 * VBO loads. */
1718 if (prolog_key->instance_divisor_is_fetched)
1719 key->opt.prefer_mono = 1;
1720
1721 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1722 unsigned count_mask = (1 << count) - 1;
1723 unsigned fix = elts->fix_fetch_always & count_mask;
1724 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1725
1726 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1727 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1728 while (mask) {
1729 unsigned i = u_bit_scan(&mask);
1730 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1731 unsigned vbidx = elts->vertex_buffer_index[i];
1732 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1733 unsigned align_mask = (1 << log_hw_load_size) - 1;
1734 if (vb->buffer_offset & align_mask ||
1735 vb->stride & align_mask) {
1736 fix |= 1 << i;
1737 opencode |= 1 << i;
1738 }
1739 }
1740 }
1741
1742 while (fix) {
1743 unsigned i = u_bit_scan(&fix);
1744 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1745 }
1746 key->mono.vs_fetch_opencode = opencode;
1747 }
1748
1749 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1750 struct si_shader_selector *vs,
1751 struct si_shader_key *key)
1752 {
1753 struct si_shader_selector *ps = sctx->ps_shader.cso;
1754
1755 key->opt.clip_disable =
1756 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1757 (vs->info.clipdist_writemask ||
1758 vs->info.writes_clipvertex) &&
1759 !vs->info.culldist_writemask;
1760
1761 /* Find out if PS is disabled. */
1762 bool ps_disabled = true;
1763 if (ps) {
1764 bool ps_modifies_zs = ps->info.uses_kill ||
1765 ps->info.writes_z ||
1766 ps->info.writes_stencil ||
1767 ps->info.writes_samplemask ||
1768 sctx->queued.named.blend->alpha_to_coverage ||
1769 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1770 unsigned ps_colormask = si_get_total_colormask(sctx);
1771
1772 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1773 (!ps_colormask &&
1774 !ps_modifies_zs &&
1775 !ps->info.writes_memory);
1776 }
1777
1778 /* Find out which VS outputs aren't used by the PS. */
1779 uint64_t outputs_written = vs->outputs_written_before_ps;
1780 uint64_t inputs_read = 0;
1781
1782 /* Ignore outputs that are not passed from VS to PS. */
1783 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1784 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1785 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1786
1787 if (!ps_disabled) {
1788 inputs_read = ps->inputs_read;
1789 }
1790
1791 uint64_t linked = outputs_written & inputs_read;
1792
1793 key->opt.kill_outputs = ~linked & outputs_written;
1794 }
1795
1796 /* Compute the key for the hw shader variant */
1797 static inline void si_shader_selector_key(struct pipe_context *ctx,
1798 struct si_shader_selector *sel,
1799 union si_vgt_stages_key stages_key,
1800 struct si_shader_key *key)
1801 {
1802 struct si_context *sctx = (struct si_context *)ctx;
1803
1804 memset(key, 0, sizeof(*key));
1805
1806 switch (sel->type) {
1807 case PIPE_SHADER_VERTEX:
1808 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1809
1810 if (sctx->tes_shader.cso)
1811 key->as_ls = 1;
1812 else if (sctx->gs_shader.cso)
1813 key->as_es = 1;
1814 else {
1815 key->as_ngg = stages_key.u.ngg;
1816 si_shader_selector_key_hw_vs(sctx, sel, key);
1817
1818 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1819 key->mono.u.vs_export_prim_id = 1;
1820 }
1821 break;
1822 case PIPE_SHADER_TESS_CTRL:
1823 if (sctx->chip_class >= GFX9) {
1824 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1825 key, &key->part.tcs.ls_prolog);
1826 key->part.tcs.ls = sctx->vs_shader.cso;
1827
1828 /* When the LS VGPR fix is needed, monolithic shaders
1829 * can:
1830 * - avoid initializing EXEC in both the LS prolog
1831 * and the LS main part when !vs_needs_prolog
1832 * - remove the fixup for unused input VGPRs
1833 */
1834 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1835
1836 /* The LS output / HS input layout can be communicated
1837 * directly instead of via user SGPRs for merged LS-HS.
1838 * The LS VGPR fix prefers this too.
1839 */
1840 key->opt.prefer_mono = 1;
1841 }
1842
1843 key->part.tcs.epilog.prim_mode =
1844 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1845 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1846 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1847 key->part.tcs.epilog.tes_reads_tess_factors =
1848 sctx->tes_shader.cso->info.reads_tess_factors;
1849
1850 if (sel == sctx->fixed_func_tcs_shader.cso)
1851 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1852 break;
1853 case PIPE_SHADER_TESS_EVAL:
1854 key->as_ngg = stages_key.u.ngg;
1855
1856 if (sctx->gs_shader.cso)
1857 key->as_es = 1;
1858 else {
1859 si_shader_selector_key_hw_vs(sctx, sel, key);
1860
1861 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1862 key->mono.u.vs_export_prim_id = 1;
1863 }
1864 break;
1865 case PIPE_SHADER_GEOMETRY:
1866 if (sctx->chip_class >= GFX9) {
1867 if (sctx->tes_shader.cso) {
1868 key->part.gs.es = sctx->tes_shader.cso;
1869 } else {
1870 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1871 key, &key->part.gs.vs_prolog);
1872 key->part.gs.es = sctx->vs_shader.cso;
1873 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1874 }
1875
1876 key->as_ngg = stages_key.u.ngg;
1877
1878 /* Merged ES-GS can have unbalanced wave usage.
1879 *
1880 * ES threads are per-vertex, while GS threads are
1881 * per-primitive. So without any amplification, there
1882 * are fewer GS threads than ES threads, which can result
1883 * in empty (no-op) GS waves. With too much amplification,
1884 * there are more GS threads than ES threads, which
1885 * can result in empty (no-op) ES waves.
1886 *
1887 * Non-monolithic shaders are implemented by setting EXEC
1888 * at the beginning of shader parts, and don't jump to
1889 * the end if EXEC is 0.
1890 *
1891 * Monolithic shaders use conditional blocks, so they can
1892 * jump and skip empty waves of ES or GS. So set this to
1893 * always use optimized variants, which are monolithic.
1894 */
1895 key->opt.prefer_mono = 1;
1896 }
1897 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1898 break;
1899 case PIPE_SHADER_FRAGMENT: {
1900 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1901 struct si_state_blend *blend = sctx->queued.named.blend;
1902
1903 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1904 sel->info.colors_written == 0x1)
1905 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1906
1907 /* Select the shader color format based on whether
1908 * blending or alpha are needed.
1909 */
1910 key->part.ps.epilog.spi_shader_col_format =
1911 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1912 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1913 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1914 sctx->framebuffer.spi_shader_col_format_blend) |
1915 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1916 sctx->framebuffer.spi_shader_col_format_alpha) |
1917 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1918 sctx->framebuffer.spi_shader_col_format);
1919 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1920
1921 /* The output for dual source blending should have
1922 * the same format as the first output.
1923 */
1924 if (blend->dual_src_blend) {
1925 key->part.ps.epilog.spi_shader_col_format |=
1926 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1927 }
1928
1929 /* If alpha-to-coverage is enabled, we have to export alpha
1930 * even if there is no color buffer.
1931 */
1932 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1933 blend->alpha_to_coverage)
1934 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1935
1936 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1937 * to the range supported by the type if a channel has less
1938 * than 16 bits and the export format is 16_ABGR.
1939 */
1940 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1941 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1942 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1943 }
1944
1945 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1946 if (!key->part.ps.epilog.last_cbuf) {
1947 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1948 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1949 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1950 }
1951
1952 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1953 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1954
1955 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1956 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1957
1958 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
1959 rs->multisample_enable;
1960
1961 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1962 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1963 (is_line && rs->line_smooth)) &&
1964 sctx->framebuffer.nr_samples <= 1;
1965 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1966
1967 if (sctx->ps_iter_samples > 1 &&
1968 sel->info.reads_samplemask) {
1969 key->part.ps.prolog.samplemask_log_ps_iter =
1970 util_logbase2(sctx->ps_iter_samples);
1971 }
1972
1973 if (rs->force_persample_interp &&
1974 rs->multisample_enable &&
1975 sctx->framebuffer.nr_samples > 1 &&
1976 sctx->ps_iter_samples > 1) {
1977 key->part.ps.prolog.force_persp_sample_interp =
1978 sel->info.uses_persp_center ||
1979 sel->info.uses_persp_centroid;
1980
1981 key->part.ps.prolog.force_linear_sample_interp =
1982 sel->info.uses_linear_center ||
1983 sel->info.uses_linear_centroid;
1984 } else if (rs->multisample_enable &&
1985 sctx->framebuffer.nr_samples > 1) {
1986 key->part.ps.prolog.bc_optimize_for_persp =
1987 sel->info.uses_persp_center &&
1988 sel->info.uses_persp_centroid;
1989 key->part.ps.prolog.bc_optimize_for_linear =
1990 sel->info.uses_linear_center &&
1991 sel->info.uses_linear_centroid;
1992 } else {
1993 /* Make sure SPI doesn't compute more than 1 pair
1994 * of (i,j), which is the optimization here. */
1995 key->part.ps.prolog.force_persp_center_interp =
1996 sel->info.uses_persp_center +
1997 sel->info.uses_persp_centroid +
1998 sel->info.uses_persp_sample > 1;
1999
2000 key->part.ps.prolog.force_linear_center_interp =
2001 sel->info.uses_linear_center +
2002 sel->info.uses_linear_centroid +
2003 sel->info.uses_linear_sample > 1;
2004
2005 if (sel->info.uses_persp_opcode_interp_sample ||
2006 sel->info.uses_linear_opcode_interp_sample)
2007 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2008 }
2009
2010 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2011
2012 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2013 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2014 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2015 struct pipe_resource *tex = cb0->texture;
2016
2017 /* 1D textures are allocated and used as 2D on GFX9. */
2018 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2019 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2020 (tex->target == PIPE_TEXTURE_1D ||
2021 tex->target == PIPE_TEXTURE_1D_ARRAY);
2022 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2023 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2024 tex->target == PIPE_TEXTURE_CUBE ||
2025 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2026 tex->target == PIPE_TEXTURE_3D;
2027 }
2028 break;
2029 }
2030 default:
2031 assert(0);
2032 }
2033
2034 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2035 memset(&key->opt, 0, sizeof(key->opt));
2036 }
2037
2038 static void si_build_shader_variant(struct si_shader *shader,
2039 int thread_index,
2040 bool low_priority)
2041 {
2042 struct si_shader_selector *sel = shader->selector;
2043 struct si_screen *sscreen = sel->screen;
2044 struct ac_llvm_compiler *compiler;
2045 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2046
2047 if (thread_index >= 0) {
2048 if (low_priority) {
2049 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2050 compiler = &sscreen->compiler_lowp[thread_index];
2051 } else {
2052 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2053 compiler = &sscreen->compiler[thread_index];
2054 }
2055 if (!debug->async)
2056 debug = NULL;
2057 } else {
2058 assert(!low_priority);
2059 compiler = shader->compiler_ctx_state.compiler;
2060 }
2061
2062 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2063 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2064 sel->type);
2065 shader->compilation_failed = true;
2066 return;
2067 }
2068
2069 if (shader->compiler_ctx_state.is_debug_context) {
2070 FILE *f = open_memstream(&shader->shader_log,
2071 &shader->shader_log_size);
2072 if (f) {
2073 si_shader_dump(sscreen, shader, NULL, f, false);
2074 fclose(f);
2075 }
2076 }
2077
2078 si_shader_init_pm4_state(sscreen, shader);
2079 }
2080
2081 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2082 {
2083 struct si_shader *shader = (struct si_shader *)job;
2084
2085 assert(thread_index >= 0);
2086
2087 si_build_shader_variant(shader, thread_index, true);
2088 }
2089
2090 static const struct si_shader_key zeroed;
2091
2092 static bool si_check_missing_main_part(struct si_screen *sscreen,
2093 struct si_shader_selector *sel,
2094 struct si_compiler_ctx_state *compiler_state,
2095 struct si_shader_key *key)
2096 {
2097 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2098
2099 if (!*mainp) {
2100 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2101
2102 if (!main_part)
2103 return false;
2104
2105 /* We can leave the fence as permanently signaled because the
2106 * main part becomes visible globally only after it has been
2107 * compiled. */
2108 util_queue_fence_init(&main_part->ready);
2109
2110 main_part->selector = sel;
2111 main_part->key.as_es = key->as_es;
2112 main_part->key.as_ls = key->as_ls;
2113 main_part->key.as_ngg = key->as_ngg;
2114 main_part->is_monolithic = false;
2115
2116 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2117 main_part, &compiler_state->debug) != 0) {
2118 FREE(main_part);
2119 return false;
2120 }
2121 *mainp = main_part;
2122 }
2123 return true;
2124 }
2125
2126 /**
2127 * Select a shader variant according to the shader key.
2128 *
2129 * \param optimized_or_none If the key describes an optimized shader variant and
2130 * the compilation isn't finished, don't select any
2131 * shader and return an error.
2132 */
2133 int si_shader_select_with_key(struct si_screen *sscreen,
2134 struct si_shader_ctx_state *state,
2135 struct si_compiler_ctx_state *compiler_state,
2136 struct si_shader_key *key,
2137 int thread_index,
2138 bool optimized_or_none)
2139 {
2140 struct si_shader_selector *sel = state->cso;
2141 struct si_shader_selector *previous_stage_sel = NULL;
2142 struct si_shader *current = state->current;
2143 struct si_shader *iter, *shader = NULL;
2144
2145 again:
2146 /* Check if we don't need to change anything.
2147 * This path is also used for most shaders that don't need multiple
2148 * variants, it will cost just a computation of the key and this
2149 * test. */
2150 if (likely(current &&
2151 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2152 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2153 if (current->is_optimized) {
2154 if (optimized_or_none)
2155 return -1;
2156
2157 memset(&key->opt, 0, sizeof(key->opt));
2158 goto current_not_ready;
2159 }
2160
2161 util_queue_fence_wait(&current->ready);
2162 }
2163
2164 return current->compilation_failed ? -1 : 0;
2165 }
2166 current_not_ready:
2167
2168 /* This must be done before the mutex is locked, because async GS
2169 * compilation calls this function too, and therefore must enter
2170 * the mutex first.
2171 *
2172 * Only wait if we are in a draw call. Don't wait if we are
2173 * in a compiler thread.
2174 */
2175 if (thread_index < 0)
2176 util_queue_fence_wait(&sel->ready);
2177
2178 mtx_lock(&sel->mutex);
2179
2180 /* Find the shader variant. */
2181 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2182 /* Don't check the "current" shader. We checked it above. */
2183 if (current != iter &&
2184 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2185 mtx_unlock(&sel->mutex);
2186
2187 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2188 /* If it's an optimized shader and its compilation has
2189 * been started but isn't done, use the unoptimized
2190 * shader so as not to cause a stall due to compilation.
2191 */
2192 if (iter->is_optimized) {
2193 if (optimized_or_none)
2194 return -1;
2195 memset(&key->opt, 0, sizeof(key->opt));
2196 goto again;
2197 }
2198
2199 util_queue_fence_wait(&iter->ready);
2200 }
2201
2202 if (iter->compilation_failed) {
2203 return -1; /* skip the draw call */
2204 }
2205
2206 state->current = iter;
2207 return 0;
2208 }
2209 }
2210
2211 /* Build a new shader. */
2212 shader = CALLOC_STRUCT(si_shader);
2213 if (!shader) {
2214 mtx_unlock(&sel->mutex);
2215 return -ENOMEM;
2216 }
2217
2218 util_queue_fence_init(&shader->ready);
2219
2220 shader->selector = sel;
2221 shader->key = *key;
2222 shader->compiler_ctx_state = *compiler_state;
2223
2224 /* If this is a merged shader, get the first shader's selector. */
2225 if (sscreen->info.chip_class >= GFX9) {
2226 if (sel->type == PIPE_SHADER_TESS_CTRL)
2227 previous_stage_sel = key->part.tcs.ls;
2228 else if (sel->type == PIPE_SHADER_GEOMETRY)
2229 previous_stage_sel = key->part.gs.es;
2230
2231 /* We need to wait for the previous shader. */
2232 if (previous_stage_sel && thread_index < 0)
2233 util_queue_fence_wait(&previous_stage_sel->ready);
2234 }
2235
2236 bool is_pure_monolithic =
2237 sscreen->use_monolithic_shaders ||
2238 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2239
2240 /* Compile the main shader part if it doesn't exist. This can happen
2241 * if the initial guess was wrong.
2242 *
2243 * The prim discard CS doesn't need the main shader part.
2244 */
2245 if (!is_pure_monolithic &&
2246 !key->opt.vs_as_prim_discard_cs) {
2247 bool ok = true;
2248
2249 /* Make sure the main shader part is present. This is needed
2250 * for shaders that can be compiled as VS, LS, or ES, and only
2251 * one of them is compiled at creation.
2252 *
2253 * It is also needed for GS, which can be compiled as non-NGG
2254 * and NGG.
2255 *
2256 * For merged shaders, check that the starting shader's main
2257 * part is present.
2258 */
2259 if (previous_stage_sel) {
2260 struct si_shader_key shader1_key = zeroed;
2261
2262 if (sel->type == PIPE_SHADER_TESS_CTRL)
2263 shader1_key.as_ls = 1;
2264 else if (sel->type == PIPE_SHADER_GEOMETRY)
2265 shader1_key.as_es = 1;
2266 else
2267 assert(0);
2268
2269 if (sel->type == PIPE_SHADER_GEOMETRY &&
2270 previous_stage_sel->type == PIPE_SHADER_TESS_EVAL)
2271 shader1_key.as_ngg = key->as_ngg;
2272
2273 mtx_lock(&previous_stage_sel->mutex);
2274 ok = si_check_missing_main_part(sscreen,
2275 previous_stage_sel,
2276 compiler_state, &shader1_key);
2277 mtx_unlock(&previous_stage_sel->mutex);
2278 }
2279
2280 if (ok) {
2281 ok = si_check_missing_main_part(sscreen, sel,
2282 compiler_state, key);
2283 }
2284
2285 if (!ok) {
2286 FREE(shader);
2287 mtx_unlock(&sel->mutex);
2288 return -ENOMEM; /* skip the draw call */
2289 }
2290 }
2291
2292 /* Keep the reference to the 1st shader of merged shaders, so that
2293 * Gallium can't destroy it before we destroy the 2nd shader.
2294 *
2295 * Set sctx = NULL, because it's unused if we're not releasing
2296 * the shader, and we don't have any sctx here.
2297 */
2298 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2299 previous_stage_sel);
2300
2301 /* Monolithic-only shaders don't make a distinction between optimized
2302 * and unoptimized. */
2303 shader->is_monolithic =
2304 is_pure_monolithic ||
2305 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2306
2307 /* The prim discard CS is always optimized. */
2308 shader->is_optimized =
2309 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2310 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2311
2312 /* If it's an optimized shader, compile it asynchronously. */
2313 if (shader->is_optimized && thread_index < 0) {
2314 /* Compile it asynchronously. */
2315 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2316 shader, &shader->ready,
2317 si_build_shader_variant_low_priority, NULL);
2318
2319 /* Add only after the ready fence was reset, to guard against a
2320 * race with si_bind_XX_shader. */
2321 if (!sel->last_variant) {
2322 sel->first_variant = shader;
2323 sel->last_variant = shader;
2324 } else {
2325 sel->last_variant->next_variant = shader;
2326 sel->last_variant = shader;
2327 }
2328
2329 /* Use the default (unoptimized) shader for now. */
2330 memset(&key->opt, 0, sizeof(key->opt));
2331 mtx_unlock(&sel->mutex);
2332
2333 if (sscreen->options.sync_compile)
2334 util_queue_fence_wait(&shader->ready);
2335
2336 if (optimized_or_none)
2337 return -1;
2338 goto again;
2339 }
2340
2341 /* Reset the fence before adding to the variant list. */
2342 util_queue_fence_reset(&shader->ready);
2343
2344 if (!sel->last_variant) {
2345 sel->first_variant = shader;
2346 sel->last_variant = shader;
2347 } else {
2348 sel->last_variant->next_variant = shader;
2349 sel->last_variant = shader;
2350 }
2351
2352 mtx_unlock(&sel->mutex);
2353
2354 assert(!shader->is_optimized);
2355 si_build_shader_variant(shader, thread_index, false);
2356
2357 util_queue_fence_signal(&shader->ready);
2358
2359 if (!shader->compilation_failed)
2360 state->current = shader;
2361
2362 return shader->compilation_failed ? -1 : 0;
2363 }
2364
2365 static int si_shader_select(struct pipe_context *ctx,
2366 struct si_shader_ctx_state *state,
2367 union si_vgt_stages_key stages_key,
2368 struct si_compiler_ctx_state *compiler_state)
2369 {
2370 struct si_context *sctx = (struct si_context *)ctx;
2371 struct si_shader_key key;
2372
2373 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2374 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2375 &key, -1, false);
2376 }
2377
2378 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2379 bool streamout,
2380 struct si_shader_key *key)
2381 {
2382 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2383
2384 switch (info->processor) {
2385 case PIPE_SHADER_VERTEX:
2386 switch (next_shader) {
2387 case PIPE_SHADER_GEOMETRY:
2388 key->as_es = 1;
2389 break;
2390 case PIPE_SHADER_TESS_CTRL:
2391 case PIPE_SHADER_TESS_EVAL:
2392 key->as_ls = 1;
2393 break;
2394 default:
2395 /* If POSITION isn't written, it can only be a HW VS
2396 * if streamout is used. If streamout isn't used,
2397 * assume that it's a HW LS. (the next shader is TCS)
2398 * This heuristic is needed for separate shader objects.
2399 */
2400 if (!info->writes_position && !streamout)
2401 key->as_ls = 1;
2402 }
2403 break;
2404
2405 case PIPE_SHADER_TESS_EVAL:
2406 if (next_shader == PIPE_SHADER_GEOMETRY ||
2407 !info->writes_position)
2408 key->as_es = 1;
2409 break;
2410 }
2411 }
2412
2413 /**
2414 * Compile the main shader part or the monolithic shader as part of
2415 * si_shader_selector initialization. Since it can be done asynchronously,
2416 * there is no way to report compile failures to applications.
2417 */
2418 static void si_init_shader_selector_async(void *job, int thread_index)
2419 {
2420 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2421 struct si_screen *sscreen = sel->screen;
2422 struct ac_llvm_compiler *compiler;
2423 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2424
2425 assert(!debug->debug_message || debug->async);
2426 assert(thread_index >= 0);
2427 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2428 compiler = &sscreen->compiler[thread_index];
2429
2430 if (sel->nir) {
2431 /* TODO: GS always sets wave size = default. Legacy GS will have
2432 * incorrect subgroup_size and ballot_bit_size. */
2433 si_lower_nir(sel, si_get_wave_size(sscreen, sel->type, true, false));
2434 }
2435
2436 /* Compile the main shader part for use with a prolog and/or epilog.
2437 * If this fails, the driver will try to compile a monolithic shader
2438 * on demand.
2439 */
2440 if (!sscreen->use_monolithic_shaders) {
2441 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2442 void *ir_binary = NULL;
2443
2444 if (!shader) {
2445 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2446 return;
2447 }
2448
2449 /* We can leave the fence signaled because use of the default
2450 * main part is guarded by the selector's ready fence. */
2451 util_queue_fence_init(&shader->ready);
2452
2453 shader->selector = sel;
2454 shader->is_monolithic = false;
2455 si_parse_next_shader_property(&sel->info,
2456 sel->so.num_outputs != 0,
2457 &shader->key);
2458
2459 if (sscreen->use_ngg &&
2460 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2461 ((sel->type == PIPE_SHADER_VERTEX &&
2462 !shader->key.as_ls && !shader->key.as_es) ||
2463 sel->type == PIPE_SHADER_TESS_EVAL ||
2464 sel->type == PIPE_SHADER_GEOMETRY))
2465 shader->key.as_ngg = 1;
2466
2467 if (sel->tokens || sel->nir)
2468 ir_binary = si_get_ir_binary(sel);
2469
2470 /* Try to load the shader from the shader cache. */
2471 mtx_lock(&sscreen->shader_cache_mutex);
2472
2473 if (ir_binary &&
2474 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2475 mtx_unlock(&sscreen->shader_cache_mutex);
2476 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2477 } else {
2478 mtx_unlock(&sscreen->shader_cache_mutex);
2479
2480 /* Compile the shader if it hasn't been loaded from the cache. */
2481 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2482 debug) != 0) {
2483 FREE(shader);
2484 FREE(ir_binary);
2485 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2486 return;
2487 }
2488
2489 if (ir_binary) {
2490 mtx_lock(&sscreen->shader_cache_mutex);
2491 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2492 FREE(ir_binary);
2493 mtx_unlock(&sscreen->shader_cache_mutex);
2494 }
2495 }
2496
2497 *si_get_main_shader_part(sel, &shader->key) = shader;
2498
2499 /* Unset "outputs_written" flags for outputs converted to
2500 * DEFAULT_VAL, so that later inter-shader optimizations don't
2501 * try to eliminate outputs that don't exist in the final
2502 * shader.
2503 *
2504 * This is only done if non-monolithic shaders are enabled.
2505 */
2506 if ((sel->type == PIPE_SHADER_VERTEX ||
2507 sel->type == PIPE_SHADER_TESS_EVAL) &&
2508 !shader->key.as_ls &&
2509 !shader->key.as_es) {
2510 unsigned i;
2511
2512 for (i = 0; i < sel->info.num_outputs; i++) {
2513 unsigned offset = shader->info.vs_output_param_offset[i];
2514
2515 if (offset <= AC_EXP_PARAM_OFFSET_31)
2516 continue;
2517
2518 unsigned name = sel->info.output_semantic_name[i];
2519 unsigned index = sel->info.output_semantic_index[i];
2520 unsigned id;
2521
2522 switch (name) {
2523 case TGSI_SEMANTIC_GENERIC:
2524 /* don't process indices the function can't handle */
2525 if (index >= SI_MAX_IO_GENERIC)
2526 break;
2527 /* fall through */
2528 default:
2529 id = si_shader_io_get_unique_index(name, index, true);
2530 sel->outputs_written_before_ps &= ~(1ull << id);
2531 break;
2532 case TGSI_SEMANTIC_POSITION: /* ignore these */
2533 case TGSI_SEMANTIC_PSIZE:
2534 case TGSI_SEMANTIC_CLIPVERTEX:
2535 case TGSI_SEMANTIC_EDGEFLAG:
2536 break;
2537 }
2538 }
2539 }
2540 }
2541
2542 /* The GS copy shader is always pre-compiled. */
2543 if (sel->type == PIPE_SHADER_GEOMETRY &&
2544 (!sscreen->use_ngg || sel->tess_turns_off_ngg)) {
2545 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2546 if (!sel->gs_copy_shader) {
2547 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2548 return;
2549 }
2550
2551 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2552 }
2553 }
2554
2555 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2556 struct util_queue_fence *ready_fence,
2557 struct si_compiler_ctx_state *compiler_ctx_state,
2558 void *job, util_queue_execute_func execute)
2559 {
2560 util_queue_fence_init(ready_fence);
2561
2562 struct util_async_debug_callback async_debug;
2563 bool debug =
2564 (sctx->debug.debug_message && !sctx->debug.async) ||
2565 sctx->is_debug ||
2566 si_can_dump_shader(sctx->screen, processor);
2567
2568 if (debug) {
2569 u_async_debug_init(&async_debug);
2570 compiler_ctx_state->debug = async_debug.base;
2571 }
2572
2573 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2574 ready_fence, execute, NULL);
2575
2576 if (debug) {
2577 util_queue_fence_wait(ready_fence);
2578 u_async_debug_drain(&async_debug, &sctx->debug);
2579 u_async_debug_cleanup(&async_debug);
2580 }
2581
2582 if (sctx->screen->options.sync_compile)
2583 util_queue_fence_wait(ready_fence);
2584 }
2585
2586 /* Return descriptor slot usage masks from the given shader info. */
2587 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2588 uint32_t *const_and_shader_buffers,
2589 uint64_t *samplers_and_images)
2590 {
2591 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2592
2593 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2594 num_constbufs = util_last_bit(info->const_buffers_declared);
2595 /* two 8-byte images share one 16-byte slot */
2596 num_images = align(util_last_bit(info->images_declared), 2);
2597 num_samplers = util_last_bit(info->samplers_declared);
2598
2599 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2600 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2601 *const_and_shader_buffers =
2602 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2603
2604 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2605 start = si_get_image_slot(num_images - 1) / 2;
2606 *samplers_and_images =
2607 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2608 }
2609
2610 static void *si_create_shader_selector(struct pipe_context *ctx,
2611 const struct pipe_shader_state *state)
2612 {
2613 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2614 struct si_context *sctx = (struct si_context*)ctx;
2615 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2616 int i;
2617
2618 if (!sel)
2619 return NULL;
2620
2621 pipe_reference_init(&sel->reference, 1);
2622 sel->screen = sscreen;
2623 sel->compiler_ctx_state.debug = sctx->debug;
2624 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2625
2626 sel->so = state->stream_output;
2627
2628 if (state->type == PIPE_SHADER_IR_TGSI &&
2629 !sscreen->options.always_nir) {
2630 sel->tokens = tgsi_dup_tokens(state->tokens);
2631 if (!sel->tokens) {
2632 FREE(sel);
2633 return NULL;
2634 }
2635
2636 tgsi_scan_shader(state->tokens, &sel->info);
2637 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2638
2639 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2640 if (sel->info.uses_persp_opcode_interp_centroid)
2641 sel->info.uses_persp_centroid = true;
2642
2643 if (sel->info.uses_linear_opcode_interp_centroid)
2644 sel->info.uses_linear_centroid = true;
2645
2646 if (sel->info.uses_persp_opcode_interp_offset ||
2647 sel->info.uses_persp_opcode_interp_sample)
2648 sel->info.uses_persp_center = true;
2649
2650 if (sel->info.uses_linear_opcode_interp_offset ||
2651 sel->info.uses_linear_opcode_interp_sample)
2652 sel->info.uses_linear_center = true;
2653 } else {
2654 if (state->type == PIPE_SHADER_IR_TGSI) {
2655 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2656 } else {
2657 assert(state->type == PIPE_SHADER_IR_NIR);
2658 sel->nir = state->ir.nir;
2659 }
2660
2661 si_nir_lower_ps_inputs(sel->nir);
2662 si_nir_opts(sel->nir);
2663 si_nir_scan_shader(sel->nir, &sel->info);
2664 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2665 }
2666
2667 sel->type = sel->info.processor;
2668 p_atomic_inc(&sscreen->num_shaders_created);
2669 si_get_active_slot_masks(&sel->info,
2670 &sel->active_const_and_shader_buffers,
2671 &sel->active_samplers_and_images);
2672
2673 /* Record which streamout buffers are enabled. */
2674 for (i = 0; i < sel->so.num_outputs; i++) {
2675 sel->enabled_streamout_buffer_mask |=
2676 (1 << sel->so.output[i].output_buffer) <<
2677 (sel->so.output[i].stream * 4);
2678 }
2679
2680 /* The prolog is a no-op if there are no inputs. */
2681 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2682 sel->info.num_inputs &&
2683 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2684
2685 sel->force_correct_derivs_after_kill =
2686 sel->type == PIPE_SHADER_FRAGMENT &&
2687 sel->info.uses_derivatives &&
2688 sel->info.uses_kill &&
2689 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2690
2691 sel->prim_discard_cs_allowed =
2692 sel->type == PIPE_SHADER_VERTEX &&
2693 !sel->info.uses_bindless_images &&
2694 !sel->info.uses_bindless_samplers &&
2695 !sel->info.writes_memory &&
2696 !sel->info.writes_viewport_index &&
2697 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2698 !sel->so.num_outputs;
2699
2700 if (sel->type == PIPE_SHADER_VERTEX &&
2701 sel->info.writes_edgeflag) {
2702 if (sscreen->info.chip_class >= GFX10)
2703 sel->ngg_writes_edgeflag = true;
2704 else
2705 sel->pos_writes_edgeflag = true;
2706 }
2707
2708 switch (sel->type) {
2709 case PIPE_SHADER_GEOMETRY:
2710 sel->gs_output_prim =
2711 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2712
2713 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2714 sel->rast_prim = sel->gs_output_prim;
2715 if (util_rast_prim_is_triangles(sel->rast_prim))
2716 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2717
2718 sel->gs_max_out_vertices =
2719 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2720 sel->gs_num_invocations =
2721 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2722 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2723 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2724 sel->gs_max_out_vertices;
2725
2726 sel->max_gs_stream = 0;
2727 for (i = 0; i < sel->so.num_outputs; i++)
2728 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2729 sel->so.output[i].stream);
2730
2731 sel->gs_input_verts_per_prim =
2732 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2733
2734 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2735 sel->tess_turns_off_ngg =
2736 (sscreen->info.family == CHIP_NAVI10 ||
2737 sscreen->info.family == CHIP_NAVI12 ||
2738 sscreen->info.family == CHIP_NAVI14) &&
2739 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2740 break;
2741
2742 case PIPE_SHADER_TESS_CTRL:
2743 /* Always reserve space for these. */
2744 sel->patch_outputs_written |=
2745 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2746 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2747 /* fall through */
2748 case PIPE_SHADER_VERTEX:
2749 case PIPE_SHADER_TESS_EVAL:
2750 for (i = 0; i < sel->info.num_outputs; i++) {
2751 unsigned name = sel->info.output_semantic_name[i];
2752 unsigned index = sel->info.output_semantic_index[i];
2753
2754 switch (name) {
2755 case TGSI_SEMANTIC_TESSINNER:
2756 case TGSI_SEMANTIC_TESSOUTER:
2757 case TGSI_SEMANTIC_PATCH:
2758 sel->patch_outputs_written |=
2759 1ull << si_shader_io_get_unique_index_patch(name, index);
2760 break;
2761
2762 case TGSI_SEMANTIC_GENERIC:
2763 /* don't process indices the function can't handle */
2764 if (index >= SI_MAX_IO_GENERIC)
2765 break;
2766 /* fall through */
2767 default:
2768 sel->outputs_written |=
2769 1ull << si_shader_io_get_unique_index(name, index, false);
2770 sel->outputs_written_before_ps |=
2771 1ull << si_shader_io_get_unique_index(name, index, true);
2772 break;
2773 case TGSI_SEMANTIC_EDGEFLAG:
2774 break;
2775 }
2776 }
2777 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2778 sel->lshs_vertex_stride = sel->esgs_itemsize;
2779
2780 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2781 * will start on a different bank. (except for the maximum 32*16).
2782 */
2783 if (sel->lshs_vertex_stride < 32*16)
2784 sel->lshs_vertex_stride += 4;
2785
2786 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2787 * conflicts, i.e. each vertex will start at a different bank.
2788 */
2789 if (sctx->chip_class >= GFX9)
2790 sel->esgs_itemsize += 4;
2791
2792 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2793
2794 /* Only for TES: */
2795 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2796 sel->rast_prim = PIPE_PRIM_POINTS;
2797 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2798 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2799 else
2800 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2801 break;
2802
2803 case PIPE_SHADER_FRAGMENT:
2804 for (i = 0; i < sel->info.num_inputs; i++) {
2805 unsigned name = sel->info.input_semantic_name[i];
2806 unsigned index = sel->info.input_semantic_index[i];
2807
2808 switch (name) {
2809 case TGSI_SEMANTIC_GENERIC:
2810 /* don't process indices the function can't handle */
2811 if (index >= SI_MAX_IO_GENERIC)
2812 break;
2813 /* fall through */
2814 default:
2815 sel->inputs_read |=
2816 1ull << si_shader_io_get_unique_index(name, index, true);
2817 break;
2818 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2819 break;
2820 }
2821 }
2822
2823 for (i = 0; i < 8; i++)
2824 if (sel->info.colors_written & (1 << i))
2825 sel->colors_written_4bit |= 0xf << (4 * i);
2826
2827 for (i = 0; i < sel->info.num_inputs; i++) {
2828 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2829 int index = sel->info.input_semantic_index[i];
2830 sel->color_attr_index[index] = i;
2831 }
2832 }
2833 break;
2834 default:;
2835 }
2836
2837 /* PA_CL_VS_OUT_CNTL */
2838 bool misc_vec_ena =
2839 sel->info.writes_psize || sel->pos_writes_edgeflag ||
2840 sel->info.writes_layer || sel->info.writes_viewport_index;
2841 sel->pa_cl_vs_out_cntl =
2842 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2843 S_02881C_USE_VTX_EDGE_FLAG(sel->pos_writes_edgeflag) |
2844 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2845 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2846 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2847 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2848 sel->clipdist_mask = sel->info.writes_clipvertex ?
2849 SIX_BITS : sel->info.clipdist_writemask;
2850 sel->culldist_mask = sel->info.culldist_writemask <<
2851 sel->info.num_written_clipdistance;
2852
2853 /* DB_SHADER_CONTROL */
2854 sel->db_shader_control =
2855 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2856 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2857 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2858 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2859
2860 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2861 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2862 sel->db_shader_control |=
2863 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2864 break;
2865 case TGSI_FS_DEPTH_LAYOUT_LESS:
2866 sel->db_shader_control |=
2867 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2868 break;
2869 }
2870
2871 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2872 *
2873 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2874 * --|-----------|------------|------------|--------------------|-------------------|-------------
2875 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2876 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2877 * 2 | false | true | n/a | LateZ | 1 | 0
2878 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2879 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2880 *
2881 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2882 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2883 *
2884 * Don't use ReZ without profiling !!!
2885 *
2886 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2887 * shaders.
2888 */
2889 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2890 /* Cases 3, 4. */
2891 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2892 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2893 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2894 } else if (sel->info.writes_memory) {
2895 /* Case 2. */
2896 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2897 S_02880C_EXEC_ON_HIER_FAIL(1);
2898 } else {
2899 /* Case 1. */
2900 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2901 }
2902
2903 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2904 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2905
2906 (void) mtx_init(&sel->mutex, mtx_plain);
2907
2908 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2909 &sel->compiler_ctx_state, sel,
2910 si_init_shader_selector_async);
2911 return sel;
2912 }
2913
2914 static void si_update_streamout_state(struct si_context *sctx)
2915 {
2916 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2917
2918 if (!shader_with_so)
2919 return;
2920
2921 sctx->streamout.enabled_stream_buffers_mask =
2922 shader_with_so->enabled_streamout_buffer_mask;
2923 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2924 }
2925
2926 static void si_update_clip_regs(struct si_context *sctx,
2927 struct si_shader_selector *old_hw_vs,
2928 struct si_shader *old_hw_vs_variant,
2929 struct si_shader_selector *next_hw_vs,
2930 struct si_shader *next_hw_vs_variant)
2931 {
2932 if (next_hw_vs &&
2933 (!old_hw_vs ||
2934 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2935 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2936 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2937 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2938 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2939 !old_hw_vs_variant ||
2940 !next_hw_vs_variant ||
2941 old_hw_vs_variant->key.opt.clip_disable !=
2942 next_hw_vs_variant->key.opt.clip_disable))
2943 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2944 }
2945
2946 static void si_update_common_shader_state(struct si_context *sctx)
2947 {
2948 sctx->uses_bindless_samplers =
2949 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2950 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2951 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2952 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2953 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2954 sctx->uses_bindless_images =
2955 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2956 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2957 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2958 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2959 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2960 sctx->do_update_shaders = true;
2961 }
2962
2963 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2964 {
2965 struct si_context *sctx = (struct si_context *)ctx;
2966 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2967 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2968 struct si_shader_selector *sel = state;
2969
2970 if (sctx->vs_shader.cso == sel)
2971 return;
2972
2973 sctx->vs_shader.cso = sel;
2974 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2975 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
2976
2977 si_update_common_shader_state(sctx);
2978 si_update_vs_viewport_state(sctx);
2979 si_set_active_descriptors_for_shader(sctx, sel);
2980 si_update_streamout_state(sctx);
2981 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2982 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2983 }
2984
2985 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2986 {
2987 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2988 (sctx->tes_shader.cso &&
2989 sctx->tes_shader.cso->info.uses_primid) ||
2990 (sctx->tcs_shader.cso &&
2991 sctx->tcs_shader.cso->info.uses_primid) ||
2992 (sctx->gs_shader.cso &&
2993 sctx->gs_shader.cso->info.uses_primid) ||
2994 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2995 sctx->ps_shader.cso->info.uses_primid);
2996 }
2997
2998 static bool si_update_ngg(struct si_context *sctx)
2999 {
3000 if (!sctx->screen->use_ngg)
3001 return false;
3002
3003 bool new_ngg = true;
3004
3005 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3006 sctx->gs_shader.cso->tess_turns_off_ngg)
3007 new_ngg = false;
3008
3009 if (new_ngg != sctx->ngg) {
3010 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3011 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3012 * pointers are set.
3013 */
3014 if ((sctx->family == CHIP_NAVI10 ||
3015 sctx->family == CHIP_NAVI12 ||
3016 sctx->family == CHIP_NAVI14) &&
3017 !new_ngg)
3018 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3019
3020 sctx->ngg = new_ngg;
3021 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3022 return true;
3023 }
3024 return false;
3025 }
3026
3027 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3028 {
3029 struct si_context *sctx = (struct si_context *)ctx;
3030 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3031 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3032 struct si_shader_selector *sel = state;
3033 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3034 bool ngg_changed;
3035
3036 if (sctx->gs_shader.cso == sel)
3037 return;
3038
3039 sctx->gs_shader.cso = sel;
3040 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3041 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3042
3043 si_update_common_shader_state(sctx);
3044 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3045
3046 ngg_changed = si_update_ngg(sctx);
3047 if (ngg_changed || enable_changed)
3048 si_shader_change_notify(sctx);
3049 if (enable_changed) {
3050 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3051 si_update_tess_uses_prim_id(sctx);
3052 }
3053 si_update_vs_viewport_state(sctx);
3054 si_set_active_descriptors_for_shader(sctx, sel);
3055 si_update_streamout_state(sctx);
3056 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3057 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3058 }
3059
3060 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3061 {
3062 struct si_context *sctx = (struct si_context *)ctx;
3063 struct si_shader_selector *sel = state;
3064 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3065
3066 if (sctx->tcs_shader.cso == sel)
3067 return;
3068
3069 sctx->tcs_shader.cso = sel;
3070 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3071 si_update_tess_uses_prim_id(sctx);
3072
3073 si_update_common_shader_state(sctx);
3074
3075 if (enable_changed)
3076 sctx->last_tcs = NULL; /* invalidate derived tess state */
3077
3078 si_set_active_descriptors_for_shader(sctx, sel);
3079 }
3080
3081 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3082 {
3083 struct si_context *sctx = (struct si_context *)ctx;
3084 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3085 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3086 struct si_shader_selector *sel = state;
3087 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3088
3089 if (sctx->tes_shader.cso == sel)
3090 return;
3091
3092 sctx->tes_shader.cso = sel;
3093 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3094 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3095 si_update_tess_uses_prim_id(sctx);
3096
3097 si_update_common_shader_state(sctx);
3098 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3099
3100 if (enable_changed) {
3101 si_update_ngg(sctx);
3102 si_shader_change_notify(sctx);
3103 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3104 }
3105 si_update_vs_viewport_state(sctx);
3106 si_set_active_descriptors_for_shader(sctx, sel);
3107 si_update_streamout_state(sctx);
3108 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3109 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3110 }
3111
3112 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3113 {
3114 struct si_context *sctx = (struct si_context *)ctx;
3115 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3116 struct si_shader_selector *sel = state;
3117
3118 /* skip if supplied shader is one already in use */
3119 if (old_sel == sel)
3120 return;
3121
3122 sctx->ps_shader.cso = sel;
3123 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3124
3125 si_update_common_shader_state(sctx);
3126 if (sel) {
3127 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3128 si_update_tess_uses_prim_id(sctx);
3129
3130 if (!old_sel ||
3131 old_sel->info.colors_written != sel->info.colors_written)
3132 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3133
3134 if (sctx->screen->has_out_of_order_rast &&
3135 (!old_sel ||
3136 old_sel->info.writes_memory != sel->info.writes_memory ||
3137 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3138 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3139 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3140 }
3141 si_set_active_descriptors_for_shader(sctx, sel);
3142 si_update_ps_colorbuf0_slot(sctx);
3143 }
3144
3145 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3146 {
3147 if (shader->is_optimized) {
3148 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3149 &shader->ready);
3150 }
3151
3152 util_queue_fence_destroy(&shader->ready);
3153
3154 if (shader->pm4) {
3155 /* If destroyed shaders were not unbound, the next compiled
3156 * shader variant could get the same pointer address and so
3157 * binding it to the same shader stage would be considered
3158 * a no-op, causing random behavior.
3159 */
3160 switch (shader->selector->type) {
3161 case PIPE_SHADER_VERTEX:
3162 if (shader->key.as_ls) {
3163 assert(sctx->chip_class <= GFX8);
3164 si_pm4_delete_state(sctx, ls, shader->pm4);
3165 } else if (shader->key.as_es) {
3166 assert(sctx->chip_class <= GFX8);
3167 si_pm4_delete_state(sctx, es, shader->pm4);
3168 } else if (shader->key.as_ngg) {
3169 si_pm4_delete_state(sctx, gs, shader->pm4);
3170 } else {
3171 si_pm4_delete_state(sctx, vs, shader->pm4);
3172 }
3173 break;
3174 case PIPE_SHADER_TESS_CTRL:
3175 si_pm4_delete_state(sctx, hs, shader->pm4);
3176 break;
3177 case PIPE_SHADER_TESS_EVAL:
3178 if (shader->key.as_es) {
3179 assert(sctx->chip_class <= GFX8);
3180 si_pm4_delete_state(sctx, es, shader->pm4);
3181 } else if (shader->key.as_ngg) {
3182 si_pm4_delete_state(sctx, gs, shader->pm4);
3183 } else {
3184 si_pm4_delete_state(sctx, vs, shader->pm4);
3185 }
3186 break;
3187 case PIPE_SHADER_GEOMETRY:
3188 if (shader->is_gs_copy_shader)
3189 si_pm4_delete_state(sctx, vs, shader->pm4);
3190 else
3191 si_pm4_delete_state(sctx, gs, shader->pm4);
3192 break;
3193 case PIPE_SHADER_FRAGMENT:
3194 si_pm4_delete_state(sctx, ps, shader->pm4);
3195 break;
3196 default:;
3197 }
3198 }
3199
3200 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3201 si_shader_destroy(shader);
3202 free(shader);
3203 }
3204
3205 void si_destroy_shader_selector(struct si_context *sctx,
3206 struct si_shader_selector *sel)
3207 {
3208 struct si_shader *p = sel->first_variant, *c;
3209 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3210 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3211 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3212 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3213 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3214 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3215 };
3216
3217 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3218
3219 if (current_shader[sel->type]->cso == sel) {
3220 current_shader[sel->type]->cso = NULL;
3221 current_shader[sel->type]->current = NULL;
3222 }
3223
3224 while (p) {
3225 c = p->next_variant;
3226 si_delete_shader(sctx, p);
3227 p = c;
3228 }
3229
3230 if (sel->main_shader_part)
3231 si_delete_shader(sctx, sel->main_shader_part);
3232 if (sel->main_shader_part_ls)
3233 si_delete_shader(sctx, sel->main_shader_part_ls);
3234 if (sel->main_shader_part_es)
3235 si_delete_shader(sctx, sel->main_shader_part_es);
3236 if (sel->main_shader_part_ngg)
3237 si_delete_shader(sctx, sel->main_shader_part_ngg);
3238 if (sel->gs_copy_shader)
3239 si_delete_shader(sctx, sel->gs_copy_shader);
3240
3241 util_queue_fence_destroy(&sel->ready);
3242 mtx_destroy(&sel->mutex);
3243 free(sel->tokens);
3244 ralloc_free(sel->nir);
3245 free(sel);
3246 }
3247
3248 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3249 {
3250 struct si_context *sctx = (struct si_context *)ctx;
3251 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3252
3253 si_shader_selector_reference(sctx, &sel, NULL);
3254 }
3255
3256 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3257 struct si_shader *vs, unsigned name,
3258 unsigned index, unsigned interpolate)
3259 {
3260 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3261 unsigned j, offset, ps_input_cntl = 0;
3262
3263 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3264 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3265 name == TGSI_SEMANTIC_PRIMID)
3266 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3267
3268 if (name == TGSI_SEMANTIC_PCOORD ||
3269 (name == TGSI_SEMANTIC_TEXCOORD &&
3270 sctx->sprite_coord_enable & (1 << index))) {
3271 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3272 }
3273
3274 for (j = 0; j < vsinfo->num_outputs; j++) {
3275 if (name == vsinfo->output_semantic_name[j] &&
3276 index == vsinfo->output_semantic_index[j]) {
3277 offset = vs->info.vs_output_param_offset[j];
3278
3279 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3280 /* The input is loaded from parameter memory. */
3281 ps_input_cntl |= S_028644_OFFSET(offset);
3282 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3283 if (offset == AC_EXP_PARAM_UNDEFINED) {
3284 /* This can happen with depth-only rendering. */
3285 offset = 0;
3286 } else {
3287 /* The input is a DEFAULT_VAL constant. */
3288 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3289 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3290 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3291 }
3292
3293 ps_input_cntl = S_028644_OFFSET(0x20) |
3294 S_028644_DEFAULT_VAL(offset);
3295 }
3296 break;
3297 }
3298 }
3299
3300 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3301 /* PrimID is written after the last output when HW VS is used. */
3302 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3303 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3304 /* No corresponding output found, load defaults into input.
3305 * Don't set any other bits.
3306 * (FLAT_SHADE=1 completely changes behavior) */
3307 ps_input_cntl = S_028644_OFFSET(0x20);
3308 /* D3D 9 behaviour. GL is undefined */
3309 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3310 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3311 }
3312 return ps_input_cntl;
3313 }
3314
3315 static void si_emit_spi_map(struct si_context *sctx)
3316 {
3317 struct si_shader *ps = sctx->ps_shader.current;
3318 struct si_shader *vs = si_get_vs_state(sctx);
3319 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3320 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3321 unsigned spi_ps_input_cntl[32];
3322
3323 if (!ps || !ps->selector->info.num_inputs)
3324 return;
3325
3326 num_interp = si_get_ps_num_interp(ps);
3327 assert(num_interp > 0);
3328
3329 for (i = 0; i < psinfo->num_inputs; i++) {
3330 unsigned name = psinfo->input_semantic_name[i];
3331 unsigned index = psinfo->input_semantic_index[i];
3332 unsigned interpolate = psinfo->input_interpolate[i];
3333
3334 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3335 index, interpolate);
3336
3337 if (name == TGSI_SEMANTIC_COLOR) {
3338 assert(index < ARRAY_SIZE(bcol_interp));
3339 bcol_interp[index] = interpolate;
3340 }
3341 }
3342
3343 if (ps->key.part.ps.prolog.color_two_side) {
3344 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3345
3346 for (i = 0; i < 2; i++) {
3347 if (!(psinfo->colors_read & (0xf << (i * 4))))
3348 continue;
3349
3350 spi_ps_input_cntl[num_written++] =
3351 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3352
3353 }
3354 }
3355 assert(num_interp == num_written);
3356
3357 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3358 /* Dota 2: Only ~16% of SPI map updates set different values. */
3359 /* Talos: Only ~9% of SPI map updates set different values. */
3360 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3361 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3362 spi_ps_input_cntl,
3363 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3364
3365 if (initial_cdw != sctx->gfx_cs->current.cdw)
3366 sctx->context_roll = true;
3367 }
3368
3369 /**
3370 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3371 */
3372 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3373 {
3374 if (sctx->init_config_has_vgt_flush)
3375 return;
3376
3377 /* Done by Vulkan before VGT_FLUSH. */
3378 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3379 si_pm4_cmd_add(sctx->init_config,
3380 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3381 si_pm4_cmd_end(sctx->init_config, false);
3382
3383 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3384 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3385 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3386 si_pm4_cmd_end(sctx->init_config, false);
3387 sctx->init_config_has_vgt_flush = true;
3388 }
3389
3390 /* Initialize state related to ESGS / GSVS ring buffers */
3391 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3392 {
3393 struct si_shader_selector *es =
3394 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3395 struct si_shader_selector *gs = sctx->gs_shader.cso;
3396 struct si_pm4_state *pm4;
3397
3398 /* Chip constants. */
3399 unsigned num_se = sctx->screen->info.max_se;
3400 unsigned wave_size = 64;
3401 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3402 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3403 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3404 */
3405 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3406 unsigned alignment = 256 * num_se;
3407 /* The maximum size is 63.999 MB per SE. */
3408 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3409
3410 /* Calculate the minimum size. */
3411 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3412 wave_size, alignment);
3413
3414 /* These are recommended sizes, not minimum sizes. */
3415 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3416 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3417 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3418 gs->max_gsvs_emit_size;
3419
3420 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3421 esgs_ring_size = align(esgs_ring_size, alignment);
3422 gsvs_ring_size = align(gsvs_ring_size, alignment);
3423
3424 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3425 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3426
3427 /* Some rings don't have to be allocated if shaders don't use them.
3428 * (e.g. no varyings between ES and GS or GS and VS)
3429 *
3430 * GFX9 doesn't have the ESGS ring.
3431 */
3432 bool update_esgs = sctx->chip_class <= GFX8 &&
3433 esgs_ring_size &&
3434 (!sctx->esgs_ring ||
3435 sctx->esgs_ring->width0 < esgs_ring_size);
3436 bool update_gsvs = gsvs_ring_size &&
3437 (!sctx->gsvs_ring ||
3438 sctx->gsvs_ring->width0 < gsvs_ring_size);
3439
3440 if (!update_esgs && !update_gsvs)
3441 return true;
3442
3443 if (update_esgs) {
3444 pipe_resource_reference(&sctx->esgs_ring, NULL);
3445 sctx->esgs_ring =
3446 pipe_aligned_buffer_create(sctx->b.screen,
3447 SI_RESOURCE_FLAG_UNMAPPABLE,
3448 PIPE_USAGE_DEFAULT,
3449 esgs_ring_size, alignment);
3450 if (!sctx->esgs_ring)
3451 return false;
3452 }
3453
3454 if (update_gsvs) {
3455 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3456 sctx->gsvs_ring =
3457 pipe_aligned_buffer_create(sctx->b.screen,
3458 SI_RESOURCE_FLAG_UNMAPPABLE,
3459 PIPE_USAGE_DEFAULT,
3460 gsvs_ring_size, alignment);
3461 if (!sctx->gsvs_ring)
3462 return false;
3463 }
3464
3465 /* Create the "init_config_gs_rings" state. */
3466 pm4 = CALLOC_STRUCT(si_pm4_state);
3467 if (!pm4)
3468 return false;
3469
3470 if (sctx->chip_class >= GFX7) {
3471 if (sctx->esgs_ring) {
3472 assert(sctx->chip_class <= GFX8);
3473 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3474 sctx->esgs_ring->width0 / 256);
3475 }
3476 if (sctx->gsvs_ring)
3477 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3478 sctx->gsvs_ring->width0 / 256);
3479 } else {
3480 if (sctx->esgs_ring)
3481 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3482 sctx->esgs_ring->width0 / 256);
3483 if (sctx->gsvs_ring)
3484 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3485 sctx->gsvs_ring->width0 / 256);
3486 }
3487
3488 /* Set the state. */
3489 if (sctx->init_config_gs_rings)
3490 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3491 sctx->init_config_gs_rings = pm4;
3492
3493 if (!sctx->init_config_has_vgt_flush) {
3494 si_init_config_add_vgt_flush(sctx);
3495 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3496 }
3497
3498 /* Flush the context to re-emit both init_config states. */
3499 sctx->initial_gfx_cs_size = 0; /* force flush */
3500 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3501
3502 /* Set ring bindings. */
3503 if (sctx->esgs_ring) {
3504 assert(sctx->chip_class <= GFX8);
3505 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3506 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3507 true, true, 4, 64, 0);
3508 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3509 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3510 false, false, 0, 0, 0);
3511 }
3512 if (sctx->gsvs_ring) {
3513 si_set_ring_buffer(sctx, SI_RING_GSVS,
3514 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3515 false, false, 0, 0, 0);
3516 }
3517
3518 return true;
3519 }
3520
3521 static void si_shader_lock(struct si_shader *shader)
3522 {
3523 mtx_lock(&shader->selector->mutex);
3524 if (shader->previous_stage_sel) {
3525 assert(shader->previous_stage_sel != shader->selector);
3526 mtx_lock(&shader->previous_stage_sel->mutex);
3527 }
3528 }
3529
3530 static void si_shader_unlock(struct si_shader *shader)
3531 {
3532 if (shader->previous_stage_sel)
3533 mtx_unlock(&shader->previous_stage_sel->mutex);
3534 mtx_unlock(&shader->selector->mutex);
3535 }
3536
3537 /**
3538 * @returns 1 if \p sel has been updated to use a new scratch buffer
3539 * 0 if not
3540 * < 0 if there was a failure
3541 */
3542 static int si_update_scratch_buffer(struct si_context *sctx,
3543 struct si_shader *shader)
3544 {
3545 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3546
3547 if (!shader)
3548 return 0;
3549
3550 /* This shader doesn't need a scratch buffer */
3551 if (shader->config.scratch_bytes_per_wave == 0)
3552 return 0;
3553
3554 /* Prevent race conditions when updating:
3555 * - si_shader::scratch_bo
3556 * - si_shader::binary::code
3557 * - si_shader::previous_stage::binary::code.
3558 */
3559 si_shader_lock(shader);
3560
3561 /* This shader is already configured to use the current
3562 * scratch buffer. */
3563 if (shader->scratch_bo == sctx->scratch_buffer) {
3564 si_shader_unlock(shader);
3565 return 0;
3566 }
3567
3568 assert(sctx->scratch_buffer);
3569
3570 /* Replace the shader bo with a new bo that has the relocs applied. */
3571 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3572 si_shader_unlock(shader);
3573 return -1;
3574 }
3575
3576 /* Update the shader state to use the new shader bo. */
3577 si_shader_init_pm4_state(sctx->screen, shader);
3578
3579 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3580
3581 si_shader_unlock(shader);
3582 return 1;
3583 }
3584
3585 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3586 {
3587 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3588 }
3589
3590 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3591 {
3592 return shader ? shader->config.scratch_bytes_per_wave : 0;
3593 }
3594
3595 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3596 {
3597 if (!sctx->tes_shader.cso)
3598 return NULL; /* tessellation disabled */
3599
3600 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3601 sctx->fixed_func_tcs_shader.current;
3602 }
3603
3604 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3605 {
3606 unsigned bytes = 0;
3607
3608 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3609 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3610 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3611 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3612
3613 if (sctx->tes_shader.cso) {
3614 struct si_shader *tcs = si_get_tcs_current(sctx);
3615
3616 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3617 }
3618 return bytes;
3619 }
3620
3621 static bool si_update_scratch_relocs(struct si_context *sctx)
3622 {
3623 struct si_shader *tcs = si_get_tcs_current(sctx);
3624 int r;
3625
3626 /* Update the shaders, so that they are using the latest scratch.
3627 * The scratch buffer may have been changed since these shaders were
3628 * last used, so we still need to try to update them, even if they
3629 * require scratch buffers smaller than the current size.
3630 */
3631 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3632 if (r < 0)
3633 return false;
3634 if (r == 1)
3635 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3636
3637 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3638 if (r < 0)
3639 return false;
3640 if (r == 1)
3641 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3642
3643 r = si_update_scratch_buffer(sctx, tcs);
3644 if (r < 0)
3645 return false;
3646 if (r == 1)
3647 si_pm4_bind_state(sctx, hs, tcs->pm4);
3648
3649 /* VS can be bound as LS, ES, or VS. */
3650 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3651 if (r < 0)
3652 return false;
3653 if (r == 1) {
3654 if (sctx->vs_shader.current->key.as_ls)
3655 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3656 else if (sctx->vs_shader.current->key.as_es)
3657 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3658 else if (sctx->vs_shader.current->key.as_ngg)
3659 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3660 else
3661 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3662 }
3663
3664 /* TES can be bound as ES or VS. */
3665 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3666 if (r < 0)
3667 return false;
3668 if (r == 1) {
3669 if (sctx->tes_shader.current->key.as_es)
3670 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3671 else if (sctx->tes_shader.current->key.as_ngg)
3672 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3673 else
3674 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3675 }
3676
3677 return true;
3678 }
3679
3680 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3681 {
3682 unsigned current_scratch_buffer_size =
3683 si_get_current_scratch_buffer_size(sctx);
3684 unsigned scratch_bytes_per_wave =
3685 si_get_max_scratch_bytes_per_wave(sctx);
3686 unsigned scratch_needed_size = scratch_bytes_per_wave *
3687 sctx->scratch_waves;
3688 unsigned spi_tmpring_size;
3689
3690 if (scratch_needed_size > 0) {
3691 if (scratch_needed_size > current_scratch_buffer_size) {
3692 /* Create a bigger scratch buffer */
3693 si_resource_reference(&sctx->scratch_buffer, NULL);
3694
3695 sctx->scratch_buffer =
3696 si_aligned_buffer_create(&sctx->screen->b,
3697 SI_RESOURCE_FLAG_UNMAPPABLE,
3698 PIPE_USAGE_DEFAULT,
3699 scratch_needed_size, 256);
3700 if (!sctx->scratch_buffer)
3701 return false;
3702
3703 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3704 si_context_add_resource_size(sctx,
3705 &sctx->scratch_buffer->b.b);
3706 }
3707
3708 if (!si_update_scratch_relocs(sctx))
3709 return false;
3710 }
3711
3712 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3713 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3714 "scratch size should already be aligned correctly.");
3715
3716 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3717 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3718 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3719 sctx->spi_tmpring_size = spi_tmpring_size;
3720 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3721 }
3722 return true;
3723 }
3724
3725 static void si_init_tess_factor_ring(struct si_context *sctx)
3726 {
3727 assert(!sctx->tess_rings);
3728
3729 /* The address must be aligned to 2^19, because the shader only
3730 * receives the high 13 bits.
3731 */
3732 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3733 SI_RESOURCE_FLAG_32BIT,
3734 PIPE_USAGE_DEFAULT,
3735 sctx->screen->tess_offchip_ring_size +
3736 sctx->screen->tess_factor_ring_size,
3737 1 << 19);
3738 if (!sctx->tess_rings)
3739 return;
3740
3741 si_init_config_add_vgt_flush(sctx);
3742
3743 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3744 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3745
3746 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3747 sctx->screen->tess_offchip_ring_size;
3748
3749 /* Append these registers to the init config state. */
3750 if (sctx->chip_class >= GFX7) {
3751 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3752 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3753 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3754 factor_va >> 8);
3755 if (sctx->chip_class >= GFX10)
3756 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3757 S_030984_BASE_HI(factor_va >> 40));
3758 else if (sctx->chip_class == GFX9)
3759 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3760 S_030944_BASE_HI(factor_va >> 40));
3761 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3762 sctx->screen->vgt_hs_offchip_param);
3763 } else {
3764 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3765 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3766 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3767 factor_va >> 8);
3768 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3769 sctx->screen->vgt_hs_offchip_param);
3770 }
3771
3772 /* Flush the context to re-emit the init_config state.
3773 * This is done only once in a lifetime of a context.
3774 */
3775 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3776 sctx->initial_gfx_cs_size = 0; /* force flush */
3777 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3778 }
3779
3780 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3781 union si_vgt_stages_key key)
3782 {
3783 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3784 uint32_t stages = 0;
3785
3786 if (key.u.tess) {
3787 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3788 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3789
3790 if (key.u.gs)
3791 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3792 S_028B54_GS_EN(1);
3793 else if (key.u.ngg)
3794 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3795 else
3796 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3797 } else if (key.u.gs) {
3798 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3799 S_028B54_GS_EN(1);
3800 } else if (key.u.ngg) {
3801 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3802 }
3803
3804 if (key.u.ngg) {
3805 stages |= S_028B54_PRIMGEN_EN(1);
3806 if (key.u.streamout)
3807 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3808 } else if (key.u.gs)
3809 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3810
3811 if (screen->info.chip_class >= GFX9)
3812 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3813
3814 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3815 stages |= S_028B54_HS_W32_EN(1) |
3816 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3817 S_028B54_VS_W32_EN(1);
3818 }
3819
3820 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3821 return pm4;
3822 }
3823
3824 static void si_update_vgt_shader_config(struct si_context *sctx,
3825 union si_vgt_stages_key key)
3826 {
3827 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3828
3829 if (unlikely(!*pm4))
3830 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3831 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3832 }
3833
3834 bool si_update_shaders(struct si_context *sctx)
3835 {
3836 struct pipe_context *ctx = (struct pipe_context*)sctx;
3837 struct si_compiler_ctx_state compiler_state;
3838 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3839 struct si_shader *old_vs = si_get_vs_state(sctx);
3840 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3841 struct si_shader *old_ps = sctx->ps_shader.current;
3842 union si_vgt_stages_key key;
3843 unsigned old_spi_shader_col_format =
3844 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3845 int r;
3846
3847 compiler_state.compiler = &sctx->compiler;
3848 compiler_state.debug = sctx->debug;
3849 compiler_state.is_debug_context = sctx->is_debug;
3850
3851 key.index = 0;
3852
3853 if (sctx->tes_shader.cso)
3854 key.u.tess = 1;
3855 if (sctx->gs_shader.cso)
3856 key.u.gs = 1;
3857
3858 if (sctx->ngg) {
3859 key.u.ngg = 1;
3860 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3861 }
3862
3863 /* Update TCS and TES. */
3864 if (sctx->tes_shader.cso) {
3865 if (!sctx->tess_rings) {
3866 si_init_tess_factor_ring(sctx);
3867 if (!sctx->tess_rings)
3868 return false;
3869 }
3870
3871 if (sctx->tcs_shader.cso) {
3872 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3873 &compiler_state);
3874 if (r)
3875 return false;
3876 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3877 } else {
3878 if (!sctx->fixed_func_tcs_shader.cso) {
3879 sctx->fixed_func_tcs_shader.cso =
3880 si_create_fixed_func_tcs(sctx);
3881 if (!sctx->fixed_func_tcs_shader.cso)
3882 return false;
3883 }
3884
3885 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3886 key, &compiler_state);
3887 if (r)
3888 return false;
3889 si_pm4_bind_state(sctx, hs,
3890 sctx->fixed_func_tcs_shader.current->pm4);
3891 }
3892
3893 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3894 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3895 if (r)
3896 return false;
3897
3898 if (sctx->gs_shader.cso) {
3899 /* TES as ES */
3900 assert(sctx->chip_class <= GFX8);
3901 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3902 } else if (key.u.ngg) {
3903 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3904 } else {
3905 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3906 }
3907 }
3908 } else {
3909 if (sctx->chip_class <= GFX8)
3910 si_pm4_bind_state(sctx, ls, NULL);
3911 si_pm4_bind_state(sctx, hs, NULL);
3912 }
3913
3914 /* Update GS. */
3915 if (sctx->gs_shader.cso) {
3916 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3917 if (r)
3918 return false;
3919 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3920 if (!key.u.ngg) {
3921 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3922
3923 if (!si_update_gs_ring_buffers(sctx))
3924 return false;
3925 } else {
3926 si_pm4_bind_state(sctx, vs, NULL);
3927 }
3928 } else {
3929 if (!key.u.ngg) {
3930 si_pm4_bind_state(sctx, gs, NULL);
3931 if (sctx->chip_class <= GFX8)
3932 si_pm4_bind_state(sctx, es, NULL);
3933 }
3934 }
3935
3936 /* Update VS. */
3937 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3938 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3939 if (r)
3940 return false;
3941
3942 if (!key.u.tess && !key.u.gs) {
3943 if (key.u.ngg) {
3944 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3945 si_pm4_bind_state(sctx, vs, NULL);
3946 } else {
3947 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3948 }
3949 } else if (sctx->tes_shader.cso) {
3950 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3951 } else {
3952 assert(sctx->gs_shader.cso);
3953 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3954 }
3955 }
3956
3957 si_update_vgt_shader_config(sctx, key);
3958
3959 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3960 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3961
3962 if (sctx->ps_shader.cso) {
3963 unsigned db_shader_control;
3964
3965 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3966 if (r)
3967 return false;
3968 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3969
3970 db_shader_control =
3971 sctx->ps_shader.cso->db_shader_control |
3972 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3973
3974 if (si_pm4_state_changed(sctx, ps) ||
3975 si_pm4_state_changed(sctx, vs) ||
3976 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3977 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3978 sctx->flatshade != rs->flatshade) {
3979 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3980 sctx->flatshade = rs->flatshade;
3981 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3982 }
3983
3984 if (sctx->screen->rbplus_allowed &&
3985 si_pm4_state_changed(sctx, ps) &&
3986 (!old_ps ||
3987 old_spi_shader_col_format !=
3988 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3989 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3990
3991 if (sctx->ps_db_shader_control != db_shader_control) {
3992 sctx->ps_db_shader_control = db_shader_control;
3993 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3994 if (sctx->screen->dpbb_allowed)
3995 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3996 }
3997
3998 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3999 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4000 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4001
4002 if (sctx->chip_class == GFX6)
4003 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4004
4005 if (sctx->framebuffer.nr_samples <= 1)
4006 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4007 }
4008 }
4009
4010 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4011 si_pm4_state_enabled_and_changed(sctx, hs) ||
4012 si_pm4_state_enabled_and_changed(sctx, es) ||
4013 si_pm4_state_enabled_and_changed(sctx, gs) ||
4014 si_pm4_state_enabled_and_changed(sctx, vs) ||
4015 si_pm4_state_enabled_and_changed(sctx, ps)) {
4016 if (!si_update_spi_tmpring_size(sctx))
4017 return false;
4018 }
4019
4020 if (sctx->chip_class >= GFX7) {
4021 if (si_pm4_state_enabled_and_changed(sctx, ls))
4022 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4023 else if (!sctx->queued.named.ls)
4024 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4025
4026 if (si_pm4_state_enabled_and_changed(sctx, hs))
4027 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4028 else if (!sctx->queued.named.hs)
4029 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4030
4031 if (si_pm4_state_enabled_and_changed(sctx, es))
4032 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4033 else if (!sctx->queued.named.es)
4034 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4035
4036 if (si_pm4_state_enabled_and_changed(sctx, gs))
4037 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4038 else if (!sctx->queued.named.gs)
4039 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4040
4041 if (si_pm4_state_enabled_and_changed(sctx, vs))
4042 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4043 else if (!sctx->queued.named.vs)
4044 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4045
4046 if (si_pm4_state_enabled_and_changed(sctx, ps))
4047 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4048 else if (!sctx->queued.named.ps)
4049 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4050 }
4051
4052 sctx->do_update_shaders = false;
4053 return true;
4054 }
4055
4056 static void si_emit_scratch_state(struct si_context *sctx)
4057 {
4058 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4059
4060 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4061 sctx->spi_tmpring_size);
4062
4063 if (sctx->scratch_buffer) {
4064 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4065 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4066 RADEON_PRIO_SCRATCH_BUFFER);
4067 }
4068 }
4069
4070 void si_init_shader_functions(struct si_context *sctx)
4071 {
4072 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4073 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4074
4075 sctx->b.create_vs_state = si_create_shader_selector;
4076 sctx->b.create_tcs_state = si_create_shader_selector;
4077 sctx->b.create_tes_state = si_create_shader_selector;
4078 sctx->b.create_gs_state = si_create_shader_selector;
4079 sctx->b.create_fs_state = si_create_shader_selector;
4080
4081 sctx->b.bind_vs_state = si_bind_vs_shader;
4082 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4083 sctx->b.bind_tes_state = si_bind_tes_shader;
4084 sctx->b.bind_gs_state = si_bind_gs_shader;
4085 sctx->b.bind_fs_state = si_bind_ps_shader;
4086
4087 sctx->b.delete_vs_state = si_delete_shader_selector;
4088 sctx->b.delete_tcs_state = si_delete_shader_selector;
4089 sctx->b.delete_tes_state = si_delete_shader_selector;
4090 sctx->b.delete_gs_state = si_delete_shader_selector;
4091 sctx->b.delete_fs_state = si_delete_shader_selector;
4092 }