2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
44 * Return the IR key for the shader cache.
46 void si_get_ir_cache_key(struct si_shader_selector
*sel
, bool ngg
, bool es
,
47 unsigned char ir_sha1_cache_key
[20])
49 struct blob blob
= {};
53 if (sel
->nir_binary
) {
54 ir_binary
= sel
->nir_binary
;
55 ir_size
= sel
->nir_size
;
60 nir_serialize(&blob
, sel
->nir
, true);
61 ir_binary
= blob
.data
;
65 /* These settings affect the compilation, but they are not derived
66 * from the input shader IR.
68 unsigned shader_variant_flags
= 0;
71 shader_variant_flags
|= 1 << 0;
73 shader_variant_flags
|= 1 << 1;
74 if (si_get_wave_size(sel
->screen
, sel
->type
, ngg
, es
) == 32)
75 shader_variant_flags
|= 1 << 2;
76 if (sel
->force_correct_derivs_after_kill
)
77 shader_variant_flags
|= 1 << 3;
80 _mesa_sha1_init(&ctx
);
81 _mesa_sha1_update(&ctx
, &shader_variant_flags
, 4);
82 _mesa_sha1_update(&ctx
, ir_binary
, ir_size
);
83 if (sel
->type
== PIPE_SHADER_VERTEX
||
84 sel
->type
== PIPE_SHADER_TESS_EVAL
||
85 sel
->type
== PIPE_SHADER_GEOMETRY
)
86 _mesa_sha1_update(&ctx
, &sel
->so
, sizeof(sel
->so
));
87 _mesa_sha1_final(&ctx
, ir_sha1_cache_key
);
89 if (ir_binary
== blob
.data
)
93 /** Copy "data" to "ptr" and return the next dword following copied data. */
94 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
96 /* data may be NULL if size == 0 */
98 memcpy(ptr
, data
, size
);
99 ptr
+= DIV_ROUND_UP(size
, 4);
103 /** Read data from "ptr". Return the next dword following the data. */
104 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
106 memcpy(data
, ptr
, size
);
107 ptr
+= DIV_ROUND_UP(size
, 4);
112 * Write the size as uint followed by the data. Return the next dword
113 * following the copied data.
115 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
118 return write_data(ptr
, data
, size
);
122 * Read the size as uint followed by the data. Return both via parameters.
123 * Return the next dword following the data.
125 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
128 assert(*data
== NULL
);
131 *data
= malloc(*size
);
132 return read_data(ptr
, *data
, *size
);
136 * Return the shader binary in a buffer. The first 4 bytes contain its size
139 static void *si_get_shader_binary(struct si_shader
*shader
)
141 /* There is always a size of data followed by the data itself. */
142 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
143 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
145 /* Refuse to allocate overly large buffers and guard against integer
147 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
148 llvm_ir_size
> UINT_MAX
/ 4)
153 4 + /* CRC32 of the data below */
154 align(sizeof(shader
->config
), 4) +
155 align(sizeof(shader
->info
), 4) +
156 4 + align(shader
->binary
.elf_size
, 4) +
157 4 + align(llvm_ir_size
, 4);
158 void *buffer
= CALLOC(1, size
);
159 uint32_t *ptr
= (uint32_t*)buffer
;
165 ptr
++; /* CRC32 is calculated at the end. */
167 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
168 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
169 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
170 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
171 assert((char *)ptr
- (char *)buffer
== size
);
174 ptr
= (uint32_t*)buffer
;
176 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
181 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
183 uint32_t *ptr
= (uint32_t*)binary
;
184 uint32_t size
= *ptr
++;
185 uint32_t crc32
= *ptr
++;
189 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
190 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
194 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
195 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
196 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
198 shader
->binary
.elf_size
= elf_size
;
199 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
205 * Insert a shader into the cache. It's assumed the shader is not in the cache.
206 * Use si_shader_cache_load_shader before calling this.
208 void si_shader_cache_insert_shader(struct si_screen
*sscreen
,
209 unsigned char ir_sha1_cache_key
[20],
210 struct si_shader
*shader
,
211 bool insert_into_disk_cache
)
214 struct hash_entry
*entry
;
215 uint8_t key
[CACHE_KEY_SIZE
];
217 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
219 return; /* already added */
221 hw_binary
= si_get_shader_binary(shader
);
225 if (_mesa_hash_table_insert(sscreen
->shader_cache
,
226 mem_dup(ir_sha1_cache_key
, 20),
227 hw_binary
) == NULL
) {
232 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
233 disk_cache_compute_key(sscreen
->disk_shader_cache
,
234 ir_sha1_cache_key
, 20, key
);
235 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
236 *((uint32_t *) hw_binary
), NULL
);
240 bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
241 unsigned char ir_sha1_cache_key
[20],
242 struct si_shader
*shader
)
244 struct hash_entry
*entry
=
245 _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
247 if (sscreen
->disk_shader_cache
) {
248 unsigned char sha1
[CACHE_KEY_SIZE
];
250 disk_cache_compute_key(sscreen
->disk_shader_cache
,
251 ir_sha1_cache_key
, 20, sha1
);
255 disk_cache_get(sscreen
->disk_shader_cache
,
260 if (binary_size
< sizeof(uint32_t) ||
261 *((uint32_t*)buffer
) != binary_size
) {
262 /* Something has gone wrong discard the item
263 * from the cache and rebuild/link from
266 assert(!"Invalid radeonsi shader disk cache "
269 disk_cache_remove(sscreen
->disk_shader_cache
,
276 if (!si_load_shader_binary(shader
, buffer
)) {
282 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
,
288 if (!si_load_shader_binary(shader
, entry
->data
))
291 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
295 static uint32_t si_shader_cache_key_hash(const void *key
)
297 /* Take the first dword of SHA1. */
298 return *(uint32_t*)key
;
301 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
304 return memcmp(a
, b
, 20) == 0;
307 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
309 FREE((void*)entry
->key
);
313 bool si_init_shader_cache(struct si_screen
*sscreen
)
315 (void) simple_mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
316 sscreen
->shader_cache
=
317 _mesa_hash_table_create(NULL
,
318 si_shader_cache_key_hash
,
319 si_shader_cache_key_equals
);
321 return sscreen
->shader_cache
!= NULL
;
324 void si_destroy_shader_cache(struct si_screen
*sscreen
)
326 if (sscreen
->shader_cache
)
327 _mesa_hash_table_destroy(sscreen
->shader_cache
,
328 si_destroy_shader_cache_entry
);
329 simple_mtx_destroy(&sscreen
->shader_cache_mutex
);
334 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
335 const struct si_shader_selector
*tes
,
336 struct si_pm4_state
*pm4
)
338 const struct si_shader_info
*info
= &tes
->info
;
339 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
340 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
341 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
342 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
343 unsigned type
, partitioning
, topology
, distribution_mode
;
345 switch (tes_prim_mode
) {
346 case PIPE_PRIM_LINES
:
347 type
= V_028B6C_TESS_ISOLINE
;
349 case PIPE_PRIM_TRIANGLES
:
350 type
= V_028B6C_TESS_TRIANGLE
;
352 case PIPE_PRIM_QUADS
:
353 type
= V_028B6C_TESS_QUAD
;
360 switch (tes_spacing
) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
362 partitioning
= V_028B6C_PART_FRAC_ODD
;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
365 partitioning
= V_028B6C_PART_FRAC_EVEN
;
367 case PIPE_TESS_SPACING_EQUAL
:
368 partitioning
= V_028B6C_PART_INTEGER
;
376 topology
= V_028B6C_OUTPUT_POINT
;
377 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
378 topology
= V_028B6C_OUTPUT_LINE
;
379 else if (tes_vertex_order_cw
)
380 /* for some reason, this must be the other way around */
381 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
383 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
385 if (sscreen
->info
.has_distributed_tess
) {
386 if (sscreen
->info
.family
== CHIP_FIJI
||
387 sscreen
->info
.family
>= CHIP_POLARIS10
)
388 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
390 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
392 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
395 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
396 S_028B6C_PARTITIONING(partitioning
) |
397 S_028B6C_TOPOLOGY(topology
) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
404 * Possible VGT configurations and which state should set the register:
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
415 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
416 struct si_shader_selector
*sel
,
417 struct si_shader
*shader
,
418 struct si_pm4_state
*pm4
)
420 unsigned type
= sel
->type
;
422 if (sscreen
->info
.family
< CHIP_POLARIS10
||
423 sscreen
->info
.chip_class
>= GFX10
)
426 /* VS as VS, or VS as ES: */
427 if ((type
== PIPE_SHADER_VERTEX
&&
429 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
430 /* TES as VS, or TES as ES: */
431 type
== PIPE_SHADER_TESS_EVAL
) {
432 unsigned vtx_reuse_depth
= 30;
434 if (type
== PIPE_SHADER_TESS_EVAL
&&
435 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
437 vtx_reuse_depth
= 14;
440 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
444 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
447 si_pm4_clear_state(shader
->pm4
);
449 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
452 shader
->pm4
->shader
= shader
;
455 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
460 static unsigned si_get_num_vs_user_sgprs(struct si_shader
*shader
,
461 unsigned num_always_on_user_sgprs
)
463 struct si_shader_selector
*vs
= shader
->previous_stage_sel
?
464 shader
->previous_stage_sel
: shader
->selector
;
465 unsigned num_vbos_in_user_sgprs
= vs
->num_vbos_in_user_sgprs
;
467 /* 1 SGPR is reserved for the vertex buffer pointer. */
468 assert(num_always_on_user_sgprs
<= SI_SGPR_VS_VB_DESCRIPTOR_FIRST
- 1);
470 if (num_vbos_in_user_sgprs
)
471 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST
+ num_vbos_in_user_sgprs
* 4;
473 /* Add the pointer to VBO descriptors. */
474 return num_always_on_user_sgprs
+ 1;
477 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
478 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen
*sscreen
,
479 struct si_shader
*shader
, bool legacy_vs_prim_id
)
481 assert(shader
->selector
->type
== PIPE_SHADER_VERTEX
||
482 (shader
->previous_stage_sel
&&
483 shader
->previous_stage_sel
->type
== PIPE_SHADER_VERTEX
));
485 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
486 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
487 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
488 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
490 bool is_ls
= shader
->selector
->type
== PIPE_SHADER_TESS_CTRL
|| shader
->key
.as_ls
;
492 if (sscreen
->info
.chip_class
>= GFX10
&& shader
->info
.uses_instanceid
)
494 else if ((is_ls
&& shader
->info
.uses_instanceid
) || legacy_vs_prim_id
)
496 else if (is_ls
|| shader
->info
.uses_instanceid
)
502 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
504 struct si_pm4_state
*pm4
;
507 assert(sscreen
->info
.chip_class
<= GFX8
);
509 pm4
= si_get_shader_pm4_state(shader
);
513 va
= shader
->bo
->gpu_address
;
514 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
516 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
517 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
519 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
520 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
521 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false)) |
522 S_00B528_DX10_CLAMP(1) |
523 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
524 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
)) |
525 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
528 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
530 struct si_pm4_state
*pm4
;
533 pm4
= si_get_shader_pm4_state(shader
);
537 va
= shader
->bo
->gpu_address
;
538 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
540 if (sscreen
->info
.chip_class
>= GFX9
) {
541 if (sscreen
->info
.chip_class
>= GFX10
) {
542 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
543 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
545 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
546 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
549 unsigned num_user_sgprs
=
550 si_get_num_vs_user_sgprs(shader
, GFX9_TCS_NUM_USER_SGPR
);
552 shader
->config
.rsrc2
=
553 S_00B42C_USER_SGPR(num_user_sgprs
) |
554 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
556 if (sscreen
->info
.chip_class
>= GFX10
)
557 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
559 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
561 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
562 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
564 shader
->config
.rsrc2
=
565 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
566 S_00B42C_OC_LDS_EN(1) |
567 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
570 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
571 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) /
572 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
573 (sscreen
->info
.chip_class
<= GFX9
?
574 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) : 0) |
575 S_00B428_DX10_CLAMP(1) |
576 S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
577 S_00B428_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
578 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
579 S_00B428_LS_VGPR_COMP_CNT(sscreen
->info
.chip_class
>= GFX9
?
580 si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false) : 0));
582 if (sscreen
->info
.chip_class
<= GFX8
) {
583 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
584 shader
->config
.rsrc2
);
588 static void si_emit_shader_es(struct si_context
*sctx
)
590 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
591 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
596 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
597 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
598 shader
->selector
->esgs_itemsize
/ 4);
600 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
601 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
602 SI_TRACKED_VGT_TF_PARAM
,
603 shader
->vgt_tf_param
);
605 if (shader
->vgt_vertex_reuse_block_cntl
)
606 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
607 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
608 shader
->vgt_vertex_reuse_block_cntl
);
610 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
611 sctx
->context_roll
= true;
614 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
616 struct si_pm4_state
*pm4
;
617 unsigned num_user_sgprs
;
618 unsigned vgpr_comp_cnt
;
622 assert(sscreen
->info
.chip_class
<= GFX8
);
624 pm4
= si_get_shader_pm4_state(shader
);
628 pm4
->atom
.emit
= si_emit_shader_es
;
629 va
= shader
->bo
->gpu_address
;
630 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
632 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
633 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
634 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
);
635 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
636 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
637 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
639 unreachable("invalid shader selector type");
641 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
643 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
644 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
645 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
646 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
647 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
648 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
649 S_00B328_DX10_CLAMP(1) |
650 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
651 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
652 S_00B32C_USER_SGPR(num_user_sgprs
) |
653 S_00B32C_OC_LDS_EN(oc_lds_en
) |
654 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
656 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
657 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
659 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
662 void gfx9_get_gs_info(struct si_shader_selector
*es
,
663 struct si_shader_selector
*gs
,
664 struct gfx9_gs_info
*out
)
666 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
667 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
668 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
669 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
671 /* All these are in dwords: */
672 /* We can't allow using the whole LDS, because GS waves compete with
673 * other shader stages for LDS space. */
674 const unsigned max_lds_size
= 8 * 1024;
675 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
676 unsigned esgs_lds_size
;
678 /* All these are per subgroup: */
679 const unsigned max_out_prims
= 32 * 1024;
680 const unsigned max_es_verts
= 255;
681 const unsigned ideal_gs_prims
= 64;
682 unsigned max_gs_prims
, gs_prims
;
683 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
685 if (uses_adjacency
|| gs_num_invocations
> 1)
686 max_gs_prims
= 127 / gs_num_invocations
;
690 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
691 * Make sure we don't go over the maximum value.
693 if (gs
->gs_max_out_vertices
> 0) {
694 max_gs_prims
= MIN2(max_gs_prims
,
696 (gs
->gs_max_out_vertices
* gs_num_invocations
));
698 assert(max_gs_prims
> 0);
700 /* If the primitive has adjacency, halve the number of vertices
701 * that will be reused in multiple primitives.
703 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
705 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
706 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
708 /* Compute ESGS LDS size based on the worst case number of ES vertices
709 * needed to create the target number of GS prims per subgroup.
711 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
713 /* If total LDS usage is too big, refactor partitions based on ratio
714 * of ESGS item sizes.
716 if (esgs_lds_size
> max_lds_size
) {
717 /* Our target GS Prims Per Subgroup was too large. Calculate
718 * the maximum number of GS Prims Per Subgroup that will fit
719 * into LDS, capped by the maximum that the hardware can support.
721 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
723 assert(gs_prims
> 0);
724 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
727 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
728 assert(esgs_lds_size
<= max_lds_size
);
731 /* Now calculate remaining ESGS information. */
733 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
735 es_verts
= max_es_verts
;
737 /* Vertices for adjacency primitives are not always reused, so restore
738 * it for ES_VERTS_PER_SUBGRP.
740 min_es_verts
= gs
->gs_input_verts_per_prim
;
742 /* For normal primitives, the VGT only checks if they are past the ES
743 * verts per subgroup after allocating a full GS primitive and if they
744 * are, kick off a new subgroup. But if those additional ES verts are
745 * unique (e.g. not reused) we need to make sure there is enough LDS
746 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
748 es_verts
-= min_es_verts
- 1;
750 out
->es_verts_per_subgroup
= es_verts
;
751 out
->gs_prims_per_subgroup
= gs_prims
;
752 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
753 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
754 gs
->gs_max_out_vertices
;
755 out
->esgs_ring_size
= 4 * esgs_lds_size
;
757 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
760 static void si_emit_shader_gs(struct si_context
*sctx
)
762 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
763 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
768 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
769 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
770 radeon_opt_set_context_reg3(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
771 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
772 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
773 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
774 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
776 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
777 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
778 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
779 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
781 /* R_028B38_VGT_GS_MAX_VERT_OUT */
782 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
783 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
784 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
786 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
787 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
788 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
789 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
790 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
791 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
792 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
793 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
795 /* R_028B90_VGT_GS_INSTANCE_CNT */
796 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
797 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
798 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
800 if (sctx
->chip_class
>= GFX9
) {
801 /* R_028A44_VGT_GS_ONCHIP_CNTL */
802 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
803 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
804 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
805 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
806 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
807 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
808 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
809 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
810 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
811 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
812 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
814 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
815 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
816 SI_TRACKED_VGT_TF_PARAM
,
817 shader
->vgt_tf_param
);
818 if (shader
->vgt_vertex_reuse_block_cntl
)
819 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
820 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
821 shader
->vgt_vertex_reuse_block_cntl
);
824 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
825 sctx
->context_roll
= true;
828 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
830 struct si_shader_selector
*sel
= shader
->selector
;
831 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
832 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
833 struct si_pm4_state
*pm4
;
835 unsigned max_stream
= sel
->max_gs_stream
;
838 pm4
= si_get_shader_pm4_state(shader
);
842 pm4
->atom
.emit
= si_emit_shader_gs
;
844 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
845 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
848 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
849 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
852 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
853 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
856 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
857 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
859 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
860 assert(offset
< (1 << 15));
862 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
864 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
865 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
866 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
867 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
869 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
870 S_028B90_ENABLE(gs_num_invocations
> 0);
872 va
= shader
->bo
->gpu_address
;
873 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
875 if (sscreen
->info
.chip_class
>= GFX9
) {
876 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
877 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
878 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
880 if (es_type
== PIPE_SHADER_VERTEX
) {
881 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
882 } else if (es_type
== PIPE_SHADER_TESS_EVAL
)
883 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
885 unreachable("invalid shader selector type");
887 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
888 * VGPR[0:4] are always loaded.
890 if (sel
->info
.uses_invocationid
)
891 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
892 else if (sel
->info
.uses_primid
)
893 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
894 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
895 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
897 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
899 unsigned num_user_sgprs
;
900 if (es_type
== PIPE_SHADER_VERTEX
)
901 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, GFX9_VSGS_NUM_USER_SGPR
);
903 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
905 if (sscreen
->info
.chip_class
>= GFX10
) {
906 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
907 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
909 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
910 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
914 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
915 S_00B228_DX10_CLAMP(1) |
916 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
917 S_00B228_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
918 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
919 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
921 S_00B22C_USER_SGPR(num_user_sgprs
) |
922 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
923 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
924 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
925 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
927 if (sscreen
->info
.chip_class
>= GFX10
) {
928 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
930 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
931 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
934 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
935 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
937 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
938 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
939 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
940 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
941 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
942 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
943 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
944 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
946 if (es_type
== PIPE_SHADER_TESS_EVAL
)
947 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
949 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
952 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
953 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
955 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
956 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
957 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
958 S_00B228_DX10_CLAMP(1) |
959 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
960 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
961 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
962 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
966 static void gfx10_emit_ge_pc_alloc(struct si_context
*sctx
, unsigned value
)
968 enum si_tracked_reg reg
= SI_TRACKED_GE_PC_ALLOC
;
970 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x1) != 0x1 ||
971 sctx
->tracked_regs
.reg_value
[reg
] != value
) {
972 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
974 if (sctx
->family
== CHIP_NAVI10
||
975 sctx
->family
== CHIP_NAVI12
||
976 sctx
->family
== CHIP_NAVI14
) {
977 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
978 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
979 radeon_emit(cs
, EVENT_TYPE(V_028A90_SQ_NON_EVENT
) | EVENT_INDEX(0));
982 radeon_set_uconfig_reg(cs
, R_030980_GE_PC_ALLOC
, value
);
984 sctx
->tracked_regs
.reg_saved
|= 0x1ull
<< reg
;
985 sctx
->tracked_regs
.reg_value
[reg
] = value
;
989 /* Common tail code for NGG primitive shaders. */
990 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
,
991 struct si_shader
*shader
,
992 unsigned initial_cdw
)
994 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
995 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
996 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
997 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
998 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
999 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
1000 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1001 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1002 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
1003 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
1004 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
1005 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
1006 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
1007 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
1008 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
1009 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
1010 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
1011 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
1012 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1013 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1014 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
1015 radeon_opt_set_context_reg2(sctx
, R_028708_SPI_SHADER_IDX_FORMAT
,
1016 SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
1017 shader
->ctx_reg
.ngg
.spi_shader_idx_format
,
1018 shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
1019 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1020 SI_TRACKED_PA_CL_VTE_CNTL
,
1021 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
1022 radeon_opt_set_context_reg(sctx
, R_028838_PA_CL_NGG_CNTL
,
1023 SI_TRACKED_PA_CL_NGG_CNTL
,
1024 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
);
1026 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
1027 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
,
1028 shader
->pa_cl_vs_out_cntl
,
1029 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
1031 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1032 sctx
->context_roll
= true;
1034 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1035 gfx10_emit_ge_pc_alloc(sctx
, shader
->ctx_reg
.ngg
.ge_pc_alloc
);
1038 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
1040 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1041 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1046 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1049 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
1051 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1052 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1057 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1058 SI_TRACKED_VGT_TF_PARAM
,
1059 shader
->vgt_tf_param
);
1061 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1064 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
1066 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1067 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1072 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1073 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1074 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1076 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1079 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1081 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1082 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1087 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1088 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1089 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1090 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1091 SI_TRACKED_VGT_TF_PARAM
,
1092 shader
->vgt_tf_param
);
1094 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1097 unsigned si_get_input_prim(const struct si_shader_selector
*gs
)
1099 if (gs
->type
== PIPE_SHADER_GEOMETRY
)
1100 return gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
1102 if (gs
->type
== PIPE_SHADER_TESS_EVAL
) {
1103 if (gs
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1104 return PIPE_PRIM_POINTS
;
1105 if (gs
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
1106 return PIPE_PRIM_LINES
;
1107 return PIPE_PRIM_TRIANGLES
;
1110 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1111 return PIPE_PRIM_TRIANGLES
; /* worst case for all callers */
1114 static unsigned si_get_vs_out_cntl(const struct si_shader_selector
*sel
, bool ngg
)
1117 sel
->info
.writes_psize
|| (sel
->info
.writes_edgeflag
&& !ngg
) ||
1118 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
1119 return S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
1120 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
&& !ngg
) |
1121 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
1122 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
1123 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
1124 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
1128 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1131 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1133 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1134 const struct si_shader_info
*gs_info
= &gs_sel
->info
;
1135 enum pipe_shader_type gs_type
= shader
->selector
->type
;
1136 const struct si_shader_selector
*es_sel
=
1137 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1138 const struct si_shader_info
*es_info
= &es_sel
->info
;
1139 enum pipe_shader_type es_type
= es_sel
->type
;
1140 unsigned num_user_sgprs
;
1141 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1143 unsigned window_space
=
1144 gs_info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1145 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1146 unsigned gs_num_invocations
= MAX2(gs_sel
->gs_num_invocations
, 1);
1147 unsigned input_prim
= si_get_input_prim(gs_sel
);
1148 bool break_wave_at_eoi
= false;
1149 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1153 if (es_type
== PIPE_SHADER_TESS_EVAL
) {
1154 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1155 : gfx10_emit_shader_ngg_tess_nogs
;
1157 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1158 : gfx10_emit_shader_ngg_notess_nogs
;
1161 va
= shader
->bo
->gpu_address
;
1162 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1164 if (es_type
== PIPE_SHADER_VERTEX
) {
1165 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
1167 if (es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1168 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1169 es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1171 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, GFX9_VSGS_NUM_USER_SGPR
);
1174 assert(es_type
== PIPE_SHADER_TESS_EVAL
);
1175 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1176 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1178 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1179 break_wave_at_eoi
= true;
1182 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1183 * VGPR[0:4] are always loaded.
1185 * Vertex shaders always need to load VGPR3, because they need to
1186 * pass edge flags for decomposed primitives (such as quads) to the PA
1187 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1189 if (gs_info
->uses_invocationid
||
1190 (gs_type
== PIPE_SHADER_VERTEX
&& !gfx10_is_ngg_passthrough(shader
)))
1191 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID, edge flags. */
1192 else if ((gs_type
== PIPE_SHADER_GEOMETRY
&& gs_info
->uses_primid
) ||
1193 (gs_type
== PIPE_SHADER_VERTEX
&& shader
->key
.mono
.u
.vs_export_prim_id
))
1194 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1195 else if (input_prim
>= PIPE_PRIM_TRIANGLES
&& !gfx10_is_ngg_passthrough(shader
))
1196 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1198 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1200 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1201 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1202 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1203 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) /
1204 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1205 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
1206 S_00B228_DX10_CLAMP(1) |
1207 S_00B228_MEM_ORDERED(1) |
1208 S_00B228_WGP_MODE(1) |
1209 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1210 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1211 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1212 S_00B22C_USER_SGPR(num_user_sgprs
) |
1213 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1214 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1215 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
1216 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1218 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1219 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1220 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
1221 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1223 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1224 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1225 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1226 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1227 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1228 V_02870C_SPI_SHADER_4COMP
:
1229 V_02870C_SPI_SHADER_NONE
) |
1230 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1231 V_02870C_SPI_SHADER_4COMP
:
1232 V_02870C_SPI_SHADER_NONE
) |
1233 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1234 V_02870C_SPI_SHADER_4COMP
:
1235 V_02870C_SPI_SHADER_NONE
);
1237 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1238 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1239 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader
->key
.mono
.u
.vs_export_prim_id
||
1240 gs_sel
->info
.writes_primid
);
1242 if (gs_type
== PIPE_SHADER_GEOMETRY
) {
1243 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1244 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->gs_max_out_vertices
;
1246 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1249 if (es_type
== PIPE_SHADER_TESS_EVAL
)
1250 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1252 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1253 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1254 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1255 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1256 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1257 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1258 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
=
1259 S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1260 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1261 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1262 S_028B90_CNT(gs_num_invocations
) |
1263 S_028B90_ENABLE(gs_num_invocations
> 1) |
1264 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1265 shader
->ngg
.max_vert_out_per_gs_instance
);
1267 /* Always output hw-generated edge flags and pass them via the prim
1268 * export to prevent drawing lines on internal edges of decomposed
1269 * primitives (such as quads) with polygon mode = lines. Only VS needs
1272 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
=
1273 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type
== PIPE_SHADER_VERTEX
);
1274 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(gs_sel
, true);
1276 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1277 float oversub_pc_factor
= 0.25;
1279 if (shader
->key
.opt
.ngg_culling
) {
1280 /* Be more aggressive with NGG culling. */
1281 if (shader
->info
.nr_param_exports
> 4)
1282 oversub_pc_factor
= 1;
1283 else if (shader
->info
.nr_param_exports
> 2)
1284 oversub_pc_factor
= 0.75;
1286 oversub_pc_factor
= 0.5;
1289 unsigned oversub_pc_lines
= sscreen
->info
.pc_lines
* oversub_pc_factor
;
1290 shader
->ctx_reg
.ngg
.ge_pc_alloc
= S_030980_OVERSUB_EN(1) |
1291 S_030980_NUM_PC_LINES(oversub_pc_lines
- 1);
1294 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1295 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1296 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1298 /* Bug workaround for a possible hang with non-tessellation cases.
1299 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1301 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1303 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1304 sscreen
->info
.family
== CHIP_NAVI12
||
1305 sscreen
->info
.family
== CHIP_NAVI14
) &&
1306 (es_type
== PIPE_SHADER_VERTEX
|| gs_type
== PIPE_SHADER_VERTEX
) && /* = no tess */
1307 shader
->ngg
.hw_max_esverts
!= 256) {
1308 shader
->ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
1310 if (shader
->ngg
.hw_max_esverts
> 5) {
1312 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
- 5);
1317 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1318 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1320 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1321 S_028818_VTX_W0_FMT(1) |
1322 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1323 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1324 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1328 static void si_emit_shader_vs(struct si_context
*sctx
)
1330 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1331 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1336 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
1337 SI_TRACKED_VGT_GS_MODE
,
1338 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1339 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1340 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1341 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1343 if (sctx
->chip_class
<= GFX8
) {
1344 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
1345 SI_TRACKED_VGT_REUSE_OFF
,
1346 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1349 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1350 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1351 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1353 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1354 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1355 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1357 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1358 SI_TRACKED_PA_CL_VTE_CNTL
,
1359 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1361 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1362 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1363 SI_TRACKED_VGT_TF_PARAM
,
1364 shader
->vgt_tf_param
);
1366 if (shader
->vgt_vertex_reuse_block_cntl
)
1367 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1368 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1369 shader
->vgt_vertex_reuse_block_cntl
);
1371 /* Required programming for tessellation. (legacy pipeline only) */
1372 if (sctx
->chip_class
== GFX10
&&
1373 shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1374 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
1375 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
1376 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1377 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1378 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1381 if (sctx
->chip_class
>= GFX10
) {
1382 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
1383 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
,
1384 shader
->pa_cl_vs_out_cntl
,
1385 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
1388 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1389 sctx
->context_roll
= true;
1391 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1392 if (sctx
->chip_class
>= GFX10
)
1393 gfx10_emit_ge_pc_alloc(sctx
, shader
->ctx_reg
.vs
.ge_pc_alloc
);
1397 * Compute the state for \p shader, which will run as a vertex shader on the
1400 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1401 * is the copy shader.
1403 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1404 struct si_shader_selector
*gs
)
1406 const struct si_shader_info
*info
= &shader
->selector
->info
;
1407 struct si_pm4_state
*pm4
;
1408 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1410 unsigned nparams
, oc_lds_en
;
1411 unsigned window_space
=
1412 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1413 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1415 pm4
= si_get_shader_pm4_state(shader
);
1419 pm4
->atom
.emit
= si_emit_shader_vs
;
1421 /* We always write VGT_GS_MODE in the VS state, because every switch
1422 * between different shader pipelines involving a different GS or no
1423 * GS at all involves a switch of the VS (different GS use different
1424 * copy shaders). On the other hand, when the API switches from a GS to
1425 * no GS and then back to the same GS used originally, the GS state is
1429 unsigned mode
= V_028A40_GS_OFF
;
1431 /* PrimID needs GS scenario A. */
1433 mode
= V_028A40_GS_SCENARIO_A
;
1435 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1436 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1438 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1439 sscreen
->info
.chip_class
);
1440 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1443 if (sscreen
->info
.chip_class
<= GFX8
) {
1444 /* Reuse needs to be set off if we write oViewport. */
1445 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1446 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1449 va
= shader
->bo
->gpu_address
;
1450 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1453 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1454 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1455 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1456 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, enable_prim_id
);
1458 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1459 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1460 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1462 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
);
1464 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1465 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1466 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1468 unreachable("invalid shader selector type");
1470 /* VS is required to export at least one param. */
1471 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1472 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1474 if (sscreen
->info
.chip_class
>= GFX10
) {
1475 shader
->ctx_reg
.vs
.spi_vs_out_config
|=
1476 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1479 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1480 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1481 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1482 V_02870C_SPI_SHADER_4COMP
:
1483 V_02870C_SPI_SHADER_NONE
) |
1484 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1485 V_02870C_SPI_SHADER_4COMP
:
1486 V_02870C_SPI_SHADER_NONE
) |
1487 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1488 V_02870C_SPI_SHADER_4COMP
:
1489 V_02870C_SPI_SHADER_NONE
);
1490 shader
->ctx_reg
.vs
.ge_pc_alloc
= S_030980_OVERSUB_EN(1) |
1491 S_030980_NUM_PC_LINES(sscreen
->info
.pc_lines
/ 4 - 1);
1492 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(shader
->selector
, false);
1494 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1496 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1497 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1499 uint32_t rsrc1
= S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) /
1500 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1501 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1502 S_00B128_DX10_CLAMP(1) |
1503 S_00B128_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1504 S_00B128_FLOAT_MODE(shader
->config
.float_mode
);
1505 uint32_t rsrc2
= S_00B12C_USER_SGPR(num_user_sgprs
) |
1506 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1507 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
1509 if (sscreen
->info
.chip_class
>= GFX10
)
1510 rsrc2
|= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
1511 else if (sscreen
->info
.chip_class
== GFX9
)
1512 rsrc2
|= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
1514 if (sscreen
->info
.chip_class
<= GFX9
)
1515 rsrc1
|= S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1517 if (!sscreen
->use_ngg_streamout
) {
1518 rsrc2
|= S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1519 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1520 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1521 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1522 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
);
1525 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
, rsrc1
);
1526 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
, rsrc2
);
1529 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1530 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1532 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1533 S_028818_VTX_W0_FMT(1) |
1534 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1535 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1536 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1538 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1539 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1541 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1544 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1546 struct si_shader_info
*info
= &ps
->selector
->info
;
1547 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1548 !!(info
->colors_read
& 0xf0);
1549 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1550 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1552 assert(num_interp
<= 32);
1553 return MIN2(num_interp
, 32);
1556 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1558 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1559 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1561 /* If the i-th target format is set, all previous target formats must
1562 * be non-zero to avoid hangs.
1564 for (i
= 0; i
< num_targets
; i
++)
1565 if (!(value
& (0xf << (i
* 4))))
1566 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1571 static void si_emit_shader_ps(struct si_context
*sctx
)
1573 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1574 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1579 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1580 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1581 SI_TRACKED_SPI_PS_INPUT_ENA
,
1582 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1583 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1585 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1586 SI_TRACKED_SPI_BARYC_CNTL
,
1587 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1588 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1589 SI_TRACKED_SPI_PS_IN_CONTROL
,
1590 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1592 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1593 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1594 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1595 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1596 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1598 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1599 SI_TRACKED_CB_SHADER_MASK
,
1600 shader
->ctx_reg
.ps
.cb_shader_mask
);
1602 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1603 sctx
->context_roll
= true;
1606 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1608 struct si_shader_info
*info
= &shader
->selector
->info
;
1609 struct si_pm4_state
*pm4
;
1610 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1611 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1613 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1615 /* we need to enable at least one of them, otherwise we hang the GPU */
1616 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1617 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1618 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1619 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1620 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1621 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1622 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1623 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1624 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1625 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1626 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1627 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1628 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1629 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1631 /* Validate interpolation optimization flags (read as implications). */
1632 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1633 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1634 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1635 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1636 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1637 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1638 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1639 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1640 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1641 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1642 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1643 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1644 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1645 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1646 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1647 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1648 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1649 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1651 /* Validate cases when the optimizations are off (read as implications). */
1652 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1653 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1654 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1655 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1656 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1657 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1659 pm4
= si_get_shader_pm4_state(shader
);
1663 pm4
->atom
.emit
= si_emit_shader_ps
;
1665 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1667 * 0 -> Position = pixel center
1668 * 1 -> Position = pixel centroid
1669 * 2 -> Position = at sample position
1671 * From GLSL 4.5 specification, section 7.1:
1672 * "The variable gl_FragCoord is available as an input variable from
1673 * within fragment shaders and it holds the window relative coordinates
1674 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1675 * value can be for any location within the pixel, or one of the
1676 * fragment samples. The use of centroid does not further restrict
1677 * this value to be inside the current primitive."
1679 * Meaning that centroid has no effect and we can return anything within
1680 * the pixel. Thus, return the value at sample position, because that's
1681 * the most accurate one shaders can get.
1683 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1685 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1686 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1687 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1689 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1690 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1692 /* Ensure that some export memory is always allocated, for two reasons:
1694 * 1) Correctness: The hardware ignores the EXEC mask if no export
1695 * memory is allocated, so KILL and alpha test do not work correctly
1697 * 2) Performance: Every shader needs at least a NULL export, even when
1698 * it writes no color/depth output. The NULL export instruction
1699 * stalls without this setting.
1701 * Don't add this to CB_SHADER_MASK.
1703 * GFX10 supports pixel shaders without exports by setting both
1704 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1705 * instructions if any are present.
1707 if ((sscreen
->info
.chip_class
<= GFX9
||
1709 shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
) &&
1710 !spi_shader_col_format
&&
1711 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1712 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1714 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1715 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1717 /* Set interpolation controls. */
1718 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
)) |
1719 S_0286D8_PS_W32_EN(sscreen
->ps_wave_size
== 32);
1721 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1722 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1723 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1724 ac_get_spi_shader_z_format(info
->writes_z
,
1725 info
->writes_stencil
,
1726 info
->writes_samplemask
);
1727 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1728 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1730 va
= shader
->bo
->gpu_address
;
1731 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1732 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1733 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1736 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) /
1737 (sscreen
->ps_wave_size
== 32 ? 8 : 4)) |
1738 S_00B028_DX10_CLAMP(1) |
1739 S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1740 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1742 if (sscreen
->info
.chip_class
< GFX10
) {
1743 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1746 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1747 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1748 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1749 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1750 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1753 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1754 struct si_shader
*shader
)
1756 switch (shader
->selector
->type
) {
1757 case PIPE_SHADER_VERTEX
:
1758 if (shader
->key
.as_ls
)
1759 si_shader_ls(sscreen
, shader
);
1760 else if (shader
->key
.as_es
)
1761 si_shader_es(sscreen
, shader
);
1762 else if (shader
->key
.as_ngg
)
1763 gfx10_shader_ngg(sscreen
, shader
);
1765 si_shader_vs(sscreen
, shader
, NULL
);
1767 case PIPE_SHADER_TESS_CTRL
:
1768 si_shader_hs(sscreen
, shader
);
1770 case PIPE_SHADER_TESS_EVAL
:
1771 if (shader
->key
.as_es
)
1772 si_shader_es(sscreen
, shader
);
1773 else if (shader
->key
.as_ngg
)
1774 gfx10_shader_ngg(sscreen
, shader
);
1776 si_shader_vs(sscreen
, shader
, NULL
);
1778 case PIPE_SHADER_GEOMETRY
:
1779 if (shader
->key
.as_ngg
)
1780 gfx10_shader_ngg(sscreen
, shader
);
1782 si_shader_gs(sscreen
, shader
);
1784 case PIPE_SHADER_FRAGMENT
:
1785 si_shader_ps(sscreen
, shader
);
1792 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1794 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1795 return sctx
->queued
.named
.dsa
->alpha_func
;
1798 void si_shader_selector_key_vs(struct si_context
*sctx
,
1799 struct si_shader_selector
*vs
,
1800 struct si_shader_key
*key
,
1801 struct si_vs_prolog_bits
*prolog_key
)
1803 if (!sctx
->vertex_elements
||
1804 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
])
1807 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1809 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1810 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1811 prolog_key
->unpack_instance_id_from_vertex_id
=
1812 sctx
->prim_discard_cs_instancing
;
1814 /* Prefer a monolithic shader to allow scheduling divisions around
1816 if (prolog_key
->instance_divisor_is_fetched
)
1817 key
->opt
.prefer_mono
= 1;
1819 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1820 unsigned count_mask
= (1 << count
) - 1;
1821 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1822 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1824 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1825 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1827 unsigned i
= u_bit_scan(&mask
);
1828 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1829 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1830 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1831 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1832 if (vb
->buffer_offset
& align_mask
||
1833 vb
->stride
& align_mask
) {
1841 unsigned i
= u_bit_scan(&fix
);
1842 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1844 key
->mono
.vs_fetch_opencode
= opencode
;
1847 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1848 struct si_shader_selector
*vs
,
1849 struct si_shader_key
*key
)
1851 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1853 key
->opt
.clip_disable
=
1854 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1855 (vs
->info
.clipdist_writemask
||
1856 vs
->info
.writes_clipvertex
) &&
1857 !vs
->info
.culldist_writemask
;
1859 /* Find out if PS is disabled. */
1860 bool ps_disabled
= true;
1862 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1863 ps
->info
.writes_z
||
1864 ps
->info
.writes_stencil
||
1865 ps
->info
.writes_samplemask
||
1866 sctx
->queued
.named
.blend
->alpha_to_coverage
||
1867 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1868 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1870 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1873 !ps
->info
.writes_memory
);
1876 /* Find out which VS outputs aren't used by the PS. */
1877 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1878 uint64_t inputs_read
= 0;
1880 /* Ignore outputs that are not passed from VS to PS. */
1881 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1882 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1883 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1886 inputs_read
= ps
->inputs_read
;
1889 uint64_t linked
= outputs_written
& inputs_read
;
1891 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1892 key
->opt
.ngg_culling
= sctx
->ngg_culling
;
1895 /* Compute the key for the hw shader variant */
1896 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1897 struct si_shader_selector
*sel
,
1898 union si_vgt_stages_key stages_key
,
1899 struct si_shader_key
*key
)
1901 struct si_context
*sctx
= (struct si_context
*)ctx
;
1903 memset(key
, 0, sizeof(*key
));
1905 switch (sel
->type
) {
1906 case PIPE_SHADER_VERTEX
:
1907 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1909 if (sctx
->tes_shader
.cso
)
1911 else if (sctx
->gs_shader
.cso
) {
1913 key
->as_ngg
= stages_key
.u
.ngg
;
1915 key
->as_ngg
= stages_key
.u
.ngg
;
1916 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1918 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1919 key
->mono
.u
.vs_export_prim_id
= 1;
1922 case PIPE_SHADER_TESS_CTRL
:
1923 if (sctx
->chip_class
>= GFX9
) {
1924 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1925 key
, &key
->part
.tcs
.ls_prolog
);
1926 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1928 /* When the LS VGPR fix is needed, monolithic shaders
1930 * - avoid initializing EXEC in both the LS prolog
1931 * and the LS main part when !vs_needs_prolog
1932 * - remove the fixup for unused input VGPRs
1934 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1936 /* The LS output / HS input layout can be communicated
1937 * directly instead of via user SGPRs for merged LS-HS.
1938 * The LS VGPR fix prefers this too.
1940 key
->opt
.prefer_mono
= 1;
1943 key
->part
.tcs
.epilog
.prim_mode
=
1944 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1945 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1946 sel
->info
.tessfactors_are_def_in_all_invocs
;
1947 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1948 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1950 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1951 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1953 case PIPE_SHADER_TESS_EVAL
:
1954 key
->as_ngg
= stages_key
.u
.ngg
;
1956 if (sctx
->gs_shader
.cso
)
1959 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1961 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1962 key
->mono
.u
.vs_export_prim_id
= 1;
1965 case PIPE_SHADER_GEOMETRY
:
1966 if (sctx
->chip_class
>= GFX9
) {
1967 if (sctx
->tes_shader
.cso
) {
1968 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1970 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1971 key
, &key
->part
.gs
.vs_prolog
);
1972 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1973 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1976 key
->as_ngg
= stages_key
.u
.ngg
;
1978 /* Merged ES-GS can have unbalanced wave usage.
1980 * ES threads are per-vertex, while GS threads are
1981 * per-primitive. So without any amplification, there
1982 * are fewer GS threads than ES threads, which can result
1983 * in empty (no-op) GS waves. With too much amplification,
1984 * there are more GS threads than ES threads, which
1985 * can result in empty (no-op) ES waves.
1987 * Non-monolithic shaders are implemented by setting EXEC
1988 * at the beginning of shader parts, and don't jump to
1989 * the end if EXEC is 0.
1991 * Monolithic shaders use conditional blocks, so they can
1992 * jump and skip empty waves of ES or GS. So set this to
1993 * always use optimized variants, which are monolithic.
1995 key
->opt
.prefer_mono
= 1;
1997 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1999 case PIPE_SHADER_FRAGMENT
: {
2000 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2001 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
2003 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
2004 sel
->info
.colors_written
== 0x1)
2005 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
2007 /* Select the shader color format based on whether
2008 * blending or alpha are needed.
2010 key
->part
.ps
.epilog
.spi_shader_col_format
=
2011 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
2012 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
2013 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
2014 sctx
->framebuffer
.spi_shader_col_format_blend
) |
2015 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
2016 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
2017 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
2018 sctx
->framebuffer
.spi_shader_col_format
);
2019 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
2021 /* The output for dual source blending should have
2022 * the same format as the first output.
2024 if (blend
->dual_src_blend
) {
2025 key
->part
.ps
.epilog
.spi_shader_col_format
|=
2026 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
2029 /* If alpha-to-coverage is enabled, we have to export alpha
2030 * even if there is no color buffer.
2032 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
2033 blend
->alpha_to_coverage
)
2034 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
2036 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
2037 * to the range supported by the type if a channel has less
2038 * than 16 bits and the export format is 16_ABGR.
2040 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
2041 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
2042 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
2045 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
2046 if (!key
->part
.ps
.epilog
.last_cbuf
) {
2047 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
2048 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
2049 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
2052 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
2053 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
2055 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
2056 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
2058 key
->part
.ps
.epilog
.alpha_to_one
= blend
->alpha_to_one
&&
2059 rs
->multisample_enable
;
2061 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
2062 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
2063 (is_line
&& rs
->line_smooth
)) &&
2064 sctx
->framebuffer
.nr_samples
<= 1;
2065 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
2067 if (sctx
->ps_iter_samples
> 1 &&
2068 sel
->info
.reads_samplemask
) {
2069 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
2070 util_logbase2(sctx
->ps_iter_samples
);
2073 if (rs
->force_persample_interp
&&
2074 rs
->multisample_enable
&&
2075 sctx
->framebuffer
.nr_samples
> 1 &&
2076 sctx
->ps_iter_samples
> 1) {
2077 key
->part
.ps
.prolog
.force_persp_sample_interp
=
2078 sel
->info
.uses_persp_center
||
2079 sel
->info
.uses_persp_centroid
;
2081 key
->part
.ps
.prolog
.force_linear_sample_interp
=
2082 sel
->info
.uses_linear_center
||
2083 sel
->info
.uses_linear_centroid
;
2084 } else if (rs
->multisample_enable
&&
2085 sctx
->framebuffer
.nr_samples
> 1) {
2086 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
2087 sel
->info
.uses_persp_center
&&
2088 sel
->info
.uses_persp_centroid
;
2089 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
2090 sel
->info
.uses_linear_center
&&
2091 sel
->info
.uses_linear_centroid
;
2093 /* Make sure SPI doesn't compute more than 1 pair
2094 * of (i,j), which is the optimization here. */
2095 key
->part
.ps
.prolog
.force_persp_center_interp
=
2096 sel
->info
.uses_persp_center
+
2097 sel
->info
.uses_persp_centroid
+
2098 sel
->info
.uses_persp_sample
> 1;
2100 key
->part
.ps
.prolog
.force_linear_center_interp
=
2101 sel
->info
.uses_linear_center
+
2102 sel
->info
.uses_linear_centroid
+
2103 sel
->info
.uses_linear_sample
> 1;
2105 if (sel
->info
.uses_persp_opcode_interp_sample
||
2106 sel
->info
.uses_linear_opcode_interp_sample
)
2107 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
2110 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
2112 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2113 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
2114 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
2115 struct pipe_resource
*tex
= cb0
->texture
;
2117 /* 1D textures are allocated and used as 2D on GFX9. */
2118 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
2119 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
2120 (tex
->target
== PIPE_TEXTURE_1D
||
2121 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
2122 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
2123 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
2124 tex
->target
== PIPE_TEXTURE_CUBE
||
2125 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2126 tex
->target
== PIPE_TEXTURE_3D
;
2134 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
2135 memset(&key
->opt
, 0, sizeof(key
->opt
));
2138 static void si_build_shader_variant(struct si_shader
*shader
,
2142 struct si_shader_selector
*sel
= shader
->selector
;
2143 struct si_screen
*sscreen
= sel
->screen
;
2144 struct ac_llvm_compiler
*compiler
;
2145 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
2147 if (thread_index
>= 0) {
2149 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
2150 compiler
= &sscreen
->compiler_lowp
[thread_index
];
2152 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2153 compiler
= &sscreen
->compiler
[thread_index
];
2158 assert(!low_priority
);
2159 compiler
= shader
->compiler_ctx_state
.compiler
;
2162 if (!compiler
->passes
)
2163 si_init_compiler(sscreen
, compiler
);
2165 if (unlikely(!si_create_shader_variant(sscreen
, compiler
, shader
, debug
))) {
2166 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2168 shader
->compilation_failed
= true;
2172 if (shader
->compiler_ctx_state
.is_debug_context
) {
2173 FILE *f
= open_memstream(&shader
->shader_log
,
2174 &shader
->shader_log_size
);
2176 si_shader_dump(sscreen
, shader
, NULL
, f
, false);
2181 si_shader_init_pm4_state(sscreen
, shader
);
2184 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2186 struct si_shader
*shader
= (struct si_shader
*)job
;
2188 assert(thread_index
>= 0);
2190 si_build_shader_variant(shader
, thread_index
, true);
2193 static const struct si_shader_key zeroed
;
2195 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
2196 struct si_shader_selector
*sel
,
2197 struct si_compiler_ctx_state
*compiler_state
,
2198 struct si_shader_key
*key
)
2200 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2203 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2208 /* We can leave the fence as permanently signaled because the
2209 * main part becomes visible globally only after it has been
2211 util_queue_fence_init(&main_part
->ready
);
2213 main_part
->selector
= sel
;
2214 main_part
->key
.as_es
= key
->as_es
;
2215 main_part
->key
.as_ls
= key
->as_ls
;
2216 main_part
->key
.as_ngg
= key
->as_ngg
;
2217 main_part
->is_monolithic
= false;
2219 if (si_compile_shader(sscreen
, compiler_state
->compiler
,
2220 main_part
, &compiler_state
->debug
) != 0) {
2230 * Select a shader variant according to the shader key.
2232 * \param optimized_or_none If the key describes an optimized shader variant and
2233 * the compilation isn't finished, don't select any
2234 * shader and return an error.
2236 int si_shader_select_with_key(struct si_screen
*sscreen
,
2237 struct si_shader_ctx_state
*state
,
2238 struct si_compiler_ctx_state
*compiler_state
,
2239 struct si_shader_key
*key
,
2241 bool optimized_or_none
)
2243 struct si_shader_selector
*sel
= state
->cso
;
2244 struct si_shader_selector
*previous_stage_sel
= NULL
;
2245 struct si_shader
*current
= state
->current
;
2246 struct si_shader
*iter
, *shader
= NULL
;
2249 /* Check if we don't need to change anything.
2250 * This path is also used for most shaders that don't need multiple
2251 * variants, it will cost just a computation of the key and this
2253 if (likely(current
&&
2254 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2255 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2256 if (current
->is_optimized
) {
2257 if (optimized_or_none
)
2260 memset(&key
->opt
, 0, sizeof(key
->opt
));
2261 goto current_not_ready
;
2264 util_queue_fence_wait(¤t
->ready
);
2267 return current
->compilation_failed
? -1 : 0;
2271 /* This must be done before the mutex is locked, because async GS
2272 * compilation calls this function too, and therefore must enter
2275 * Only wait if we are in a draw call. Don't wait if we are
2276 * in a compiler thread.
2278 if (thread_index
< 0)
2279 util_queue_fence_wait(&sel
->ready
);
2281 simple_mtx_lock(&sel
->mutex
);
2283 /* Find the shader variant. */
2284 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2285 /* Don't check the "current" shader. We checked it above. */
2286 if (current
!= iter
&&
2287 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2288 simple_mtx_unlock(&sel
->mutex
);
2290 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2291 /* If it's an optimized shader and its compilation has
2292 * been started but isn't done, use the unoptimized
2293 * shader so as not to cause a stall due to compilation.
2295 if (iter
->is_optimized
) {
2296 if (optimized_or_none
)
2298 memset(&key
->opt
, 0, sizeof(key
->opt
));
2302 util_queue_fence_wait(&iter
->ready
);
2305 if (iter
->compilation_failed
) {
2306 return -1; /* skip the draw call */
2309 state
->current
= iter
;
2314 /* Build a new shader. */
2315 shader
= CALLOC_STRUCT(si_shader
);
2317 simple_mtx_unlock(&sel
->mutex
);
2321 util_queue_fence_init(&shader
->ready
);
2323 shader
->selector
= sel
;
2325 shader
->compiler_ctx_state
= *compiler_state
;
2327 /* If this is a merged shader, get the first shader's selector. */
2328 if (sscreen
->info
.chip_class
>= GFX9
) {
2329 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2330 previous_stage_sel
= key
->part
.tcs
.ls
;
2331 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2332 previous_stage_sel
= key
->part
.gs
.es
;
2334 /* We need to wait for the previous shader. */
2335 if (previous_stage_sel
&& thread_index
< 0)
2336 util_queue_fence_wait(&previous_stage_sel
->ready
);
2339 bool is_pure_monolithic
=
2340 sscreen
->use_monolithic_shaders
||
2341 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2343 /* Compile the main shader part if it doesn't exist. This can happen
2344 * if the initial guess was wrong.
2346 * The prim discard CS doesn't need the main shader part.
2348 if (!is_pure_monolithic
&&
2349 !key
->opt
.vs_as_prim_discard_cs
) {
2352 /* Make sure the main shader part is present. This is needed
2353 * for shaders that can be compiled as VS, LS, or ES, and only
2354 * one of them is compiled at creation.
2356 * It is also needed for GS, which can be compiled as non-NGG
2359 * For merged shaders, check that the starting shader's main
2362 if (previous_stage_sel
) {
2363 struct si_shader_key shader1_key
= zeroed
;
2365 if (sel
->type
== PIPE_SHADER_TESS_CTRL
) {
2366 shader1_key
.as_ls
= 1;
2367 } else if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
2368 shader1_key
.as_es
= 1;
2369 shader1_key
.as_ngg
= key
->as_ngg
; /* for Wave32 vs Wave64 */
2374 simple_mtx_lock(&previous_stage_sel
->mutex
);
2375 ok
= si_check_missing_main_part(sscreen
,
2377 compiler_state
, &shader1_key
);
2378 simple_mtx_unlock(&previous_stage_sel
->mutex
);
2382 ok
= si_check_missing_main_part(sscreen
, sel
,
2383 compiler_state
, key
);
2388 simple_mtx_unlock(&sel
->mutex
);
2389 return -ENOMEM
; /* skip the draw call */
2393 /* Keep the reference to the 1st shader of merged shaders, so that
2394 * Gallium can't destroy it before we destroy the 2nd shader.
2396 * Set sctx = NULL, because it's unused if we're not releasing
2397 * the shader, and we don't have any sctx here.
2399 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
2400 previous_stage_sel
);
2402 /* Monolithic-only shaders don't make a distinction between optimized
2403 * and unoptimized. */
2404 shader
->is_monolithic
=
2405 is_pure_monolithic
||
2406 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2408 /* The prim discard CS is always optimized. */
2409 shader
->is_optimized
=
2410 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2411 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2413 /* If it's an optimized shader, compile it asynchronously. */
2414 if (shader
->is_optimized
&& thread_index
< 0) {
2415 /* Compile it asynchronously. */
2416 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
2417 shader
, &shader
->ready
,
2418 si_build_shader_variant_low_priority
, NULL
,
2421 /* Add only after the ready fence was reset, to guard against a
2422 * race with si_bind_XX_shader. */
2423 if (!sel
->last_variant
) {
2424 sel
->first_variant
= shader
;
2425 sel
->last_variant
= shader
;
2427 sel
->last_variant
->next_variant
= shader
;
2428 sel
->last_variant
= shader
;
2431 /* Use the default (unoptimized) shader for now. */
2432 memset(&key
->opt
, 0, sizeof(key
->opt
));
2433 simple_mtx_unlock(&sel
->mutex
);
2435 if (sscreen
->options
.sync_compile
)
2436 util_queue_fence_wait(&shader
->ready
);
2438 if (optimized_or_none
)
2443 /* Reset the fence before adding to the variant list. */
2444 util_queue_fence_reset(&shader
->ready
);
2446 if (!sel
->last_variant
) {
2447 sel
->first_variant
= shader
;
2448 sel
->last_variant
= shader
;
2450 sel
->last_variant
->next_variant
= shader
;
2451 sel
->last_variant
= shader
;
2454 simple_mtx_unlock(&sel
->mutex
);
2456 assert(!shader
->is_optimized
);
2457 si_build_shader_variant(shader
, thread_index
, false);
2459 util_queue_fence_signal(&shader
->ready
);
2461 if (!shader
->compilation_failed
)
2462 state
->current
= shader
;
2464 return shader
->compilation_failed
? -1 : 0;
2467 static int si_shader_select(struct pipe_context
*ctx
,
2468 struct si_shader_ctx_state
*state
,
2469 union si_vgt_stages_key stages_key
,
2470 struct si_compiler_ctx_state
*compiler_state
)
2472 struct si_context
*sctx
= (struct si_context
*)ctx
;
2473 struct si_shader_key key
;
2475 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2476 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2480 static void si_parse_next_shader_property(const struct si_shader_info
*info
,
2482 struct si_shader_key
*key
)
2484 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2486 switch (info
->processor
) {
2487 case PIPE_SHADER_VERTEX
:
2488 switch (next_shader
) {
2489 case PIPE_SHADER_GEOMETRY
:
2492 case PIPE_SHADER_TESS_CTRL
:
2493 case PIPE_SHADER_TESS_EVAL
:
2497 /* If POSITION isn't written, it can only be a HW VS
2498 * if streamout is used. If streamout isn't used,
2499 * assume that it's a HW LS. (the next shader is TCS)
2500 * This heuristic is needed for separate shader objects.
2502 if (!info
->writes_position
&& !streamout
)
2507 case PIPE_SHADER_TESS_EVAL
:
2508 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2509 !info
->writes_position
)
2516 * Compile the main shader part or the monolithic shader as part of
2517 * si_shader_selector initialization. Since it can be done asynchronously,
2518 * there is no way to report compile failures to applications.
2520 static void si_init_shader_selector_async(void *job
, int thread_index
)
2522 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2523 struct si_screen
*sscreen
= sel
->screen
;
2524 struct ac_llvm_compiler
*compiler
;
2525 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2527 assert(!debug
->debug_message
|| debug
->async
);
2528 assert(thread_index
>= 0);
2529 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2530 compiler
= &sscreen
->compiler
[thread_index
];
2532 if (!compiler
->passes
)
2533 si_init_compiler(sscreen
, compiler
);
2535 /* Serialize NIR to save memory. Monolithic shader variants
2536 * have to deserialize NIR before compilation.
2543 /* true = remove optional debugging data to increase
2544 * the likehood of getting more shader cache hits.
2545 * It also drops variable names, so we'll save more memory.
2547 nir_serialize(&blob
, sel
->nir
, true);
2548 blob_finish_get_buffer(&blob
, &sel
->nir_binary
, &size
);
2549 sel
->nir_size
= size
;
2552 /* Compile the main shader part for use with a prolog and/or epilog.
2553 * If this fails, the driver will try to compile a monolithic shader
2556 if (!sscreen
->use_monolithic_shaders
) {
2557 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2558 unsigned char ir_sha1_cache_key
[20];
2561 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2565 /* We can leave the fence signaled because use of the default
2566 * main part is guarded by the selector's ready fence. */
2567 util_queue_fence_init(&shader
->ready
);
2569 shader
->selector
= sel
;
2570 shader
->is_monolithic
= false;
2571 si_parse_next_shader_property(&sel
->info
,
2572 sel
->so
.num_outputs
!= 0,
2575 if (sscreen
->use_ngg
&&
2576 (!sel
->so
.num_outputs
|| sscreen
->use_ngg_streamout
) &&
2577 ((sel
->type
== PIPE_SHADER_VERTEX
&& !shader
->key
.as_ls
) ||
2578 sel
->type
== PIPE_SHADER_TESS_EVAL
||
2579 sel
->type
== PIPE_SHADER_GEOMETRY
))
2580 shader
->key
.as_ngg
= 1;
2583 si_get_ir_cache_key(sel
, shader
->key
.as_ngg
,
2584 shader
->key
.as_es
, ir_sha1_cache_key
);
2587 /* Try to load the shader from the shader cache. */
2588 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2590 if (si_shader_cache_load_shader(sscreen
, ir_sha1_cache_key
, shader
)) {
2591 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2592 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2594 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2596 /* Compile the shader if it hasn't been loaded from the cache. */
2597 if (si_compile_shader(sscreen
, compiler
, shader
,
2600 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2604 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2605 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
,
2607 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2610 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2612 /* Unset "outputs_written" flags for outputs converted to
2613 * DEFAULT_VAL, so that later inter-shader optimizations don't
2614 * try to eliminate outputs that don't exist in the final
2617 * This is only done if non-monolithic shaders are enabled.
2619 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2620 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2621 !shader
->key
.as_ls
&&
2622 !shader
->key
.as_es
) {
2625 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2626 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2628 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2631 unsigned name
= sel
->info
.output_semantic_name
[i
];
2632 unsigned index
= sel
->info
.output_semantic_index
[i
];
2636 case TGSI_SEMANTIC_GENERIC
:
2637 /* don't process indices the function can't handle */
2638 if (index
>= SI_MAX_IO_GENERIC
)
2642 id
= si_shader_io_get_unique_index(name
, index
, true);
2643 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2645 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2646 case TGSI_SEMANTIC_PSIZE
:
2647 case TGSI_SEMANTIC_CLIPVERTEX
:
2648 case TGSI_SEMANTIC_EDGEFLAG
:
2655 /* The GS copy shader is always pre-compiled. */
2656 if (sel
->type
== PIPE_SHADER_GEOMETRY
&&
2657 (!sscreen
->use_ngg
||
2658 !sscreen
->use_ngg_streamout
|| /* also for PRIMITIVES_GENERATED */
2659 sel
->tess_turns_off_ngg
)) {
2660 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2661 if (!sel
->gs_copy_shader
) {
2662 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2666 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2669 /* Free NIR. We only keep serialized NIR after this point. */
2671 ralloc_free(sel
->nir
);
2676 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2677 struct util_queue_fence
*ready_fence
,
2678 struct si_compiler_ctx_state
*compiler_ctx_state
,
2679 void *job
, util_queue_execute_func execute
)
2681 util_queue_fence_init(ready_fence
);
2683 struct util_async_debug_callback async_debug
;
2685 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2687 si_can_dump_shader(sctx
->screen
, processor
);
2690 u_async_debug_init(&async_debug
);
2691 compiler_ctx_state
->debug
= async_debug
.base
;
2694 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2695 ready_fence
, execute
, NULL
, 0);
2698 util_queue_fence_wait(ready_fence
);
2699 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2700 u_async_debug_cleanup(&async_debug
);
2703 if (sctx
->screen
->options
.sync_compile
)
2704 util_queue_fence_wait(ready_fence
);
2707 /* Return descriptor slot usage masks from the given shader info. */
2708 void si_get_active_slot_masks(const struct si_shader_info
*info
,
2709 uint32_t *const_and_shader_buffers
,
2710 uint64_t *samplers_and_images
)
2712 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_msaa_images
, num_samplers
;
2714 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2715 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2716 /* two 8-byte images share one 16-byte slot */
2717 num_images
= align(util_last_bit(info
->images_declared
), 2);
2718 num_msaa_images
= align(util_last_bit(info
->msaa_images_declared
), 2);
2719 num_samplers
= util_last_bit(info
->samplers_declared
);
2721 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2722 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2723 *const_and_shader_buffers
=
2724 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2727 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2728 * - image[last] ... image[0] go to [31-last .. 31]
2729 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2731 * FMASKs for images are placed separately, because MSAA images are rare,
2732 * and so we can benefit from a better cache hit rate if we keep image
2733 * descriptors together.
2735 if (num_msaa_images
)
2736 num_images
= SI_NUM_IMAGES
+ num_msaa_images
; /* add FMASK descriptors */
2738 start
= si_get_image_slot(num_images
- 1) / 2;
2739 *samplers_and_images
=
2740 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2743 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2744 const struct pipe_shader_state
*state
)
2746 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2747 struct si_context
*sctx
= (struct si_context
*)ctx
;
2748 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2754 pipe_reference_init(&sel
->reference
, 1);
2755 sel
->screen
= sscreen
;
2756 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2757 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2759 sel
->so
= state
->stream_output
;
2761 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2762 sel
->nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
2764 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2765 sel
->nir
= state
->ir
.nir
;
2768 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2769 si_nir_adjust_driver_locations(sel
->nir
);
2771 sel
->type
= sel
->info
.processor
;
2772 p_atomic_inc(&sscreen
->num_shaders_created
);
2773 si_get_active_slot_masks(&sel
->info
,
2774 &sel
->active_const_and_shader_buffers
,
2775 &sel
->active_samplers_and_images
);
2777 /* Record which streamout buffers are enabled. */
2778 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2779 sel
->enabled_streamout_buffer_mask
|=
2780 (1 << sel
->so
.output
[i
].output_buffer
) <<
2781 (sel
->so
.output
[i
].stream
* 4);
2784 sel
->num_vs_inputs
= sel
->type
== PIPE_SHADER_VERTEX
&&
2785 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] ?
2786 sel
->info
.num_inputs
: 0;
2787 sel
->num_vbos_in_user_sgprs
=
2788 MIN2(sel
->num_vs_inputs
, sscreen
->num_vbos_in_user_sgprs
);
2790 /* The prolog is a no-op if there are no inputs. */
2791 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2792 sel
->info
.num_inputs
&&
2793 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
2795 sel
->force_correct_derivs_after_kill
=
2796 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2797 sel
->info
.uses_derivatives
&&
2798 sel
->info
.uses_kill
&&
2799 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2801 sel
->prim_discard_cs_allowed
=
2802 sel
->type
== PIPE_SHADER_VERTEX
&&
2803 !sel
->info
.uses_bindless_images
&&
2804 !sel
->info
.uses_bindless_samplers
&&
2805 !sel
->info
.writes_memory
&&
2806 !sel
->info
.writes_viewport_index
&&
2807 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2808 !sel
->so
.num_outputs
;
2810 switch (sel
->type
) {
2811 case PIPE_SHADER_GEOMETRY
:
2812 sel
->gs_output_prim
=
2813 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2815 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2816 sel
->rast_prim
= sel
->gs_output_prim
;
2817 if (util_rast_prim_is_triangles(sel
->rast_prim
))
2818 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2820 sel
->gs_max_out_vertices
=
2821 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2822 sel
->gs_num_invocations
=
2823 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2824 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2825 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2826 sel
->gs_max_out_vertices
;
2828 sel
->max_gs_stream
= 0;
2829 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2830 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2831 sel
->so
.output
[i
].stream
);
2833 sel
->gs_input_verts_per_prim
=
2834 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2836 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2837 sel
->tess_turns_off_ngg
=
2838 sscreen
->info
.chip_class
== GFX10
&&
2839 sel
->gs_num_invocations
* sel
->gs_max_out_vertices
> 256;
2842 case PIPE_SHADER_TESS_CTRL
:
2843 /* Always reserve space for these. */
2844 sel
->patch_outputs_written
|=
2845 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2846 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2848 case PIPE_SHADER_VERTEX
:
2849 case PIPE_SHADER_TESS_EVAL
:
2850 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2851 unsigned name
= sel
->info
.output_semantic_name
[i
];
2852 unsigned index
= sel
->info
.output_semantic_index
[i
];
2855 case TGSI_SEMANTIC_TESSINNER
:
2856 case TGSI_SEMANTIC_TESSOUTER
:
2857 case TGSI_SEMANTIC_PATCH
:
2858 sel
->patch_outputs_written
|=
2859 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2862 case TGSI_SEMANTIC_GENERIC
:
2863 /* don't process indices the function can't handle */
2864 if (index
>= SI_MAX_IO_GENERIC
)
2868 sel
->outputs_written
|=
2869 1ull << si_shader_io_get_unique_index(name
, index
, false);
2870 sel
->outputs_written_before_ps
|=
2871 1ull << si_shader_io_get_unique_index(name
, index
, true);
2873 case TGSI_SEMANTIC_EDGEFLAG
:
2877 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2878 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2880 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2881 * will start on a different bank. (except for the maximum 32*16).
2883 if (sel
->lshs_vertex_stride
< 32*16)
2884 sel
->lshs_vertex_stride
+= 4;
2886 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2887 * conflicts, i.e. each vertex will start at a different bank.
2889 if (sctx
->chip_class
>= GFX9
)
2890 sel
->esgs_itemsize
+= 4;
2892 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2895 if (sel
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
2896 sel
->rast_prim
= PIPE_PRIM_POINTS
;
2897 else if (sel
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
2898 sel
->rast_prim
= PIPE_PRIM_LINE_STRIP
;
2900 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2903 case PIPE_SHADER_FRAGMENT
:
2904 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2905 unsigned name
= sel
->info
.input_semantic_name
[i
];
2906 unsigned index
= sel
->info
.input_semantic_index
[i
];
2909 case TGSI_SEMANTIC_GENERIC
:
2910 /* don't process indices the function can't handle */
2911 if (index
>= SI_MAX_IO_GENERIC
)
2916 1ull << si_shader_io_get_unique_index(name
, index
, true);
2918 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2923 for (i
= 0; i
< 8; i
++)
2924 if (sel
->info
.colors_written
& (1 << i
))
2925 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2927 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2928 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2929 int index
= sel
->info
.input_semantic_index
[i
];
2930 sel
->color_attr_index
[index
] = i
;
2937 sel
->ngg_culling_allowed
=
2938 sscreen
->info
.chip_class
== GFX10
&&
2939 sscreen
->info
.has_dedicated_vram
&&
2940 sscreen
->use_ngg_culling
&&
2941 /* Disallow TES by default, because TessMark results are mixed. */
2942 (sel
->type
== PIPE_SHADER_VERTEX
||
2943 (sscreen
->always_use_ngg_culling
&& sel
->type
== PIPE_SHADER_TESS_EVAL
)) &&
2944 sel
->info
.writes_position
&&
2945 !sel
->info
.writes_viewport_index
&& /* cull only against viewport 0 */
2946 !sel
->info
.writes_memory
&&
2947 !sel
->so
.num_outputs
&&
2948 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] &&
2949 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
2951 /* PA_CL_VS_OUT_CNTL */
2952 if (sctx
->chip_class
<= GFX9
)
2953 sel
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(sel
, false);
2955 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2956 SIX_BITS
: sel
->info
.clipdist_writemask
;
2957 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2958 sel
->info
.num_written_clipdistance
;
2960 /* DB_SHADER_CONTROL */
2961 sel
->db_shader_control
=
2962 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2963 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2964 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2965 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2967 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2968 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2969 sel
->db_shader_control
|=
2970 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2972 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2973 sel
->db_shader_control
|=
2974 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2978 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2980 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2981 * --|-----------|------------|------------|--------------------|-------------------|-------------
2982 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2983 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2984 * 2 | false | true | n/a | LateZ | 1 | 0
2985 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2986 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2988 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2989 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2991 * Don't use ReZ without profiling !!!
2993 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2996 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2998 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2999 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
3000 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
3001 } else if (sel
->info
.writes_memory
) {
3003 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
3004 S_02880C_EXEC_ON_HIER_FAIL(1);
3007 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3010 if (sel
->info
.properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
])
3011 sel
->db_shader_control
|= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
3013 (void) simple_mtx_init(&sel
->mutex
, mtx_plain
);
3015 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
3016 &sel
->compiler_ctx_state
, sel
,
3017 si_init_shader_selector_async
);
3021 static void si_update_streamout_state(struct si_context
*sctx
)
3023 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
3025 if (!shader_with_so
)
3028 sctx
->streamout
.enabled_stream_buffers_mask
=
3029 shader_with_so
->enabled_streamout_buffer_mask
;
3030 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
3033 static void si_update_clip_regs(struct si_context
*sctx
,
3034 struct si_shader_selector
*old_hw_vs
,
3035 struct si_shader
*old_hw_vs_variant
,
3036 struct si_shader_selector
*next_hw_vs
,
3037 struct si_shader
*next_hw_vs_variant
)
3041 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
3042 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
3043 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
3044 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
3045 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
3046 !old_hw_vs_variant
||
3047 !next_hw_vs_variant
||
3048 old_hw_vs_variant
->key
.opt
.clip_disable
!=
3049 next_hw_vs_variant
->key
.opt
.clip_disable
))
3050 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3053 static void si_update_common_shader_state(struct si_context
*sctx
)
3055 sctx
->uses_bindless_samplers
=
3056 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
3057 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
3058 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
3059 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
3060 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
3061 sctx
->uses_bindless_images
=
3062 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
3063 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
3064 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
3065 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
3066 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
3067 sctx
->do_update_shaders
= true;
3070 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
3072 struct si_context
*sctx
= (struct si_context
*)ctx
;
3073 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3074 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3075 struct si_shader_selector
*sel
= state
;
3077 if (sctx
->vs_shader
.cso
== sel
)
3080 sctx
->vs_shader
.cso
= sel
;
3081 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3082 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] : 0;
3084 if (si_update_ngg(sctx
))
3085 si_shader_change_notify(sctx
);
3087 si_update_common_shader_state(sctx
);
3088 si_update_vs_viewport_state(sctx
);
3089 si_set_active_descriptors_for_shader(sctx
, sel
);
3090 si_update_streamout_state(sctx
);
3091 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3092 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3095 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
3097 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
3098 (sctx
->tes_shader
.cso
&&
3099 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
3100 (sctx
->tcs_shader
.cso
&&
3101 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
3102 (sctx
->gs_shader
.cso
&&
3103 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
3104 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
3105 sctx
->ps_shader
.cso
->info
.uses_primid
);
3108 bool si_update_ngg(struct si_context
*sctx
)
3110 if (!sctx
->screen
->use_ngg
) {
3115 bool new_ngg
= true;
3117 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&&
3118 sctx
->gs_shader
.cso
->tess_turns_off_ngg
) {
3120 } else if (!sctx
->screen
->use_ngg_streamout
) {
3121 struct si_shader_selector
*last
= si_get_vs(sctx
)->cso
;
3123 if ((last
&& last
->so
.num_outputs
) ||
3124 sctx
->streamout
.prims_gen_query_enabled
)
3128 if (new_ngg
!= sctx
->ngg
) {
3129 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3130 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3133 if ((sctx
->family
== CHIP_NAVI10
||
3134 sctx
->family
== CHIP_NAVI12
||
3135 sctx
->family
== CHIP_NAVI14
) &&
3137 sctx
->flags
|= SI_CONTEXT_VGT_FLUSH
;
3139 sctx
->ngg
= new_ngg
;
3140 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
3146 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
3148 struct si_context
*sctx
= (struct si_context
*)ctx
;
3149 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3150 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3151 struct si_shader_selector
*sel
= state
;
3152 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
3155 if (sctx
->gs_shader
.cso
== sel
)
3158 sctx
->gs_shader
.cso
= sel
;
3159 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3160 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
3162 si_update_common_shader_state(sctx
);
3163 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
3165 ngg_changed
= si_update_ngg(sctx
);
3166 if (ngg_changed
|| enable_changed
)
3167 si_shader_change_notify(sctx
);
3168 if (enable_changed
) {
3169 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3170 si_update_tess_uses_prim_id(sctx
);
3172 si_update_vs_viewport_state(sctx
);
3173 si_set_active_descriptors_for_shader(sctx
, sel
);
3174 si_update_streamout_state(sctx
);
3175 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3176 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3179 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
3181 struct si_context
*sctx
= (struct si_context
*)ctx
;
3182 struct si_shader_selector
*sel
= state
;
3183 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
3185 if (sctx
->tcs_shader
.cso
== sel
)
3188 sctx
->tcs_shader
.cso
= sel
;
3189 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3190 si_update_tess_uses_prim_id(sctx
);
3192 si_update_common_shader_state(sctx
);
3195 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
3197 si_set_active_descriptors_for_shader(sctx
, sel
);
3200 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
3202 struct si_context
*sctx
= (struct si_context
*)ctx
;
3203 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3204 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3205 struct si_shader_selector
*sel
= state
;
3206 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
3208 if (sctx
->tes_shader
.cso
== sel
)
3211 sctx
->tes_shader
.cso
= sel
;
3212 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
3213 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
3214 si_update_tess_uses_prim_id(sctx
);
3216 si_update_common_shader_state(sctx
);
3217 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
3219 bool ngg_changed
= si_update_ngg(sctx
);
3220 if (ngg_changed
|| enable_changed
)
3221 si_shader_change_notify(sctx
);
3223 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
3224 si_update_vs_viewport_state(sctx
);
3225 si_set_active_descriptors_for_shader(sctx
, sel
);
3226 si_update_streamout_state(sctx
);
3227 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3228 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3231 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3233 struct si_context
*sctx
= (struct si_context
*)ctx
;
3234 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3235 struct si_shader_selector
*sel
= state
;
3237 /* skip if supplied shader is one already in use */
3241 sctx
->ps_shader
.cso
= sel
;
3242 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3244 si_update_common_shader_state(sctx
);
3246 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3247 si_update_tess_uses_prim_id(sctx
);
3250 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3251 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3253 if (sctx
->screen
->has_out_of_order_rast
&&
3255 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
3256 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
3257 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
3258 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3260 si_set_active_descriptors_for_shader(sctx
, sel
);
3261 si_update_ps_colorbuf0_slot(sctx
);
3264 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3266 if (shader
->is_optimized
) {
3267 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
3271 util_queue_fence_destroy(&shader
->ready
);
3274 /* If destroyed shaders were not unbound, the next compiled
3275 * shader variant could get the same pointer address and so
3276 * binding it to the same shader stage would be considered
3277 * a no-op, causing random behavior.
3279 switch (shader
->selector
->type
) {
3280 case PIPE_SHADER_VERTEX
:
3281 if (shader
->key
.as_ls
) {
3282 assert(sctx
->chip_class
<= GFX8
);
3283 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3284 } else if (shader
->key
.as_es
) {
3285 assert(sctx
->chip_class
<= GFX8
);
3286 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3287 } else if (shader
->key
.as_ngg
) {
3288 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3290 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3293 case PIPE_SHADER_TESS_CTRL
:
3294 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3296 case PIPE_SHADER_TESS_EVAL
:
3297 if (shader
->key
.as_es
) {
3298 assert(sctx
->chip_class
<= GFX8
);
3299 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3300 } else if (shader
->key
.as_ngg
) {
3301 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3303 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3306 case PIPE_SHADER_GEOMETRY
:
3307 if (shader
->is_gs_copy_shader
)
3308 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3310 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3312 case PIPE_SHADER_FRAGMENT
:
3313 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3319 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3320 si_shader_destroy(shader
);
3324 void si_destroy_shader_selector(struct si_context
*sctx
,
3325 struct si_shader_selector
*sel
)
3327 struct si_shader
*p
= sel
->first_variant
, *c
;
3328 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3329 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
3330 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3331 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3332 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3333 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3336 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3338 if (current_shader
[sel
->type
]->cso
== sel
) {
3339 current_shader
[sel
->type
]->cso
= NULL
;
3340 current_shader
[sel
->type
]->current
= NULL
;
3344 c
= p
->next_variant
;
3345 si_delete_shader(sctx
, p
);
3349 if (sel
->main_shader_part
)
3350 si_delete_shader(sctx
, sel
->main_shader_part
);
3351 if (sel
->main_shader_part_ls
)
3352 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3353 if (sel
->main_shader_part_es
)
3354 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3355 if (sel
->main_shader_part_ngg
)
3356 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3357 if (sel
->gs_copy_shader
)
3358 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3360 util_queue_fence_destroy(&sel
->ready
);
3361 simple_mtx_destroy(&sel
->mutex
);
3362 ralloc_free(sel
->nir
);
3363 free(sel
->nir_binary
);
3367 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3369 struct si_context
*sctx
= (struct si_context
*)ctx
;
3370 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3372 si_shader_selector_reference(sctx
, &sel
, NULL
);
3375 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
3376 struct si_shader
*vs
, unsigned name
,
3377 unsigned index
, unsigned interpolate
)
3379 struct si_shader_info
*vsinfo
= &vs
->selector
->info
;
3380 unsigned j
, offset
, ps_input_cntl
= 0;
3382 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3383 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
3384 name
== TGSI_SEMANTIC_PRIMID
)
3385 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3387 if (name
== TGSI_SEMANTIC_PCOORD
||
3388 (name
== TGSI_SEMANTIC_TEXCOORD
&&
3389 sctx
->sprite_coord_enable
& (1 << index
))) {
3390 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3393 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
3394 if (name
== vsinfo
->output_semantic_name
[j
] &&
3395 index
== vsinfo
->output_semantic_index
[j
]) {
3396 offset
= vs
->info
.vs_output_param_offset
[j
];
3398 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3399 /* The input is loaded from parameter memory. */
3400 ps_input_cntl
|= S_028644_OFFSET(offset
);
3401 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3402 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3403 /* This can happen with depth-only rendering. */
3406 /* The input is a DEFAULT_VAL constant. */
3407 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3408 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3409 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3412 ps_input_cntl
= S_028644_OFFSET(0x20) |
3413 S_028644_DEFAULT_VAL(offset
);
3419 if (j
== vsinfo
->num_outputs
&& name
== TGSI_SEMANTIC_PRIMID
)
3420 /* PrimID is written after the last output when HW VS is used. */
3421 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3422 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3423 /* No corresponding output found, load defaults into input.
3424 * Don't set any other bits.
3425 * (FLAT_SHADE=1 completely changes behavior) */
3426 ps_input_cntl
= S_028644_OFFSET(0x20);
3427 /* D3D 9 behaviour. GL is undefined */
3428 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
3429 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3431 return ps_input_cntl
;
3434 static void si_emit_spi_map(struct si_context
*sctx
)
3436 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3437 struct si_shader
*vs
= si_get_vs_state(sctx
);
3438 struct si_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3439 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
3440 unsigned spi_ps_input_cntl
[32];
3442 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3445 num_interp
= si_get_ps_num_interp(ps
);
3446 assert(num_interp
> 0);
3448 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3449 unsigned name
= psinfo
->input_semantic_name
[i
];
3450 unsigned index
= psinfo
->input_semantic_index
[i
];
3451 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3453 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
3454 index
, interpolate
);
3456 if (name
== TGSI_SEMANTIC_COLOR
) {
3457 assert(index
< ARRAY_SIZE(bcol_interp
));
3458 bcol_interp
[index
] = interpolate
;
3462 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3463 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
3465 for (i
= 0; i
< 2; i
++) {
3466 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3469 spi_ps_input_cntl
[num_written
++] =
3470 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
3474 assert(num_interp
== num_written
);
3476 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3477 /* Dota 2: Only ~16% of SPI map updates set different values. */
3478 /* Talos: Only ~9% of SPI map updates set different values. */
3479 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3480 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
3482 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3484 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3485 sctx
->context_roll
= true;
3489 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3491 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
3493 if (sctx
->init_config_has_vgt_flush
)
3496 /* Done by Vulkan before VGT_FLUSH. */
3497 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3498 si_pm4_cmd_add(sctx
->init_config
,
3499 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3500 si_pm4_cmd_end(sctx
->init_config
, false);
3502 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3503 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3504 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3505 si_pm4_cmd_end(sctx
->init_config
, false);
3506 sctx
->init_config_has_vgt_flush
= true;
3509 /* Initialize state related to ESGS / GSVS ring buffers */
3510 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3512 struct si_shader_selector
*es
=
3513 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3514 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3515 struct si_pm4_state
*pm4
;
3517 /* Chip constants. */
3518 unsigned num_se
= sctx
->screen
->info
.max_se
;
3519 unsigned wave_size
= 64;
3520 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3521 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3522 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3524 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3525 unsigned alignment
= 256 * num_se
;
3526 /* The maximum size is 63.999 MB per SE. */
3527 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3529 /* Calculate the minimum size. */
3530 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
3531 wave_size
, alignment
);
3533 /* These are recommended sizes, not minimum sizes. */
3534 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
3535 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3536 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
3537 gs
->max_gsvs_emit_size
;
3539 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3540 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3541 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3543 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3544 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3546 /* Some rings don't have to be allocated if shaders don't use them.
3547 * (e.g. no varyings between ES and GS or GS and VS)
3549 * GFX9 doesn't have the ESGS ring.
3551 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
3553 (!sctx
->esgs_ring
||
3554 sctx
->esgs_ring
->width0
< esgs_ring_size
);
3555 bool update_gsvs
= gsvs_ring_size
&&
3556 (!sctx
->gsvs_ring
||
3557 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3559 if (!update_esgs
&& !update_gsvs
)
3563 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3565 pipe_aligned_buffer_create(sctx
->b
.screen
,
3566 SI_RESOURCE_FLAG_UNMAPPABLE
,
3569 sctx
->screen
->info
.pte_fragment_size
);
3570 if (!sctx
->esgs_ring
)
3575 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3577 pipe_aligned_buffer_create(sctx
->b
.screen
,
3578 SI_RESOURCE_FLAG_UNMAPPABLE
,
3581 sctx
->screen
->info
.pte_fragment_size
);
3582 if (!sctx
->gsvs_ring
)
3586 /* Create the "init_config_gs_rings" state. */
3587 pm4
= CALLOC_STRUCT(si_pm4_state
);
3591 if (sctx
->chip_class
>= GFX7
) {
3592 if (sctx
->esgs_ring
) {
3593 assert(sctx
->chip_class
<= GFX8
);
3594 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3595 sctx
->esgs_ring
->width0
/ 256);
3597 if (sctx
->gsvs_ring
)
3598 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3599 sctx
->gsvs_ring
->width0
/ 256);
3601 if (sctx
->esgs_ring
)
3602 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3603 sctx
->esgs_ring
->width0
/ 256);
3604 if (sctx
->gsvs_ring
)
3605 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3606 sctx
->gsvs_ring
->width0
/ 256);
3609 /* Set the state. */
3610 if (sctx
->init_config_gs_rings
)
3611 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3612 sctx
->init_config_gs_rings
= pm4
;
3614 if (!sctx
->init_config_has_vgt_flush
) {
3615 si_init_config_add_vgt_flush(sctx
);
3616 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3619 /* Flush the context to re-emit both init_config states. */
3620 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3621 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3623 /* Set ring bindings. */
3624 if (sctx
->esgs_ring
) {
3625 assert(sctx
->chip_class
<= GFX8
);
3626 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3627 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3628 true, true, 4, 64, 0);
3629 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3630 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3631 false, false, 0, 0, 0);
3633 if (sctx
->gsvs_ring
) {
3634 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3635 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3636 false, false, 0, 0, 0);
3642 static void si_shader_lock(struct si_shader
*shader
)
3644 simple_mtx_lock(&shader
->selector
->mutex
);
3645 if (shader
->previous_stage_sel
) {
3646 assert(shader
->previous_stage_sel
!= shader
->selector
);
3647 simple_mtx_lock(&shader
->previous_stage_sel
->mutex
);
3651 static void si_shader_unlock(struct si_shader
*shader
)
3653 if (shader
->previous_stage_sel
)
3654 simple_mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3655 simple_mtx_unlock(&shader
->selector
->mutex
);
3659 * @returns 1 if \p sel has been updated to use a new scratch buffer
3661 * < 0 if there was a failure
3663 static int si_update_scratch_buffer(struct si_context
*sctx
,
3664 struct si_shader
*shader
)
3666 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3671 /* This shader doesn't need a scratch buffer */
3672 if (shader
->config
.scratch_bytes_per_wave
== 0)
3675 /* Prevent race conditions when updating:
3676 * - si_shader::scratch_bo
3677 * - si_shader::binary::code
3678 * - si_shader::previous_stage::binary::code.
3680 si_shader_lock(shader
);
3682 /* This shader is already configured to use the current
3683 * scratch buffer. */
3684 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3685 si_shader_unlock(shader
);
3689 assert(sctx
->scratch_buffer
);
3691 /* Replace the shader bo with a new bo that has the relocs applied. */
3692 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3693 si_shader_unlock(shader
);
3697 /* Update the shader state to use the new shader bo. */
3698 si_shader_init_pm4_state(sctx
->screen
, shader
);
3700 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3702 si_shader_unlock(shader
);
3706 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3708 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3711 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3713 if (!sctx
->tes_shader
.cso
)
3714 return NULL
; /* tessellation disabled */
3716 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3717 sctx
->fixed_func_tcs_shader
.current
;
3720 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3722 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3725 /* Update the shaders, so that they are using the latest scratch.
3726 * The scratch buffer may have been changed since these shaders were
3727 * last used, so we still need to try to update them, even if they
3728 * require scratch buffers smaller than the current size.
3730 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3734 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3736 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3740 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3742 r
= si_update_scratch_buffer(sctx
, tcs
);
3746 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3748 /* VS can be bound as LS, ES, or VS. */
3749 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3753 if (sctx
->vs_shader
.current
->key
.as_ls
)
3754 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3755 else if (sctx
->vs_shader
.current
->key
.as_es
)
3756 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3757 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3758 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3760 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3763 /* TES can be bound as ES or VS. */
3764 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3768 if (sctx
->tes_shader
.current
->key
.as_es
)
3769 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3770 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3771 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3773 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3779 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3781 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3782 * There are 2 cases to handle:
3784 * - If the current needed size is less than the maximum seen size,
3785 * use the maximum seen size, so that WAVESIZE remains the same.
3787 * - If the current needed size is greater than the maximum seen size,
3788 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3790 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3791 * Otherwise, the number of waves that can use scratch is
3792 * SPI_TMPRING_SIZE.WAVES.
3796 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3797 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3798 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3800 if (sctx
->tes_shader
.cso
) {
3801 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3802 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx
)));
3805 sctx
->max_seen_scratch_bytes_per_wave
=
3806 MAX2(sctx
->max_seen_scratch_bytes_per_wave
, bytes
);
3808 unsigned scratch_needed_size
=
3809 sctx
->max_seen_scratch_bytes_per_wave
* sctx
->scratch_waves
;
3810 unsigned spi_tmpring_size
;
3812 if (scratch_needed_size
> 0) {
3813 if (!sctx
->scratch_buffer
||
3814 scratch_needed_size
> sctx
->scratch_buffer
->b
.b
.width0
) {
3815 /* Create a bigger scratch buffer */
3816 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3818 sctx
->scratch_buffer
=
3819 si_aligned_buffer_create(&sctx
->screen
->b
,
3820 SI_RESOURCE_FLAG_UNMAPPABLE
,
3822 scratch_needed_size
,
3823 sctx
->screen
->info
.pte_fragment_size
);
3824 if (!sctx
->scratch_buffer
)
3827 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3828 si_context_add_resource_size(sctx
,
3829 &sctx
->scratch_buffer
->b
.b
);
3832 if (!si_update_scratch_relocs(sctx
))
3836 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3837 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3838 "scratch size should already be aligned correctly.");
3840 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3841 S_0286E8_WAVESIZE(sctx
->max_seen_scratch_bytes_per_wave
>> 10);
3842 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3843 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3844 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3849 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3851 assert(!sctx
->tess_rings
);
3852 assert(((sctx
->screen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
3854 /* The address must be aligned to 2^19, because the shader only
3855 * receives the high 13 bits.
3857 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3858 SI_RESOURCE_FLAG_32BIT
,
3860 sctx
->screen
->tess_offchip_ring_size
+
3861 sctx
->screen
->tess_factor_ring_size
,
3863 if (!sctx
->tess_rings
)
3866 si_init_config_add_vgt_flush(sctx
);
3868 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3869 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3871 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3872 sctx
->screen
->tess_offchip_ring_size
;
3874 /* Append these registers to the init config state. */
3875 if (sctx
->chip_class
>= GFX7
) {
3876 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3877 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3878 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3880 if (sctx
->chip_class
>= GFX10
)
3881 si_pm4_set_reg(sctx
->init_config
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3882 S_030984_BASE_HI(factor_va
>> 40));
3883 else if (sctx
->chip_class
== GFX9
)
3884 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3885 S_030944_BASE_HI(factor_va
>> 40));
3886 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3887 sctx
->screen
->vgt_hs_offchip_param
);
3889 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3890 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3891 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3893 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3894 sctx
->screen
->vgt_hs_offchip_param
);
3897 /* Flush the context to re-emit the init_config state.
3898 * This is done only once in a lifetime of a context.
3900 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3901 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3902 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3905 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3906 union si_vgt_stages_key key
)
3908 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3909 uint32_t stages
= 0;
3912 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3913 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3916 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3919 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3921 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3922 } else if (key
.u
.gs
) {
3923 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3925 } else if (key
.u
.ngg
) {
3926 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3930 stages
|= S_028B54_PRIMGEN_EN(1) |
3931 S_028B54_NGG_WAVE_ID_EN(key
.u
.streamout
) |
3932 S_028B54_PRIMGEN_PASSTHRU_EN(key
.u
.ngg_passthrough
);
3933 } else if (key
.u
.gs
)
3934 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3936 if (screen
->info
.chip_class
>= GFX9
)
3937 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3939 if (screen
->info
.chip_class
>= GFX10
&& screen
->ge_wave_size
== 32) {
3940 stages
|= S_028B54_HS_W32_EN(1) |
3941 S_028B54_GS_W32_EN(key
.u
.ngg
) | /* legacy GS only supports Wave64 */
3942 S_028B54_VS_W32_EN(1);
3945 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3949 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3950 union si_vgt_stages_key key
)
3952 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3954 if (unlikely(!*pm4
))
3955 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3956 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3959 bool si_update_shaders(struct si_context
*sctx
)
3961 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3962 struct si_compiler_ctx_state compiler_state
;
3963 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3964 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3965 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3966 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3967 union si_vgt_stages_key key
;
3968 unsigned old_spi_shader_col_format
=
3969 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3972 if (!sctx
->compiler
.passes
)
3973 si_init_compiler(sctx
->screen
, &sctx
->compiler
);
3975 compiler_state
.compiler
= &sctx
->compiler
;
3976 compiler_state
.debug
= sctx
->debug
;
3977 compiler_state
.is_debug_context
= sctx
->is_debug
;
3981 if (sctx
->tes_shader
.cso
)
3983 if (sctx
->gs_shader
.cso
)
3988 key
.u
.streamout
= !!si_get_vs(sctx
)->cso
->so
.num_outputs
;
3991 /* Update TCS and TES. */
3992 if (sctx
->tes_shader
.cso
) {
3993 if (!sctx
->tess_rings
) {
3994 si_init_tess_factor_ring(sctx
);
3995 if (!sctx
->tess_rings
)
3999 if (sctx
->tcs_shader
.cso
) {
4000 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
,
4004 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
4006 if (!sctx
->fixed_func_tcs_shader
.cso
) {
4007 sctx
->fixed_func_tcs_shader
.cso
=
4008 si_create_fixed_func_tcs(sctx
);
4009 if (!sctx
->fixed_func_tcs_shader
.cso
)
4013 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
4014 key
, &compiler_state
);
4017 si_pm4_bind_state(sctx
, hs
,
4018 sctx
->fixed_func_tcs_shader
.current
->pm4
);
4021 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
4022 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
4026 if (sctx
->gs_shader
.cso
) {
4028 assert(sctx
->chip_class
<= GFX8
);
4029 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
4030 } else if (key
.u
.ngg
) {
4031 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
4033 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
4037 if (sctx
->chip_class
<= GFX8
)
4038 si_pm4_bind_state(sctx
, ls
, NULL
);
4039 si_pm4_bind_state(sctx
, hs
, NULL
);
4043 if (sctx
->gs_shader
.cso
) {
4044 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
4047 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
4049 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
4051 if (!si_update_gs_ring_buffers(sctx
))
4054 si_pm4_bind_state(sctx
, vs
, NULL
);
4058 si_pm4_bind_state(sctx
, gs
, NULL
);
4059 if (sctx
->chip_class
<= GFX8
)
4060 si_pm4_bind_state(sctx
, es
, NULL
);
4065 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
4066 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
4070 if (!key
.u
.tess
&& !key
.u
.gs
) {
4072 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
4073 si_pm4_bind_state(sctx
, vs
, NULL
);
4075 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
4077 } else if (sctx
->tes_shader
.cso
) {
4078 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
4080 assert(sctx
->gs_shader
.cso
);
4081 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
4085 /* This must be done after the shader variant is selected. */
4087 key
.u
.ngg_passthrough
= gfx10_is_ngg_passthrough(si_get_vs(sctx
)->current
);
4089 si_update_vgt_shader_config(sctx
, key
);
4091 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
4092 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
4094 if (sctx
->ps_shader
.cso
) {
4095 unsigned db_shader_control
;
4097 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
4100 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
4103 sctx
->ps_shader
.cso
->db_shader_control
|
4104 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
4106 if (si_pm4_state_changed(sctx
, ps
) ||
4107 si_pm4_state_changed(sctx
, vs
) ||
4108 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
4109 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
4110 sctx
->flatshade
!= rs
->flatshade
) {
4111 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
4112 sctx
->flatshade
= rs
->flatshade
;
4113 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
4116 if (sctx
->screen
->info
.rbplus_allowed
&&
4117 si_pm4_state_changed(sctx
, ps
) &&
4119 old_spi_shader_col_format
!=
4120 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
4121 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
4123 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
4124 sctx
->ps_db_shader_control
= db_shader_control
;
4125 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4126 if (sctx
->screen
->dpbb_allowed
)
4127 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
4130 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
4131 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
4132 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
4134 if (sctx
->chip_class
== GFX6
)
4135 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4137 if (sctx
->framebuffer
.nr_samples
<= 1)
4138 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
4142 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
4143 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
4144 si_pm4_state_enabled_and_changed(sctx
, es
) ||
4145 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
4146 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
4147 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
4148 if (!si_update_spi_tmpring_size(sctx
))
4152 if (sctx
->chip_class
>= GFX7
) {
4153 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
4154 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
4155 else if (!sctx
->queued
.named
.ls
)
4156 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
4158 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
4159 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
4160 else if (!sctx
->queued
.named
.hs
)
4161 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
4163 if (si_pm4_state_enabled_and_changed(sctx
, es
))
4164 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
4165 else if (!sctx
->queued
.named
.es
)
4166 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
4168 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
4169 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
4170 else if (!sctx
->queued
.named
.gs
)
4171 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
4173 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
4174 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
4175 else if (!sctx
->queued
.named
.vs
)
4176 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
4178 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
4179 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
4180 else if (!sctx
->queued
.named
.ps
)
4181 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
4184 sctx
->do_update_shaders
= false;
4188 static void si_emit_scratch_state(struct si_context
*sctx
)
4190 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4192 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
4193 sctx
->spi_tmpring_size
);
4195 if (sctx
->scratch_buffer
) {
4196 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
4197 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
4198 RADEON_PRIO_SCRATCH_BUFFER
);
4202 void si_init_shader_functions(struct si_context
*sctx
)
4204 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
4205 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
4207 sctx
->b
.create_vs_state
= si_create_shader_selector
;
4208 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
4209 sctx
->b
.create_tes_state
= si_create_shader_selector
;
4210 sctx
->b
.create_gs_state
= si_create_shader_selector
;
4211 sctx
->b
.create_fs_state
= si_create_shader_selector
;
4213 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
4214 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
4215 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
4216 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
4217 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
4219 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
4220 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
4221 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
4222 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
4223 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;