radeonsi/gfx10: remove incorrect ngg/pos_writes_edgeflag variables
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 void *si_get_ir_binary(struct si_shader_selector *sel, bool ngg, bool es)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 /* These settings affect the compilation, but they are not derived
68 * from the input shader IR.
69 */
70 unsigned shader_variant_flags = 0;
71
72 if (ngg)
73 shader_variant_flags |= 1 << 0;
74 if (sel->nir)
75 shader_variant_flags |= 1 << 1;
76 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
77 shader_variant_flags |= 1 << 2;
78 if (sel->force_correct_derivs_after_kill)
79 shader_variant_flags |= 1 << 3;
80
81 unsigned size = 4 + 4 + ir_size + sizeof(sel->so);
82 char *result = (char*)MALLOC(size);
83 if (!result)
84 return NULL;
85
86 ((uint32_t*)result)[0] = size;
87 ((uint32_t*)result)[1] = shader_variant_flags;
88 memcpy(result + 8, ir_binary, ir_size);
89 memcpy(result + 8 + ir_size, &sel->so, sizeof(sel->so));
90
91 if (sel->nir)
92 blob_finish(&blob);
93
94 return result;
95 }
96
97 /** Copy "data" to "ptr" and return the next dword following copied data. */
98 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
99 {
100 /* data may be NULL if size == 0 */
101 if (size)
102 memcpy(ptr, data, size);
103 ptr += DIV_ROUND_UP(size, 4);
104 return ptr;
105 }
106
107 /** Read data from "ptr". Return the next dword following the data. */
108 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
109 {
110 memcpy(data, ptr, size);
111 ptr += DIV_ROUND_UP(size, 4);
112 return ptr;
113 }
114
115 /**
116 * Write the size as uint followed by the data. Return the next dword
117 * following the copied data.
118 */
119 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
120 {
121 *ptr++ = size;
122 return write_data(ptr, data, size);
123 }
124
125 /**
126 * Read the size as uint followed by the data. Return both via parameters.
127 * Return the next dword following the data.
128 */
129 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
130 {
131 *size = *ptr++;
132 assert(*data == NULL);
133 if (!*size)
134 return ptr;
135 *data = malloc(*size);
136 return read_data(ptr, *data, *size);
137 }
138
139 /**
140 * Return the shader binary in a buffer. The first 4 bytes contain its size
141 * as integer.
142 */
143 static void *si_get_shader_binary(struct si_shader *shader)
144 {
145 /* There is always a size of data followed by the data itself. */
146 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
147 strlen(shader->binary.llvm_ir_string) + 1 : 0;
148
149 /* Refuse to allocate overly large buffers and guard against integer
150 * overflow. */
151 if (shader->binary.elf_size > UINT_MAX / 4 ||
152 llvm_ir_size > UINT_MAX / 4)
153 return NULL;
154
155 unsigned size =
156 4 + /* total size */
157 4 + /* CRC32 of the data below */
158 align(sizeof(shader->config), 4) +
159 align(sizeof(shader->info), 4) +
160 4 + align(shader->binary.elf_size, 4) +
161 4 + align(llvm_ir_size, 4);
162 void *buffer = CALLOC(1, size);
163 uint32_t *ptr = (uint32_t*)buffer;
164
165 if (!buffer)
166 return NULL;
167
168 *ptr++ = size;
169 ptr++; /* CRC32 is calculated at the end. */
170
171 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
172 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
173 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
174 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
175 assert((char *)ptr - (char *)buffer == size);
176
177 /* Compute CRC32. */
178 ptr = (uint32_t*)buffer;
179 ptr++;
180 *ptr = util_hash_crc32(ptr + 1, size - 8);
181
182 return buffer;
183 }
184
185 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
186 {
187 uint32_t *ptr = (uint32_t*)binary;
188 uint32_t size = *ptr++;
189 uint32_t crc32 = *ptr++;
190 unsigned chunk_size;
191 unsigned elf_size;
192
193 if (util_hash_crc32(ptr, size - 8) != crc32) {
194 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
195 return false;
196 }
197
198 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
199 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
200 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
201 &elf_size);
202 shader->binary.elf_size = elf_size;
203 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
204
205 return true;
206 }
207
208 /**
209 * Insert a shader into the cache. It's assumed the shader is not in the cache.
210 * Use si_shader_cache_load_shader before calling this.
211 *
212 * Returns false on failure, in which case the ir_binary should be freed.
213 */
214 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
215 struct si_shader *shader,
216 bool insert_into_disk_cache)
217 {
218 void *hw_binary;
219 struct hash_entry *entry;
220 uint8_t key[CACHE_KEY_SIZE];
221
222 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
223 if (entry)
224 return false; /* already added */
225
226 hw_binary = si_get_shader_binary(shader);
227 if (!hw_binary)
228 return false;
229
230 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
231 hw_binary) == NULL) {
232 FREE(hw_binary);
233 return false;
234 }
235
236 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
237 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
238 *((uint32_t *)ir_binary), key);
239 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
240 *((uint32_t *) hw_binary), NULL);
241 }
242
243 return true;
244 }
245
246 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
247 struct si_shader *shader)
248 {
249 struct hash_entry *entry =
250 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
251 if (!entry) {
252 if (sscreen->disk_shader_cache) {
253 unsigned char sha1[CACHE_KEY_SIZE];
254 size_t tg_size = *((uint32_t *) ir_binary);
255
256 disk_cache_compute_key(sscreen->disk_shader_cache,
257 ir_binary, tg_size, sha1);
258
259 size_t binary_size;
260 uint8_t *buffer =
261 disk_cache_get(sscreen->disk_shader_cache,
262 sha1, &binary_size);
263 if (!buffer)
264 return false;
265
266 if (binary_size < sizeof(uint32_t) ||
267 *((uint32_t*)buffer) != binary_size) {
268 /* Something has gone wrong discard the item
269 * from the cache and rebuild/link from
270 * source.
271 */
272 assert(!"Invalid radeonsi shader disk cache "
273 "item!");
274
275 disk_cache_remove(sscreen->disk_shader_cache,
276 sha1);
277 free(buffer);
278
279 return false;
280 }
281
282 if (!si_load_shader_binary(shader, buffer)) {
283 free(buffer);
284 return false;
285 }
286 free(buffer);
287
288 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
289 shader, false))
290 FREE(ir_binary);
291 } else {
292 return false;
293 }
294 } else {
295 if (si_load_shader_binary(shader, entry->data))
296 FREE(ir_binary);
297 else
298 return false;
299 }
300 p_atomic_inc(&sscreen->num_shader_cache_hits);
301 return true;
302 }
303
304 static uint32_t si_shader_cache_key_hash(const void *key)
305 {
306 /* The first dword is the key size. */
307 return util_hash_crc32(key, *(uint32_t*)key);
308 }
309
310 static bool si_shader_cache_key_equals(const void *a, const void *b)
311 {
312 uint32_t *keya = (uint32_t*)a;
313 uint32_t *keyb = (uint32_t*)b;
314
315 /* The first dword is the key size. */
316 if (*keya != *keyb)
317 return false;
318
319 return memcmp(keya, keyb, *keya) == 0;
320 }
321
322 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
323 {
324 FREE((void*)entry->key);
325 FREE(entry->data);
326 }
327
328 bool si_init_shader_cache(struct si_screen *sscreen)
329 {
330 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
331 sscreen->shader_cache =
332 _mesa_hash_table_create(NULL,
333 si_shader_cache_key_hash,
334 si_shader_cache_key_equals);
335
336 return sscreen->shader_cache != NULL;
337 }
338
339 void si_destroy_shader_cache(struct si_screen *sscreen)
340 {
341 if (sscreen->shader_cache)
342 _mesa_hash_table_destroy(sscreen->shader_cache,
343 si_destroy_shader_cache_entry);
344 mtx_destroy(&sscreen->shader_cache_mutex);
345 }
346
347 /* SHADER STATES */
348
349 static void si_set_tesseval_regs(struct si_screen *sscreen,
350 const struct si_shader_selector *tes,
351 struct si_pm4_state *pm4)
352 {
353 const struct tgsi_shader_info *info = &tes->info;
354 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
355 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
356 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
357 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
358 unsigned type, partitioning, topology, distribution_mode;
359
360 switch (tes_prim_mode) {
361 case PIPE_PRIM_LINES:
362 type = V_028B6C_TESS_ISOLINE;
363 break;
364 case PIPE_PRIM_TRIANGLES:
365 type = V_028B6C_TESS_TRIANGLE;
366 break;
367 case PIPE_PRIM_QUADS:
368 type = V_028B6C_TESS_QUAD;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 switch (tes_spacing) {
376 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
377 partitioning = V_028B6C_PART_FRAC_ODD;
378 break;
379 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
380 partitioning = V_028B6C_PART_FRAC_EVEN;
381 break;
382 case PIPE_TESS_SPACING_EQUAL:
383 partitioning = V_028B6C_PART_INTEGER;
384 break;
385 default:
386 assert(0);
387 return;
388 }
389
390 if (tes_point_mode)
391 topology = V_028B6C_OUTPUT_POINT;
392 else if (tes_prim_mode == PIPE_PRIM_LINES)
393 topology = V_028B6C_OUTPUT_LINE;
394 else if (tes_vertex_order_cw)
395 /* for some reason, this must be the other way around */
396 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
397 else
398 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
399
400 if (sscreen->info.has_distributed_tess) {
401 if (sscreen->info.family == CHIP_FIJI ||
402 sscreen->info.family >= CHIP_POLARIS10)
403 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
404 else
405 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
406 } else
407 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
408
409 assert(pm4->shader);
410 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
411 S_028B6C_PARTITIONING(partitioning) |
412 S_028B6C_TOPOLOGY(topology) |
413 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
414 }
415
416 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
417 * whether the "fractional odd" tessellation spacing is used.
418 *
419 * Possible VGT configurations and which state should set the register:
420 *
421 * Reg set in | VGT shader configuration | Value
422 * ------------------------------------------------------
423 * VS as VS | VS | 30
424 * VS as ES | ES -> GS -> VS | 30
425 * TES as VS | LS -> HS -> VS | 14 or 30
426 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
427 *
428 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
429 */
430 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
431 struct si_shader_selector *sel,
432 struct si_shader *shader,
433 struct si_pm4_state *pm4)
434 {
435 unsigned type = sel->type;
436
437 if (sscreen->info.family < CHIP_POLARIS10 ||
438 sscreen->info.chip_class >= GFX10)
439 return;
440
441 /* VS as VS, or VS as ES: */
442 if ((type == PIPE_SHADER_VERTEX &&
443 (!shader ||
444 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
445 /* TES as VS, or TES as ES: */
446 type == PIPE_SHADER_TESS_EVAL) {
447 unsigned vtx_reuse_depth = 30;
448
449 if (type == PIPE_SHADER_TESS_EVAL &&
450 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
451 PIPE_TESS_SPACING_FRACTIONAL_ODD)
452 vtx_reuse_depth = 14;
453
454 assert(pm4->shader);
455 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
456 }
457 }
458
459 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
460 {
461 if (shader->pm4)
462 si_pm4_clear_state(shader->pm4);
463 else
464 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
465
466 if (shader->pm4) {
467 shader->pm4->shader = shader;
468 return shader->pm4;
469 } else {
470 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
471 return NULL;
472 }
473 }
474
475 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
476 {
477 /* Add the pointer to VBO descriptors. */
478 return num_always_on_user_sgprs + 1;
479 }
480
481 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
482 {
483 struct si_pm4_state *pm4;
484 unsigned vgpr_comp_cnt;
485 uint64_t va;
486
487 assert(sscreen->info.chip_class <= GFX8);
488
489 pm4 = si_get_shader_pm4_state(shader);
490 if (!pm4)
491 return;
492
493 va = shader->bo->gpu_address;
494 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
495
496 /* We need at least 2 components for LS.
497 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
498 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
499 */
500 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
501
502 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
503 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
504
505 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
506 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
507 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
508 S_00B528_DX10_CLAMP(1) |
509 S_00B528_FLOAT_MODE(shader->config.float_mode);
510 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
511 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
512 }
513
514 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
515 {
516 struct si_pm4_state *pm4;
517 uint64_t va;
518 unsigned ls_vgpr_comp_cnt = 0;
519
520 pm4 = si_get_shader_pm4_state(shader);
521 if (!pm4)
522 return;
523
524 va = shader->bo->gpu_address;
525 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
526
527 if (sscreen->info.chip_class >= GFX9) {
528 if (sscreen->info.chip_class >= GFX10) {
529 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
530 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
531 } else {
532 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
533 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
534 }
535
536 /* We need at least 2 components for LS.
537 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
538 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
539 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
540 * be loaded.
541 */
542 ls_vgpr_comp_cnt = 1;
543 if (shader->info.uses_instanceid) {
544 if (sscreen->info.chip_class >= GFX10)
545 ls_vgpr_comp_cnt = 3;
546 else
547 ls_vgpr_comp_cnt = 2;
548 }
549
550 unsigned num_user_sgprs =
551 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
552
553 shader->config.rsrc2 =
554 S_00B42C_USER_SGPR(num_user_sgprs) |
555 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
556
557 if (sscreen->info.chip_class >= GFX10)
558 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
559 else
560 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
561 } else {
562 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
563 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
564
565 shader->config.rsrc2 =
566 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
567 S_00B42C_OC_LDS_EN(1) |
568 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
569 }
570
571 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
572 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
573 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
574 (sscreen->info.chip_class <= GFX9 ?
575 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
576 S_00B428_DX10_CLAMP(1) |
577 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
578 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
579 S_00B428_FLOAT_MODE(shader->config.float_mode) |
580 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
581
582 if (sscreen->info.chip_class <= GFX8) {
583 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
584 shader->config.rsrc2);
585 }
586 }
587
588 static void si_emit_shader_es(struct si_context *sctx)
589 {
590 struct si_shader *shader = sctx->queued.named.es->shader;
591 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
592
593 if (!shader)
594 return;
595
596 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
597 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
598 shader->selector->esgs_itemsize / 4);
599
600 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
601 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
602 SI_TRACKED_VGT_TF_PARAM,
603 shader->vgt_tf_param);
604
605 if (shader->vgt_vertex_reuse_block_cntl)
606 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
607 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
608 shader->vgt_vertex_reuse_block_cntl);
609
610 if (initial_cdw != sctx->gfx_cs->current.cdw)
611 sctx->context_roll = true;
612 }
613
614 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
615 {
616 struct si_pm4_state *pm4;
617 unsigned num_user_sgprs;
618 unsigned vgpr_comp_cnt;
619 uint64_t va;
620 unsigned oc_lds_en;
621
622 assert(sscreen->info.chip_class <= GFX8);
623
624 pm4 = si_get_shader_pm4_state(shader);
625 if (!pm4)
626 return;
627
628 pm4->atom.emit = si_emit_shader_es;
629 va = shader->bo->gpu_address;
630 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
631
632 if (shader->selector->type == PIPE_SHADER_VERTEX) {
633 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
634 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
635 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
636 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
637 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
638 num_user_sgprs = SI_TES_NUM_USER_SGPR;
639 } else
640 unreachable("invalid shader selector type");
641
642 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
643
644 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
645 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
646 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
647 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
648 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
649 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
650 S_00B328_DX10_CLAMP(1) |
651 S_00B328_FLOAT_MODE(shader->config.float_mode));
652 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
653 S_00B32C_USER_SGPR(num_user_sgprs) |
654 S_00B32C_OC_LDS_EN(oc_lds_en) |
655 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
656
657 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
658 si_set_tesseval_regs(sscreen, shader->selector, pm4);
659
660 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
661 }
662
663 void gfx9_get_gs_info(struct si_shader_selector *es,
664 struct si_shader_selector *gs,
665 struct gfx9_gs_info *out)
666 {
667 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
668 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
669 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
670 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
671
672 /* All these are in dwords: */
673 /* We can't allow using the whole LDS, because GS waves compete with
674 * other shader stages for LDS space. */
675 const unsigned max_lds_size = 8 * 1024;
676 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
677 unsigned esgs_lds_size;
678
679 /* All these are per subgroup: */
680 const unsigned max_out_prims = 32 * 1024;
681 const unsigned max_es_verts = 255;
682 const unsigned ideal_gs_prims = 64;
683 unsigned max_gs_prims, gs_prims;
684 unsigned min_es_verts, es_verts, worst_case_es_verts;
685
686 if (uses_adjacency || gs_num_invocations > 1)
687 max_gs_prims = 127 / gs_num_invocations;
688 else
689 max_gs_prims = 255;
690
691 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
692 * Make sure we don't go over the maximum value.
693 */
694 if (gs->gs_max_out_vertices > 0) {
695 max_gs_prims = MIN2(max_gs_prims,
696 max_out_prims /
697 (gs->gs_max_out_vertices * gs_num_invocations));
698 }
699 assert(max_gs_prims > 0);
700
701 /* If the primitive has adjacency, halve the number of vertices
702 * that will be reused in multiple primitives.
703 */
704 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
705
706 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
707 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
708
709 /* Compute ESGS LDS size based on the worst case number of ES vertices
710 * needed to create the target number of GS prims per subgroup.
711 */
712 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
713
714 /* If total LDS usage is too big, refactor partitions based on ratio
715 * of ESGS item sizes.
716 */
717 if (esgs_lds_size > max_lds_size) {
718 /* Our target GS Prims Per Subgroup was too large. Calculate
719 * the maximum number of GS Prims Per Subgroup that will fit
720 * into LDS, capped by the maximum that the hardware can support.
721 */
722 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
723 max_gs_prims);
724 assert(gs_prims > 0);
725 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
726 max_es_verts);
727
728 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
729 assert(esgs_lds_size <= max_lds_size);
730 }
731
732 /* Now calculate remaining ESGS information. */
733 if (esgs_lds_size)
734 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
735 else
736 es_verts = max_es_verts;
737
738 /* Vertices for adjacency primitives are not always reused, so restore
739 * it for ES_VERTS_PER_SUBGRP.
740 */
741 min_es_verts = gs->gs_input_verts_per_prim;
742
743 /* For normal primitives, the VGT only checks if they are past the ES
744 * verts per subgroup after allocating a full GS primitive and if they
745 * are, kick off a new subgroup. But if those additional ES verts are
746 * unique (e.g. not reused) we need to make sure there is enough LDS
747 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
748 */
749 es_verts -= min_es_verts - 1;
750
751 out->es_verts_per_subgroup = es_verts;
752 out->gs_prims_per_subgroup = gs_prims;
753 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
754 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
755 gs->gs_max_out_vertices;
756 out->esgs_ring_size = 4 * esgs_lds_size;
757
758 assert(out->max_prims_per_subgroup <= max_out_prims);
759 }
760
761 static void si_emit_shader_gs(struct si_context *sctx)
762 {
763 struct si_shader *shader = sctx->queued.named.gs->shader;
764 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
765
766 if (!shader)
767 return;
768
769 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
770 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
771 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
772 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
773 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
774 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
775 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
776
777 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
778 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
779 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
780 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
781
782 /* R_028B38_VGT_GS_MAX_VERT_OUT */
783 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
784 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
785 shader->ctx_reg.gs.vgt_gs_max_vert_out);
786
787 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
788 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
789 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
790 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
791 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
792 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
793 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
794 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
795
796 /* R_028B90_VGT_GS_INSTANCE_CNT */
797 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
798 SI_TRACKED_VGT_GS_INSTANCE_CNT,
799 shader->ctx_reg.gs.vgt_gs_instance_cnt);
800
801 if (sctx->chip_class >= GFX9) {
802 /* R_028A44_VGT_GS_ONCHIP_CNTL */
803 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
804 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
805 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
806 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
807 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
808 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
809 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
810 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
811 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
812 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
813 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
814
815 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
816 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
817 SI_TRACKED_VGT_TF_PARAM,
818 shader->vgt_tf_param);
819 if (shader->vgt_vertex_reuse_block_cntl)
820 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
821 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
822 shader->vgt_vertex_reuse_block_cntl);
823 }
824
825 if (initial_cdw != sctx->gfx_cs->current.cdw)
826 sctx->context_roll = true;
827 }
828
829 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
830 {
831 struct si_shader_selector *sel = shader->selector;
832 const ubyte *num_components = sel->info.num_stream_output_components;
833 unsigned gs_num_invocations = sel->gs_num_invocations;
834 struct si_pm4_state *pm4;
835 uint64_t va;
836 unsigned max_stream = sel->max_gs_stream;
837 unsigned offset;
838
839 pm4 = si_get_shader_pm4_state(shader);
840 if (!pm4)
841 return;
842
843 pm4->atom.emit = si_emit_shader_gs;
844
845 offset = num_components[0] * sel->gs_max_out_vertices;
846 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
847
848 if (max_stream >= 1)
849 offset += num_components[1] * sel->gs_max_out_vertices;
850 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
851
852 if (max_stream >= 2)
853 offset += num_components[2] * sel->gs_max_out_vertices;
854 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
855
856 if (max_stream >= 3)
857 offset += num_components[3] * sel->gs_max_out_vertices;
858 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
859
860 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
861 assert(offset < (1 << 15));
862
863 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
864
865 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
866 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
867 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
868 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
869
870 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
871 S_028B90_ENABLE(gs_num_invocations > 0);
872
873 va = shader->bo->gpu_address;
874 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
875
876 if (sscreen->info.chip_class >= GFX9) {
877 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
878 unsigned es_type = shader->key.part.gs.es->type;
879 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
880
881 if (es_type == PIPE_SHADER_VERTEX) {
882 /* GFX10: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 or InstanceID)
883 * GFX9: (VertexID, InstanceID / StepRate0, ...)
884 */
885 if (sscreen->info.chip_class >= GFX10)
886 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
887 else
888 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
889 } else if (es_type == PIPE_SHADER_TESS_EVAL)
890 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
891 else
892 unreachable("invalid shader selector type");
893
894 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
895 * VGPR[0:4] are always loaded.
896 */
897 if (sel->info.uses_invocationid)
898 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
899 else if (sel->info.uses_primid)
900 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
901 else if (input_prim >= PIPE_PRIM_TRIANGLES)
902 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
903 else
904 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
905
906 unsigned num_user_sgprs;
907 if (es_type == PIPE_SHADER_VERTEX)
908 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
909 else
910 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
911
912 if (sscreen->info.chip_class >= GFX10) {
913 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
914 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
915 } else {
916 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
917 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
918 }
919
920 uint32_t rsrc1 =
921 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
922 S_00B228_DX10_CLAMP(1) |
923 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
924 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
925 S_00B228_FLOAT_MODE(shader->config.float_mode) |
926 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
927 uint32_t rsrc2 =
928 S_00B22C_USER_SGPR(num_user_sgprs) |
929 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
930 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
931 S_00B22C_LDS_SIZE(shader->config.lds_size) |
932 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
933
934 if (sscreen->info.chip_class >= GFX10) {
935 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
936 } else {
937 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
938 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
939 }
940
941 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
942 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
943
944 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
945 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
946 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
947 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
948 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
949 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
950 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
951 shader->key.part.gs.es->esgs_itemsize / 4;
952
953 if (es_type == PIPE_SHADER_TESS_EVAL)
954 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
955
956 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
957 NULL, pm4);
958 } else {
959 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
960 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
961
962 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
963 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
964 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
965 S_00B228_DX10_CLAMP(1) |
966 S_00B228_FLOAT_MODE(shader->config.float_mode));
967 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
968 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
969 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
970 }
971 }
972
973 /* Common tail code for NGG primitive shaders. */
974 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
975 struct si_shader *shader,
976 unsigned initial_cdw)
977 {
978 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
979 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
980 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
981 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
982 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
983 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
984 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
985 SI_TRACKED_VGT_PRIMITIVEID_EN,
986 shader->ctx_reg.ngg.vgt_primitiveid_en);
987 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
988 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
989 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
990 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
991 SI_TRACKED_VGT_GS_INSTANCE_CNT,
992 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
993 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
994 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
995 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
996 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
997 SI_TRACKED_SPI_VS_OUT_CONFIG,
998 shader->ctx_reg.ngg.spi_vs_out_config);
999 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
1000 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
1001 shader->ctx_reg.ngg.spi_shader_idx_format,
1002 shader->ctx_reg.ngg.spi_shader_pos_format);
1003 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1004 SI_TRACKED_PA_CL_VTE_CNTL,
1005 shader->ctx_reg.ngg.pa_cl_vte_cntl);
1006 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1007 SI_TRACKED_PA_CL_NGG_CNTL,
1008 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1009
1010 if (initial_cdw != sctx->gfx_cs->current.cdw)
1011 sctx->context_roll = true;
1012 }
1013
1014 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1015 {
1016 struct si_shader *shader = sctx->queued.named.gs->shader;
1017 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1018
1019 if (!shader)
1020 return;
1021
1022 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1023 }
1024
1025 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1026 {
1027 struct si_shader *shader = sctx->queued.named.gs->shader;
1028 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1029
1030 if (!shader)
1031 return;
1032
1033 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1034 SI_TRACKED_VGT_TF_PARAM,
1035 shader->vgt_tf_param);
1036
1037 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1038 }
1039
1040 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1041 {
1042 struct si_shader *shader = sctx->queued.named.gs->shader;
1043 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1044
1045 if (!shader)
1046 return;
1047
1048 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1049 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1050 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1051
1052 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1053 }
1054
1055 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1056 {
1057 struct si_shader *shader = sctx->queued.named.gs->shader;
1058 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1059
1060 if (!shader)
1061 return;
1062
1063 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1064 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1065 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1066 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1067 SI_TRACKED_VGT_TF_PARAM,
1068 shader->vgt_tf_param);
1069
1070 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1071 }
1072
1073 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1074 {
1075 if (gs->type == PIPE_SHADER_GEOMETRY)
1076 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1077
1078 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1079 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1080 return PIPE_PRIM_POINTS;
1081 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1082 return PIPE_PRIM_LINES;
1083 return PIPE_PRIM_TRIANGLES;
1084 }
1085
1086 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1087 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1088 }
1089
1090 /**
1091 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1092 * in NGG mode.
1093 */
1094 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1095 {
1096 const struct si_shader_selector *gs_sel = shader->selector;
1097 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1098 enum pipe_shader_type gs_type = shader->selector->type;
1099 const struct si_shader_selector *es_sel =
1100 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1101 const struct tgsi_shader_info *es_info = &es_sel->info;
1102 enum pipe_shader_type es_type = es_sel->type;
1103 unsigned num_user_sgprs;
1104 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1105 uint64_t va;
1106 unsigned window_space =
1107 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1108 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1109 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1110 unsigned input_prim = si_get_input_prim(gs_sel);
1111 bool break_wave_at_eoi = false;
1112 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1113 if (!pm4)
1114 return;
1115
1116 if (es_type == PIPE_SHADER_TESS_EVAL) {
1117 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1118 : gfx10_emit_shader_ngg_tess_nogs;
1119 } else {
1120 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1121 : gfx10_emit_shader_ngg_notess_nogs;
1122 }
1123
1124 va = shader->bo->gpu_address;
1125 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1126
1127 if (es_type == PIPE_SHADER_VERTEX) {
1128 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1129 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1130
1131 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1132 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1133 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1134 } else {
1135 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1136 }
1137 } else {
1138 assert(es_type == PIPE_SHADER_TESS_EVAL);
1139 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1140 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1141
1142 if (es_enable_prim_id || gs_info->uses_primid)
1143 break_wave_at_eoi = true;
1144 }
1145
1146 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1147 * VGPR[0:4] are always loaded.
1148 *
1149 * Vertex shaders always need to load VGPR3, because they need to
1150 * pass edge flags for decomposed primitives (such as quads) to the PA
1151 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1152 */
1153 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1154 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1155 else if (gs_info->uses_primid)
1156 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1157 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1158 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1159 else
1160 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1161
1162 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1163 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1164 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1165 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1166 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1167 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1168 S_00B228_DX10_CLAMP(1) |
1169 S_00B228_MEM_ORDERED(1) |
1170 S_00B228_WGP_MODE(1) |
1171 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1172 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1173 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1174 S_00B22C_USER_SGPR(num_user_sgprs) |
1175 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1176 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1177 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1178 S_00B22C_LDS_SIZE(shader->config.lds_size));
1179
1180 nparams = MAX2(shader->info.nr_param_exports, 1);
1181 shader->ctx_reg.ngg.spi_vs_out_config =
1182 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1183 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1184
1185 shader->ctx_reg.ngg.spi_shader_idx_format =
1186 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1187 shader->ctx_reg.ngg.spi_shader_pos_format =
1188 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1189 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1190 V_02870C_SPI_SHADER_4COMP :
1191 V_02870C_SPI_SHADER_NONE) |
1192 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1193 V_02870C_SPI_SHADER_4COMP :
1194 V_02870C_SPI_SHADER_NONE) |
1195 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1196 V_02870C_SPI_SHADER_4COMP :
1197 V_02870C_SPI_SHADER_NONE);
1198
1199 shader->ctx_reg.ngg.vgt_primitiveid_en =
1200 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1201 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1202
1203 if (gs_type == PIPE_SHADER_GEOMETRY) {
1204 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1205 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1206 } else {
1207 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1208 }
1209
1210 if (es_type == PIPE_SHADER_TESS_EVAL)
1211 si_set_tesseval_regs(sscreen, es_sel, pm4);
1212
1213 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1214 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1215 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1216 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1217 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1218 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1219 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1220 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1221 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1222 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1223 S_028B90_CNT(gs_num_invocations) |
1224 S_028B90_ENABLE(gs_num_invocations > 1) |
1225 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1226 shader->ngg.max_vert_out_per_gs_instance);
1227
1228 /* Always output hw-generated edge flags and pass them via the prim
1229 * export to prevent drawing lines on internal edges of decomposed
1230 * primitives (such as quads) with polygon mode = lines. Only VS needs
1231 * this.
1232 */
1233 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1234 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1235
1236 shader->ge_cntl =
1237 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1238 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1239 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1240
1241 /* Bug workaround for a possible hang with non-tessellation cases.
1242 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1243 *
1244 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1245 */
1246 if ((sscreen->info.family == CHIP_NAVI10 ||
1247 sscreen->info.family == CHIP_NAVI12 ||
1248 sscreen->info.family == CHIP_NAVI14) &&
1249 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1250 shader->ngg.hw_max_esverts != 256) {
1251 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1252
1253 if (shader->ngg.hw_max_esverts > 5) {
1254 shader->ge_cntl |=
1255 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1256 }
1257 }
1258
1259 if (window_space) {
1260 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1261 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1262 } else {
1263 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1264 S_028818_VTX_W0_FMT(1) |
1265 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1266 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1267 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1268 }
1269 }
1270
1271 static void si_emit_shader_vs(struct si_context *sctx)
1272 {
1273 struct si_shader *shader = sctx->queued.named.vs->shader;
1274 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1275
1276 if (!shader)
1277 return;
1278
1279 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1280 SI_TRACKED_VGT_GS_MODE,
1281 shader->ctx_reg.vs.vgt_gs_mode);
1282 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1283 SI_TRACKED_VGT_PRIMITIVEID_EN,
1284 shader->ctx_reg.vs.vgt_primitiveid_en);
1285
1286 if (sctx->chip_class <= GFX8) {
1287 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1288 SI_TRACKED_VGT_REUSE_OFF,
1289 shader->ctx_reg.vs.vgt_reuse_off);
1290 }
1291
1292 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1293 SI_TRACKED_SPI_VS_OUT_CONFIG,
1294 shader->ctx_reg.vs.spi_vs_out_config);
1295
1296 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1297 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1298 shader->ctx_reg.vs.spi_shader_pos_format);
1299
1300 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1301 SI_TRACKED_PA_CL_VTE_CNTL,
1302 shader->ctx_reg.vs.pa_cl_vte_cntl);
1303
1304 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1305 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1306 SI_TRACKED_VGT_TF_PARAM,
1307 shader->vgt_tf_param);
1308
1309 if (shader->vgt_vertex_reuse_block_cntl)
1310 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1311 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1312 shader->vgt_vertex_reuse_block_cntl);
1313
1314 if (initial_cdw != sctx->gfx_cs->current.cdw)
1315 sctx->context_roll = true;
1316
1317 /* Required programming for tessellation. (legacy pipeline only) */
1318 if (sctx->chip_class == GFX10 &&
1319 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1320 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1321 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1322 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1323 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1324 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1325 }
1326 }
1327
1328 /**
1329 * Compute the state for \p shader, which will run as a vertex shader on the
1330 * hardware.
1331 *
1332 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1333 * is the copy shader.
1334 */
1335 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1336 struct si_shader_selector *gs)
1337 {
1338 const struct tgsi_shader_info *info = &shader->selector->info;
1339 struct si_pm4_state *pm4;
1340 unsigned num_user_sgprs, vgpr_comp_cnt;
1341 uint64_t va;
1342 unsigned nparams, oc_lds_en;
1343 unsigned window_space =
1344 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1345 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1346
1347 pm4 = si_get_shader_pm4_state(shader);
1348 if (!pm4)
1349 return;
1350
1351 pm4->atom.emit = si_emit_shader_vs;
1352
1353 /* We always write VGT_GS_MODE in the VS state, because every switch
1354 * between different shader pipelines involving a different GS or no
1355 * GS at all involves a switch of the VS (different GS use different
1356 * copy shaders). On the other hand, when the API switches from a GS to
1357 * no GS and then back to the same GS used originally, the GS state is
1358 * not sent again.
1359 */
1360 if (!gs) {
1361 unsigned mode = V_028A40_GS_OFF;
1362
1363 /* PrimID needs GS scenario A. */
1364 if (enable_prim_id)
1365 mode = V_028A40_GS_SCENARIO_A;
1366
1367 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1368 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1369 } else {
1370 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1371 sscreen->info.chip_class);
1372 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1373 }
1374
1375 if (sscreen->info.chip_class <= GFX8) {
1376 /* Reuse needs to be set off if we write oViewport. */
1377 shader->ctx_reg.vs.vgt_reuse_off =
1378 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1379 }
1380
1381 va = shader->bo->gpu_address;
1382 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1383
1384 if (gs) {
1385 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1386 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1387 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1388 if (sscreen->info.chip_class >= GFX10) {
1389 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
1390 } else {
1391 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1392 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1393 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1394 */
1395 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1396 }
1397
1398 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1399 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1400 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1401 } else {
1402 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1403 }
1404 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1405 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1406 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1407 } else
1408 unreachable("invalid shader selector type");
1409
1410 /* VS is required to export at least one param. */
1411 nparams = MAX2(shader->info.nr_param_exports, 1);
1412 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1413
1414 if (sscreen->info.chip_class >= GFX10) {
1415 shader->ctx_reg.vs.spi_vs_out_config |=
1416 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1417 }
1418
1419 shader->ctx_reg.vs.spi_shader_pos_format =
1420 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1421 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1422 V_02870C_SPI_SHADER_4COMP :
1423 V_02870C_SPI_SHADER_NONE) |
1424 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1425 V_02870C_SPI_SHADER_4COMP :
1426 V_02870C_SPI_SHADER_NONE) |
1427 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1428 V_02870C_SPI_SHADER_4COMP :
1429 V_02870C_SPI_SHADER_NONE);
1430
1431 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1432
1433 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1434 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1435
1436 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1437 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1438 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1439 S_00B128_DX10_CLAMP(1) |
1440 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1441 S_00B128_FLOAT_MODE(shader->config.float_mode);
1442 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1443 S_00B12C_OC_LDS_EN(oc_lds_en) |
1444 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1445
1446 if (sscreen->info.chip_class <= GFX9)
1447 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1448
1449 if (!sscreen->use_ngg_streamout) {
1450 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1451 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1452 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1453 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1454 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1455 }
1456
1457 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1458 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1459
1460 if (window_space)
1461 shader->ctx_reg.vs.pa_cl_vte_cntl =
1462 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1463 else
1464 shader->ctx_reg.vs.pa_cl_vte_cntl =
1465 S_028818_VTX_W0_FMT(1) |
1466 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1467 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1468 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1469
1470 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1471 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1472
1473 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1474 }
1475
1476 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1477 {
1478 struct tgsi_shader_info *info = &ps->selector->info;
1479 unsigned num_colors = !!(info->colors_read & 0x0f) +
1480 !!(info->colors_read & 0xf0);
1481 unsigned num_interp = ps->selector->info.num_inputs +
1482 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1483
1484 assert(num_interp <= 32);
1485 return MIN2(num_interp, 32);
1486 }
1487
1488 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1489 {
1490 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1491 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1492
1493 /* If the i-th target format is set, all previous target formats must
1494 * be non-zero to avoid hangs.
1495 */
1496 for (i = 0; i < num_targets; i++)
1497 if (!(value & (0xf << (i * 4))))
1498 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1499
1500 return value;
1501 }
1502
1503 static void si_emit_shader_ps(struct si_context *sctx)
1504 {
1505 struct si_shader *shader = sctx->queued.named.ps->shader;
1506 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1507
1508 if (!shader)
1509 return;
1510
1511 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1512 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1513 SI_TRACKED_SPI_PS_INPUT_ENA,
1514 shader->ctx_reg.ps.spi_ps_input_ena,
1515 shader->ctx_reg.ps.spi_ps_input_addr);
1516
1517 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1518 SI_TRACKED_SPI_BARYC_CNTL,
1519 shader->ctx_reg.ps.spi_baryc_cntl);
1520 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1521 SI_TRACKED_SPI_PS_IN_CONTROL,
1522 shader->ctx_reg.ps.spi_ps_in_control);
1523
1524 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1525 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1526 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1527 shader->ctx_reg.ps.spi_shader_z_format,
1528 shader->ctx_reg.ps.spi_shader_col_format);
1529
1530 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1531 SI_TRACKED_CB_SHADER_MASK,
1532 shader->ctx_reg.ps.cb_shader_mask);
1533
1534 if (initial_cdw != sctx->gfx_cs->current.cdw)
1535 sctx->context_roll = true;
1536 }
1537
1538 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1539 {
1540 struct tgsi_shader_info *info = &shader->selector->info;
1541 struct si_pm4_state *pm4;
1542 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1543 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1544 uint64_t va;
1545 unsigned input_ena = shader->config.spi_ps_input_ena;
1546
1547 /* we need to enable at least one of them, otherwise we hang the GPU */
1548 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1549 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1550 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1551 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1552 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1553 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1554 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1555 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1556 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1557 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1558 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1559 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1560 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1561 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1562
1563 /* Validate interpolation optimization flags (read as implications). */
1564 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1565 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1566 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1567 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1568 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1569 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1570 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1571 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1572 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1573 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1574 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1575 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1576 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1577 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1578 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1579 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1580 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1581 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1582
1583 /* Validate cases when the optimizations are off (read as implications). */
1584 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1585 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1586 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1587 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1588 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1589 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1590
1591 pm4 = si_get_shader_pm4_state(shader);
1592 if (!pm4)
1593 return;
1594
1595 pm4->atom.emit = si_emit_shader_ps;
1596
1597 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1598 * Possible vaules:
1599 * 0 -> Position = pixel center
1600 * 1 -> Position = pixel centroid
1601 * 2 -> Position = at sample position
1602 *
1603 * From GLSL 4.5 specification, section 7.1:
1604 * "The variable gl_FragCoord is available as an input variable from
1605 * within fragment shaders and it holds the window relative coordinates
1606 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1607 * value can be for any location within the pixel, or one of the
1608 * fragment samples. The use of centroid does not further restrict
1609 * this value to be inside the current primitive."
1610 *
1611 * Meaning that centroid has no effect and we can return anything within
1612 * the pixel. Thus, return the value at sample position, because that's
1613 * the most accurate one shaders can get.
1614 */
1615 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1616
1617 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1618 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1619 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1620
1621 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1622 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1623
1624 /* Ensure that some export memory is always allocated, for two reasons:
1625 *
1626 * 1) Correctness: The hardware ignores the EXEC mask if no export
1627 * memory is allocated, so KILL and alpha test do not work correctly
1628 * without this.
1629 * 2) Performance: Every shader needs at least a NULL export, even when
1630 * it writes no color/depth output. The NULL export instruction
1631 * stalls without this setting.
1632 *
1633 * Don't add this to CB_SHADER_MASK.
1634 *
1635 * GFX10 supports pixel shaders without exports by setting both
1636 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1637 * instructions if any are present.
1638 */
1639 if ((sscreen->info.chip_class <= GFX9 ||
1640 info->uses_kill ||
1641 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1642 !spi_shader_col_format &&
1643 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1644 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1645
1646 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1647 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1648
1649 /* Set interpolation controls. */
1650 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1651 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1652
1653 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1654 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1655 shader->ctx_reg.ps.spi_shader_z_format =
1656 ac_get_spi_shader_z_format(info->writes_z,
1657 info->writes_stencil,
1658 info->writes_samplemask);
1659 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1660 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1661
1662 va = shader->bo->gpu_address;
1663 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1664 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1665 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1666
1667 uint32_t rsrc1 =
1668 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1669 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1670 S_00B028_DX10_CLAMP(1) |
1671 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1672 S_00B028_FLOAT_MODE(shader->config.float_mode);
1673
1674 if (sscreen->info.chip_class < GFX10) {
1675 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1676 }
1677
1678 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1679 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1680 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1681 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1682 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1683 }
1684
1685 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1686 struct si_shader *shader)
1687 {
1688 switch (shader->selector->type) {
1689 case PIPE_SHADER_VERTEX:
1690 if (shader->key.as_ls)
1691 si_shader_ls(sscreen, shader);
1692 else if (shader->key.as_es)
1693 si_shader_es(sscreen, shader);
1694 else if (shader->key.as_ngg)
1695 gfx10_shader_ngg(sscreen, shader);
1696 else
1697 si_shader_vs(sscreen, shader, NULL);
1698 break;
1699 case PIPE_SHADER_TESS_CTRL:
1700 si_shader_hs(sscreen, shader);
1701 break;
1702 case PIPE_SHADER_TESS_EVAL:
1703 if (shader->key.as_es)
1704 si_shader_es(sscreen, shader);
1705 else if (shader->key.as_ngg)
1706 gfx10_shader_ngg(sscreen, shader);
1707 else
1708 si_shader_vs(sscreen, shader, NULL);
1709 break;
1710 case PIPE_SHADER_GEOMETRY:
1711 if (shader->key.as_ngg)
1712 gfx10_shader_ngg(sscreen, shader);
1713 else
1714 si_shader_gs(sscreen, shader);
1715 break;
1716 case PIPE_SHADER_FRAGMENT:
1717 si_shader_ps(sscreen, shader);
1718 break;
1719 default:
1720 assert(0);
1721 }
1722 }
1723
1724 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1725 {
1726 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1727 return sctx->queued.named.dsa->alpha_func;
1728 }
1729
1730 void si_shader_selector_key_vs(struct si_context *sctx,
1731 struct si_shader_selector *vs,
1732 struct si_shader_key *key,
1733 struct si_vs_prolog_bits *prolog_key)
1734 {
1735 if (!sctx->vertex_elements ||
1736 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1737 return;
1738
1739 struct si_vertex_elements *elts = sctx->vertex_elements;
1740
1741 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1742 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1743 prolog_key->unpack_instance_id_from_vertex_id =
1744 sctx->prim_discard_cs_instancing;
1745
1746 /* Prefer a monolithic shader to allow scheduling divisions around
1747 * VBO loads. */
1748 if (prolog_key->instance_divisor_is_fetched)
1749 key->opt.prefer_mono = 1;
1750
1751 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1752 unsigned count_mask = (1 << count) - 1;
1753 unsigned fix = elts->fix_fetch_always & count_mask;
1754 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1755
1756 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1757 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1758 while (mask) {
1759 unsigned i = u_bit_scan(&mask);
1760 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1761 unsigned vbidx = elts->vertex_buffer_index[i];
1762 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1763 unsigned align_mask = (1 << log_hw_load_size) - 1;
1764 if (vb->buffer_offset & align_mask ||
1765 vb->stride & align_mask) {
1766 fix |= 1 << i;
1767 opencode |= 1 << i;
1768 }
1769 }
1770 }
1771
1772 while (fix) {
1773 unsigned i = u_bit_scan(&fix);
1774 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1775 }
1776 key->mono.vs_fetch_opencode = opencode;
1777 }
1778
1779 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1780 struct si_shader_selector *vs,
1781 struct si_shader_key *key)
1782 {
1783 struct si_shader_selector *ps = sctx->ps_shader.cso;
1784
1785 key->opt.clip_disable =
1786 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1787 (vs->info.clipdist_writemask ||
1788 vs->info.writes_clipvertex) &&
1789 !vs->info.culldist_writemask;
1790
1791 /* Find out if PS is disabled. */
1792 bool ps_disabled = true;
1793 if (ps) {
1794 bool ps_modifies_zs = ps->info.uses_kill ||
1795 ps->info.writes_z ||
1796 ps->info.writes_stencil ||
1797 ps->info.writes_samplemask ||
1798 sctx->queued.named.blend->alpha_to_coverage ||
1799 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1800 unsigned ps_colormask = si_get_total_colormask(sctx);
1801
1802 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1803 (!ps_colormask &&
1804 !ps_modifies_zs &&
1805 !ps->info.writes_memory);
1806 }
1807
1808 /* Find out which VS outputs aren't used by the PS. */
1809 uint64_t outputs_written = vs->outputs_written_before_ps;
1810 uint64_t inputs_read = 0;
1811
1812 /* Ignore outputs that are not passed from VS to PS. */
1813 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1814 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1815 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1816
1817 if (!ps_disabled) {
1818 inputs_read = ps->inputs_read;
1819 }
1820
1821 uint64_t linked = outputs_written & inputs_read;
1822
1823 key->opt.kill_outputs = ~linked & outputs_written;
1824 }
1825
1826 /* Compute the key for the hw shader variant */
1827 static inline void si_shader_selector_key(struct pipe_context *ctx,
1828 struct si_shader_selector *sel,
1829 union si_vgt_stages_key stages_key,
1830 struct si_shader_key *key)
1831 {
1832 struct si_context *sctx = (struct si_context *)ctx;
1833
1834 memset(key, 0, sizeof(*key));
1835
1836 switch (sel->type) {
1837 case PIPE_SHADER_VERTEX:
1838 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1839
1840 if (sctx->tes_shader.cso)
1841 key->as_ls = 1;
1842 else if (sctx->gs_shader.cso) {
1843 key->as_es = 1;
1844 key->as_ngg = stages_key.u.ngg;
1845 } else {
1846 key->as_ngg = stages_key.u.ngg;
1847 si_shader_selector_key_hw_vs(sctx, sel, key);
1848
1849 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1850 key->mono.u.vs_export_prim_id = 1;
1851 }
1852 break;
1853 case PIPE_SHADER_TESS_CTRL:
1854 if (sctx->chip_class >= GFX9) {
1855 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1856 key, &key->part.tcs.ls_prolog);
1857 key->part.tcs.ls = sctx->vs_shader.cso;
1858
1859 /* When the LS VGPR fix is needed, monolithic shaders
1860 * can:
1861 * - avoid initializing EXEC in both the LS prolog
1862 * and the LS main part when !vs_needs_prolog
1863 * - remove the fixup for unused input VGPRs
1864 */
1865 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1866
1867 /* The LS output / HS input layout can be communicated
1868 * directly instead of via user SGPRs for merged LS-HS.
1869 * The LS VGPR fix prefers this too.
1870 */
1871 key->opt.prefer_mono = 1;
1872 }
1873
1874 key->part.tcs.epilog.prim_mode =
1875 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1876 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1877 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1878 key->part.tcs.epilog.tes_reads_tess_factors =
1879 sctx->tes_shader.cso->info.reads_tess_factors;
1880
1881 if (sel == sctx->fixed_func_tcs_shader.cso)
1882 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1883 break;
1884 case PIPE_SHADER_TESS_EVAL:
1885 key->as_ngg = stages_key.u.ngg;
1886
1887 if (sctx->gs_shader.cso)
1888 key->as_es = 1;
1889 else {
1890 si_shader_selector_key_hw_vs(sctx, sel, key);
1891
1892 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1893 key->mono.u.vs_export_prim_id = 1;
1894 }
1895 break;
1896 case PIPE_SHADER_GEOMETRY:
1897 if (sctx->chip_class >= GFX9) {
1898 if (sctx->tes_shader.cso) {
1899 key->part.gs.es = sctx->tes_shader.cso;
1900 } else {
1901 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1902 key, &key->part.gs.vs_prolog);
1903 key->part.gs.es = sctx->vs_shader.cso;
1904 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1905 }
1906
1907 key->as_ngg = stages_key.u.ngg;
1908
1909 /* Merged ES-GS can have unbalanced wave usage.
1910 *
1911 * ES threads are per-vertex, while GS threads are
1912 * per-primitive. So without any amplification, there
1913 * are fewer GS threads than ES threads, which can result
1914 * in empty (no-op) GS waves. With too much amplification,
1915 * there are more GS threads than ES threads, which
1916 * can result in empty (no-op) ES waves.
1917 *
1918 * Non-monolithic shaders are implemented by setting EXEC
1919 * at the beginning of shader parts, and don't jump to
1920 * the end if EXEC is 0.
1921 *
1922 * Monolithic shaders use conditional blocks, so they can
1923 * jump and skip empty waves of ES or GS. So set this to
1924 * always use optimized variants, which are monolithic.
1925 */
1926 key->opt.prefer_mono = 1;
1927 }
1928 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1929 break;
1930 case PIPE_SHADER_FRAGMENT: {
1931 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1932 struct si_state_blend *blend = sctx->queued.named.blend;
1933
1934 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1935 sel->info.colors_written == 0x1)
1936 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1937
1938 /* Select the shader color format based on whether
1939 * blending or alpha are needed.
1940 */
1941 key->part.ps.epilog.spi_shader_col_format =
1942 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1943 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1944 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1945 sctx->framebuffer.spi_shader_col_format_blend) |
1946 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1947 sctx->framebuffer.spi_shader_col_format_alpha) |
1948 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1949 sctx->framebuffer.spi_shader_col_format);
1950 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1951
1952 /* The output for dual source blending should have
1953 * the same format as the first output.
1954 */
1955 if (blend->dual_src_blend) {
1956 key->part.ps.epilog.spi_shader_col_format |=
1957 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1958 }
1959
1960 /* If alpha-to-coverage is enabled, we have to export alpha
1961 * even if there is no color buffer.
1962 */
1963 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1964 blend->alpha_to_coverage)
1965 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1966
1967 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1968 * to the range supported by the type if a channel has less
1969 * than 16 bits and the export format is 16_ABGR.
1970 */
1971 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1972 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1973 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1974 }
1975
1976 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1977 if (!key->part.ps.epilog.last_cbuf) {
1978 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1979 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1980 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1981 }
1982
1983 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1984 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1985
1986 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1987 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1988
1989 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
1990 rs->multisample_enable;
1991
1992 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1993 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1994 (is_line && rs->line_smooth)) &&
1995 sctx->framebuffer.nr_samples <= 1;
1996 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1997
1998 if (sctx->ps_iter_samples > 1 &&
1999 sel->info.reads_samplemask) {
2000 key->part.ps.prolog.samplemask_log_ps_iter =
2001 util_logbase2(sctx->ps_iter_samples);
2002 }
2003
2004 if (rs->force_persample_interp &&
2005 rs->multisample_enable &&
2006 sctx->framebuffer.nr_samples > 1 &&
2007 sctx->ps_iter_samples > 1) {
2008 key->part.ps.prolog.force_persp_sample_interp =
2009 sel->info.uses_persp_center ||
2010 sel->info.uses_persp_centroid;
2011
2012 key->part.ps.prolog.force_linear_sample_interp =
2013 sel->info.uses_linear_center ||
2014 sel->info.uses_linear_centroid;
2015 } else if (rs->multisample_enable &&
2016 sctx->framebuffer.nr_samples > 1) {
2017 key->part.ps.prolog.bc_optimize_for_persp =
2018 sel->info.uses_persp_center &&
2019 sel->info.uses_persp_centroid;
2020 key->part.ps.prolog.bc_optimize_for_linear =
2021 sel->info.uses_linear_center &&
2022 sel->info.uses_linear_centroid;
2023 } else {
2024 /* Make sure SPI doesn't compute more than 1 pair
2025 * of (i,j), which is the optimization here. */
2026 key->part.ps.prolog.force_persp_center_interp =
2027 sel->info.uses_persp_center +
2028 sel->info.uses_persp_centroid +
2029 sel->info.uses_persp_sample > 1;
2030
2031 key->part.ps.prolog.force_linear_center_interp =
2032 sel->info.uses_linear_center +
2033 sel->info.uses_linear_centroid +
2034 sel->info.uses_linear_sample > 1;
2035
2036 if (sel->info.uses_persp_opcode_interp_sample ||
2037 sel->info.uses_linear_opcode_interp_sample)
2038 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2039 }
2040
2041 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2042
2043 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2044 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2045 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2046 struct pipe_resource *tex = cb0->texture;
2047
2048 /* 1D textures are allocated and used as 2D on GFX9. */
2049 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2050 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2051 (tex->target == PIPE_TEXTURE_1D ||
2052 tex->target == PIPE_TEXTURE_1D_ARRAY);
2053 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2054 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2055 tex->target == PIPE_TEXTURE_CUBE ||
2056 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2057 tex->target == PIPE_TEXTURE_3D;
2058 }
2059 break;
2060 }
2061 default:
2062 assert(0);
2063 }
2064
2065 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2066 memset(&key->opt, 0, sizeof(key->opt));
2067 }
2068
2069 static void si_build_shader_variant(struct si_shader *shader,
2070 int thread_index,
2071 bool low_priority)
2072 {
2073 struct si_shader_selector *sel = shader->selector;
2074 struct si_screen *sscreen = sel->screen;
2075 struct ac_llvm_compiler *compiler;
2076 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2077
2078 if (thread_index >= 0) {
2079 if (low_priority) {
2080 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2081 compiler = &sscreen->compiler_lowp[thread_index];
2082 } else {
2083 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2084 compiler = &sscreen->compiler[thread_index];
2085 }
2086 if (!debug->async)
2087 debug = NULL;
2088 } else {
2089 assert(!low_priority);
2090 compiler = shader->compiler_ctx_state.compiler;
2091 }
2092
2093 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2094 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2095 sel->type);
2096 shader->compilation_failed = true;
2097 return;
2098 }
2099
2100 if (shader->compiler_ctx_state.is_debug_context) {
2101 FILE *f = open_memstream(&shader->shader_log,
2102 &shader->shader_log_size);
2103 if (f) {
2104 si_shader_dump(sscreen, shader, NULL, f, false);
2105 fclose(f);
2106 }
2107 }
2108
2109 si_shader_init_pm4_state(sscreen, shader);
2110 }
2111
2112 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2113 {
2114 struct si_shader *shader = (struct si_shader *)job;
2115
2116 assert(thread_index >= 0);
2117
2118 si_build_shader_variant(shader, thread_index, true);
2119 }
2120
2121 static const struct si_shader_key zeroed;
2122
2123 static bool si_check_missing_main_part(struct si_screen *sscreen,
2124 struct si_shader_selector *sel,
2125 struct si_compiler_ctx_state *compiler_state,
2126 struct si_shader_key *key)
2127 {
2128 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2129
2130 if (!*mainp) {
2131 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2132
2133 if (!main_part)
2134 return false;
2135
2136 /* We can leave the fence as permanently signaled because the
2137 * main part becomes visible globally only after it has been
2138 * compiled. */
2139 util_queue_fence_init(&main_part->ready);
2140
2141 main_part->selector = sel;
2142 main_part->key.as_es = key->as_es;
2143 main_part->key.as_ls = key->as_ls;
2144 main_part->key.as_ngg = key->as_ngg;
2145 main_part->is_monolithic = false;
2146
2147 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2148 main_part, &compiler_state->debug) != 0) {
2149 FREE(main_part);
2150 return false;
2151 }
2152 *mainp = main_part;
2153 }
2154 return true;
2155 }
2156
2157 /**
2158 * Select a shader variant according to the shader key.
2159 *
2160 * \param optimized_or_none If the key describes an optimized shader variant and
2161 * the compilation isn't finished, don't select any
2162 * shader and return an error.
2163 */
2164 int si_shader_select_with_key(struct si_screen *sscreen,
2165 struct si_shader_ctx_state *state,
2166 struct si_compiler_ctx_state *compiler_state,
2167 struct si_shader_key *key,
2168 int thread_index,
2169 bool optimized_or_none)
2170 {
2171 struct si_shader_selector *sel = state->cso;
2172 struct si_shader_selector *previous_stage_sel = NULL;
2173 struct si_shader *current = state->current;
2174 struct si_shader *iter, *shader = NULL;
2175
2176 again:
2177 /* Check if we don't need to change anything.
2178 * This path is also used for most shaders that don't need multiple
2179 * variants, it will cost just a computation of the key and this
2180 * test. */
2181 if (likely(current &&
2182 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2183 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2184 if (current->is_optimized) {
2185 if (optimized_or_none)
2186 return -1;
2187
2188 memset(&key->opt, 0, sizeof(key->opt));
2189 goto current_not_ready;
2190 }
2191
2192 util_queue_fence_wait(&current->ready);
2193 }
2194
2195 return current->compilation_failed ? -1 : 0;
2196 }
2197 current_not_ready:
2198
2199 /* This must be done before the mutex is locked, because async GS
2200 * compilation calls this function too, and therefore must enter
2201 * the mutex first.
2202 *
2203 * Only wait if we are in a draw call. Don't wait if we are
2204 * in a compiler thread.
2205 */
2206 if (thread_index < 0)
2207 util_queue_fence_wait(&sel->ready);
2208
2209 mtx_lock(&sel->mutex);
2210
2211 /* Find the shader variant. */
2212 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2213 /* Don't check the "current" shader. We checked it above. */
2214 if (current != iter &&
2215 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2216 mtx_unlock(&sel->mutex);
2217
2218 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2219 /* If it's an optimized shader and its compilation has
2220 * been started but isn't done, use the unoptimized
2221 * shader so as not to cause a stall due to compilation.
2222 */
2223 if (iter->is_optimized) {
2224 if (optimized_or_none)
2225 return -1;
2226 memset(&key->opt, 0, sizeof(key->opt));
2227 goto again;
2228 }
2229
2230 util_queue_fence_wait(&iter->ready);
2231 }
2232
2233 if (iter->compilation_failed) {
2234 return -1; /* skip the draw call */
2235 }
2236
2237 state->current = iter;
2238 return 0;
2239 }
2240 }
2241
2242 /* Build a new shader. */
2243 shader = CALLOC_STRUCT(si_shader);
2244 if (!shader) {
2245 mtx_unlock(&sel->mutex);
2246 return -ENOMEM;
2247 }
2248
2249 util_queue_fence_init(&shader->ready);
2250
2251 shader->selector = sel;
2252 shader->key = *key;
2253 shader->compiler_ctx_state = *compiler_state;
2254
2255 /* If this is a merged shader, get the first shader's selector. */
2256 if (sscreen->info.chip_class >= GFX9) {
2257 if (sel->type == PIPE_SHADER_TESS_CTRL)
2258 previous_stage_sel = key->part.tcs.ls;
2259 else if (sel->type == PIPE_SHADER_GEOMETRY)
2260 previous_stage_sel = key->part.gs.es;
2261
2262 /* We need to wait for the previous shader. */
2263 if (previous_stage_sel && thread_index < 0)
2264 util_queue_fence_wait(&previous_stage_sel->ready);
2265 }
2266
2267 bool is_pure_monolithic =
2268 sscreen->use_monolithic_shaders ||
2269 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2270
2271 /* Compile the main shader part if it doesn't exist. This can happen
2272 * if the initial guess was wrong.
2273 *
2274 * The prim discard CS doesn't need the main shader part.
2275 */
2276 if (!is_pure_monolithic &&
2277 !key->opt.vs_as_prim_discard_cs) {
2278 bool ok = true;
2279
2280 /* Make sure the main shader part is present. This is needed
2281 * for shaders that can be compiled as VS, LS, or ES, and only
2282 * one of them is compiled at creation.
2283 *
2284 * It is also needed for GS, which can be compiled as non-NGG
2285 * and NGG.
2286 *
2287 * For merged shaders, check that the starting shader's main
2288 * part is present.
2289 */
2290 if (previous_stage_sel) {
2291 struct si_shader_key shader1_key = zeroed;
2292
2293 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2294 shader1_key.as_ls = 1;
2295 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2296 shader1_key.as_es = 1;
2297 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2298 } else {
2299 assert(0);
2300 }
2301
2302 mtx_lock(&previous_stage_sel->mutex);
2303 ok = si_check_missing_main_part(sscreen,
2304 previous_stage_sel,
2305 compiler_state, &shader1_key);
2306 mtx_unlock(&previous_stage_sel->mutex);
2307 }
2308
2309 if (ok) {
2310 ok = si_check_missing_main_part(sscreen, sel,
2311 compiler_state, key);
2312 }
2313
2314 if (!ok) {
2315 FREE(shader);
2316 mtx_unlock(&sel->mutex);
2317 return -ENOMEM; /* skip the draw call */
2318 }
2319 }
2320
2321 /* Keep the reference to the 1st shader of merged shaders, so that
2322 * Gallium can't destroy it before we destroy the 2nd shader.
2323 *
2324 * Set sctx = NULL, because it's unused if we're not releasing
2325 * the shader, and we don't have any sctx here.
2326 */
2327 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2328 previous_stage_sel);
2329
2330 /* Monolithic-only shaders don't make a distinction between optimized
2331 * and unoptimized. */
2332 shader->is_monolithic =
2333 is_pure_monolithic ||
2334 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2335
2336 /* The prim discard CS is always optimized. */
2337 shader->is_optimized =
2338 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2339 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2340
2341 /* If it's an optimized shader, compile it asynchronously. */
2342 if (shader->is_optimized && thread_index < 0) {
2343 /* Compile it asynchronously. */
2344 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2345 shader, &shader->ready,
2346 si_build_shader_variant_low_priority, NULL);
2347
2348 /* Add only after the ready fence was reset, to guard against a
2349 * race with si_bind_XX_shader. */
2350 if (!sel->last_variant) {
2351 sel->first_variant = shader;
2352 sel->last_variant = shader;
2353 } else {
2354 sel->last_variant->next_variant = shader;
2355 sel->last_variant = shader;
2356 }
2357
2358 /* Use the default (unoptimized) shader for now. */
2359 memset(&key->opt, 0, sizeof(key->opt));
2360 mtx_unlock(&sel->mutex);
2361
2362 if (sscreen->options.sync_compile)
2363 util_queue_fence_wait(&shader->ready);
2364
2365 if (optimized_or_none)
2366 return -1;
2367 goto again;
2368 }
2369
2370 /* Reset the fence before adding to the variant list. */
2371 util_queue_fence_reset(&shader->ready);
2372
2373 if (!sel->last_variant) {
2374 sel->first_variant = shader;
2375 sel->last_variant = shader;
2376 } else {
2377 sel->last_variant->next_variant = shader;
2378 sel->last_variant = shader;
2379 }
2380
2381 mtx_unlock(&sel->mutex);
2382
2383 assert(!shader->is_optimized);
2384 si_build_shader_variant(shader, thread_index, false);
2385
2386 util_queue_fence_signal(&shader->ready);
2387
2388 if (!shader->compilation_failed)
2389 state->current = shader;
2390
2391 return shader->compilation_failed ? -1 : 0;
2392 }
2393
2394 static int si_shader_select(struct pipe_context *ctx,
2395 struct si_shader_ctx_state *state,
2396 union si_vgt_stages_key stages_key,
2397 struct si_compiler_ctx_state *compiler_state)
2398 {
2399 struct si_context *sctx = (struct si_context *)ctx;
2400 struct si_shader_key key;
2401
2402 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2403 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2404 &key, -1, false);
2405 }
2406
2407 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2408 bool streamout,
2409 struct si_shader_key *key)
2410 {
2411 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2412
2413 switch (info->processor) {
2414 case PIPE_SHADER_VERTEX:
2415 switch (next_shader) {
2416 case PIPE_SHADER_GEOMETRY:
2417 key->as_es = 1;
2418 break;
2419 case PIPE_SHADER_TESS_CTRL:
2420 case PIPE_SHADER_TESS_EVAL:
2421 key->as_ls = 1;
2422 break;
2423 default:
2424 /* If POSITION isn't written, it can only be a HW VS
2425 * if streamout is used. If streamout isn't used,
2426 * assume that it's a HW LS. (the next shader is TCS)
2427 * This heuristic is needed for separate shader objects.
2428 */
2429 if (!info->writes_position && !streamout)
2430 key->as_ls = 1;
2431 }
2432 break;
2433
2434 case PIPE_SHADER_TESS_EVAL:
2435 if (next_shader == PIPE_SHADER_GEOMETRY ||
2436 !info->writes_position)
2437 key->as_es = 1;
2438 break;
2439 }
2440 }
2441
2442 /**
2443 * Compile the main shader part or the monolithic shader as part of
2444 * si_shader_selector initialization. Since it can be done asynchronously,
2445 * there is no way to report compile failures to applications.
2446 */
2447 static void si_init_shader_selector_async(void *job, int thread_index)
2448 {
2449 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2450 struct si_screen *sscreen = sel->screen;
2451 struct ac_llvm_compiler *compiler;
2452 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2453
2454 assert(!debug->debug_message || debug->async);
2455 assert(thread_index >= 0);
2456 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2457 compiler = &sscreen->compiler[thread_index];
2458
2459 if (sel->nir)
2460 si_lower_nir(sel);
2461
2462 /* Compile the main shader part for use with a prolog and/or epilog.
2463 * If this fails, the driver will try to compile a monolithic shader
2464 * on demand.
2465 */
2466 if (!sscreen->use_monolithic_shaders) {
2467 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2468 void *ir_binary = NULL;
2469
2470 if (!shader) {
2471 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2472 return;
2473 }
2474
2475 /* We can leave the fence signaled because use of the default
2476 * main part is guarded by the selector's ready fence. */
2477 util_queue_fence_init(&shader->ready);
2478
2479 shader->selector = sel;
2480 shader->is_monolithic = false;
2481 si_parse_next_shader_property(&sel->info,
2482 sel->so.num_outputs != 0,
2483 &shader->key);
2484
2485 if (sscreen->use_ngg &&
2486 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2487 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2488 sel->type == PIPE_SHADER_TESS_EVAL ||
2489 sel->type == PIPE_SHADER_GEOMETRY))
2490 shader->key.as_ngg = 1;
2491
2492 if (sel->tokens || sel->nir) {
2493 ir_binary = si_get_ir_binary(sel, shader->key.as_ngg,
2494 shader->key.as_es);
2495 }
2496
2497 /* Try to load the shader from the shader cache. */
2498 mtx_lock(&sscreen->shader_cache_mutex);
2499
2500 if (ir_binary &&
2501 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2502 mtx_unlock(&sscreen->shader_cache_mutex);
2503 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2504 } else {
2505 mtx_unlock(&sscreen->shader_cache_mutex);
2506
2507 /* Compile the shader if it hasn't been loaded from the cache. */
2508 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2509 debug) != 0) {
2510 FREE(shader);
2511 FREE(ir_binary);
2512 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2513 return;
2514 }
2515
2516 if (ir_binary) {
2517 mtx_lock(&sscreen->shader_cache_mutex);
2518 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2519 FREE(ir_binary);
2520 mtx_unlock(&sscreen->shader_cache_mutex);
2521 }
2522 }
2523
2524 *si_get_main_shader_part(sel, &shader->key) = shader;
2525
2526 /* Unset "outputs_written" flags for outputs converted to
2527 * DEFAULT_VAL, so that later inter-shader optimizations don't
2528 * try to eliminate outputs that don't exist in the final
2529 * shader.
2530 *
2531 * This is only done if non-monolithic shaders are enabled.
2532 */
2533 if ((sel->type == PIPE_SHADER_VERTEX ||
2534 sel->type == PIPE_SHADER_TESS_EVAL) &&
2535 !shader->key.as_ls &&
2536 !shader->key.as_es) {
2537 unsigned i;
2538
2539 for (i = 0; i < sel->info.num_outputs; i++) {
2540 unsigned offset = shader->info.vs_output_param_offset[i];
2541
2542 if (offset <= AC_EXP_PARAM_OFFSET_31)
2543 continue;
2544
2545 unsigned name = sel->info.output_semantic_name[i];
2546 unsigned index = sel->info.output_semantic_index[i];
2547 unsigned id;
2548
2549 switch (name) {
2550 case TGSI_SEMANTIC_GENERIC:
2551 /* don't process indices the function can't handle */
2552 if (index >= SI_MAX_IO_GENERIC)
2553 break;
2554 /* fall through */
2555 default:
2556 id = si_shader_io_get_unique_index(name, index, true);
2557 sel->outputs_written_before_ps &= ~(1ull << id);
2558 break;
2559 case TGSI_SEMANTIC_POSITION: /* ignore these */
2560 case TGSI_SEMANTIC_PSIZE:
2561 case TGSI_SEMANTIC_CLIPVERTEX:
2562 case TGSI_SEMANTIC_EDGEFLAG:
2563 break;
2564 }
2565 }
2566 }
2567 }
2568
2569 /* The GS copy shader is always pre-compiled. */
2570 if (sel->type == PIPE_SHADER_GEOMETRY &&
2571 (!sscreen->use_ngg ||
2572 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2573 sel->tess_turns_off_ngg)) {
2574 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2575 if (!sel->gs_copy_shader) {
2576 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2577 return;
2578 }
2579
2580 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2581 }
2582 }
2583
2584 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2585 struct util_queue_fence *ready_fence,
2586 struct si_compiler_ctx_state *compiler_ctx_state,
2587 void *job, util_queue_execute_func execute)
2588 {
2589 util_queue_fence_init(ready_fence);
2590
2591 struct util_async_debug_callback async_debug;
2592 bool debug =
2593 (sctx->debug.debug_message && !sctx->debug.async) ||
2594 sctx->is_debug ||
2595 si_can_dump_shader(sctx->screen, processor);
2596
2597 if (debug) {
2598 u_async_debug_init(&async_debug);
2599 compiler_ctx_state->debug = async_debug.base;
2600 }
2601
2602 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2603 ready_fence, execute, NULL);
2604
2605 if (debug) {
2606 util_queue_fence_wait(ready_fence);
2607 u_async_debug_drain(&async_debug, &sctx->debug);
2608 u_async_debug_cleanup(&async_debug);
2609 }
2610
2611 if (sctx->screen->options.sync_compile)
2612 util_queue_fence_wait(ready_fence);
2613 }
2614
2615 /* Return descriptor slot usage masks from the given shader info. */
2616 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2617 uint32_t *const_and_shader_buffers,
2618 uint64_t *samplers_and_images)
2619 {
2620 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2621
2622 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2623 num_constbufs = util_last_bit(info->const_buffers_declared);
2624 /* two 8-byte images share one 16-byte slot */
2625 num_images = align(util_last_bit(info->images_declared), 2);
2626 num_samplers = util_last_bit(info->samplers_declared);
2627
2628 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2629 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2630 *const_and_shader_buffers =
2631 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2632
2633 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2634 start = si_get_image_slot(num_images - 1) / 2;
2635 *samplers_and_images =
2636 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2637 }
2638
2639 static void *si_create_shader_selector(struct pipe_context *ctx,
2640 const struct pipe_shader_state *state)
2641 {
2642 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2643 struct si_context *sctx = (struct si_context*)ctx;
2644 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2645 int i;
2646
2647 if (!sel)
2648 return NULL;
2649
2650 pipe_reference_init(&sel->reference, 1);
2651 sel->screen = sscreen;
2652 sel->compiler_ctx_state.debug = sctx->debug;
2653 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2654
2655 sel->so = state->stream_output;
2656
2657 if (state->type == PIPE_SHADER_IR_TGSI &&
2658 !sscreen->options.enable_nir) {
2659 sel->tokens = tgsi_dup_tokens(state->tokens);
2660 if (!sel->tokens) {
2661 FREE(sel);
2662 return NULL;
2663 }
2664
2665 tgsi_scan_shader(state->tokens, &sel->info);
2666 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2667
2668 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2669 if (sel->info.uses_persp_opcode_interp_centroid)
2670 sel->info.uses_persp_centroid = true;
2671
2672 if (sel->info.uses_linear_opcode_interp_centroid)
2673 sel->info.uses_linear_centroid = true;
2674
2675 if (sel->info.uses_persp_opcode_interp_offset ||
2676 sel->info.uses_persp_opcode_interp_sample)
2677 sel->info.uses_persp_center = true;
2678
2679 if (sel->info.uses_linear_opcode_interp_offset ||
2680 sel->info.uses_linear_opcode_interp_sample)
2681 sel->info.uses_linear_center = true;
2682 } else {
2683 if (state->type == PIPE_SHADER_IR_TGSI) {
2684 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2685 } else {
2686 assert(state->type == PIPE_SHADER_IR_NIR);
2687 sel->nir = state->ir.nir;
2688 }
2689
2690 si_nir_lower_ps_inputs(sel->nir);
2691 si_nir_opts(sel->nir);
2692 si_nir_scan_shader(sel->nir, &sel->info);
2693 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2694 }
2695
2696 sel->type = sel->info.processor;
2697 p_atomic_inc(&sscreen->num_shaders_created);
2698 si_get_active_slot_masks(&sel->info,
2699 &sel->active_const_and_shader_buffers,
2700 &sel->active_samplers_and_images);
2701
2702 /* Record which streamout buffers are enabled. */
2703 for (i = 0; i < sel->so.num_outputs; i++) {
2704 sel->enabled_streamout_buffer_mask |=
2705 (1 << sel->so.output[i].output_buffer) <<
2706 (sel->so.output[i].stream * 4);
2707 }
2708
2709 /* The prolog is a no-op if there are no inputs. */
2710 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2711 sel->info.num_inputs &&
2712 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2713
2714 sel->force_correct_derivs_after_kill =
2715 sel->type == PIPE_SHADER_FRAGMENT &&
2716 sel->info.uses_derivatives &&
2717 sel->info.uses_kill &&
2718 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2719
2720 sel->prim_discard_cs_allowed =
2721 sel->type == PIPE_SHADER_VERTEX &&
2722 !sel->info.uses_bindless_images &&
2723 !sel->info.uses_bindless_samplers &&
2724 !sel->info.writes_memory &&
2725 !sel->info.writes_viewport_index &&
2726 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2727 !sel->so.num_outputs;
2728
2729 switch (sel->type) {
2730 case PIPE_SHADER_GEOMETRY:
2731 sel->gs_output_prim =
2732 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2733
2734 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2735 sel->rast_prim = sel->gs_output_prim;
2736 if (util_rast_prim_is_triangles(sel->rast_prim))
2737 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2738
2739 sel->gs_max_out_vertices =
2740 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2741 sel->gs_num_invocations =
2742 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2743 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2744 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2745 sel->gs_max_out_vertices;
2746
2747 sel->max_gs_stream = 0;
2748 for (i = 0; i < sel->so.num_outputs; i++)
2749 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2750 sel->so.output[i].stream);
2751
2752 sel->gs_input_verts_per_prim =
2753 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2754
2755 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2756 sel->tess_turns_off_ngg =
2757 (sscreen->info.family == CHIP_NAVI10 ||
2758 sscreen->info.family == CHIP_NAVI12 ||
2759 sscreen->info.family == CHIP_NAVI14) &&
2760 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2761 break;
2762
2763 case PIPE_SHADER_TESS_CTRL:
2764 /* Always reserve space for these. */
2765 sel->patch_outputs_written |=
2766 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2767 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2768 /* fall through */
2769 case PIPE_SHADER_VERTEX:
2770 case PIPE_SHADER_TESS_EVAL:
2771 for (i = 0; i < sel->info.num_outputs; i++) {
2772 unsigned name = sel->info.output_semantic_name[i];
2773 unsigned index = sel->info.output_semantic_index[i];
2774
2775 switch (name) {
2776 case TGSI_SEMANTIC_TESSINNER:
2777 case TGSI_SEMANTIC_TESSOUTER:
2778 case TGSI_SEMANTIC_PATCH:
2779 sel->patch_outputs_written |=
2780 1ull << si_shader_io_get_unique_index_patch(name, index);
2781 break;
2782
2783 case TGSI_SEMANTIC_GENERIC:
2784 /* don't process indices the function can't handle */
2785 if (index >= SI_MAX_IO_GENERIC)
2786 break;
2787 /* fall through */
2788 default:
2789 sel->outputs_written |=
2790 1ull << si_shader_io_get_unique_index(name, index, false);
2791 sel->outputs_written_before_ps |=
2792 1ull << si_shader_io_get_unique_index(name, index, true);
2793 break;
2794 case TGSI_SEMANTIC_EDGEFLAG:
2795 break;
2796 }
2797 }
2798 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2799 sel->lshs_vertex_stride = sel->esgs_itemsize;
2800
2801 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2802 * will start on a different bank. (except for the maximum 32*16).
2803 */
2804 if (sel->lshs_vertex_stride < 32*16)
2805 sel->lshs_vertex_stride += 4;
2806
2807 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2808 * conflicts, i.e. each vertex will start at a different bank.
2809 */
2810 if (sctx->chip_class >= GFX9)
2811 sel->esgs_itemsize += 4;
2812
2813 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2814
2815 /* Only for TES: */
2816 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2817 sel->rast_prim = PIPE_PRIM_POINTS;
2818 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2819 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2820 else
2821 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2822 break;
2823
2824 case PIPE_SHADER_FRAGMENT:
2825 for (i = 0; i < sel->info.num_inputs; i++) {
2826 unsigned name = sel->info.input_semantic_name[i];
2827 unsigned index = sel->info.input_semantic_index[i];
2828
2829 switch (name) {
2830 case TGSI_SEMANTIC_GENERIC:
2831 /* don't process indices the function can't handle */
2832 if (index >= SI_MAX_IO_GENERIC)
2833 break;
2834 /* fall through */
2835 default:
2836 sel->inputs_read |=
2837 1ull << si_shader_io_get_unique_index(name, index, true);
2838 break;
2839 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2840 break;
2841 }
2842 }
2843
2844 for (i = 0; i < 8; i++)
2845 if (sel->info.colors_written & (1 << i))
2846 sel->colors_written_4bit |= 0xf << (4 * i);
2847
2848 for (i = 0; i < sel->info.num_inputs; i++) {
2849 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2850 int index = sel->info.input_semantic_index[i];
2851 sel->color_attr_index[index] = i;
2852 }
2853 }
2854 break;
2855 default:;
2856 }
2857
2858 /* PA_CL_VS_OUT_CNTL */
2859 bool misc_vec_ena =
2860 sel->info.writes_psize || sel->info.writes_edgeflag ||
2861 sel->info.writes_layer || sel->info.writes_viewport_index;
2862 sel->pa_cl_vs_out_cntl =
2863 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2864 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2865 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2866 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2867 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2868 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2869 sel->clipdist_mask = sel->info.writes_clipvertex ?
2870 SIX_BITS : sel->info.clipdist_writemask;
2871 sel->culldist_mask = sel->info.culldist_writemask <<
2872 sel->info.num_written