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radeonsi/gfx10: set PA_CL_VS_OUT_CNTL with CONTEXT_REG_RMW to fix edge flags
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 void *si_get_ir_binary(struct si_shader_selector *sel, bool ngg, bool es)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 /* These settings affect the compilation, but they are not derived
68 * from the input shader IR.
69 */
70 unsigned shader_variant_flags = 0;
71
72 if (ngg)
73 shader_variant_flags |= 1 << 0;
74 if (sel->nir)
75 shader_variant_flags |= 1 << 1;
76 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
77 shader_variant_flags |= 1 << 2;
78 if (sel->force_correct_derivs_after_kill)
79 shader_variant_flags |= 1 << 3;
80
81 unsigned size = 4 + 4 + ir_size + sizeof(sel->so);
82 char *result = (char*)MALLOC(size);
83 if (!result)
84 return NULL;
85
86 ((uint32_t*)result)[0] = size;
87 ((uint32_t*)result)[1] = shader_variant_flags;
88 memcpy(result + 8, ir_binary, ir_size);
89 memcpy(result + 8 + ir_size, &sel->so, sizeof(sel->so));
90
91 if (sel->nir)
92 blob_finish(&blob);
93
94 return result;
95 }
96
97 /** Copy "data" to "ptr" and return the next dword following copied data. */
98 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
99 {
100 /* data may be NULL if size == 0 */
101 if (size)
102 memcpy(ptr, data, size);
103 ptr += DIV_ROUND_UP(size, 4);
104 return ptr;
105 }
106
107 /** Read data from "ptr". Return the next dword following the data. */
108 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
109 {
110 memcpy(data, ptr, size);
111 ptr += DIV_ROUND_UP(size, 4);
112 return ptr;
113 }
114
115 /**
116 * Write the size as uint followed by the data. Return the next dword
117 * following the copied data.
118 */
119 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
120 {
121 *ptr++ = size;
122 return write_data(ptr, data, size);
123 }
124
125 /**
126 * Read the size as uint followed by the data. Return both via parameters.
127 * Return the next dword following the data.
128 */
129 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
130 {
131 *size = *ptr++;
132 assert(*data == NULL);
133 if (!*size)
134 return ptr;
135 *data = malloc(*size);
136 return read_data(ptr, *data, *size);
137 }
138
139 /**
140 * Return the shader binary in a buffer. The first 4 bytes contain its size
141 * as integer.
142 */
143 static void *si_get_shader_binary(struct si_shader *shader)
144 {
145 /* There is always a size of data followed by the data itself. */
146 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
147 strlen(shader->binary.llvm_ir_string) + 1 : 0;
148
149 /* Refuse to allocate overly large buffers and guard against integer
150 * overflow. */
151 if (shader->binary.elf_size > UINT_MAX / 4 ||
152 llvm_ir_size > UINT_MAX / 4)
153 return NULL;
154
155 unsigned size =
156 4 + /* total size */
157 4 + /* CRC32 of the data below */
158 align(sizeof(shader->config), 4) +
159 align(sizeof(shader->info), 4) +
160 4 + align(shader->binary.elf_size, 4) +
161 4 + align(llvm_ir_size, 4);
162 void *buffer = CALLOC(1, size);
163 uint32_t *ptr = (uint32_t*)buffer;
164
165 if (!buffer)
166 return NULL;
167
168 *ptr++ = size;
169 ptr++; /* CRC32 is calculated at the end. */
170
171 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
172 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
173 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
174 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
175 assert((char *)ptr - (char *)buffer == size);
176
177 /* Compute CRC32. */
178 ptr = (uint32_t*)buffer;
179 ptr++;
180 *ptr = util_hash_crc32(ptr + 1, size - 8);
181
182 return buffer;
183 }
184
185 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
186 {
187 uint32_t *ptr = (uint32_t*)binary;
188 uint32_t size = *ptr++;
189 uint32_t crc32 = *ptr++;
190 unsigned chunk_size;
191 unsigned elf_size;
192
193 if (util_hash_crc32(ptr, size - 8) != crc32) {
194 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
195 return false;
196 }
197
198 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
199 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
200 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
201 &elf_size);
202 shader->binary.elf_size = elf_size;
203 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
204
205 return true;
206 }
207
208 /**
209 * Insert a shader into the cache. It's assumed the shader is not in the cache.
210 * Use si_shader_cache_load_shader before calling this.
211 *
212 * Returns false on failure, in which case the ir_binary should be freed.
213 */
214 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
215 struct si_shader *shader,
216 bool insert_into_disk_cache)
217 {
218 void *hw_binary;
219 struct hash_entry *entry;
220 uint8_t key[CACHE_KEY_SIZE];
221
222 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
223 if (entry)
224 return false; /* already added */
225
226 hw_binary = si_get_shader_binary(shader);
227 if (!hw_binary)
228 return false;
229
230 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
231 hw_binary) == NULL) {
232 FREE(hw_binary);
233 return false;
234 }
235
236 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
237 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
238 *((uint32_t *)ir_binary), key);
239 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
240 *((uint32_t *) hw_binary), NULL);
241 }
242
243 return true;
244 }
245
246 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
247 struct si_shader *shader)
248 {
249 struct hash_entry *entry =
250 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
251 if (!entry) {
252 if (sscreen->disk_shader_cache) {
253 unsigned char sha1[CACHE_KEY_SIZE];
254 size_t tg_size = *((uint32_t *) ir_binary);
255
256 disk_cache_compute_key(sscreen->disk_shader_cache,
257 ir_binary, tg_size, sha1);
258
259 size_t binary_size;
260 uint8_t *buffer =
261 disk_cache_get(sscreen->disk_shader_cache,
262 sha1, &binary_size);
263 if (!buffer)
264 return false;
265
266 if (binary_size < sizeof(uint32_t) ||
267 *((uint32_t*)buffer) != binary_size) {
268 /* Something has gone wrong discard the item
269 * from the cache and rebuild/link from
270 * source.
271 */
272 assert(!"Invalid radeonsi shader disk cache "
273 "item!");
274
275 disk_cache_remove(sscreen->disk_shader_cache,
276 sha1);
277 free(buffer);
278
279 return false;
280 }
281
282 if (!si_load_shader_binary(shader, buffer)) {
283 free(buffer);
284 return false;
285 }
286 free(buffer);
287
288 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
289 shader, false))
290 FREE(ir_binary);
291 } else {
292 return false;
293 }
294 } else {
295 if (si_load_shader_binary(shader, entry->data))
296 FREE(ir_binary);
297 else
298 return false;
299 }
300 p_atomic_inc(&sscreen->num_shader_cache_hits);
301 return true;
302 }
303
304 static uint32_t si_shader_cache_key_hash(const void *key)
305 {
306 /* The first dword is the key size. */
307 return util_hash_crc32(key, *(uint32_t*)key);
308 }
309
310 static bool si_shader_cache_key_equals(const void *a, const void *b)
311 {
312 uint32_t *keya = (uint32_t*)a;
313 uint32_t *keyb = (uint32_t*)b;
314
315 /* The first dword is the key size. */
316 if (*keya != *keyb)
317 return false;
318
319 return memcmp(keya, keyb, *keya) == 0;
320 }
321
322 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
323 {
324 FREE((void*)entry->key);
325 FREE(entry->data);
326 }
327
328 bool si_init_shader_cache(struct si_screen *sscreen)
329 {
330 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
331 sscreen->shader_cache =
332 _mesa_hash_table_create(NULL,
333 si_shader_cache_key_hash,
334 si_shader_cache_key_equals);
335
336 return sscreen->shader_cache != NULL;
337 }
338
339 void si_destroy_shader_cache(struct si_screen *sscreen)
340 {
341 if (sscreen->shader_cache)
342 _mesa_hash_table_destroy(sscreen->shader_cache,
343 si_destroy_shader_cache_entry);
344 mtx_destroy(&sscreen->shader_cache_mutex);
345 }
346
347 /* SHADER STATES */
348
349 static void si_set_tesseval_regs(struct si_screen *sscreen,
350 const struct si_shader_selector *tes,
351 struct si_pm4_state *pm4)
352 {
353 const struct tgsi_shader_info *info = &tes->info;
354 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
355 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
356 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
357 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
358 unsigned type, partitioning, topology, distribution_mode;
359
360 switch (tes_prim_mode) {
361 case PIPE_PRIM_LINES:
362 type = V_028B6C_TESS_ISOLINE;
363 break;
364 case PIPE_PRIM_TRIANGLES:
365 type = V_028B6C_TESS_TRIANGLE;
366 break;
367 case PIPE_PRIM_QUADS:
368 type = V_028B6C_TESS_QUAD;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 switch (tes_spacing) {
376 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
377 partitioning = V_028B6C_PART_FRAC_ODD;
378 break;
379 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
380 partitioning = V_028B6C_PART_FRAC_EVEN;
381 break;
382 case PIPE_TESS_SPACING_EQUAL:
383 partitioning = V_028B6C_PART_INTEGER;
384 break;
385 default:
386 assert(0);
387 return;
388 }
389
390 if (tes_point_mode)
391 topology = V_028B6C_OUTPUT_POINT;
392 else if (tes_prim_mode == PIPE_PRIM_LINES)
393 topology = V_028B6C_OUTPUT_LINE;
394 else if (tes_vertex_order_cw)
395 /* for some reason, this must be the other way around */
396 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
397 else
398 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
399
400 if (sscreen->info.has_distributed_tess) {
401 if (sscreen->info.family == CHIP_FIJI ||
402 sscreen->info.family >= CHIP_POLARIS10)
403 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
404 else
405 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
406 } else
407 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
408
409 assert(pm4->shader);
410 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
411 S_028B6C_PARTITIONING(partitioning) |
412 S_028B6C_TOPOLOGY(topology) |
413 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
414 }
415
416 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
417 * whether the "fractional odd" tessellation spacing is used.
418 *
419 * Possible VGT configurations and which state should set the register:
420 *
421 * Reg set in | VGT shader configuration | Value
422 * ------------------------------------------------------
423 * VS as VS | VS | 30
424 * VS as ES | ES -> GS -> VS | 30
425 * TES as VS | LS -> HS -> VS | 14 or 30
426 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
427 *
428 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
429 */
430 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
431 struct si_shader_selector *sel,
432 struct si_shader *shader,
433 struct si_pm4_state *pm4)
434 {
435 unsigned type = sel->type;
436
437 if (sscreen->info.family < CHIP_POLARIS10 ||
438 sscreen->info.chip_class >= GFX10)
439 return;
440
441 /* VS as VS, or VS as ES: */
442 if ((type == PIPE_SHADER_VERTEX &&
443 (!shader ||
444 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
445 /* TES as VS, or TES as ES: */
446 type == PIPE_SHADER_TESS_EVAL) {
447 unsigned vtx_reuse_depth = 30;
448
449 if (type == PIPE_SHADER_TESS_EVAL &&
450 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
451 PIPE_TESS_SPACING_FRACTIONAL_ODD)
452 vtx_reuse_depth = 14;
453
454 assert(pm4->shader);
455 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
456 }
457 }
458
459 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
460 {
461 if (shader->pm4)
462 si_pm4_clear_state(shader->pm4);
463 else
464 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
465
466 if (shader->pm4) {
467 shader->pm4->shader = shader;
468 return shader->pm4;
469 } else {
470 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
471 return NULL;
472 }
473 }
474
475 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
476 {
477 /* Add the pointer to VBO descriptors. */
478 return num_always_on_user_sgprs + 1;
479 }
480
481 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
482 {
483 struct si_pm4_state *pm4;
484 unsigned vgpr_comp_cnt;
485 uint64_t va;
486
487 assert(sscreen->info.chip_class <= GFX8);
488
489 pm4 = si_get_shader_pm4_state(shader);
490 if (!pm4)
491 return;
492
493 va = shader->bo->gpu_address;
494 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
495
496 /* We need at least 2 components for LS.
497 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
498 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
499 */
500 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
501
502 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
503 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
504
505 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
506 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
507 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
508 S_00B528_DX10_CLAMP(1) |
509 S_00B528_FLOAT_MODE(shader->config.float_mode);
510 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
511 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
512 }
513
514 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
515 {
516 struct si_pm4_state *pm4;
517 uint64_t va;
518 unsigned ls_vgpr_comp_cnt = 0;
519
520 pm4 = si_get_shader_pm4_state(shader);
521 if (!pm4)
522 return;
523
524 va = shader->bo->gpu_address;
525 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
526
527 if (sscreen->info.chip_class >= GFX9) {
528 if (sscreen->info.chip_class >= GFX10) {
529 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
530 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
531 } else {
532 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
533 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
534 }
535
536 /* We need at least 2 components for LS.
537 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
538 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
539 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
540 * be loaded.
541 */
542 ls_vgpr_comp_cnt = 1;
543 if (shader->info.uses_instanceid) {
544 if (sscreen->info.chip_class >= GFX10)
545 ls_vgpr_comp_cnt = 3;
546 else
547 ls_vgpr_comp_cnt = 2;
548 }
549
550 unsigned num_user_sgprs =
551 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
552
553 shader->config.rsrc2 =
554 S_00B42C_USER_SGPR(num_user_sgprs) |
555 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
556
557 if (sscreen->info.chip_class >= GFX10)
558 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
559 else
560 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
561 } else {
562 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
563 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
564
565 shader->config.rsrc2 =
566 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
567 S_00B42C_OC_LDS_EN(1) |
568 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
569 }
570
571 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
572 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
573 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
574 (sscreen->info.chip_class <= GFX9 ?
575 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
576 S_00B428_DX10_CLAMP(1) |
577 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
578 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
579 S_00B428_FLOAT_MODE(shader->config.float_mode) |
580 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
581
582 if (sscreen->info.chip_class <= GFX8) {
583 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
584 shader->config.rsrc2);
585 }
586 }
587
588 static void si_emit_shader_es(struct si_context *sctx)
589 {
590 struct si_shader *shader = sctx->queued.named.es->shader;
591 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
592
593 if (!shader)
594 return;
595
596 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
597 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
598 shader->selector->esgs_itemsize / 4);
599
600 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
601 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
602 SI_TRACKED_VGT_TF_PARAM,
603 shader->vgt_tf_param);
604
605 if (shader->vgt_vertex_reuse_block_cntl)
606 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
607 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
608 shader->vgt_vertex_reuse_block_cntl);
609
610 if (initial_cdw != sctx->gfx_cs->current.cdw)
611 sctx->context_roll = true;
612 }
613
614 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
615 {
616 struct si_pm4_state *pm4;
617 unsigned num_user_sgprs;
618 unsigned vgpr_comp_cnt;
619 uint64_t va;
620 unsigned oc_lds_en;
621
622 assert(sscreen->info.chip_class <= GFX8);
623
624 pm4 = si_get_shader_pm4_state(shader);
625 if (!pm4)
626 return;
627
628 pm4->atom.emit = si_emit_shader_es;
629 va = shader->bo->gpu_address;
630 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
631
632 if (shader->selector->type == PIPE_SHADER_VERTEX) {
633 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
634 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
635 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
636 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
637 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
638 num_user_sgprs = SI_TES_NUM_USER_SGPR;
639 } else
640 unreachable("invalid shader selector type");
641
642 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
643
644 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
645 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
646 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
647 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
648 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
649 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
650 S_00B328_DX10_CLAMP(1) |
651 S_00B328_FLOAT_MODE(shader->config.float_mode));
652 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
653 S_00B32C_USER_SGPR(num_user_sgprs) |
654 S_00B32C_OC_LDS_EN(oc_lds_en) |
655 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
656
657 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
658 si_set_tesseval_regs(sscreen, shader->selector, pm4);
659
660 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
661 }
662
663 void gfx9_get_gs_info(struct si_shader_selector *es,
664 struct si_shader_selector *gs,
665 struct gfx9_gs_info *out)
666 {
667 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
668 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
669 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
670 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
671
672 /* All these are in dwords: */
673 /* We can't allow using the whole LDS, because GS waves compete with
674 * other shader stages for LDS space. */
675 const unsigned max_lds_size = 8 * 1024;
676 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
677 unsigned esgs_lds_size;
678
679 /* All these are per subgroup: */
680 const unsigned max_out_prims = 32 * 1024;
681 const unsigned max_es_verts = 255;
682 const unsigned ideal_gs_prims = 64;
683 unsigned max_gs_prims, gs_prims;
684 unsigned min_es_verts, es_verts, worst_case_es_verts;
685
686 if (uses_adjacency || gs_num_invocations > 1)
687 max_gs_prims = 127 / gs_num_invocations;
688 else
689 max_gs_prims = 255;
690
691 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
692 * Make sure we don't go over the maximum value.
693 */
694 if (gs->gs_max_out_vertices > 0) {
695 max_gs_prims = MIN2(max_gs_prims,
696 max_out_prims /
697 (gs->gs_max_out_vertices * gs_num_invocations));
698 }
699 assert(max_gs_prims > 0);
700
701 /* If the primitive has adjacency, halve the number of vertices
702 * that will be reused in multiple primitives.
703 */
704 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
705
706 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
707 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
708
709 /* Compute ESGS LDS size based on the worst case number of ES vertices
710 * needed to create the target number of GS prims per subgroup.
711 */
712 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
713
714 /* If total LDS usage is too big, refactor partitions based on ratio
715 * of ESGS item sizes.
716 */
717 if (esgs_lds_size > max_lds_size) {
718 /* Our target GS Prims Per Subgroup was too large. Calculate
719 * the maximum number of GS Prims Per Subgroup that will fit
720 * into LDS, capped by the maximum that the hardware can support.
721 */
722 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
723 max_gs_prims);
724 assert(gs_prims > 0);
725 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
726 max_es_verts);
727
728 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
729 assert(esgs_lds_size <= max_lds_size);
730 }
731
732 /* Now calculate remaining ESGS information. */
733 if (esgs_lds_size)
734 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
735 else
736 es_verts = max_es_verts;
737
738 /* Vertices for adjacency primitives are not always reused, so restore
739 * it for ES_VERTS_PER_SUBGRP.
740 */
741 min_es_verts = gs->gs_input_verts_per_prim;
742
743 /* For normal primitives, the VGT only checks if they are past the ES
744 * verts per subgroup after allocating a full GS primitive and if they
745 * are, kick off a new subgroup. But if those additional ES verts are
746 * unique (e.g. not reused) we need to make sure there is enough LDS
747 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
748 */
749 es_verts -= min_es_verts - 1;
750
751 out->es_verts_per_subgroup = es_verts;
752 out->gs_prims_per_subgroup = gs_prims;
753 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
754 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
755 gs->gs_max_out_vertices;
756 out->esgs_ring_size = 4 * esgs_lds_size;
757
758 assert(out->max_prims_per_subgroup <= max_out_prims);
759 }
760
761 static void si_emit_shader_gs(struct si_context *sctx)
762 {
763 struct si_shader *shader = sctx->queued.named.gs->shader;
764 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
765
766 if (!shader)
767 return;
768
769 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
770 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
771 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
772 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
773 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
774 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
775 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
776
777 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
778 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
779 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
780 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
781
782 /* R_028B38_VGT_GS_MAX_VERT_OUT */
783 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
784 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
785 shader->ctx_reg.gs.vgt_gs_max_vert_out);
786
787 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
788 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
789 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
790 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
791 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
792 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
793 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
794 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
795
796 /* R_028B90_VGT_GS_INSTANCE_CNT */
797 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
798 SI_TRACKED_VGT_GS_INSTANCE_CNT,
799 shader->ctx_reg.gs.vgt_gs_instance_cnt);
800
801 if (sctx->chip_class >= GFX9) {
802 /* R_028A44_VGT_GS_ONCHIP_CNTL */
803 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
804 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
805 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
806 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
807 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
808 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
809 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
810 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
811 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
812 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
813 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
814
815 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
816 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
817 SI_TRACKED_VGT_TF_PARAM,
818 shader->vgt_tf_param);
819 if (shader->vgt_vertex_reuse_block_cntl)
820 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
821 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
822 shader->vgt_vertex_reuse_block_cntl);
823 }
824
825 if (initial_cdw != sctx->gfx_cs->current.cdw)
826 sctx->context_roll = true;
827 }
828
829 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
830 {
831 struct si_shader_selector *sel = shader->selector;
832 const ubyte *num_components = sel->info.num_stream_output_components;
833 unsigned gs_num_invocations = sel->gs_num_invocations;
834 struct si_pm4_state *pm4;
835 uint64_t va;
836 unsigned max_stream = sel->max_gs_stream;
837 unsigned offset;
838
839 pm4 = si_get_shader_pm4_state(shader);
840 if (!pm4)
841 return;
842
843 pm4->atom.emit = si_emit_shader_gs;
844
845 offset = num_components[0] * sel->gs_max_out_vertices;
846 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
847
848 if (max_stream >= 1)
849 offset += num_components[1] * sel->gs_max_out_vertices;
850 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
851
852 if (max_stream >= 2)
853 offset += num_components[2] * sel->gs_max_out_vertices;
854 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
855
856 if (max_stream >= 3)
857 offset += num_components[3] * sel->gs_max_out_vertices;
858 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
859
860 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
861 assert(offset < (1 << 15));
862
863 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
864
865 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
866 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
867 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
868 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
869
870 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
871 S_028B90_ENABLE(gs_num_invocations > 0);
872
873 va = shader->bo->gpu_address;
874 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
875
876 if (sscreen->info.chip_class >= GFX9) {
877 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
878 unsigned es_type = shader->key.part.gs.es->type;
879 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
880
881 if (es_type == PIPE_SHADER_VERTEX) {
882 /* GFX10: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 or InstanceID)
883 * GFX9: (VertexID, InstanceID / StepRate0, ...)
884 */
885 if (sscreen->info.chip_class >= GFX10)
886 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
887 else
888 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
889 } else if (es_type == PIPE_SHADER_TESS_EVAL)
890 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
891 else
892 unreachable("invalid shader selector type");
893
894 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
895 * VGPR[0:4] are always loaded.
896 */
897 if (sel->info.uses_invocationid)
898 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
899 else if (sel->info.uses_primid)
900 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
901 else if (input_prim >= PIPE_PRIM_TRIANGLES)
902 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
903 else
904 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
905
906 unsigned num_user_sgprs;
907 if (es_type == PIPE_SHADER_VERTEX)
908 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
909 else
910 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
911
912 if (sscreen->info.chip_class >= GFX10) {
913 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
914 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
915 } else {
916 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
917 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
918 }
919
920 uint32_t rsrc1 =
921 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
922 S_00B228_DX10_CLAMP(1) |
923 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
924 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
925 S_00B228_FLOAT_MODE(shader->config.float_mode) |
926 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
927 uint32_t rsrc2 =
928 S_00B22C_USER_SGPR(num_user_sgprs) |
929 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
930 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
931 S_00B22C_LDS_SIZE(shader->config.lds_size) |
932 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
933
934 if (sscreen->info.chip_class >= GFX10) {
935 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
936 } else {
937 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
938 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
939 }
940
941 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
942 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
943
944 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
945 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
946 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
947 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
948 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
949 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
950 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
951 shader->key.part.gs.es->esgs_itemsize / 4;
952
953 if (es_type == PIPE_SHADER_TESS_EVAL)
954 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
955
956 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
957 NULL, pm4);
958 } else {
959 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
960 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
961
962 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
963 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
964 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
965 S_00B228_DX10_CLAMP(1) |
966 S_00B228_FLOAT_MODE(shader->config.float_mode));
967 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
968 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
969 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
970 }
971 }
972
973 /* Common tail code for NGG primitive shaders. */
974 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
975 struct si_shader *shader,
976 unsigned initial_cdw)
977 {
978 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
979 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
980 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
981 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
982 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
983 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
984 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
985 SI_TRACKED_VGT_PRIMITIVEID_EN,
986 shader->ctx_reg.ngg.vgt_primitiveid_en);
987 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
988 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
989 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
990 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
991 SI_TRACKED_VGT_GS_INSTANCE_CNT,
992 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
993 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
994 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
995 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
996 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
997 SI_TRACKED_SPI_VS_OUT_CONFIG,
998 shader->ctx_reg.ngg.spi_vs_out_config);
999 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
1000 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
1001 shader->ctx_reg.ngg.spi_shader_idx_format,
1002 shader->ctx_reg.ngg.spi_shader_pos_format);
1003 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1004 SI_TRACKED_PA_CL_VTE_CNTL,
1005 shader->ctx_reg.ngg.pa_cl_vte_cntl);
1006 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1007 SI_TRACKED_PA_CL_NGG_CNTL,
1008 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1009
1010 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1011 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1012 shader->pa_cl_vs_out_cntl,
1013 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1014
1015 if (initial_cdw != sctx->gfx_cs->current.cdw)
1016 sctx->context_roll = true;
1017 }
1018
1019 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1020 {
1021 struct si_shader *shader = sctx->queued.named.gs->shader;
1022 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1023
1024 if (!shader)
1025 return;
1026
1027 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1028 }
1029
1030 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1031 {
1032 struct si_shader *shader = sctx->queued.named.gs->shader;
1033 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1034
1035 if (!shader)
1036 return;
1037
1038 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1039 SI_TRACKED_VGT_TF_PARAM,
1040 shader->vgt_tf_param);
1041
1042 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1043 }
1044
1045 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1046 {
1047 struct si_shader *shader = sctx->queued.named.gs->shader;
1048 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1049
1050 if (!shader)
1051 return;
1052
1053 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1054 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1055 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1056
1057 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1058 }
1059
1060 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1061 {
1062 struct si_shader *shader = sctx->queued.named.gs->shader;
1063 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1064
1065 if (!shader)
1066 return;
1067
1068 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1069 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1070 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1071 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1072 SI_TRACKED_VGT_TF_PARAM,
1073 shader->vgt_tf_param);
1074
1075 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1076 }
1077
1078 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1079 {
1080 if (gs->type == PIPE_SHADER_GEOMETRY)
1081 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1082
1083 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1084 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1085 return PIPE_PRIM_POINTS;
1086 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1087 return PIPE_PRIM_LINES;
1088 return PIPE_PRIM_TRIANGLES;
1089 }
1090
1091 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1092 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1093 }
1094
1095 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1096 {
1097 bool misc_vec_ena =
1098 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1099 sel->info.writes_layer || sel->info.writes_viewport_index;
1100 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1101 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1102 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1103 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1104 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1105 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1106 }
1107
1108 /**
1109 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1110 * in NGG mode.
1111 */
1112 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1113 {
1114 const struct si_shader_selector *gs_sel = shader->selector;
1115 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1116 enum pipe_shader_type gs_type = shader->selector->type;
1117 const struct si_shader_selector *es_sel =
1118 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1119 const struct tgsi_shader_info *es_info = &es_sel->info;
1120 enum pipe_shader_type es_type = es_sel->type;
1121 unsigned num_user_sgprs;
1122 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1123 uint64_t va;
1124 unsigned window_space =
1125 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1126 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1127 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1128 unsigned input_prim = si_get_input_prim(gs_sel);
1129 bool break_wave_at_eoi = false;
1130 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1131 if (!pm4)
1132 return;
1133
1134 if (es_type == PIPE_SHADER_TESS_EVAL) {
1135 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1136 : gfx10_emit_shader_ngg_tess_nogs;
1137 } else {
1138 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1139 : gfx10_emit_shader_ngg_notess_nogs;
1140 }
1141
1142 va = shader->bo->gpu_address;
1143 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1144
1145 if (es_type == PIPE_SHADER_VERTEX) {
1146 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1147 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1148
1149 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1150 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1151 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1152 } else {
1153 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1154 }
1155 } else {
1156 assert(es_type == PIPE_SHADER_TESS_EVAL);
1157 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1158 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1159
1160 if (es_enable_prim_id || gs_info->uses_primid)
1161 break_wave_at_eoi = true;
1162 }
1163
1164 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1165 * VGPR[0:4] are always loaded.
1166 *
1167 * Vertex shaders always need to load VGPR3, because they need to
1168 * pass edge flags for decomposed primitives (such as quads) to the PA
1169 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1170 */
1171 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1172 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1173 else if (gs_info->uses_primid)
1174 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1175 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1176 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1177 else
1178 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1179
1180 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1181 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1182 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1183 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1184 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1185 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1186 S_00B228_DX10_CLAMP(1) |
1187 S_00B228_MEM_ORDERED(1) |
1188 S_00B228_WGP_MODE(1) |
1189 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1190 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1191 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1192 S_00B22C_USER_SGPR(num_user_sgprs) |
1193 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1194 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1195 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1196 S_00B22C_LDS_SIZE(shader->config.lds_size));
1197
1198 nparams = MAX2(shader->info.nr_param_exports, 1);
1199 shader->ctx_reg.ngg.spi_vs_out_config =
1200 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1201 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1202
1203 shader->ctx_reg.ngg.spi_shader_idx_format =
1204 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1205 shader->ctx_reg.ngg.spi_shader_pos_format =
1206 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1207 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1208 V_02870C_SPI_SHADER_4COMP :
1209 V_02870C_SPI_SHADER_NONE) |
1210 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1211 V_02870C_SPI_SHADER_4COMP :
1212 V_02870C_SPI_SHADER_NONE) |
1213 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1214 V_02870C_SPI_SHADER_4COMP :
1215 V_02870C_SPI_SHADER_NONE);
1216
1217 shader->ctx_reg.ngg.vgt_primitiveid_en =
1218 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1219 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1220
1221 if (gs_type == PIPE_SHADER_GEOMETRY) {
1222 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1223 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1224 } else {
1225 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1226 }
1227
1228 if (es_type == PIPE_SHADER_TESS_EVAL)
1229 si_set_tesseval_regs(sscreen, es_sel, pm4);
1230
1231 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1232 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1233 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1234 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1235 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1236 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1237 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1238 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1239 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1240 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1241 S_028B90_CNT(gs_num_invocations) |
1242 S_028B90_ENABLE(gs_num_invocations > 1) |
1243 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1244 shader->ngg.max_vert_out_per_gs_instance);
1245
1246 /* Always output hw-generated edge flags and pass them via the prim
1247 * export to prevent drawing lines on internal edges of decomposed
1248 * primitives (such as quads) with polygon mode = lines. Only VS needs
1249 * this.
1250 */
1251 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1252 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1253 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1254
1255 shader->ge_cntl =
1256 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1257 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1258 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1259
1260 /* Bug workaround for a possible hang with non-tessellation cases.
1261 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1262 *
1263 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1264 */
1265 if ((sscreen->info.family == CHIP_NAVI10 ||
1266 sscreen->info.family == CHIP_NAVI12 ||
1267 sscreen->info.family == CHIP_NAVI14) &&
1268 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1269 shader->ngg.hw_max_esverts != 256) {
1270 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1271
1272 if (shader->ngg.hw_max_esverts > 5) {
1273 shader->ge_cntl |=
1274 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1275 }
1276 }
1277
1278 if (window_space) {
1279 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1280 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1281 } else {
1282 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1283 S_028818_VTX_W0_FMT(1) |
1284 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1285 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1286 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1287 }
1288 }
1289
1290 static void si_emit_shader_vs(struct si_context *sctx)
1291 {
1292 struct si_shader *shader = sctx->queued.named.vs->shader;
1293 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1294
1295 if (!shader)
1296 return;
1297
1298 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1299 SI_TRACKED_VGT_GS_MODE,
1300 shader->ctx_reg.vs.vgt_gs_mode);
1301 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1302 SI_TRACKED_VGT_PRIMITIVEID_EN,
1303 shader->ctx_reg.vs.vgt_primitiveid_en);
1304
1305 if (sctx->chip_class <= GFX8) {
1306 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1307 SI_TRACKED_VGT_REUSE_OFF,
1308 shader->ctx_reg.vs.vgt_reuse_off);
1309 }
1310
1311 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1312 SI_TRACKED_SPI_VS_OUT_CONFIG,
1313 shader->ctx_reg.vs.spi_vs_out_config);
1314
1315 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1316 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1317 shader->ctx_reg.vs.spi_shader_pos_format);
1318
1319 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1320 SI_TRACKED_PA_CL_VTE_CNTL,
1321 shader->ctx_reg.vs.pa_cl_vte_cntl);
1322
1323 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1324 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1325 SI_TRACKED_VGT_TF_PARAM,
1326 shader->vgt_tf_param);
1327
1328 if (shader->vgt_vertex_reuse_block_cntl)
1329 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1330 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1331 shader->vgt_vertex_reuse_block_cntl);
1332
1333 if (initial_cdw != sctx->gfx_cs->current.cdw)
1334 sctx->context_roll = true;
1335
1336 /* Required programming for tessellation. (legacy pipeline only) */
1337 if (sctx->chip_class == GFX10 &&
1338 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1339 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1340 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1341 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1342 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1343 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1344 }
1345
1346 if (sctx->chip_class >= GFX10) {
1347 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1348 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1349 shader->pa_cl_vs_out_cntl,
1350 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1351 }
1352 }
1353
1354 /**
1355 * Compute the state for \p shader, which will run as a vertex shader on the
1356 * hardware.
1357 *
1358 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1359 * is the copy shader.
1360 */
1361 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1362 struct si_shader_selector *gs)
1363 {
1364 const struct tgsi_shader_info *info = &shader->selector->info;
1365 struct si_pm4_state *pm4;
1366 unsigned num_user_sgprs, vgpr_comp_cnt;
1367 uint64_t va;
1368 unsigned nparams, oc_lds_en;
1369 unsigned window_space =
1370 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1371 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1372
1373 pm4 = si_get_shader_pm4_state(shader);
1374 if (!pm4)
1375 return;
1376
1377 pm4->atom.emit = si_emit_shader_vs;
1378
1379 /* We always write VGT_GS_MODE in the VS state, because every switch
1380 * between different shader pipelines involving a different GS or no
1381 * GS at all involves a switch of the VS (different GS use different
1382 * copy shaders). On the other hand, when the API switches from a GS to
1383 * no GS and then back to the same GS used originally, the GS state is
1384 * not sent again.
1385 */
1386 if (!gs) {
1387 unsigned mode = V_028A40_GS_OFF;
1388
1389 /* PrimID needs GS scenario A. */
1390 if (enable_prim_id)
1391 mode = V_028A40_GS_SCENARIO_A;
1392
1393 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1394 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1395 } else {
1396 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1397 sscreen->info.chip_class);
1398 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1399 }
1400
1401 if (sscreen->info.chip_class <= GFX8) {
1402 /* Reuse needs to be set off if we write oViewport. */
1403 shader->ctx_reg.vs.vgt_reuse_off =
1404 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1405 }
1406
1407 va = shader->bo->gpu_address;
1408 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1409
1410 if (gs) {
1411 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1412 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1413 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1414 if (sscreen->info.chip_class >= GFX10) {
1415 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
1416 } else {
1417 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1418 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1419 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1420 */
1421 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1422 }
1423
1424 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1425 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1426 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1427 } else {
1428 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1429 }
1430 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1431 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1432 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1433 } else
1434 unreachable("invalid shader selector type");
1435
1436 /* VS is required to export at least one param. */
1437 nparams = MAX2(shader->info.nr_param_exports, 1);
1438 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1439
1440 if (sscreen->info.chip_class >= GFX10) {
1441 shader->ctx_reg.vs.spi_vs_out_config |=
1442 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1443 }
1444
1445 shader->ctx_reg.vs.spi_shader_pos_format =
1446 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1447 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1448 V_02870C_SPI_SHADER_4COMP :
1449 V_02870C_SPI_SHADER_NONE) |
1450 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1451 V_02870C_SPI_SHADER_4COMP :
1452 V_02870C_SPI_SHADER_NONE) |
1453 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1454 V_02870C_SPI_SHADER_4COMP :
1455 V_02870C_SPI_SHADER_NONE);
1456 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1457
1458 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1459
1460 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1461 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1462
1463 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1464 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1465 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1466 S_00B128_DX10_CLAMP(1) |
1467 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1468 S_00B128_FLOAT_MODE(shader->config.float_mode);
1469 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1470 S_00B12C_OC_LDS_EN(oc_lds_en) |
1471 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1472
1473 if (sscreen->info.chip_class <= GFX9)
1474 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1475
1476 if (!sscreen->use_ngg_streamout) {
1477 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1478 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1479 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1480 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1481 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1482 }
1483
1484 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1485 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1486
1487 if (window_space)
1488 shader->ctx_reg.vs.pa_cl_vte_cntl =
1489 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1490 else
1491 shader->ctx_reg.vs.pa_cl_vte_cntl =
1492 S_028818_VTX_W0_FMT(1) |
1493 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1494 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1495 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1496
1497 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1498 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1499
1500 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1501 }
1502
1503 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1504 {
1505 struct tgsi_shader_info *info = &ps->selector->info;
1506 unsigned num_colors = !!(info->colors_read & 0x0f) +
1507 !!(info->colors_read & 0xf0);
1508 unsigned num_interp = ps->selector->info.num_inputs +
1509 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1510
1511 assert(num_interp <= 32);
1512 return MIN2(num_interp, 32);
1513 }
1514
1515 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1516 {
1517 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1518 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1519
1520 /* If the i-th target format is set, all previous target formats must
1521 * be non-zero to avoid hangs.
1522 */
1523 for (i = 0; i < num_targets; i++)
1524 if (!(value & (0xf << (i * 4))))
1525 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1526
1527 return value;
1528 }
1529
1530 static void si_emit_shader_ps(struct si_context *sctx)
1531 {
1532 struct si_shader *shader = sctx->queued.named.ps->shader;
1533 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1534
1535 if (!shader)
1536 return;
1537
1538 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1539 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1540 SI_TRACKED_SPI_PS_INPUT_ENA,
1541 shader->ctx_reg.ps.spi_ps_input_ena,
1542 shader->ctx_reg.ps.spi_ps_input_addr);
1543
1544 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1545 SI_TRACKED_SPI_BARYC_CNTL,
1546 shader->ctx_reg.ps.spi_baryc_cntl);
1547 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1548 SI_TRACKED_SPI_PS_IN_CONTROL,
1549 shader->ctx_reg.ps.spi_ps_in_control);
1550
1551 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1552 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1553 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1554 shader->ctx_reg.ps.spi_shader_z_format,
1555 shader->ctx_reg.ps.spi_shader_col_format);
1556
1557 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1558 SI_TRACKED_CB_SHADER_MASK,
1559 shader->ctx_reg.ps.cb_shader_mask);
1560
1561 if (initial_cdw != sctx->gfx_cs->current.cdw)
1562 sctx->context_roll = true;
1563 }
1564
1565 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1566 {
1567 struct tgsi_shader_info *info = &shader->selector->info;
1568 struct si_pm4_state *pm4;
1569 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1570 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1571 uint64_t va;
1572 unsigned input_ena = shader->config.spi_ps_input_ena;
1573
1574 /* we need to enable at least one of them, otherwise we hang the GPU */
1575 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1576 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1577 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1578 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1579 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1580 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1581 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1582 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1583 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1584 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1585 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1586 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1587 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1588 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1589
1590 /* Validate interpolation optimization flags (read as implications). */
1591 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1592 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1593 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1594 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1595 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1596 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1597 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1598 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1599 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1600 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1601 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1602 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1603 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1604 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1605 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1606 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1607 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1608 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1609
1610 /* Validate cases when the optimizations are off (read as implications). */
1611 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1612 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1613 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1614 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1615 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1616 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1617
1618 pm4 = si_get_shader_pm4_state(shader);
1619 if (!pm4)
1620 return;
1621
1622 pm4->atom.emit = si_emit_shader_ps;
1623
1624 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1625 * Possible vaules:
1626 * 0 -> Position = pixel center
1627 * 1 -> Position = pixel centroid
1628 * 2 -> Position = at sample position
1629 *
1630 * From GLSL 4.5 specification, section 7.1:
1631 * "The variable gl_FragCoord is available as an input variable from
1632 * within fragment shaders and it holds the window relative coordinates
1633 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1634 * value can be for any location within the pixel, or one of the
1635 * fragment samples. The use of centroid does not further restrict
1636 * this value to be inside the current primitive."
1637 *
1638 * Meaning that centroid has no effect and we can return anything within
1639 * the pixel. Thus, return the value at sample position, because that's
1640 * the most accurate one shaders can get.
1641 */
1642 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1643
1644 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1645 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1646 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1647
1648 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1649 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1650
1651 /* Ensure that some export memory is always allocated, for two reasons:
1652 *
1653 * 1) Correctness: The hardware ignores the EXEC mask if no export
1654 * memory is allocated, so KILL and alpha test do not work correctly
1655 * without this.
1656 * 2) Performance: Every shader needs at least a NULL export, even when
1657 * it writes no color/depth output. The NULL export instruction
1658 * stalls without this setting.
1659 *
1660 * Don't add this to CB_SHADER_MASK.
1661 *
1662 * GFX10 supports pixel shaders without exports by setting both
1663 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1664 * instructions if any are present.
1665 */
1666 if ((sscreen->info.chip_class <= GFX9 ||
1667 info->uses_kill ||
1668 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1669 !spi_shader_col_format &&
1670 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1671 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1672
1673 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1674 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1675
1676 /* Set interpolation controls. */
1677 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1678 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1679
1680 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1681 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1682 shader->ctx_reg.ps.spi_shader_z_format =
1683 ac_get_spi_shader_z_format(info->writes_z,
1684 info->writes_stencil,
1685 info->writes_samplemask);
1686 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1687 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1688
1689 va = shader->bo->gpu_address;
1690 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1691 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1692 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1693
1694 uint32_t rsrc1 =
1695 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1696 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1697 S_00B028_DX10_CLAMP(1) |
1698 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1699 S_00B028_FLOAT_MODE(shader->config.float_mode);
1700
1701 if (sscreen->info.chip_class < GFX10) {
1702 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1703 }
1704
1705 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1706 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1707 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1708 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1709 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1710 }
1711
1712 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1713 struct si_shader *shader)
1714 {
1715 switch (shader->selector->type) {
1716 case PIPE_SHADER_VERTEX:
1717 if (shader->key.as_ls)
1718 si_shader_ls(sscreen, shader);
1719 else if (shader->key.as_es)
1720 si_shader_es(sscreen, shader);
1721 else if (shader->key.as_ngg)
1722 gfx10_shader_ngg(sscreen, shader);
1723 else
1724 si_shader_vs(sscreen, shader, NULL);
1725 break;
1726 case PIPE_SHADER_TESS_CTRL:
1727 si_shader_hs(sscreen, shader);
1728 break;
1729 case PIPE_SHADER_TESS_EVAL:
1730 if (shader->key.as_es)
1731 si_shader_es(sscreen, shader);
1732 else if (shader->key.as_ngg)
1733 gfx10_shader_ngg(sscreen, shader);
1734 else
1735 si_shader_vs(sscreen, shader, NULL);
1736 break;
1737 case PIPE_SHADER_GEOMETRY:
1738 if (shader->key.as_ngg)
1739 gfx10_shader_ngg(sscreen, shader);
1740 else
1741 si_shader_gs(sscreen, shader);
1742 break;
1743 case PIPE_SHADER_FRAGMENT:
1744 si_shader_ps(sscreen, shader);
1745 break;
1746 default:
1747 assert(0);
1748 }
1749 }
1750
1751 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1752 {
1753 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1754 return sctx->queued.named.dsa->alpha_func;
1755 }
1756
1757 void si_shader_selector_key_vs(struct si_context *sctx,
1758 struct si_shader_selector *vs,
1759 struct si_shader_key *key,
1760 struct si_vs_prolog_bits *prolog_key)
1761 {
1762 if (!sctx->vertex_elements ||
1763 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1764 return;
1765
1766 struct si_vertex_elements *elts = sctx->vertex_elements;
1767
1768 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1769 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1770 prolog_key->unpack_instance_id_from_vertex_id =
1771 sctx->prim_discard_cs_instancing;
1772
1773 /* Prefer a monolithic shader to allow scheduling divisions around
1774 * VBO loads. */
1775 if (prolog_key->instance_divisor_is_fetched)
1776 key->opt.prefer_mono = 1;
1777
1778 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1779 unsigned count_mask = (1 << count) - 1;
1780 unsigned fix = elts->fix_fetch_always & count_mask;
1781 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1782
1783 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1784 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1785 while (mask) {
1786 unsigned i = u_bit_scan(&mask);
1787 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1788 unsigned vbidx = elts->vertex_buffer_index[i];
1789 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1790 unsigned align_mask = (1 << log_hw_load_size) - 1;
1791 if (vb->buffer_offset & align_mask ||
1792 vb->stride & align_mask) {
1793 fix |= 1 << i;
1794 opencode |= 1 << i;
1795 }
1796 }
1797 }
1798
1799 while (fix) {
1800 unsigned i = u_bit_scan(&fix);
1801 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1802 }
1803 key->mono.vs_fetch_opencode = opencode;
1804 }
1805
1806 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1807 struct si_shader_selector *vs,
1808 struct si_shader_key *key)
1809 {
1810 struct si_shader_selector *ps = sctx->ps_shader.cso;
1811
1812 key->opt.clip_disable =
1813 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1814 (vs->info.clipdist_writemask ||
1815 vs->info.writes_clipvertex) &&
1816 !vs->info.culldist_writemask;
1817
1818 /* Find out if PS is disabled. */
1819 bool ps_disabled = true;
1820 if (ps) {
1821 bool ps_modifies_zs = ps->info.uses_kill ||
1822 ps->info.writes_z ||
1823 ps->info.writes_stencil ||
1824 ps->info.writes_samplemask ||
1825 sctx->queued.named.blend->alpha_to_coverage ||
1826 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1827 unsigned ps_colormask = si_get_total_colormask(sctx);
1828
1829 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1830 (!ps_colormask &&
1831 !ps_modifies_zs &&
1832 !ps->info.writes_memory);
1833 }
1834
1835 /* Find out which VS outputs aren't used by the PS. */
1836 uint64_t outputs_written = vs->outputs_written_before_ps;
1837 uint64_t inputs_read = 0;
1838
1839 /* Ignore outputs that are not passed from VS to PS. */
1840 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1841 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1842 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1843
1844 if (!ps_disabled) {
1845 inputs_read = ps->inputs_read;
1846 }
1847
1848 uint64_t linked = outputs_written & inputs_read;
1849
1850 key->opt.kill_outputs = ~linked & outputs_written;
1851 }
1852
1853 /* Compute the key for the hw shader variant */
1854 static inline void si_shader_selector_key(struct pipe_context *ctx,
1855 struct si_shader_selector *sel,
1856 union si_vgt_stages_key stages_key,
1857 struct si_shader_key *key)
1858 {
1859 struct si_context *sctx = (struct si_context *)ctx;
1860
1861 memset(key, 0, sizeof(*key));
1862
1863 switch (sel->type) {
1864 case PIPE_SHADER_VERTEX:
1865 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1866
1867 if (sctx->tes_shader.cso)
1868 key->as_ls = 1;
1869 else if (sctx->gs_shader.cso) {
1870 key->as_es = 1;
1871 key->as_ngg = stages_key.u.ngg;
1872 } else {
1873 key->as_ngg = stages_key.u.ngg;
1874 si_shader_selector_key_hw_vs(sctx, sel, key);
1875
1876 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1877 key->mono.u.vs_export_prim_id = 1;
1878 }
1879 break;
1880 case PIPE_SHADER_TESS_CTRL:
1881 if (sctx->chip_class >= GFX9) {
1882 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1883 key, &key->part.tcs.ls_prolog);
1884 key->part.tcs.ls = sctx->vs_shader.cso;
1885
1886 /* When the LS VGPR fix is needed, monolithic shaders
1887 * can:
1888 * - avoid initializing EXEC in both the LS prolog
1889 * and the LS main part when !vs_needs_prolog
1890 * - remove the fixup for unused input VGPRs
1891 */
1892 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1893
1894 /* The LS output / HS input layout can be communicated
1895 * directly instead of via user SGPRs for merged LS-HS.
1896 * The LS VGPR fix prefers this too.
1897 */
1898 key->opt.prefer_mono = 1;
1899 }
1900
1901 key->part.tcs.epilog.prim_mode =
1902 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1903 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1904 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1905 key->part.tcs.epilog.tes_reads_tess_factors =
1906 sctx->tes_shader.cso->info.reads_tess_factors;
1907
1908 if (sel == sctx->fixed_func_tcs_shader.cso)
1909 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1910 break;
1911 case PIPE_SHADER_TESS_EVAL:
1912 key->as_ngg = stages_key.u.ngg;
1913
1914 if (sctx->gs_shader.cso)
1915 key->as_es = 1;
1916 else {
1917 si_shader_selector_key_hw_vs(sctx, sel, key);
1918
1919 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1920 key->mono.u.vs_export_prim_id = 1;
1921 }
1922 break;
1923 case PIPE_SHADER_GEOMETRY:
1924 if (sctx->chip_class >= GFX9) {
1925 if (sctx->tes_shader.cso) {
1926 key->part.gs.es = sctx->tes_shader.cso;
1927 } else {
1928 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1929 key, &key->part.gs.vs_prolog);
1930 key->part.gs.es = sctx->vs_shader.cso;
1931 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1932 }
1933
1934 key->as_ngg = stages_key.u.ngg;
1935
1936 /* Merged ES-GS can have unbalanced wave usage.
1937 *
1938 * ES threads are per-vertex, while GS threads are
1939 * per-primitive. So without any amplification, there
1940 * are fewer GS threads than ES threads, which can result
1941 * in empty (no-op) GS waves. With too much amplification,
1942 * there are more GS threads than ES threads, which
1943 * can result in empty (no-op) ES waves.
1944 *
1945 * Non-monolithic shaders are implemented by setting EXEC
1946 * at the beginning of shader parts, and don't jump to
1947 * the end if EXEC is 0.
1948 *
1949 * Monolithic shaders use conditional blocks, so they can
1950 * jump and skip empty waves of ES or GS. So set this to
1951 * always use optimized variants, which are monolithic.
1952 */
1953 key->opt.prefer_mono = 1;
1954 }
1955 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1956 break;
1957 case PIPE_SHADER_FRAGMENT: {
1958 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1959 struct si_state_blend *blend = sctx->queued.named.blend;
1960
1961 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1962 sel->info.colors_written == 0x1)
1963 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1964
1965 /* Select the shader color format based on whether
1966 * blending or alpha are needed.
1967 */
1968 key->part.ps.epilog.spi_shader_col_format =
1969 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1970 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1971 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1972 sctx->framebuffer.spi_shader_col_format_blend) |
1973 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1974 sctx->framebuffer.spi_shader_col_format_alpha) |
1975 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1976 sctx->framebuffer.spi_shader_col_format);
1977 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1978
1979 /* The output for dual source blending should have
1980 * the same format as the first output.
1981 */
1982 if (blend->dual_src_blend) {
1983 key->part.ps.epilog.spi_shader_col_format |=
1984 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1985 }
1986
1987 /* If alpha-to-coverage is enabled, we have to export alpha
1988 * even if there is no color buffer.
1989 */
1990 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1991 blend->alpha_to_coverage)
1992 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1993
1994 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1995 * to the range supported by the type if a channel has less
1996 * than 16 bits and the export format is 16_ABGR.
1997 */
1998 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1999 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
2000 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
2001 }
2002
2003 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
2004 if (!key->part.ps.epilog.last_cbuf) {
2005 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
2006 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
2007 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
2008 }
2009
2010 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
2011 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
2012
2013 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
2014 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
2015
2016 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
2017 rs->multisample_enable;
2018
2019 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
2020 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
2021 (is_line && rs->line_smooth)) &&
2022 sctx->framebuffer.nr_samples <= 1;
2023 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2024
2025 if (sctx->ps_iter_samples > 1 &&
2026 sel->info.reads_samplemask) {
2027 key->part.ps.prolog.samplemask_log_ps_iter =
2028 util_logbase2(sctx->ps_iter_samples);
2029 }
2030
2031 if (rs->force_persample_interp &&
2032 rs->multisample_enable &&
2033 sctx->framebuffer.nr_samples > 1 &&
2034 sctx->ps_iter_samples > 1) {
2035 key->part.ps.prolog.force_persp_sample_interp =
2036 sel->info.uses_persp_center ||
2037 sel->info.uses_persp_centroid;
2038
2039 key->part.ps.prolog.force_linear_sample_interp =
2040 sel->info.uses_linear_center ||
2041 sel->info.uses_linear_centroid;
2042 } else if (rs->multisample_enable &&
2043 sctx->framebuffer.nr_samples > 1) {
2044 key->part.ps.prolog.bc_optimize_for_persp =
2045 sel->info.uses_persp_center &&
2046 sel->info.uses_persp_centroid;
2047 key->part.ps.prolog.bc_optimize_for_linear =
2048 sel->info.uses_linear_center &&
2049 sel->info.uses_linear_centroid;
2050 } else {
2051 /* Make sure SPI doesn't compute more than 1 pair
2052 * of (i,j), which is the optimization here. */
2053 key->part.ps.prolog.force_persp_center_interp =
2054 sel->info.uses_persp_center +
2055 sel->info.uses_persp_centroid +
2056 sel->info.uses_persp_sample > 1;
2057
2058 key->part.ps.prolog.force_linear_center_interp =
2059 sel->info.uses_linear_center +
2060 sel->info.uses_linear_centroid +
2061 sel->info.uses_linear_sample > 1;
2062
2063 if (sel->info.uses_persp_opcode_interp_sample ||
2064 sel->info.uses_linear_opcode_interp_sample)
2065 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2066 }
2067
2068 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2069
2070 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2071 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2072 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2073 struct pipe_resource *tex = cb0->texture;
2074
2075 /* 1D textures are allocated and used as 2D on GFX9. */
2076 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2077 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2078 (tex->target == PIPE_TEXTURE_1D ||
2079 tex->target == PIPE_TEXTURE_1D_ARRAY);
2080 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2081 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2082 tex->target == PIPE_TEXTURE_CUBE ||
2083 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2084 tex->target == PIPE_TEXTURE_3D;
2085 }
2086 break;
2087 }
2088 default:
2089 assert(0);
2090 }
2091
2092 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2093 memset(&key->opt, 0, sizeof(key->opt));
2094 }
2095
2096 static void si_build_shader_variant(struct si_shader *shader,
2097 int thread_index,
2098 bool low_priority)
2099 {
2100 struct si_shader_selector *sel = shader->selector;
2101 struct si_screen *sscreen = sel->screen;
2102 struct ac_llvm_compiler *compiler;
2103 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2104
2105 if (thread_index >= 0) {
2106 if (low_priority) {
2107 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2108 compiler = &sscreen->compiler_lowp[thread_index];
2109 } else {
2110 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2111 compiler = &sscreen->compiler[thread_index];
2112 }
2113 if (!debug->async)
2114 debug = NULL;
2115 } else {
2116 assert(!low_priority);
2117 compiler = shader->compiler_ctx_state.compiler;
2118 }
2119
2120 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2121 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2122 sel->type);
2123 shader->compilation_failed = true;
2124 return;
2125 }
2126
2127 if (shader->compiler_ctx_state.is_debug_context) {
2128 FILE *f = open_memstream(&shader->shader_log,
2129 &shader->shader_log_size);
2130 if (f) {
2131 si_shader_dump(sscreen, shader, NULL, f, false);
2132 fclose(f);
2133 }
2134 }
2135
2136 si_shader_init_pm4_state(sscreen, shader);
2137 }
2138
2139 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2140 {
2141 struct si_shader *shader = (struct si_shader *)job;
2142
2143 assert(thread_index >= 0);
2144
2145 si_build_shader_variant(shader, thread_index, true);
2146 }
2147
2148 static const struct si_shader_key zeroed;
2149
2150 static bool si_check_missing_main_part(struct si_screen *sscreen,
2151 struct si_shader_selector *sel,
2152 struct si_compiler_ctx_state *compiler_state,
2153 struct si_shader_key *key)
2154 {
2155 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2156
2157 if (!*mainp) {
2158 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2159
2160 if (!main_part)
2161 return false;
2162
2163 /* We can leave the fence as permanently signaled because the
2164 * main part becomes visible globally only after it has been
2165 * compiled. */
2166 util_queue_fence_init(&main_part->ready);
2167
2168 main_part->selector = sel;
2169 main_part->key.as_es = key->as_es;
2170 main_part->key.as_ls = key->as_ls;
2171 main_part->key.as_ngg = key->as_ngg;
2172 main_part->is_monolithic = false;
2173
2174 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2175 main_part, &compiler_state->debug) != 0) {
2176 FREE(main_part);
2177 return false;
2178 }
2179 *mainp = main_part;
2180 }
2181 return true;
2182 }
2183
2184 /**
2185 * Select a shader variant according to the shader key.
2186 *
2187 * \param optimized_or_none If the key describes an optimized shader variant and
2188 * the compilation isn't finished, don't select any
2189 * shader and return an error.
2190 */
2191 int si_shader_select_with_key(struct si_screen *sscreen,
2192 struct si_shader_ctx_state *state,
2193 struct si_compiler_ctx_state *compiler_state,
2194 struct si_shader_key *key,
2195 int thread_index,
2196 bool optimized_or_none)
2197 {
2198 struct si_shader_selector *sel = state->cso;
2199 struct si_shader_selector *previous_stage_sel = NULL;
2200 struct si_shader *current = state->current;
2201 struct si_shader *iter, *shader = NULL;
2202
2203 again:
2204 /* Check if we don't need to change anything.
2205 * This path is also used for most shaders that don't need multiple
2206 * variants, it will cost just a computation of the key and this
2207 * test. */
2208 if (likely(current &&
2209 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2210 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2211 if (current->is_optimized) {
2212 if (optimized_or_none)
2213 return -1;
2214
2215 memset(&key->opt, 0, sizeof(key->opt));
2216 goto current_not_ready;
2217 }
2218
2219 util_queue_fence_wait(&current->ready);
2220 }
2221
2222 return current->compilation_failed ? -1 : 0;
2223 }
2224 current_not_ready:
2225
2226 /* This must be done before the mutex is locked, because async GS
2227 * compilation calls this function too, and therefore must enter
2228 * the mutex first.
2229 *
2230 * Only wait if we are in a draw call. Don't wait if we are
2231 * in a compiler thread.
2232 */
2233 if (thread_index < 0)
2234 util_queue_fence_wait(&sel->ready);
2235
2236 mtx_lock(&sel->mutex);
2237
2238 /* Find the shader variant. */
2239 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2240 /* Don't check the "current" shader. We checked it above. */
2241 if (current != iter &&
2242 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2243 mtx_unlock(&sel->mutex);
2244
2245 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2246 /* If it's an optimized shader and its compilation has
2247 * been started but isn't done, use the unoptimized
2248 * shader so as not to cause a stall due to compilation.
2249 */
2250 if (iter->is_optimized) {
2251 if (optimized_or_none)
2252 return -1;
2253 memset(&key->opt, 0, sizeof(key->opt));
2254 goto again;
2255 }
2256
2257 util_queue_fence_wait(&iter->ready);
2258 }
2259
2260 if (iter->compilation_failed) {
2261 return -1; /* skip the draw call */
2262 }
2263
2264 state->current = iter;
2265 return 0;
2266 }
2267 }
2268
2269 /* Build a new shader. */
2270 shader = CALLOC_STRUCT(si_shader);
2271 if (!shader) {
2272 mtx_unlock(&sel->mutex);
2273 return -ENOMEM;
2274 }
2275
2276 util_queue_fence_init(&shader->ready);
2277
2278 shader->selector = sel;
2279 shader->key = *key;
2280 shader->compiler_ctx_state = *compiler_state;
2281
2282 /* If this is a merged shader, get the first shader's selector. */
2283 if (sscreen->info.chip_class >= GFX9) {
2284 if (sel->type == PIPE_SHADER_TESS_CTRL)
2285 previous_stage_sel = key->part.tcs.ls;
2286 else if (sel->type == PIPE_SHADER_GEOMETRY)
2287 previous_stage_sel = key->part.gs.es;
2288
2289 /* We need to wait for the previous shader. */
2290 if (previous_stage_sel && thread_index < 0)
2291 util_queue_fence_wait(&previous_stage_sel->ready);
2292 }
2293
2294 bool is_pure_monolithic =
2295 sscreen->use_monolithic_shaders ||
2296 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2297
2298 /* Compile the main shader part if it doesn't exist. This can happen
2299 * if the initial guess was wrong.
2300 *
2301 * The prim discard CS doesn't need the main shader part.
2302 */
2303 if (!is_pure_monolithic &&
2304 !key->opt.vs_as_prim_discard_cs) {
2305 bool ok = true;
2306
2307 /* Make sure the main shader part is present. This is needed
2308 * for shaders that can be compiled as VS, LS, or ES, and only
2309 * one of them is compiled at creation.
2310 *
2311 * It is also needed for GS, which can be compiled as non-NGG
2312 * and NGG.
2313 *
2314 * For merged shaders, check that the starting shader's main
2315 * part is present.
2316 */
2317 if (previous_stage_sel) {
2318 struct si_shader_key shader1_key = zeroed;
2319
2320 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2321 shader1_key.as_ls = 1;
2322 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2323 shader1_key.as_es = 1;
2324 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2325 } else {
2326 assert(0);
2327 }
2328
2329 mtx_lock(&previous_stage_sel->mutex);
2330 ok = si_check_missing_main_part(sscreen,
2331 previous_stage_sel,
2332 compiler_state, &shader1_key);
2333 mtx_unlock(&previous_stage_sel->mutex);
2334 }
2335
2336 if (ok) {
2337 ok = si_check_missing_main_part(sscreen, sel,
2338 compiler_state, key);
2339 }
2340
2341 if (!ok) {
2342 FREE(shader);
2343 mtx_unlock(&sel->mutex);
2344 return -ENOMEM; /* skip the draw call */
2345 }
2346 }
2347
2348 /* Keep the reference to the 1st shader of merged shaders, so that
2349 * Gallium can't destroy it before we destroy the 2nd shader.
2350 *
2351 * Set sctx = NULL, because it's unused if we're not releasing
2352 * the shader, and we don't have any sctx here.
2353 */
2354 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2355 previous_stage_sel);
2356
2357 /* Monolithic-only shaders don't make a distinction between optimized
2358 * and unoptimized. */
2359 shader->is_monolithic =
2360 is_pure_monolithic ||
2361 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2362
2363 /* The prim discard CS is always optimized. */
2364 shader->is_optimized =
2365 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2366 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2367
2368 /* If it's an optimized shader, compile it asynchronously. */
2369 if (shader->is_optimized && thread_index < 0) {
2370 /* Compile it asynchronously. */
2371 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2372 shader, &shader->ready,
2373 si_build_shader_variant_low_priority, NULL);
2374
2375 /* Add only after the ready fence was reset, to guard against a
2376 * race with si_bind_XX_shader. */
2377 if (!sel->last_variant) {
2378 sel->first_variant = shader;
2379 sel->last_variant = shader;
2380 } else {
2381 sel->last_variant->next_variant = shader;
2382 sel->last_variant = shader;
2383 }
2384
2385 /* Use the default (unoptimized) shader for now. */
2386 memset(&key->opt, 0, sizeof(key->opt));
2387 mtx_unlock(&sel->mutex);
2388
2389 if (sscreen->options.sync_compile)
2390 util_queue_fence_wait(&shader->ready);
2391
2392 if (optimized_or_none)
2393 return -1;
2394 goto again;
2395 }
2396
2397 /* Reset the fence before adding to the variant list. */
2398 util_queue_fence_reset(&shader->ready);
2399
2400 if (!sel->last_variant) {
2401 sel->first_variant = shader;
2402 sel->last_variant = shader;
2403 } else {
2404 sel->last_variant->next_variant = shader;
2405 sel->last_variant = shader;
2406 }
2407
2408 mtx_unlock(&sel->mutex);
2409
2410 assert(!shader->is_optimized);
2411 si_build_shader_variant(shader, thread_index, false);
2412
2413 util_queue_fence_signal(&shader->ready);
2414
2415 if (!shader->compilation_failed)
2416 state->current = shader;
2417
2418 return shader->compilation_failed ? -1 : 0;
2419 }
2420
2421 static int si_shader_select(struct pipe_context *ctx,
2422 struct si_shader_ctx_state *state,
2423 union si_vgt_stages_key stages_key,
2424 struct si_compiler_ctx_state *compiler_state)
2425 {
2426 struct si_context *sctx = (struct si_context *)ctx;
2427 struct si_shader_key key;
2428
2429 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2430 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2431 &key, -1, false);
2432 }
2433
2434 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2435 bool streamout,
2436 struct si_shader_key *key)
2437 {
2438 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2439
2440 switch (info->processor) {
2441 case PIPE_SHADER_VERTEX:
2442 switch (next_shader) {
2443 case PIPE_SHADER_GEOMETRY:
2444 key->as_es = 1;
2445 break;
2446 case PIPE_SHADER_TESS_CTRL:
2447 case PIPE_SHADER_TESS_EVAL:
2448 key->as_ls = 1;
2449 break;
2450 default:
2451 /* If POSITION isn't written, it can only be a HW VS
2452 * if streamout is used. If streamout isn't used,
2453 * assume that it's a HW LS. (the next shader is TCS)
2454 * This heuristic is needed for separate shader objects.
2455 */
2456 if (!info->writes_position && !streamout)
2457 key->as_ls = 1;
2458 }
2459 break;
2460
2461 case PIPE_SHADER_TESS_EVAL:
2462 if (next_shader == PIPE_SHADER_GEOMETRY ||
2463 !info->writes_position)
2464 key->as_es = 1;
2465 break;
2466 }
2467 }
2468
2469 /**
2470 * Compile the main shader part or the monolithic shader as part of
2471 * si_shader_selector initialization. Since it can be done asynchronously,
2472 * there is no way to report compile failures to applications.
2473 */
2474 static void si_init_shader_selector_async(void *job, int thread_index)
2475 {
2476 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2477 struct si_screen *sscreen = sel->screen;
2478 struct ac_llvm_compiler *compiler;
2479 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2480
2481 assert(!debug->debug_message || debug->async);
2482 assert(thread_index >= 0);
2483 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2484 compiler = &sscreen->compiler[thread_index];
2485
2486 if (sel->nir)
2487 si_lower_nir(sel);
2488
2489 /* Compile the main shader part for use with a prolog and/or epilog.
2490 * If this fails, the driver will try to compile a monolithic shader
2491 * on demand.
2492 */
2493 if (!sscreen->use_monolithic_shaders) {
2494 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2495 void *ir_binary = NULL;
2496
2497 if (!shader) {
2498 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2499 return;
2500 }
2501
2502 /* We can leave the fence signaled because use of the default
2503 * main part is guarded by the selector's ready fence. */
2504 util_queue_fence_init(&shader->ready);
2505
2506 shader->selector = sel;
2507 shader->is_monolithic = false;
2508 si_parse_next_shader_property(&sel->info,
2509 sel->so.num_outputs != 0,
2510 &shader->key);
2511
2512 if (sscreen->use_ngg &&
2513 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2514 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2515 sel->type == PIPE_SHADER_TESS_EVAL ||
2516 sel->type == PIPE_SHADER_GEOMETRY))
2517 shader->key.as_ngg = 1;
2518
2519 if (sel->tokens || sel->nir) {
2520 ir_binary = si_get_ir_binary(sel, shader->key.as_ngg,
2521 shader->key.as_es);
2522 }
2523
2524 /* Try to load the shader from the shader cache. */
2525 mtx_lock(&sscreen->shader_cache_mutex);
2526
2527 if (ir_binary &&
2528 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2529 mtx_unlock(&sscreen->shader_cache_mutex);
2530 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2531 } else {
2532 mtx_unlock(&sscreen->shader_cache_mutex);
2533
2534 /* Compile the shader if it hasn't been loaded from the cache. */
2535 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2536 debug) != 0) {
2537 FREE(shader);
2538 FREE(ir_binary);
2539 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2540 return;
2541 }
2542
2543 if (ir_binary) {
2544 mtx_lock(&sscreen->shader_cache_mutex);
2545 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2546 FREE(ir_binary);
2547 mtx_unlock(&sscreen->shader_cache_mutex);
2548 }
2549 }
2550
2551 *si_get_main_shader_part(sel, &shader->key) = shader;
2552
2553 /* Unset "outputs_written" flags for outputs converted to
2554 * DEFAULT_VAL, so that later inter-shader optimizations don't
2555 * try to eliminate outputs that don't exist in the final
2556 * shader.
2557 *
2558 * This is only done if non-monolithic shaders are enabled.
2559 */
2560 if ((sel->type == PIPE_SHADER_VERTEX ||
2561 sel->type == PIPE_SHADER_TESS_EVAL) &&
2562 !shader->key.as_ls &&
2563 !shader->key.as_es) {
2564 unsigned i;
2565
2566 for (i = 0; i < sel->info.num_outputs; i++) {
2567 unsigned offset = shader->info.vs_output_param_offset[i];
2568
2569 if (offset <= AC_EXP_PARAM_OFFSET_31)
2570 continue;
2571
2572 unsigned name = sel->info.output_semantic_name[i];
2573 unsigned index = sel->info.output_semantic_index[i];
2574 unsigned id;
2575
2576 switch (name) {
2577 case TGSI_SEMANTIC_GENERIC:
2578 /* don't process indices the function can't handle */
2579 if (index >= SI_MAX_IO_GENERIC)
2580 break;
2581 /* fall through */
2582 default:
2583 id = si_shader_io_get_unique_index(name, index, true);
2584 sel->outputs_written_before_ps &= ~(1ull << id);
2585 break;
2586 case TGSI_SEMANTIC_POSITION: /* ignore these */
2587 case TGSI_SEMANTIC_PSIZE:
2588 case TGSI_SEMANTIC_CLIPVERTEX:
2589 case TGSI_SEMANTIC_EDGEFLAG:
2590 break;
2591 }
2592 }
2593 }
2594 }
2595
2596 /* The GS copy shader is always pre-compiled. */
2597 if (sel->type == PIPE_SHADER_GEOMETRY &&
2598 (!sscreen->use_ngg ||
2599 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2600 sel->tess_turns_off_ngg)) {
2601 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2602 if (!sel->gs_copy_shader) {
2603 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2604 return;
2605 }
2606
2607 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2608 }
2609 }
2610
2611 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2612 struct util_queue_fence *ready_fence,
2613 struct si_compiler_ctx_state *compiler_ctx_state,
2614 void *job, util_queue_execute_func execute)
2615 {
2616 util_queue_fence_init(ready_fence);
2617
2618 struct util_async_debug_callback async_debug;
2619 bool debug =
2620 (sctx->debug.debug_message && !sctx->debug.async) ||
2621 sctx->is_debug ||
2622 si_can_dump_shader(sctx->screen, processor);
2623
2624 if (debug) {
2625 u_async_debug_init(&async_debug);
2626 compiler_ctx_state->debug = async_debug.base;
2627 }
2628
2629 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2630 ready_fence, execute, NULL);
2631
2632 if (debug) {
2633 util_queue_fence_wait(ready_fence);
2634 u_async_debug_drain(&async_debug, &sctx->debug);
2635 u_async_debug_cleanup(&async_debug);
2636 }
2637
2638 if (sctx->screen->options.sync_compile)
2639 util_queue_fence_wait(ready_fence);
2640 }
2641
2642 /* Return descriptor slot usage masks from the given shader info. */
2643 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2644 uint32_t *const_and_shader_buffers,
2645 uint64_t *samplers_and_images)
2646 {
2647 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2648
2649 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2650 num_constbufs = util_last_bit(info->const_buffers_declared);
2651 /* two 8-byte images share one 16-byte slot */
2652 num_images = align(util_last_bit(info->images_declared), 2);
2653 num_samplers = util_last_bit(info->samplers_declared);
2654
2655 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2656 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2657 *const_and_shader_buffers =
2658 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2659
2660 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2661 start = si_get_image_slot(num_images - 1) / 2;
2662 *samplers_and_images =
2663 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2664 }
2665
2666 static void *si_create_shader_selector(struct pipe_context *ctx,
2667 const struct pipe_shader_state *state)
2668 {
2669 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2670 struct si_context *sctx = (struct si_context*)ctx;
2671 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2672 int i;
2673
2674 if (!sel)
2675 return NULL;
2676
2677 pipe_reference_init(&sel->reference, 1);
2678 sel->screen = sscreen;
2679 sel->compiler_ctx_state.debug = sctx->debug;
2680 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2681
2682 sel->so = state->stream_output;
2683
2684 if (state->type == PIPE_SHADER_IR_TGSI &&
2685 !sscreen->options.enable_nir) {
2686 sel->tokens = tgsi_dup_tokens(state->tokens);
2687 if (!sel->tokens) {
2688 FREE(sel);
2689 return NULL;
2690 }
2691
2692 tgsi_scan_shader(state->tokens, &sel->info);
2693 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2694
2695 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2696 if (sel->info.uses_persp_opcode_interp_centroid)
2697 sel->info.uses_persp_centroid = true;
2698
2699 if (sel->info.uses_linear_opcode_interp_centroid)
2700 sel->info.uses_linear_centroid = true;
2701
2702 if (sel->info.uses_persp_opcode_interp_offset ||
2703 sel->info.uses_persp_opcode_interp_sample)
2704 sel->info.uses_persp_center = true;
2705
2706 if (sel->info.uses_linear_opcode_interp_offset ||
2707 sel->info.uses_linear_opcode_interp_sample)
2708 sel->info.uses_linear_center = true;
2709 } else {
2710 if (state->type == PIPE_SHADER_IR_TGSI) {
2711 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2712 } else {
2713 assert(state->type == PIPE_SHADER_IR_NIR);
2714 sel->nir = state->ir.nir;
2715 }
2716
2717 si_nir_lower_ps_inputs(sel->nir);
2718 si_nir_opts(sel->nir);
2719 si_nir_scan_shader(sel->nir, &sel->info);
2720 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2721 }
2722
2723 sel->type = sel->info.processor;
2724 p_atomic_inc(&sscreen->num_shaders_created);
2725 si_get_active_slot_masks(&sel->info,
2726 &sel->active_const_and_shader_buffers,
2727 &sel->active_samplers_and_images);
2728
2729 /* Record which streamout buffers are enabled. */
2730 for (i = 0; i < sel->so.num_outputs; i++) {
2731 sel->enabled_streamout_buffer_mask |=
2732 (1 << sel->so.output[i].output_buffer) <<
2733 (sel->so.output[i].stream * 4);
2734 }
2735
2736 /* The prolog is a no-op if there are no inputs. */
2737 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2738 sel->info.num_inputs &&
2739 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2740
2741 sel->force_correct_derivs_after_kill =
2742 sel->type == PIPE_SHADER_FRAGMENT &&
2743 sel->info.uses_derivatives &&
2744 sel->info.uses_kill &&
2745 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2746
2747 sel->prim_discard_cs_allowed =
2748 sel->type == PIPE_SHADER_VERTEX &&
2749 !sel->info.uses_bindless_images &&
2750 !sel->info.uses_bindless_samplers &&
2751 !sel->info.writes_memory &&
2752 !sel->info.writes_viewport_index &&
2753 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2754 !sel->so.num_outputs;
2755
2756 switch (sel->type) {
2757 case PIPE_SHADER_GEOMETRY:
2758 sel->gs_output_prim =
2759 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2760
2761 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2762 sel->rast_prim = sel->gs_output_prim;
2763 if (util_rast_prim_is_triangles(sel->rast_prim))
2764 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2765
2766 sel->gs_max_out_vertices =
2767 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2768 sel->gs_num_invocations =
2769 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2770 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2771 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2772 sel->gs_max_out_vertices;
2773
2774 sel->max_gs_stream = 0;
2775 for (i = 0; i < sel->so.num_outputs; i++)
2776 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2777 sel->so.output[i].stream);
2778
2779 sel->gs_input_verts_per_prim =
2780 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2781
2782 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2783 sel->tess_turns_off_ngg =
2784 (sscreen->info.family == CHIP_NAVI10 ||
2785 sscreen->info.family == CHIP_NAVI12 ||
2786 sscreen->info.family == CHIP_NAVI14) &&
2787 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2788 break;
2789
2790 case PIPE_SHADER_TESS_CTRL:
2791 /* Always reserve space for these. */
2792 sel->patch_outputs_written |=
2793 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2794 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2795 /* fall through */
2796 case PIPE_SHADER_VERTEX:
2797 case PIPE_SHADER_TESS_EVAL:
2798 for (i = 0; i < sel->info.num_outputs; i++) {
2799 unsigned name = sel->info.output_semantic_name[i];
2800 unsigned index = sel->info.output_semantic_index[i];
2801
2802 switch (name) {
2803 case TGSI_SEMANTIC_TESSINNER:
2804 case TGSI_SEMANTIC_TESSOUTER:
2805 case TGSI_SEMANTIC_PATCH:
2806 sel->patch_outputs_written |=
2807 1ull << si_shader_io_get_unique_index_patch(name, index);
2808 break;
2809
2810 case TGSI_SEMANTIC_GENERIC:
2811 /* don't process indices the function can't handle */
2812 if (index >= SI_MAX_IO_GENERIC)
2813 break;
2814 /* fall through */
2815 default:
2816 sel->outputs_written |=
2817 1ull << si_shader_io_get_unique_index(name, index, false);
2818 sel->outputs_written_before_ps |=
2819 1ull << si_shader_io_get_unique_index(name, index, true);
2820 break;
2821 case TGSI_SEMANTIC_EDGEFLAG:
2822 break;
2823 }
2824 }
2825 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2826 sel->lshs_vertex_stride = sel->esgs_itemsize;
2827
2828 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2829 * will start on a different bank. (except for the maximum 32*16).
2830 */
2831 if (sel->lshs_vertex_stride < 32*16)
2832 sel->lshs_vertex_stride += 4;
2833
2834 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2835 * conflicts, i.e. each vertex will start at a different bank.
2836 */
2837 if (sctx->chip_class >= GFX9)
2838 sel->esgs_itemsize += 4;
2839
2840 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2841
2842 /* Only for TES: */
2843 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2844 sel->rast_prim = PIPE_PRIM_POINTS;
2845 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2846 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2847 else
2848 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2849 break;
2850
2851 case PIPE_SHADER_FRAGMENT:
2852 for (i = 0; i < sel->info.num_inputs; i++) {
2853 unsigned name = sel->info.input_semantic_name[i];
2854 unsigned index = sel->info.input_semantic_index[i];
2855
2856 switch (name) {
2857 case TGSI_SEMANTIC_GENERIC:
2858 /* don't process indices the function can't handle */
2859 if (index >= SI_MAX_IO_GENERIC)
2860 break;
2861 /* fall through */
2862 default:
2863 sel->inputs_read |=
2864 1ull << si_shader_io_get_unique_index(name, index, true);
2865 break;
2866 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2867 break;
2868 }
2869 }
2870
2871 for (i = 0; i < 8; i++)
2872 if (sel->info.colors_written & (1 << i))
2873 sel->colors_written_4bit |= 0xf << (4 * i);
2874
2875 for (i = 0; i < sel->info.num_inputs; i++) {
2876 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2877 int index = sel->info.input_semantic_index[i];
2878 sel->color_attr_index[index] = i;
2879 }
2880 }
2881 break;
2882 default:;
2883 }
2884
2885 /* PA_CL_VS_OUT_CNTL */
2886 if (sctx->chip_class <= GFX9)
2887 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2888
2889 sel->clipdist_mask = sel->info.writes_clipvertex ?
2890 SIX_BITS : sel->info.clipdist_writemask;
2891 sel->culldist_mask = sel->info.culldist_writemask <<
2892 sel->info.num_written_clipdistance;
2893
2894 /* DB_SHADER_CONTROL */
2895 sel->db_shader_control =
2896 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2897 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2898 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2899 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2900
2901 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2902 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2903 sel->db_shader_control |=
2904 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2905 break;
2906 case TGSI_FS_DEPTH_LAYOUT_LESS:
2907 sel->db_shader_control |=
2908 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2909 break;
2910 }
2911
2912 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2913 *
2914 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2915 * --|-----------|------------|------------|--------------------|-------------------|-------------
2916 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2917 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2918 * 2 | false | true | n/a | LateZ | 1 | 0
2919 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2920 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2921 *
2922 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2923 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2924 *
2925 * Don't use ReZ without profiling !!!
2926 *
2927 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2928 * shaders.
2929 */
2930 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2931 /* Cases 3, 4. */
2932 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2933 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2934 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2935 } else if (sel->info.writes_memory) {
2936 /* Case 2. */
2937 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2938 S_02880C_EXEC_ON_HIER_FAIL(1);
2939 } else {
2940 /* Case 1. */
2941 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2942 }
2943
2944 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2945 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2946
2947 (void) mtx_init(&sel->mutex, mtx_plain);
2948
2949 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2950 &sel->compiler_ctx_state, sel,
2951 si_init_shader_selector_async);
2952 return sel;
2953 }
2954
2955 static void si_update_streamout_state(struct si_context *sctx)
2956 {
2957 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2958
2959 if (!shader_with_so)
2960 return;
2961
2962 sctx->streamout.enabled_stream_buffers_mask =
2963 shader_with_so->enabled_streamout_buffer_mask;
2964 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2965 }
2966
2967 static void si_update_clip_regs(struct si_context *sctx,
2968 struct si_shader_selector *old_hw_vs,
2969 struct si_shader *old_hw_vs_variant,
2970 struct si_shader_selector *next_hw_vs,
2971 struct si_shader *next_hw_vs_variant)
2972 {
2973 if (next_hw_vs &&
2974 (!old_hw_vs ||
2975 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2976 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2977 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2978 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2979 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2980 !old_hw_vs_variant ||
2981 !next_hw_vs_variant ||
2982 old_hw_vs_variant->key.opt.clip_disable !=
2983 next_hw_vs_variant->key.opt.clip_disable))
2984 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2985 }
2986
2987 static void si_update_common_shader_state(struct si_context *sctx)
2988 {
2989 sctx->uses_bindless_samplers =
2990 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2991 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2992 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2993 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2994 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2995 sctx->uses_bindless_images =
2996 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2997 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2998 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2999 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3000 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3001 sctx->do_update_shaders = true;
3002 }
3003
3004 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3005 {
3006 struct si_context *sctx = (struct si_context *)ctx;
3007 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3008 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3009 struct si_shader_selector *sel = state;
3010
3011 if (sctx->vs_shader.cso == sel)
3012 return;
3013
3014 sctx->vs_shader.cso = sel;
3015 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3016 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3017
3018 if (si_update_ngg(sctx))
3019 si_shader_change_notify(sctx);
3020
3021 si_update_common_shader_state(sctx);
3022 si_update_vs_viewport_state(sctx);
3023 si_set_active_descriptors_for_shader(sctx, sel);
3024 si_update_streamout_state(sctx);
3025 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3026 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3027 }
3028
3029 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3030 {
3031 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3032 (sctx->tes_shader.cso &&
3033 sctx->tes_shader.cso->info.uses_primid) ||
3034 (sctx->tcs_shader.cso &&
3035 sctx->tcs_shader.cso->info.uses_primid) ||
3036 (sctx->gs_shader.cso &&
3037 sctx->gs_shader.cso->info.uses_primid) ||
3038 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3039 sctx->ps_shader.cso->info.uses_primid);
3040 }
3041
3042 bool si_update_ngg(struct si_context *sctx)
3043 {
3044 if (!sctx->screen->use_ngg) {
3045 assert(!sctx->ngg);
3046 return false;
3047 }
3048
3049 bool new_ngg = true;
3050
3051 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3052 sctx->gs_shader.cso->tess_turns_off_ngg) {
3053 new_ngg = false;
3054 } else if (!sctx->screen->use_ngg_streamout) {
3055 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3056
3057 if ((last && last->so.num_outputs) ||
3058 sctx->streamout.prims_gen_query_enabled)
3059 new_ngg = false;
3060 }
3061
3062 if (new_ngg != sctx->ngg) {
3063 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3064 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3065 * pointers are set.
3066 */
3067 if ((sctx->family == CHIP_NAVI10 ||
3068 sctx->family == CHIP_NAVI12 ||
3069 sctx->family == CHIP_NAVI14) &&
3070 !new_ngg)
3071 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3072
3073 sctx->ngg = new_ngg;
3074 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3075 return true;
3076 }
3077 return false;
3078 }
3079
3080 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3081 {
3082 struct si_context *sctx = (struct si_context *)ctx;
3083 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3084 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3085 struct si_shader_selector *sel = state;
3086 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3087 bool ngg_changed;
3088
3089 if (sctx->gs_shader.cso == sel)
3090 return;
3091
3092 sctx->gs_shader.cso = sel;
3093 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3094 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3095
3096 si_update_common_shader_state(sctx);
3097 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3098
3099 ngg_changed = si_update_ngg(sctx);
3100 if (ngg_changed || enable_changed)
3101 si_shader_change_notify(sctx);
3102 if (enable_changed) {
3103 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3104 si_update_tess_uses_prim_id(sctx);
3105 }
3106 si_update_vs_viewport_state(sctx);
3107 si_set_active_descriptors_for_shader(sctx, sel);
3108 si_update_streamout_state(sctx);
3109 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3110 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3111 }
3112
3113 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3114 {
3115 struct si_context *sctx = (struct si_context *)ctx;
3116 struct si_shader_selector *sel = state;
3117 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3118
3119 if (sctx->tcs_shader.cso == sel)
3120 return;
3121
3122 sctx->tcs_shader.cso = sel;
3123 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3124 si_update_tess_uses_prim_id(sctx);
3125
3126 si_update_common_shader_state(sctx);
3127
3128 if (enable_changed)
3129 sctx->last_tcs = NULL; /* invalidate derived tess state */
3130
3131 si_set_active_descriptors_for_shader(sctx, sel);
3132 }
3133
3134 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3135 {
3136 struct si_context *sctx = (struct si_context *)ctx;
3137 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3138 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3139 struct si_shader_selector *sel = state;
3140 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3141
3142 if (sctx->tes_shader.cso == sel)
3143 return;
3144
3145 sctx->tes_shader.cso = sel;
3146 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3147 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3148 si_update_tess_uses_prim_id(sctx);
3149
3150 si_update_common_shader_state(sctx);
3151 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3152
3153 bool ngg_changed = si_update_ngg(sctx);
3154 if (ngg_changed || enable_changed)
3155 si_shader_change_notify(sctx);
3156 if (enable_changed)
3157 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3158 si_update_vs_viewport_state(sctx);
3159 si_set_active_descriptors_for_shader(sctx, sel);
3160 si_update_streamout_state(sctx);
3161 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3162 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3163 }
3164
3165 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3166 {
3167 struct si_context *sctx = (struct si_context *)ctx;
3168 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3169 struct si_shader_selector *sel = state;
3170
3171 /* skip if supplied shader is one already in use */
3172 if (old_sel == sel)
3173 return;
3174
3175 sctx->ps_shader.cso = sel;
3176 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3177
3178 si_update_common_shader_state(sctx);
3179 if (sel) {
3180 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3181 si_update_tess_uses_prim_id(sctx);
3182
3183 if (!old_sel ||
3184 old_sel->info.colors_written != sel->info.colors_written)
3185 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3186
3187 if (sctx->screen->has_out_of_order_rast &&
3188 (!old_sel ||
3189 old_sel->info.writes_memory != sel->info.writes_memory ||
3190 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3191 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3192 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3193 }
3194 si_set_active_descriptors_for_shader(sctx, sel);
3195 si_update_ps_colorbuf0_slot(sctx);
3196 }
3197
3198 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3199 {
3200 if (shader->is_optimized) {
3201 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3202 &shader->ready);
3203 }
3204
3205 util_queue_fence_destroy(&shader->ready);
3206
3207 if (shader->pm4) {
3208 /* If destroyed shaders were not unbound, the next compiled
3209 * shader variant could get the same pointer address and so
3210 * binding it to the same shader stage would be considered
3211 * a no-op, causing random behavior.
3212 */
3213 switch (shader->selector->type) {
3214 case PIPE_SHADER_VERTEX:
3215 if (shader->key.as_ls) {
3216 assert(sctx->chip_class <= GFX8);
3217 si_pm4_delete_state(sctx, ls, shader->pm4);
3218 } else if (shader->key.as_es) {
3219 assert(sctx->chip_class <= GFX8);
3220 si_pm4_delete_state(sctx, es, shader->pm4);
3221 } else if (shader->key.as_ngg) {
3222 si_pm4_delete_state(sctx, gs, shader->pm4);
3223 } else {
3224 si_pm4_delete_state(sctx, vs, shader->pm4);
3225 }
3226 break;
3227 case PIPE_SHADER_TESS_CTRL:
3228 si_pm4_delete_state(sctx, hs, shader->pm4);
3229 break;
3230 case PIPE_SHADER_TESS_EVAL:
3231 if (shader->key.as_es) {
3232 assert(sctx->chip_class <= GFX8);
3233 si_pm4_delete_state(sctx, es, shader->pm4);
3234 } else if (shader->key.as_ngg) {
3235 si_pm4_delete_state(sctx, gs, shader->pm4);
3236 } else {
3237 si_pm4_delete_state(sctx, vs, shader->pm4);
3238 }
3239 break;
3240 case PIPE_SHADER_GEOMETRY:
3241 if (shader->is_gs_copy_shader)
3242 si_pm4_delete_state(sctx, vs, shader->pm4);
3243 else
3244 si_pm4_delete_state(sctx, gs, shader->pm4);
3245 break;
3246 case PIPE_SHADER_FRAGMENT:
3247 si_pm4_delete_state(sctx, ps, shader->pm4);
3248 break;
3249 default:;
3250 }
3251 }
3252
3253 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3254 si_shader_destroy(shader);
3255 free(shader);
3256 }
3257
3258 void si_destroy_shader_selector(struct si_context *sctx,
3259 struct si_shader_selector *sel)
3260 {
3261 struct si_shader *p = sel->first_variant, *c;
3262 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3263 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3264 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3265 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3266 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3267 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3268 };
3269
3270 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3271
3272 if (current_shader[sel->type]->cso == sel) {
3273 current_shader[sel->type]->cso = NULL;
3274 current_shader[sel->type]->current = NULL;
3275 }
3276
3277 while (p) {
3278 c = p->next_variant;
3279 si_delete_shader(sctx, p);
3280 p = c;
3281 }
3282
3283 if (sel->main_shader_part)
3284 si_delete_shader(sctx, sel->main_shader_part);
3285 if (sel->main_shader_part_ls)
3286 si_delete_shader(sctx, sel->main_shader_part_ls);
3287 if (sel->main_shader_part_es)
3288 si_delete_shader(sctx, sel->main_shader_part_es);
3289 if (sel->main_shader_part_ngg)
3290 si_delete_shader(sctx, sel->main_shader_part_ngg);
3291 if (sel->gs_copy_shader)
3292 si_delete_shader(sctx, sel->gs_copy_shader);
3293
3294 util_queue_fence_destroy(&sel->ready);
3295 mtx_destroy(&sel->mutex);
3296 free(sel->tokens);
3297 ralloc_free(sel->nir);
3298 free(sel);
3299 }
3300
3301 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3302 {
3303 struct si_context *sctx = (struct si_context *)ctx;
3304 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3305
3306 si_shader_selector_reference(sctx, &sel, NULL);
3307 }
3308
3309 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3310 struct si_shader *vs, unsigned name,
3311 unsigned index, unsigned interpolate)
3312 {
3313 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3314 unsigned j, offset, ps_input_cntl = 0;
3315
3316 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3317 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3318 name == TGSI_SEMANTIC_PRIMID)
3319 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3320
3321 if (name == TGSI_SEMANTIC_PCOORD ||
3322 (name == TGSI_SEMANTIC_TEXCOORD &&
3323 sctx->sprite_coord_enable & (1 << index))) {
3324 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3325 }
3326
3327 for (j = 0; j < vsinfo->num_outputs; j++) {
3328 if (name == vsinfo->output_semantic_name[j] &&
3329 index == vsinfo->output_semantic_index[j]) {
3330 offset = vs->info.vs_output_param_offset[j];
3331
3332 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3333 /* The input is loaded from parameter memory. */
3334 ps_input_cntl |= S_028644_OFFSET(offset);
3335 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3336 if (offset == AC_EXP_PARAM_UNDEFINED) {
3337 /* This can happen with depth-only rendering. */
3338 offset = 0;
3339 } else {
3340 /* The input is a DEFAULT_VAL constant. */
3341 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3342 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3343 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3344 }
3345
3346 ps_input_cntl = S_028644_OFFSET(0x20) |
3347 S_028644_DEFAULT_VAL(offset);
3348 }
3349 break;
3350 }
3351 }
3352
3353 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3354 /* PrimID is written after the last output when HW VS is used. */
3355 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3356 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3357 /* No corresponding output found, load defaults into input.
3358 * Don't set any other bits.
3359 * (FLAT_SHADE=1 completely changes behavior) */
3360 ps_input_cntl = S_028644_OFFSET(0x20);
3361 /* D3D 9 behaviour. GL is undefined */
3362 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3363 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3364 }
3365 return ps_input_cntl;
3366 }
3367
3368 static void si_emit_spi_map(struct si_context *sctx)
3369 {
3370 struct si_shader *ps = sctx->ps_shader.current;
3371 struct si_shader *vs = si_get_vs_state(sctx);
3372 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3373 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3374 unsigned spi_ps_input_cntl[32];
3375
3376 if (!ps || !ps->selector->info.num_inputs)
3377 return;
3378
3379 num_interp = si_get_ps_num_interp(ps);
3380 assert(num_interp > 0);
3381
3382 for (i = 0; i < psinfo->num_inputs; i++) {
3383 unsigned name = psinfo->input_semantic_name[i];
3384 unsigned index = psinfo->input_semantic_index[i];
3385 unsigned interpolate = psinfo->input_interpolate[i];
3386
3387 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3388 index, interpolate);
3389
3390 if (name == TGSI_SEMANTIC_COLOR) {
3391 assert(index < ARRAY_SIZE(bcol_interp));
3392 bcol_interp[index] = interpolate;
3393 }
3394 }
3395
3396 if (ps->key.part.ps.prolog.color_two_side) {
3397 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3398
3399 for (i = 0; i < 2; i++) {
3400 if (!(psinfo->colors_read & (0xf << (i * 4))))
3401 continue;
3402
3403 spi_ps_input_cntl[num_written++] =
3404 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3405
3406 }
3407 }
3408 assert(num_interp == num_written);
3409
3410 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3411 /* Dota 2: Only ~16% of SPI map updates set different values. */
3412 /* Talos: Only ~9% of SPI map updates set different values. */
3413 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3414 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3415 spi_ps_input_cntl,
3416 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3417
3418 if (initial_cdw != sctx->gfx_cs->current.cdw)
3419 sctx->context_roll = true;
3420 }
3421
3422 /**
3423 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3424 */
3425 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3426 {
3427 if (sctx->init_config_has_vgt_flush)
3428 return;
3429
3430 /* Done by Vulkan before VGT_FLUSH. */
3431 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3432 si_pm4_cmd_add(sctx->init_config,
3433 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3434 si_pm4_cmd_end(sctx->init_config, false);
3435
3436 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3437 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3438 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3439 si_pm4_cmd_end(sctx->init_config, false);
3440 sctx->init_config_has_vgt_flush = true;
3441 }
3442
3443 /* Initialize state related to ESGS / GSVS ring buffers */
3444 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3445 {
3446 struct si_shader_selector *es =
3447 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3448 struct si_shader_selector *gs = sctx->gs_shader.cso;
3449 struct si_pm4_state *pm4;
3450
3451 /* Chip constants. */
3452 unsigned num_se = sctx->screen->info.max_se;
3453 unsigned wave_size = 64;
3454 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3455 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3456 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3457 */
3458 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3459 unsigned alignment = 256 * num_se;
3460 /* The maximum size is 63.999 MB per SE. */
3461 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3462
3463 /* Calculate the minimum size. */
3464 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3465 wave_size, alignment);
3466
3467 /* These are recommended sizes, not minimum sizes. */
3468 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3469 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3470 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3471 gs->max_gsvs_emit_size;
3472
3473 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3474 esgs_ring_size = align(esgs_ring_size, alignment);
3475 gsvs_ring_size = align(gsvs_ring_size, alignment);
3476
3477 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3478 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3479
3480 /* Some rings don't have to be allocated if shaders don't use them.
3481 * (e.g. no varyings between ES and GS or GS and VS)
3482 *
3483 * GFX9 doesn't have the ESGS ring.
3484 */
3485 bool update_esgs = sctx->chip_class <= GFX8 &&
3486 esgs_ring_size &&
3487 (!sctx->esgs_ring ||
3488 sctx->esgs_ring->width0 < esgs_ring_size);
3489 bool update_gsvs = gsvs_ring_size &&
3490 (!sctx->gsvs_ring ||
3491 sctx->gsvs_ring->width0 < gsvs_ring_size);
3492
3493 if (!update_esgs && !update_gsvs)
3494 return true;
3495
3496 if (update_esgs) {
3497 pipe_resource_reference(&sctx->esgs_ring, NULL);
3498 sctx->esgs_ring =
3499 pipe_aligned_buffer_create(sctx->b.screen,
3500 SI_RESOURCE_FLAG_UNMAPPABLE,
3501 PIPE_USAGE_DEFAULT,
3502 esgs_ring_size, alignment);
3503 if (!sctx->esgs_ring)
3504 return false;
3505 }
3506
3507 if (update_gsvs) {
3508 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3509 sctx->gsvs_ring =
3510 pipe_aligned_buffer_create(sctx->b.screen,
3511 SI_RESOURCE_FLAG_UNMAPPABLE,
3512 PIPE_USAGE_DEFAULT,
3513 gsvs_ring_size, alignment);
3514 if (!sctx->gsvs_ring)
3515 return false;
3516 }
3517
3518 /* Create the "init_config_gs_rings" state. */
3519 pm4 = CALLOC_STRUCT(si_pm4_state);
3520 if (!pm4)
3521 return false;
3522
3523 if (sctx->chip_class >= GFX7) {
3524 if (sctx->esgs_ring) {
3525 assert(sctx->chip_class <= GFX8);
3526 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3527 sctx->esgs_ring->width0 / 256);
3528 }
3529 if (sctx->gsvs_ring)
3530 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3531 sctx->gsvs_ring->width0 / 256);
3532 } else {
3533 if (sctx->esgs_ring)
3534 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3535 sctx->esgs_ring->width0 / 256);
3536 if (sctx->gsvs_ring)
3537 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3538 sctx->gsvs_ring->width0 / 256);
3539 }
3540
3541 /* Set the state. */
3542 if (sctx->init_config_gs_rings)
3543 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3544 sctx->init_config_gs_rings = pm4;
3545
3546 if (!sctx->init_config_has_vgt_flush) {
3547 si_init_config_add_vgt_flush(sctx);
3548 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3549 }
3550
3551 /* Flush the context to re-emit both init_config states. */
3552 sctx->initial_gfx_cs_size = 0; /* force flush */
3553 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3554
3555 /* Set ring bindings. */
3556 if (sctx->esgs_ring) {
3557 assert(sctx->chip_class <= GFX8);
3558 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3559 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3560 true, true, 4, 64, 0);
3561 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3562 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3563 false, false, 0, 0, 0);
3564 }
3565 if (sctx->gsvs_ring) {
3566 si_set_ring_buffer(sctx, SI_RING_GSVS,
3567 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3568 false, false, 0, 0, 0);
3569 }
3570
3571 return true;
3572 }
3573
3574 static void si_shader_lock(struct si_shader *shader)
3575 {
3576 mtx_lock(&shader->selector->mutex);
3577 if (shader->previous_stage_sel) {
3578 assert(shader->previous_stage_sel != shader->selector);
3579 mtx_lock(&shader->previous_stage_sel->mutex);
3580 }
3581 }
3582
3583 static void si_shader_unlock(struct si_shader *shader)
3584 {
3585 if (shader->previous_stage_sel)
3586 mtx_unlock(&shader->previous_stage_sel->mutex);
3587 mtx_unlock(&shader->selector->mutex);
3588 }
3589
3590 /**
3591 * @returns 1 if \p sel has been updated to use a new scratch buffer
3592 * 0 if not
3593 * < 0 if there was a failure
3594 */
3595 static int si_update_scratch_buffer(struct si_context *sctx,
3596 struct si_shader *shader)
3597 {
3598 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3599
3600 if (!shader)
3601 return 0;
3602
3603 /* This shader doesn't need a scratch buffer */
3604 if (shader->config.scratch_bytes_per_wave == 0)
3605 return 0;
3606
3607 /* Prevent race conditions when updating:
3608 * - si_shader::scratch_bo
3609 * - si_shader::binary::code
3610 * - si_shader::previous_stage::binary::code.
3611 */
3612 si_shader_lock(shader);
3613
3614 /* This shader is already configured to use the current
3615 * scratch buffer. */
3616 if (shader->scratch_bo == sctx->scratch_buffer) {
3617 si_shader_unlock(shader);
3618 return 0;
3619 }
3620
3621 assert(sctx->scratch_buffer);
3622
3623 /* Replace the shader bo with a new bo that has the relocs applied. */
3624 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3625 si_shader_unlock(shader);
3626 return -1;
3627 }
3628
3629 /* Update the shader state to use the new shader bo. */
3630 si_shader_init_pm4_state(sctx->screen, shader);
3631
3632 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3633
3634 si_shader_unlock(shader);
3635 return 1;
3636 }
3637
3638 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3639 {
3640 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3641 }
3642
3643 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3644 {
3645 return shader ? shader->config.scratch_bytes_per_wave : 0;
3646 }
3647
3648 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3649 {
3650 if (!sctx->tes_shader.cso)
3651 return NULL; /* tessellation disabled */
3652
3653 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3654 sctx->fixed_func_tcs_shader.current;
3655 }
3656
3657 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3658 {
3659 unsigned bytes = 0;
3660
3661 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3662 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3663 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3664 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3665
3666 if (sctx->tes_shader.cso) {
3667 struct si_shader *tcs = si_get_tcs_current(sctx);
3668
3669 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3670 }
3671 return bytes;
3672 }
3673
3674 static bool si_update_scratch_relocs(struct si_context *sctx)
3675 {
3676 struct si_shader *tcs = si_get_tcs_current(sctx);
3677 int r;
3678
3679 /* Update the shaders, so that they are using the latest scratch.
3680 * The scratch buffer may have been changed since these shaders were
3681 * last used, so we still need to try to update them, even if they
3682 * require scratch buffers smaller than the current size.
3683 */
3684 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3685 if (r < 0)
3686 return false;
3687 if (r == 1)
3688 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3689
3690 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3691 if (r < 0)
3692 return false;
3693 if (r == 1)
3694 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3695
3696 r = si_update_scratch_buffer(sctx, tcs);
3697 if (r < 0)
3698 return false;
3699 if (r == 1)
3700 si_pm4_bind_state(sctx, hs, tcs->pm4);
3701
3702 /* VS can be bound as LS, ES, or VS. */
3703 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3704 if (r < 0)
3705 return false;
3706 if (r == 1) {
3707 if (sctx->vs_shader.current->key.as_ls)
3708 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3709 else if (sctx->vs_shader.current->key.as_es)
3710 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3711 else if (sctx->vs_shader.current->key.as_ngg)
3712 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3713 else
3714 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3715 }
3716
3717 /* TES can be bound as ES or VS. */
3718 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3719 if (r < 0)
3720 return false;
3721 if (r == 1) {
3722 if (sctx->tes_shader.current->key.as_es)
3723 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3724 else if (sctx->tes_shader.current->key.as_ngg)
3725 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3726 else
3727 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3728 }
3729
3730 return true;
3731 }
3732
3733 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3734 {
3735 unsigned current_scratch_buffer_size =
3736 si_get_current_scratch_buffer_size(sctx);
3737 unsigned scratch_bytes_per_wave =
3738 si_get_max_scratch_bytes_per_wave(sctx);
3739 unsigned scratch_needed_size = scratch_bytes_per_wave *
3740 sctx->scratch_waves;
3741 unsigned spi_tmpring_size;
3742
3743 if (scratch_needed_size > 0) {
3744 if (scratch_needed_size > current_scratch_buffer_size) {
3745 /* Create a bigger scratch buffer */
3746 si_resource_reference(&sctx->scratch_buffer, NULL);
3747
3748 sctx->scratch_buffer =
3749 si_aligned_buffer_create(&sctx->screen->b,
3750 SI_RESOURCE_FLAG_UNMAPPABLE,
3751 PIPE_USAGE_DEFAULT,
3752 scratch_needed_size, 256);
3753 if (!sctx->scratch_buffer)
3754 return false;
3755
3756 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3757 si_context_add_resource_size(sctx,
3758 &sctx->scratch_buffer->b.b);
3759 }
3760
3761 if (!si_update_scratch_relocs(sctx))
3762 return false;
3763 }
3764
3765 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3766 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3767 "scratch size should already be aligned correctly.");
3768
3769 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3770 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3771 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3772 sctx->spi_tmpring_size = spi_tmpring_size;
3773 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3774 }
3775 return true;
3776 }
3777
3778 static void si_init_tess_factor_ring(struct si_context *sctx)
3779 {
3780 assert(!sctx->tess_rings);
3781 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3782
3783 /* The address must be aligned to 2^19, because the shader only
3784 * receives the high 13 bits.
3785 */
3786 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3787 SI_RESOURCE_FLAG_32BIT,
3788 PIPE_USAGE_DEFAULT,
3789 sctx->screen->tess_offchip_ring_size +
3790 sctx->screen->tess_factor_ring_size,
3791 1 << 19);
3792 if (!sctx->tess_rings)
3793 return;
3794
3795 si_init_config_add_vgt_flush(sctx);
3796
3797 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3798 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3799
3800 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3801 sctx->screen->tess_offchip_ring_size;
3802
3803 /* Append these registers to the init config state. */
3804 if (sctx->chip_class >= GFX7) {
3805 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3806 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3807 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3808 factor_va >> 8);
3809 if (sctx->chip_class >= GFX10)
3810 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3811 S_030984_BASE_HI(factor_va >> 40));
3812 else if (sctx->chip_class == GFX9)
3813 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3814 S_030944_BASE_HI(factor_va >> 40));
3815 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3816 sctx->screen->vgt_hs_offchip_param);
3817 } else {
3818 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3819 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3820 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3821 factor_va >> 8);
3822 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3823 sctx->screen->vgt_hs_offchip_param);
3824 }
3825
3826 /* Flush the context to re-emit the init_config state.
3827 * This is done only once in a lifetime of a context.
3828 */
3829 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3830 sctx->initial_gfx_cs_size = 0; /* force flush */
3831 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3832 }
3833
3834 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3835 union si_vgt_stages_key key)
3836 {
3837 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3838 uint32_t stages = 0;
3839
3840 if (key.u.tess) {
3841 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3842 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3843
3844 if (key.u.gs)
3845 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3846 S_028B54_GS_EN(1);
3847 else if (key.u.ngg)
3848 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3849 else
3850 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3851 } else if (key.u.gs) {
3852 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3853 S_028B54_GS_EN(1);
3854 } else if (key.u.ngg) {
3855 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3856 }
3857
3858 if (key.u.ngg) {
3859 stages |= S_028B54_PRIMGEN_EN(1);
3860 if (key.u.streamout)
3861 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3862 } else if (key.u.gs)
3863 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3864
3865 if (screen->info.chip_class >= GFX9)
3866 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3867
3868 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3869 stages |= S_028B54_HS_W32_EN(1) |
3870 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3871 S_028B54_VS_W32_EN(1);
3872 }
3873
3874 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3875 return pm4;
3876 }
3877
3878 static void si_update_vgt_shader_config(struct si_context *sctx,
3879 union si_vgt_stages_key key)
3880 {
3881 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3882
3883 if (unlikely(!*pm4))
3884 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3885 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3886 }
3887
3888 bool si_update_shaders(struct si_context *sctx)
3889 {
3890 struct pipe_context *ctx = (struct pipe_context*)sctx;
3891 struct si_compiler_ctx_state compiler_state;
3892 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3893 struct si_shader *old_vs = si_get_vs_state(sctx);
3894 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3895 struct si_shader *old_ps = sctx->ps_shader.current;
3896 union si_vgt_stages_key key;
3897 unsigned old_spi_shader_col_format =
3898 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3899 int r;
3900
3901 compiler_state.compiler = &sctx->compiler;
3902 compiler_state.debug = sctx->debug;
3903 compiler_state.is_debug_context = sctx->is_debug;
3904
3905 key.index = 0;
3906
3907 if (sctx->tes_shader.cso)
3908 key.u.tess = 1;
3909 if (sctx->gs_shader.cso)
3910 key.u.gs = 1;
3911
3912 if (sctx->ngg) {
3913 key.u.ngg = 1;
3914 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3915 }
3916
3917 /* Update TCS and TES. */
3918 if (sctx->tes_shader.cso) {
3919 if (!sctx->tess_rings) {
3920 si_init_tess_factor_ring(sctx);
3921 if (!sctx->tess_rings)
3922 return false;
3923 }
3924
3925 if (sctx->tcs_shader.cso) {
3926 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3927 &compiler_state);
3928 if (r)
3929 return false;
3930 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3931 } else {
3932 if (!sctx->fixed_func_tcs_shader.cso) {
3933 sctx->fixed_func_tcs_shader.cso =
3934 si_create_fixed_func_tcs(sctx);
3935 if (!sctx->fixed_func_tcs_shader.cso)
3936 return false;
3937 }
3938
3939 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3940 key, &compiler_state);
3941 if (r)
3942 return false;
3943 si_pm4_bind_state(sctx, hs,
3944 sctx->fixed_func_tcs_shader.current->pm4);
3945 }
3946
3947 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3948 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3949 if (r)
3950 return false;
3951
3952 if (sctx->gs_shader.cso) {
3953 /* TES as ES */
3954 assert(sctx->chip_class <= GFX8);
3955 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3956 } else if (key.u.ngg) {
3957 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3958 } else {
3959 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3960 }
3961 }
3962 } else {
3963 if (sctx->chip_class <= GFX8)
3964 si_pm4_bind_state(sctx, ls, NULL);
3965 si_pm4_bind_state(sctx, hs, NULL);
3966 }
3967
3968 /* Update GS. */
3969 if (sctx->gs_shader.cso) {
3970 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3971 if (r)
3972 return false;
3973 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3974 if (!key.u.ngg) {
3975 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3976
3977 if (!si_update_gs_ring_buffers(sctx))
3978 return false;
3979 } else {
3980 si_pm4_bind_state(sctx, vs, NULL);
3981 }
3982 } else {
3983 if (!key.u.ngg) {
3984 si_pm4_bind_state(sctx, gs, NULL);
3985 if (sctx->chip_class <= GFX8)
3986 si_pm4_bind_state(sctx, es, NULL);
3987 }
3988 }
3989
3990 /* Update VS. */
3991 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3992 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3993 if (r)
3994 return false;
3995
3996 if (!key.u.tess && !key.u.gs) {
3997 if (key.u.ngg) {
3998 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3999 si_pm4_bind_state(sctx, vs, NULL);
4000 } else {
4001 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4002 }
4003 } else if (sctx->tes_shader.cso) {
4004 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4005 } else {
4006 assert(sctx->gs_shader.cso);
4007 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4008 }
4009 }
4010
4011 si_update_vgt_shader_config(sctx, key);
4012
4013 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4014 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4015
4016 if (sctx->ps_shader.cso) {
4017 unsigned db_shader_control;
4018
4019 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4020 if (r)
4021 return false;
4022 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4023
4024 db_shader_control =
4025 sctx->ps_shader.cso->db_shader_control |
4026 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4027
4028 if (si_pm4_state_changed(sctx, ps) ||
4029 si_pm4_state_changed(sctx, vs) ||
4030 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4031 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4032 sctx->flatshade != rs->flatshade) {
4033 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4034 sctx->flatshade = rs->flatshade;
4035 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4036 }
4037
4038 if (sctx->screen->info.rbplus_allowed &&
4039 si_pm4_state_changed(sctx, ps) &&
4040 (!old_ps ||
4041 old_spi_shader_col_format !=
4042 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4043 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4044
4045 if (sctx->ps_db_shader_control != db_shader_control) {
4046 sctx->ps_db_shader_control = db_shader_control;
4047 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4048 if (sctx->screen->dpbb_allowed)
4049 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4050 }
4051
4052 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4053 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4054 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4055
4056 if (sctx->chip_class == GFX6)
4057 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4058
4059 if (sctx->framebuffer.nr_samples <= 1)
4060 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4061 }
4062 }
4063
4064 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4065 si_pm4_state_enabled_and_changed(sctx, hs) ||
4066 si_pm4_state_enabled_and_changed(sctx, es) ||
4067 si_pm4_state_enabled_and_changed(sctx, gs) ||
4068 si_pm4_state_enabled_and_changed(sctx, vs) ||
4069 si_pm4_state_enabled_and_changed(sctx, ps)) {
4070 if (!si_update_spi_tmpring_size(sctx))
4071 return false;
4072 }
4073
4074 if (sctx->chip_class >= GFX7) {
4075 if (si_pm4_state_enabled_and_changed(sctx, ls))
4076 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4077 else if (!sctx->queued.named.ls)
4078 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4079
4080 if (si_pm4_state_enabled_and_changed(sctx, hs))
4081 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4082 else if (!sctx->queued.named.hs)
4083 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4084
4085 if (si_pm4_state_enabled_and_changed(sctx, es))
4086 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4087 else if (!sctx->queued.named.es)
4088 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4089
4090 if (si_pm4_state_enabled_and_changed(sctx, gs))
4091 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4092 else if (!sctx->queued.named.gs)
4093 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4094
4095 if (si_pm4_state_enabled_and_changed(sctx, vs))
4096 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4097 else if (!sctx->queued.named.vs)
4098 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4099
4100 if (si_pm4_state_enabled_and_changed(sctx, ps))
4101 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4102 else if (!sctx->queued.named.ps)
4103 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4104 }
4105
4106 sctx->do_update_shaders = false;
4107 return true;
4108 }
4109
4110 static void si_emit_scratch_state(struct si_context *sctx)
4111 {
4112 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4113
4114 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4115 sctx->spi_tmpring_size);
4116
4117 if (sctx->scratch_buffer) {
4118 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4119 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4120 RADEON_PRIO_SCRATCH_BUFFER);
4121 }
4122 }
4123
4124 void si_init_shader_functions(struct si_context *sctx)
4125 {
4126 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4127 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4128
4129 sctx->b.create_vs_state = si_create_shader_selector;
4130 sctx->b.create_tcs_state = si_create_shader_selector;
4131 sctx->b.create_tes_state = si_create_shader_selector;
4132 sctx->b.create_gs_state = si_create_shader_selector;
4133 sctx->b.create_fs_state = si_create_shader_selector;
4134
4135 sctx->b.bind_vs_state = si_bind_vs_shader;
4136 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4137 sctx->b.bind_tes_state = si_bind_tes_shader;
4138 sctx->b.bind_gs_state = si_bind_gs_shader;
4139 sctx->b.bind_fs_state = si_bind_ps_shader;
4140
4141 sctx->b.delete_vs_state = si_delete_shader_selector;
4142 sctx->b.delete_tcs_state = si_delete_shader_selector;
4143 sctx->b.delete_tes_state = si_delete_shader_selector;
4144 sctx->b.delete_gs_state = si_delete_shader_selector;
4145 sctx->b.delete_fs_state = si_delete_shader_selector;
4146 }