radeonsi: remove redundant si_shader_info::uses_derivatives
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "ac_exp_param.h"
26 #include "ac_shader_util.h"
27 #include "compiler/nir/nir_serialize.h"
28 #include "nir/tgsi_to_nir.h"
29 #include "si_build_pm4.h"
30 #include "sid.h"
31 #include "util/crc32.h"
32 #include "util/disk_cache.h"
33 #include "util/hash_table.h"
34 #include "util/mesa-sha1.h"
35 #include "util/u_async_debug.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38 #include "tgsi/tgsi_from_mesa.h"
39
40 /* SHADER_CACHE */
41
42 /**
43 * Return the IR key for the shader cache.
44 */
45 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
46 unsigned char ir_sha1_cache_key[20])
47 {
48 struct blob blob = {};
49 unsigned ir_size;
50 void *ir_binary;
51
52 if (sel->nir_binary) {
53 ir_binary = sel->nir_binary;
54 ir_size = sel->nir_size;
55 } else {
56 assert(sel->nir);
57
58 blob_init(&blob);
59 nir_serialize(&blob, sel->nir, true);
60 ir_binary = blob.data;
61 ir_size = blob.size;
62 }
63
64 /* These settings affect the compilation, but they are not derived
65 * from the input shader IR.
66 */
67 unsigned shader_variant_flags = 0;
68
69 if (ngg)
70 shader_variant_flags |= 1 << 0;
71 if (sel->nir)
72 shader_variant_flags |= 1 << 1;
73 if (si_get_wave_size(sel->screen, sel->info.stage, ngg, es, false, false) == 32)
74 shader_variant_flags |= 1 << 2;
75 if (sel->info.stage == MESA_SHADER_FRAGMENT &&
76 /* Derivatives imply helper invocations so check for needs_helper_invocations. */
77 sel->info.base.fs.needs_helper_invocations &&
78 sel->info.base.fs.uses_discard &&
79 sel->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
80 shader_variant_flags |= 1 << 3;
81
82 /* This varies depending on whether compute-based culling is enabled. */
83 shader_variant_flags |= sel->screen->num_vbos_in_user_sgprs << 4;
84
85 struct mesa_sha1 ctx;
86 _mesa_sha1_init(&ctx);
87 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
88 _mesa_sha1_update(&ctx, ir_binary, ir_size);
89 if (sel->info.stage == MESA_SHADER_VERTEX || sel->info.stage == MESA_SHADER_TESS_EVAL ||
90 sel->info.stage == MESA_SHADER_GEOMETRY)
91 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
92 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
93
94 if (ir_binary == blob.data)
95 blob_finish(&blob);
96 }
97
98 /** Copy "data" to "ptr" and return the next dword following copied data. */
99 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
100 {
101 /* data may be NULL if size == 0 */
102 if (size)
103 memcpy(ptr, data, size);
104 ptr += DIV_ROUND_UP(size, 4);
105 return ptr;
106 }
107
108 /** Read data from "ptr". Return the next dword following the data. */
109 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
110 {
111 memcpy(data, ptr, size);
112 ptr += DIV_ROUND_UP(size, 4);
113 return ptr;
114 }
115
116 /**
117 * Write the size as uint followed by the data. Return the next dword
118 * following the copied data.
119 */
120 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
121 {
122 *ptr++ = size;
123 return write_data(ptr, data, size);
124 }
125
126 /**
127 * Read the size as uint followed by the data. Return both via parameters.
128 * Return the next dword following the data.
129 */
130 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
131 {
132 *size = *ptr++;
133 assert(*data == NULL);
134 if (!*size)
135 return ptr;
136 *data = malloc(*size);
137 return read_data(ptr, *data, *size);
138 }
139
140 /**
141 * Return the shader binary in a buffer. The first 4 bytes contain its size
142 * as integer.
143 */
144 static void *si_get_shader_binary(struct si_shader *shader)
145 {
146 /* There is always a size of data followed by the data itself. */
147 unsigned llvm_ir_size =
148 shader->binary.llvm_ir_string ? strlen(shader->binary.llvm_ir_string) + 1 : 0;
149
150 /* Refuse to allocate overly large buffers and guard against integer
151 * overflow. */
152 if (shader->binary.elf_size > UINT_MAX / 4 || llvm_ir_size > UINT_MAX / 4)
153 return NULL;
154
155 unsigned size = 4 + /* total size */
156 4 + /* CRC32 of the data below */
157 align(sizeof(shader->config), 4) + align(sizeof(shader->info), 4) + 4 +
158 align(shader->binary.elf_size, 4) + 4 + align(llvm_ir_size, 4);
159 void *buffer = CALLOC(1, size);
160 uint32_t *ptr = (uint32_t *)buffer;
161
162 if (!buffer)
163 return NULL;
164
165 *ptr++ = size;
166 ptr++; /* CRC32 is calculated at the end. */
167
168 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
169 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
170 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
171 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
172 assert((char *)ptr - (char *)buffer == size);
173
174 /* Compute CRC32. */
175 ptr = (uint32_t *)buffer;
176 ptr++;
177 *ptr = util_hash_crc32(ptr + 1, size - 8);
178
179 return buffer;
180 }
181
182 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
183 {
184 uint32_t *ptr = (uint32_t *)binary;
185 uint32_t size = *ptr++;
186 uint32_t crc32 = *ptr++;
187 unsigned chunk_size;
188 unsigned elf_size;
189
190 if (util_hash_crc32(ptr, size - 8) != crc32) {
191 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
192 return false;
193 }
194
195 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
196 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
197 ptr = read_chunk(ptr, (void **)&shader->binary.elf_buffer, &elf_size);
198 shader->binary.elf_size = elf_size;
199 ptr = read_chunk(ptr, (void **)&shader->binary.llvm_ir_string, &chunk_size);
200
201 return true;
202 }
203
204 /**
205 * Insert a shader into the cache. It's assumed the shader is not in the cache.
206 * Use si_shader_cache_load_shader before calling this.
207 */
208 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
209 struct si_shader *shader, bool insert_into_disk_cache)
210 {
211 void *hw_binary;
212 struct hash_entry *entry;
213 uint8_t key[CACHE_KEY_SIZE];
214
215 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
216 if (entry)
217 return; /* already added */
218
219 hw_binary = si_get_shader_binary(shader);
220 if (!hw_binary)
221 return;
222
223 if (_mesa_hash_table_insert(sscreen->shader_cache, mem_dup(ir_sha1_cache_key, 20), hw_binary) ==
224 NULL) {
225 FREE(hw_binary);
226 return;
227 }
228
229 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
230 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, key);
231 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary, *((uint32_t *)hw_binary), NULL);
232 }
233 }
234
235 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
236 struct si_shader *shader)
237 {
238 struct hash_entry *entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
239
240 if (entry) {
241 if (si_load_shader_binary(shader, entry->data)) {
242 p_atomic_inc(&sscreen->num_memory_shader_cache_hits);
243 return true;
244 }
245 }
246 p_atomic_inc(&sscreen->num_memory_shader_cache_misses);
247
248 if (!sscreen->disk_shader_cache)
249 return false;
250
251 unsigned char sha1[CACHE_KEY_SIZE];
252 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, sha1);
253
254 size_t binary_size;
255 uint8_t *buffer = disk_cache_get(sscreen->disk_shader_cache, sha1, &binary_size);
256 if (buffer) {
257 if (binary_size >= sizeof(uint32_t) && *((uint32_t *)buffer) == binary_size) {
258 if (si_load_shader_binary(shader, buffer)) {
259 free(buffer);
260 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, false);
261 p_atomic_inc(&sscreen->num_disk_shader_cache_hits);
262 return true;
263 }
264 } else {
265 /* Something has gone wrong discard the item from the cache and
266 * rebuild/link from source.
267 */
268 assert(!"Invalid radeonsi shader disk cache item!");
269 disk_cache_remove(sscreen->disk_shader_cache, sha1);
270 }
271 }
272
273 free(buffer);
274 p_atomic_inc(&sscreen->num_disk_shader_cache_misses);
275 return false;
276 }
277
278 static uint32_t si_shader_cache_key_hash(const void *key)
279 {
280 /* Take the first dword of SHA1. */
281 return *(uint32_t *)key;
282 }
283
284 static bool si_shader_cache_key_equals(const void *a, const void *b)
285 {
286 /* Compare SHA1s. */
287 return memcmp(a, b, 20) == 0;
288 }
289
290 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
291 {
292 FREE((void *)entry->key);
293 FREE(entry->data);
294 }
295
296 bool si_init_shader_cache(struct si_screen *sscreen)
297 {
298 (void)simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
299 sscreen->shader_cache =
300 _mesa_hash_table_create(NULL, si_shader_cache_key_hash, si_shader_cache_key_equals);
301
302 return sscreen->shader_cache != NULL;
303 }
304
305 void si_destroy_shader_cache(struct si_screen *sscreen)
306 {
307 if (sscreen->shader_cache)
308 _mesa_hash_table_destroy(sscreen->shader_cache, si_destroy_shader_cache_entry);
309 simple_mtx_destroy(&sscreen->shader_cache_mutex);
310 }
311
312 /* SHADER STATES */
313
314 static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shader_selector *tes,
315 struct si_pm4_state *pm4)
316 {
317 const struct si_shader_info *info = &tes->info;
318 unsigned tes_prim_mode = info->base.tess.primitive_mode;
319 unsigned tes_spacing = info->base.tess.spacing;
320 bool tes_vertex_order_cw = !info->base.tess.ccw;
321 bool tes_point_mode = info->base.tess.point_mode;
322 unsigned type, partitioning, topology, distribution_mode;
323
324 switch (tes_prim_mode) {
325 case GL_LINES:
326 type = V_028B6C_TESS_ISOLINE;
327 break;
328 case GL_TRIANGLES:
329 type = V_028B6C_TESS_TRIANGLE;
330 break;
331 case GL_QUADS:
332 type = V_028B6C_TESS_QUAD;
333 break;
334 default:
335 assert(0);
336 return;
337 }
338
339 switch (tes_spacing) {
340 case TESS_SPACING_FRACTIONAL_ODD:
341 partitioning = V_028B6C_PART_FRAC_ODD;
342 break;
343 case TESS_SPACING_FRACTIONAL_EVEN:
344 partitioning = V_028B6C_PART_FRAC_EVEN;
345 break;
346 case TESS_SPACING_EQUAL:
347 partitioning = V_028B6C_PART_INTEGER;
348 break;
349 default:
350 assert(0);
351 return;
352 }
353
354 if (tes_point_mode)
355 topology = V_028B6C_OUTPUT_POINT;
356 else if (tes_prim_mode == GL_LINES)
357 topology = V_028B6C_OUTPUT_LINE;
358 else if (tes_vertex_order_cw)
359 /* for some reason, this must be the other way around */
360 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
361 else
362 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
363
364 if (sscreen->info.has_distributed_tess) {
365 if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10)
366 distribution_mode = V_028B6C_TRAPEZOIDS;
367 else
368 distribution_mode = V_028B6C_DONUTS;
369 } else
370 distribution_mode = V_028B6C_NO_DIST;
371
372 assert(pm4->shader);
373 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
374 S_028B6C_TOPOLOGY(topology) |
375 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
376 }
377
378 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
379 * whether the "fractional odd" tessellation spacing is used.
380 *
381 * Possible VGT configurations and which state should set the register:
382 *
383 * Reg set in | VGT shader configuration | Value
384 * ------------------------------------------------------
385 * VS as VS | VS | 30
386 * VS as ES | ES -> GS -> VS | 30
387 * TES as VS | LS -> HS -> VS | 14 or 30
388 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
389 *
390 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
391 */
392 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_shader_selector *sel,
393 struct si_shader *shader, struct si_pm4_state *pm4)
394 {
395 if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.chip_class >= GFX10)
396 return;
397
398 /* VS as VS, or VS as ES: */
399 if ((sel->info.stage == MESA_SHADER_VERTEX &&
400 (!shader || (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
401 /* TES as VS, or TES as ES: */
402 sel->info.stage == MESA_SHADER_TESS_EVAL) {
403 unsigned vtx_reuse_depth = 30;
404
405 if (sel->info.stage == MESA_SHADER_TESS_EVAL &&
406 sel->info.base.tess.spacing == TESS_SPACING_FRACTIONAL_ODD)
407 vtx_reuse_depth = 14;
408
409 assert(pm4->shader);
410 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
411 }
412 }
413
414 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
415 {
416 if (shader->pm4)
417 si_pm4_clear_state(shader->pm4);
418 else
419 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
420
421 if (shader->pm4) {
422 shader->pm4->shader = shader;
423 return shader->pm4;
424 } else {
425 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
426 return NULL;
427 }
428 }
429
430 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
431 unsigned num_always_on_user_sgprs)
432 {
433 struct si_shader_selector *vs =
434 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
435 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
436
437 /* 1 SGPR is reserved for the vertex buffer pointer. */
438 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
439
440 if (num_vbos_in_user_sgprs)
441 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
442
443 /* Add the pointer to VBO descriptors. */
444 return num_always_on_user_sgprs + 1;
445 }
446
447 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
448 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_shader *shader,
449 bool legacy_vs_prim_id)
450 {
451 assert(shader->selector->info.stage == MESA_SHADER_VERTEX ||
452 (shader->previous_stage_sel && shader->previous_stage_sel->info.stage == MESA_SHADER_VERTEX));
453
454 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
455 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
456 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
457 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or
458 * InstanceID)
459 */
460 bool is_ls = shader->selector->info.stage == MESA_SHADER_TESS_CTRL || shader->key.as_ls;
461
462 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
463 return 3;
464 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
465 return 2;
466 else if (is_ls || shader->info.uses_instanceid)
467 return 1;
468 else
469 return 0;
470 }
471
472 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
473 {
474 struct si_pm4_state *pm4;
475 uint64_t va;
476
477 assert(sscreen->info.chip_class <= GFX8);
478
479 pm4 = si_get_shader_pm4_state(shader);
480 if (!pm4)
481 return;
482
483 va = shader->bo->gpu_address;
484 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
485 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
486
487 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
488 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
489 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
490 S_00B528_DX10_CLAMP(1) | S_00B528_FLOAT_MODE(shader->config.float_mode);
491 shader->config.rsrc2 =
492 S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
493 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
494 }
495
496 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
497 {
498 struct si_pm4_state *pm4;
499 uint64_t va;
500
501 pm4 = si_get_shader_pm4_state(shader);
502 if (!pm4)
503 return;
504
505 va = shader->bo->gpu_address;
506
507 if (sscreen->info.chip_class >= GFX9) {
508 if (sscreen->info.chip_class >= GFX10) {
509 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
510 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
511 } else {
512 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
513 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
514 }
515
516 unsigned num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
517
518 shader->config.rsrc2 = S_00B42C_USER_SGPR(num_user_sgprs) |
519 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
520
521 if (sscreen->info.chip_class >= GFX10)
522 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
523 else
524 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
525 } else {
526 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
527 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
528
529 shader->config.rsrc2 = S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) | S_00B42C_OC_LDS_EN(1) |
530 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
531 }
532
533 si_pm4_set_reg(
534 pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
535 S_00B428_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
536 (sscreen->info.chip_class <= GFX9 ? S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8)
537 : 0) |
538 S_00B428_DX10_CLAMP(1) | S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
539 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
540 S_00B428_FLOAT_MODE(shader->config.float_mode) |
541 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9
542 ? si_get_vs_vgpr_comp_cnt(sscreen, shader, false)
543 : 0));
544
545 if (sscreen->info.chip_class <= GFX8) {
546 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2);
547 }
548 }
549
550 static void si_emit_shader_es(struct si_context *sctx)
551 {
552 struct si_shader *shader = sctx->queued.named.es->shader;
553 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
554
555 if (!shader)
556 return;
557
558 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
559 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
560 shader->selector->esgs_itemsize / 4);
561
562 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
563 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
564 shader->vgt_tf_param);
565
566 if (shader->vgt_vertex_reuse_block_cntl)
567 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
568 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
569 shader->vgt_vertex_reuse_block_cntl);
570
571 if (initial_cdw != sctx->gfx_cs->current.cdw)
572 sctx->context_roll = true;
573 }
574
575 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
576 {
577 struct si_pm4_state *pm4;
578 unsigned num_user_sgprs;
579 unsigned vgpr_comp_cnt;
580 uint64_t va;
581 unsigned oc_lds_en;
582
583 assert(sscreen->info.chip_class <= GFX8);
584
585 pm4 = si_get_shader_pm4_state(shader);
586 if (!pm4)
587 return;
588
589 pm4->atom.emit = si_emit_shader_es;
590 va = shader->bo->gpu_address;
591
592 if (shader->selector->info.stage == MESA_SHADER_VERTEX) {
593 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
594 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
595 } else if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) {
596 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
597 num_user_sgprs = SI_TES_NUM_USER_SGPR;
598 } else
599 unreachable("invalid shader selector type");
600
601 oc_lds_en = shader->selector->info.stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
602
603 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
604 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
605 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
606 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
607 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
608 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B328_DX10_CLAMP(1) |
609 S_00B328_FLOAT_MODE(shader->config.float_mode));
610 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
611 S_00B32C_USER_SGPR(num_user_sgprs) | S_00B32C_OC_LDS_EN(oc_lds_en) |
612 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
613
614 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
615 si_set_tesseval_regs(sscreen, shader->selector, pm4);
616
617 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
618 }
619
620 void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *gs,
621 struct gfx9_gs_info *out)
622 {
623 unsigned gs_num_invocations = MAX2(gs->info.base.gs.invocations, 1);
624 unsigned input_prim = gs->info.base.gs.input_primitive;
625 bool uses_adjacency =
626 input_prim >= PIPE_PRIM_LINES_ADJACENCY && input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
627
628 /* All these are in dwords: */
629 /* We can't allow using the whole LDS, because GS waves compete with
630 * other shader stages for LDS space. */
631 const unsigned max_lds_size = 8 * 1024;
632 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
633 unsigned esgs_lds_size;
634
635 /* All these are per subgroup: */
636 const unsigned max_out_prims = 32 * 1024;
637 const unsigned max_es_verts = 255;
638 const unsigned ideal_gs_prims = 64;
639 unsigned max_gs_prims, gs_prims;
640 unsigned min_es_verts, es_verts, worst_case_es_verts;
641
642 if (uses_adjacency || gs_num_invocations > 1)
643 max_gs_prims = 127 / gs_num_invocations;
644 else
645 max_gs_prims = 255;
646
647 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
648 * Make sure we don't go over the maximum value.
649 */
650 if (gs->info.base.gs.vertices_out > 0) {
651 max_gs_prims =
652 MIN2(max_gs_prims, max_out_prims / (gs->info.base.gs.vertices_out * gs_num_invocations));
653 }
654 assert(max_gs_prims > 0);
655
656 /* If the primitive has adjacency, halve the number of vertices
657 * that will be reused in multiple primitives.
658 */
659 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
660
661 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
662 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
663
664 /* Compute ESGS LDS size based on the worst case number of ES vertices
665 * needed to create the target number of GS prims per subgroup.
666 */
667 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
668
669 /* If total LDS usage is too big, refactor partitions based on ratio
670 * of ESGS item sizes.
671 */
672 if (esgs_lds_size > max_lds_size) {
673 /* Our target GS Prims Per Subgroup was too large. Calculate
674 * the maximum number of GS Prims Per Subgroup that will fit
675 * into LDS, capped by the maximum that the hardware can support.
676 */
677 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)), max_gs_prims);
678 assert(gs_prims > 0);
679 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
680
681 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
682 assert(esgs_lds_size <= max_lds_size);
683 }
684
685 /* Now calculate remaining ESGS information. */
686 if (esgs_lds_size)
687 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
688 else
689 es_verts = max_es_verts;
690
691 /* Vertices for adjacency primitives are not always reused, so restore
692 * it for ES_VERTS_PER_SUBGRP.
693 */
694 min_es_verts = gs->gs_input_verts_per_prim;
695
696 /* For normal primitives, the VGT only checks if they are past the ES
697 * verts per subgroup after allocating a full GS primitive and if they
698 * are, kick off a new subgroup. But if those additional ES verts are
699 * unique (e.g. not reused) we need to make sure there is enough LDS
700 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
701 */
702 es_verts -= min_es_verts - 1;
703
704 out->es_verts_per_subgroup = es_verts;
705 out->gs_prims_per_subgroup = gs_prims;
706 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
707 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup * gs->info.base.gs.vertices_out;
708 out->esgs_ring_size = esgs_lds_size;
709
710 assert(out->max_prims_per_subgroup <= max_out_prims);
711 }
712
713 static void si_emit_shader_gs(struct si_context *sctx)
714 {
715 struct si_shader *shader = sctx->queued.named.gs->shader;
716 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
717
718 if (!shader)
719 return;
720
721 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
722 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
723 radeon_opt_set_context_reg3(
724 sctx, R_028A60_VGT_GSVS_RING_OFFSET_1, SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
725 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1, shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
726 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
727
728 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
729 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
730 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
731 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
732
733 /* R_028B38_VGT_GS_MAX_VERT_OUT */
734 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
735 shader->ctx_reg.gs.vgt_gs_max_vert_out);
736
737 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
738 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
739 radeon_opt_set_context_reg4(
740 sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE, SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
741 shader->ctx_reg.gs.vgt_gs_vert_itemsize, shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
742 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2, shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
743
744 /* R_028B90_VGT_GS_INSTANCE_CNT */
745 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
746 shader->ctx_reg.gs.vgt_gs_instance_cnt);
747
748 if (sctx->chip_class >= GFX9) {
749 /* R_028A44_VGT_GS_ONCHIP_CNTL */
750 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
751 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
752 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
753 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
754 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
755 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
756 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
757 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
758 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
759 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
760
761 if (shader->key.part.gs.es->info.stage == MESA_SHADER_TESS_EVAL)
762 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
763 shader->vgt_tf_param);
764 if (shader->vgt_vertex_reuse_block_cntl)
765 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
766 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
767 shader->vgt_vertex_reuse_block_cntl);
768 }
769
770 if (initial_cdw != sctx->gfx_cs->current.cdw)
771 sctx->context_roll = true;
772 }
773
774 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
775 {
776 struct si_shader_selector *sel = shader->selector;
777 const ubyte *num_components = sel->info.num_stream_output_components;
778 unsigned gs_num_invocations = sel->info.base.gs.invocations;
779 struct si_pm4_state *pm4;
780 uint64_t va;
781 unsigned max_stream = util_last_bit(sel->info.base.gs.active_stream_mask);
782 unsigned offset;
783
784 pm4 = si_get_shader_pm4_state(shader);
785 if (!pm4)
786 return;
787
788 pm4->atom.emit = si_emit_shader_gs;
789
790 offset = num_components[0] * sel->info.base.gs.vertices_out;
791 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
792
793 if (max_stream >= 2)
794 offset += num_components[1] * sel->info.base.gs.vertices_out;
795 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
796
797 if (max_stream >= 3)
798 offset += num_components[2] * sel->info.base.gs.vertices_out;
799 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
800
801 if (max_stream >= 4)
802 offset += num_components[3] * sel->info.base.gs.vertices_out;
803 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
804
805 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
806 assert(offset < (1 << 15));
807
808 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->info.base.gs.vertices_out;
809
810 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
811 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 2) ? num_components[1] : 0;
812 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 3) ? num_components[2] : 0;
813 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 4) ? num_components[3] : 0;
814
815 shader->ctx_reg.gs.vgt_gs_instance_cnt =
816 S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0);
817
818 va = shader->bo->gpu_address;
819
820 if (sscreen->info.chip_class >= GFX9) {
821 unsigned input_prim = sel->info.base.gs.input_primitive;
822 gl_shader_stage es_stage = shader->key.part.gs.es->info.stage;
823 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
824
825 if (es_stage == MESA_SHADER_VERTEX) {
826 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
827 } else if (es_stage == MESA_SHADER_TESS_EVAL)
828 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
829 else
830 unreachable("invalid shader selector type");
831
832 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
833 * VGPR[0:4] are always loaded.
834 */
835 if (sel->info.uses_invocationid)
836 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
837 else if (sel->info.uses_primid)
838 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
839 else if (input_prim >= PIPE_PRIM_TRIANGLES)
840 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
841 else
842 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
843
844 unsigned num_user_sgprs;
845 if (es_stage == MESA_SHADER_VERTEX)
846 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
847 else
848 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
849
850 if (sscreen->info.chip_class >= GFX10) {
851 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
852 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
853 } else {
854 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
855 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
856 }
857
858 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) |
859 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
860 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
861 S_00B228_FLOAT_MODE(shader->config.float_mode) |
862 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
863 uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) |
864 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
865 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL) |
866 S_00B22C_LDS_SIZE(shader->config.lds_size) |
867 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
868
869 if (sscreen->info.chip_class >= GFX10) {
870 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
871 } else {
872 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
873 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
874 }
875
876 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
877 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
878
879 if (sscreen->info.chip_class >= GFX10) {
880 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
881 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
882 }
883
884 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
885 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
886 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
887 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
888 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
889 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
890 shader->ctx_reg.gs.vgt_esgs_ring_itemsize = shader->key.part.gs.es->esgs_itemsize / 4;
891
892 if (es_stage == MESA_SHADER_TESS_EVAL)
893 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
894
895 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es, NULL, pm4);
896 } else {
897 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
898 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
899
900 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
901 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
902 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
903 S_00B228_DX10_CLAMP(1) | S_00B228_FLOAT_MODE(shader->config.float_mode));
904 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
905 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
906 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
907 }
908 }
909
910 static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
911 {
912 enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
913
914 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
915 sctx->tracked_regs.reg_value[reg] != value) {
916 struct radeon_cmdbuf *cs = sctx->gfx_cs;
917
918 if (sctx->chip_class == GFX10) {
919 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
920 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
921 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
922 }
923
924 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
925
926 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
927 sctx->tracked_regs.reg_value[reg] = value;
928 }
929 }
930
931 /* Common tail code for NGG primitive shaders. */
932 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader *shader,
933 unsigned initial_cdw)
934 {
935 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
936 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
937 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
938 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
939 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
940 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
941 shader->ctx_reg.ngg.vgt_primitiveid_en);
942 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
943 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
944 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
945 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
946 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
947 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
948 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
949 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
950 shader->ctx_reg.ngg.spi_vs_out_config);
951 radeon_opt_set_context_reg2(
952 sctx, R_028708_SPI_SHADER_IDX_FORMAT, SI_TRACKED_SPI_SHADER_IDX_FORMAT,
953 shader->ctx_reg.ngg.spi_shader_idx_format, shader->ctx_reg.ngg.spi_shader_pos_format);
954 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
955 shader->ctx_reg.ngg.pa_cl_vte_cntl);
956 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
957 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
958
959 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
960 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, shader->pa_cl_vs_out_cntl,
961 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
962
963 if (initial_cdw != sctx->gfx_cs->current.cdw)
964 sctx->context_roll = true;
965
966 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
967 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
968 }
969
970 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
971 {
972 struct si_shader *shader = sctx->queued.named.gs->shader;
973 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
974
975 if (!shader)
976 return;
977
978 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
979 }
980
981 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
982 {
983 struct si_shader *shader = sctx->queued.named.gs->shader;
984 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
985
986 if (!shader)
987 return;
988
989 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
990 shader->vgt_tf_param);
991
992 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
993 }
994
995 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
996 {
997 struct si_shader *shader = sctx->queued.named.gs->shader;
998 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
999
1000 if (!shader)
1001 return;
1002
1003 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1004 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1005
1006 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1007 }
1008
1009 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1010 {
1011 struct si_shader *shader = sctx->queued.named.gs->shader;
1012 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1013
1014 if (!shader)
1015 return;
1016
1017 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1018 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1019 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1020 shader->vgt_tf_param);
1021
1022 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1023 }
1024
1025 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1026 {
1027 if (gs->info.stage == MESA_SHADER_GEOMETRY)
1028 return gs->info.base.gs.input_primitive;
1029
1030 if (gs->info.stage == MESA_SHADER_TESS_EVAL) {
1031 if (gs->info.base.tess.point_mode)
1032 return PIPE_PRIM_POINTS;
1033 if (gs->info.base.tess.primitive_mode == GL_LINES)
1034 return PIPE_PRIM_LINES;
1035 return PIPE_PRIM_TRIANGLES;
1036 }
1037
1038 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1039 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1040 }
1041
1042 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1043 {
1044 bool misc_vec_ena = sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1045 sel->info.writes_layer || sel->info.writes_viewport_index;
1046 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1047 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1048 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1049 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1050 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1051 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1052 }
1053
1054 /**
1055 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1056 * in NGG mode.
1057 */
1058 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1059 {
1060 const struct si_shader_selector *gs_sel = shader->selector;
1061 const struct si_shader_info *gs_info = &gs_sel->info;
1062 const gl_shader_stage gs_stage = shader->selector->info.stage;
1063 const struct si_shader_selector *es_sel =
1064 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1065 const struct si_shader_info *es_info = &es_sel->info;
1066 const gl_shader_stage es_stage = es_sel->info.stage;
1067 unsigned num_user_sgprs;
1068 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1069 uint64_t va;
1070 bool window_space = gs_info->stage == MESA_SHADER_VERTEX ?
1071 gs_info->base.vs.window_space_position : 0;
1072 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1073 unsigned gs_num_invocations = MAX2(gs_sel->info.base.gs.invocations, 1);
1074 unsigned input_prim = si_get_input_prim(gs_sel);
1075 bool break_wave_at_eoi = false;
1076 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1077 if (!pm4)
1078 return;
1079
1080 if (es_stage == MESA_SHADER_TESS_EVAL) {
1081 pm4->atom.emit = gs_stage == MESA_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1082 : gfx10_emit_shader_ngg_tess_nogs;
1083 } else {
1084 pm4->atom.emit = gs_stage == MESA_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1085 : gfx10_emit_shader_ngg_notess_nogs;
1086 }
1087
1088 va = shader->bo->gpu_address;
1089
1090 if (es_stage == MESA_SHADER_VERTEX) {
1091 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1092
1093 if (es_info->base.vs.blit_sgprs_amd) {
1094 num_user_sgprs =
1095 SI_SGPR_VS_BLIT_DATA + es_info->base.vs.blit_sgprs_amd;
1096 } else {
1097 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1098 }
1099 } else {
1100 assert(es_stage == MESA_SHADER_TESS_EVAL);
1101 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1102 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1103
1104 if (es_enable_prim_id || gs_info->uses_primid)
1105 break_wave_at_eoi = true;
1106 }
1107
1108 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1109 * VGPR[0:4] are always loaded.
1110 *
1111 * Vertex shaders always need to load VGPR3, because they need to
1112 * pass edge flags for decomposed primitives (such as quads) to the PA
1113 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1114 */
1115 if (gs_info->uses_invocationid ||
1116 (gs_stage == MESA_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1117 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1118 else if ((gs_stage == MESA_SHADER_GEOMETRY && gs_info->uses_primid) ||
1119 (gs_stage == MESA_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1120 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1121 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1122 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1123 else
1124 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1125
1126 unsigned wave_size = si_get_shader_wave_size(shader);
1127
1128 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1129 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1130 si_pm4_set_reg(
1131 pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1132 S_00B228_VGPRS((shader->config.num_vgprs - 1) / (wave_size == 32 ? 8 : 4)) |
1133 S_00B228_FLOAT_MODE(shader->config.float_mode) | S_00B228_DX10_CLAMP(1) |
1134 S_00B228_MEM_ORDERED(1) | S_00B228_WGP_MODE(1) |
1135 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1136 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1137 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1138 S_00B22C_USER_SGPR(num_user_sgprs) |
1139 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1140 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1141 S_00B22C_OC_LDS_EN(es_stage == MESA_SHADER_TESS_EVAL) |
1142 S_00B22C_LDS_SIZE(shader->config.lds_size));
1143
1144 /* Determine LATE_ALLOC_GS. */
1145 unsigned num_cu_per_sh = sscreen->info.min_good_cu_per_sa;
1146 unsigned late_alloc_wave64; /* The limit is per SA. */
1147
1148 /* For Wave32, the hw will launch twice the number of late
1149 * alloc waves, so 1 == 2x wave32.
1150 *
1151 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1152 */
1153 if (sscreen->info.family == CHIP_NAVI14 || !sscreen->info.use_late_alloc)
1154 late_alloc_wave64 = 0;
1155 else if (num_cu_per_sh <= 6)
1156 late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
1157 else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
1158 late_alloc_wave64 = (num_cu_per_sh - 2) * 6;
1159 else
1160 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
1161
1162 /* Limit LATE_ALLOC_GS for prevent a hang (hw bug). */
1163 if (sscreen->info.chip_class == GFX10)
1164 late_alloc_wave64 = MIN2(late_alloc_wave64, 64);
1165
1166 si_pm4_set_reg(
1167 pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1168 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64));
1169
1170 nparams = MAX2(shader->info.nr_param_exports, 1);
1171 shader->ctx_reg.ngg.spi_vs_out_config =
1172 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1173 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1174
1175 shader->ctx_reg.ngg.spi_shader_idx_format =
1176 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1177 shader->ctx_reg.ngg.spi_shader_pos_format =
1178 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1179 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1180 : V_02870C_SPI_SHADER_NONE) |
1181 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1182 : V_02870C_SPI_SHADER_NONE) |
1183 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1184 : V_02870C_SPI_SHADER_NONE);
1185
1186 shader->ctx_reg.ngg.vgt_primitiveid_en =
1187 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1188 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1189 gs_sel->info.writes_primid);
1190
1191 if (gs_stage == MESA_SHADER_GEOMETRY) {
1192 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1193 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->info.base.gs.vertices_out;
1194 } else {
1195 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1196 }
1197
1198 if (es_stage == MESA_SHADER_TESS_EVAL)
1199 si_set_tesseval_regs(sscreen, es_sel, pm4);
1200
1201 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1202 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1203 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1204 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1205 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1206 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1207 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl = S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1208 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1209 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1210 S_028B90_CNT(gs_num_invocations) | S_028B90_ENABLE(gs_num_invocations > 1) |
1211 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(shader->ngg.max_vert_out_per_gs_instance);
1212
1213 /* Always output hw-generated edge flags and pass them via the prim
1214 * export to prevent drawing lines on internal edges of decomposed
1215 * primitives (such as quads) with polygon mode = lines. Only VS needs
1216 * this.
1217 */
1218 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1219 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_stage == MESA_SHADER_VERTEX) |
1220 /* Reuse for NGG. */
1221 S_028838_VERTEX_REUSE_DEPTH(sscreen->info.chip_class >= GFX10_3 ? 30 : 0);
1222 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1223
1224 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1225 float oversub_pc_factor = 0.25;
1226
1227 if (shader->key.opt.ngg_culling) {
1228 /* Be more aggressive with NGG culling. */
1229 if (shader->info.nr_param_exports > 4)
1230 oversub_pc_factor = 1;
1231 else if (shader->info.nr_param_exports > 2)
1232 oversub_pc_factor = 0.75;
1233 else
1234 oversub_pc_factor = 0.5;
1235 }
1236
1237 unsigned oversub_pc_lines = sscreen->info.pc_lines * oversub_pc_factor;
1238 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
1239 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1240
1241 if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
1242 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1243 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims * 3);
1244 } else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP) {
1245 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1246 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims + 2);
1247 } else {
1248 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1249 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1250 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1251
1252 /* Bug workaround for a possible hang with non-tessellation cases.
1253 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1254 *
1255 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1256 */
1257 if ((sscreen->info.chip_class == GFX10) &&
1258 (es_stage == MESA_SHADER_VERTEX || gs_stage == MESA_SHADER_VERTEX) && /* = no tess */
1259 shader->ngg.hw_max_esverts != 256) {
1260 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1261
1262 if (shader->ngg.hw_max_esverts > 5) {
1263 shader->ge_cntl |= S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1264 }
1265 }
1266 }
1267
1268 if (window_space) {
1269 shader->ctx_reg.ngg.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1270 } else {
1271 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1272 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1273 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1274 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1275 }
1276 }
1277
1278 static void si_emit_shader_vs(struct si_context *sctx)
1279 {
1280 struct si_shader *shader = sctx->queued.named.vs->shader;
1281 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1282
1283 if (!shader)
1284 return;
1285
1286 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE, SI_TRACKED_VGT_GS_MODE,
1287 shader->ctx_reg.vs.vgt_gs_mode);
1288 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
1289 shader->ctx_reg.vs.vgt_primitiveid_en);
1290
1291 if (sctx->chip_class <= GFX8) {
1292 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
1293 shader->ctx_reg.vs.vgt_reuse_off);
1294 }
1295
1296 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
1297 shader->ctx_reg.vs.spi_vs_out_config);
1298
1299 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1300 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1301 shader->ctx_reg.vs.spi_shader_pos_format);
1302
1303 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1304 shader->ctx_reg.vs.pa_cl_vte_cntl);
1305
1306 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
1307 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1308 shader->vgt_tf_param);
1309
1310 if (shader->vgt_vertex_reuse_block_cntl)
1311 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1312 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1313 shader->vgt_vertex_reuse_block_cntl);
1314
1315 /* Required programming for tessellation. (legacy pipeline only) */
1316 if (sctx->chip_class >= GFX10 && shader->selector->info.stage == MESA_SHADER_TESS_EVAL) {
1317 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1318 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1319 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1320 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1321 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1322 }
1323
1324 if (sctx->chip_class >= GFX10) {
1325 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1326 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, shader->pa_cl_vs_out_cntl,
1327 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1328 }
1329
1330 if (initial_cdw != sctx->gfx_cs->current.cdw)
1331 sctx->context_roll = true;
1332
1333 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1334 if (sctx->chip_class >= GFX10)
1335 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
1336 }
1337
1338 /**
1339 * Compute the state for \p shader, which will run as a vertex shader on the
1340 * hardware.
1341 *
1342 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1343 * is the copy shader.
1344 */
1345 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1346 struct si_shader_selector *gs)
1347 {
1348 const struct si_shader_info *info = &shader->selector->info;
1349 struct si_pm4_state *pm4;
1350 unsigned num_user_sgprs, vgpr_comp_cnt;
1351 uint64_t va;
1352 unsigned nparams, oc_lds_en;
1353 bool window_space = info->stage == MESA_SHADER_VERTEX ?
1354 info->base.vs.window_space_position : 0;
1355 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1356
1357 pm4 = si_get_shader_pm4_state(shader);
1358 if (!pm4)
1359 return;
1360
1361 pm4->atom.emit = si_emit_shader_vs;
1362
1363 /* We always write VGT_GS_MODE in the VS state, because every switch
1364 * between different shader pipelines involving a different GS or no
1365 * GS at all involves a switch of the VS (different GS use different
1366 * copy shaders). On the other hand, when the API switches from a GS to
1367 * no GS and then back to the same GS used originally, the GS state is
1368 * not sent again.
1369 */
1370 if (!gs) {
1371 unsigned mode = V_028A40_GS_OFF;
1372
1373 /* PrimID needs GS scenario A. */
1374 if (enable_prim_id)
1375 mode = V_028A40_GS_SCENARIO_A;
1376
1377 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1378 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1379 } else {
1380 shader->ctx_reg.vs.vgt_gs_mode =
1381 ac_vgt_gs_mode(gs->info.base.gs.vertices_out, sscreen->info.chip_class);
1382 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1383 }
1384
1385 if (sscreen->info.chip_class <= GFX8) {
1386 /* Reuse needs to be set off if we write oViewport. */
1387 shader->ctx_reg.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(info->writes_viewport_index);
1388 }
1389
1390 va = shader->bo->gpu_address;
1391
1392 if (gs) {
1393 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1394 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1395 } else if (shader->selector->info.stage == MESA_SHADER_VERTEX) {
1396 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1397
1398 if (info->base.vs.blit_sgprs_amd) {
1399 num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->base.vs.blit_sgprs_amd;
1400 } else {
1401 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1402 }
1403 } else if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL) {
1404 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1405 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1406 } else
1407 unreachable("invalid shader selector type");
1408
1409 /* VS is required to export at least one param. */
1410 nparams = MAX2(shader->info.nr_param_exports, 1);
1411 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1412
1413 if (sscreen->info.chip_class >= GFX10) {
1414 shader->ctx_reg.vs.spi_vs_out_config |=
1415 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1416 }
1417
1418 shader->ctx_reg.vs.spi_shader_pos_format =
1419 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1420 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1421 : V_02870C_SPI_SHADER_NONE) |
1422 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1423 : V_02870C_SPI_SHADER_NONE) |
1424 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1425 : V_02870C_SPI_SHADER_NONE);
1426 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
1427 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1428 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1429
1430 oc_lds_en = shader->selector->info.stage == MESA_SHADER_TESS_EVAL ? 1 : 0;
1431
1432 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1433 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1434
1435 uint32_t rsrc1 =
1436 S_00B128_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1437 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B128_DX10_CLAMP(1) |
1438 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1439 S_00B128_FLOAT_MODE(shader->config.float_mode);
1440 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) | S_00B12C_OC_LDS_EN(oc_lds_en) |
1441 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1442
1443 if (sscreen->info.chip_class >= GFX10)
1444 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1445 else if (sscreen->info.chip_class == GFX9)
1446 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1447
1448 if (sscreen->info.chip_class <= GFX9)
1449 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1450
1451 if (!sscreen->use_ngg_streamout) {
1452 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1453 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1454 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1455 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1456 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1457 }
1458
1459 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1460 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1461
1462 if (window_space)
1463 shader->ctx_reg.vs.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1464 else
1465 shader->ctx_reg.vs.pa_cl_vte_cntl =
1466 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1467 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1468 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1469
1470 if (shader->selector->info.stage == MESA_SHADER_TESS_EVAL)
1471 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1472
1473 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1474 }
1475
1476 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1477 {
1478 struct si_shader_info *info = &ps->selector->info;
1479 unsigned num_colors = !!(info->colors_read & 0x0f) + !!(info->colors_read & 0xf0);
1480 unsigned num_interp =
1481 ps->selector->info.num_inputs + (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1482
1483 assert(num_interp <= 32);
1484 return MIN2(num_interp, 32);
1485 }
1486
1487 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1488 {
1489 unsigned spi_shader_col_format = shader->key.part.ps.epilog.spi_shader_col_format;
1490 unsigned value = 0, num_mrts = 0;
1491 unsigned i, num_targets = (util_last_bit(spi_shader_col_format) + 3) / 4;
1492
1493 /* Remove holes in spi_shader_col_format. */
1494 for (i = 0; i < num_targets; i++) {
1495 unsigned spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
1496
1497 if (spi_format) {
1498 value |= spi_format << (num_mrts * 4);
1499 num_mrts++;
1500 }
1501 }
1502
1503 return value;
1504 }
1505
1506 static void si_emit_shader_ps(struct si_context *sctx)
1507 {
1508 struct si_shader *shader = sctx->queued.named.ps->shader;
1509 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1510
1511 if (!shader)
1512 return;
1513
1514 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1515 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
1516 shader->ctx_reg.ps.spi_ps_input_ena,
1517 shader->ctx_reg.ps.spi_ps_input_addr);
1518
1519 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
1520 shader->ctx_reg.ps.spi_baryc_cntl);
1521 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
1522 shader->ctx_reg.ps.spi_ps_in_control);
1523
1524 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1525 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
1526 shader->ctx_reg.ps.spi_shader_z_format,
1527 shader->ctx_reg.ps.spi_shader_col_format);
1528
1529 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
1530 shader->ctx_reg.ps.cb_shader_mask);
1531
1532 if (initial_cdw != sctx->gfx_cs->current.cdw)
1533 sctx->context_roll = true;
1534 }
1535
1536 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1537 {
1538 struct si_shader_info *info = &shader->selector->info;
1539 struct si_pm4_state *pm4;
1540 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1541 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1542 uint64_t va;
1543 unsigned input_ena = shader->config.spi_ps_input_ena;
1544
1545 /* we need to enable at least one of them, otherwise we hang the GPU */
1546 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) || G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1547 G_0286CC_PERSP_CENTROID_ENA(input_ena) || G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1548 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) || G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1549 G_0286CC_LINEAR_CENTROID_ENA(input_ena) || G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1550 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1551 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) || G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1552 G_0286CC_PERSP_CENTER_ENA(input_ena) || G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1553 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1554
1555 /* Validate interpolation optimization flags (read as implications). */
1556 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1557 (G_0286CC_PERSP_CENTER_ENA(input_ena) && G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1558 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1559 (G_0286CC_LINEAR_CENTER_ENA(input_ena) && G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1560 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1561 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1562 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1563 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1564 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1565 (!G_0286CC_PERSP_CENTER_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1566 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1567 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1568
1569 /* Validate cases when the optimizations are off (read as implications). */
1570 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1571 !G_0286CC_PERSP_CENTER_ENA(input_ena) || !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1572 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1573 !G_0286CC_LINEAR_CENTER_ENA(input_ena) || !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1574
1575 pm4 = si_get_shader_pm4_state(shader);
1576 if (!pm4)
1577 return;
1578
1579 pm4->atom.emit = si_emit_shader_ps;
1580
1581 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1582 * Possible vaules:
1583 * 0 -> Position = pixel center
1584 * 1 -> Position = pixel centroid
1585 * 2 -> Position = at sample position
1586 *
1587 * From GLSL 4.5 specification, section 7.1:
1588 * "The variable gl_FragCoord is available as an input variable from
1589 * within fragment shaders and it holds the window relative coordinates
1590 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1591 * value can be for any location within the pixel, or one of the
1592 * fragment samples. The use of centroid does not further restrict
1593 * this value to be inside the current primitive."
1594 *
1595 * Meaning that centroid has no effect and we can return anything within
1596 * the pixel. Thus, return the value at sample position, because that's
1597 * the most accurate one shaders can get.
1598 */
1599 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1600
1601 if (info->base.fs.pixel_center_integer)
1602 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1603
1604 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1605 cb_shader_mask = ac_get_cb_shader_mask(shader->key.part.ps.epilog.spi_shader_col_format);
1606
1607 /* Ensure that some export memory is always allocated, for two reasons:
1608 *
1609 * 1) Correctness: The hardware ignores the EXEC mask if no export
1610 * memory is allocated, so KILL and alpha test do not work correctly
1611 * without this.
1612 * 2) Performance: Every shader needs at least a NULL export, even when
1613 * it writes no color/depth output. The NULL export instruction
1614 * stalls without this setting.
1615 *
1616 * Don't add this to CB_SHADER_MASK.
1617 *
1618 * GFX10 supports pixel shaders without exports by setting both
1619 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1620 * instructions if any are present.
1621 */
1622 if ((sscreen->info.chip_class <= GFX9 || info->base.fs.uses_discard ||
1623 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1624 !spi_shader_col_format && !info->writes_z && !info->writes_stencil &&
1625 !info->writes_samplemask)
1626 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1627
1628 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1629 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1630
1631 /* Set interpolation controls. */
1632 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1633 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1634
1635 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1636 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1637 shader->ctx_reg.ps.spi_shader_z_format =
1638 ac_get_spi_shader_z_format(info->writes_z, info->writes_stencil, info->writes_samplemask);
1639 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1640 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1641
1642 va = shader->bo->gpu_address;
1643 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1644 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1645
1646 uint32_t rsrc1 =
1647 S_00B028_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1648 S_00B028_DX10_CLAMP(1) | S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1649 S_00B028_FLOAT_MODE(shader->config.float_mode);
1650
1651 if (sscreen->info.chip_class < GFX10) {
1652 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1653 }
1654
1655 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1656 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1657 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1658 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1659 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1660 }
1661
1662 static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader *shader)
1663 {
1664 switch (shader->selector->info.stage) {
1665 case MESA_SHADER_VERTEX:
1666 if (shader->key.as_ls)
1667 si_shader_ls(sscreen, shader);
1668 else if (shader->key.as_es)
1669 si_shader_es(sscreen, shader);
1670 else if (shader->key.as_ngg)
1671 gfx10_shader_ngg(sscreen, shader);
1672 else
1673 si_shader_vs(sscreen, shader, NULL);
1674 break;
1675 case MESA_SHADER_TESS_CTRL:
1676 si_shader_hs(sscreen, shader);
1677 break;
1678 case MESA_SHADER_TESS_EVAL:
1679 if (shader->key.as_es)
1680 si_shader_es(sscreen, shader);
1681 else if (shader->key.as_ngg)
1682 gfx10_shader_ngg(sscreen, shader);
1683 else
1684 si_shader_vs(sscreen, shader, NULL);
1685 break;
1686 case MESA_SHADER_GEOMETRY:
1687 if (shader->key.as_ngg)
1688 gfx10_shader_ngg(sscreen, shader);
1689 else
1690 si_shader_gs(sscreen, shader);
1691 break;
1692 case MESA_SHADER_FRAGMENT:
1693 si_shader_ps(sscreen, shader);
1694 break;
1695 default:
1696 assert(0);
1697 }
1698 }
1699
1700 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1701 {
1702 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1703 return sctx->queued.named.dsa->alpha_func;
1704 }
1705
1706 void si_shader_selector_key_vs(struct si_context *sctx, struct si_shader_selector *vs,
1707 struct si_shader_key *key, struct si_vs_prolog_bits *prolog_key)
1708 {
1709 if (!sctx->vertex_elements || vs->info.base.vs.blit_sgprs_amd)
1710 return;
1711
1712 struct si_vertex_elements *elts = sctx->vertex_elements;
1713
1714 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1715 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1716 prolog_key->unpack_instance_id_from_vertex_id = sctx->prim_discard_cs_instancing;
1717
1718 /* Prefer a monolithic shader to allow scheduling divisions around
1719 * VBO loads. */
1720 if (prolog_key->instance_divisor_is_fetched)
1721 key->opt.prefer_mono = 1;
1722
1723 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1724 unsigned count_mask = (1 << count) - 1;
1725 unsigned fix = elts->fix_fetch_always & count_mask;
1726 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1727
1728 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1729 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1730 while (mask) {
1731 unsigned i = u_bit_scan(&mask);
1732 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1733 unsigned vbidx = elts->vertex_buffer_index[i];
1734 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1735 unsigned align_mask = (1 << log_hw_load_size) - 1;
1736 if (vb->buffer_offset & align_mask || vb->stride & align_mask) {
1737 fix |= 1 << i;
1738 opencode |= 1 << i;
1739 }
1740 }
1741 }
1742
1743 while (fix) {
1744 unsigned i = u_bit_scan(&fix);
1745 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1746 }
1747 key->mono.vs_fetch_opencode = opencode;
1748 }
1749
1750 static void si_shader_selector_key_hw_vs(struct si_context *sctx, struct si_shader_selector *vs,
1751 struct si_shader_key *key)
1752 {
1753 struct si_shader_selector *ps = sctx->ps_shader.cso;
1754
1755 key->opt.clip_disable = sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1756 (vs->info.base.clip_distance_array_size || vs->info.writes_clipvertex) &&
1757 !vs->info.base.cull_distance_array_size;
1758
1759 /* Find out if PS is disabled. */
1760 bool ps_disabled = true;
1761 if (ps) {
1762 bool ps_modifies_zs = ps->info.base.fs.uses_discard || ps->info.writes_z || ps->info.writes_stencil ||
1763 ps->info.writes_samplemask ||
1764 sctx->queued.named.blend->alpha_to_coverage ||
1765 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1766 unsigned ps_colormask = si_get_total_colormask(sctx);
1767
1768 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1769 (!ps_colormask && !ps_modifies_zs && !ps->info.base.writes_memory);
1770 }
1771
1772 /* Find out which VS outputs aren't used by the PS. */
1773 uint64_t outputs_written = vs->outputs_written_before_ps;
1774 uint64_t inputs_read = 0;
1775
1776 /* Ignore outputs that are not passed from VS to PS. */
1777 outputs_written &= ~((1ull << si_shader_io_get_unique_index(VARYING_SLOT_POS, true)) |
1778 (1ull << si_shader_io_get_unique_index(VARYING_SLOT_PSIZ, true)) |
1779 (1ull << si_shader_io_get_unique_index(VARYING_SLOT_CLIP_VERTEX, true)));
1780
1781 if (!ps_disabled) {
1782 inputs_read = ps->inputs_read;
1783 }
1784
1785 uint64_t linked = outputs_written & inputs_read;
1786
1787 key->opt.kill_outputs = ~linked & outputs_written;
1788 key->opt.ngg_culling = sctx->ngg_culling;
1789 }
1790
1791 /* Compute the key for the hw shader variant */
1792 static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_shader_selector *sel,
1793 union si_vgt_stages_key stages_key,
1794 struct si_shader_key *key)
1795 {
1796 struct si_context *sctx = (struct si_context *)ctx;
1797
1798 memset(key, 0, sizeof(*key));
1799
1800 switch (sel->info.stage) {
1801 case MESA_SHADER_VERTEX:
1802 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1803
1804 if (sctx->tes_shader.cso)
1805 key->as_ls = 1;
1806 else if (sctx->gs_shader.cso) {
1807 key->as_es = 1;
1808 key->as_ngg = stages_key.u.ngg;
1809 } else {
1810 key->as_ngg = stages_key.u.ngg;
1811 si_shader_selector_key_hw_vs(sctx, sel, key);
1812
1813 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1814 key->mono.u.vs_export_prim_id = 1;
1815 }
1816 break;
1817 case MESA_SHADER_TESS_CTRL:
1818 if (sctx->chip_class >= GFX9) {
1819 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.tcs.ls_prolog);
1820 key->part.tcs.ls = sctx->vs_shader.cso;
1821
1822 /* When the LS VGPR fix is needed, monolithic shaders
1823 * can:
1824 * - avoid initializing EXEC in both the LS prolog
1825 * and the LS main part when !vs_needs_prolog
1826 * - remove the fixup for unused input VGPRs
1827 */
1828 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1829
1830 /* The LS output / HS input layout can be communicated
1831 * directly instead of via user SGPRs for merged LS-HS.
1832 * The LS VGPR fix prefers this too.
1833 */
1834 key->opt.prefer_mono = 1;
1835 }
1836
1837 key->part.tcs.epilog.prim_mode =
1838 sctx->tes_shader.cso->info.base.tess.primitive_mode;
1839 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1840 sel->info.tessfactors_are_def_in_all_invocs;
1841 key->part.tcs.epilog.tes_reads_tess_factors = sctx->tes_shader.cso->info.reads_tess_factors;
1842
1843 if (sel == sctx->fixed_func_tcs_shader.cso)
1844 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1845 break;
1846 case MESA_SHADER_TESS_EVAL:
1847 key->as_ngg = stages_key.u.ngg;
1848
1849 if (sctx->gs_shader.cso)
1850 key->as_es = 1;
1851 else {
1852 si_shader_selector_key_hw_vs(sctx, sel, key);
1853
1854 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1855 key->mono.u.vs_export_prim_id = 1;
1856 }
1857 break;
1858 case MESA_SHADER_GEOMETRY:
1859 if (sctx->chip_class >= GFX9) {
1860 if (sctx->tes_shader.cso) {
1861 key->part.gs.es = sctx->tes_shader.cso;
1862 } else {
1863 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.gs.vs_prolog);
1864 key->part.gs.es = sctx->vs_shader.cso;
1865 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1866 }
1867
1868 key->as_ngg = stages_key.u.ngg;
1869
1870 /* Merged ES-GS can have unbalanced wave usage.
1871 *
1872 * ES threads are per-vertex, while GS threads are
1873 * per-primitive. So without any amplification, there
1874 * are fewer GS threads than ES threads, which can result
1875 * in empty (no-op) GS waves. With too much amplification,
1876 * there are more GS threads than ES threads, which
1877 * can result in empty (no-op) ES waves.
1878 *
1879 * Non-monolithic shaders are implemented by setting EXEC
1880 * at the beginning of shader parts, and don't jump to
1881 * the end if EXEC is 0.
1882 *
1883 * Monolithic shaders use conditional blocks, so they can
1884 * jump and skip empty waves of ES or GS. So set this to
1885 * always use optimized variants, which are monolithic.
1886 */
1887 key->opt.prefer_mono = 1;
1888 }
1889 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1890 break;
1891 case MESA_SHADER_FRAGMENT: {
1892 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1893 struct si_state_blend *blend = sctx->queued.named.blend;
1894
1895 if (sel->info.color0_writes_all_cbufs &&
1896 sel->info.colors_written == 0x1)
1897 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1898
1899 /* Select the shader color format based on whether
1900 * blending or alpha are needed.
1901 */
1902 key->part.ps.epilog.spi_shader_col_format =
1903 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1904 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1905 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1906 sctx->framebuffer.spi_shader_col_format_blend) |
1907 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1908 sctx->framebuffer.spi_shader_col_format_alpha) |
1909 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1910 sctx->framebuffer.spi_shader_col_format);
1911 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1912
1913 /* The output for dual source blending should have
1914 * the same format as the first output.
1915 */
1916 if (blend->dual_src_blend) {
1917 key->part.ps.epilog.spi_shader_col_format |=
1918 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1919 }
1920
1921 /* If alpha-to-coverage is enabled, we have to export alpha
1922 * even if there is no color buffer.
1923 */
1924 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) && blend->alpha_to_coverage)
1925 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1926
1927 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1928 * to the range supported by the type if a channel has less
1929 * than 16 bits and the export format is 16_ABGR.
1930 */
1931 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1932 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1933 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1934 }
1935
1936 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1937 if (!key->part.ps.epilog.last_cbuf) {
1938 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1939 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1940 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1941 }
1942
1943 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1944 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1945
1946 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1947 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1948
1949 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one && rs->multisample_enable;
1950
1951 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1952 key->part.ps.epilog.poly_line_smoothing =
1953 ((is_poly && rs->poly_smooth) || (is_line && rs->line_smooth)) &&
1954 sctx->framebuffer.nr_samples <= 1;
1955 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1956
1957 if (sctx->ps_iter_samples > 1 && sel->info.reads_samplemask) {
1958 key->part.ps.prolog.samplemask_log_ps_iter = util_logbase2(sctx->ps_iter_samples);
1959 }
1960
1961 if (rs->force_persample_interp && rs->multisample_enable &&
1962 sctx->framebuffer.nr_samples > 1 && sctx->ps_iter_samples > 1) {
1963 key->part.ps.prolog.force_persp_sample_interp =
1964 sel->info.uses_persp_center || sel->info.uses_persp_centroid;
1965
1966 key->part.ps.prolog.force_linear_sample_interp =
1967 sel->info.uses_linear_center || sel->info.uses_linear_centroid;
1968 } else if (rs->multisample_enable && sctx->framebuffer.nr_samples > 1) {
1969 key->part.ps.prolog.bc_optimize_for_persp =
1970 sel->info.uses_persp_center && sel->info.uses_persp_centroid;
1971 key->part.ps.prolog.bc_optimize_for_linear =
1972 sel->info.uses_linear_center && sel->info.uses_linear_centroid;
1973 } else {
1974 /* Make sure SPI doesn't compute more than 1 pair
1975 * of (i,j), which is the optimization here. */
1976 key->part.ps.prolog.force_persp_center_interp = sel->info.uses_persp_center +
1977 sel->info.uses_persp_centroid +
1978 sel->info.uses_persp_sample >
1979 1;
1980
1981 key->part.ps.prolog.force_linear_center_interp = sel->info.uses_linear_center +
1982 sel->info.uses_linear_centroid +
1983 sel->info.uses_linear_sample >
1984 1;
1985
1986 if (sel->info.uses_interp_at_sample)
1987 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1988 }
1989
1990 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1991
1992 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1993 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1994 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1995 struct pipe_resource *tex = cb0->texture;
1996
1997 /* 1D textures are allocated and used as 2D on GFX9. */
1998 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1999 key->mono.u.ps.fbfetch_is_1D =
2000 sctx->chip_class != GFX9 &&
2001 (tex->target == PIPE_TEXTURE_1D || tex->target == PIPE_TEXTURE_1D_ARRAY);
2002 key->mono.u.ps.fbfetch_layered =
2003 tex->target == PIPE_TEXTURE_1D_ARRAY || tex->target == PIPE_TEXTURE_2D_ARRAY ||
2004 tex->target == PIPE_TEXTURE_CUBE || tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2005 tex->target == PIPE_TEXTURE_3D;
2006 }
2007 break;
2008 }
2009 default:
2010 assert(0);
2011 }
2012
2013 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2014 memset(&key->opt, 0, sizeof(key->opt));
2015 }
2016
2017 static void si_build_shader_variant(struct si_shader *shader, int thread_index, bool low_priority)
2018 {
2019 struct si_shader_selector *sel = shader->selector;
2020 struct si_screen *sscreen = sel->screen;
2021 struct ac_llvm_compiler *compiler;
2022 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2023
2024 if (thread_index >= 0) {
2025 if (low_priority) {
2026 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2027 compiler = &sscreen->compiler_lowp[thread_index];
2028 } else {
2029 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2030 compiler = &sscreen->compiler[thread_index];
2031 }
2032 if (!debug->async)
2033 debug = NULL;
2034 } else {
2035 assert(!low_priority);
2036 compiler = shader->compiler_ctx_state.compiler;
2037 }
2038
2039 if (!compiler->passes)
2040 si_init_compiler(sscreen, compiler);
2041
2042 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2043 PRINT_ERR("Failed to build shader variant (type=%u)\n", sel->info.stage);
2044 shader->compilation_failed = true;
2045 return;
2046 }
2047
2048 if (shader->compiler_ctx_state.is_debug_context) {
2049 FILE *f = open_memstream(&shader->shader_log, &shader->shader_log_size);
2050 if (f) {
2051 si_shader_dump(sscreen, shader, NULL, f, false);
2052 fclose(f);
2053 }
2054 }
2055
2056 si_shader_init_pm4_state(sscreen, shader);
2057 }
2058
2059 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2060 {
2061 struct si_shader *shader = (struct si_shader *)job;
2062
2063 assert(thread_index >= 0);
2064
2065 si_build_shader_variant(shader, thread_index, true);
2066 }
2067
2068 static const struct si_shader_key zeroed;
2069
2070 static bool si_check_missing_main_part(struct si_screen *sscreen, struct si_shader_selector *sel,
2071 struct si_compiler_ctx_state *compiler_state,
2072 struct si_shader_key *key)
2073 {
2074 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2075
2076 if (!*mainp) {
2077 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2078
2079 if (!main_part)
2080 return false;
2081
2082 /* We can leave the fence as permanently signaled because the
2083 * main part becomes visible globally only after it has been
2084 * compiled. */
2085 util_queue_fence_init(&main_part->ready);
2086
2087 main_part->selector = sel;
2088 main_part->key.as_es = key->as_es;
2089 main_part->key.as_ls = key->as_ls;
2090 main_part->key.as_ngg = key->as_ngg;
2091 main_part->is_monolithic = false;
2092
2093 if (!si_compile_shader(sscreen, compiler_state->compiler, main_part,
2094 &compiler_state->debug)) {
2095 FREE(main_part);
2096 return false;
2097 }
2098 *mainp = main_part;
2099 }
2100 return true;
2101 }
2102
2103 /**
2104 * Select a shader variant according to the shader key.
2105 *
2106 * \param optimized_or_none If the key describes an optimized shader variant and
2107 * the compilation isn't finished, don't select any
2108 * shader and return an error.
2109 */
2110 int si_shader_select_with_key(struct si_screen *sscreen, struct si_shader_ctx_state *state,
2111 struct si_compiler_ctx_state *compiler_state,
2112 struct si_shader_key *key, int thread_index, bool optimized_or_none)
2113 {
2114 struct si_shader_selector *sel = state->cso;
2115 struct si_shader_selector *previous_stage_sel = NULL;
2116 struct si_shader *current = state->current;
2117 struct si_shader *iter, *shader = NULL;
2118
2119 again:
2120 /* Check if we don't need to change anything.
2121 * This path is also used for most shaders that don't need multiple
2122 * variants, it will cost just a computation of the key and this
2123 * test. */
2124 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0)) {
2125 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2126 if (current->is_optimized) {
2127 if (optimized_or_none)
2128 return -1;
2129
2130 memset(&key->opt, 0, sizeof(key->opt));
2131 goto current_not_ready;
2132 }
2133
2134 util_queue_fence_wait(&current->ready);
2135 }
2136
2137 return current->compilation_failed ? -1 : 0;
2138 }
2139 current_not_ready:
2140
2141 /* This must be done before the mutex is locked, because async GS
2142 * compilation calls this function too, and therefore must enter
2143 * the mutex first.
2144 *
2145 * Only wait if we are in a draw call. Don't wait if we are
2146 * in a compiler thread.
2147 */
2148 if (thread_index < 0)
2149 util_queue_fence_wait(&sel->ready);
2150
2151 simple_mtx_lock(&sel->mutex);
2152
2153 /* Find the shader variant. */
2154 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2155 /* Don't check the "current" shader. We checked it above. */
2156 if (current != iter && memcmp(&iter->key, key, sizeof(*key)) == 0) {
2157 simple_mtx_unlock(&sel->mutex);
2158
2159 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2160 /* If it's an optimized shader and its compilation has
2161 * been started but isn't done, use the unoptimized
2162 * shader so as not to cause a stall due to compilation.
2163 */
2164 if (iter->is_optimized) {
2165 if (optimized_or_none)
2166 return -1;
2167 memset(&key->opt, 0, sizeof(key->opt));
2168 goto again;
2169 }
2170
2171 util_queue_fence_wait(&iter->ready);
2172 }
2173
2174 if (iter->compilation_failed) {
2175 return -1; /* skip the draw call */
2176 }
2177
2178 state->current = iter;
2179 return 0;
2180 }
2181 }
2182
2183 /* Build a new shader. */
2184 shader = CALLOC_STRUCT(si_shader);
2185 if (!shader) {
2186 simple_mtx_unlock(&sel->mutex);
2187 return -ENOMEM;
2188 }
2189
2190 util_queue_fence_init(&shader->ready);
2191
2192 shader->selector = sel;
2193 shader->key = *key;
2194 shader->compiler_ctx_state = *compiler_state;
2195
2196 /* If this is a merged shader, get the first shader's selector. */
2197 if (sscreen->info.chip_class >= GFX9) {
2198 if (sel->info.stage == MESA_SHADER_TESS_CTRL)
2199 previous_stage_sel = key->part.tcs.ls;
2200 else if (sel->info.stage == MESA_SHADER_GEOMETRY)
2201 previous_stage_sel = key->part.gs.es;
2202
2203 /* We need to wait for the previous shader. */
2204 if (previous_stage_sel && thread_index < 0)
2205 util_queue_fence_wait(&previous_stage_sel->ready);
2206 }
2207
2208 bool is_pure_monolithic =
2209 sscreen->use_monolithic_shaders || memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2210
2211 /* Compile the main shader part if it doesn't exist. This can happen
2212 * if the initial guess was wrong.
2213 *
2214 * The prim discard CS doesn't need the main shader part.
2215 */
2216 if (!is_pure_monolithic && !key->opt.vs_as_prim_discard_cs) {
2217 bool ok = true;
2218
2219 /* Make sure the main shader part is present. This is needed
2220 * for shaders that can be compiled as VS, LS, or ES, and only
2221 * one of them is compiled at creation.
2222 *
2223 * It is also needed for GS, which can be compiled as non-NGG
2224 * and NGG.
2225 *
2226 * For merged shaders, check that the starting shader's main
2227 * part is present.
2228 */
2229 if (previous_stage_sel) {
2230 struct si_shader_key shader1_key = zeroed;
2231
2232 if (sel->info.stage == MESA_SHADER_TESS_CTRL) {
2233 shader1_key.as_ls = 1;
2234 } else if (sel->info.stage == MESA_SHADER_GEOMETRY) {
2235 shader1_key.as_es = 1;
2236 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2237 } else {
2238 assert(0);
2239 }
2240
2241 simple_mtx_lock(&previous_stage_sel->mutex);
2242 ok = si_check_missing_main_part(sscreen, previous_stage_sel, compiler_state, &shader1_key);
2243 simple_mtx_unlock(&previous_stage_sel->mutex);
2244 }
2245
2246 if (ok) {
2247 ok = si_check_missing_main_part(sscreen, sel, compiler_state, key);
2248 }
2249
2250 if (!ok) {
2251 FREE(shader);
2252 simple_mtx_unlock(&sel->mutex);
2253 return -ENOMEM; /* skip the draw call */
2254 }
2255 }
2256
2257 /* Keep the reference to the 1st shader of merged shaders, so that
2258 * Gallium can't destroy it before we destroy the 2nd shader.
2259 *
2260 * Set sctx = NULL, because it's unused if we're not releasing
2261 * the shader, and we don't have any sctx here.
2262 */
2263 si_shader_selector_reference(NULL, &shader->previous_stage_sel, previous_stage_sel);
2264
2265 /* Monolithic-only shaders don't make a distinction between optimized
2266 * and unoptimized. */
2267 shader->is_monolithic =
2268 is_pure_monolithic || memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2269
2270 /* The prim discard CS is always optimized. */
2271 shader->is_optimized = (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2272 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2273
2274 /* If it's an optimized shader, compile it asynchronously. */
2275 if (shader->is_optimized && thread_index < 0) {
2276 /* Compile it asynchronously. */
2277 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority, shader, &shader->ready,
2278 si_build_shader_variant_low_priority, NULL, 0);
2279
2280 /* Add only after the ready fence was reset, to guard against a
2281 * race with si_bind_XX_shader. */
2282 if (!sel->last_variant) {
2283 sel->first_variant = shader;
2284 sel->last_variant = shader;
2285 } else {
2286 sel->last_variant->next_variant = shader;
2287 sel->last_variant = shader;
2288 }
2289
2290 /* Use the default (unoptimized) shader for now. */
2291 memset(&key->opt, 0, sizeof(key->opt));
2292 simple_mtx_unlock(&sel->mutex);
2293
2294 if (sscreen->options.sync_compile)
2295 util_queue_fence_wait(&shader->ready);
2296
2297 if (optimized_or_none)
2298 return -1;
2299 goto again;
2300 }
2301
2302 /* Reset the fence before adding to the variant list. */
2303 util_queue_fence_reset(&shader->ready);
2304
2305 if (!sel->last_variant) {
2306 sel->first_variant = shader;
2307 sel->last_variant = shader;
2308 } else {
2309 sel->last_variant->next_variant = shader;
2310 sel->last_variant = shader;
2311 }
2312
2313 simple_mtx_unlock(&sel->mutex);
2314
2315 assert(!shader->is_optimized);
2316 si_build_shader_variant(shader, thread_index, false);
2317
2318 util_queue_fence_signal(&shader->ready);
2319
2320 if (!shader->compilation_failed)
2321 state->current = shader;
2322
2323 return shader->compilation_failed ? -1 : 0;
2324 }
2325
2326 static int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state,
2327 union si_vgt_stages_key stages_key,
2328 struct si_compiler_ctx_state *compiler_state)
2329 {
2330 struct si_context *sctx = (struct si_context *)ctx;
2331 struct si_shader_key key;
2332
2333 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2334 return si_shader_select_with_key(sctx->screen, state, compiler_state, &key, -1, false);
2335 }
2336
2337 static void si_parse_next_shader_property(const struct si_shader_info *info, bool streamout,
2338 struct si_shader_key *key)
2339 {
2340 gl_shader_stage next_shader = info->base.next_stage;
2341
2342 switch (info->stage) {
2343 case MESA_SHADER_VERTEX:
2344 switch (next_shader) {
2345 case MESA_SHADER_GEOMETRY:
2346 key->as_es = 1;
2347 break;
2348 case MESA_SHADER_TESS_CTRL:
2349 case MESA_SHADER_TESS_EVAL:
2350 key->as_ls = 1;
2351 break;
2352 default:
2353 /* If POSITION isn't written, it can only be a HW VS
2354 * if streamout is used. If streamout isn't used,
2355 * assume that it's a HW LS. (the next shader is TCS)
2356 * This heuristic is needed for separate shader objects.
2357 */
2358 if (!info->writes_position && !streamout)
2359 key->as_ls = 1;
2360 }
2361 break;
2362
2363 case MESA_SHADER_TESS_EVAL:
2364 if (next_shader == MESA_SHADER_GEOMETRY || !info->writes_position)
2365 key->as_es = 1;
2366 break;
2367
2368 default:;
2369 }
2370 }
2371
2372 /**
2373 * Compile the main shader part or the monolithic shader as part of
2374 * si_shader_selector initialization. Since it can be done asynchronously,
2375 * there is no way to report compile failures to applications.
2376 */
2377 static void si_init_shader_selector_async(void *job, int thread_index)
2378 {
2379 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2380 struct si_screen *sscreen = sel->screen;
2381 struct ac_llvm_compiler *compiler;
2382 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2383
2384 assert(!debug->debug_message || debug->async);
2385 assert(thread_index >= 0);
2386 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2387 compiler = &sscreen->compiler[thread_index];
2388
2389 if (!compiler->passes)
2390 si_init_compiler(sscreen, compiler);
2391
2392 /* Serialize NIR to save memory. Monolithic shader variants
2393 * have to deserialize NIR before compilation.
2394 */
2395 if (sel->nir) {
2396 struct blob blob;
2397 size_t size;
2398
2399 blob_init(&blob);
2400 /* true = remove optional debugging data to increase
2401 * the likehood of getting more shader cache hits.
2402 * It also drops variable names, so we'll save more memory.
2403 */
2404 nir_serialize(&blob, sel->nir, true);
2405 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2406 sel->nir_size = size;
2407 }
2408
2409 /* Compile the main shader part for use with a prolog and/or epilog.
2410 * If this fails, the driver will try to compile a monolithic shader
2411 * on demand.
2412 */
2413 if (!sscreen->use_monolithic_shaders) {
2414 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2415 unsigned char ir_sha1_cache_key[20];
2416
2417 if (!shader) {
2418 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2419 return;
2420 }
2421
2422 /* We can leave the fence signaled because use of the default
2423 * main part is guarded by the selector's ready fence. */
2424 util_queue_fence_init(&shader->ready);
2425
2426 shader->selector = sel;
2427 shader->is_monolithic = false;
2428 si_parse_next_shader_property(&sel->info, sel->so.num_outputs != 0, &shader->key);
2429
2430 if (sscreen->use_ngg && (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2431 ((sel->info.stage == MESA_SHADER_VERTEX && !shader->key.as_ls) ||
2432 sel->info.stage == MESA_SHADER_TESS_EVAL || sel->info.stage == MESA_SHADER_GEOMETRY))
2433 shader->key.as_ngg = 1;
2434
2435 if (sel->nir) {
2436 si_get_ir_cache_key(sel, shader->key.as_ngg, shader->key.as_es, ir_sha1_cache_key);
2437 }
2438
2439 /* Try to load the shader from the shader cache. */
2440 simple_mtx_lock(&sscreen->shader_cache_mutex);
2441
2442 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2443 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2444 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2445 } else {
2446 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2447
2448 /* Compile the shader if it hasn't been loaded from the cache. */
2449 if (!si_compile_shader(sscreen, compiler, shader, debug)) {
2450 FREE(shader);
2451 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2452 return;
2453 }
2454
2455 simple_mtx_lock(&sscreen->shader_cache_mutex);
2456 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
2457 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2458 }
2459
2460 *si_get_main_shader_part(sel, &shader->key) = shader;
2461
2462 /* Unset "outputs_written" flags for outputs converted to
2463 * DEFAULT_VAL, so that later inter-shader optimizations don't
2464 * try to eliminate outputs that don't exist in the final
2465 * shader.
2466 *
2467 * This is only done if non-monolithic shaders are enabled.
2468 */
2469 if ((sel->info.stage == MESA_SHADER_VERTEX || sel->info.stage == MESA_SHADER_TESS_EVAL) &&
2470 !shader->key.as_ls && !shader->key.as_es) {
2471 unsigned i;
2472
2473 for (i = 0; i < sel->info.num_outputs; i++) {
2474 unsigned offset = shader->info.vs_output_param_offset[i];
2475
2476 if (offset <= AC_EXP_PARAM_OFFSET_31)
2477 continue;
2478
2479 unsigned semantic = sel->info.output_semantic[i];
2480 unsigned id;
2481
2482 if (semantic < VARYING_SLOT_MAX &&
2483 semantic != VARYING_SLOT_POS &&
2484 semantic != VARYING_SLOT_PSIZ &&
2485 semantic != VARYING_SLOT_CLIP_VERTEX &&
2486 semantic != VARYING_SLOT_EDGE) {
2487 id = si_shader_io_get_unique_index(semantic, true);
2488 sel->outputs_written_before_ps &= ~(1ull << id);
2489 }
2490 }
2491 }
2492 }
2493
2494 /* The GS copy shader is always pre-compiled. */
2495 if (sel->info.stage == MESA_SHADER_GEOMETRY &&
2496 (!sscreen->use_ngg || !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2497 sel->tess_turns_off_ngg)) {
2498 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2499 if (!sel->gs_copy_shader) {
2500 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2501 return;
2502 }
2503
2504 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2505 }
2506
2507 /* Free NIR. We only keep serialized NIR after this point. */
2508 if (sel->nir) {
2509 ralloc_free(sel->nir);
2510 sel->nir = NULL;
2511 }
2512 }
2513
2514 void si_schedule_initial_compile(struct si_context *sctx, gl_shader_stage stage,
2515 struct util_queue_fence *ready_fence,
2516 struct si_compiler_ctx_state *compiler_ctx_state, void *job,
2517 util_queue_execute_func execute)
2518 {
2519 util_queue_fence_init(ready_fence);
2520
2521 struct util_async_debug_callback async_debug;
2522 bool debug = (sctx->debug.debug_message && !sctx->debug.async) || sctx->is_debug ||
2523 si_can_dump_shader(sctx->screen, stage);
2524
2525 if (debug) {
2526 u_async_debug_init(&async_debug);
2527 compiler_ctx_state->debug = async_debug.base;
2528 }
2529
2530 util_queue_add_job(&sctx->screen->shader_compiler_queue, job, ready_fence, execute, NULL, 0);
2531
2532 if (debug) {
2533 util_queue_fence_wait(ready_fence);
2534 u_async_debug_drain(&async_debug, &sctx->debug);
2535 u_async_debug_cleanup(&async_debug);
2536 }
2537
2538 if (sctx->screen->options.sync_compile)
2539 util_queue_fence_wait(ready_fence);
2540 }
2541
2542 /* Return descriptor slot usage masks from the given shader info. */
2543 void si_get_active_slot_masks(const struct si_shader_info *info, uint64_t *const_and_shader_buffers,
2544 uint64_t *samplers_and_images)
2545 {
2546 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2547
2548 num_shaderbufs = info->base.num_ssbos;
2549 num_constbufs = info->base.num_ubos;
2550 /* two 8-byte images share one 16-byte slot */
2551 num_images = align(info->base.num_images, 2);
2552 num_msaa_images = align(util_last_bit(info->base.msaa_images), 2);
2553 num_samplers = util_last_bit(info->base.textures_used);
2554
2555 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2556 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2557 *const_and_shader_buffers = u_bit_consecutive64(start, num_shaderbufs + num_constbufs);
2558
2559 /* The layout is:
2560 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2561 * - image[last] ... image[0] go to [31-last .. 31]
2562 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2563 *
2564 * FMASKs for images are placed separately, because MSAA images are rare,
2565 * and so we can benefit from a better cache hit rate if we keep image
2566 * descriptors together.
2567 */
2568 if (num_msaa_images)
2569 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2570
2571 start = si_get_image_slot(num_images - 1) / 2;
2572 *samplers_and_images = u_bit_consecutive64(start, num_images / 2 + num_samplers);
2573 }
2574
2575 static void *si_create_shader_selector(struct pipe_context *ctx,
2576 const struct pipe_shader_state *state)
2577 {
2578 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2579 struct si_context *sctx = (struct si_context *)ctx;
2580 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2581 int i;
2582
2583 if (!sel)
2584 return NULL;
2585
2586 sel->screen = sscreen;
2587 sel->compiler_ctx_state.debug = sctx->debug;
2588 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2589
2590 sel->so = state->stream_output;
2591
2592 if (state->type == PIPE_SHADER_IR_TGSI) {
2593 sel->nir = tgsi_to_nir(state->tokens, ctx->screen, true);
2594 } else {
2595 assert(state->type == PIPE_SHADER_IR_NIR);
2596 sel->nir = state->ir.nir;
2597 }
2598
2599 si_nir_scan_shader(sel->nir, &sel->info);
2600
2601 const enum pipe_shader_type type = pipe_shader_type_from_mesa(sel->info.stage);
2602 sel->const_and_shader_buf_descriptors_index =
2603 si_const_and_shader_buffer_descriptors_idx(type);
2604 sel->sampler_and_images_descriptors_index =
2605 si_sampler_and_image_descriptors_idx(type);
2606
2607 p_atomic_inc(&sscreen->num_shaders_created);
2608 si_get_active_slot_masks(&sel->info, &sel->active_const_and_shader_buffers,
2609 &sel->active_samplers_and_images);
2610
2611 /* Record which streamout buffers are enabled. */
2612 for (i = 0; i < sel->so.num_outputs; i++) {
2613 sel->enabled_streamout_buffer_mask |= (1 << sel->so.output[i].output_buffer)
2614 << (sel->so.output[i].stream * 4);
2615 }
2616
2617 sel->num_vs_inputs =
2618 sel->info.stage == MESA_SHADER_VERTEX && !sel->info.base.vs.blit_sgprs_amd
2619 ? sel->info.num_inputs
2620 : 0;
2621 sel->num_vbos_in_user_sgprs = MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2622
2623 /* The prolog is a no-op if there are no inputs. */
2624 sel->vs_needs_prolog = sel->info.stage == MESA_SHADER_VERTEX && sel->info.num_inputs &&
2625 !sel->info.base.vs.blit_sgprs_amd;
2626
2627 sel->prim_discard_cs_allowed =
2628 sel->info.stage == MESA_SHADER_VERTEX && !sel->info.uses_bindless_images &&
2629 !sel->info.uses_bindless_samplers && !sel->info.base.writes_memory &&
2630 !sel->info.writes_viewport_index &&
2631 !sel->info.base.vs.window_space_position && !sel->so.num_outputs;
2632
2633 switch (sel->info.stage) {
2634 case MESA_SHADER_GEOMETRY:
2635 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2636 sel->rast_prim = sel->info.base.gs.output_primitive;
2637 if (util_rast_prim_is_triangles(sel->rast_prim))
2638 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2639
2640 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2641 sel->max_gsvs_emit_size = sel->gsvs_vertex_size * sel->info.base.gs.vertices_out;
2642 sel->gs_input_verts_per_prim =
2643 u_vertices_per_prim(sel->info.base.gs.input_primitive);
2644
2645 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation so
2646 * we can't split workgroups. Disable ngg if any of the following conditions is true:
2647 * - num_invocations * gs.vertices_out > 256
2648 * - LDS usage is too high
2649 */
2650 sel->tess_turns_off_ngg = sscreen->info.chip_class >= GFX10 &&
2651 (sel->info.base.gs.invocations * sel->info.base.gs.vertices_out > 256 ||
2652 sel->info.base.gs.invocations * sel->info.base.gs.vertices_out *
2653 (sel->info.num_outputs * 4 + 1) > 6500 /* max dw per GS primitive */);
2654 break;
2655
2656 case MESA_SHADER_TESS_CTRL:
2657 /* Always reserve space for these. */
2658 sel->patch_outputs_written |=
2659 (1ull << si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_INNER)) |
2660 (1ull << si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_OUTER));
2661 /* fall through */
2662 case MESA_SHADER_VERTEX:
2663 case MESA_SHADER_TESS_EVAL:
2664 for (i = 0; i < sel->info.num_outputs; i++) {
2665 unsigned semantic = sel->info.output_semantic[i];
2666
2667 if (semantic == VARYING_SLOT_TESS_LEVEL_INNER ||
2668 semantic == VARYING_SLOT_TESS_LEVEL_OUTER ||
2669 (semantic >= VARYING_SLOT_PATCH0 && semantic < VARYING_SLOT_TESS_MAX)) {
2670 sel->patch_outputs_written |= 1ull << si_shader_io_get_unique_index_patch(semantic);
2671 } else if (semantic < VARYING_SLOT_MAX &&
2672 semantic != VARYING_SLOT_EDGE) {
2673 sel->outputs_written |= 1ull << si_shader_io_get_unique_index(semantic, false);
2674 sel->outputs_written_before_ps |= 1ull
2675 << si_shader_io_get_unique_index(semantic, true);
2676 }
2677 }
2678 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2679 sel->lshs_vertex_stride = sel->esgs_itemsize;
2680
2681 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2682 * will start on a different bank. (except for the maximum 32*16).
2683 */
2684 if (sel->lshs_vertex_stride < 32 * 16)
2685 sel->lshs_vertex_stride += 4;
2686
2687 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2688 * conflicts, i.e. each vertex will start at a different bank.
2689 */
2690 if (sctx->chip_class >= GFX9)
2691 sel->esgs_itemsize += 4;
2692
2693 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2694
2695 /* Only for TES: */
2696 if (sel->info.stage == MESA_SHADER_TESS_EVAL) {
2697 if (sel->info.base.tess.point_mode)
2698 sel->rast_prim = PIPE_PRIM_POINTS;
2699 else if (sel->info.base.tess.primitive_mode == GL_LINES)
2700 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2701 else
2702 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2703 } else {
2704 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2705 }
2706 break;
2707
2708 case MESA_SHADER_FRAGMENT:
2709 for (i = 0; i < sel->info.num_inputs; i++) {
2710 unsigned semantic = sel->info.input_semantic[i];
2711
2712 if (semantic < VARYING_SLOT_MAX &&
2713 semantic != VARYING_SLOT_PNTC) {
2714 sel->inputs_read |= 1ull << si_shader_io_get_unique_index(semantic, true);
2715 }
2716 }
2717
2718 for (i = 0; i < 8; i++)
2719 if (sel->info.colors_written & (1 << i))
2720 sel->colors_written_4bit |= 0xf << (4 * i);
2721
2722 for (i = 0; i < sel->info.num_inputs; i++) {
2723 if (sel->info.input_semantic[i] == VARYING_SLOT_COL0)
2724 sel->color_attr_index[0] = i;
2725 else if (sel->info.input_semantic[i] == VARYING_SLOT_COL1)
2726 sel->color_attr_index[1] = i;
2727 }
2728 break;
2729 default:;
2730 }
2731
2732 sel->ngg_culling_allowed =
2733 sscreen->info.chip_class >= GFX10 &&
2734 sscreen->info.has_dedicated_vram &&
2735 sscreen->use_ngg_culling &&
2736 (sel->info.stage == MESA_SHADER_VERTEX ||
2737 (sel->info.stage == MESA_SHADER_TESS_EVAL &&
2738 (sscreen->always_use_ngg_culling_all ||
2739 sscreen->always_use_ngg_culling_tess))) &&
2740 sel->info.writes_position &&
2741 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
2742 !sel->info.base.writes_memory && !sel->so.num_outputs &&
2743 (sel->info.stage != MESA_SHADER_VERTEX ||
2744 (!sel->info.base.vs.blit_sgprs_amd &&
2745 !sel->info.base.vs.window_space_position));
2746
2747 /* PA_CL_VS_OUT_CNTL */
2748 if (sctx->chip_class <= GFX9)
2749 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2750
2751 sel->clipdist_mask = sel->info.writes_clipvertex ? SIX_BITS :
2752 u_bit_consecutive(0, sel->info.base.clip_distance_array_size);
2753 sel->culldist_mask = u_bit_consecutive(0, sel->info.base.cull_distance_array_size) <<
2754 sel->info.base.clip_distance_array_size;
2755
2756 /* DB_SHADER_CONTROL */
2757 sel->db_shader_control = S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2758 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2759 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2760 S_02880C_KILL_ENABLE(sel->info.base.fs.uses_discard);
2761
2762 if (sel->info.stage == MESA_SHADER_FRAGMENT) {
2763 switch (sel->info.base.fs.depth_layout) {
2764 case FRAG_DEPTH_LAYOUT_GREATER:
2765 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2766 break;
2767 case FRAG_DEPTH_LAYOUT_LESS:
2768 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2769 break;
2770 default:;
2771 }
2772
2773 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2774 *
2775 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2776 * --|-----------|------------|------------|--------------------|-------------------|-------------
2777 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2778 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2779 * 2 | false | true | n/a | LateZ | 1 | 0
2780 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2781 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2782 *
2783 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2784 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2785 *
2786 * Don't use ReZ without profiling !!!
2787 *
2788 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2789 * shaders.
2790 */
2791 if (sel->info.base.fs.early_fragment_tests) {
2792 /* Cases 3, 4. */
2793 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2794 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2795 S_02880C_EXEC_ON_NOOP(sel->info.base.writes_memory);
2796 } else if (sel->info.base.writes_memory) {
2797 /* Case 2. */
2798 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) | S_02880C_EXEC_ON_HIER_FAIL(1);
2799 } else {
2800 /* Case 1. */
2801 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2802 }
2803
2804 if (sel->info.base.fs.post_depth_coverage)
2805 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2806 }
2807
2808 (void)simple_mtx_init(&sel->mutex, mtx_plain);
2809
2810 si_schedule_initial_compile(sctx, sel->info.stage, &sel->ready, &sel->compiler_ctx_state,
2811 sel, si_init_shader_selector_async);
2812 return sel;
2813 }
2814
2815 static void *si_create_shader(struct pipe_context *ctx, const struct pipe_shader_state *state)
2816 {
2817 struct si_context *sctx = (struct si_context *)ctx;
2818 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2819 bool cache_hit;
2820 struct si_shader_selector *sel = (struct si_shader_selector *)util_live_shader_cache_get(
2821 ctx, &sscreen->live_shader_cache, state, &cache_hit);
2822
2823 if (sel && cache_hit && sctx->debug.debug_message) {
2824 if (sel->main_shader_part)
2825 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part, &sctx->debug);
2826 if (sel->main_shader_part_ls)
2827 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ls, &sctx->debug);
2828 if (sel->main_shader_part_es)
2829 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_es, &sctx->debug);
2830 if (sel->main_shader_part_ngg)
2831 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg, &sctx->debug);
2832 if (sel->main_shader_part_ngg_es)
2833 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg_es, &sctx->debug);
2834 }
2835 return sel;
2836 }
2837
2838 static void si_update_streamout_state(struct si_context *sctx)
2839 {