projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi/gfx10: enable GS fast launch for triangles and strips with NGG culling
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR key for the shader cache.
45 */
46 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
47 unsigned char ir_sha1_cache_key[20])
48 {
49 struct blob blob = {};
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->nir_binary) {
54 ir_binary = sel->nir_binary;
55 ir_size = sel->nir_size;
56 } else {
57 assert(sel->nir);
58
59 blob_init(&blob);
60 nir_serialize(&blob, sel->nir, true);
61 ir_binary = blob.data;
62 ir_size = blob.size;
63 }
64
65 /* These settings affect the compilation, but they are not derived
66 * from the input shader IR.
67 */
68 unsigned shader_variant_flags = 0;
69
70 if (ngg)
71 shader_variant_flags |= 1 << 0;
72 if (sel->nir)
73 shader_variant_flags |= 1 << 1;
74 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
75 shader_variant_flags |= 1 << 2;
76 if (sel->force_correct_derivs_after_kill)
77 shader_variant_flags |= 1 << 3;
78
79 struct mesa_sha1 ctx;
80 _mesa_sha1_init(&ctx);
81 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
82 _mesa_sha1_update(&ctx, ir_binary, ir_size);
83 if (sel->type == PIPE_SHADER_VERTEX ||
84 sel->type == PIPE_SHADER_TESS_EVAL ||
85 sel->type == PIPE_SHADER_GEOMETRY)
86 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
87 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
88
89 if (ir_binary == blob.data)
90 blob_finish(&blob);
91 }
92
93 /** Copy "data" to "ptr" and return the next dword following copied data. */
94 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
95 {
96 /* data may be NULL if size == 0 */
97 if (size)
98 memcpy(ptr, data, size);
99 ptr += DIV_ROUND_UP(size, 4);
100 return ptr;
101 }
102
103 /** Read data from "ptr". Return the next dword following the data. */
104 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
105 {
106 memcpy(data, ptr, size);
107 ptr += DIV_ROUND_UP(size, 4);
108 return ptr;
109 }
110
111 /**
112 * Write the size as uint followed by the data. Return the next dword
113 * following the copied data.
114 */
115 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
116 {
117 *ptr++ = size;
118 return write_data(ptr, data, size);
119 }
120
121 /**
122 * Read the size as uint followed by the data. Return both via parameters.
123 * Return the next dword following the data.
124 */
125 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
126 {
127 *size = *ptr++;
128 assert(*data == NULL);
129 if (!*size)
130 return ptr;
131 *data = malloc(*size);
132 return read_data(ptr, *data, *size);
133 }
134
135 /**
136 * Return the shader binary in a buffer. The first 4 bytes contain its size
137 * as integer.
138 */
139 static void *si_get_shader_binary(struct si_shader *shader)
140 {
141 /* There is always a size of data followed by the data itself. */
142 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
143 strlen(shader->binary.llvm_ir_string) + 1 : 0;
144
145 /* Refuse to allocate overly large buffers and guard against integer
146 * overflow. */
147 if (shader->binary.elf_size > UINT_MAX / 4 ||
148 llvm_ir_size > UINT_MAX / 4)
149 return NULL;
150
151 unsigned size =
152 4 + /* total size */
153 4 + /* CRC32 of the data below */
154 align(sizeof(shader->config), 4) +
155 align(sizeof(shader->info), 4) +
156 4 + align(shader->binary.elf_size, 4) +
157 4 + align(llvm_ir_size, 4);
158 void *buffer = CALLOC(1, size);
159 uint32_t *ptr = (uint32_t*)buffer;
160
161 if (!buffer)
162 return NULL;
163
164 *ptr++ = size;
165 ptr++; /* CRC32 is calculated at the end. */
166
167 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
168 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
169 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
170 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
171 assert((char *)ptr - (char *)buffer == size);
172
173 /* Compute CRC32. */
174 ptr = (uint32_t*)buffer;
175 ptr++;
176 *ptr = util_hash_crc32(ptr + 1, size - 8);
177
178 return buffer;
179 }
180
181 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
182 {
183 uint32_t *ptr = (uint32_t*)binary;
184 uint32_t size = *ptr++;
185 uint32_t crc32 = *ptr++;
186 unsigned chunk_size;
187 unsigned elf_size;
188
189 if (util_hash_crc32(ptr, size - 8) != crc32) {
190 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
191 return false;
192 }
193
194 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
195 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
196 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
197 &elf_size);
198 shader->binary.elf_size = elf_size;
199 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
200
201 return true;
202 }
203
204 /**
205 * Insert a shader into the cache. It's assumed the shader is not in the cache.
206 * Use si_shader_cache_load_shader before calling this.
207 */
208 void si_shader_cache_insert_shader(struct si_screen *sscreen,
209 unsigned char ir_sha1_cache_key[20],
210 struct si_shader *shader,
211 bool insert_into_disk_cache)
212 {
213 void *hw_binary;
214 struct hash_entry *entry;
215 uint8_t key[CACHE_KEY_SIZE];
216
217 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
218 if (entry)
219 return; /* already added */
220
221 hw_binary = si_get_shader_binary(shader);
222 if (!hw_binary)
223 return;
224
225 if (_mesa_hash_table_insert(sscreen->shader_cache,
226 mem_dup(ir_sha1_cache_key, 20),
227 hw_binary) == NULL) {
228 FREE(hw_binary);
229 return;
230 }
231
232 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
233 disk_cache_compute_key(sscreen->disk_shader_cache,
234 ir_sha1_cache_key, 20, key);
235 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
236 *((uint32_t *) hw_binary), NULL);
237 }
238 }
239
240 bool si_shader_cache_load_shader(struct si_screen *sscreen,
241 unsigned char ir_sha1_cache_key[20],
242 struct si_shader *shader)
243 {
244 struct hash_entry *entry =
245 _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
246 if (!entry) {
247 if (sscreen->disk_shader_cache) {
248 unsigned char sha1[CACHE_KEY_SIZE];
249
250 disk_cache_compute_key(sscreen->disk_shader_cache,
251 ir_sha1_cache_key, 20, sha1);
252
253 size_t binary_size;
254 uint8_t *buffer =
255 disk_cache_get(sscreen->disk_shader_cache,
256 sha1, &binary_size);
257 if (!buffer)
258 return false;
259
260 if (binary_size < sizeof(uint32_t) ||
261 *((uint32_t*)buffer) != binary_size) {
262 /* Something has gone wrong discard the item
263 * from the cache and rebuild/link from
264 * source.
265 */
266 assert(!"Invalid radeonsi shader disk cache "
267 "item!");
268
269 disk_cache_remove(sscreen->disk_shader_cache,
270 sha1);
271 free(buffer);
272
273 return false;
274 }
275
276 if (!si_load_shader_binary(shader, buffer)) {
277 free(buffer);
278 return false;
279 }
280 free(buffer);
281
282 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
283 shader, false);
284 } else {
285 return false;
286 }
287 } else {
288 if (!si_load_shader_binary(shader, entry->data))
289 return false;
290 }
291 p_atomic_inc(&sscreen->num_shader_cache_hits);
292 return true;
293 }
294
295 static uint32_t si_shader_cache_key_hash(const void *key)
296 {
297 /* Take the first dword of SHA1. */
298 return *(uint32_t*)key;
299 }
300
301 static bool si_shader_cache_key_equals(const void *a, const void *b)
302 {
303 /* Compare SHA1s. */
304 return memcmp(a, b, 20) == 0;
305 }
306
307 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
308 {
309 FREE((void*)entry->key);
310 FREE(entry->data);
311 }
312
313 bool si_init_shader_cache(struct si_screen *sscreen)
314 {
315 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
316 sscreen->shader_cache =
317 _mesa_hash_table_create(NULL,
318 si_shader_cache_key_hash,
319 si_shader_cache_key_equals);
320
321 return sscreen->shader_cache != NULL;
322 }
323
324 void si_destroy_shader_cache(struct si_screen *sscreen)
325 {
326 if (sscreen->shader_cache)
327 _mesa_hash_table_destroy(sscreen->shader_cache,
328 si_destroy_shader_cache_entry);
329 simple_mtx_destroy(&sscreen->shader_cache_mutex);
330 }
331
332 /* SHADER STATES */
333
334 static void si_set_tesseval_regs(struct si_screen *sscreen,
335 const struct si_shader_selector *tes,
336 struct si_pm4_state *pm4)
337 {
338 const struct si_shader_info *info = &tes->info;
339 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
340 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
341 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
342 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
343 unsigned type, partitioning, topology, distribution_mode;
344
345 switch (tes_prim_mode) {
346 case PIPE_PRIM_LINES:
347 type = V_028B6C_TESS_ISOLINE;
348 break;
349 case PIPE_PRIM_TRIANGLES:
350 type = V_028B6C_TESS_TRIANGLE;
351 break;
352 case PIPE_PRIM_QUADS:
353 type = V_028B6C_TESS_QUAD;
354 break;
355 default:
356 assert(0);
357 return;
358 }
359
360 switch (tes_spacing) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
362 partitioning = V_028B6C_PART_FRAC_ODD;
363 break;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
365 partitioning = V_028B6C_PART_FRAC_EVEN;
366 break;
367 case PIPE_TESS_SPACING_EQUAL:
368 partitioning = V_028B6C_PART_INTEGER;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 if (tes_point_mode)
376 topology = V_028B6C_OUTPUT_POINT;
377 else if (tes_prim_mode == PIPE_PRIM_LINES)
378 topology = V_028B6C_OUTPUT_LINE;
379 else if (tes_vertex_order_cw)
380 /* for some reason, this must be the other way around */
381 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
382 else
383 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
384
385 if (sscreen->info.has_distributed_tess) {
386 if (sscreen->info.family == CHIP_FIJI ||
387 sscreen->info.family >= CHIP_POLARIS10)
388 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
389 else
390 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
391 } else
392 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
393
394 assert(pm4->shader);
395 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
396 S_028B6C_PARTITIONING(partitioning) |
397 S_028B6C_TOPOLOGY(topology) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
399 }
400
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
403 *
404 * Possible VGT configurations and which state should set the register:
405 *
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
408 * VS as VS | VS | 30
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 *
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 */
415 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
416 struct si_shader_selector *sel,
417 struct si_shader *shader,
418 struct si_pm4_state *pm4)
419 {
420 unsigned type = sel->type;
421
422 if (sscreen->info.family < CHIP_POLARIS10 ||
423 sscreen->info.chip_class >= GFX10)
424 return;
425
426 /* VS as VS, or VS as ES: */
427 if ((type == PIPE_SHADER_VERTEX &&
428 (!shader ||
429 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
430 /* TES as VS, or TES as ES: */
431 type == PIPE_SHADER_TESS_EVAL) {
432 unsigned vtx_reuse_depth = 30;
433
434 if (type == PIPE_SHADER_TESS_EVAL &&
435 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD)
437 vtx_reuse_depth = 14;
438
439 assert(pm4->shader);
440 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
441 }
442 }
443
444 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
445 {
446 if (shader->pm4)
447 si_pm4_clear_state(shader->pm4);
448 else
449 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
450
451 if (shader->pm4) {
452 shader->pm4->shader = shader;
453 return shader->pm4;
454 } else {
455 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
456 return NULL;
457 }
458 }
459
460 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
461 unsigned num_always_on_user_sgprs)
462 {
463 struct si_shader_selector *vs = shader->previous_stage_sel ?
464 shader->previous_stage_sel : shader->selector;
465 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
466
467 /* 1 SGPR is reserved for the vertex buffer pointer. */
468 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
469
470 if (num_vbos_in_user_sgprs)
471 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
472
473 /* Add the pointer to VBO descriptors. */
474 return num_always_on_user_sgprs + 1;
475 }
476
477 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
478 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
479 struct si_shader *shader, bool legacy_vs_prim_id)
480 {
481 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
482 (shader->previous_stage_sel &&
483 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
484
485 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
486 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
487 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
488 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
489 */
490 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
491
492 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
493 return 3;
494 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
495 return 2;
496 else if (is_ls || shader->info.uses_instanceid)
497 return 1;
498 else
499 return 0;
500 }
501
502 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
503 {
504 struct si_pm4_state *pm4;
505 uint64_t va;
506
507 assert(sscreen->info.chip_class <= GFX8);
508
509 pm4 = si_get_shader_pm4_state(shader);
510 if (!pm4)
511 return;
512
513 va = shader->bo->gpu_address;
514 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
515
516 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
518
519 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
520 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
521 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
522 S_00B528_DX10_CLAMP(1) |
523 S_00B528_FLOAT_MODE(shader->config.float_mode);
524 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
525 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
526 }
527
528 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
529 {
530 struct si_pm4_state *pm4;
531 uint64_t va;
532
533 pm4 = si_get_shader_pm4_state(shader);
534 if (!pm4)
535 return;
536
537 va = shader->bo->gpu_address;
538 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
539
540 if (sscreen->info.chip_class >= GFX9) {
541 if (sscreen->info.chip_class >= GFX10) {
542 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
543 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
544 } else {
545 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
546 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
547 }
548
549 unsigned num_user_sgprs =
550 si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
551
552 shader->config.rsrc2 =
553 S_00B42C_USER_SGPR(num_user_sgprs) |
554 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
555
556 if (sscreen->info.chip_class >= GFX10)
557 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
558 else
559 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
560 } else {
561 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
562 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
563
564 shader->config.rsrc2 =
565 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
566 S_00B42C_OC_LDS_EN(1) |
567 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
568 }
569
570 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
571 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
572 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
573 (sscreen->info.chip_class <= GFX9 ?
574 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
575 S_00B428_DX10_CLAMP(1) |
576 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
577 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
578 S_00B428_FLOAT_MODE(shader->config.float_mode) |
579 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
580 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
581
582 if (sscreen->info.chip_class <= GFX8) {
583 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
584 shader->config.rsrc2);
585 }
586 }
587
588 static void si_emit_shader_es(struct si_context *sctx)
589 {
590 struct si_shader *shader = sctx->queued.named.es->shader;
591 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
592
593 if (!shader)
594 return;
595
596 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
597 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
598 shader->selector->esgs_itemsize / 4);
599
600 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
601 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
602 SI_TRACKED_VGT_TF_PARAM,
603 shader->vgt_tf_param);
604
605 if (shader->vgt_vertex_reuse_block_cntl)
606 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
607 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
608 shader->vgt_vertex_reuse_block_cntl);
609
610 if (initial_cdw != sctx->gfx_cs->current.cdw)
611 sctx->context_roll = true;
612 }
613
614 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
615 {
616 struct si_pm4_state *pm4;
617 unsigned num_user_sgprs;
618 unsigned vgpr_comp_cnt;
619 uint64_t va;
620 unsigned oc_lds_en;
621
622 assert(sscreen->info.chip_class <= GFX8);
623
624 pm4 = si_get_shader_pm4_state(shader);
625 if (!pm4)
626 return;
627
628 pm4->atom.emit = si_emit_shader_es;
629 va = shader->bo->gpu_address;
630 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
631
632 if (shader->selector->type == PIPE_SHADER_VERTEX) {
633 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
634 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
635 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
636 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
637 num_user_sgprs = SI_TES_NUM_USER_SGPR;
638 } else
639 unreachable("invalid shader selector type");
640
641 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
642
643 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
644 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
645 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
646 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
647 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
648 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
649 S_00B328_DX10_CLAMP(1) |
650 S_00B328_FLOAT_MODE(shader->config.float_mode));
651 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
652 S_00B32C_USER_SGPR(num_user_sgprs) |
653 S_00B32C_OC_LDS_EN(oc_lds_en) |
654 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
655
656 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
657 si_set_tesseval_regs(sscreen, shader->selector, pm4);
658
659 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
660 }
661
662 void gfx9_get_gs_info(struct si_shader_selector *es,
663 struct si_shader_selector *gs,
664 struct gfx9_gs_info *out)
665 {
666 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
667 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
668 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
669 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
670
671 /* All these are in dwords: */
672 /* We can't allow using the whole LDS, because GS waves compete with
673 * other shader stages for LDS space. */
674 const unsigned max_lds_size = 8 * 1024;
675 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
676 unsigned esgs_lds_size;
677
678 /* All these are per subgroup: */
679 const unsigned max_out_prims = 32 * 1024;
680 const unsigned max_es_verts = 255;
681 const unsigned ideal_gs_prims = 64;
682 unsigned max_gs_prims, gs_prims;
683 unsigned min_es_verts, es_verts, worst_case_es_verts;
684
685 if (uses_adjacency || gs_num_invocations > 1)
686 max_gs_prims = 127 / gs_num_invocations;
687 else
688 max_gs_prims = 255;
689
690 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
691 * Make sure we don't go over the maximum value.
692 */
693 if (gs->gs_max_out_vertices > 0) {
694 max_gs_prims = MIN2(max_gs_prims,
695 max_out_prims /
696 (gs->gs_max_out_vertices * gs_num_invocations));
697 }
698 assert(max_gs_prims > 0);
699
700 /* If the primitive has adjacency, halve the number of vertices
701 * that will be reused in multiple primitives.
702 */
703 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
704
705 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
706 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
707
708 /* Compute ESGS LDS size based on the worst case number of ES vertices
709 * needed to create the target number of GS prims per subgroup.
710 */
711 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
712
713 /* If total LDS usage is too big, refactor partitions based on ratio
714 * of ESGS item sizes.
715 */
716 if (esgs_lds_size > max_lds_size) {
717 /* Our target GS Prims Per Subgroup was too large. Calculate
718 * the maximum number of GS Prims Per Subgroup that will fit
719 * into LDS, capped by the maximum that the hardware can support.
720 */
721 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
722 max_gs_prims);
723 assert(gs_prims > 0);
724 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
725 max_es_verts);
726
727 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
728 assert(esgs_lds_size <= max_lds_size);
729 }
730
731 /* Now calculate remaining ESGS information. */
732 if (esgs_lds_size)
733 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
734 else
735 es_verts = max_es_verts;
736
737 /* Vertices for adjacency primitives are not always reused, so restore
738 * it for ES_VERTS_PER_SUBGRP.
739 */
740 min_es_verts = gs->gs_input_verts_per_prim;
741
742 /* For normal primitives, the VGT only checks if they are past the ES
743 * verts per subgroup after allocating a full GS primitive and if they
744 * are, kick off a new subgroup. But if those additional ES verts are
745 * unique (e.g. not reused) we need to make sure there is enough LDS
746 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
747 */
748 es_verts -= min_es_verts - 1;
749
750 out->es_verts_per_subgroup = es_verts;
751 out->gs_prims_per_subgroup = gs_prims;
752 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
753 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
754 gs->gs_max_out_vertices;
755 out->esgs_ring_size = 4 * esgs_lds_size;
756
757 assert(out->max_prims_per_subgroup <= max_out_prims);
758 }
759
760 static void si_emit_shader_gs(struct si_context *sctx)
761 {
762 struct si_shader *shader = sctx->queued.named.gs->shader;
763 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
764
765 if (!shader)
766 return;
767
768 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
769 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
770 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
771 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
772 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
773 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
774 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
775
776 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
777 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
778 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
779 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
780
781 /* R_028B38_VGT_GS_MAX_VERT_OUT */
782 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
783 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
784 shader->ctx_reg.gs.vgt_gs_max_vert_out);
785
786 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
787 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
788 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
789 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
790 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
791 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
792 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
793 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
794
795 /* R_028B90_VGT_GS_INSTANCE_CNT */
796 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
797 SI_TRACKED_VGT_GS_INSTANCE_CNT,
798 shader->ctx_reg.gs.vgt_gs_instance_cnt);
799
800 if (sctx->chip_class >= GFX9) {
801 /* R_028A44_VGT_GS_ONCHIP_CNTL */
802 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
803 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
804 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
805 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
806 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
807 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
808 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
809 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
810 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
811 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
812 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
813
814 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
815 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
816 SI_TRACKED_VGT_TF_PARAM,
817 shader->vgt_tf_param);
818 if (shader->vgt_vertex_reuse_block_cntl)
819 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
820 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
821 shader->vgt_vertex_reuse_block_cntl);
822 }
823
824 if (initial_cdw != sctx->gfx_cs->current.cdw)
825 sctx->context_roll = true;
826 }
827
828 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
829 {
830 struct si_shader_selector *sel = shader->selector;
831 const ubyte *num_components = sel->info.num_stream_output_components;
832 unsigned gs_num_invocations = sel->gs_num_invocations;
833 struct si_pm4_state *pm4;
834 uint64_t va;
835 unsigned max_stream = sel->max_gs_stream;
836 unsigned offset;
837
838 pm4 = si_get_shader_pm4_state(shader);
839 if (!pm4)
840 return;
841
842 pm4->atom.emit = si_emit_shader_gs;
843
844 offset = num_components[0] * sel->gs_max_out_vertices;
845 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
846
847 if (max_stream >= 1)
848 offset += num_components[1] * sel->gs_max_out_vertices;
849 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
850
851 if (max_stream >= 2)
852 offset += num_components[2] * sel->gs_max_out_vertices;
853 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
854
855 if (max_stream >= 3)
856 offset += num_components[3] * sel->gs_max_out_vertices;
857 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
858
859 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
860 assert(offset < (1 << 15));
861
862 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
863
864 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
865 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
866 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
867 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
868
869 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
870 S_028B90_ENABLE(gs_num_invocations > 0);
871
872 va = shader->bo->gpu_address;
873 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
874
875 if (sscreen->info.chip_class >= GFX9) {
876 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
877 unsigned es_type = shader->key.part.gs.es->type;
878 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
879
880 if (es_type == PIPE_SHADER_VERTEX) {
881 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
882 } else if (es_type == PIPE_SHADER_TESS_EVAL)
883 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
884 else
885 unreachable("invalid shader selector type");
886
887 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
888 * VGPR[0:4] are always loaded.
889 */
890 if (sel->info.uses_invocationid)
891 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
892 else if (sel->info.uses_primid)
893 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
894 else if (input_prim >= PIPE_PRIM_TRIANGLES)
895 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
896 else
897 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
898
899 unsigned num_user_sgprs;
900 if (es_type == PIPE_SHADER_VERTEX)
901 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
902 else
903 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
904
905 if (sscreen->info.chip_class >= GFX10) {
906 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
907 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
908 } else {
909 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
910 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
911 }
912
913 uint32_t rsrc1 =
914 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
915 S_00B228_DX10_CLAMP(1) |
916 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
917 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
918 S_00B228_FLOAT_MODE(shader->config.float_mode) |
919 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
920 uint32_t rsrc2 =
921 S_00B22C_USER_SGPR(num_user_sgprs) |
922 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
923 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
924 S_00B22C_LDS_SIZE(shader->config.lds_size) |
925 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
926
927 if (sscreen->info.chip_class >= GFX10) {
928 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
929 } else {
930 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
931 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
932 }
933
934 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
935 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
936
937 if (sscreen->info.chip_class >= GFX10) {
938 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
939 S_00B204_CU_EN(0xffff) |
940 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
941 }
942
943 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
944 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
945 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
946 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
947 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
948 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
949 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
950 shader->key.part.gs.es->esgs_itemsize / 4;
951
952 if (es_type == PIPE_SHADER_TESS_EVAL)
953 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
954
955 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
956 NULL, pm4);
957 } else {
958 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
959 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
960
961 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
962 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
963 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
964 S_00B228_DX10_CLAMP(1) |
965 S_00B228_FLOAT_MODE(shader->config.float_mode));
966 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
967 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
968 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
969 }
970 }
971
972 static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
973 {
974 enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
975
976 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
977 sctx->tracked_regs.reg_value[reg] != value) {
978 struct radeon_cmdbuf *cs = sctx->gfx_cs;
979
980 if (sctx->family == CHIP_NAVI10 ||
981 sctx->family == CHIP_NAVI12 ||
982 sctx->family == CHIP_NAVI14) {
983 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
984 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
985 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
986 }
987
988 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
989
990 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
991 sctx->tracked_regs.reg_value[reg] = value;
992 }
993 }
994
995 /* Common tail code for NGG primitive shaders. */
996 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
997 struct si_shader *shader,
998 unsigned initial_cdw)
999 {
1000 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
1001 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
1002 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
1003 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
1004 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
1005 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
1006 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1007 SI_TRACKED_VGT_PRIMITIVEID_EN,
1008 shader->ctx_reg.ngg.vgt_primitiveid_en);
1009 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1010 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1011 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
1012 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
1013 SI_TRACKED_VGT_GS_INSTANCE_CNT,
1014 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
1015 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
1016 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
1017 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
1018 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1019 SI_TRACKED_SPI_VS_OUT_CONFIG,
1020 shader->ctx_reg.ngg.spi_vs_out_config);
1021 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
1022 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
1023 shader->ctx_reg.ngg.spi_shader_idx_format,
1024 shader->ctx_reg.ngg.spi_shader_pos_format);
1025 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1026 SI_TRACKED_PA_CL_VTE_CNTL,
1027 shader->ctx_reg.ngg.pa_cl_vte_cntl);
1028 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1029 SI_TRACKED_PA_CL_NGG_CNTL,
1030 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1031
1032 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1033 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1034 shader->pa_cl_vs_out_cntl,
1035 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1036
1037 if (initial_cdw != sctx->gfx_cs->current.cdw)
1038 sctx->context_roll = true;
1039
1040 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1041 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
1042 }
1043
1044 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1045 {
1046 struct si_shader *shader = sctx->queued.named.gs->shader;
1047 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1048
1049 if (!shader)
1050 return;
1051
1052 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1053 }
1054
1055 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1056 {
1057 struct si_shader *shader = sctx->queued.named.gs->shader;
1058 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1059
1060 if (!shader)
1061 return;
1062
1063 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1064 SI_TRACKED_VGT_TF_PARAM,
1065 shader->vgt_tf_param);
1066
1067 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1068 }
1069
1070 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1071 {
1072 struct si_shader *shader = sctx->queued.named.gs->shader;
1073 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1074
1075 if (!shader)
1076 return;
1077
1078 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1079 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1080 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1081
1082 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1083 }
1084
1085 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1086 {
1087 struct si_shader *shader = sctx->queued.named.gs->shader;
1088 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1089
1090 if (!shader)
1091 return;
1092
1093 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1094 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1095 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1096 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1097 SI_TRACKED_VGT_TF_PARAM,
1098 shader->vgt_tf_param);
1099
1100 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1101 }
1102
1103 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1104 {
1105 if (gs->type == PIPE_SHADER_GEOMETRY)
1106 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1107
1108 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1109 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1110 return PIPE_PRIM_POINTS;
1111 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1112 return PIPE_PRIM_LINES;
1113 return PIPE_PRIM_TRIANGLES;
1114 }
1115
1116 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1117 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1118 }
1119
1120 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1121 {
1122 bool misc_vec_ena =
1123 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1124 sel->info.writes_layer || sel->info.writes_viewport_index;
1125 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1126 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1127 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1128 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1129 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1130 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1131 }
1132
1133 /**
1134 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1135 * in NGG mode.
1136 */
1137 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1138 {
1139 const struct si_shader_selector *gs_sel = shader->selector;
1140 const struct si_shader_info *gs_info = &gs_sel->info;
1141 enum pipe_shader_type gs_type = shader->selector->type;
1142 const struct si_shader_selector *es_sel =
1143 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1144 const struct si_shader_info *es_info = &es_sel->info;
1145 enum pipe_shader_type es_type = es_sel->type;
1146 unsigned num_user_sgprs;
1147 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1148 uint64_t va;
1149 unsigned window_space =
1150 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1151 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1152 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1153 unsigned input_prim = si_get_input_prim(gs_sel);
1154 bool break_wave_at_eoi = false;
1155 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1156 if (!pm4)
1157 return;
1158
1159 if (es_type == PIPE_SHADER_TESS_EVAL) {
1160 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1161 : gfx10_emit_shader_ngg_tess_nogs;
1162 } else {
1163 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1164 : gfx10_emit_shader_ngg_notess_nogs;
1165 }
1166
1167 va = shader->bo->gpu_address;
1168 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1169
1170 if (es_type == PIPE_SHADER_VERTEX) {
1171 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1172
1173 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1174 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1175 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1176 } else {
1177 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1178 }
1179 } else {
1180 assert(es_type == PIPE_SHADER_TESS_EVAL);
1181 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1182 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1183
1184 if (es_enable_prim_id || gs_info->uses_primid)
1185 break_wave_at_eoi = true;
1186 }
1187
1188 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1189 * VGPR[0:4] are always loaded.
1190 *
1191 * Vertex shaders always need to load VGPR3, because they need to
1192 * pass edge flags for decomposed primitives (such as quads) to the PA
1193 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1194 */
1195 if (gs_info->uses_invocationid ||
1196 (gs_type == PIPE_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1197 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1198 else if ((gs_type == PIPE_SHADER_GEOMETRY && gs_info->uses_primid) ||
1199 (gs_type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1200 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1201 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1202 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1203 else
1204 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1205
1206 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1207 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1208 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1209 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1210 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1211 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1212 S_00B228_DX10_CLAMP(1) |
1213 S_00B228_MEM_ORDERED(1) |
1214 S_00B228_WGP_MODE(1) |
1215 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1216 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1217 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1218 S_00B22C_USER_SGPR(num_user_sgprs) |
1219 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1220 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1221 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1222 S_00B22C_LDS_SIZE(shader->config.lds_size));
1223
1224 /* Determine LATE_ALLOC_GS. */
1225 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
1226 unsigned late_alloc_wave64; /* The limit is per SH. */
1227
1228 /* For Wave32, the hw will launch twice the number of late
1229 * alloc waves, so 1 == 2x wave32.
1230 *
1231 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1232 */
1233 if (sscreen->info.family == CHIP_NAVI14)
1234 late_alloc_wave64 = 0;
1235 else if (num_cu_per_sh <= 6)
1236 late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
1237 else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
1238 late_alloc_wave64 = (num_cu_per_sh - 2) * 6;
1239 else
1240 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
1241
1242 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1243 S_00B204_CU_EN(0xffff) |
1244 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64));
1245
1246 nparams = MAX2(shader->info.nr_param_exports, 1);
1247 shader->ctx_reg.ngg.spi_vs_out_config =
1248 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1249 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1250
1251 shader->ctx_reg.ngg.spi_shader_idx_format =
1252 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1253 shader->ctx_reg.ngg.spi_shader_pos_format =
1254 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1255 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1256 V_02870C_SPI_SHADER_4COMP :
1257 V_02870C_SPI_SHADER_NONE) |
1258 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1259 V_02870C_SPI_SHADER_4COMP :
1260 V_02870C_SPI_SHADER_NONE) |
1261 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1262 V_02870C_SPI_SHADER_4COMP :
1263 V_02870C_SPI_SHADER_NONE);
1264
1265 shader->ctx_reg.ngg.vgt_primitiveid_en =
1266 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1267 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1268 gs_sel->info.writes_primid);
1269
1270 if (gs_type == PIPE_SHADER_GEOMETRY) {
1271 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1272 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1273 } else {
1274 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1275 }
1276
1277 if (es_type == PIPE_SHADER_TESS_EVAL)
1278 si_set_tesseval_regs(sscreen, es_sel, pm4);
1279
1280 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1281 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1282 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1283 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1284 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1285 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1286 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1287 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1288 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1289 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1290 S_028B90_CNT(gs_num_invocations) |
1291 S_028B90_ENABLE(gs_num_invocations > 1) |
1292 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1293 shader->ngg.max_vert_out_per_gs_instance);
1294
1295 /* Always output hw-generated edge flags and pass them via the prim
1296 * export to prevent drawing lines on internal edges of decomposed
1297 * primitives (such as quads) with polygon mode = lines. Only VS needs
1298 * this.
1299 */
1300 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1301 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1302 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1303
1304 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1305 float oversub_pc_factor = 0.25;
1306
1307 if (shader->key.opt.ngg_culling) {
1308 /* Be more aggressive with NGG culling. */
1309 if (shader->info.nr_param_exports > 4)
1310 oversub_pc_factor = 1;
1311 else if (shader->info.nr_param_exports > 2)
1312 oversub_pc_factor = 0.75;
1313 else
1314 oversub_pc_factor = 0.5;
1315 }
1316
1317 unsigned oversub_pc_lines = sscreen->info.pc_lines * oversub_pc_factor;
1318 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1319 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1320
1321 if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
1322 shader->ge_cntl =
1323 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1324 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims * 3);
1325 } else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP) {
1326 shader->ge_cntl =
1327 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1328 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims + 2);
1329 } else {
1330 shader->ge_cntl =
1331 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1332 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1333 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1334
1335 /* Bug workaround for a possible hang with non-tessellation cases.
1336 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1337 *
1338 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1339 */
1340 if ((sscreen->info.family == CHIP_NAVI10 ||
1341 sscreen->info.family == CHIP_NAVI12 ||
1342 sscreen->info.family == CHIP_NAVI14) &&
1343 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1344 shader->ngg.hw_max_esverts != 256) {
1345 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1346
1347 if (shader->ngg.hw_max_esverts > 5) {
1348 shader->ge_cntl |=
1349 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1350 }
1351 }
1352 }
1353
1354 if (window_space) {
1355 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1356 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1357 } else {
1358 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1359 S_028818_VTX_W0_FMT(1) |
1360 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1361 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1362 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1363 }
1364 }
1365
1366 static void si_emit_shader_vs(struct si_context *sctx)
1367 {
1368 struct si_shader *shader = sctx->queued.named.vs->shader;
1369 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1370
1371 if (!shader)
1372 return;
1373
1374 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1375 SI_TRACKED_VGT_GS_MODE,
1376 shader->ctx_reg.vs.vgt_gs_mode);
1377 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1378 SI_TRACKED_VGT_PRIMITIVEID_EN,
1379 shader->ctx_reg.vs.vgt_primitiveid_en);
1380
1381 if (sctx->chip_class <= GFX8) {
1382 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1383 SI_TRACKED_VGT_REUSE_OFF,
1384 shader->ctx_reg.vs.vgt_reuse_off);
1385 }
1386
1387 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1388 SI_TRACKED_SPI_VS_OUT_CONFIG,
1389 shader->ctx_reg.vs.spi_vs_out_config);
1390
1391 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1392 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1393 shader->ctx_reg.vs.spi_shader_pos_format);
1394
1395 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1396 SI_TRACKED_PA_CL_VTE_CNTL,
1397 shader->ctx_reg.vs.pa_cl_vte_cntl);
1398
1399 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1400 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1401 SI_TRACKED_VGT_TF_PARAM,
1402 shader->vgt_tf_param);
1403
1404 if (shader->vgt_vertex_reuse_block_cntl)
1405 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1406 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1407 shader->vgt_vertex_reuse_block_cntl);
1408
1409 /* Required programming for tessellation. (legacy pipeline only) */
1410 if (sctx->chip_class == GFX10 &&
1411 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1412 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1413 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1414 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1415 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1416 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1417 }
1418
1419 if (sctx->chip_class >= GFX10) {
1420 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1421 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1422 shader->pa_cl_vs_out_cntl,
1423 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1424 }
1425
1426 if (initial_cdw != sctx->gfx_cs->current.cdw)
1427 sctx->context_roll = true;
1428
1429 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1430 if (sctx->chip_class >= GFX10)
1431 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
1432 }
1433
1434 /**
1435 * Compute the state for \p shader, which will run as a vertex shader on the
1436 * hardware.
1437 *
1438 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1439 * is the copy shader.
1440 */
1441 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1442 struct si_shader_selector *gs)
1443 {
1444 const struct si_shader_info *info = &shader->selector->info;
1445 struct si_pm4_state *pm4;
1446 unsigned num_user_sgprs, vgpr_comp_cnt;
1447 uint64_t va;
1448 unsigned nparams, oc_lds_en;
1449 unsigned window_space =
1450 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1451 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1452
1453 pm4 = si_get_shader_pm4_state(shader);
1454 if (!pm4)
1455 return;
1456
1457 pm4->atom.emit = si_emit_shader_vs;
1458
1459 /* We always write VGT_GS_MODE in the VS state, because every switch
1460 * between different shader pipelines involving a different GS or no
1461 * GS at all involves a switch of the VS (different GS use different
1462 * copy shaders). On the other hand, when the API switches from a GS to
1463 * no GS and then back to the same GS used originally, the GS state is
1464 * not sent again.
1465 */
1466 if (!gs) {
1467 unsigned mode = V_028A40_GS_OFF;
1468
1469 /* PrimID needs GS scenario A. */
1470 if (enable_prim_id)
1471 mode = V_028A40_GS_SCENARIO_A;
1472
1473 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1474 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1475 } else {
1476 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1477 sscreen->info.chip_class);
1478 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1479 }
1480
1481 if (sscreen->info.chip_class <= GFX8) {
1482 /* Reuse needs to be set off if we write oViewport. */
1483 shader->ctx_reg.vs.vgt_reuse_off =
1484 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1485 }
1486
1487 va = shader->bo->gpu_address;
1488 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1489
1490 if (gs) {
1491 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1492 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1493 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1494 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1495
1496 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1497 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1498 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1499 } else {
1500 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1501 }
1502 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1503 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1504 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1505 } else
1506 unreachable("invalid shader selector type");
1507
1508 /* VS is required to export at least one param. */
1509 nparams = MAX2(shader->info.nr_param_exports, 1);
1510 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1511
1512 if (sscreen->info.chip_class >= GFX10) {
1513 shader->ctx_reg.vs.spi_vs_out_config |=
1514 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1515 }
1516
1517 shader->ctx_reg.vs.spi_shader_pos_format =
1518 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1519 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1520 V_02870C_SPI_SHADER_4COMP :
1521 V_02870C_SPI_SHADER_NONE) |
1522 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1523 V_02870C_SPI_SHADER_4COMP :
1524 V_02870C_SPI_SHADER_NONE) |
1525 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1526 V_02870C_SPI_SHADER_4COMP :
1527 V_02870C_SPI_SHADER_NONE);
1528 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1529 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1530 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1531
1532 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1533
1534 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1535 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1536
1537 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1538 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1539 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1540 S_00B128_DX10_CLAMP(1) |
1541 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1542 S_00B128_FLOAT_MODE(shader->config.float_mode);
1543 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1544 S_00B12C_OC_LDS_EN(oc_lds_en) |
1545 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1546
1547 if (sscreen->info.chip_class >= GFX10)
1548 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1549 else if (sscreen->info.chip_class == GFX9)
1550 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1551
1552 if (sscreen->info.chip_class <= GFX9)
1553 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1554
1555 if (!sscreen->use_ngg_streamout) {
1556 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1557 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1558 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1559 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1560 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1561 }
1562
1563 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1564 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1565
1566 if (window_space)
1567 shader->ctx_reg.vs.pa_cl_vte_cntl =
1568 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1569 else
1570 shader->ctx_reg.vs.pa_cl_vte_cntl =
1571 S_028818_VTX_W0_FMT(1) |
1572 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1573 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1574 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1575
1576 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1577 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1578
1579 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1580 }
1581
1582 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1583 {
1584 struct si_shader_info *info = &ps->selector->info;
1585 unsigned num_colors = !!(info->colors_read & 0x0f) +
1586 !!(info->colors_read & 0xf0);
1587 unsigned num_interp = ps->selector->info.num_inputs +
1588 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1589
1590 assert(num_interp <= 32);
1591 return MIN2(num_interp, 32);
1592 }
1593
1594 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1595 {
1596 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1597 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1598
1599 /* If the i-th target format is set, all previous target formats must
1600 * be non-zero to avoid hangs.
1601 */
1602 for (i = 0; i < num_targets; i++)
1603 if (!(value & (0xf << (i * 4))))
1604 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1605
1606 return value;
1607 }
1608
1609 static void si_emit_shader_ps(struct si_context *sctx)
1610 {
1611 struct si_shader *shader = sctx->queued.named.ps->shader;
1612 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1613
1614 if (!shader)
1615 return;
1616
1617 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1618 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1619 SI_TRACKED_SPI_PS_INPUT_ENA,
1620 shader->ctx_reg.ps.spi_ps_input_ena,
1621 shader->ctx_reg.ps.spi_ps_input_addr);
1622
1623 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1624 SI_TRACKED_SPI_BARYC_CNTL,
1625 shader->ctx_reg.ps.spi_baryc_cntl);
1626 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1627 SI_TRACKED_SPI_PS_IN_CONTROL,
1628 shader->ctx_reg.ps.spi_ps_in_control);
1629
1630 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1631 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1632 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1633 shader->ctx_reg.ps.spi_shader_z_format,
1634 shader->ctx_reg.ps.spi_shader_col_format);
1635
1636 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1637 SI_TRACKED_CB_SHADER_MASK,
1638 shader->ctx_reg.ps.cb_shader_mask);
1639
1640 if (initial_cdw != sctx->gfx_cs->current.cdw)
1641 sctx->context_roll = true;
1642 }
1643
1644 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1645 {
1646 struct si_shader_info *info = &shader->selector->info;
1647 struct si_pm4_state *pm4;
1648 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1649 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1650 uint64_t va;
1651 unsigned input_ena = shader->config.spi_ps_input_ena;
1652
1653 /* we need to enable at least one of them, otherwise we hang the GPU */
1654 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1655 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1656 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1657 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1658 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1659 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1660 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1661 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1662 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1663 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1664 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1665 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1666 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1667 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1668
1669 /* Validate interpolation optimization flags (read as implications). */
1670 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1671 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1672 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1673 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1674 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1675 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1676 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1677 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1678 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1679 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1680 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1681 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1682 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1683 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1684 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1685 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1686 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1687 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1688
1689 /* Validate cases when the optimizations are off (read as implications). */
1690 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1691 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1692 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1693 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1694 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1695 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1696
1697 pm4 = si_get_shader_pm4_state(shader);
1698 if (!pm4)
1699 return;
1700
1701 pm4->atom.emit = si_emit_shader_ps;
1702
1703 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1704 * Possible vaules:
1705 * 0 -> Position = pixel center
1706 * 1 -> Position = pixel centroid
1707 * 2 -> Position = at sample position
1708 *
1709 * From GLSL 4.5 specification, section 7.1:
1710 * "The variable gl_FragCoord is available as an input variable from
1711 * within fragment shaders and it holds the window relative coordinates
1712 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1713 * value can be for any location within the pixel, or one of the
1714 * fragment samples. The use of centroid does not further restrict
1715 * this value to be inside the current primitive."
1716 *
1717 * Meaning that centroid has no effect and we can return anything within
1718 * the pixel. Thus, return the value at sample position, because that's
1719 * the most accurate one shaders can get.
1720 */
1721 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1722
1723 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1724 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1725 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1726
1727 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1728 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1729
1730 /* Ensure that some export memory is always allocated, for two reasons:
1731 *
1732 * 1) Correctness: The hardware ignores the EXEC mask if no export
1733 * memory is allocated, so KILL and alpha test do not work correctly
1734 * without this.
1735 * 2) Performance: Every shader needs at least a NULL export, even when
1736 * it writes no color/depth output. The NULL export instruction
1737 * stalls without this setting.
1738 *
1739 * Don't add this to CB_SHADER_MASK.
1740 *
1741 * GFX10 supports pixel shaders without exports by setting both
1742 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1743 * instructions if any are present.
1744 */
1745 if ((sscreen->info.chip_class <= GFX9 ||
1746 info->uses_kill ||
1747 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1748 !spi_shader_col_format &&
1749 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1750 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1751
1752 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1753 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1754
1755 /* Set interpolation controls. */
1756 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1757 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1758
1759 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1760 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1761 shader->ctx_reg.ps.spi_shader_z_format =
1762 ac_get_spi_shader_z_format(info->writes_z,
1763 info->writes_stencil,
1764 info->writes_samplemask);
1765 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1766 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1767
1768 va = shader->bo->gpu_address;
1769 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1770 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1771 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1772
1773 uint32_t rsrc1 =
1774 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1775 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1776 S_00B028_DX10_CLAMP(1) |
1777 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1778 S_00B028_FLOAT_MODE(shader->config.float_mode);
1779
1780 if (sscreen->info.chip_class < GFX10) {
1781 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1782 }
1783
1784 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1785 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1786 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1787 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1788 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1789 }
1790
1791 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1792 struct si_shader *shader)
1793 {
1794 switch (shader->selector->type) {
1795 case PIPE_SHADER_VERTEX:
1796 if (shader->key.as_ls)
1797 si_shader_ls(sscreen, shader);
1798 else if (shader->key.as_es)
1799 si_shader_es(sscreen, shader);
1800 else if (shader->key.as_ngg)
1801 gfx10_shader_ngg(sscreen, shader);
1802 else
1803 si_shader_vs(sscreen, shader, NULL);
1804 break;
1805 case PIPE_SHADER_TESS_CTRL:
1806 si_shader_hs(sscreen, shader);
1807 break;
1808 case PIPE_SHADER_TESS_EVAL:
1809 if (shader->key.as_es)
1810 si_shader_es(sscreen, shader);
1811 else if (shader->key.as_ngg)
1812 gfx10_shader_ngg(sscreen, shader);
1813 else
1814 si_shader_vs(sscreen, shader, NULL);
1815 break;
1816 case PIPE_SHADER_GEOMETRY:
1817 if (shader->key.as_ngg)
1818 gfx10_shader_ngg(sscreen, shader);
1819 else
1820 si_shader_gs(sscreen, shader);
1821 break;
1822 case PIPE_SHADER_FRAGMENT:
1823 si_shader_ps(sscreen, shader);
1824 break;
1825 default:
1826 assert(0);
1827 }
1828 }
1829
1830 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1831 {
1832 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1833 return sctx->queued.named.dsa->alpha_func;
1834 }
1835
1836 void si_shader_selector_key_vs(struct si_context *sctx,
1837 struct si_shader_selector *vs,
1838 struct si_shader_key *key,
1839 struct si_vs_prolog_bits *prolog_key)
1840 {
1841 if (!sctx->vertex_elements ||
1842 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1843 return;
1844
1845 struct si_vertex_elements *elts = sctx->vertex_elements;
1846
1847 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1848 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1849 prolog_key->unpack_instance_id_from_vertex_id =
1850 sctx->prim_discard_cs_instancing;
1851
1852 /* Prefer a monolithic shader to allow scheduling divisions around
1853 * VBO loads. */
1854 if (prolog_key->instance_divisor_is_fetched)
1855 key->opt.prefer_mono = 1;
1856
1857 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1858 unsigned count_mask = (1 << count) - 1;
1859 unsigned fix = elts->fix_fetch_always & count_mask;
1860 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1861
1862 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1863 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1864 while (mask) {
1865 unsigned i = u_bit_scan(&mask);
1866 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1867 unsigned vbidx = elts->vertex_buffer_index[i];
1868 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1869 unsigned align_mask = (1 << log_hw_load_size) - 1;
1870 if (vb->buffer_offset & align_mask ||
1871 vb->stride & align_mask) {
1872 fix |= 1 << i;
1873 opencode |= 1 << i;
1874 }
1875 }
1876 }
1877
1878 while (fix) {
1879 unsigned i = u_bit_scan(&fix);
1880 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1881 }
1882 key->mono.vs_fetch_opencode = opencode;
1883 }
1884
1885 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1886 struct si_shader_selector *vs,
1887 struct si_shader_key *key)
1888 {
1889 struct si_shader_selector *ps = sctx->ps_shader.cso;
1890
1891 key->opt.clip_disable =
1892 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1893 (vs->info.clipdist_writemask ||
1894 vs->info.writes_clipvertex) &&
1895 !vs->info.culldist_writemask;
1896
1897 /* Find out if PS is disabled. */
1898 bool ps_disabled = true;
1899 if (ps) {
1900 bool ps_modifies_zs = ps->info.uses_kill ||
1901 ps->info.writes_z ||
1902 ps->info.writes_stencil ||
1903 ps->info.writes_samplemask ||
1904 sctx->queued.named.blend->alpha_to_coverage ||
1905 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1906 unsigned ps_colormask = si_get_total_colormask(sctx);
1907
1908 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1909 (!ps_colormask &&
1910 !ps_modifies_zs &&
1911 !ps->info.writes_memory);
1912 }
1913
1914 /* Find out which VS outputs aren't used by the PS. */
1915 uint64_t outputs_written = vs->outputs_written_before_ps;
1916 uint64_t inputs_read = 0;
1917
1918 /* Ignore outputs that are not passed from VS to PS. */
1919 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1920 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1921 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1922
1923 if (!ps_disabled) {
1924 inputs_read = ps->inputs_read;
1925 }
1926
1927 uint64_t linked = outputs_written & inputs_read;
1928
1929 key->opt.kill_outputs = ~linked & outputs_written;
1930 key->opt.ngg_culling = sctx->ngg_culling;
1931 }
1932
1933 /* Compute the key for the hw shader variant */
1934 static inline void si_shader_selector_key(struct pipe_context *ctx,
1935 struct si_shader_selector *sel,
1936 union si_vgt_stages_key stages_key,
1937 struct si_shader_key *key)
1938 {
1939 struct si_context *sctx = (struct si_context *)ctx;
1940
1941 memset(key, 0, sizeof(*key));
1942
1943 switch (sel->type) {
1944 case PIPE_SHADER_VERTEX:
1945 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1946
1947 if (sctx->tes_shader.cso)
1948 key->as_ls = 1;
1949 else if (sctx->gs_shader.cso) {
1950 key->as_es = 1;
1951 key->as_ngg = stages_key.u.ngg;
1952 } else {
1953 key->as_ngg = stages_key.u.ngg;
1954 si_shader_selector_key_hw_vs(sctx, sel, key);
1955
1956 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1957 key->mono.u.vs_export_prim_id = 1;
1958 }
1959 break;
1960 case PIPE_SHADER_TESS_CTRL:
1961 if (sctx->chip_class >= GFX9) {
1962 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1963 key, &key->part.tcs.ls_prolog);
1964 key->part.tcs.ls = sctx->vs_shader.cso;
1965
1966 /* When the LS VGPR fix is needed, monolithic shaders
1967 * can:
1968 * - avoid initializing EXEC in both the LS prolog
1969 * and the LS main part when !vs_needs_prolog
1970 * - remove the fixup for unused input VGPRs
1971 */
1972 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1973
1974 /* The LS output / HS input layout can be communicated
1975 * directly instead of via user SGPRs for merged LS-HS.
1976 * The LS VGPR fix prefers this too.
1977 */
1978 key->opt.prefer_mono = 1;
1979 }
1980
1981 key->part.tcs.epilog.prim_mode =
1982 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1983 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1984 sel->info.tessfactors_are_def_in_all_invocs;
1985 key->part.tcs.epilog.tes_reads_tess_factors =
1986 sctx->tes_shader.cso->info.reads_tess_factors;
1987
1988 if (sel == sctx->fixed_func_tcs_shader.cso)
1989 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1990 break;
1991 case PIPE_SHADER_TESS_EVAL:
1992 key->as_ngg = stages_key.u.ngg;
1993
1994 if (sctx->gs_shader.cso)
1995 key->as_es = 1;
1996 else {
1997 si_shader_selector_key_hw_vs(sctx, sel, key);
1998
1999 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
2000 key->mono.u.vs_export_prim_id = 1;
2001 }
2002 break;
2003 case PIPE_SHADER_GEOMETRY:
2004 if (sctx->chip_class >= GFX9) {
2005 if (sctx->tes_shader.cso) {
2006 key->part.gs.es = sctx->tes_shader.cso;
2007 } else {
2008 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
2009 key, &key->part.gs.vs_prolog);
2010 key->part.gs.es = sctx->vs_shader.cso;
2011 key->part.gs.prolog.gfx9_prev_is_vs = 1;
2012 }
2013
2014 key->as_ngg = stages_key.u.ngg;
2015
2016 /* Merged ES-GS can have unbalanced wave usage.
2017 *
2018 * ES threads are per-vertex, while GS threads are
2019 * per-primitive. So without any amplification, there
2020 * are fewer GS threads than ES threads, which can result
2021 * in empty (no-op) GS waves. With too much amplification,
2022 * there are more GS threads than ES threads, which
2023 * can result in empty (no-op) ES waves.
2024 *
2025 * Non-monolithic shaders are implemented by setting EXEC
2026 * at the beginning of shader parts, and don't jump to
2027 * the end if EXEC is 0.
2028 *
2029 * Monolithic shaders use conditional blocks, so they can
2030 * jump and skip empty waves of ES or GS. So set this to
2031 * always use optimized variants, which are monolithic.
2032 */
2033 key->opt.prefer_mono = 1;
2034 }
2035 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
2036 break;
2037 case PIPE_SHADER_FRAGMENT: {
2038 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2039 struct si_state_blend *blend = sctx->queued.named.blend;
2040
2041 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2042 sel->info.colors_written == 0x1)
2043 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
2044
2045 /* Select the shader color format based on whether
2046 * blending or alpha are needed.
2047 */
2048 key->part.ps.epilog.spi_shader_col_format =
2049 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
2050 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
2051 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
2052 sctx->framebuffer.spi_shader_col_format_blend) |
2053 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
2054 sctx->framebuffer.spi_shader_col_format_alpha) |
2055 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
2056 sctx->framebuffer.spi_shader_col_format);
2057 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
2058
2059 /* The output for dual source blending should have
2060 * the same format as the first output.
2061 */
2062 if (blend->dual_src_blend) {
2063 key->part.ps.epilog.spi_shader_col_format |=
2064 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
2065 }
2066
2067 /* If alpha-to-coverage is enabled, we have to export alpha
2068 * even if there is no color buffer.
2069 */
2070 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
2071 blend->alpha_to_coverage)
2072 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
2073
2074 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
2075 * to the range supported by the type if a channel has less
2076 * than 16 bits and the export format is 16_ABGR.
2077 */
2078 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
2079 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
2080 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
2081 }
2082
2083 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
2084 if (!key->part.ps.epilog.last_cbuf) {
2085 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
2086 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
2087 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
2088 }
2089
2090 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
2091 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
2092
2093 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
2094 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
2095
2096 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
2097 rs->multisample_enable;
2098
2099 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
2100 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
2101 (is_line && rs->line_smooth)) &&
2102 sctx->framebuffer.nr_samples <= 1;
2103 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2104
2105 if (sctx->ps_iter_samples > 1 &&
2106 sel->info.reads_samplemask) {
2107 key->part.ps.prolog.samplemask_log_ps_iter =
2108 util_logbase2(sctx->ps_iter_samples);
2109 }
2110
2111 if (rs->force_persample_interp &&
2112 rs->multisample_enable &&
2113 sctx->framebuffer.nr_samples > 1 &&
2114 sctx->ps_iter_samples > 1) {
2115 key->part.ps.prolog.force_persp_sample_interp =
2116 sel->info.uses_persp_center ||
2117 sel->info.uses_persp_centroid;
2118
2119 key->part.ps.prolog.force_linear_sample_interp =
2120 sel->info.uses_linear_center ||
2121 sel->info.uses_linear_centroid;
2122 } else if (rs->multisample_enable &&
2123 sctx->framebuffer.nr_samples > 1) {
2124 key->part.ps.prolog.bc_optimize_for_persp =
2125 sel->info.uses_persp_center &&
2126 sel->info.uses_persp_centroid;
2127 key->part.ps.prolog.bc_optimize_for_linear =
2128 sel->info.uses_linear_center &&
2129 sel->info.uses_linear_centroid;
2130 } else {
2131 /* Make sure SPI doesn't compute more than 1 pair
2132 * of (i,j), which is the optimization here. */
2133 key->part.ps.prolog.force_persp_center_interp =
2134 sel->info.uses_persp_center +
2135 sel->info.uses_persp_centroid +
2136 sel->info.uses_persp_sample > 1;
2137
2138 key->part.ps.prolog.force_linear_center_interp =
2139 sel->info.uses_linear_center +
2140 sel->info.uses_linear_centroid +
2141 sel->info.uses_linear_sample > 1;
2142
2143 if (sel->info.uses_persp_opcode_interp_sample ||
2144 sel->info.uses_linear_opcode_interp_sample)
2145 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2146 }
2147
2148 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2149
2150 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2151 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2152 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2153 struct pipe_resource *tex = cb0->texture;
2154
2155 /* 1D textures are allocated and used as 2D on GFX9. */
2156 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2157 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2158 (tex->target == PIPE_TEXTURE_1D ||
2159 tex->target == PIPE_TEXTURE_1D_ARRAY);
2160 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2161 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2162 tex->target == PIPE_TEXTURE_CUBE ||
2163 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2164 tex->target == PIPE_TEXTURE_3D;
2165 }
2166 break;
2167 }
2168 default:
2169 assert(0);
2170 }
2171
2172 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2173 memset(&key->opt, 0, sizeof(key->opt));
2174 }
2175
2176 static void si_build_shader_variant(struct si_shader *shader,
2177 int thread_index,
2178 bool low_priority)
2179 {
2180 struct si_shader_selector *sel = shader->selector;
2181 struct si_screen *sscreen = sel->screen;
2182 struct ac_llvm_compiler *compiler;
2183 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2184
2185 if (thread_index >= 0) {
2186 if (low_priority) {
2187 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2188 compiler = &sscreen->compiler_lowp[thread_index];
2189 } else {
2190 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2191 compiler = &sscreen->compiler[thread_index];
2192 }
2193 if (!debug->async)
2194 debug = NULL;
2195 } else {
2196 assert(!low_priority);
2197 compiler = shader->compiler_ctx_state.compiler;
2198 }
2199
2200 if (!compiler->passes)
2201 si_init_compiler(sscreen, compiler);
2202
2203 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2204 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2205 sel->type);
2206 shader->compilation_failed = true;
2207 return;
2208 }
2209
2210 if (shader->compiler_ctx_state.is_debug_context) {
2211 FILE *f = open_memstream(&shader->shader_log,
2212 &shader->shader_log_size);
2213 if (f) {
2214 si_shader_dump(sscreen, shader, NULL, f, false);
2215 fclose(f);
2216 }
2217 }
2218
2219 si_shader_init_pm4_state(sscreen, shader);
2220 }
2221
2222 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2223 {
2224 struct si_shader *shader = (struct si_shader *)job;
2225
2226 assert(thread_index >= 0);
2227
2228 si_build_shader_variant(shader, thread_index, true);
2229 }
2230
2231 static const struct si_shader_key zeroed;
2232
2233 static bool si_check_missing_main_part(struct si_screen *sscreen,
2234 struct si_shader_selector *sel,
2235 struct si_compiler_ctx_state *compiler_state,
2236 struct si_shader_key *key)
2237 {
2238 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2239
2240 if (!*mainp) {
2241 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2242
2243 if (!main_part)
2244 return false;
2245
2246 /* We can leave the fence as permanently signaled because the
2247 * main part becomes visible globally only after it has been
2248 * compiled. */
2249 util_queue_fence_init(&main_part->ready);
2250
2251 main_part->selector = sel;
2252 main_part->key.as_es = key->as_es;
2253 main_part->key.as_ls = key->as_ls;
2254 main_part->key.as_ngg = key->as_ngg;
2255 main_part->is_monolithic = false;
2256
2257 if (si_compile_shader(sscreen, compiler_state->compiler,
2258 main_part, &compiler_state->debug) != 0) {
2259 FREE(main_part);
2260 return false;
2261 }
2262 *mainp = main_part;
2263 }
2264 return true;
2265 }
2266
2267 /**
2268 * Select a shader variant according to the shader key.
2269 *
2270 * \param optimized_or_none If the key describes an optimized shader variant and
2271 * the compilation isn't finished, don't select any
2272 * shader and return an error.
2273 */
2274 int si_shader_select_with_key(struct si_screen *sscreen,
2275 struct si_shader_ctx_state *state,
2276 struct si_compiler_ctx_state *compiler_state,
2277 struct si_shader_key *key,
2278 int thread_index,
2279 bool optimized_or_none)
2280 {
2281 struct si_shader_selector *sel = state->cso;
2282 struct si_shader_selector *previous_stage_sel = NULL;
2283 struct si_shader *current = state->current;
2284 struct si_shader *iter, *shader = NULL;
2285
2286 again:
2287 /* Check if we don't need to change anything.
2288 * This path is also used for most shaders that don't need multiple
2289 * variants, it will cost just a computation of the key and this
2290 * test. */
2291 if (likely(current &&
2292 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2293 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2294 if (current->is_optimized) {
2295 if (optimized_or_none)
2296 return -1;
2297
2298 memset(&key->opt, 0, sizeof(key->opt));
2299 goto current_not_ready;
2300 }
2301
2302 util_queue_fence_wait(&current->ready);
2303 }
2304
2305 return current->compilation_failed ? -1 : 0;
2306 }
2307 current_not_ready:
2308
2309 /* This must be done before the mutex is locked, because async GS
2310 * compilation calls this function too, and therefore must enter
2311 * the mutex first.
2312 *
2313 * Only wait if we are in a draw call. Don't wait if we are
2314 * in a compiler thread.
2315 */
2316 if (thread_index < 0)
2317 util_queue_fence_wait(&sel->ready);
2318
2319 simple_mtx_lock(&sel->mutex);
2320
2321 /* Find the shader variant. */
2322 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2323 /* Don't check the "current" shader. We checked it above. */
2324 if (current != iter &&
2325 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2326 simple_mtx_unlock(&sel->mutex);
2327
2328 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2329 /* If it's an optimized shader and its compilation has
2330 * been started but isn't done, use the unoptimized
2331 * shader so as not to cause a stall due to compilation.
2332 */
2333 if (iter->is_optimized) {
2334 if (optimized_or_none)
2335 return -1;
2336 memset(&key->opt, 0, sizeof(key->opt));
2337 goto again;
2338 }
2339
2340 util_queue_fence_wait(&iter->ready);
2341 }
2342
2343 if (iter->compilation_failed) {
2344 return -1; /* skip the draw call */
2345 }
2346
2347 state->current = iter;
2348 return 0;
2349 }
2350 }
2351
2352 /* Build a new shader. */
2353 shader = CALLOC_STRUCT(si_shader);
2354 if (!shader) {
2355 simple_mtx_unlock(&sel->mutex);
2356 return -ENOMEM;
2357 }
2358
2359 util_queue_fence_init(&shader->ready);
2360
2361 shader->selector = sel;
2362 shader->key = *key;
2363 shader->compiler_ctx_state = *compiler_state;
2364
2365 /* If this is a merged shader, get the first shader's selector. */
2366 if (sscreen->info.chip_class >= GFX9) {
2367 if (sel->type == PIPE_SHADER_TESS_CTRL)
2368 previous_stage_sel = key->part.tcs.ls;
2369 else if (sel->type == PIPE_SHADER_GEOMETRY)
2370 previous_stage_sel = key->part.gs.es;
2371
2372 /* We need to wait for the previous shader. */
2373 if (previous_stage_sel && thread_index < 0)
2374 util_queue_fence_wait(&previous_stage_sel->ready);
2375 }
2376
2377 bool is_pure_monolithic =
2378 sscreen->use_monolithic_shaders ||
2379 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2380
2381 /* Compile the main shader part if it doesn't exist. This can happen
2382 * if the initial guess was wrong.
2383 *
2384 * The prim discard CS doesn't need the main shader part.
2385 */
2386 if (!is_pure_monolithic &&
2387 !key->opt.vs_as_prim_discard_cs) {
2388 bool ok = true;
2389
2390 /* Make sure the main shader part is present. This is needed
2391 * for shaders that can be compiled as VS, LS, or ES, and only
2392 * one of them is compiled at creation.
2393 *
2394 * It is also needed for GS, which can be compiled as non-NGG
2395 * and NGG.
2396 *
2397 * For merged shaders, check that the starting shader's main
2398 * part is present.
2399 */
2400 if (previous_stage_sel) {
2401 struct si_shader_key shader1_key = zeroed;
2402
2403 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2404 shader1_key.as_ls = 1;
2405 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2406 shader1_key.as_es = 1;
2407 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2408 } else {
2409 assert(0);
2410 }
2411
2412 simple_mtx_lock(&previous_stage_sel->mutex);
2413 ok = si_check_missing_main_part(sscreen,
2414 previous_stage_sel,
2415 compiler_state, &shader1_key);
2416 simple_mtx_unlock(&previous_stage_sel->mutex);
2417 }
2418
2419 if (ok) {
2420 ok = si_check_missing_main_part(sscreen, sel,
2421 compiler_state, key);
2422 }
2423
2424 if (!ok) {
2425 FREE(shader);
2426 simple_mtx_unlock(&sel->mutex);
2427 return -ENOMEM; /* skip the draw call */
2428 }
2429 }
2430
2431 /* Keep the reference to the 1st shader of merged shaders, so that
2432 * Gallium can't destroy it before we destroy the 2nd shader.
2433 *
2434 * Set sctx = NULL, because it's unused if we're not releasing
2435 * the shader, and we don't have any sctx here.
2436 */
2437 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2438 previous_stage_sel);
2439
2440 /* Monolithic-only shaders don't make a distinction between optimized
2441 * and unoptimized. */
2442 shader->is_monolithic =
2443 is_pure_monolithic ||
2444 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2445
2446 /* The prim discard CS is always optimized. */
2447 shader->is_optimized =
2448 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2449 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2450
2451 /* If it's an optimized shader, compile it asynchronously. */
2452 if (shader->is_optimized && thread_index < 0) {
2453 /* Compile it asynchronously. */
2454 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2455 shader, &shader->ready,
2456 si_build_shader_variant_low_priority, NULL,
2457 0);
2458
2459 /* Add only after the ready fence was reset, to guard against a
2460 * race with si_bind_XX_shader. */
2461 if (!sel->last_variant) {
2462 sel->first_variant = shader;
2463 sel->last_variant = shader;
2464 } else {
2465 sel->last_variant->next_variant = shader;
2466 sel->last_variant = shader;
2467 }
2468
2469 /* Use the default (unoptimized) shader for now. */
2470 memset(&key->opt, 0, sizeof(key->opt));
2471 simple_mtx_unlock(&sel->mutex);
2472
2473 if (sscreen->options.sync_compile)
2474 util_queue_fence_wait(&shader->ready);
2475
2476 if (optimized_or_none)
2477 return -1;
2478 goto again;
2479 }
2480
2481 /* Reset the fence before adding to the variant list. */
2482 util_queue_fence_reset(&shader->ready);
2483
2484 if (!sel->last_variant) {
2485 sel->first_variant = shader;
2486 sel->last_variant = shader;
2487 } else {
2488 sel->last_variant->next_variant = shader;
2489 sel->last_variant = shader;
2490 }
2491
2492 simple_mtx_unlock(&sel->mutex);
2493
2494 assert(!shader->is_optimized);
2495 si_build_shader_variant(shader, thread_index, false);
2496
2497 util_queue_fence_signal(&shader->ready);
2498
2499 if (!shader->compilation_failed)
2500 state->current = shader;
2501
2502 return shader->compilation_failed ? -1 : 0;
2503 }
2504
2505 static int si_shader_select(struct pipe_context *ctx,
2506 struct si_shader_ctx_state *state,
2507 union si_vgt_stages_key stages_key,
2508 struct si_compiler_ctx_state *compiler_state)
2509 {
2510 struct si_context *sctx = (struct si_context *)ctx;
2511 struct si_shader_key key;
2512
2513 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2514 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2515 &key, -1, false);
2516 }
2517
2518 static void si_parse_next_shader_property(const struct si_shader_info *info,
2519 bool streamout,
2520 struct si_shader_key *key)
2521 {
2522 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2523
2524 switch (info->processor) {
2525 case PIPE_SHADER_VERTEX:
2526 switch (next_shader) {
2527 case PIPE_SHADER_GEOMETRY:
2528 key->as_es = 1;
2529 break;
2530 case PIPE_SHADER_TESS_CTRL:
2531 case PIPE_SHADER_TESS_EVAL:
2532 key->as_ls = 1;
2533 break;
2534 default:
2535 /* If POSITION isn't written, it can only be a HW VS
2536 * if streamout is used. If streamout isn't used,
2537 * assume that it's a HW LS. (the next shader is TCS)
2538 * This heuristic is needed for separate shader objects.
2539 */
2540 if (!info->writes_position && !streamout)
2541 key->as_ls = 1;
2542 }
2543 break;
2544
2545 case PIPE_SHADER_TESS_EVAL:
2546 if (next_shader == PIPE_SHADER_GEOMETRY ||
2547 !info->writes_position)
2548 key->as_es = 1;
2549 break;
2550 }
2551 }
2552
2553 /**
2554 * Compile the main shader part or the monolithic shader as part of
2555 * si_shader_selector initialization. Since it can be done asynchronously,
2556 * there is no way to report compile failures to applications.
2557 */
2558 static void si_init_shader_selector_async(void *job, int thread_index)
2559 {
2560 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2561 struct si_screen *sscreen = sel->screen;
2562 struct ac_llvm_compiler *compiler;
2563 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2564
2565 assert(!debug->debug_message || debug->async);
2566 assert(thread_index >= 0);
2567 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2568 compiler = &sscreen->compiler[thread_index];
2569
2570 if (!compiler->passes)
2571 si_init_compiler(sscreen, compiler);
2572
2573 /* Serialize NIR to save memory. Monolithic shader variants
2574 * have to deserialize NIR before compilation.
2575 */
2576 if (sel->nir) {
2577 struct blob blob;
2578 size_t size;
2579
2580 blob_init(&blob);
2581 /* true = remove optional debugging data to increase
2582 * the likehood of getting more shader cache hits.
2583 * It also drops variable names, so we'll save more memory.
2584 */
2585 nir_serialize(&blob, sel->nir, true);
2586 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2587 sel->nir_size = size;
2588 }
2589
2590 /* Compile the main shader part for use with a prolog and/or epilog.
2591 * If this fails, the driver will try to compile a monolithic shader
2592 * on demand.
2593 */
2594 if (!sscreen->use_monolithic_shaders) {
2595 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2596 unsigned char ir_sha1_cache_key[20];
2597
2598 if (!shader) {
2599 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2600 return;
2601 }
2602
2603 /* We can leave the fence signaled because use of the default
2604 * main part is guarded by the selector's ready fence. */
2605 util_queue_fence_init(&shader->ready);
2606
2607 shader->selector = sel;
2608 shader->is_monolithic = false;
2609 si_parse_next_shader_property(&sel->info,
2610 sel->so.num_outputs != 0,
2611 &shader->key);
2612
2613 if (sscreen->use_ngg &&
2614 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2615 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2616 sel->type == PIPE_SHADER_TESS_EVAL ||
2617 sel->type == PIPE_SHADER_GEOMETRY))
2618 shader->key.as_ngg = 1;
2619
2620 if (sel->nir) {
2621 si_get_ir_cache_key(sel, shader->key.as_ngg,
2622 shader->key.as_es, ir_sha1_cache_key);
2623 }
2624
2625 /* Try to load the shader from the shader cache. */
2626 simple_mtx_lock(&sscreen->shader_cache_mutex);
2627
2628 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2629 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2630 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2631 } else {
2632 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2633
2634 /* Compile the shader if it hasn't been loaded from the cache. */
2635 if (si_compile_shader(sscreen, compiler, shader,
2636 debug) != 0) {
2637 FREE(shader);
2638 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2639 return;
2640 }
2641
2642 simple_mtx_lock(&sscreen->shader_cache_mutex);
2643 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
2644 shader, true);
2645 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2646 }
2647
2648 *si_get_main_shader_part(sel, &shader->key) = shader;
2649
2650 /* Unset "outputs_written" flags for outputs converted to
2651 * DEFAULT_VAL, so that later inter-shader optimizations don't
2652 * try to eliminate outputs that don't exist in the final
2653 * shader.
2654 *
2655 * This is only done if non-monolithic shaders are enabled.
2656 */
2657 if ((sel->type == PIPE_SHADER_VERTEX ||
2658 sel->type == PIPE_SHADER_TESS_EVAL) &&
2659 !shader->key.as_ls &&
2660 !shader->key.as_es) {
2661 unsigned i;
2662
2663 for (i = 0; i < sel->info.num_outputs; i++) {
2664 unsigned offset = shader->info.vs_output_param_offset[i];
2665
2666 if (offset <= AC_EXP_PARAM_OFFSET_31)
2667 continue;
2668
2669 unsigned name = sel->info.output_semantic_name[i];
2670 unsigned index = sel->info.output_semantic_index[i];
2671 unsigned id;
2672
2673 switch (name) {
2674 case TGSI_SEMANTIC_GENERIC:
2675 /* don't process indices the function can't handle */
2676 if (index >= SI_MAX_IO_GENERIC)
2677 break;
2678 /* fall through */
2679 default:
2680 id = si_shader_io_get_unique_index(name, index, true);
2681 sel->outputs_written_before_ps &= ~(1ull << id);
2682 break;
2683 case TGSI_SEMANTIC_POSITION: /* ignore these */
2684 case TGSI_SEMANTIC_PSIZE:
2685 case TGSI_SEMANTIC_CLIPVERTEX:
2686 case TGSI_SEMANTIC_EDGEFLAG:
2687 break;
2688 }
2689 }
2690 }
2691 }
2692
2693 /* The GS copy shader is always pre-compiled. */
2694 if (sel->type == PIPE_SHADER_GEOMETRY &&
2695 (!sscreen->use_ngg ||
2696 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2697 sel->tess_turns_off_ngg)) {
2698 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2699 if (!sel->gs_copy_shader) {
2700 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2701 return;
2702 }
2703
2704 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2705 }
2706
2707 /* Free NIR. We only keep serialized NIR after this point. */
2708 if (sel->nir) {
2709 ralloc_free(sel->nir);
2710 sel->nir = NULL;
2711 }
2712 }
2713
2714 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2715 struct util_queue_fence *ready_fence,
2716 struct si_compiler_ctx_state *compiler_ctx_state,
2717 void *job, util_queue_execute_func execute)
2718 {
2719 util_queue_fence_init(ready_fence);
2720
2721 struct util_async_debug_callback async_debug;
2722 bool debug =
2723 (sctx->debug.debug_message && !sctx->debug.async) ||
2724 sctx->is_debug ||
2725 si_can_dump_shader(sctx->screen, processor);
2726
2727 if (debug) {
2728 u_async_debug_init(&async_debug);
2729 compiler_ctx_state->debug = async_debug.base;
2730 }
2731
2732 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2733 ready_fence, execute, NULL, 0);
2734
2735 if (debug) {
2736 util_queue_fence_wait(ready_fence);
2737 u_async_debug_drain(&async_debug, &sctx->debug);
2738 u_async_debug_cleanup(&async_debug);
2739 }
2740
2741 if (sctx->screen->options.sync_compile)
2742 util_queue_fence_wait(ready_fence);
2743 }
2744
2745 /* Return descriptor slot usage masks from the given shader info. */
2746 void si_get_active_slot_masks(const struct si_shader_info *info,
2747 uint32_t *const_and_shader_buffers,
2748 uint64_t *samplers_and_images)
2749 {
2750 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2751
2752 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2753 num_constbufs = util_last_bit(info->const_buffers_declared);
2754 /* two 8-byte images share one 16-byte slot */
2755 num_images = align(util_last_bit(info->images_declared), 2);
2756 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2757 num_samplers = util_last_bit(info->samplers_declared);
2758
2759 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2760 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2761 *const_and_shader_buffers =
2762 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2763
2764 /* The layout is:
2765 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2766 * - image[last] ... image[0] go to [31-last .. 31]
2767 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2768 *
2769 * FMASKs for images are placed separately, because MSAA images are rare,
2770 * and so we can benefit from a better cache hit rate if we keep image
2771 * descriptors together.
2772 */
2773 if (num_msaa_images)
2774 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2775
2776 start = si_get_image_slot(num_images - 1) / 2;
2777 *samplers_and_images =
2778 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2779 }
2780
2781 static void *si_create_shader_selector(struct pipe_context *ctx,
2782 const struct pipe_shader_state *state)
2783 {
2784 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2785 struct si_context *sctx = (struct si_context*)ctx;
2786 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2787 int i;
2788
2789 if (!sel)
2790 return NULL;
2791
2792 pipe_reference_init(&sel->reference, 1);
2793 sel->screen = sscreen;
2794 sel->compiler_ctx_state.debug = sctx->debug;
2795 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2796
2797 sel->so = state->stream_output;
2798
2799 if (state->type == PIPE_SHADER_IR_TGSI) {
2800 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2801 } else {
2802 assert(state->type == PIPE_SHADER_IR_NIR);
2803 sel->nir = state->ir.nir;
2804 }
2805
2806 si_nir_scan_shader(sel->nir, &sel->info);
2807 si_nir_adjust_driver_locations(sel->nir);
2808
2809 sel->type = sel->info.processor;
2810 p_atomic_inc(&sscreen->num_shaders_created);
2811 si_get_active_slot_masks(&sel->info,
2812 &sel->active_const_and_shader_buffers,
2813 &sel->active_samplers_and_images);
2814
2815 /* Record which streamout buffers are enabled. */
2816 for (i = 0; i < sel->so.num_outputs; i++) {
2817 sel->enabled_streamout_buffer_mask |=
2818 (1 << sel->so.output[i].output_buffer) <<
2819 (sel->so.output[i].stream * 4);
2820 }
2821
2822 sel->num_vs_inputs = sel->type == PIPE_SHADER_VERTEX &&
2823 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] ?
2824 sel->info.num_inputs : 0;
2825 sel->num_vbos_in_user_sgprs =
2826 MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2827
2828 /* The prolog is a no-op if there are no inputs. */
2829 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2830 sel->info.num_inputs &&
2831 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2832
2833 sel->force_correct_derivs_after_kill =
2834 sel->type == PIPE_SHADER_FRAGMENT &&
2835 sel->info.uses_derivatives &&
2836 sel->info.uses_kill &&
2837 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2838
2839 sel->prim_discard_cs_allowed =
2840 sel->type == PIPE_SHADER_VERTEX &&
2841 !sel->info.uses_bindless_images &&
2842 !sel->info.uses_bindless_samplers &&
2843 !sel->info.writes_memory &&
2844 !sel->info.writes_viewport_index &&
2845 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2846 !sel->so.num_outputs;
2847
2848 switch (sel->type) {
2849 case PIPE_SHADER_GEOMETRY:
2850 sel->gs_output_prim =
2851 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2852
2853 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2854 sel->rast_prim = sel->gs_output_prim;
2855 if (util_rast_prim_is_triangles(sel->rast_prim))
2856 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2857
2858 sel->gs_max_out_vertices =
2859 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2860 sel->gs_num_invocations =
2861 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2862 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2863 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2864 sel->gs_max_out_vertices;
2865
2866 sel->max_gs_stream = 0;
2867 for (i = 0; i < sel->so.num_outputs; i++)
2868 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2869 sel->so.output[i].stream);
2870
2871 sel->gs_input_verts_per_prim =
2872 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2873
2874 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2875 sel->tess_turns_off_ngg =
2876 sscreen->info.chip_class == GFX10 &&
2877 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2878 break;
2879
2880 case PIPE_SHADER_TESS_CTRL:
2881 /* Always reserve space for these. */
2882 sel->patch_outputs_written |=
2883 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2884 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2885 /* fall through */
2886 case PIPE_SHADER_VERTEX:
2887 case PIPE_SHADER_TESS_EVAL:
2888 for (i = 0; i < sel->info.num_outputs; i++) {
2889 unsigned name = sel->info.output_semantic_name[i];
2890 unsigned index = sel->info.output_semantic_index[i];
2891
2892 switch (name) {
2893 case TGSI_SEMANTIC_TESSINNER:
2894 case TGSI_SEMANTIC_TESSOUTER:
2895 case TGSI_SEMANTIC_PATCH:
2896 sel->patch_outputs_written |=
2897 1ull << si_shader_io_get_unique_index_patch(name, index);
2898 break;
2899
2900 case TGSI_SEMANTIC_GENERIC:
2901 /* don't process indices the function can't handle */
2902 if (index >= SI_MAX_IO_GENERIC)
2903 break;
2904 /* fall through */
2905 default:
2906 sel->outputs_written |=
2907 1ull << si_shader_io_get_unique_index(name, index, false);
2908 sel->outputs_written_before_ps |=
2909 1ull << si_shader_io_get_unique_index(name, index, true);
2910 break;
2911 case TGSI_SEMANTIC_EDGEFLAG:
2912 break;
2913 }
2914 }
2915 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2916 sel->lshs_vertex_stride = sel->esgs_itemsize;
2917
2918 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2919 * will start on a different bank. (except for the maximum 32*16).
2920 */
2921 if (sel->lshs_vertex_stride < 32*16)
2922 sel->lshs_vertex_stride += 4;
2923
2924 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2925 * conflicts, i.e. each vertex will start at a different bank.
2926 */
2927 if (sctx->chip_class >= GFX9)
2928 sel->esgs_itemsize += 4;
2929
2930 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2931
2932 /* Only for TES: */
2933 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2934 sel->rast_prim = PIPE_PRIM_POINTS;
2935 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2936 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2937 else
2938 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2939 break;
2940
2941 case PIPE_SHADER_FRAGMENT:
2942 for (i = 0; i < sel->info.num_inputs; i++) {
2943 unsigned name = sel->info.input_semantic_name[i];
2944 unsigned index = sel->info.input_semantic_index[i];
2945
2946 switch (name) {
2947 case TGSI_SEMANTIC_GENERIC:
2948 /* don't process indices the function can't handle */
2949 if (index >= SI_MAX_IO_GENERIC)
2950 break;
2951 /* fall through */
2952 default:
2953 sel->inputs_read |=
2954 1ull << si_shader_io_get_unique_index(name, index, true);
2955 break;
2956 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2957 break;
2958 }
2959 }
2960
2961 for (i = 0; i < 8; i++)
2962 if (sel->info.colors_written & (1 << i))
2963 sel->colors_written_4bit |= 0xf << (4 * i);
2964
2965 for (i = 0; i < sel->info.num_inputs; i++) {
2966 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2967 int index = sel->info.input_semantic_index[i];
2968 sel->color_attr_index[index] = i;
2969 }
2970 }
2971 break;
2972 default:;
2973 }
2974
2975 sel->ngg_culling_allowed =
2976 sscreen->info.chip_class == GFX10 &&
2977 sscreen->info.has_dedicated_vram &&
2978 sscreen->use_ngg_culling &&
2979 /* Disallow TES by default, because TessMark results are mixed. */
2980 (sel->type == PIPE_SHADER_VERTEX ||
2981 (sscreen->always_use_ngg_culling && sel->type == PIPE_SHADER_TESS_EVAL)) &&
2982 sel->info.writes_position &&
2983 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
2984 !sel->info.writes_memory &&
2985 !sel->so.num_outputs &&
2986 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] &&
2987 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2988
2989 /* PA_CL_VS_OUT_CNTL */
2990 if (sctx->chip_class <= GFX9)
2991 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2992
2993 sel->clipdist_mask = sel->info.writes_clipvertex ?
2994 SIX_BITS : sel->info.clipdist_writemask;
2995 sel->culldist_mask = sel->info.culldist_writemask <<
2996 sel->info.num_written_clipdistance;
2997
2998 /* DB_SHADER_CONTROL */
2999 sel->db_shader_control =
3000 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
3001 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
3002 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
3003 S_02880C_KILL_ENABLE(sel->info.uses_kill);
3004
3005 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
3006 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3007 sel->db_shader_control |=
3008 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3009 break;
3010 case TGSI_FS_DEPTH_LAYOUT_LESS:
3011 sel->db_shader_control |=
3012 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3013 break;
3014 }
3015
3016 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
3017 *
3018 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
3019 * --|-----------|------------|------------|--------------------|-------------------|-------------
3020 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
3021 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
3022 * 2 | false | true | n/a | LateZ | 1 | 0
3023 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
3024 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
3025 *
3026 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
3027 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
3028 *
3029 * Don't use ReZ without profiling !!!
3030 *
3031 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
3032 * shaders.
3033 */
3034 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3035 /* Cases 3, 4. */
3036 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3037 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
3038 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
3039 } else if (sel->info.writes_memory) {
3040 /* Case 2. */
3041 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
3042 S_02880C_EXEC_ON_HIER_FAIL(1);
3043 } else {
3044 /* Case 1. */
3045 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3046 }
3047
3048 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
3049 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
3050
3051 (void) simple_mtx_init(&sel->mutex, mtx_plain);
3052
3053 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
3054 &sel->compiler_ctx_state, sel,
3055 si_init_shader_selector_async);
3056 return sel;
3057 }
3058
3059 static void si_update_streamout_state(struct si_context *sctx)
3060 {
3061 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
3062
3063 if (!shader_with_so)
3064 return;
3065
3066 sctx->streamout.enabled_stream_buffers_mask =
3067 shader_with_so->enabled_streamout_buffer_mask;
3068 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
3069 }
3070
3071 static void si_update_clip_regs(struct si_context *sctx,
3072 struct si_shader_selector *old_hw_vs,
3073 struct si_shader *old_hw_vs_variant,
3074 struct si_shader_selector *next_hw_vs,
3075 struct si_shader *next_hw_vs_variant)
3076 {
3077 if (next_hw_vs &&
3078 (!old_hw_vs ||
3079 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
3080 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
3081 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
3082 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
3083 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
3084 !old_hw_vs_variant ||
3085 !next_hw_vs_variant ||
3086 old_hw_vs_variant->key.opt.clip_disable !=
3087 next_hw_vs_variant->key.opt.clip_disable))
3088 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3089 }
3090
3091 static void si_update_common_shader_state(struct si_context *sctx)
3092 {
3093 sctx->uses_bindless_samplers =
3094 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
3095 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
3096 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
3097 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
3098 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
3099 sctx->uses_bindless_images =
3100 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
3101 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
3102 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
3103 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3104 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3105 sctx->do_update_shaders = true;
3106 }
3107
3108 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3109 {
3110 struct si_context *sctx = (struct si_context *)ctx;
3111 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3112 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3113 struct si_shader_selector *sel = state;
3114
3115 if (sctx->vs_shader.cso == sel)
3116 return;
3117
3118 sctx->vs_shader.cso = sel;
3119 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3120 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3121
3122 if (si_update_ngg(sctx))
3123 si_shader_change_notify(sctx);
3124
3125 si_update_common_shader_state(sctx);
3126 si_update_vs_viewport_state(sctx);
3127 si_set_active_descriptors_for_shader(sctx, sel);
3128 si_update_streamout_state(sctx);
3129 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3130 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3131 }
3132
3133 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3134 {
3135 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3136 (sctx->tes_shader.cso &&
3137 sctx->tes_shader.cso->info.uses_primid) ||
3138 (sctx->tcs_shader.cso &&
3139 sctx->tcs_shader.cso->info.uses_primid) ||
3140 (sctx->gs_shader.cso &&
3141 sctx->gs_shader.cso->info.uses_primid) ||
3142 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3143 sctx->ps_shader.cso->info.uses_primid);
3144 }
3145
3146 bool si_update_ngg(struct si_context *sctx)
3147 {
3148 if (!sctx->screen->use_ngg) {
3149 assert(!sctx->ngg);
3150 return false;
3151 }
3152
3153 bool new_ngg = true;
3154
3155 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3156 sctx->gs_shader.cso->tess_turns_off_ngg) {
3157 new_ngg = false;
3158 } else if (!sctx->screen->use_ngg_streamout) {
3159 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3160
3161 if ((last && last->so.num_outputs) ||
3162 sctx->streamout.prims_gen_query_enabled)
3163 new_ngg = false;
3164 }
3165
3166 if (new_ngg != sctx->ngg) {
3167 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3168 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3169 * pointers are set.
3170 */
3171 if ((sctx->family == CHIP_NAVI10 ||
3172 sctx->family == CHIP_NAVI12 ||
3173 sctx->family == CHIP_NAVI14) &&
3174 !new_ngg)
3175 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3176
3177 sctx->ngg = new_ngg;
3178 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3179 return true;
3180 }
3181 return false;
3182 }
3183
3184 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3185 {
3186 struct si_context *sctx = (struct si_context *)ctx;
3187 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3188 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3189 struct si_shader_selector *sel = state;
3190 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3191 bool ngg_changed;
3192
3193 if (sctx->gs_shader.cso == sel)
3194 return;
3195
3196 sctx->gs_shader.cso = sel;
3197 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3198 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3199
3200 si_update_common_shader_state(sctx);
3201 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3202
3203 ngg_changed = si_update_ngg(sctx);
3204 if (ngg_changed || enable_changed)
3205 si_shader_change_notify(sctx);
3206 if (enable_changed) {
3207 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3208 si_update_tess_uses_prim_id(sctx);
3209 }
3210 si_update_vs_viewport_state(sctx);
3211 si_set_active_descriptors_for_shader(sctx, sel);
3212 si_update_streamout_state(sctx);
3213 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3214 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3215 }
3216
3217 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3218 {
3219 struct si_context *sctx = (struct si_context *)ctx;
3220 struct si_shader_selector *sel = state;
3221 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3222
3223 if (sctx->tcs_shader.cso == sel)
3224 return;
3225
3226 sctx->tcs_shader.cso = sel;
3227 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3228 si_update_tess_uses_prim_id(sctx);
3229
3230 si_update_common_shader_state(sctx);
3231
3232 if (enable_changed)
3233 sctx->last_tcs = NULL; /* invalidate derived tess state */
3234
3235 si_set_active_descriptors_for_shader(sctx, sel);
3236 }
3237
3238 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3239 {
3240 struct si_context *sctx = (struct si_context *)ctx;
3241 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3242 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3243 struct si_shader_selector *sel = state;
3244 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3245
3246 if (sctx->tes_shader.cso == sel)
3247 return;
3248
3249 sctx->tes_shader.cso = sel;
3250 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3251 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3252 si_update_tess_uses_prim_id(sctx);
3253
3254 si_update_common_shader_state(sctx);
3255 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3256
3257 bool ngg_changed = si_update_ngg(sctx);
3258 if (ngg_changed || enable_changed)
3259 si_shader_change_notify(sctx);
3260 if (enable_changed)
3261 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3262 si_update_vs_viewport_state(sctx);
3263 si_set_active_descriptors_for_shader(sctx, sel);
3264 si_update_streamout_state(sctx);
3265 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3266 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3267 }
3268
3269 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3270 {
3271 struct si_context *sctx = (struct si_context *)ctx;
3272 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3273 struct si_shader_selector *sel = state;
3274
3275 /* skip if supplied shader is one already in use */
3276 if (old_sel == sel)
3277 return;
3278
3279 sctx->ps_shader.cso = sel;
3280 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3281
3282 si_update_common_shader_state(sctx);
3283 if (sel) {
3284 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3285 si_update_tess_uses_prim_id(sctx);
3286
3287 if (!old_sel ||
3288 old_sel->info.colors_written != sel->info.colors_written)
3289 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3290
3291 if (sctx->screen->has_out_of_order_rast &&
3292 (!old_sel ||
3293 old_sel->info.writes_memory != sel->info.writes_memory ||
3294 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3295 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3296 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3297 }
3298 si_set_active_descriptors_for_shader(sctx, sel);
3299 si_update_ps_colorbuf0_slot(sctx);
3300 }
3301
3302 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3303 {
3304 if (shader->is_optimized) {
3305 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3306 &shader->ready);
3307 }
3308
3309 util_queue_fence_destroy(&shader->ready);
3310
3311 if (shader->pm4) {
3312 /* If destroyed shaders were not unbound, the next compiled
3313 * shader variant could get the same pointer address and so
3314 * binding it to the same shader stage would be considered
3315 * a no-op, causing random behavior.
3316 */
3317 switch (shader->selector->type) {
3318 case PIPE_SHADER_VERTEX:
3319 if (shader->key.as_ls) {
3320 assert(sctx->chip_class <= GFX8);
3321 si_pm4_delete_state(sctx, ls, shader->pm4);
3322 } else if (shader->key.as_es) {
3323 assert(sctx->chip_class <= GFX8);
3324 si_pm4_delete_state(sctx, es, shader->pm4);
3325 } else if (shader->key.as_ngg) {
3326 si_pm4_delete_state(sctx, gs, shader->pm4);
3327 } else {
3328 si_pm4_delete_state(sctx, vs, shader->pm4);
3329 }
3330 break;
3331 case PIPE_SHADER_TESS_CTRL:
3332 si_pm4_delete_state(sctx, hs, shader->pm4);
3333 break;
3334 case PIPE_SHADER_TESS_EVAL:
3335 if (shader->key.as_es) {
3336 assert(sctx->chip_class <= GFX8);
3337 si_pm4_delete_state(sctx, es, shader->pm4);
3338 } else if (shader->key.as_ngg) {
3339 si_pm4_delete_state(sctx, gs, shader->pm4);
3340 } else {
3341 si_pm4_delete_state(sctx, vs, shader->pm4);
3342 }
3343 break;
3344 case PIPE_SHADER_GEOMETRY:
3345 if (shader->is_gs_copy_shader)
3346 si_pm4_delete_state(sctx, vs, shader->pm4);
3347 else
3348 si_pm4_delete_state(sctx, gs, shader->pm4);
3349 break;
3350 case PIPE_SHADER_FRAGMENT:
3351 si_pm4_delete_state(sctx, ps, shader->pm4);
3352 break;
3353 default:;
3354 }
3355 }
3356
3357 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3358 si_shader_destroy(shader);
3359 free(shader);
3360 }
3361
3362 void si_destroy_shader_selector(struct si_context *sctx,
3363 struct si_shader_selector *sel)
3364 {
3365 struct si_shader *p = sel->first_variant, *c;
3366 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3367 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3368 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3369 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3370 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3371 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3372 };
3373
3374 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3375
3376 if (current_shader[sel->type]->cso == sel) {
3377 current_shader[sel->type]->cso = NULL;
3378 current_shader[sel->type]->current = NULL;
3379 }
3380
3381 while (p) {
3382 c = p->next_variant;
3383 si_delete_shader(sctx, p);
3384 p = c;
3385 }
3386
3387 if (sel->main_shader_part)
3388 si_delete_shader(sctx, sel->main_shader_part);
3389 if (sel->main_shader_part_ls)
3390 si_delete_shader(sctx, sel->main_shader_part_ls);
3391 if (sel->main_shader_part_es)
3392 si_delete_shader(sctx, sel->main_shader_part_es);
3393 if (sel->main_shader_part_ngg)
3394 si_delete_shader(sctx, sel->main_shader_part_ngg);
3395 if (sel->gs_copy_shader)
3396 si_delete_shader(sctx, sel->gs_copy_shader);
3397
3398 util_queue_fence_destroy(&sel->ready);
3399 simple_mtx_destroy(&sel->mutex);
3400 ralloc_free(sel->nir);
3401 free(sel->nir_binary);
3402 free(sel);
3403 }
3404
3405 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3406 {
3407 struct si_context *sctx = (struct si_context *)ctx;
3408 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3409
3410 si_shader_selector_reference(sctx, &sel, NULL);
3411 }
3412
3413 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3414 struct si_shader *vs, unsigned name,
3415 unsigned index, unsigned interpolate)
3416 {
3417 struct si_shader_info *vsinfo = &vs->selector->info;
3418 unsigned j, offset, ps_input_cntl = 0;
3419
3420 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3421 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3422 name == TGSI_SEMANTIC_PRIMID)
3423 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3424
3425 if (name == TGSI_SEMANTIC_PCOORD ||
3426 (name == TGSI_SEMANTIC_TEXCOORD &&
3427 sctx->sprite_coord_enable & (1 << index))) {
3428 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3429 }
3430
3431 for (j = 0; j < vsinfo->num_outputs; j++) {
3432 if (name == vsinfo->output_semantic_name[j] &&
3433 index == vsinfo->output_semantic_index[j]) {
3434 offset = vs->info.vs_output_param_offset[j];
3435
3436 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3437 /* The input is loaded from parameter memory. */
3438 ps_input_cntl |= S_028644_OFFSET(offset);
3439 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3440 if (offset == AC_EXP_PARAM_UNDEFINED) {
3441 /* This can happen with depth-only rendering. */
3442 offset = 0;
3443 } else {
3444 /* The input is a DEFAULT_VAL constant. */
3445 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3446 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3447 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3448 }
3449
3450 ps_input_cntl = S_028644_OFFSET(0x20) |
3451 S_028644_DEFAULT_VAL(offset);
3452 }
3453 break;
3454 }
3455 }
3456
3457 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3458 /* PrimID is written after the last output when HW VS is used. */
3459 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3460 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3461 /* No corresponding output found, load defaults into input.
3462 * Don't set any other bits.
3463 * (FLAT_SHADE=1 completely changes behavior) */
3464 ps_input_cntl = S_028644_OFFSET(0x20);
3465 /* D3D 9 behaviour. GL is undefined */
3466 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3467 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3468 }
3469 return ps_input_cntl;
3470 }
3471
3472 static void si_emit_spi_map(struct si_context *sctx)
3473 {
3474 struct si_shader *ps = sctx->ps_shader.current;
3475 struct si_shader *vs = si_get_vs_state(sctx);
3476 struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3477 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3478 unsigned spi_ps_input_cntl[32];
3479
3480 if (!ps || !ps->selector->info.num_inputs)
3481 return;
3482
3483 num_interp = si_get_ps_num_interp(ps);
3484 assert(num_interp > 0);
3485
3486 for (i = 0; i < psinfo->num_inputs; i++) {
3487 unsigned name = psinfo->input_semantic_name[i];
3488 unsigned index = psinfo->input_semantic_index[i];
3489 unsigned interpolate = psinfo->input_interpolate[i];
3490
3491 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3492 index, interpolate);
3493
3494 if (name == TGSI_SEMANTIC_COLOR) {
3495 assert(index < ARRAY_SIZE(bcol_interp));
3496 bcol_interp[index] = interpolate;
3497 }
3498 }
3499
3500 if (ps->key.part.ps.prolog.color_two_side) {
3501 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3502
3503 for (i = 0; i < 2; i++) {
3504 if (!(psinfo->colors_read & (0xf << (i * 4))))
3505 continue;
3506
3507 spi_ps_input_cntl[num_written++] =
3508 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3509
3510 }
3511 }
3512 assert(num_interp == num_written);
3513
3514 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3515 /* Dota 2: Only ~16% of SPI map updates set different values. */
3516 /* Talos: Only ~9% of SPI map updates set different values. */
3517 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3518 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3519 spi_ps_input_cntl,
3520 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3521
3522 if (initial_cdw != sctx->gfx_cs->current.cdw)
3523 sctx->context_roll = true;
3524 }
3525
3526 /**
3527 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3528 */
3529 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3530 {
3531 if (sctx->init_config_has_vgt_flush)
3532 return;
3533
3534 /* Done by Vulkan before VGT_FLUSH. */
3535 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3536 si_pm4_cmd_add(sctx->init_config,
3537 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3538 si_pm4_cmd_end(sctx->init_config, false);
3539
3540 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3541 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3542 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3543 si_pm4_cmd_end(sctx->init_config, false);
3544 sctx->init_config_has_vgt_flush = true;
3545 }
3546
3547 /* Initialize state related to ESGS / GSVS ring buffers */
3548 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3549 {
3550 struct si_shader_selector *es =
3551 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3552 struct si_shader_selector *gs = sctx->gs_shader.cso;
3553 struct si_pm4_state *pm4;
3554
3555 /* Chip constants. */
3556 unsigned num_se = sctx->screen->info.max_se;
3557 unsigned wave_size = 64;
3558 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3559 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3560 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3561 */
3562 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3563 unsigned alignment = 256 * num_se;
3564 /* The maximum size is 63.999 MB per SE. */
3565 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3566
3567 /* Calculate the minimum size. */
3568 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3569 wave_size, alignment);
3570
3571 /* These are recommended sizes, not minimum sizes. */
3572 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3573 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3574 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3575 gs->max_gsvs_emit_size;
3576
3577 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3578 esgs_ring_size = align(esgs_ring_size, alignment);
3579 gsvs_ring_size = align(gsvs_ring_size, alignment);
3580
3581 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3582 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3583
3584 /* Some rings don't have to be allocated if shaders don't use them.
3585 * (e.g. no varyings between ES and GS or GS and VS)
3586 *
3587 * GFX9 doesn't have the ESGS ring.
3588 */
3589 bool update_esgs = sctx->chip_class <= GFX8 &&
3590 esgs_ring_size &&
3591 (!sctx->esgs_ring ||
3592 sctx->esgs_ring->width0 < esgs_ring_size);
3593 bool update_gsvs = gsvs_ring_size &&
3594 (!sctx->gsvs_ring ||
3595 sctx->gsvs_ring->width0 < gsvs_ring_size);
3596
3597 if (!update_esgs && !update_gsvs)
3598 return true;
3599
3600 if (update_esgs) {
3601 pipe_resource_reference(&sctx->esgs_ring, NULL);
3602 sctx->esgs_ring =
3603 pipe_aligned_buffer_create(sctx->b.screen,
3604 SI_RESOURCE_FLAG_UNMAPPABLE,
3605 PIPE_USAGE_DEFAULT,
3606 esgs_ring_size,
3607 sctx->screen->info.pte_fragment_size);
3608 if (!sctx->esgs_ring)
3609 return false;
3610 }
3611
3612 if (update_gsvs) {
3613 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3614 sctx->gsvs_ring =
3615 pipe_aligned_buffer_create(sctx->b.screen,
3616 SI_RESOURCE_FLAG_UNMAPPABLE,
3617 PIPE_USAGE_DEFAULT,
3618 gsvs_ring_size,
3619 sctx->screen->info.pte_fragment_size);
3620 if (!sctx->gsvs_ring)
3621 return false;
3622 }
3623
3624 /* Create the "init_config_gs_rings" state. */
3625 pm4 = CALLOC_STRUCT(si_pm4_state);
3626 if (!pm4)
3627 return false;
3628
3629 if (sctx->chip_class >= GFX7) {
3630 if (sctx->esgs_ring) {
3631 assert(sctx->chip_class <= GFX8);
3632 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3633 sctx->esgs_ring->width0 / 256);
3634 }
3635 if (sctx->gsvs_ring)
3636 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3637 sctx->gsvs_ring->width0 / 256);
3638 } else {
3639 if (sctx->esgs_ring)
3640 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3641 sctx->esgs_ring->width0 / 256);
3642 if (sctx->gsvs_ring)
3643 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3644 sctx->gsvs_ring->width0 / 256);
3645 }
3646
3647 /* Set the state. */
3648 if (sctx->init_config_gs_rings)
3649 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3650 sctx->init_config_gs_rings = pm4;
3651
3652 if (!sctx->init_config_has_vgt_flush) {
3653 si_init_config_add_vgt_flush(sctx);
3654 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3655 }
3656
3657 /* Flush the context to re-emit both init_config states. */
3658 sctx->initial_gfx_cs_size = 0; /* force flush */
3659 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3660
3661 /* Set ring bindings. */
3662 if (sctx->esgs_ring) {
3663 assert(sctx->chip_class <= GFX8);
3664 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3665 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3666 true, true, 4, 64, 0);
3667 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3668 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3669 false, false, 0, 0, 0);
3670 }
3671 if (sctx->gsvs_ring) {
3672 si_set_ring_buffer(sctx, SI_RING_GSVS,
3673 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3674 false, false, 0, 0, 0);
3675 }
3676
3677 return true;
3678 }
3679
3680 static void si_shader_lock(struct si_shader *shader)
3681 {
3682 simple_mtx_lock(&shader->selector->mutex);
3683 if (shader->previous_stage_sel) {
3684 assert(shader->previous_stage_sel != shader->selector);
3685 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3686 }
3687 }
3688
3689 static void si_shader_unlock(struct si_shader *shader)
3690 {
3691 if (shader->previous_stage_sel)
3692 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3693 simple_mtx_unlock(&shader->selector->mutex);
3694 }
3695
3696 /**
3697 * @returns 1 if \p sel has been updated to use a new scratch buffer
3698 * 0 if not
3699 * < 0 if there was a failure
3700 */
3701 static int si_update_scratch_buffer(struct si_context *sctx,
3702 struct si_shader *shader)
3703 {
3704 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3705
3706 if (!shader)
3707 return 0;
3708
3709 /* This shader doesn't need a scratch buffer */
3710 if (shader->config.scratch_bytes_per_wave == 0)
3711 return 0;
3712
3713 /* Prevent race conditions when updating:
3714 * - si_shader::scratch_bo
3715 * - si_shader::binary::code
3716 * - si_shader::previous_stage::binary::code.
3717 */
3718 si_shader_lock(shader);
3719
3720 /* This shader is already configured to use the current
3721 * scratch buffer. */
3722 if (shader->scratch_bo == sctx->scratch_buffer) {
3723 si_shader_unlock(shader);
3724 return 0;
3725 }
3726
3727 assert(sctx->scratch_buffer);
3728
3729 /* Replace the shader bo with a new bo that has the relocs applied. */
3730 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3731 si_shader_unlock(shader);
3732 return -1;
3733 }
3734
3735 /* Update the shader state to use the new shader bo. */
3736 si_shader_init_pm4_state(sctx->screen, shader);
3737
3738 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3739
3740 si_shader_unlock(shader);
3741 return 1;
3742 }
3743
3744 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3745 {
3746 return shader ? shader->config.scratch_bytes_per_wave : 0;
3747 }
3748
3749 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3750 {
3751 if (!sctx->tes_shader.cso)
3752 return NULL; /* tessellation disabled */
3753
3754 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3755 sctx->fixed_func_tcs_shader.current;
3756 }
3757
3758 static bool si_update_scratch_relocs(struct si_context *sctx)
3759 {
3760 struct si_shader *tcs = si_get_tcs_current(sctx);
3761 int r;
3762
3763 /* Update the shaders, so that they are using the latest scratch.
3764 * The scratch buffer may have been changed since these shaders were
3765 * last used, so we still need to try to update them, even if they
3766 * require scratch buffers smaller than the current size.
3767 */
3768 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3769 if (r < 0)
3770 return false;
3771 if (r == 1)
3772 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3773
3774 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3775 if (r < 0)
3776 return false;
3777 if (r == 1)
3778 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3779
3780 r = si_update_scratch_buffer(sctx, tcs);
3781 if (r < 0)
3782 return false;
3783 if (r == 1)
3784 si_pm4_bind_state(sctx, hs, tcs->pm4);
3785
3786 /* VS can be bound as LS, ES, or VS. */
3787 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3788 if (r < 0)
3789 return false;
3790 if (r == 1) {
3791 if (sctx->vs_shader.current->key.as_ls)
3792 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3793 else if (sctx->vs_shader.current->key.as_es)
3794 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3795 else if (sctx->vs_shader.current->key.as_ngg)
3796 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3797 else
3798 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3799 }
3800
3801 /* TES can be bound as ES or VS. */
3802 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3803 if (r < 0)
3804 return false;
3805 if (r == 1) {
3806 if (sctx->tes_shader.current->key.as_es)
3807 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3808 else if (sctx->tes_shader.current->key.as_ngg)
3809 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3810 else
3811 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3812 }
3813
3814 return true;
3815 }
3816
3817 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3818 {
3819 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3820 * There are 2 cases to handle:
3821 *
3822 * - If the current needed size is less than the maximum seen size,
3823 * use the maximum seen size, so that WAVESIZE remains the same.
3824 *
3825 * - If the current needed size is greater than the maximum seen size,
3826 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3827 *
3828 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3829 * Otherwise, the number of waves that can use scratch is
3830 * SPI_TMPRING_SIZE.WAVES.
3831 */
3832 unsigned bytes = 0;
3833
3834 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3835 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3836 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3837
3838 if (sctx->tes_shader.cso) {
3839 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3840 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3841 }
3842
3843 sctx->max_seen_scratch_bytes_per_wave =
3844 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3845
3846 unsigned scratch_needed_size =
3847 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3848 unsigned spi_tmpring_size;
3849
3850 if (scratch_needed_size > 0) {
3851 if (!sctx->scratch_buffer ||
3852 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3853 /* Create a bigger scratch buffer */
3854 si_resource_reference(&sctx->scratch_buffer, NULL);
3855
3856 sctx->scratch_buffer =
3857 si_aligned_buffer_create(&sctx->screen->b,
3858 SI_RESOURCE_FLAG_UNMAPPABLE,
3859 PIPE_USAGE_DEFAULT,
3860 scratch_needed_size,
3861 sctx->screen->info.pte_fragment_size);
3862 if (!sctx->scratch_buffer)
3863 return false;
3864
3865 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3866 si_context_add_resource_size(sctx,
3867 &sctx->scratch_buffer->b.b);
3868 }
3869
3870 if (!si_update_scratch_relocs(sctx))
3871 return false;
3872 }
3873
3874 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3875 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3876 "scratch size should already be aligned correctly.");
3877
3878 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3879 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3880 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3881 sctx->spi_tmpring_size = spi_tmpring_size;
3882 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3883 }
3884 return true;
3885 }
3886
3887 static void si_init_tess_factor_ring(struct si_context *sctx)
3888 {
3889 assert(!sctx->tess_rings);
3890 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3891
3892 /* The address must be aligned to 2^19, because the shader only
3893 * receives the high 13 bits.
3894 */
3895 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3896 SI_RESOURCE_FLAG_32BIT,
3897 PIPE_USAGE_DEFAULT,
3898 sctx->screen->tess_offchip_ring_size +
3899 sctx->screen->tess_factor_ring_size,
3900 1 << 19);
3901 if (!sctx->tess_rings)
3902 return;
3903
3904 si_init_config_add_vgt_flush(sctx);
3905
3906 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3907 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3908
3909 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3910 sctx->screen->tess_offchip_ring_size;
3911
3912 /* Append these registers to the init config state. */
3913 if (sctx->chip_class >= GFX7) {
3914 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3915 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3916 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3917 factor_va >> 8);
3918 if (sctx->chip_class >= GFX10)
3919 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3920 S_030984_BASE_HI(factor_va >> 40));
3921 else if (sctx->chip_class == GFX9)
3922 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3923 S_030944_BASE_HI(factor_va >> 40));
3924 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3925 sctx->screen->vgt_hs_offchip_param);
3926 } else {
3927 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3928 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3929 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3930 factor_va >> 8);
3931 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3932 sctx->screen->vgt_hs_offchip_param);
3933 }
3934
3935 /* Flush the context to re-emit the init_config state.
3936 * This is done only once in a lifetime of a context.
3937 */
3938 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3939 sctx->initial_gfx_cs_size = 0; /* force flush */
3940 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3941 }
3942
3943 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3944 union si_vgt_stages_key key)
3945 {
3946 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3947 uint32_t stages = 0;
3948
3949 if (key.u.tess) {
3950 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3951 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3952
3953 if (key.u.gs)
3954 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3955 S_028B54_GS_EN(1);
3956 else if (key.u.ngg)
3957 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3958 else
3959 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3960 } else if (key.u.gs) {
3961 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3962 S_028B54_GS_EN(1);
3963 } else if (key.u.ngg) {
3964 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3965 }
3966
3967 if (key.u.ngg) {
3968 stages |= S_028B54_PRIMGEN_EN(1) |
3969 S_028B54_GS_FAST_LAUNCH(key.u.ngg_gs_fast_launch) |
3970 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3971 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3972 } else if (key.u.gs)
3973 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3974
3975 if (screen->info.chip_class >= GFX9)
3976 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3977
3978 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3979 stages |= S_028B54_HS_W32_EN(1) |
3980 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3981 S_028B54_VS_W32_EN(1);
3982 }
3983
3984 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3985 return pm4;
3986 }
3987
3988 static void si_update_vgt_shader_config(struct si_context *sctx,
3989 union si_vgt_stages_key key)
3990 {
3991 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3992
3993 if (unlikely(!*pm4))
3994 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3995 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3996 }
3997
3998 bool si_update_shaders(struct si_context *sctx)
3999 {
4000 struct pipe_context *ctx = (struct pipe_context*)sctx;
4001 struct si_compiler_ctx_state compiler_state;
4002 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
4003 struct si_shader *old_vs = si_get_vs_state(sctx);
4004 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
4005 struct si_shader *old_ps = sctx->ps_shader.current;
4006 union si_vgt_stages_key key;
4007 unsigned old_spi_shader_col_format =
4008 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
4009 int r;
4010
4011 if (!sctx->compiler.passes)
4012 si_init_compiler(sctx->screen, &sctx->compiler);
4013
4014 compiler_state.compiler = &sctx->compiler;
4015 compiler_state.debug = sctx->debug;
4016 compiler_state.is_debug_context = sctx->is_debug;
4017
4018 key.index = 0;
4019
4020 if (sctx->tes_shader.cso)
4021 key.u.tess = 1;
4022 if (sctx->gs_shader.cso)
4023 key.u.gs = 1;
4024
4025 if (sctx->ngg) {
4026 key.u.ngg = 1;
4027 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
4028 }
4029
4030 /* Update TCS and TES. */
4031 if (sctx->tes_shader.cso) {
4032 if (!sctx->tess_rings) {
4033 si_init_tess_factor_ring(sctx);
4034 if (!sctx->tess_rings)
4035 return false;
4036 }
4037
4038 if (sctx->tcs_shader.cso) {
4039 r = si_shader_select(ctx, &sctx->tcs_shader, key,
4040 &compiler_state);
4041 if (r)
4042 return false;
4043 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
4044 } else {
4045 if (!sctx->fixed_func_tcs_shader.cso) {
4046 sctx->fixed_func_tcs_shader.cso =
4047 si_create_fixed_func_tcs(sctx);
4048 if (!sctx->fixed_func_tcs_shader.cso)
4049 return false;
4050 }
4051
4052 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
4053 key, &compiler_state);
4054 if (r)
4055 return false;
4056 si_pm4_bind_state(sctx, hs,
4057 sctx->fixed_func_tcs_shader.current->pm4);
4058 }
4059
4060 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
4061 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
4062 if (r)
4063 return false;
4064
4065 if (sctx->gs_shader.cso) {
4066 /* TES as ES */
4067 assert(sctx->chip_class <= GFX8);
4068 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
4069 } else if (key.u.ngg) {
4070 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
4071 } else {
4072 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
4073 }
4074 }
4075 } else {
4076 if (sctx->chip_class <= GFX8)
4077 si_pm4_bind_state(sctx, ls, NULL);
4078 si_pm4_bind_state(sctx, hs, NULL);
4079 }
4080
4081 /* Update GS. */
4082 if (sctx->gs_shader.cso) {
4083 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
4084 if (r)
4085 return false;
4086 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
4087 if (!key.u.ngg) {
4088 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
4089
4090 if (!si_update_gs_ring_buffers(sctx))
4091 return false;
4092 } else {
4093 si_pm4_bind_state(sctx, vs, NULL);
4094 }
4095 } else {
4096 if (!key.u.ngg) {
4097 si_pm4_bind_state(sctx, gs, NULL);
4098 if (sctx->chip_class <= GFX8)
4099 si_pm4_bind_state(sctx, es, NULL);
4100 }
4101 }
4102
4103 /* Update VS. */
4104 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
4105 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
4106 if (r)
4107 return false;
4108
4109 if (!key.u.tess && !key.u.gs) {
4110 if (key.u.ngg) {
4111 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
4112 si_pm4_bind_state(sctx, vs, NULL);
4113 } else {
4114 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4115 }
4116 } else if (sctx->tes_shader.cso) {
4117 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4118 } else {
4119 assert(sctx->gs_shader.cso);
4120 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4121 }
4122 }
4123
4124 /* This must be done after the shader variant is selected. */
4125 if (sctx->ngg) {
4126 struct si_shader *vs = si_get_vs(sctx)->current;
4127
4128 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(vs);
4129 key.u.ngg_gs_fast_launch = !!(vs->key.opt.ngg_culling &
4130 SI_NGG_CULL_GS_FAST_LAUNCH_ALL);
4131 }
4132
4133 si_update_vgt_shader_config(sctx, key);
4134
4135 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4136 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4137
4138 if (sctx->ps_shader.cso) {
4139 unsigned db_shader_control;
4140
4141 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4142 if (r)
4143 return false;
4144 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4145
4146 db_shader_control =
4147 sctx->ps_shader.cso->db_shader_control |
4148 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4149
4150 if (si_pm4_state_changed(sctx, ps) ||
4151 si_pm4_state_changed(sctx, vs) ||
4152 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4153 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4154 sctx->flatshade != rs->flatshade) {
4155 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4156 sctx->flatshade = rs->flatshade;
4157 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4158 }
4159
4160 if (sctx->screen->info.rbplus_allowed &&
4161 si_pm4_state_changed(sctx, ps) &&
4162 (!old_ps ||
4163 old_spi_shader_col_format !=
4164 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4165 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4166
4167 if (sctx->ps_db_shader_control != db_shader_control) {
4168 sctx->ps_db_shader_control = db_shader_control;
4169 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4170 if (sctx->screen->dpbb_allowed)
4171 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4172 }
4173
4174 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4175 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4176 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4177
4178 if (sctx->chip_class == GFX6)
4179 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4180
4181 if (sctx->framebuffer.nr_samples <= 1)
4182 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4183 }
4184 }
4185
4186 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4187 si_pm4_state_enabled_and_changed(sctx, hs) ||
4188 si_pm4_state_enabled_and_changed(sctx, es) ||
4189 si_pm4_state_enabled_and_changed(sctx, gs) ||
4190 si_pm4_state_enabled_and_changed(sctx, vs) ||
4191 si_pm4_state_enabled_and_changed(sctx, ps)) {
4192 if (!si_update_spi_tmpring_size(sctx))
4193 return false;
4194 }
4195
4196 if (sctx->chip_class >= GFX7) {
4197 if (si_pm4_state_enabled_and_changed(sctx, ls))
4198 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4199 else if (!sctx->queued.named.ls)
4200 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4201
4202 if (si_pm4_state_enabled_and_changed(sctx, hs))
4203 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4204 else if (!sctx->queued.named.hs)
4205 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4206
4207 if (si_pm4_state_enabled_and_changed(sctx, es))
4208 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4209 else if (!sctx->queued.named.es)
4210 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4211
4212 if (si_pm4_state_enabled_and_changed(sctx, gs))
4213 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4214 else if (!sctx->queued.named.gs)
4215 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4216
4217 if (si_pm4_state_enabled_and_changed(sctx, vs))
4218 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4219 else if (!sctx->queued.named.vs)
4220 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4221
4222 if (si_pm4_state_enabled_and_changed(sctx, ps))
4223 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4224 else if (!sctx->queued.named.ps)
4225 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4226 }
4227
4228 sctx->do_update_shaders = false;
4229 return true;
4230 }
4231
4232 static void si_emit_scratch_state(struct si_context *sctx)
4233 {
4234 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4235
4236 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4237 sctx->spi_tmpring_size);
4238
4239 if (sctx->scratch_buffer) {
4240 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4241 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4242 RADEON_PRIO_SCRATCH_BUFFER);
4243 }
4244 }
4245
4246 void si_init_shader_functions(struct si_context *sctx)
4247 {
4248 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4249 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4250
4251 sctx->b.create_vs_state = si_create_shader_selector;
4252 sctx->b.create_tcs_state = si_create_shader_selector;
4253 sctx->b.create_tes_state = si_create_shader_selector;
4254 sctx->b.create_gs_state = si_create_shader_selector;
4255 sctx->b.create_fs_state = si_create_shader_selector;
4256
4257 sctx->b.bind_vs_state = si_bind_vs_shader;
4258 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4259 sctx->b.bind_tes_state = si_bind_tes_shader;
4260 sctx->b.bind_gs_state = si_bind_gs_shader;
4261 sctx->b.bind_fs_state = si_bind_ps_shader;
4262
4263 sctx->b.delete_vs_state = si_delete_shader_selector;
4264 sctx->b.delete_tcs_state = si_delete_shader_selector;
4265 sctx->b.delete_tes_state = si_delete_shader_selector;
4266 sctx->b.delete_gs_state = si_delete_shader_selector;
4267 sctx->b.delete_fs_state = si_delete_shader_selector;
4268 }