de5ca569473a4d572368113555c60e2746711e8e
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "ac_exp_param.h"
26 #include "ac_shader_util.h"
27 #include "compiler/nir/nir_serialize.h"
28 #include "nir/tgsi_to_nir.h"
29 #include "si_build_pm4.h"
30 #include "sid.h"
31 #include "util/crc32.h"
32 #include "util/disk_cache.h"
33 #include "util/hash_table.h"
34 #include "util/mesa-sha1.h"
35 #include "util/u_async_debug.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38
39 /* SHADER_CACHE */
40
41 /**
42 * Return the IR key for the shader cache.
43 */
44 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
45 unsigned char ir_sha1_cache_key[20])
46 {
47 struct blob blob = {};
48 unsigned ir_size;
49 void *ir_binary;
50
51 if (sel->nir_binary) {
52 ir_binary = sel->nir_binary;
53 ir_size = sel->nir_size;
54 } else {
55 assert(sel->nir);
56
57 blob_init(&blob);
58 nir_serialize(&blob, sel->nir, true);
59 ir_binary = blob.data;
60 ir_size = blob.size;
61 }
62
63 /* These settings affect the compilation, but they are not derived
64 * from the input shader IR.
65 */
66 unsigned shader_variant_flags = 0;
67
68 if (ngg)
69 shader_variant_flags |= 1 << 0;
70 if (sel->nir)
71 shader_variant_flags |= 1 << 1;
72 if (si_get_wave_size(sel->screen, sel->type, ngg, es, false) == 32)
73 shader_variant_flags |= 1 << 2;
74 if (sel->type == PIPE_SHADER_FRAGMENT && sel->info.uses_derivatives && sel->info.uses_kill &&
75 sel->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
76 shader_variant_flags |= 1 << 3;
77
78 /* This varies depending on whether compute-based culling is enabled. */
79 shader_variant_flags |= sel->screen->num_vbos_in_user_sgprs << 4;
80
81 struct mesa_sha1 ctx;
82 _mesa_sha1_init(&ctx);
83 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
84 _mesa_sha1_update(&ctx, ir_binary, ir_size);
85 if (sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_TESS_EVAL ||
86 sel->type == PIPE_SHADER_GEOMETRY)
87 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
88 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
89
90 if (ir_binary == blob.data)
91 blob_finish(&blob);
92 }
93
94 /** Copy "data" to "ptr" and return the next dword following copied data. */
95 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
96 {
97 /* data may be NULL if size == 0 */
98 if (size)
99 memcpy(ptr, data, size);
100 ptr += DIV_ROUND_UP(size, 4);
101 return ptr;
102 }
103
104 /** Read data from "ptr". Return the next dword following the data. */
105 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
106 {
107 memcpy(data, ptr, size);
108 ptr += DIV_ROUND_UP(size, 4);
109 return ptr;
110 }
111
112 /**
113 * Write the size as uint followed by the data. Return the next dword
114 * following the copied data.
115 */
116 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
117 {
118 *ptr++ = size;
119 return write_data(ptr, data, size);
120 }
121
122 /**
123 * Read the size as uint followed by the data. Return both via parameters.
124 * Return the next dword following the data.
125 */
126 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
127 {
128 *size = *ptr++;
129 assert(*data == NULL);
130 if (!*size)
131 return ptr;
132 *data = malloc(*size);
133 return read_data(ptr, *data, *size);
134 }
135
136 /**
137 * Return the shader binary in a buffer. The first 4 bytes contain its size
138 * as integer.
139 */
140 static void *si_get_shader_binary(struct si_shader *shader)
141 {
142 /* There is always a size of data followed by the data itself. */
143 unsigned llvm_ir_size =
144 shader->binary.llvm_ir_string ? strlen(shader->binary.llvm_ir_string) + 1 : 0;
145
146 /* Refuse to allocate overly large buffers and guard against integer
147 * overflow. */
148 if (shader->binary.elf_size > UINT_MAX / 4 || llvm_ir_size > UINT_MAX / 4)
149 return NULL;
150
151 unsigned size = 4 + /* total size */
152 4 + /* CRC32 of the data below */
153 align(sizeof(shader->config), 4) + align(sizeof(shader->info), 4) + 4 +
154 align(shader->binary.elf_size, 4) + 4 + align(llvm_ir_size, 4);
155 void *buffer = CALLOC(1, size);
156 uint32_t *ptr = (uint32_t *)buffer;
157
158 if (!buffer)
159 return NULL;
160
161 *ptr++ = size;
162 ptr++; /* CRC32 is calculated at the end. */
163
164 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
165 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
166 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
167 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
168 assert((char *)ptr - (char *)buffer == size);
169
170 /* Compute CRC32. */
171 ptr = (uint32_t *)buffer;
172 ptr++;
173 *ptr = util_hash_crc32(ptr + 1, size - 8);
174
175 return buffer;
176 }
177
178 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
179 {
180 uint32_t *ptr = (uint32_t *)binary;
181 uint32_t size = *ptr++;
182 uint32_t crc32 = *ptr++;
183 unsigned chunk_size;
184 unsigned elf_size;
185
186 if (util_hash_crc32(ptr, size - 8) != crc32) {
187 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
188 return false;
189 }
190
191 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
192 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
193 ptr = read_chunk(ptr, (void **)&shader->binary.elf_buffer, &elf_size);
194 shader->binary.elf_size = elf_size;
195 ptr = read_chunk(ptr, (void **)&shader->binary.llvm_ir_string, &chunk_size);
196
197 return true;
198 }
199
200 /**
201 * Insert a shader into the cache. It's assumed the shader is not in the cache.
202 * Use si_shader_cache_load_shader before calling this.
203 */
204 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
205 struct si_shader *shader, bool insert_into_disk_cache)
206 {
207 void *hw_binary;
208 struct hash_entry *entry;
209 uint8_t key[CACHE_KEY_SIZE];
210
211 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
212 if (entry)
213 return; /* already added */
214
215 hw_binary = si_get_shader_binary(shader);
216 if (!hw_binary)
217 return;
218
219 if (_mesa_hash_table_insert(sscreen->shader_cache, mem_dup(ir_sha1_cache_key, 20), hw_binary) ==
220 NULL) {
221 FREE(hw_binary);
222 return;
223 }
224
225 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
226 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, key);
227 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary, *((uint32_t *)hw_binary), NULL);
228 }
229 }
230
231 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
232 struct si_shader *shader)
233 {
234 struct hash_entry *entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
235
236 if (entry) {
237 if (si_load_shader_binary(shader, entry->data)) {
238 p_atomic_inc(&sscreen->num_memory_shader_cache_hits);
239 return true;
240 }
241 }
242 p_atomic_inc(&sscreen->num_memory_shader_cache_misses);
243
244 if (!sscreen->disk_shader_cache)
245 return false;
246
247 unsigned char sha1[CACHE_KEY_SIZE];
248 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, sha1);
249
250 size_t binary_size;
251 uint8_t *buffer = disk_cache_get(sscreen->disk_shader_cache, sha1, &binary_size);
252 if (buffer) {
253 if (binary_size >= sizeof(uint32_t) && *((uint32_t *)buffer) == binary_size) {
254 if (si_load_shader_binary(shader, buffer)) {
255 free(buffer);
256 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, false);
257 p_atomic_inc(&sscreen->num_disk_shader_cache_hits);
258 return true;
259 }
260 } else {
261 /* Something has gone wrong discard the item from the cache and
262 * rebuild/link from source.
263 */
264 assert(!"Invalid radeonsi shader disk cache item!");
265 disk_cache_remove(sscreen->disk_shader_cache, sha1);
266 }
267 }
268
269 free(buffer);
270 p_atomic_inc(&sscreen->num_disk_shader_cache_misses);
271 return false;
272 }
273
274 static uint32_t si_shader_cache_key_hash(const void *key)
275 {
276 /* Take the first dword of SHA1. */
277 return *(uint32_t *)key;
278 }
279
280 static bool si_shader_cache_key_equals(const void *a, const void *b)
281 {
282 /* Compare SHA1s. */
283 return memcmp(a, b, 20) == 0;
284 }
285
286 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
287 {
288 FREE((void *)entry->key);
289 FREE(entry->data);
290 }
291
292 bool si_init_shader_cache(struct si_screen *sscreen)
293 {
294 (void)simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
295 sscreen->shader_cache =
296 _mesa_hash_table_create(NULL, si_shader_cache_key_hash, si_shader_cache_key_equals);
297
298 return sscreen->shader_cache != NULL;
299 }
300
301 void si_destroy_shader_cache(struct si_screen *sscreen)
302 {
303 if (sscreen->shader_cache)
304 _mesa_hash_table_destroy(sscreen->shader_cache, si_destroy_shader_cache_entry);
305 simple_mtx_destroy(&sscreen->shader_cache_mutex);
306 }
307
308 /* SHADER STATES */
309
310 static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shader_selector *tes,
311 struct si_pm4_state *pm4)
312 {
313 const struct si_shader_info *info = &tes->info;
314 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
315 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
316 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
317 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
318 unsigned type, partitioning, topology, distribution_mode;
319
320 switch (tes_prim_mode) {
321 case PIPE_PRIM_LINES:
322 type = V_028B6C_TESS_ISOLINE;
323 break;
324 case PIPE_PRIM_TRIANGLES:
325 type = V_028B6C_TESS_TRIANGLE;
326 break;
327 case PIPE_PRIM_QUADS:
328 type = V_028B6C_TESS_QUAD;
329 break;
330 default:
331 assert(0);
332 return;
333 }
334
335 switch (tes_spacing) {
336 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
337 partitioning = V_028B6C_PART_FRAC_ODD;
338 break;
339 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
340 partitioning = V_028B6C_PART_FRAC_EVEN;
341 break;
342 case PIPE_TESS_SPACING_EQUAL:
343 partitioning = V_028B6C_PART_INTEGER;
344 break;
345 default:
346 assert(0);
347 return;
348 }
349
350 if (tes_point_mode)
351 topology = V_028B6C_OUTPUT_POINT;
352 else if (tes_prim_mode == PIPE_PRIM_LINES)
353 topology = V_028B6C_OUTPUT_LINE;
354 else if (tes_vertex_order_cw)
355 /* for some reason, this must be the other way around */
356 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
357 else
358 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
359
360 if (sscreen->info.has_distributed_tess) {
361 if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10)
362 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
363 else
364 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
365 } else
366 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
367
368 assert(pm4->shader);
369 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
370 S_028B6C_TOPOLOGY(topology) |
371 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
372 }
373
374 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
375 * whether the "fractional odd" tessellation spacing is used.
376 *
377 * Possible VGT configurations and which state should set the register:
378 *
379 * Reg set in | VGT shader configuration | Value
380 * ------------------------------------------------------
381 * VS as VS | VS | 30
382 * VS as ES | ES -> GS -> VS | 30
383 * TES as VS | LS -> HS -> VS | 14 or 30
384 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
385 *
386 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
387 */
388 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_shader_selector *sel,
389 struct si_shader *shader, struct si_pm4_state *pm4)
390 {
391 unsigned type = sel->type;
392
393 if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.chip_class >= GFX10)
394 return;
395
396 /* VS as VS, or VS as ES: */
397 if ((type == PIPE_SHADER_VERTEX &&
398 (!shader || (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
399 /* TES as VS, or TES as ES: */
400 type == PIPE_SHADER_TESS_EVAL) {
401 unsigned vtx_reuse_depth = 30;
402
403 if (type == PIPE_SHADER_TESS_EVAL &&
404 sel->info.properties[TGSI_PROPERTY_TES_SPACING] == PIPE_TESS_SPACING_FRACTIONAL_ODD)
405 vtx_reuse_depth = 14;
406
407 assert(pm4->shader);
408 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
409 }
410 }
411
412 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
413 {
414 if (shader->pm4)
415 si_pm4_clear_state(shader->pm4);
416 else
417 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
418
419 if (shader->pm4) {
420 shader->pm4->shader = shader;
421 return shader->pm4;
422 } else {
423 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
424 return NULL;
425 }
426 }
427
428 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
429 unsigned num_always_on_user_sgprs)
430 {
431 struct si_shader_selector *vs =
432 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
433 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
434
435 /* 1 SGPR is reserved for the vertex buffer pointer. */
436 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
437
438 if (num_vbos_in_user_sgprs)
439 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
440
441 /* Add the pointer to VBO descriptors. */
442 return num_always_on_user_sgprs + 1;
443 }
444
445 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
446 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_shader *shader,
447 bool legacy_vs_prim_id)
448 {
449 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
450 (shader->previous_stage_sel && shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
451
452 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
453 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
454 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
455 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or
456 * InstanceID)
457 */
458 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
459
460 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
461 return 3;
462 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
463 return 2;
464 else if (is_ls || shader->info.uses_instanceid)
465 return 1;
466 else
467 return 0;
468 }
469
470 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
471 {
472 struct si_pm4_state *pm4;
473 uint64_t va;
474
475 assert(sscreen->info.chip_class <= GFX8);
476
477 pm4 = si_get_shader_pm4_state(shader);
478 if (!pm4)
479 return;
480
481 va = shader->bo->gpu_address;
482 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
483
484 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
485 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
486
487 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
488 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
489 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
490 S_00B528_DX10_CLAMP(1) | S_00B528_FLOAT_MODE(shader->config.float_mode);
491 shader->config.rsrc2 =
492 S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
493 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
494 }
495
496 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
497 {
498 struct si_pm4_state *pm4;
499 uint64_t va;
500
501 pm4 = si_get_shader_pm4_state(shader);
502 if (!pm4)
503 return;
504
505 va = shader->bo->gpu_address;
506 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
507
508 if (sscreen->info.chip_class >= GFX9) {
509 if (sscreen->info.chip_class >= GFX10) {
510 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
511 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
512 } else {
513 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
514 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
515 }
516
517 unsigned num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
518
519 shader->config.rsrc2 = S_00B42C_USER_SGPR(num_user_sgprs) |
520 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
521
522 if (sscreen->info.chip_class >= GFX10)
523 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
524 else
525 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
526 } else {
527 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
528 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
529
530 shader->config.rsrc2 = S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) | S_00B42C_OC_LDS_EN(1) |
531 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
532 }
533
534 si_pm4_set_reg(
535 pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
536 S_00B428_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
537 (sscreen->info.chip_class <= GFX9 ? S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8)
538 : 0) |
539 S_00B428_DX10_CLAMP(1) | S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
540 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
541 S_00B428_FLOAT_MODE(shader->config.float_mode) |
542 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9
543 ? si_get_vs_vgpr_comp_cnt(sscreen, shader, false)
544 : 0));
545
546 if (sscreen->info.chip_class <= GFX8) {
547 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2);
548 }
549 }
550
551 static void si_emit_shader_es(struct si_context *sctx)
552 {
553 struct si_shader *shader = sctx->queued.named.es->shader;
554 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
555
556 if (!shader)
557 return;
558
559 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
560 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
561 shader->selector->esgs_itemsize / 4);
562
563 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
564 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
565 shader->vgt_tf_param);
566
567 if (shader->vgt_vertex_reuse_block_cntl)
568 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
569 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
570 shader->vgt_vertex_reuse_block_cntl);
571
572 if (initial_cdw != sctx->gfx_cs->current.cdw)
573 sctx->context_roll = true;
574 }
575
576 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
577 {
578 struct si_pm4_state *pm4;
579 unsigned num_user_sgprs;
580 unsigned vgpr_comp_cnt;
581 uint64_t va;
582 unsigned oc_lds_en;
583
584 assert(sscreen->info.chip_class <= GFX8);
585
586 pm4 = si_get_shader_pm4_state(shader);
587 if (!pm4)
588 return;
589
590 pm4->atom.emit = si_emit_shader_es;
591 va = shader->bo->gpu_address;
592 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
593
594 if (shader->selector->type == PIPE_SHADER_VERTEX) {
595 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
596 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
597 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
598 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
599 num_user_sgprs = SI_TES_NUM_USER_SGPR;
600 } else
601 unreachable("invalid shader selector type");
602
603 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
604
605 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
606 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
607 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
608 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
609 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
610 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B328_DX10_CLAMP(1) |
611 S_00B328_FLOAT_MODE(shader->config.float_mode));
612 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
613 S_00B32C_USER_SGPR(num_user_sgprs) | S_00B32C_OC_LDS_EN(oc_lds_en) |
614 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
615
616 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
617 si_set_tesseval_regs(sscreen, shader->selector, pm4);
618
619 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
620 }
621
622 void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *gs,
623 struct gfx9_gs_info *out)
624 {
625 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
626 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
627 bool uses_adjacency =
628 input_prim >= PIPE_PRIM_LINES_ADJACENCY && input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
629
630 /* All these are in dwords: */
631 /* We can't allow using the whole LDS, because GS waves compete with
632 * other shader stages for LDS space. */
633 const unsigned max_lds_size = 8 * 1024;
634 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
635 unsigned esgs_lds_size;
636
637 /* All these are per subgroup: */
638 const unsigned max_out_prims = 32 * 1024;
639 const unsigned max_es_verts = 255;
640 const unsigned ideal_gs_prims = 64;
641 unsigned max_gs_prims, gs_prims;
642 unsigned min_es_verts, es_verts, worst_case_es_verts;
643
644 if (uses_adjacency || gs_num_invocations > 1)
645 max_gs_prims = 127 / gs_num_invocations;
646 else
647 max_gs_prims = 255;
648
649 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
650 * Make sure we don't go over the maximum value.
651 */
652 if (gs->gs_max_out_vertices > 0) {
653 max_gs_prims =
654 MIN2(max_gs_prims, max_out_prims / (gs->gs_max_out_vertices * gs_num_invocations));
655 }
656 assert(max_gs_prims > 0);
657
658 /* If the primitive has adjacency, halve the number of vertices
659 * that will be reused in multiple primitives.
660 */
661 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
662
663 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
664 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
665
666 /* Compute ESGS LDS size based on the worst case number of ES vertices
667 * needed to create the target number of GS prims per subgroup.
668 */
669 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
670
671 /* If total LDS usage is too big, refactor partitions based on ratio
672 * of ESGS item sizes.
673 */
674 if (esgs_lds_size > max_lds_size) {
675 /* Our target GS Prims Per Subgroup was too large. Calculate
676 * the maximum number of GS Prims Per Subgroup that will fit
677 * into LDS, capped by the maximum that the hardware can support.
678 */
679 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)), max_gs_prims);
680 assert(gs_prims > 0);
681 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
682
683 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
684 assert(esgs_lds_size <= max_lds_size);
685 }
686
687 /* Now calculate remaining ESGS information. */
688 if (esgs_lds_size)
689 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
690 else
691 es_verts = max_es_verts;
692
693 /* Vertices for adjacency primitives are not always reused, so restore
694 * it for ES_VERTS_PER_SUBGRP.
695 */
696 min_es_verts = gs->gs_input_verts_per_prim;
697
698 /* For normal primitives, the VGT only checks if they are past the ES
699 * verts per subgroup after allocating a full GS primitive and if they
700 * are, kick off a new subgroup. But if those additional ES verts are
701 * unique (e.g. not reused) we need to make sure there is enough LDS
702 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
703 */
704 es_verts -= min_es_verts - 1;
705
706 out->es_verts_per_subgroup = es_verts;
707 out->gs_prims_per_subgroup = gs_prims;
708 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
709 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup * gs->gs_max_out_vertices;
710 out->esgs_ring_size = 4 * esgs_lds_size;
711
712 assert(out->max_prims_per_subgroup <= max_out_prims);
713 }
714
715 static void si_emit_shader_gs(struct si_context *sctx)
716 {
717 struct si_shader *shader = sctx->queued.named.gs->shader;
718 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
719
720 if (!shader)
721 return;
722
723 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
724 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
725 radeon_opt_set_context_reg3(
726 sctx, R_028A60_VGT_GSVS_RING_OFFSET_1, SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
727 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1, shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
728 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
729
730 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
731 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
732 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
733 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
734
735 /* R_028B38_VGT_GS_MAX_VERT_OUT */
736 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
737 shader->ctx_reg.gs.vgt_gs_max_vert_out);
738
739 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
740 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
741 radeon_opt_set_context_reg4(
742 sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE, SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
743 shader->ctx_reg.gs.vgt_gs_vert_itemsize, shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
744 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2, shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
745
746 /* R_028B90_VGT_GS_INSTANCE_CNT */
747 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
748 shader->ctx_reg.gs.vgt_gs_instance_cnt);
749
750 if (sctx->chip_class >= GFX9) {
751 /* R_028A44_VGT_GS_ONCHIP_CNTL */
752 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
753 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
754 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
755 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
756 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
757 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
758 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
759 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
760 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
761 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
762
763 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
764 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
765 shader->vgt_tf_param);
766 if (shader->vgt_vertex_reuse_block_cntl)
767 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
768 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
769 shader->vgt_vertex_reuse_block_cntl);
770 }
771
772 if (initial_cdw != sctx->gfx_cs->current.cdw)
773 sctx->context_roll = true;
774 }
775
776 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
777 {
778 struct si_shader_selector *sel = shader->selector;
779 const ubyte *num_components = sel->info.num_stream_output_components;
780 unsigned gs_num_invocations = sel->gs_num_invocations;
781 struct si_pm4_state *pm4;
782 uint64_t va;
783 unsigned max_stream = sel->max_gs_stream;
784 unsigned offset;
785
786 pm4 = si_get_shader_pm4_state(shader);
787 if (!pm4)
788 return;
789
790 pm4->atom.emit = si_emit_shader_gs;
791
792 offset = num_components[0] * sel->gs_max_out_vertices;
793 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
794
795 if (max_stream >= 1)
796 offset += num_components[1] * sel->gs_max_out_vertices;
797 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
798
799 if (max_stream >= 2)
800 offset += num_components[2] * sel->gs_max_out_vertices;
801 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
802
803 if (max_stream >= 3)
804 offset += num_components[3] * sel->gs_max_out_vertices;
805 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
806
807 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
808 assert(offset < (1 << 15));
809
810 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
811
812 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
813 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
814 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
815 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
816
817 shader->ctx_reg.gs.vgt_gs_instance_cnt =
818 S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0);
819
820 va = shader->bo->gpu_address;
821 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
822
823 if (sscreen->info.chip_class >= GFX9) {
824 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
825 unsigned es_type = shader->key.part.gs.es->type;
826 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
827
828 if (es_type == PIPE_SHADER_VERTEX) {
829 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
830 } else if (es_type == PIPE_SHADER_TESS_EVAL)
831 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
832 else
833 unreachable("invalid shader selector type");
834
835 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
836 * VGPR[0:4] are always loaded.
837 */
838 if (sel->info.uses_invocationid)
839 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
840 else if (sel->info.uses_primid)
841 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
842 else if (input_prim >= PIPE_PRIM_TRIANGLES)
843 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
844 else
845 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
846
847 unsigned num_user_sgprs;
848 if (es_type == PIPE_SHADER_VERTEX)
849 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
850 else
851 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
852
853 if (sscreen->info.chip_class >= GFX10) {
854 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
855 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
856 } else {
857 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
858 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
859 }
860
861 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) |
862 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
863 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
864 S_00B228_FLOAT_MODE(shader->config.float_mode) |
865 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
866 uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) |
867 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
868 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
869 S_00B22C_LDS_SIZE(shader->config.lds_size) |
870 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
871
872 if (sscreen->info.chip_class >= GFX10) {
873 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
874 } else {
875 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
876 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
877 }
878
879 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
880 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
881
882 if (sscreen->info.chip_class >= GFX10) {
883 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
884 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
885 }
886
887 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
888 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
889 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
890 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
891 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
892 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
893 shader->ctx_reg.gs.vgt_esgs_ring_itemsize = shader->key.part.gs.es->esgs_itemsize / 4;
894
895 if (es_type == PIPE_SHADER_TESS_EVAL)
896 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
897
898 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es, NULL, pm4);
899 } else {
900 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
901 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
902
903 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
904 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
905 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
906 S_00B228_DX10_CLAMP(1) | S_00B228_FLOAT_MODE(shader->config.float_mode));
907 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
908 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
909 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
910 }
911 }
912
913 static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
914 {
915 enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
916
917 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
918 sctx->tracked_regs.reg_value[reg] != value) {
919 struct radeon_cmdbuf *cs = sctx->gfx_cs;
920
921 if (sctx->chip_class == GFX10) {
922 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
923 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
924 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
925 }
926
927 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
928
929 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
930 sctx->tracked_regs.reg_value[reg] = value;
931 }
932 }
933
934 /* Common tail code for NGG primitive shaders. */
935 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader *shader,
936 unsigned initial_cdw)
937 {
938 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
939 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
940 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
941 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
942 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
943 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
944 shader->ctx_reg.ngg.vgt_primitiveid_en);
945 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
946 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
947 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
948 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
949 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
950 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
951 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
952 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
953 shader->ctx_reg.ngg.spi_vs_out_config);
954 radeon_opt_set_context_reg2(
955 sctx, R_028708_SPI_SHADER_IDX_FORMAT, SI_TRACKED_SPI_SHADER_IDX_FORMAT,
956 shader->ctx_reg.ngg.spi_shader_idx_format, shader->ctx_reg.ngg.spi_shader_pos_format);
957 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
958 shader->ctx_reg.ngg.pa_cl_vte_cntl);
959 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
960 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
961
962 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
963 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, shader->pa_cl_vs_out_cntl,
964 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
965
966 if (initial_cdw != sctx->gfx_cs->current.cdw)
967 sctx->context_roll = true;
968
969 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
970 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
971 }
972
973 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
974 {
975 struct si_shader *shader = sctx->queued.named.gs->shader;
976 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
977
978 if (!shader)
979 return;
980
981 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
982 }
983
984 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
985 {
986 struct si_shader *shader = sctx->queued.named.gs->shader;
987 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
988
989 if (!shader)
990 return;
991
992 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
993 shader->vgt_tf_param);
994
995 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
996 }
997
998 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
999 {
1000 struct si_shader *shader = sctx->queued.named.gs->shader;
1001 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1002
1003 if (!shader)
1004 return;
1005
1006 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1007 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1008
1009 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1010 }
1011
1012 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1013 {
1014 struct si_shader *shader = sctx->queued.named.gs->shader;
1015 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1016
1017 if (!shader)
1018 return;
1019
1020 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1021 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1022 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1023 shader->vgt_tf_param);
1024
1025 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1026 }
1027
1028 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1029 {
1030 if (gs->type == PIPE_SHADER_GEOMETRY)
1031 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1032
1033 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1034 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1035 return PIPE_PRIM_POINTS;
1036 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1037 return PIPE_PRIM_LINES;
1038 return PIPE_PRIM_TRIANGLES;
1039 }
1040
1041 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1042 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1043 }
1044
1045 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1046 {
1047 bool misc_vec_ena = sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1048 sel->info.writes_layer || sel->info.writes_viewport_index;
1049 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1050 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1051 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1052 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1053 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1054 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1055 }
1056
1057 /**
1058 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1059 * in NGG mode.
1060 */
1061 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1062 {
1063 const struct si_shader_selector *gs_sel = shader->selector;
1064 const struct si_shader_info *gs_info = &gs_sel->info;
1065 enum pipe_shader_type gs_type = shader->selector->type;
1066 const struct si_shader_selector *es_sel =
1067 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1068 const struct si_shader_info *es_info = &es_sel->info;
1069 enum pipe_shader_type es_type = es_sel->type;
1070 unsigned num_user_sgprs;
1071 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1072 uint64_t va;
1073 unsigned window_space = gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1074 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1075 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1076 unsigned input_prim = si_get_input_prim(gs_sel);
1077 bool break_wave_at_eoi = false;
1078 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1079 if (!pm4)
1080 return;
1081
1082 if (es_type == PIPE_SHADER_TESS_EVAL) {
1083 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1084 : gfx10_emit_shader_ngg_tess_nogs;
1085 } else {
1086 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1087 : gfx10_emit_shader_ngg_notess_nogs;
1088 }
1089
1090 va = shader->bo->gpu_address;
1091 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1092
1093 if (es_type == PIPE_SHADER_VERTEX) {
1094 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1095
1096 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1097 num_user_sgprs =
1098 SI_SGPR_VS_BLIT_DATA + es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1099 } else {
1100 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1101 }
1102 } else {
1103 assert(es_type == PIPE_SHADER_TESS_EVAL);
1104 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1105 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1106
1107 if (es_enable_prim_id || gs_info->uses_primid)
1108 break_wave_at_eoi = true;
1109 }
1110
1111 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1112 * VGPR[0:4] are always loaded.
1113 *
1114 * Vertex shaders always need to load VGPR3, because they need to
1115 * pass edge flags for decomposed primitives (such as quads) to the PA
1116 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1117 */
1118 if (gs_info->uses_invocationid ||
1119 (gs_type == PIPE_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1120 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1121 else if ((gs_type == PIPE_SHADER_GEOMETRY && gs_info->uses_primid) ||
1122 (gs_type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1123 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1124 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1125 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1126 else
1127 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1128
1129 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1130 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1131 si_pm4_set_reg(
1132 pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1133 S_00B228_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1134 S_00B228_FLOAT_MODE(shader->config.float_mode) | S_00B228_DX10_CLAMP(1) |
1135 S_00B228_MEM_ORDERED(1) | S_00B228_WGP_MODE(1) |
1136 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1137 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1138 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1139 S_00B22C_USER_SGPR(num_user_sgprs) |
1140 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1141 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1142 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1143 S_00B22C_LDS_SIZE(shader->config.lds_size));
1144
1145 /* Determine LATE_ALLOC_GS. */
1146 unsigned num_cu_per_sh = sscreen->info.min_good_cu_per_sa;
1147 unsigned late_alloc_wave64; /* The limit is per SA. */
1148
1149 /* For Wave32, the hw will launch twice the number of late
1150 * alloc waves, so 1 == 2x wave32.
1151 *
1152 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1153 */
1154 if (sscreen->info.family == CHIP_NAVI14 || !sscreen->info.use_late_alloc)
1155 late_alloc_wave64 = 0;
1156 else if (num_cu_per_sh <= 6)
1157 late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
1158 else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
1159 late_alloc_wave64 = (num_cu_per_sh - 2) * 6;
1160 else
1161 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
1162
1163 /* Limit LATE_ALLOC_GS for prevent a hang (hw bug). */
1164 if (sscreen->info.chip_class == GFX10)
1165 late_alloc_wave64 = MIN2(late_alloc_wave64, 64);
1166
1167 si_pm4_set_reg(
1168 pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1169 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64));
1170
1171 nparams = MAX2(shader->info.nr_param_exports, 1);
1172 shader->ctx_reg.ngg.spi_vs_out_config =
1173 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1174 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1175
1176 shader->ctx_reg.ngg.spi_shader_idx_format =
1177 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1178 shader->ctx_reg.ngg.spi_shader_pos_format =
1179 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1180 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1181 : V_02870C_SPI_SHADER_NONE) |
1182 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1183 : V_02870C_SPI_SHADER_NONE) |
1184 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1185 : V_02870C_SPI_SHADER_NONE);
1186
1187 shader->ctx_reg.ngg.vgt_primitiveid_en =
1188 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1189 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1190 gs_sel->info.writes_primid);
1191
1192 if (gs_type == PIPE_SHADER_GEOMETRY) {
1193 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1194 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1195 } else {
1196 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1197 }
1198
1199 if (es_type == PIPE_SHADER_TESS_EVAL)
1200 si_set_tesseval_regs(sscreen, es_sel, pm4);
1201
1202 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1203 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1204 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1205 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1206 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1207 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1208 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl = S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1209 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1210 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1211 S_028B90_CNT(gs_num_invocations) | S_028B90_ENABLE(gs_num_invocations > 1) |
1212 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(shader->ngg.max_vert_out_per_gs_instance);
1213
1214 /* Always output hw-generated edge flags and pass them via the prim
1215 * export to prevent drawing lines on internal edges of decomposed
1216 * primitives (such as quads) with polygon mode = lines. Only VS needs
1217 * this.
1218 */
1219 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1220 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX) |
1221 /* Reuse for NGG. */
1222 S_028838_VERTEX_REUSE_DEPTH_GFX103(sscreen->info.chip_class >= GFX10_3 ? 30 : 0);
1223 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1224
1225 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1226 float oversub_pc_factor = 0.25;
1227
1228 if (shader->key.opt.ngg_culling) {
1229 /* Be more aggressive with NGG culling. */
1230 if (shader->info.nr_param_exports > 4)
1231 oversub_pc_factor = 1;
1232 else if (shader->info.nr_param_exports > 2)
1233 oversub_pc_factor = 0.75;
1234 else
1235 oversub_pc_factor = 0.5;
1236 }
1237
1238 unsigned oversub_pc_lines = sscreen->info.pc_lines * oversub_pc_factor;
1239 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
1240 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1241
1242 if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
1243 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1244 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims * 3);
1245 } else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP) {
1246 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1247 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims + 2);
1248 } else {
1249 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1250 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1251 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1252
1253 /* Bug workaround for a possible hang with non-tessellation cases.
1254 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1255 *
1256 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1257 */
1258 if ((sscreen->info.chip_class == GFX10) &&
1259 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1260 shader->ngg.hw_max_esverts != 256) {
1261 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1262
1263 if (shader->ngg.hw_max_esverts > 5) {
1264 shader->ge_cntl |= S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1265 }
1266 }
1267 }
1268
1269 if (window_space) {
1270 shader->ctx_reg.ngg.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1271 } else {
1272 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1273 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1274 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1275 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1276 }
1277 }
1278
1279 static void si_emit_shader_vs(struct si_context *sctx)
1280 {
1281 struct si_shader *shader = sctx->queued.named.vs->shader;
1282 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1283
1284 if (!shader)
1285 return;
1286
1287 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE, SI_TRACKED_VGT_GS_MODE,
1288 shader->ctx_reg.vs.vgt_gs_mode);
1289 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
1290 shader->ctx_reg.vs.vgt_primitiveid_en);
1291
1292 if (sctx->chip_class <= GFX8) {
1293 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
1294 shader->ctx_reg.vs.vgt_reuse_off);
1295 }
1296
1297 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
1298 shader->ctx_reg.vs.spi_vs_out_config);
1299
1300 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1301 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1302 shader->ctx_reg.vs.spi_shader_pos_format);
1303
1304 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1305 shader->ctx_reg.vs.pa_cl_vte_cntl);
1306
1307 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1308 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1309 shader->vgt_tf_param);
1310
1311 if (shader->vgt_vertex_reuse_block_cntl)
1312 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1313 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1314 shader->vgt_vertex_reuse_block_cntl);
1315
1316 /* Required programming for tessellation. (legacy pipeline only) */
1317 if (sctx->chip_class >= GFX10 && shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1318 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1319 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1320 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1321 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1322 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1323 }
1324
1325 if (sctx->chip_class >= GFX10) {
1326 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1327 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, shader->pa_cl_vs_out_cntl,
1328 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1329 }
1330
1331 if (initial_cdw != sctx->gfx_cs->current.cdw)
1332 sctx->context_roll = true;
1333
1334 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1335 if (sctx->chip_class >= GFX10)
1336 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
1337 }
1338
1339 /**
1340 * Compute the state for \p shader, which will run as a vertex shader on the
1341 * hardware.
1342 *
1343 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1344 * is the copy shader.
1345 */
1346 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1347 struct si_shader_selector *gs)
1348 {
1349 const struct si_shader_info *info = &shader->selector->info;
1350 struct si_pm4_state *pm4;
1351 unsigned num_user_sgprs, vgpr_comp_cnt;
1352 uint64_t va;
1353 unsigned nparams, oc_lds_en;
1354 unsigned window_space = info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1355 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1356
1357 pm4 = si_get_shader_pm4_state(shader);
1358 if (!pm4)
1359 return;
1360
1361 pm4->atom.emit = si_emit_shader_vs;
1362
1363 /* We always write VGT_GS_MODE in the VS state, because every switch
1364 * between different shader pipelines involving a different GS or no
1365 * GS at all involves a switch of the VS (different GS use different
1366 * copy shaders). On the other hand, when the API switches from a GS to
1367 * no GS and then back to the same GS used originally, the GS state is
1368 * not sent again.
1369 */
1370 if (!gs) {
1371 unsigned mode = V_028A40_GS_OFF;
1372
1373 /* PrimID needs GS scenario A. */
1374 if (enable_prim_id)
1375 mode = V_028A40_GS_SCENARIO_A;
1376
1377 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1378 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1379 } else {
1380 shader->ctx_reg.vs.vgt_gs_mode =
1381 ac_vgt_gs_mode(gs->gs_max_out_vertices, sscreen->info.chip_class);
1382 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1383 }
1384
1385 if (sscreen->info.chip_class <= GFX8) {
1386 /* Reuse needs to be set off if we write oViewport. */
1387 shader->ctx_reg.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(info->writes_viewport_index);
1388 }
1389
1390 va = shader->bo->gpu_address;
1391 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1392
1393 if (gs) {
1394 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1395 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1396 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1397 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1398
1399 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1400 num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1401 } else {
1402 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1403 }
1404 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1405 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1406 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1407 } else
1408 unreachable("invalid shader selector type");
1409
1410 /* VS is required to export at least one param. */
1411 nparams = MAX2(shader->info.nr_param_exports, 1);
1412 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1413
1414 if (sscreen->info.chip_class >= GFX10) {
1415 shader->ctx_reg.vs.spi_vs_out_config |=
1416 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1417 }
1418
1419 shader->ctx_reg.vs.spi_shader_pos_format =
1420 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1421 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1422 : V_02870C_SPI_SHADER_NONE) |
1423 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1424 : V_02870C_SPI_SHADER_NONE) |
1425 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1426 : V_02870C_SPI_SHADER_NONE);
1427 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
1428 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1429 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1430
1431 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1432
1433 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1434 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1435
1436 uint32_t rsrc1 =
1437 S_00B128_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1438 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B128_DX10_CLAMP(1) |
1439 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1440 S_00B128_FLOAT_MODE(shader->config.float_mode);
1441 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) | S_00B12C_OC_LDS_EN(oc_lds_en) |
1442 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1443
1444 if (sscreen->info.chip_class >= GFX10)
1445 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1446 else if (sscreen->info.chip_class == GFX9)
1447 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1448
1449 if (sscreen->info.chip_class <= GFX9)
1450 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1451
1452 if (!sscreen->use_ngg_streamout) {
1453 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1454 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1455 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1456 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1457 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1458 }
1459
1460 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1461 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1462
1463 if (window_space)
1464 shader->ctx_reg.vs.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1465 else
1466 shader->ctx_reg.vs.pa_cl_vte_cntl =
1467 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1468 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1469 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1470
1471 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1472 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1473
1474 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1475 }
1476
1477 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1478 {
1479 struct si_shader_info *info = &ps->selector->info;
1480 unsigned num_colors = !!(info->colors_read & 0x0f) + !!(info->colors_read & 0xf0);
1481 unsigned num_interp =
1482 ps->selector->info.num_inputs + (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1483
1484 assert(num_interp <= 32);
1485 return MIN2(num_interp, 32);
1486 }
1487
1488 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1489 {
1490 unsigned spi_shader_col_format = shader->key.part.ps.epilog.spi_shader_col_format;
1491 unsigned value = 0, num_mrts = 0;
1492 unsigned i, num_targets = (util_last_bit(spi_shader_col_format) + 3) / 4;
1493
1494 /* Remove holes in spi_shader_col_format. */
1495 for (i = 0; i < num_targets; i++) {
1496 unsigned spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
1497
1498 if (spi_format) {
1499 value |= spi_format << (num_mrts * 4);
1500 num_mrts++;
1501 }
1502 }
1503
1504 return value;
1505 }
1506
1507 static void si_emit_shader_ps(struct si_context *sctx)
1508 {
1509 struct si_shader *shader = sctx->queued.named.ps->shader;
1510 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1511
1512 if (!shader)
1513 return;
1514
1515 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1516 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
1517 shader->ctx_reg.ps.spi_ps_input_ena,
1518 shader->ctx_reg.ps.spi_ps_input_addr);
1519
1520 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
1521 shader->ctx_reg.ps.spi_baryc_cntl);
1522 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
1523 shader->ctx_reg.ps.spi_ps_in_control);
1524
1525 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1526 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
1527 shader->ctx_reg.ps.spi_shader_z_format,
1528 shader->ctx_reg.ps.spi_shader_col_format);
1529
1530 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
1531 shader->ctx_reg.ps.cb_shader_mask);
1532
1533 if (initial_cdw != sctx->gfx_cs->current.cdw)
1534 sctx->context_roll = true;
1535 }
1536
1537 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1538 {
1539 struct si_shader_info *info = &shader->selector->info;
1540 struct si_pm4_state *pm4;
1541 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1542 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1543 uint64_t va;
1544 unsigned input_ena = shader->config.spi_ps_input_ena;
1545
1546 /* we need to enable at least one of them, otherwise we hang the GPU */
1547 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) || G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1548 G_0286CC_PERSP_CENTROID_ENA(input_ena) || G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1549 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) || G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1550 G_0286CC_LINEAR_CENTROID_ENA(input_ena) || G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1551 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1552 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) || G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1553 G_0286CC_PERSP_CENTER_ENA(input_ena) || G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1554 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1555
1556 /* Validate interpolation optimization flags (read as implications). */
1557 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1558 (G_0286CC_PERSP_CENTER_ENA(input_ena) && G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1559 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1560 (G_0286CC_LINEAR_CENTER_ENA(input_ena) && G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1561 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1562 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1563 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1564 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1565 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1566 (!G_0286CC_PERSP_CENTER_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1567 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1568 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1569
1570 /* Validate cases when the optimizations are off (read as implications). */
1571 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1572 !G_0286CC_PERSP_CENTER_ENA(input_ena) || !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1573 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1574 !G_0286CC_LINEAR_CENTER_ENA(input_ena) || !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1575
1576 pm4 = si_get_shader_pm4_state(shader);
1577 if (!pm4)
1578 return;
1579
1580 pm4->atom.emit = si_emit_shader_ps;
1581
1582 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1583 * Possible vaules:
1584 * 0 -> Position = pixel center
1585 * 1 -> Position = pixel centroid
1586 * 2 -> Position = at sample position
1587 *
1588 * From GLSL 4.5 specification, section 7.1:
1589 * "The variable gl_FragCoord is available as an input variable from
1590 * within fragment shaders and it holds the window relative coordinates
1591 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1592 * value can be for any location within the pixel, or one of the
1593 * fragment samples. The use of centroid does not further restrict
1594 * this value to be inside the current primitive."
1595 *
1596 * Meaning that centroid has no effect and we can return anything within
1597 * the pixel. Thus, return the value at sample position, because that's
1598 * the most accurate one shaders can get.
1599 */
1600 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1601
1602 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] == TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1603 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1604
1605 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1606 cb_shader_mask = ac_get_cb_shader_mask(shader->key.part.ps.epilog.spi_shader_col_format);
1607
1608 /* Ensure that some export memory is always allocated, for two reasons:
1609 *
1610 * 1) Correctness: The hardware ignores the EXEC mask if no export
1611 * memory is allocated, so KILL and alpha test do not work correctly
1612 * without this.
1613 * 2) Performance: Every shader needs at least a NULL export, even when
1614 * it writes no color/depth output. The NULL export instruction
1615 * stalls without this setting.
1616 *
1617 * Don't add this to CB_SHADER_MASK.
1618 *
1619 * GFX10 supports pixel shaders without exports by setting both
1620 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1621 * instructions if any are present.
1622 */
1623 if ((sscreen->info.chip_class <= GFX9 || info->uses_kill ||
1624 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1625 !spi_shader_col_format && !info->writes_z && !info->writes_stencil &&
1626 !info->writes_samplemask)
1627 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1628
1629 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1630 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1631
1632 /* Set interpolation controls. */
1633 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1634 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1635
1636 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1637 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1638 shader->ctx_reg.ps.spi_shader_z_format =
1639 ac_get_spi_shader_z_format(info->writes_z, info->writes_stencil, info->writes_samplemask);
1640 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1641 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1642
1643 va = shader->bo->gpu_address;
1644 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1645 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1646 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1647
1648 uint32_t rsrc1 =
1649 S_00B028_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1650 S_00B028_DX10_CLAMP(1) | S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1651 S_00B028_FLOAT_MODE(shader->config.float_mode);
1652
1653 if (sscreen->info.chip_class < GFX10) {
1654 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1655 }
1656
1657 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1658 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1659 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1660 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1661 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1662 }
1663
1664 static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader *shader)
1665 {
1666 switch (shader->selector->type) {
1667 case PIPE_SHADER_VERTEX:
1668 if (shader->key.as_ls)
1669 si_shader_ls(sscreen, shader);
1670 else if (shader->key.as_es)
1671 si_shader_es(sscreen, shader);
1672 else if (shader->key.as_ngg)
1673 gfx10_shader_ngg(sscreen, shader);
1674 else
1675 si_shader_vs(sscreen, shader, NULL);
1676 break;
1677 case PIPE_SHADER_TESS_CTRL:
1678 si_shader_hs(sscreen, shader);
1679 break;
1680 case PIPE_SHADER_TESS_EVAL:
1681 if (shader->key.as_es)
1682 si_shader_es(sscreen, shader);
1683 else if (shader->key.as_ngg)
1684 gfx10_shader_ngg(sscreen, shader);
1685 else
1686 si_shader_vs(sscreen, shader, NULL);
1687 break;
1688 case PIPE_SHADER_GEOMETRY:
1689 if (shader->key.as_ngg)
1690 gfx10_shader_ngg(sscreen, shader);
1691 else
1692 si_shader_gs(sscreen, shader);
1693 break;
1694 case PIPE_SHADER_FRAGMENT:
1695 si_shader_ps(sscreen, shader);
1696 break;
1697 default:
1698 assert(0);
1699 }
1700 }
1701
1702 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1703 {
1704 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1705 return sctx->queued.named.dsa->alpha_func;
1706 }
1707
1708 void si_shader_selector_key_vs(struct si_context *sctx, struct si_shader_selector *vs,
1709 struct si_shader_key *key, struct si_vs_prolog_bits *prolog_key)
1710 {
1711 if (!sctx->vertex_elements || vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1712 return;
1713
1714 struct si_vertex_elements *elts = sctx->vertex_elements;
1715
1716 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1717 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1718 prolog_key->unpack_instance_id_from_vertex_id = sctx->prim_discard_cs_instancing;
1719
1720 /* Prefer a monolithic shader to allow scheduling divisions around
1721 * VBO loads. */
1722 if (prolog_key->instance_divisor_is_fetched)
1723 key->opt.prefer_mono = 1;
1724
1725 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1726 unsigned count_mask = (1 << count) - 1;
1727 unsigned fix = elts->fix_fetch_always & count_mask;
1728 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1729
1730 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1731 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1732 while (mask) {
1733 unsigned i = u_bit_scan(&mask);
1734 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1735 unsigned vbidx = elts->vertex_buffer_index[i];
1736 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1737 unsigned align_mask = (1 << log_hw_load_size) - 1;
1738 if (vb->buffer_offset & align_mask || vb->stride & align_mask) {
1739 fix |= 1 << i;
1740 opencode |= 1 << i;
1741 }
1742 }
1743 }
1744
1745 while (fix) {
1746 unsigned i = u_bit_scan(&fix);
1747 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1748 }
1749 key->mono.vs_fetch_opencode = opencode;
1750 }
1751
1752 static void si_shader_selector_key_hw_vs(struct si_context *sctx, struct si_shader_selector *vs,
1753 struct si_shader_key *key)
1754 {
1755 struct si_shader_selector *ps = sctx->ps_shader.cso;
1756
1757 key->opt.clip_disable = sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1758 (vs->info.clipdist_writemask || vs->info.writes_clipvertex) &&
1759 !vs->info.culldist_writemask;
1760
1761 /* Find out if PS is disabled. */
1762 bool ps_disabled = true;
1763 if (ps) {
1764 bool ps_modifies_zs = ps->info.uses_kill || ps->info.writes_z || ps->info.writes_stencil ||
1765 ps->info.writes_samplemask ||
1766 sctx->queued.named.blend->alpha_to_coverage ||
1767 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1768 unsigned ps_colormask = si_get_total_colormask(sctx);
1769
1770 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1771 (!ps_colormask && !ps_modifies_zs && !ps->info.writes_memory);
1772 }
1773
1774 /* Find out which VS outputs aren't used by the PS. */
1775 uint64_t outputs_written = vs->outputs_written_before_ps;
1776 uint64_t inputs_read = 0;
1777
1778 /* Ignore outputs that are not passed from VS to PS. */
1779 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1780 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1781 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1782
1783 if (!ps_disabled) {
1784 inputs_read = ps->inputs_read;
1785 }
1786
1787 uint64_t linked = outputs_written & inputs_read;
1788
1789 key->opt.kill_outputs = ~linked & outputs_written;
1790 key->opt.ngg_culling = sctx->ngg_culling;
1791 }
1792
1793 /* Compute the key for the hw shader variant */
1794 static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_shader_selector *sel,
1795 union si_vgt_stages_key stages_key,
1796 struct si_shader_key *key)
1797 {
1798 struct si_context *sctx = (struct si_context *)ctx;
1799
1800 memset(key, 0, sizeof(*key));
1801
1802 switch (sel->type) {
1803 case PIPE_SHADER_VERTEX:
1804 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1805
1806 if (sctx->tes_shader.cso)
1807 key->as_ls = 1;
1808 else if (sctx->gs_shader.cso) {
1809 key->as_es = 1;
1810 key->as_ngg = stages_key.u.ngg;
1811 } else {
1812 key->as_ngg = stages_key.u.ngg;
1813 si_shader_selector_key_hw_vs(sctx, sel, key);
1814
1815 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1816 key->mono.u.vs_export_prim_id = 1;
1817 }
1818 break;
1819 case PIPE_SHADER_TESS_CTRL:
1820 if (sctx->chip_class >= GFX9) {
1821 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.tcs.ls_prolog);
1822 key->part.tcs.ls = sctx->vs_shader.cso;
1823
1824 /* When the LS VGPR fix is needed, monolithic shaders
1825 * can:
1826 * - avoid initializing EXEC in both the LS prolog
1827 * and the LS main part when !vs_needs_prolog
1828 * - remove the fixup for unused input VGPRs
1829 */
1830 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1831
1832 /* The LS output / HS input layout can be communicated
1833 * directly instead of via user SGPRs for merged LS-HS.
1834 * The LS VGPR fix prefers this too.
1835 */
1836 key->opt.prefer_mono = 1;
1837 }
1838
1839 key->part.tcs.epilog.prim_mode =
1840 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1841 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1842 sel->info.tessfactors_are_def_in_all_invocs;
1843 key->part.tcs.epilog.tes_reads_tess_factors = sctx->tes_shader.cso->info.reads_tess_factors;
1844
1845 if (sel == sctx->fixed_func_tcs_shader.cso)
1846 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1847 break;
1848 case PIPE_SHADER_TESS_EVAL:
1849 key->as_ngg = stages_key.u.ngg;
1850
1851 if (sctx->gs_shader.cso)
1852 key->as_es = 1;
1853 else {
1854 si_shader_selector_key_hw_vs(sctx, sel, key);
1855
1856 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1857 key->mono.u.vs_export_prim_id = 1;
1858 }
1859 break;
1860 case PIPE_SHADER_GEOMETRY:
1861 if (sctx->chip_class >= GFX9) {
1862 if (sctx->tes_shader.cso) {
1863 key->part.gs.es = sctx->tes_shader.cso;
1864 } else {
1865 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.gs.vs_prolog);
1866 key->part.gs.es = sctx->vs_shader.cso;
1867 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1868 }
1869
1870 key->as_ngg = stages_key.u.ngg;
1871
1872 /* Merged ES-GS can have unbalanced wave usage.
1873 *
1874 * ES threads are per-vertex, while GS threads are
1875 * per-primitive. So without any amplification, there
1876 * are fewer GS threads than ES threads, which can result
1877 * in empty (no-op) GS waves. With too much amplification,
1878 * there are more GS threads than ES threads, which
1879 * can result in empty (no-op) ES waves.
1880 *
1881 * Non-monolithic shaders are implemented by setting EXEC
1882 * at the beginning of shader parts, and don't jump to
1883 * the end if EXEC is 0.
1884 *
1885 * Monolithic shaders use conditional blocks, so they can
1886 * jump and skip empty waves of ES or GS. So set this to
1887 * always use optimized variants, which are monolithic.
1888 */
1889 key->opt.prefer_mono = 1;
1890 }
1891 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1892 break;
1893 case PIPE_SHADER_FRAGMENT: {
1894 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1895 struct si_state_blend *blend = sctx->queued.named.blend;
1896
1897 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1898 sel->info.colors_written == 0x1)
1899 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1900
1901 /* Select the shader color format based on whether
1902 * blending or alpha are needed.
1903 */
1904 key->part.ps.epilog.spi_shader_col_format =
1905 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1906 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1907 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1908 sctx->framebuffer.spi_shader_col_format_blend) |
1909 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1910 sctx->framebuffer.spi_shader_col_format_alpha) |
1911 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1912 sctx->framebuffer.spi_shader_col_format);
1913 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1914
1915 /* The output for dual source blending should have
1916 * the same format as the first output.
1917 */
1918 if (blend->dual_src_blend) {
1919 key->part.ps.epilog.spi_shader_col_format |=
1920 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1921 }
1922
1923 /* If alpha-to-coverage is enabled, we have to export alpha
1924 * even if there is no color buffer.
1925 */
1926 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) && blend->alpha_to_coverage)
1927 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1928
1929 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1930 * to the range supported by the type if a channel has less
1931 * than 16 bits and the export format is 16_ABGR.
1932 */
1933 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1934 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1935 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1936 }
1937
1938 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1939 if (!key->part.ps.epilog.last_cbuf) {
1940 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1941 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1942 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1943 }
1944
1945 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1946 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1947
1948 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1949 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1950
1951 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one && rs->multisample_enable;
1952
1953 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1954 key->part.ps.epilog.poly_line_smoothing =
1955 ((is_poly && rs->poly_smooth) || (is_line && rs->line_smooth)) &&
1956 sctx->framebuffer.nr_samples <= 1;
1957 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1958
1959 if (sctx->ps_iter_samples > 1 && sel->info.reads_samplemask) {
1960 key->part.ps.prolog.samplemask_log_ps_iter = util_logbase2(sctx->ps_iter_samples);
1961 }
1962
1963 if (rs->force_persample_interp && rs->multisample_enable &&
1964 sctx->framebuffer.nr_samples > 1 && sctx->ps_iter_samples > 1) {
1965 key->part.ps.prolog.force_persp_sample_interp =
1966 sel->info.uses_persp_center || sel->info.uses_persp_centroid;
1967
1968 key->part.ps.prolog.force_linear_sample_interp =
1969 sel->info.uses_linear_center || sel->info.uses_linear_centroid;
1970 } else if (rs->multisample_enable && sctx->framebuffer.nr_samples > 1) {
1971 key->part.ps.prolog.bc_optimize_for_persp =
1972 sel->info.uses_persp_center && sel->info.uses_persp_centroid;
1973 key->part.ps.prolog.bc_optimize_for_linear =
1974 sel->info.uses_linear_center && sel->info.uses_linear_centroid;
1975 } else {
1976 /* Make sure SPI doesn't compute more than 1 pair
1977 * of (i,j), which is the optimization here. */
1978 key->part.ps.prolog.force_persp_center_interp = sel->info.uses_persp_center +
1979 sel->info.uses_persp_centroid +
1980 sel->info.uses_persp_sample >
1981 1;
1982
1983 key->part.ps.prolog.force_linear_center_interp = sel->info.uses_linear_center +
1984 sel->info.uses_linear_centroid +
1985 sel->info.uses_linear_sample >
1986 1;
1987
1988 if (sel->info.uses_persp_opcode_interp_sample ||
1989 sel->info.uses_linear_opcode_interp_sample)
1990 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1991 }
1992
1993 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1994
1995 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1996 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1997 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1998 struct pipe_resource *tex = cb0->texture;
1999
2000 /* 1D textures are allocated and used as 2D on GFX9. */
2001 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2002 key->mono.u.ps.fbfetch_is_1D =
2003 sctx->chip_class != GFX9 &&
2004 (tex->target == PIPE_TEXTURE_1D || tex->target == PIPE_TEXTURE_1D_ARRAY);
2005 key->mono.u.ps.fbfetch_layered =
2006 tex->target == PIPE_TEXTURE_1D_ARRAY || tex->target == PIPE_TEXTURE_2D_ARRAY ||
2007 tex->target == PIPE_TEXTURE_CUBE || tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2008 tex->target == PIPE_TEXTURE_3D;
2009 }
2010 break;
2011 }
2012 default:
2013 assert(0);
2014 }
2015
2016 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2017 memset(&key->opt, 0, sizeof(key->opt));
2018 }
2019
2020 static void si_build_shader_variant(struct si_shader *shader, int thread_index, bool low_priority)
2021 {
2022 struct si_shader_selector *sel = shader->selector;
2023 struct si_screen *sscreen = sel->screen;
2024 struct ac_llvm_compiler *compiler;
2025 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2026
2027 if (thread_index >= 0) {
2028 if (low_priority) {
2029 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2030 compiler = &sscreen->compiler_lowp[thread_index];
2031 } else {
2032 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2033 compiler = &sscreen->compiler[thread_index];
2034 }
2035 if (!debug->async)
2036 debug = NULL;
2037 } else {
2038 assert(!low_priority);
2039 compiler = shader->compiler_ctx_state.compiler;
2040 }
2041
2042 if (!compiler->passes)
2043 si_init_compiler(sscreen, compiler);
2044
2045 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2046 PRINT_ERR("Failed to build shader variant (type=%u)\n", sel->type);
2047 shader->compilation_failed = true;
2048 return;
2049 }
2050
2051 if (shader->compiler_ctx_state.is_debug_context) {
2052 FILE *f = open_memstream(&shader->shader_log, &shader->shader_log_size);
2053 if (f) {
2054 si_shader_dump(sscreen, shader, NULL, f, false);
2055 fclose(f);
2056 }
2057 }
2058
2059 si_shader_init_pm4_state(sscreen, shader);
2060 }
2061
2062 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2063 {
2064 struct si_shader *shader = (struct si_shader *)job;
2065
2066 assert(thread_index >= 0);
2067
2068 si_build_shader_variant(shader, thread_index, true);
2069 }
2070
2071 static const struct si_shader_key zeroed;
2072
2073 static bool si_check_missing_main_part(struct si_screen *sscreen, struct si_shader_selector *sel,
2074 struct si_compiler_ctx_state *compiler_state,
2075 struct si_shader_key *key)
2076 {
2077 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2078
2079 if (!*mainp) {
2080 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2081
2082 if (!main_part)
2083 return false;
2084
2085 /* We can leave the fence as permanently signaled because the
2086 * main part becomes visible globally only after it has been
2087 * compiled. */
2088 util_queue_fence_init(&main_part->ready);
2089
2090 main_part->selector = sel;
2091 main_part->key.as_es = key->as_es;
2092 main_part->key.as_ls = key->as_ls;
2093 main_part->key.as_ngg = key->as_ngg;
2094 main_part->is_monolithic = false;
2095
2096 if (!si_compile_shader(sscreen, compiler_state->compiler, main_part,
2097 &compiler_state->debug)) {
2098 FREE(main_part);
2099 return false;
2100 }
2101 *mainp = main_part;
2102 }
2103 return true;
2104 }
2105
2106 /**
2107 * Select a shader variant according to the shader key.
2108 *
2109 * \param optimized_or_none If the key describes an optimized shader variant and
2110 * the compilation isn't finished, don't select any
2111 * shader and return an error.
2112 */
2113 int si_shader_select_with_key(struct si_screen *sscreen, struct si_shader_ctx_state *state,
2114 struct si_compiler_ctx_state *compiler_state,
2115 struct si_shader_key *key, int thread_index, bool optimized_or_none)
2116 {
2117 struct si_shader_selector *sel = state->cso;
2118 struct si_shader_selector *previous_stage_sel = NULL;
2119 struct si_shader *current = state->current;
2120 struct si_shader *iter, *shader = NULL;
2121
2122 again:
2123 /* Check if we don't need to change anything.
2124 * This path is also used for most shaders that don't need multiple
2125 * variants, it will cost just a computation of the key and this
2126 * test. */
2127 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0)) {
2128 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2129 if (current->is_optimized) {
2130 if (optimized_or_none)
2131 return -1;
2132
2133 memset(&key->opt, 0, sizeof(key->opt));
2134 goto current_not_ready;
2135 }
2136
2137 util_queue_fence_wait(&current->ready);
2138 }
2139
2140 return current->compilation_failed ? -1 : 0;
2141 }
2142 current_not_ready:
2143
2144 /* This must be done before the mutex is locked, because async GS
2145 * compilation calls this function too, and therefore must enter
2146 * the mutex first.
2147 *
2148 * Only wait if we are in a draw call. Don't wait if we are
2149 * in a compiler thread.
2150 */
2151 if (thread_index < 0)
2152 util_queue_fence_wait(&sel->ready);
2153
2154 simple_mtx_lock(&sel->mutex);
2155
2156 /* Find the shader variant. */
2157 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2158 /* Don't check the "current" shader. We checked it above. */
2159 if (current != iter && memcmp(&iter->key, key, sizeof(*key)) == 0) {
2160 simple_mtx_unlock(&sel->mutex);
2161
2162 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2163 /* If it's an optimized shader and its compilation has
2164 * been started but isn't done, use the unoptimized
2165 * shader so as not to cause a stall due to compilation.
2166 */
2167 if (iter->is_optimized) {
2168 if (optimized_or_none)
2169 return -1;
2170 memset(&key->opt, 0, sizeof(key->opt));
2171 goto again;
2172 }
2173
2174 util_queue_fence_wait(&iter->ready);
2175 }
2176
2177 if (iter->compilation_failed) {
2178 return -1; /* skip the draw call */
2179 }
2180
2181 state->current = iter;
2182 return 0;
2183 }
2184 }
2185
2186 /* Build a new shader. */
2187 shader = CALLOC_STRUCT(si_shader);
2188 if (!shader) {
2189 simple_mtx_unlock(&sel->mutex);
2190 return -ENOMEM;
2191 }
2192
2193 util_queue_fence_init(&shader->ready);
2194
2195 shader->selector = sel;
2196 shader->key = *key;
2197 shader->compiler_ctx_state = *compiler_state;
2198
2199 /* If this is a merged shader, get the first shader's selector. */
2200 if (sscreen->info.chip_class >= GFX9) {
2201 if (sel->type == PIPE_SHADER_TESS_CTRL)
2202 previous_stage_sel = key->part.tcs.ls;
2203 else if (sel->type == PIPE_SHADER_GEOMETRY)
2204 previous_stage_sel = key->part.gs.es;
2205
2206 /* We need to wait for the previous shader. */
2207 if (previous_stage_sel && thread_index < 0)
2208 util_queue_fence_wait(&previous_stage_sel->ready);
2209 }
2210
2211 bool is_pure_monolithic =
2212 sscreen->use_monolithic_shaders || memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2213
2214 /* Compile the main shader part if it doesn't exist. This can happen
2215 * if the initial guess was wrong.
2216 *
2217 * The prim discard CS doesn't need the main shader part.
2218 */
2219 if (!is_pure_monolithic && !key->opt.vs_as_prim_discard_cs) {
2220 bool ok = true;
2221
2222 /* Make sure the main shader part is present. This is needed
2223 * for shaders that can be compiled as VS, LS, or ES, and only
2224 * one of them is compiled at creation.
2225 *
2226 * It is also needed for GS, which can be compiled as non-NGG
2227 * and NGG.
2228 *
2229 * For merged shaders, check that the starting shader's main
2230 * part is present.
2231 */
2232 if (previous_stage_sel) {
2233 struct si_shader_key shader1_key = zeroed;
2234
2235 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2236 shader1_key.as_ls = 1;
2237 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2238 shader1_key.as_es = 1;
2239 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2240 } else {
2241 assert(0);
2242 }
2243
2244 simple_mtx_lock(&previous_stage_sel->mutex);
2245 ok = si_check_missing_main_part(sscreen, previous_stage_sel, compiler_state, &shader1_key);
2246 simple_mtx_unlock(&previous_stage_sel->mutex);
2247 }
2248
2249 if (ok) {
2250 ok = si_check_missing_main_part(sscreen, sel, compiler_state, key);
2251 }
2252
2253 if (!ok) {
2254 FREE(shader);
2255 simple_mtx_unlock(&sel->mutex);
2256 return -ENOMEM; /* skip the draw call */
2257 }
2258 }
2259
2260 /* Keep the reference to the 1st shader of merged shaders, so that
2261 * Gallium can't destroy it before we destroy the 2nd shader.
2262 *
2263 * Set sctx = NULL, because it's unused if we're not releasing
2264 * the shader, and we don't have any sctx here.
2265 */
2266 si_shader_selector_reference(NULL, &shader->previous_stage_sel, previous_stage_sel);
2267
2268 /* Monolithic-only shaders don't make a distinction between optimized
2269 * and unoptimized. */
2270 shader->is_monolithic =
2271 is_pure_monolithic || memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2272
2273 /* The prim discard CS is always optimized. */
2274 shader->is_optimized = (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2275 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2276
2277 /* If it's an optimized shader, compile it asynchronously. */
2278 if (shader->is_optimized && thread_index < 0) {
2279 /* Compile it asynchronously. */
2280 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority, shader, &shader->ready,
2281 si_build_shader_variant_low_priority, NULL, 0);
2282
2283 /* Add only after the ready fence was reset, to guard against a
2284 * race with si_bind_XX_shader. */
2285 if (!sel->last_variant) {
2286 sel->first_variant = shader;
2287 sel->last_variant = shader;
2288 } else {
2289 sel->last_variant->next_variant = shader;
2290 sel->last_variant = shader;
2291 }
2292
2293 /* Use the default (unoptimized) shader for now. */
2294 memset(&key->opt, 0, sizeof(key->opt));
2295 simple_mtx_unlock(&sel->mutex);
2296
2297 if (sscreen->options.sync_compile)
2298 util_queue_fence_wait(&shader->ready);
2299
2300 if (optimized_or_none)
2301 return -1;
2302 goto again;
2303 }
2304
2305 /* Reset the fence before adding to the variant list. */
2306 util_queue_fence_reset(&shader->ready);
2307
2308 if (!sel->last_variant) {
2309 sel->first_variant = shader;
2310 sel->last_variant = shader;
2311 } else {
2312 sel->last_variant->next_variant = shader;
2313 sel->last_variant = shader;
2314 }
2315
2316 simple_mtx_unlock(&sel->mutex);
2317
2318 assert(!shader->is_optimized);
2319 si_build_shader_variant(shader, thread_index, false);
2320
2321 util_queue_fence_signal(&shader->ready);
2322
2323 if (!shader->compilation_failed)
2324 state->current = shader;
2325
2326 return shader->compilation_failed ? -1 : 0;
2327 }
2328
2329 static int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state,
2330 union si_vgt_stages_key stages_key,
2331 struct si_compiler_ctx_state *compiler_state)
2332 {
2333 struct si_context *sctx = (struct si_context *)ctx;
2334 struct si_shader_key key;
2335
2336 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2337 return si_shader_select_with_key(sctx->screen, state, compiler_state, &key, -1, false);
2338 }
2339
2340 static void si_parse_next_shader_property(const struct si_shader_info *info, bool streamout,
2341 struct si_shader_key *key)
2342 {
2343 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2344
2345 switch (info->processor) {
2346 case PIPE_SHADER_VERTEX:
2347 switch (next_shader) {
2348 case PIPE_SHADER_GEOMETRY:
2349 key->as_es = 1;
2350 break;
2351 case PIPE_SHADER_TESS_CTRL:
2352 case PIPE_SHADER_TESS_EVAL:
2353 key->as_ls = 1;
2354 break;
2355 default:
2356 /* If POSITION isn't written, it can only be a HW VS
2357 * if streamout is used. If streamout isn't used,
2358 * assume that it's a HW LS. (the next shader is TCS)
2359 * This heuristic is needed for separate shader objects.
2360 */
2361 if (!info->writes_position && !streamout)
2362 key->as_ls = 1;
2363 }
2364 break;
2365
2366 case PIPE_SHADER_TESS_EVAL:
2367 if (next_shader == PIPE_SHADER_GEOMETRY || !info->writes_position)
2368 key->as_es = 1;
2369 break;
2370 }
2371 }
2372
2373 /**
2374 * Compile the main shader part or the monolithic shader as part of
2375 * si_shader_selector initialization. Since it can be done asynchronously,
2376 * there is no way to report compile failures to applications.
2377 */
2378 static void si_init_shader_selector_async(void *job, int thread_index)
2379 {
2380 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2381 struct si_screen *sscreen = sel->screen;
2382 struct ac_llvm_compiler *compiler;
2383 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2384
2385 assert(!debug->debug_message || debug->async);
2386 assert(thread_index >= 0);
2387 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2388 compiler = &sscreen->compiler[thread_index];
2389
2390 if (!compiler->passes)
2391 si_init_compiler(sscreen, compiler);
2392
2393 /* Serialize NIR to save memory. Monolithic shader variants
2394 * have to deserialize NIR before compilation.
2395 */
2396 if (sel->nir) {
2397 struct blob blob;
2398 size_t size;
2399
2400 blob_init(&blob);
2401 /* true = remove optional debugging data to increase
2402 * the likehood of getting more shader cache hits.
2403 * It also drops variable names, so we'll save more memory.
2404 */
2405 nir_serialize(&blob, sel->nir, true);
2406 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2407 sel->nir_size = size;
2408 }
2409
2410 /* Compile the main shader part for use with a prolog and/or epilog.
2411 * If this fails, the driver will try to compile a monolithic shader
2412 * on demand.
2413 */
2414 if (!sscreen->use_monolithic_shaders) {
2415 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2416 unsigned char ir_sha1_cache_key[20];
2417
2418 if (!shader) {
2419 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2420 return;
2421 }
2422
2423 /* We can leave the fence signaled because use of the default
2424 * main part is guarded by the selector's ready fence. */
2425 util_queue_fence_init(&shader->ready);
2426
2427 shader->selector = sel;
2428 shader->is_monolithic = false;
2429 si_parse_next_shader_property(&sel->info, sel->so.num_outputs != 0, &shader->key);
2430
2431 if (sscreen->use_ngg && (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2432 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2433 sel->type == PIPE_SHADER_TESS_EVAL || sel->type == PIPE_SHADER_GEOMETRY))
2434 shader->key.as_ngg = 1;
2435
2436 if (sel->nir) {
2437 si_get_ir_cache_key(sel, shader->key.as_ngg, shader->key.as_es, ir_sha1_cache_key);
2438 }
2439
2440 /* Try to load the shader from the shader cache. */
2441 simple_mtx_lock(&sscreen->shader_cache_mutex);
2442
2443 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2444 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2445 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2446 } else {
2447 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2448
2449 /* Compile the shader if it hasn't been loaded from the cache. */
2450 if (!si_compile_shader(sscreen, compiler, shader, debug)) {
2451 FREE(shader);
2452 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2453 return;
2454 }
2455
2456 simple_mtx_lock(&sscreen->shader_cache_mutex);
2457 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
2458 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2459 }
2460
2461 *si_get_main_shader_part(sel, &shader->key) = shader;
2462
2463 /* Unset "outputs_written" flags for outputs converted to
2464 * DEFAULT_VAL, so that later inter-shader optimizations don't
2465 * try to eliminate outputs that don't exist in the final
2466 * shader.
2467 *
2468 * This is only done if non-monolithic shaders are enabled.
2469 */
2470 if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_TESS_EVAL) &&
2471 !shader->key.as_ls && !shader->key.as_es) {
2472 unsigned i;
2473
2474 for (i = 0; i < sel->info.num_outputs; i++) {
2475 unsigned offset = shader->info.vs_output_param_offset[i];
2476
2477 if (offset <= AC_EXP_PARAM_OFFSET_31)
2478 continue;
2479
2480 unsigned name = sel->info.output_semantic_name[i];
2481 unsigned index = sel->info.output_semantic_index[i];
2482 unsigned id;
2483
2484 switch (name) {
2485 case TGSI_SEMANTIC_GENERIC:
2486 /* don't process indices the function can't handle */
2487 if (index >= SI_MAX_IO_GENERIC)
2488 break;
2489 /* fall through */
2490 default:
2491 id = si_shader_io_get_unique_index(name, index, true);
2492 sel->outputs_written_before_ps &= ~(1ull << id);
2493 break;
2494 case TGSI_SEMANTIC_POSITION: /* ignore these */
2495 case TGSI_SEMANTIC_PSIZE:
2496 case TGSI_SEMANTIC_CLIPVERTEX:
2497 case TGSI_SEMANTIC_EDGEFLAG:
2498 break;
2499 }
2500 }
2501 }
2502 }
2503
2504 /* The GS copy shader is always pre-compiled. */
2505 if (sel->type == PIPE_SHADER_GEOMETRY &&
2506 (!sscreen->use_ngg || !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2507 sel->tess_turns_off_ngg)) {
2508 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2509 if (!sel->gs_copy_shader) {
2510 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2511 return;
2512 }
2513
2514 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2515 }
2516
2517 /* Free NIR. We only keep serialized NIR after this point. */
2518 if (sel->nir) {
2519 ralloc_free(sel->nir);
2520 sel->nir = NULL;
2521 }
2522 }
2523
2524 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2525 struct util_queue_fence *ready_fence,
2526 struct si_compiler_ctx_state *compiler_ctx_state, void *job,
2527 util_queue_execute_func execute)
2528 {
2529 util_queue_fence_init(ready_fence);
2530
2531 struct util_async_debug_callback async_debug;
2532 bool debug = (sctx->debug.debug_message && !sctx->debug.async) || sctx->is_debug ||
2533 si_can_dump_shader(sctx->screen, processor);
2534
2535 if (debug) {
2536 u_async_debug_init(&async_debug);
2537 compiler_ctx_state->debug = async_debug.base;
2538 }
2539
2540 util_queue_add_job(&sctx->screen->shader_compiler_queue, job, ready_fence, execute, NULL, 0);
2541
2542 if (debug) {
2543 util_queue_fence_wait(ready_fence);
2544 u_async_debug_drain(&async_debug, &sctx->debug);
2545 u_async_debug_cleanup(&async_debug);
2546 }
2547
2548 if (sctx->screen->options.sync_compile)
2549 util_queue_fence_wait(ready_fence);
2550 }
2551
2552 /* Return descriptor slot usage masks from the given shader info. */
2553 void si_get_active_slot_masks(const struct si_shader_info *info, uint32_t *const_and_shader_buffers,
2554 uint64_t *samplers_and_images)
2555 {
2556 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2557
2558 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2559 num_constbufs = util_last_bit(info->const_buffers_declared);
2560 /* two 8-byte images share one 16-byte slot */
2561 num_images = align(util_last_bit(info->images_declared), 2);
2562 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2563 num_samplers = util_last_bit(info->samplers_declared);
2564
2565 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2566 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2567 *const_and_shader_buffers = u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2568
2569 /* The layout is:
2570 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2571 * - image[last] ... image[0] go to [31-last .. 31]
2572 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2573 *
2574 * FMASKs for images are placed separately, because MSAA images are rare,
2575 * and so we can benefit from a better cache hit rate if we keep image
2576 * descriptors together.
2577 */
2578 if (num_msaa_images)
2579 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2580
2581 start = si_get_image_slot(num_images - 1) / 2;
2582 *samplers_and_images = u_bit_consecutive64(start, num_images / 2 + num_samplers);
2583 }
2584
2585 static void *si_create_shader_selector(struct pipe_context *ctx,
2586 const struct pipe_shader_state *state)
2587 {
2588 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2589 struct si_context *sctx = (struct si_context *)ctx;
2590 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2591 int i;
2592
2593 if (!sel)
2594 return NULL;
2595
2596 sel->screen = sscreen;
2597 sel->compiler_ctx_state.debug = sctx->debug;
2598 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2599
2600 sel->so = state->stream_output;
2601
2602 if (state->type == PIPE_SHADER_IR_TGSI) {
2603 sel->nir = tgsi_to_nir(state->tokens, ctx->screen, true);
2604 } else {
2605 assert(state->type == PIPE_SHADER_IR_NIR);
2606 sel->nir = state->ir.nir;
2607 }
2608
2609 si_nir_scan_shader(sel->nir, &sel->info);
2610 si_nir_adjust_driver_locations(sel->nir);
2611
2612 sel->type = sel->info.processor;
2613 p_atomic_inc(&sscreen->num_shaders_created);
2614 si_get_active_slot_masks(&sel->info, &sel->active_const_and_shader_buffers,
2615 &sel->active_samplers_and_images);
2616
2617 /* Record which streamout buffers are enabled. */
2618 for (i = 0; i < sel->so.num_outputs; i++) {
2619 sel->enabled_streamout_buffer_mask |= (1 << sel->so.output[i].output_buffer)
2620 << (sel->so.output[i].stream * 4);
2621 }
2622
2623 sel->num_vs_inputs =
2624 sel->type == PIPE_SHADER_VERTEX && !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]
2625 ? sel->info.num_inputs
2626 : 0;
2627 sel->num_vbos_in_user_sgprs = MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2628
2629 /* The prolog is a no-op if there are no inputs. */
2630 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX && sel->info.num_inputs &&
2631 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2632
2633 sel->prim_discard_cs_allowed =
2634 sel->type == PIPE_SHADER_VERTEX && !sel->info.uses_bindless_images &&
2635 !sel->info.uses_bindless_samplers && !sel->info.writes_memory &&
2636 !sel->info.writes_viewport_index &&
2637 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] && !sel->so.num_outputs;
2638
2639 switch (sel->type) {
2640 case PIPE_SHADER_GEOMETRY:
2641 sel->gs_output_prim = sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2642
2643 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2644 sel->rast_prim = sel->gs_output_prim;
2645 if (util_rast_prim_is_triangles(sel->rast_prim))
2646 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2647
2648 sel->gs_max_out_vertices = sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2649 sel->gs_num_invocations = sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2650 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2651 sel->max_gsvs_emit_size = sel->gsvs_vertex_size * sel->gs_max_out_vertices;
2652
2653 sel->max_gs_stream = 0;
2654 for (i = 0; i < sel->so.num_outputs; i++)
2655 sel->max_gs_stream = MAX2(sel->max_gs_stream, sel->so.output[i].stream);
2656
2657 sel->gs_input_verts_per_prim =
2658 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2659
2660 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2661 sel->tess_turns_off_ngg = sscreen->info.chip_class >= GFX10 &&
2662 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2663 break;
2664
2665 case PIPE_SHADER_TESS_CTRL:
2666 /* Always reserve space for these. */
2667 sel->patch_outputs_written |=
2668 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2669 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2670 /* fall through */
2671 case PIPE_SHADER_VERTEX:
2672 case PIPE_SHADER_TESS_EVAL:
2673 for (i = 0; i < sel->info.num_outputs; i++) {
2674 unsigned name = sel->info.output_semantic_name[i];
2675 unsigned index = sel->info.output_semantic_index[i];
2676
2677 switch (name) {
2678 case TGSI_SEMANTIC_TESSINNER:
2679 case TGSI_SEMANTIC_TESSOUTER:
2680 case TGSI_SEMANTIC_PATCH:
2681 sel->patch_outputs_written |= 1ull << si_shader_io_get_unique_index_patch(name, index);
2682 break;
2683
2684 case TGSI_SEMANTIC_GENERIC:
2685 /* don't process indices the function can't handle */
2686 if (index >= SI_MAX_IO_GENERIC)
2687 break;
2688 /* fall through */
2689 default:
2690 sel->outputs_written |= 1ull << si_shader_io_get_unique_index(name, index, false);
2691 sel->outputs_written_before_ps |= 1ull
2692 << si_shader_io_get_unique_index(name, index, true);
2693 break;
2694 case TGSI_SEMANTIC_EDGEFLAG:
2695 break;
2696 }
2697 }
2698 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2699 sel->lshs_vertex_stride = sel->esgs_itemsize;
2700
2701 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2702 * will start on a different bank. (except for the maximum 32*16).
2703 */
2704 if (sel->lshs_vertex_stride < 32 * 16)
2705 sel->lshs_vertex_stride += 4;
2706
2707 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2708 * conflicts, i.e. each vertex will start at a different bank.
2709 */
2710 if (sctx->chip_class >= GFX9)
2711 sel->esgs_itemsize += 4;
2712
2713 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2714
2715 /* Only for TES: */
2716 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2717 sel->rast_prim = PIPE_PRIM_POINTS;
2718 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2719 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2720 else
2721 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2722 break;
2723
2724 case PIPE_SHADER_FRAGMENT:
2725 for (i = 0; i < sel->info.num_inputs; i++) {
2726 unsigned name = sel->info.input_semantic_name[i];
2727 unsigned index = sel->info.input_semantic_index[i];
2728
2729 switch (name) {
2730 case TGSI_SEMANTIC_GENERIC:
2731 /* don't process indices the function can't handle */
2732 if (index >= SI_MAX_IO_GENERIC)
2733 break;
2734 /* fall through */
2735 default:
2736 sel->inputs_read |= 1ull << si_shader_io_get_unique_index(name, index, true);
2737 break;
2738 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2739 break;
2740 }
2741 }
2742
2743 for (i = 0; i < 8; i++)
2744 if (sel->info.colors_written & (1 << i))
2745 sel->colors_written_4bit |= 0xf << (4 * i);
2746
2747 for (i = 0; i < sel->info.num_inputs; i++) {
2748 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2749 int index = sel->info.input_semantic_index[i];
2750 sel->color_attr_index[index] = i;
2751 }
2752 }
2753 break;
2754 default:;
2755 }
2756
2757 sel->ngg_culling_allowed =
2758 sscreen->info.chip_class >= GFX10 &&
2759 sscreen->info.has_dedicated_vram &&
2760 sscreen->use_ngg_culling &&
2761 /* Disallow TES by default, because TessMark results are mixed. */
2762 (sel->type == PIPE_SHADER_VERTEX ||
2763 (sscreen->always_use_ngg_culling && sel->type == PIPE_SHADER_TESS_EVAL)) &&
2764 sel->info.writes_position &&
2765 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
2766 !sel->info.writes_memory && !sel->so.num_outputs &&
2767 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] &&
2768 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2769
2770 /* PA_CL_VS_OUT_CNTL */
2771 if (sctx->chip_class <= GFX9)
2772 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2773
2774 sel->clipdist_mask = sel->info.writes_clipvertex ? SIX_BITS : sel->info.clipdist_writemask;
2775 sel->culldist_mask = sel->info.culldist_writemask << sel->info.num_written_clipdistance;
2776
2777 /* DB_SHADER_CONTROL */
2778 sel->db_shader_control = S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2779 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2780 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2781 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2782
2783 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2784 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2785 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2786 break;
2787 case TGSI_FS_DEPTH_LAYOUT_LESS:
2788 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2789 break;
2790 }
2791
2792 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2793 *
2794 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2795 * --|-----------|------------|------------|--------------------|-------------------|-------------
2796 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2797 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2798 * 2 | false | true | n/a | LateZ | 1 | 0
2799 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2800 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2801 *
2802 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2803 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2804 *
2805 * Don't use ReZ without profiling !!!
2806 *
2807 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2808 * shaders.
2809 */
2810 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2811 /* Cases 3, 4. */
2812 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2813 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2814 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2815 } else if (sel->info.writes_memory) {
2816 /* Case 2. */
2817 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) | S_02880C_EXEC_ON_HIER_FAIL(1);
2818 } else {
2819 /* Case 1. */
2820 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2821 }
2822
2823 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2824 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2825
2826 (void)simple_mtx_init(&sel->mutex, mtx_plain);
2827
2828 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready, &sel->compiler_ctx_state,
2829 sel, si_init_shader_selector_async);
2830 return sel;
2831 }
2832
2833 static void *si_create_shader(struct pipe_context *ctx, const struct pipe_shader_state *state)
2834 {
2835 struct si_context *sctx = (struct si_context *)ctx;
2836 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2837 bool cache_hit;
2838 struct si_shader_selector *sel = (struct si_shader_selector *)util_live_shader_cache_get(
2839 ctx, &sscreen->live_shader_cache, state, &cache_hit);
2840
2841 if (sel && cache_hit && sctx->debug.debug_message) {
2842 if (sel->main_shader_part)
2843 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part, &sctx->debug);
2844 if (sel->main_shader_part_ls)
2845 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ls, &sctx->debug);
2846 if (sel->main_shader_part_es)
2847 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_es, &sctx->debug);
2848 if (sel->main_shader_part_ngg)
2849 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg, &sctx->debug);
2850 if (sel->main_shader_part_ngg_es)
2851 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg_es, &sctx->debug);
2852 }
2853 return sel;
2854 }
2855
2856 static void si_update_streamout_state(struct si_context *sctx)
2857 {
2858 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2859
2860 if (!shader_with_so)
2861 return;
2862
2863 sctx->streamout.enabled_stream_buffers_mask = shader_with_so->enabled_streamout_buffer_mask;
2864 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2865 }
2866
2867 static void si_update_clip_regs(struct si_context *sctx, struct si_shader_selector *old_hw_vs,
2868 struct si_shader *old_hw_vs_variant,
2869 struct si_shader_selector *next_hw_vs,
2870 struct si_shader *next_hw_vs_variant)
2871 {
2872 if (next_hw_vs &&
2873 (!old_hw_vs ||
2874 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2875 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2876 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2877 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2878 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask || !old_hw_vs_variant ||
2879 !next_hw_vs_variant ||
2880 old_hw_vs_variant->key.opt.clip_disable != next_hw_vs_variant->key.opt.clip_disable))
2881 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2882 }
2883
2884 static void si_update_common_shader_state(struct si_context *sctx)
2885 {
2886 sctx->uses_bindless_samplers = si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2887 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2888 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2889 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2890 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2891 sctx->uses_bindless_images = si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2892 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2893 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2894 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2895 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2896 sctx->do_update_shaders = true;
2897 }
2898
2899 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2900 {
2901 struct si_context *sctx = (struct si_context *)ctx;
2902 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2903 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2904 struct si_shader_selector *sel = state;
2905
2906 if (sctx->vs_shader.cso == sel)
2907 return;
2908
2909 sctx->vs_shader.cso = sel;
2910 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2911 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
2912
2913 if (si_update_ngg(sctx))
2914 si_shader_change_notify(sctx);
2915
2916 si_update_common_shader_state(sctx);
2917 si_update_vs_viewport_state(sctx);
2918 si_set_active_descriptors_for_shader(sctx, sel);
2919 si_update_streamout_state(sctx);
2920 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso,
2921 si_get_vs_state(sctx));
2922 }
2923
2924 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2925 {
2926 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2927 (sctx->tes_shader.cso && sctx->tes_shader.cso->info.uses_primid) ||
2928 (sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
2929 (sctx->gs_shader.cso && sctx->gs_shader.cso->info.uses_primid) ||
2930 (sctx->ps_shader.cso && !sctx->gs_shader.cso && sctx->ps_shader.cso->info.uses_primid);
2931 }
2932
2933 bool si_update_ngg(struct si_context *sctx)
2934 {
2935 if (!sctx->screen->use_ngg) {
2936 assert(!sctx->ngg);
2937 return false;
2938 }
2939
2940 bool new_ngg = true;
2941
2942 if (sctx->gs_shader.cso && sctx->tes_shader.cso && sctx->gs_shader.cso->tess_turns_off_ngg) {
2943 new_ngg = false;
2944 } else if (!sctx->screen->use_ngg_streamout) {
2945 struct si_shader_selector *last = si_get_vs(sctx)->cso;
2946
2947 if ((last && last->so.num_outputs) || sctx->streamout.prims_gen_query_enabled)
2948 new_ngg = false;
2949 }
2950
2951 if (new_ngg != sctx->ngg) {
2952 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
2953 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
2954 * pointers are set.
2955 */
2956 if (sctx->chip_class == GFX10 && !new_ngg)
2957 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
2958
2959 sctx->ngg = new_ngg;
2960 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
2961 return true;
2962 }
2963 return false;
2964 }
2965
2966 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2967 {
2968 struct si_context *sctx = (struct si_context *)ctx;
2969 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2970 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2971 struct si_shader_selector *sel = state;
2972 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2973 bool ngg_changed;
2974
2975 if (sctx->gs_shader.cso == sel)
2976 return;
2977
2978 sctx->gs_shader.cso = sel;
2979 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2980 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2981
2982 si_update_common_shader_state(sctx);
2983 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
2984
2985 ngg_changed = si_update_ngg(sctx);
2986 if (ngg_changed || enable_changed)
2987 si_shader_change_notify(sctx);
2988 if (enable_changed) {
2989 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2990 si_update_tess_uses_prim_id(sctx);
2991 }
2992 si_update_vs_viewport_state(sctx);
2993 si_set_active_descriptors_for_shader(sctx, sel);
2994 si_update_streamout_state(sctx);
2995 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso,
2996 si_get_vs_state(sctx));
2997 }
2998
2999 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3000 {
3001 struct si_context *sctx = (struct si_context *)ctx;
3002 struct si_shader_selector *sel = state;
3003 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3004
3005 if (sctx->tcs_shader.cso == sel)
3006 return;
3007
3008 sctx->tcs_shader.cso = sel;
3009 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3010 si_update_tess_uses_prim_id(sctx);
3011
3012 si_update_common_shader_state(sctx);
3013
3014 if (enable_changed)
3015 sctx->last_tcs = NULL; /* invalidate derived tess state */
3016
3017 si_set_active_descriptors_for_shader(sctx, sel);
3018 }
3019
3020 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3021 {
3022 struct si_context *sctx = (struct si_context *)ctx;
3023 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3024 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3025 struct si_shader_selector *sel = state;
3026 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3027
3028 if (sctx->tes_shader.cso == sel)
3029 return;
3030
3031 sctx->tes_shader.cso = sel;
3032 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3033 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3034 si_update_tess_uses_prim_id(sctx);
3035
3036 si_update_common_shader_state(sctx);
3037 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3038
3039 bool ngg_changed = si_update_ngg(sctx);
3040 if (ngg_changed || enable_changed)
3041 si_shader_change_notify(sctx);
3042 if (enable_changed)
3043 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3044 si_update_vs_viewport_state(sctx);
3045 si_set_active_descriptors_for_shader(sctx, sel);
3046 si_update_streamout_state(sctx);
3047 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso,
3048 si_get_vs_state(sctx));
3049 }
3050
3051 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3052 {
3053 struct si_context *sctx = (struct si_context *)ctx;
3054 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3055 struct si_shader_selector *sel = state;
3056
3057 /* skip if supplied shader is one already in use */
3058 if (old_sel == sel)
3059 return;
3060
3061 sctx->ps_shader.cso = sel;
3062 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3063
3064 si_update_common_shader_state(sctx);
3065 if (sel) {
3066 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3067 si_update_tess_uses_prim_id(sctx);
3068
3069 if (!old_sel || old_sel->info.colors_written != sel->info.colors_written)
3070 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3071
3072 if (sctx->screen->has_out_of_order_rast &&
3073 (!old_sel || old_sel->info.writes_memory != sel->info.writes_memory ||
3074 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3075 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3076 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3077 }
3078 si_set_active_descriptors_for_shader(sctx, sel);
3079 si_update_ps_colorbuf0_slot(sctx);
3080 }
3081
3082 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3083 {
3084 if (shader->is_optimized) {
3085 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority, &shader->ready);
3086 }
3087
3088 util_queue_fence_destroy(&shader->ready);
3089
3090 if (shader->pm4) {
3091 /* If destroyed shaders were not unbound, the next compiled
3092 * shader variant could get the same pointer address and so
3093 * binding it to the same shader stage would be considered
3094 * a no-op, causing random behavior.
3095 */
3096 switch (shader->selector->type) {
3097 case PIPE_SHADER_VERTEX:
3098 if (shader->key.as_ls) {
3099 assert(sctx->chip_class <= GFX8);
3100 si_pm4_delete_state(sctx, ls, shader->pm4);
3101 } else if (shader->key.as_es) {
3102 assert(sctx->chip_class <= GFX8);
3103 si_pm4_delete_state(sctx, es, shader->pm4);
3104 } else if (shader->key.as_ngg) {
3105 si_pm4_delete_state(sctx, gs, shader->pm4);
3106 } else {
3107 si_pm4_delete_state(sctx, vs, shader->pm4);
3108 }
3109 break;
3110 case PIPE_SHADER_TESS_CTRL:
3111 si_pm4_delete_state(sctx, hs, shader->pm4);
3112 break;
3113 case PIPE_SHADER_TESS_EVAL:
3114 if (shader->key.as_es) {
3115 assert(sctx->chip_class <= GFX8);
3116 si_pm4_delete_state(sctx, es, shader->pm4);
3117 } else if (shader->key.as_ngg) {
3118 si_pm4_delete_state(sctx, gs, shader->pm4);
3119 } else {
3120 si_pm4_delete_state(sctx, vs, shader->pm4);
3121 }
3122 break;
3123 case PIPE_SHADER_GEOMETRY:
3124 if (shader->is_gs_copy_shader)
3125 si_pm4_delete_state(sctx, vs, shader->pm4);
3126 else
3127 si_pm4_delete_state(sctx, gs, shader->pm4);
3128 break;
3129 case PIPE_SHADER_FRAGMENT:
3130 si_pm4_delete_state(sctx, ps, shader->pm4);
3131 break;
3132 default:;
3133 }
3134 }
3135
3136 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3137 si_shader_destroy(shader);
3138 free(shader);
3139 }
3140
3141 static void si_destroy_shader_selector(struct pipe_context *ctx, void *cso)
3142 {
3143 struct si_context *sctx = (struct si_context *)ctx;
3144 struct si_shader_selector *sel = (struct si_shader_selector *)cso;
3145 struct si_shader *p = sel->first_variant, *c;
3146 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3147 [PIPE_SHADER_VERTEX] = &sctx->vs_shader, [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3148 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader, [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3149 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3150 };
3151
3152 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3153
3154 if (current_shader[sel->type]->cso == sel) {
3155 current_shader[sel->type]->cso = NULL;
3156 current_shader[sel->type]->current = NULL;
3157 }
3158
3159 while (p) {
3160 c = p->next_variant;
3161 si_delete_shader(sctx, p);
3162 p = c;
3163 }
3164
3165 if (sel->main_shader_part)
3166 si_delete_shader(sctx, sel->main_shader_part);
3167 if (sel->main_shader_part_ls)
3168 si_delete_shader(sctx, sel->main_shader_part_ls);
3169 if (sel->main_shader_part_es)
3170 si_delete_shader(sctx, sel->main_shader_part_es);
3171 if (sel->main_shader_part_ngg)
3172 si_delete_shader(sctx, sel->main_shader_part_ngg);
3173 if (sel->gs_copy_shader)
3174 si_delete_shader(sctx, sel->gs_copy_shader);
3175
3176 util_queue_fence_destroy(&sel->ready);
3177 simple_mtx_destroy(&sel->mutex);
3178 ralloc_free(sel->nir);
3179 free(sel->nir_binary);
3180 free(sel);
3181 }
3182
3183 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3184 {
3185 struct si_context *sctx = (struct si_context *)ctx;
3186 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3187
3188 si_shader_selector_reference(sctx, &sel, NULL);
3189 }
3190
3191 static unsigned si_get_ps_input_cntl(struct si_context *sctx, struct si_shader *vs, unsigned name,
3192 unsigned index, unsigned interpolate)
3193 {
3194 struct si_shader_info *vsinfo = &vs->selector->info;
3195 unsigned j, offset, ps_input_cntl = 0;
3196
3197 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3198 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) || name == TGSI_SEMANTIC_PRIMID)
3199 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3200
3201 if (name == TGSI_SEMANTIC_PCOORD ||
3202 (name == TGSI_SEMANTIC_TEXCOORD && sctx->sprite_coord_enable & (1 << index))) {
3203 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3204 }
3205
3206 for (j = 0; j < vsinfo->num_outputs; j++) {
3207 if (name == vsinfo->output_semantic_name[j] && index == vsinfo->output_semantic_index[j]) {
3208 offset = vs->info.vs_output_param_offset[j];
3209
3210 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3211 /* The input is loaded from parameter memory. */
3212 ps_input_cntl |= S_028644_OFFSET(offset);
3213 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3214 if (offset == AC_EXP_PARAM_UNDEFINED) {
3215 /* This can happen with depth-only rendering. */
3216 offset = 0;
3217 } else {
3218 /* The input is a DEFAULT_VAL constant. */
3219 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3220 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3221 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3222 }
3223
3224 ps_input_cntl = S_028644_OFFSET(0x20) | S_028644_DEFAULT_VAL(offset);
3225 }
3226 break;
3227 }
3228 }
3229
3230 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3231 /* PrimID is written after the last output when HW VS is used. */
3232 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3233 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3234 /* No corresponding output found, load defaults into input.
3235 * Don't set any other bits.
3236 * (FLAT_SHADE=1 completely changes behavior) */
3237 ps_input_cntl = S_028644_O