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[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR key for the shader cache.
45 */
46 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
47 unsigned char ir_sha1_cache_key[20])
48 {
49 struct blob blob = {};
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->nir_binary) {
54 ir_binary = sel->nir_binary;
55 ir_size = sel->nir_size;
56 } else {
57 assert(sel->nir);
58
59 blob_init(&blob);
60 nir_serialize(&blob, sel->nir, true);
61 ir_binary = blob.data;
62 ir_size = blob.size;
63 }
64
65 /* These settings affect the compilation, but they are not derived
66 * from the input shader IR.
67 */
68 unsigned shader_variant_flags = 0;
69
70 if (ngg)
71 shader_variant_flags |= 1 << 0;
72 if (sel->nir)
73 shader_variant_flags |= 1 << 1;
74 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
75 shader_variant_flags |= 1 << 2;
76 if (sel->force_correct_derivs_after_kill)
77 shader_variant_flags |= 1 << 3;
78
79 struct mesa_sha1 ctx;
80 _mesa_sha1_init(&ctx);
81 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
82 _mesa_sha1_update(&ctx, ir_binary, ir_size);
83 if (sel->type == PIPE_SHADER_VERTEX ||
84 sel->type == PIPE_SHADER_TESS_EVAL ||
85 sel->type == PIPE_SHADER_GEOMETRY)
86 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
87 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
88
89 if (ir_binary == blob.data)
90 blob_finish(&blob);
91 }
92
93 /** Copy "data" to "ptr" and return the next dword following copied data. */
94 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
95 {
96 /* data may be NULL if size == 0 */
97 if (size)
98 memcpy(ptr, data, size);
99 ptr += DIV_ROUND_UP(size, 4);
100 return ptr;
101 }
102
103 /** Read data from "ptr". Return the next dword following the data. */
104 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
105 {
106 memcpy(data, ptr, size);
107 ptr += DIV_ROUND_UP(size, 4);
108 return ptr;
109 }
110
111 /**
112 * Write the size as uint followed by the data. Return the next dword
113 * following the copied data.
114 */
115 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
116 {
117 *ptr++ = size;
118 return write_data(ptr, data, size);
119 }
120
121 /**
122 * Read the size as uint followed by the data. Return both via parameters.
123 * Return the next dword following the data.
124 */
125 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
126 {
127 *size = *ptr++;
128 assert(*data == NULL);
129 if (!*size)
130 return ptr;
131 *data = malloc(*size);
132 return read_data(ptr, *data, *size);
133 }
134
135 /**
136 * Return the shader binary in a buffer. The first 4 bytes contain its size
137 * as integer.
138 */
139 static void *si_get_shader_binary(struct si_shader *shader)
140 {
141 /* There is always a size of data followed by the data itself. */
142 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
143 strlen(shader->binary.llvm_ir_string) + 1 : 0;
144
145 /* Refuse to allocate overly large buffers and guard against integer
146 * overflow. */
147 if (shader->binary.elf_size > UINT_MAX / 4 ||
148 llvm_ir_size > UINT_MAX / 4)
149 return NULL;
150
151 unsigned size =
152 4 + /* total size */
153 4 + /* CRC32 of the data below */
154 align(sizeof(shader->config), 4) +
155 align(sizeof(shader->info), 4) +
156 4 + align(shader->binary.elf_size, 4) +
157 4 + align(llvm_ir_size, 4);
158 void *buffer = CALLOC(1, size);
159 uint32_t *ptr = (uint32_t*)buffer;
160
161 if (!buffer)
162 return NULL;
163
164 *ptr++ = size;
165 ptr++; /* CRC32 is calculated at the end. */
166
167 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
168 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
169 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
170 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
171 assert((char *)ptr - (char *)buffer == size);
172
173 /* Compute CRC32. */
174 ptr = (uint32_t*)buffer;
175 ptr++;
176 *ptr = util_hash_crc32(ptr + 1, size - 8);
177
178 return buffer;
179 }
180
181 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
182 {
183 uint32_t *ptr = (uint32_t*)binary;
184 uint32_t size = *ptr++;
185 uint32_t crc32 = *ptr++;
186 unsigned chunk_size;
187 unsigned elf_size;
188
189 if (util_hash_crc32(ptr, size - 8) != crc32) {
190 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
191 return false;
192 }
193
194 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
195 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
196 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
197 &elf_size);
198 shader->binary.elf_size = elf_size;
199 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
200
201 return true;
202 }
203
204 /**
205 * Insert a shader into the cache. It's assumed the shader is not in the cache.
206 * Use si_shader_cache_load_shader before calling this.
207 */
208 void si_shader_cache_insert_shader(struct si_screen *sscreen,
209 unsigned char ir_sha1_cache_key[20],
210 struct si_shader *shader,
211 bool insert_into_disk_cache)
212 {
213 void *hw_binary;
214 struct hash_entry *entry;
215 uint8_t key[CACHE_KEY_SIZE];
216
217 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
218 if (entry)
219 return; /* already added */
220
221 hw_binary = si_get_shader_binary(shader);
222 if (!hw_binary)
223 return;
224
225 if (_mesa_hash_table_insert(sscreen->shader_cache,
226 mem_dup(ir_sha1_cache_key, 20),
227 hw_binary) == NULL) {
228 FREE(hw_binary);
229 return;
230 }
231
232 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
233 disk_cache_compute_key(sscreen->disk_shader_cache,
234 ir_sha1_cache_key, 20, key);
235 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
236 *((uint32_t *) hw_binary), NULL);
237 }
238 }
239
240 bool si_shader_cache_load_shader(struct si_screen *sscreen,
241 unsigned char ir_sha1_cache_key[20],
242 struct si_shader *shader)
243 {
244 struct hash_entry *entry =
245 _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
246 if (!entry) {
247 if (sscreen->disk_shader_cache) {
248 unsigned char sha1[CACHE_KEY_SIZE];
249
250 disk_cache_compute_key(sscreen->disk_shader_cache,
251 ir_sha1_cache_key, 20, sha1);
252
253 size_t binary_size;
254 uint8_t *buffer =
255 disk_cache_get(sscreen->disk_shader_cache,
256 sha1, &binary_size);
257 if (!buffer)
258 return false;
259
260 if (binary_size < sizeof(uint32_t) ||
261 *((uint32_t*)buffer) != binary_size) {
262 /* Something has gone wrong discard the item
263 * from the cache and rebuild/link from
264 * source.
265 */
266 assert(!"Invalid radeonsi shader disk cache "
267 "item!");
268
269 disk_cache_remove(sscreen->disk_shader_cache,
270 sha1);
271 free(buffer);
272
273 return false;
274 }
275
276 if (!si_load_shader_binary(shader, buffer)) {
277 free(buffer);
278 return false;
279 }
280 free(buffer);
281
282 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
283 shader, false);
284 } else {
285 return false;
286 }
287 } else {
288 if (!si_load_shader_binary(shader, entry->data))
289 return false;
290 }
291 p_atomic_inc(&sscreen->num_shader_cache_hits);
292 return true;
293 }
294
295 static uint32_t si_shader_cache_key_hash(const void *key)
296 {
297 /* Take the first dword of SHA1. */
298 return *(uint32_t*)key;
299 }
300
301 static bool si_shader_cache_key_equals(const void *a, const void *b)
302 {
303 /* Compare SHA1s. */
304 return memcmp(a, b, 20) == 0;
305 }
306
307 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
308 {
309 FREE((void*)entry->key);
310 FREE(entry->data);
311 }
312
313 bool si_init_shader_cache(struct si_screen *sscreen)
314 {
315 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
316 sscreen->shader_cache =
317 _mesa_hash_table_create(NULL,
318 si_shader_cache_key_hash,
319 si_shader_cache_key_equals);
320
321 return sscreen->shader_cache != NULL;
322 }
323
324 void si_destroy_shader_cache(struct si_screen *sscreen)
325 {
326 if (sscreen->shader_cache)
327 _mesa_hash_table_destroy(sscreen->shader_cache,
328 si_destroy_shader_cache_entry);
329 simple_mtx_destroy(&sscreen->shader_cache_mutex);
330 }
331
332 /* SHADER STATES */
333
334 static void si_set_tesseval_regs(struct si_screen *sscreen,
335 const struct si_shader_selector *tes,
336 struct si_pm4_state *pm4)
337 {
338 const struct si_shader_info *info = &tes->info;
339 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
340 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
341 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
342 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
343 unsigned type, partitioning, topology, distribution_mode;
344
345 switch (tes_prim_mode) {
346 case PIPE_PRIM_LINES:
347 type = V_028B6C_TESS_ISOLINE;
348 break;
349 case PIPE_PRIM_TRIANGLES:
350 type = V_028B6C_TESS_TRIANGLE;
351 break;
352 case PIPE_PRIM_QUADS:
353 type = V_028B6C_TESS_QUAD;
354 break;
355 default:
356 assert(0);
357 return;
358 }
359
360 switch (tes_spacing) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
362 partitioning = V_028B6C_PART_FRAC_ODD;
363 break;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
365 partitioning = V_028B6C_PART_FRAC_EVEN;
366 break;
367 case PIPE_TESS_SPACING_EQUAL:
368 partitioning = V_028B6C_PART_INTEGER;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 if (tes_point_mode)
376 topology = V_028B6C_OUTPUT_POINT;
377 else if (tes_prim_mode == PIPE_PRIM_LINES)
378 topology = V_028B6C_OUTPUT_LINE;
379 else if (tes_vertex_order_cw)
380 /* for some reason, this must be the other way around */
381 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
382 else
383 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
384
385 if (sscreen->info.has_distributed_tess) {
386 if (sscreen->info.family == CHIP_FIJI ||
387 sscreen->info.family >= CHIP_POLARIS10)
388 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
389 else
390 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
391 } else
392 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
393
394 assert(pm4->shader);
395 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
396 S_028B6C_PARTITIONING(partitioning) |
397 S_028B6C_TOPOLOGY(topology) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
399 }
400
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
403 *
404 * Possible VGT configurations and which state should set the register:
405 *
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
408 * VS as VS | VS | 30
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 *
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 */
415 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
416 struct si_shader_selector *sel,
417 struct si_shader *shader,
418 struct si_pm4_state *pm4)
419 {
420 unsigned type = sel->type;
421
422 if (sscreen->info.family < CHIP_POLARIS10 ||
423 sscreen->info.chip_class >= GFX10)
424 return;
425
426 /* VS as VS, or VS as ES: */
427 if ((type == PIPE_SHADER_VERTEX &&
428 (!shader ||
429 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
430 /* TES as VS, or TES as ES: */
431 type == PIPE_SHADER_TESS_EVAL) {
432 unsigned vtx_reuse_depth = 30;
433
434 if (type == PIPE_SHADER_TESS_EVAL &&
435 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD)
437 vtx_reuse_depth = 14;
438
439 assert(pm4->shader);
440 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
441 }
442 }
443
444 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
445 {
446 if (shader->pm4)
447 si_pm4_clear_state(shader->pm4);
448 else
449 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
450
451 if (shader->pm4) {
452 shader->pm4->shader = shader;
453 return shader->pm4;
454 } else {
455 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
456 return NULL;
457 }
458 }
459
460 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
461 unsigned num_always_on_user_sgprs)
462 {
463 struct si_shader_selector *vs = shader->previous_stage_sel ?
464 shader->previous_stage_sel : shader->selector;
465 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
466
467 /* 1 SGPR is reserved for the vertex buffer pointer. */
468 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
469
470 if (num_vbos_in_user_sgprs)
471 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
472
473 /* Add the pointer to VBO descriptors. */
474 return num_always_on_user_sgprs + 1;
475 }
476
477 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
478 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
479 struct si_shader *shader, bool legacy_vs_prim_id)
480 {
481 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
482 (shader->previous_stage_sel &&
483 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
484
485 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
486 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
487 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
488 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
489 */
490 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
491
492 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
493 return 3;
494 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
495 return 2;
496 else if (is_ls || shader->info.uses_instanceid)
497 return 1;
498 else
499 return 0;
500 }
501
502 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
503 {
504 struct si_pm4_state *pm4;
505 uint64_t va;
506
507 assert(sscreen->info.chip_class <= GFX8);
508
509 pm4 = si_get_shader_pm4_state(shader);
510 if (!pm4)
511 return;
512
513 va = shader->bo->gpu_address;
514 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
515
516 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
518
519 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
520 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
521 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
522 S_00B528_DX10_CLAMP(1) |
523 S_00B528_FLOAT_MODE(shader->config.float_mode);
524 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
525 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
526 }
527
528 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
529 {
530 struct si_pm4_state *pm4;
531 uint64_t va;
532
533 pm4 = si_get_shader_pm4_state(shader);
534 if (!pm4)
535 return;
536
537 va = shader->bo->gpu_address;
538 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
539
540 if (sscreen->info.chip_class >= GFX9) {
541 if (sscreen->info.chip_class >= GFX10) {
542 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
543 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
544 } else {
545 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
546 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
547 }
548
549 unsigned num_user_sgprs =
550 si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
551
552 shader->config.rsrc2 =
553 S_00B42C_USER_SGPR(num_user_sgprs) |
554 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
555
556 if (sscreen->info.chip_class >= GFX10)
557 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
558 else
559 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
560 } else {
561 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
562 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
563
564 shader->config.rsrc2 =
565 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
566 S_00B42C_OC_LDS_EN(1) |
567 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
568 }
569
570 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
571 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
572 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
573 (sscreen->info.chip_class <= GFX9 ?
574 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
575 S_00B428_DX10_CLAMP(1) |
576 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
577 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
578 S_00B428_FLOAT_MODE(shader->config.float_mode) |
579 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
580 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
581
582 if (sscreen->info.chip_class <= GFX8) {
583 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
584 shader->config.rsrc2);
585 }
586 }
587
588 static void si_emit_shader_es(struct si_context *sctx)
589 {
590 struct si_shader *shader = sctx->queued.named.es->shader;
591 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
592
593 if (!shader)
594 return;
595
596 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
597 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
598 shader->selector->esgs_itemsize / 4);
599
600 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
601 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
602 SI_TRACKED_VGT_TF_PARAM,
603 shader->vgt_tf_param);
604
605 if (shader->vgt_vertex_reuse_block_cntl)
606 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
607 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
608 shader->vgt_vertex_reuse_block_cntl);
609
610 if (initial_cdw != sctx->gfx_cs->current.cdw)
611 sctx->context_roll = true;
612 }
613
614 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
615 {
616 struct si_pm4_state *pm4;
617 unsigned num_user_sgprs;
618 unsigned vgpr_comp_cnt;
619 uint64_t va;
620 unsigned oc_lds_en;
621
622 assert(sscreen->info.chip_class <= GFX8);
623
624 pm4 = si_get_shader_pm4_state(shader);
625 if (!pm4)
626 return;
627
628 pm4->atom.emit = si_emit_shader_es;
629 va = shader->bo->gpu_address;
630 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
631
632 if (shader->selector->type == PIPE_SHADER_VERTEX) {
633 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
634 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
635 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
636 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
637 num_user_sgprs = SI_TES_NUM_USER_SGPR;
638 } else
639 unreachable("invalid shader selector type");
640
641 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
642
643 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
644 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
645 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
646 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
647 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
648 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
649 S_00B328_DX10_CLAMP(1) |
650 S_00B328_FLOAT_MODE(shader->config.float_mode));
651 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
652 S_00B32C_USER_SGPR(num_user_sgprs) |
653 S_00B32C_OC_LDS_EN(oc_lds_en) |
654 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
655
656 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
657 si_set_tesseval_regs(sscreen, shader->selector, pm4);
658
659 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
660 }
661
662 void gfx9_get_gs_info(struct si_shader_selector *es,
663 struct si_shader_selector *gs,
664 struct gfx9_gs_info *out)
665 {
666 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
667 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
668 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
669 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
670
671 /* All these are in dwords: */
672 /* We can't allow using the whole LDS, because GS waves compete with
673 * other shader stages for LDS space. */
674 const unsigned max_lds_size = 8 * 1024;
675 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
676 unsigned esgs_lds_size;
677
678 /* All these are per subgroup: */
679 const unsigned max_out_prims = 32 * 1024;
680 const unsigned max_es_verts = 255;
681 const unsigned ideal_gs_prims = 64;
682 unsigned max_gs_prims, gs_prims;
683 unsigned min_es_verts, es_verts, worst_case_es_verts;
684
685 if (uses_adjacency || gs_num_invocations > 1)
686 max_gs_prims = 127 / gs_num_invocations;
687 else
688 max_gs_prims = 255;
689
690 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
691 * Make sure we don't go over the maximum value.
692 */
693 if (gs->gs_max_out_vertices > 0) {
694 max_gs_prims = MIN2(max_gs_prims,
695 max_out_prims /
696 (gs->gs_max_out_vertices * gs_num_invocations));
697 }
698 assert(max_gs_prims > 0);
699
700 /* If the primitive has adjacency, halve the number of vertices
701 * that will be reused in multiple primitives.
702 */
703 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
704
705 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
706 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
707
708 /* Compute ESGS LDS size based on the worst case number of ES vertices
709 * needed to create the target number of GS prims per subgroup.
710 */
711 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
712
713 /* If total LDS usage is too big, refactor partitions based on ratio
714 * of ESGS item sizes.
715 */
716 if (esgs_lds_size > max_lds_size) {
717 /* Our target GS Prims Per Subgroup was too large. Calculate
718 * the maximum number of GS Prims Per Subgroup that will fit
719 * into LDS, capped by the maximum that the hardware can support.
720 */
721 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
722 max_gs_prims);
723 assert(gs_prims > 0);
724 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
725 max_es_verts);
726
727 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
728 assert(esgs_lds_size <= max_lds_size);
729 }
730
731 /* Now calculate remaining ESGS information. */
732 if (esgs_lds_size)
733 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
734 else
735 es_verts = max_es_verts;
736
737 /* Vertices for adjacency primitives are not always reused, so restore
738 * it for ES_VERTS_PER_SUBGRP.
739 */
740 min_es_verts = gs->gs_input_verts_per_prim;
741
742 /* For normal primitives, the VGT only checks if they are past the ES
743 * verts per subgroup after allocating a full GS primitive and if they
744 * are, kick off a new subgroup. But if those additional ES verts are
745 * unique (e.g. not reused) we need to make sure there is enough LDS
746 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
747 */
748 es_verts -= min_es_verts - 1;
749
750 out->es_verts_per_subgroup = es_verts;
751 out->gs_prims_per_subgroup = gs_prims;
752 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
753 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
754 gs->gs_max_out_vertices;
755 out->esgs_ring_size = 4 * esgs_lds_size;
756
757 assert(out->max_prims_per_subgroup <= max_out_prims);
758 }
759
760 static void si_emit_shader_gs(struct si_context *sctx)
761 {
762 struct si_shader *shader = sctx->queued.named.gs->shader;
763 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
764
765 if (!shader)
766 return;
767
768 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
769 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
770 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
771 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
772 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
773 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
774 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
775
776 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
777 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
778 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
779 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
780
781 /* R_028B38_VGT_GS_MAX_VERT_OUT */
782 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
783 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
784 shader->ctx_reg.gs.vgt_gs_max_vert_out);
785
786 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
787 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
788 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
789 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
790 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
791 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
792 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
793 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
794
795 /* R_028B90_VGT_GS_INSTANCE_CNT */
796 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
797 SI_TRACKED_VGT_GS_INSTANCE_CNT,
798 shader->ctx_reg.gs.vgt_gs_instance_cnt);
799
800 if (sctx->chip_class >= GFX9) {
801 /* R_028A44_VGT_GS_ONCHIP_CNTL */
802 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
803 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
804 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
805 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
806 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
807 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
808 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
809 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
810 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
811 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
812 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
813
814 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
815 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
816 SI_TRACKED_VGT_TF_PARAM,
817 shader->vgt_tf_param);
818 if (shader->vgt_vertex_reuse_block_cntl)
819 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
820 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
821 shader->vgt_vertex_reuse_block_cntl);
822 }
823
824 if (initial_cdw != sctx->gfx_cs->current.cdw)
825 sctx->context_roll = true;
826 }
827
828 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
829 {
830 struct si_shader_selector *sel = shader->selector;
831 const ubyte *num_components = sel->info.num_stream_output_components;
832 unsigned gs_num_invocations = sel->gs_num_invocations;
833 struct si_pm4_state *pm4;
834 uint64_t va;
835 unsigned max_stream = sel->max_gs_stream;
836 unsigned offset;
837
838 pm4 = si_get_shader_pm4_state(shader);
839 if (!pm4)
840 return;
841
842 pm4->atom.emit = si_emit_shader_gs;
843
844 offset = num_components[0] * sel->gs_max_out_vertices;
845 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
846
847 if (max_stream >= 1)
848 offset += num_components[1] * sel->gs_max_out_vertices;
849 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
850
851 if (max_stream >= 2)
852 offset += num_components[2] * sel->gs_max_out_vertices;
853 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
854
855 if (max_stream >= 3)
856 offset += num_components[3] * sel->gs_max_out_vertices;
857 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
858
859 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
860 assert(offset < (1 << 15));
861
862 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
863
864 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
865 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
866 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
867 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
868
869 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
870 S_028B90_ENABLE(gs_num_invocations > 0);
871
872 va = shader->bo->gpu_address;
873 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
874
875 if (sscreen->info.chip_class >= GFX9) {
876 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
877 unsigned es_type = shader->key.part.gs.es->type;
878 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
879
880 if (es_type == PIPE_SHADER_VERTEX) {
881 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
882 } else if (es_type == PIPE_SHADER_TESS_EVAL)
883 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
884 else
885 unreachable("invalid shader selector type");
886
887 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
888 * VGPR[0:4] are always loaded.
889 */
890 if (sel->info.uses_invocationid)
891 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
892 else if (sel->info.uses_primid)
893 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
894 else if (input_prim >= PIPE_PRIM_TRIANGLES)
895 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
896 else
897 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
898
899 unsigned num_user_sgprs;
900 if (es_type == PIPE_SHADER_VERTEX)
901 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
902 else
903 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
904
905 if (sscreen->info.chip_class >= GFX10) {
906 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
907 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
908 } else {
909 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
910 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
911 }
912
913 uint32_t rsrc1 =
914 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
915 S_00B228_DX10_CLAMP(1) |
916 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
917 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
918 S_00B228_FLOAT_MODE(shader->config.float_mode) |
919 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
920 uint32_t rsrc2 =
921 S_00B22C_USER_SGPR(num_user_sgprs) |
922 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
923 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
924 S_00B22C_LDS_SIZE(shader->config.lds_size) |
925 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
926
927 if (sscreen->info.chip_class >= GFX10) {
928 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
929 } else {
930 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
931 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
932 }
933
934 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
935 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
936
937 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
938 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
939 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
940 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
941 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
942 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
943 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
944 shader->key.part.gs.es->esgs_itemsize / 4;
945
946 if (es_type == PIPE_SHADER_TESS_EVAL)
947 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
948
949 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
950 NULL, pm4);
951 } else {
952 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
953 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
954
955 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
956 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
957 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
958 S_00B228_DX10_CLAMP(1) |
959 S_00B228_FLOAT_MODE(shader->config.float_mode));
960 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
961 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
962 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
963 }
964 }
965
966 static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
967 {
968 enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
969
970 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
971 sctx->tracked_regs.reg_value[reg] != value) {
972 struct radeon_cmdbuf *cs = sctx->gfx_cs;
973
974 if (sctx->family == CHIP_NAVI10 ||
975 sctx->family == CHIP_NAVI12 ||
976 sctx->family == CHIP_NAVI14) {
977 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
978 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
979 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
980 }
981
982 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
983
984 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
985 sctx->tracked_regs.reg_value[reg] = value;
986 }
987 }
988
989 /* Common tail code for NGG primitive shaders. */
990 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
991 struct si_shader *shader,
992 unsigned initial_cdw)
993 {
994 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
995 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
996 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
997 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
998 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
999 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
1000 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1001 SI_TRACKED_VGT_PRIMITIVEID_EN,
1002 shader->ctx_reg.ngg.vgt_primitiveid_en);
1003 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1004 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1005 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
1006 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
1007 SI_TRACKED_VGT_GS_INSTANCE_CNT,
1008 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
1009 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
1010 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
1011 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
1012 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1013 SI_TRACKED_SPI_VS_OUT_CONFIG,
1014 shader->ctx_reg.ngg.spi_vs_out_config);
1015 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
1016 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
1017 shader->ctx_reg.ngg.spi_shader_idx_format,
1018 shader->ctx_reg.ngg.spi_shader_pos_format);
1019 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1020 SI_TRACKED_PA_CL_VTE_CNTL,
1021 shader->ctx_reg.ngg.pa_cl_vte_cntl);
1022 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1023 SI_TRACKED_PA_CL_NGG_CNTL,
1024 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1025
1026 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1027 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1028 shader->pa_cl_vs_out_cntl,
1029 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1030
1031 if (initial_cdw != sctx->gfx_cs->current.cdw)
1032 sctx->context_roll = true;
1033
1034 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1035 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
1036 }
1037
1038 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1039 {
1040 struct si_shader *shader = sctx->queued.named.gs->shader;
1041 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1042
1043 if (!shader)
1044 return;
1045
1046 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1047 }
1048
1049 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1050 {
1051 struct si_shader *shader = sctx->queued.named.gs->shader;
1052 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1053
1054 if (!shader)
1055 return;
1056
1057 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1058 SI_TRACKED_VGT_TF_PARAM,
1059 shader->vgt_tf_param);
1060
1061 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1062 }
1063
1064 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1065 {
1066 struct si_shader *shader = sctx->queued.named.gs->shader;
1067 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1068
1069 if (!shader)
1070 return;
1071
1072 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1073 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1074 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1075
1076 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1077 }
1078
1079 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1080 {
1081 struct si_shader *shader = sctx->queued.named.gs->shader;
1082 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1083
1084 if (!shader)
1085 return;
1086
1087 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1088 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1089 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1090 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1091 SI_TRACKED_VGT_TF_PARAM,
1092 shader->vgt_tf_param);
1093
1094 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1095 }
1096
1097 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1098 {
1099 if (gs->type == PIPE_SHADER_GEOMETRY)
1100 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1101
1102 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1103 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1104 return PIPE_PRIM_POINTS;
1105 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1106 return PIPE_PRIM_LINES;
1107 return PIPE_PRIM_TRIANGLES;
1108 }
1109
1110 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1111 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1112 }
1113
1114 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1115 {
1116 bool misc_vec_ena =
1117 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1118 sel->info.writes_layer || sel->info.writes_viewport_index;
1119 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1120 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1121 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1122 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1123 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1124 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1125 }
1126
1127 /**
1128 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1129 * in NGG mode.
1130 */
1131 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1132 {
1133 const struct si_shader_selector *gs_sel = shader->selector;
1134 const struct si_shader_info *gs_info = &gs_sel->info;
1135 enum pipe_shader_type gs_type = shader->selector->type;
1136 const struct si_shader_selector *es_sel =
1137 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1138 const struct si_shader_info *es_info = &es_sel->info;
1139 enum pipe_shader_type es_type = es_sel->type;
1140 unsigned num_user_sgprs;
1141 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1142 uint64_t va;
1143 unsigned window_space =
1144 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1145 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1146 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1147 unsigned input_prim = si_get_input_prim(gs_sel);
1148 bool break_wave_at_eoi = false;
1149 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1150 if (!pm4)
1151 return;
1152
1153 if (es_type == PIPE_SHADER_TESS_EVAL) {
1154 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1155 : gfx10_emit_shader_ngg_tess_nogs;
1156 } else {
1157 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1158 : gfx10_emit_shader_ngg_notess_nogs;
1159 }
1160
1161 va = shader->bo->gpu_address;
1162 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1163
1164 if (es_type == PIPE_SHADER_VERTEX) {
1165 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1166
1167 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1168 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1169 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1170 } else {
1171 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1172 }
1173 } else {
1174 assert(es_type == PIPE_SHADER_TESS_EVAL);
1175 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1176 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1177
1178 if (es_enable_prim_id || gs_info->uses_primid)
1179 break_wave_at_eoi = true;
1180 }
1181
1182 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1183 * VGPR[0:4] are always loaded.
1184 *
1185 * Vertex shaders always need to load VGPR3, because they need to
1186 * pass edge flags for decomposed primitives (such as quads) to the PA
1187 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1188 */
1189 if (gs_info->uses_invocationid ||
1190 (gs_type == PIPE_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1191 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1192 else if ((gs_type == PIPE_SHADER_GEOMETRY && gs_info->uses_primid) ||
1193 (gs_type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1194 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1195 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1196 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1197 else
1198 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1199
1200 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1201 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1202 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1203 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1204 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1205 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1206 S_00B228_DX10_CLAMP(1) |
1207 S_00B228_MEM_ORDERED(1) |
1208 S_00B228_WGP_MODE(1) |
1209 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1210 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1211 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1212 S_00B22C_USER_SGPR(num_user_sgprs) |
1213 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1214 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1215 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1216 S_00B22C_LDS_SIZE(shader->config.lds_size));
1217
1218 nparams = MAX2(shader->info.nr_param_exports, 1);
1219 shader->ctx_reg.ngg.spi_vs_out_config =
1220 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1221 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1222
1223 shader->ctx_reg.ngg.spi_shader_idx_format =
1224 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1225 shader->ctx_reg.ngg.spi_shader_pos_format =
1226 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1227 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1228 V_02870C_SPI_SHADER_4COMP :
1229 V_02870C_SPI_SHADER_NONE) |
1230 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1231 V_02870C_SPI_SHADER_4COMP :
1232 V_02870C_SPI_SHADER_NONE) |
1233 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1234 V_02870C_SPI_SHADER_4COMP :
1235 V_02870C_SPI_SHADER_NONE);
1236
1237 shader->ctx_reg.ngg.vgt_primitiveid_en =
1238 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1239 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1240 gs_sel->info.writes_primid);
1241
1242 if (gs_type == PIPE_SHADER_GEOMETRY) {
1243 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1244 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1245 } else {
1246 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1247 }
1248
1249 if (es_type == PIPE_SHADER_TESS_EVAL)
1250 si_set_tesseval_regs(sscreen, es_sel, pm4);
1251
1252 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1253 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1254 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1255 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1256 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1257 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1258 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1259 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1260 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1261 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1262 S_028B90_CNT(gs_num_invocations) |
1263 S_028B90_ENABLE(gs_num_invocations > 1) |
1264 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1265 shader->ngg.max_vert_out_per_gs_instance);
1266
1267 /* Always output hw-generated edge flags and pass them via the prim
1268 * export to prevent drawing lines on internal edges of decomposed
1269 * primitives (such as quads) with polygon mode = lines. Only VS needs
1270 * this.
1271 */
1272 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1273 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1274 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1275 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1276 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1277
1278 shader->ge_cntl =
1279 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1280 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1281 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1282
1283 /* Bug workaround for a possible hang with non-tessellation cases.
1284 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1285 *
1286 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1287 */
1288 if ((sscreen->info.family == CHIP_NAVI10 ||
1289 sscreen->info.family == CHIP_NAVI12 ||
1290 sscreen->info.family == CHIP_NAVI14) &&
1291 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1292 shader->ngg.hw_max_esverts != 256) {
1293 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1294
1295 if (shader->ngg.hw_max_esverts > 5) {
1296 shader->ge_cntl |=
1297 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1298 }
1299 }
1300
1301 if (window_space) {
1302 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1303 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1304 } else {
1305 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1306 S_028818_VTX_W0_FMT(1) |
1307 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1308 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1309 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1310 }
1311 }
1312
1313 static void si_emit_shader_vs(struct si_context *sctx)
1314 {
1315 struct si_shader *shader = sctx->queued.named.vs->shader;
1316 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1317
1318 if (!shader)
1319 return;
1320
1321 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1322 SI_TRACKED_VGT_GS_MODE,
1323 shader->ctx_reg.vs.vgt_gs_mode);
1324 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1325 SI_TRACKED_VGT_PRIMITIVEID_EN,
1326 shader->ctx_reg.vs.vgt_primitiveid_en);
1327
1328 if (sctx->chip_class <= GFX8) {
1329 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1330 SI_TRACKED_VGT_REUSE_OFF,
1331 shader->ctx_reg.vs.vgt_reuse_off);
1332 }
1333
1334 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1335 SI_TRACKED_SPI_VS_OUT_CONFIG,
1336 shader->ctx_reg.vs.spi_vs_out_config);
1337
1338 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1339 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1340 shader->ctx_reg.vs.spi_shader_pos_format);
1341
1342 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1343 SI_TRACKED_PA_CL_VTE_CNTL,
1344 shader->ctx_reg.vs.pa_cl_vte_cntl);
1345
1346 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1347 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1348 SI_TRACKED_VGT_TF_PARAM,
1349 shader->vgt_tf_param);
1350
1351 if (shader->vgt_vertex_reuse_block_cntl)
1352 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1353 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1354 shader->vgt_vertex_reuse_block_cntl);
1355
1356 /* Required programming for tessellation. (legacy pipeline only) */
1357 if (sctx->chip_class == GFX10 &&
1358 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1359 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1360 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1361 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1362 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1363 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1364 }
1365
1366 if (sctx->chip_class >= GFX10) {
1367 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1368 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1369 shader->pa_cl_vs_out_cntl,
1370 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1371 }
1372
1373 if (initial_cdw != sctx->gfx_cs->current.cdw)
1374 sctx->context_roll = true;
1375
1376 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1377 if (sctx->chip_class >= GFX10)
1378 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
1379 }
1380
1381 /**
1382 * Compute the state for \p shader, which will run as a vertex shader on the
1383 * hardware.
1384 *
1385 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1386 * is the copy shader.
1387 */
1388 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1389 struct si_shader_selector *gs)
1390 {
1391 const struct si_shader_info *info = &shader->selector->info;
1392 struct si_pm4_state *pm4;
1393 unsigned num_user_sgprs, vgpr_comp_cnt;
1394 uint64_t va;
1395 unsigned nparams, oc_lds_en;
1396 unsigned window_space =
1397 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1398 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1399
1400 pm4 = si_get_shader_pm4_state(shader);
1401 if (!pm4)
1402 return;
1403
1404 pm4->atom.emit = si_emit_shader_vs;
1405
1406 /* We always write VGT_GS_MODE in the VS state, because every switch
1407 * between different shader pipelines involving a different GS or no
1408 * GS at all involves a switch of the VS (different GS use different
1409 * copy shaders). On the other hand, when the API switches from a GS to
1410 * no GS and then back to the same GS used originally, the GS state is
1411 * not sent again.
1412 */
1413 if (!gs) {
1414 unsigned mode = V_028A40_GS_OFF;
1415
1416 /* PrimID needs GS scenario A. */
1417 if (enable_prim_id)
1418 mode = V_028A40_GS_SCENARIO_A;
1419
1420 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1421 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1422 } else {
1423 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1424 sscreen->info.chip_class);
1425 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1426 }
1427
1428 if (sscreen->info.chip_class <= GFX8) {
1429 /* Reuse needs to be set off if we write oViewport. */
1430 shader->ctx_reg.vs.vgt_reuse_off =
1431 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1432 }
1433
1434 va = shader->bo->gpu_address;
1435 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1436
1437 if (gs) {
1438 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1439 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1440 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1441 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1442
1443 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1444 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1445 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1446 } else {
1447 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1448 }
1449 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1450 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1451 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1452 } else
1453 unreachable("invalid shader selector type");
1454
1455 /* VS is required to export at least one param. */
1456 nparams = MAX2(shader->info.nr_param_exports, 1);
1457 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1458
1459 if (sscreen->info.chip_class >= GFX10) {
1460 shader->ctx_reg.vs.spi_vs_out_config |=
1461 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1462 }
1463
1464 shader->ctx_reg.vs.spi_shader_pos_format =
1465 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1466 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1467 V_02870C_SPI_SHADER_4COMP :
1468 V_02870C_SPI_SHADER_NONE) |
1469 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1470 V_02870C_SPI_SHADER_4COMP :
1471 V_02870C_SPI_SHADER_NONE) |
1472 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1473 V_02870C_SPI_SHADER_4COMP :
1474 V_02870C_SPI_SHADER_NONE);
1475 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1476 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1477 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1478
1479 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1480
1481 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1482 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1483
1484 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1485 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1486 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1487 S_00B128_DX10_CLAMP(1) |
1488 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1489 S_00B128_FLOAT_MODE(shader->config.float_mode);
1490 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1491 S_00B12C_OC_LDS_EN(oc_lds_en) |
1492 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1493
1494 if (sscreen->info.chip_class >= GFX10)
1495 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1496 else if (sscreen->info.chip_class == GFX9)
1497 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1498
1499 if (sscreen->info.chip_class <= GFX9)
1500 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1501
1502 if (!sscreen->use_ngg_streamout) {
1503 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1504 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1505 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1506 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1507 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1508 }
1509
1510 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1511 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1512
1513 if (window_space)
1514 shader->ctx_reg.vs.pa_cl_vte_cntl =
1515 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1516 else
1517 shader->ctx_reg.vs.pa_cl_vte_cntl =
1518 S_028818_VTX_W0_FMT(1) |
1519 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1520 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1521 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1522
1523 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1524 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1525
1526 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1527 }
1528
1529 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1530 {
1531 struct si_shader_info *info = &ps->selector->info;
1532 unsigned num_colors = !!(info->colors_read & 0x0f) +
1533 !!(info->colors_read & 0xf0);
1534 unsigned num_interp = ps->selector->info.num_inputs +
1535 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1536
1537 assert(num_interp <= 32);
1538 return MIN2(num_interp, 32);
1539 }
1540
1541 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1542 {
1543 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1544 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1545
1546 /* If the i-th target format is set, all previous target formats must
1547 * be non-zero to avoid hangs.
1548 */
1549 for (i = 0; i < num_targets; i++)
1550 if (!(value & (0xf << (i * 4))))
1551 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1552
1553 return value;
1554 }
1555
1556 static void si_emit_shader_ps(struct si_context *sctx)
1557 {
1558 struct si_shader *shader = sctx->queued.named.ps->shader;
1559 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1560
1561 if (!shader)
1562 return;
1563
1564 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1565 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1566 SI_TRACKED_SPI_PS_INPUT_ENA,
1567 shader->ctx_reg.ps.spi_ps_input_ena,
1568 shader->ctx_reg.ps.spi_ps_input_addr);
1569
1570 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1571 SI_TRACKED_SPI_BARYC_CNTL,
1572 shader->ctx_reg.ps.spi_baryc_cntl);
1573 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1574 SI_TRACKED_SPI_PS_IN_CONTROL,
1575 shader->ctx_reg.ps.spi_ps_in_control);
1576
1577 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1578 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1579 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1580 shader->ctx_reg.ps.spi_shader_z_format,
1581 shader->ctx_reg.ps.spi_shader_col_format);
1582
1583 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1584 SI_TRACKED_CB_SHADER_MASK,
1585 shader->ctx_reg.ps.cb_shader_mask);
1586
1587 if (initial_cdw != sctx->gfx_cs->current.cdw)
1588 sctx->context_roll = true;
1589 }
1590
1591 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1592 {
1593 struct si_shader_info *info = &shader->selector->info;
1594 struct si_pm4_state *pm4;
1595 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1596 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1597 uint64_t va;
1598 unsigned input_ena = shader->config.spi_ps_input_ena;
1599
1600 /* we need to enable at least one of them, otherwise we hang the GPU */
1601 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1602 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1603 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1604 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1605 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1606 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1607 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1608 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1609 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1610 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1611 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1612 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1613 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1614 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1615
1616 /* Validate interpolation optimization flags (read as implications). */
1617 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1618 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1619 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1620 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1621 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1622 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1623 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1624 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1625 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1626 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1627 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1628 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1629 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1630 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1631 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1632 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1633 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1634 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1635
1636 /* Validate cases when the optimizations are off (read as implications). */
1637 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1638 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1639 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1640 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1641 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1642 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1643
1644 pm4 = si_get_shader_pm4_state(shader);
1645 if (!pm4)
1646 return;
1647
1648 pm4->atom.emit = si_emit_shader_ps;
1649
1650 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1651 * Possible vaules:
1652 * 0 -> Position = pixel center
1653 * 1 -> Position = pixel centroid
1654 * 2 -> Position = at sample position
1655 *
1656 * From GLSL 4.5 specification, section 7.1:
1657 * "The variable gl_FragCoord is available as an input variable from
1658 * within fragment shaders and it holds the window relative coordinates
1659 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1660 * value can be for any location within the pixel, or one of the
1661 * fragment samples. The use of centroid does not further restrict
1662 * this value to be inside the current primitive."
1663 *
1664 * Meaning that centroid has no effect and we can return anything within
1665 * the pixel. Thus, return the value at sample position, because that's
1666 * the most accurate one shaders can get.
1667 */
1668 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1669
1670 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1671 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1672 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1673
1674 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1675 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1676
1677 /* Ensure that some export memory is always allocated, for two reasons:
1678 *
1679 * 1) Correctness: The hardware ignores the EXEC mask if no export
1680 * memory is allocated, so KILL and alpha test do not work correctly
1681 * without this.
1682 * 2) Performance: Every shader needs at least a NULL export, even when
1683 * it writes no color/depth output. The NULL export instruction
1684 * stalls without this setting.
1685 *
1686 * Don't add this to CB_SHADER_MASK.
1687 *
1688 * GFX10 supports pixel shaders without exports by setting both
1689 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1690 * instructions if any are present.
1691 */
1692 if ((sscreen->info.chip_class <= GFX9 ||
1693 info->uses_kill ||
1694 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1695 !spi_shader_col_format &&
1696 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1697 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1698
1699 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1700 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1701
1702 /* Set interpolation controls. */
1703 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1704 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1705
1706 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1707 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1708 shader->ctx_reg.ps.spi_shader_z_format =
1709 ac_get_spi_shader_z_format(info->writes_z,
1710 info->writes_stencil,
1711 info->writes_samplemask);
1712 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1713 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1714
1715 va = shader->bo->gpu_address;
1716 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1717 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1718 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1719
1720 uint32_t rsrc1 =
1721 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1722 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1723 S_00B028_DX10_CLAMP(1) |
1724 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1725 S_00B028_FLOAT_MODE(shader->config.float_mode);
1726
1727 if (sscreen->info.chip_class < GFX10) {
1728 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1729 }
1730
1731 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1732 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1733 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1734 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1735 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1736 }
1737
1738 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1739 struct si_shader *shader)
1740 {
1741 switch (shader->selector->type) {
1742 case PIPE_SHADER_VERTEX:
1743 if (shader->key.as_ls)
1744 si_shader_ls(sscreen, shader);
1745 else if (shader->key.as_es)
1746 si_shader_es(sscreen, shader);
1747 else if (shader->key.as_ngg)
1748 gfx10_shader_ngg(sscreen, shader);
1749 else
1750 si_shader_vs(sscreen, shader, NULL);
1751 break;
1752 case PIPE_SHADER_TESS_CTRL:
1753 si_shader_hs(sscreen, shader);
1754 break;
1755 case PIPE_SHADER_TESS_EVAL:
1756 if (shader->key.as_es)
1757 si_shader_es(sscreen, shader);
1758 else if (shader->key.as_ngg)
1759 gfx10_shader_ngg(sscreen, shader);
1760 else
1761 si_shader_vs(sscreen, shader, NULL);
1762 break;
1763 case PIPE_SHADER_GEOMETRY:
1764 if (shader->key.as_ngg)
1765 gfx10_shader_ngg(sscreen, shader);
1766 else
1767 si_shader_gs(sscreen, shader);
1768 break;
1769 case PIPE_SHADER_FRAGMENT:
1770 si_shader_ps(sscreen, shader);
1771 break;
1772 default:
1773 assert(0);
1774 }
1775 }
1776
1777 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1778 {
1779 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1780 return sctx->queued.named.dsa->alpha_func;
1781 }
1782
1783 void si_shader_selector_key_vs(struct si_context *sctx,
1784 struct si_shader_selector *vs,
1785 struct si_shader_key *key,
1786 struct si_vs_prolog_bits *prolog_key)
1787 {
1788 if (!sctx->vertex_elements ||
1789 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1790 return;
1791
1792 struct si_vertex_elements *elts = sctx->vertex_elements;
1793
1794 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1795 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1796 prolog_key->unpack_instance_id_from_vertex_id =
1797 sctx->prim_discard_cs_instancing;
1798
1799 /* Prefer a monolithic shader to allow scheduling divisions around
1800 * VBO loads. */
1801 if (prolog_key->instance_divisor_is_fetched)
1802 key->opt.prefer_mono = 1;
1803
1804 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1805 unsigned count_mask = (1 << count) - 1;
1806 unsigned fix = elts->fix_fetch_always & count_mask;
1807 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1808
1809 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1810 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1811 while (mask) {
1812 unsigned i = u_bit_scan(&mask);
1813 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1814 unsigned vbidx = elts->vertex_buffer_index[i];
1815 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1816 unsigned align_mask = (1 << log_hw_load_size) - 1;
1817 if (vb->buffer_offset & align_mask ||
1818 vb->stride & align_mask) {
1819 fix |= 1 << i;
1820 opencode |= 1 << i;
1821 }
1822 }
1823 }
1824
1825 while (fix) {
1826 unsigned i = u_bit_scan(&fix);
1827 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1828 }
1829 key->mono.vs_fetch_opencode = opencode;
1830 }
1831
1832 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1833 struct si_shader_selector *vs,
1834 struct si_shader_key *key)
1835 {
1836 struct si_shader_selector *ps = sctx->ps_shader.cso;
1837
1838 key->opt.clip_disable =
1839 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1840 (vs->info.clipdist_writemask ||
1841 vs->info.writes_clipvertex) &&
1842 !vs->info.culldist_writemask;
1843
1844 /* Find out if PS is disabled. */
1845 bool ps_disabled = true;
1846 if (ps) {
1847 bool ps_modifies_zs = ps->info.uses_kill ||
1848 ps->info.writes_z ||
1849 ps->info.writes_stencil ||
1850 ps->info.writes_samplemask ||
1851 sctx->queued.named.blend->alpha_to_coverage ||
1852 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1853 unsigned ps_colormask = si_get_total_colormask(sctx);
1854
1855 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1856 (!ps_colormask &&
1857 !ps_modifies_zs &&
1858 !ps->info.writes_memory);
1859 }
1860
1861 /* Find out which VS outputs aren't used by the PS. */
1862 uint64_t outputs_written = vs->outputs_written_before_ps;
1863 uint64_t inputs_read = 0;
1864
1865 /* Ignore outputs that are not passed from VS to PS. */
1866 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1867 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1868 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1869
1870 if (!ps_disabled) {
1871 inputs_read = ps->inputs_read;
1872 }
1873
1874 uint64_t linked = outputs_written & inputs_read;
1875
1876 key->opt.kill_outputs = ~linked & outputs_written;
1877 }
1878
1879 /* Compute the key for the hw shader variant */
1880 static inline void si_shader_selector_key(struct pipe_context *ctx,
1881 struct si_shader_selector *sel,
1882 union si_vgt_stages_key stages_key,
1883 struct si_shader_key *key)
1884 {
1885 struct si_context *sctx = (struct si_context *)ctx;
1886
1887 memset(key, 0, sizeof(*key));
1888
1889 switch (sel->type) {
1890 case PIPE_SHADER_VERTEX:
1891 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1892
1893 if (sctx->tes_shader.cso)
1894 key->as_ls = 1;
1895 else if (sctx->gs_shader.cso) {
1896 key->as_es = 1;
1897 key->as_ngg = stages_key.u.ngg;
1898 } else {
1899 key->as_ngg = stages_key.u.ngg;
1900 si_shader_selector_key_hw_vs(sctx, sel, key);
1901
1902 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1903 key->mono.u.vs_export_prim_id = 1;
1904 }
1905 break;
1906 case PIPE_SHADER_TESS_CTRL:
1907 if (sctx->chip_class >= GFX9) {
1908 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1909 key, &key->part.tcs.ls_prolog);
1910 key->part.tcs.ls = sctx->vs_shader.cso;
1911
1912 /* When the LS VGPR fix is needed, monolithic shaders
1913 * can:
1914 * - avoid initializing EXEC in both the LS prolog
1915 * and the LS main part when !vs_needs_prolog
1916 * - remove the fixup for unused input VGPRs
1917 */
1918 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1919
1920 /* The LS output / HS input layout can be communicated
1921 * directly instead of via user SGPRs for merged LS-HS.
1922 * The LS VGPR fix prefers this too.
1923 */
1924 key->opt.prefer_mono = 1;
1925 }
1926
1927 key->part.tcs.epilog.prim_mode =
1928 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1929 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1930 sel->info.tessfactors_are_def_in_all_invocs;
1931 key->part.tcs.epilog.tes_reads_tess_factors =
1932 sctx->tes_shader.cso->info.reads_tess_factors;
1933
1934 if (sel == sctx->fixed_func_tcs_shader.cso)
1935 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1936 break;
1937 case PIPE_SHADER_TESS_EVAL:
1938 key->as_ngg = stages_key.u.ngg;
1939
1940 if (sctx->gs_shader.cso)
1941 key->as_es = 1;
1942 else {
1943 si_shader_selector_key_hw_vs(sctx, sel, key);
1944
1945 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1946 key->mono.u.vs_export_prim_id = 1;
1947 }
1948 break;
1949 case PIPE_SHADER_GEOMETRY:
1950 if (sctx->chip_class >= GFX9) {
1951 if (sctx->tes_shader.cso) {
1952 key->part.gs.es = sctx->tes_shader.cso;
1953 } else {
1954 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1955 key, &key->part.gs.vs_prolog);
1956 key->part.gs.es = sctx->vs_shader.cso;
1957 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1958 }
1959
1960 key->as_ngg = stages_key.u.ngg;
1961
1962 /* Merged ES-GS can have unbalanced wave usage.
1963 *
1964 * ES threads are per-vertex, while GS threads are
1965 * per-primitive. So without any amplification, there
1966 * are fewer GS threads than ES threads, which can result
1967 * in empty (no-op) GS waves. With too much amplification,
1968 * there are more GS threads than ES threads, which
1969 * can result in empty (no-op) ES waves.
1970 *
1971 * Non-monolithic shaders are implemented by setting EXEC
1972 * at the beginning of shader parts, and don't jump to
1973 * the end if EXEC is 0.
1974 *
1975 * Monolithic shaders use conditional blocks, so they can
1976 * jump and skip empty waves of ES or GS. So set this to
1977 * always use optimized variants, which are monolithic.
1978 */
1979 key->opt.prefer_mono = 1;
1980 }
1981 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1982 break;
1983 case PIPE_SHADER_FRAGMENT: {
1984 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1985 struct si_state_blend *blend = sctx->queued.named.blend;
1986
1987 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1988 sel->info.colors_written == 0x1)
1989 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1990
1991 /* Select the shader color format based on whether
1992 * blending or alpha are needed.
1993 */
1994 key->part.ps.epilog.spi_shader_col_format =
1995 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1996 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1997 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1998 sctx->framebuffer.spi_shader_col_format_blend) |
1999 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
2000 sctx->framebuffer.spi_shader_col_format_alpha) |
2001 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
2002 sctx->framebuffer.spi_shader_col_format);
2003 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
2004
2005 /* The output for dual source blending should have
2006 * the same format as the first output.
2007 */
2008 if (blend->dual_src_blend) {
2009 key->part.ps.epilog.spi_shader_col_format |=
2010 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
2011 }
2012
2013 /* If alpha-to-coverage is enabled, we have to export alpha
2014 * even if there is no color buffer.
2015 */
2016 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
2017 blend->alpha_to_coverage)
2018 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
2019
2020 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
2021 * to the range supported by the type if a channel has less
2022 * than 16 bits and the export format is 16_ABGR.
2023 */
2024 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
2025 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
2026 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
2027 }
2028
2029 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
2030 if (!key->part.ps.epilog.last_cbuf) {
2031 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
2032 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
2033 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
2034 }
2035
2036 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
2037 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
2038
2039 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
2040 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
2041
2042 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
2043 rs->multisample_enable;
2044
2045 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
2046 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
2047 (is_line && rs->line_smooth)) &&
2048 sctx->framebuffer.nr_samples <= 1;
2049 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2050
2051 if (sctx->ps_iter_samples > 1 &&
2052 sel->info.reads_samplemask) {
2053 key->part.ps.prolog.samplemask_log_ps_iter =
2054 util_logbase2(sctx->ps_iter_samples);
2055 }
2056
2057 if (rs->force_persample_interp &&
2058 rs->multisample_enable &&
2059 sctx->framebuffer.nr_samples > 1 &&
2060 sctx->ps_iter_samples > 1) {
2061 key->part.ps.prolog.force_persp_sample_interp =
2062 sel->info.uses_persp_center ||
2063 sel->info.uses_persp_centroid;
2064
2065 key->part.ps.prolog.force_linear_sample_interp =
2066 sel->info.uses_linear_center ||
2067 sel->info.uses_linear_centroid;
2068 } else if (rs->multisample_enable &&
2069 sctx->framebuffer.nr_samples > 1) {
2070 key->part.ps.prolog.bc_optimize_for_persp =
2071 sel->info.uses_persp_center &&
2072 sel->info.uses_persp_centroid;
2073 key->part.ps.prolog.bc_optimize_for_linear =
2074 sel->info.uses_linear_center &&
2075 sel->info.uses_linear_centroid;
2076 } else {
2077 /* Make sure SPI doesn't compute more than 1 pair
2078 * of (i,j), which is the optimization here. */
2079 key->part.ps.prolog.force_persp_center_interp =
2080 sel->info.uses_persp_center +
2081 sel->info.uses_persp_centroid +
2082 sel->info.uses_persp_sample > 1;
2083
2084 key->part.ps.prolog.force_linear_center_interp =
2085 sel->info.uses_linear_center +
2086 sel->info.uses_linear_centroid +
2087 sel->info.uses_linear_sample > 1;
2088
2089 if (sel->info.uses_persp_opcode_interp_sample ||
2090 sel->info.uses_linear_opcode_interp_sample)
2091 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2092 }
2093
2094 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2095
2096 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2097 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2098 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2099 struct pipe_resource *tex = cb0->texture;
2100
2101 /* 1D textures are allocated and used as 2D on GFX9. */
2102 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2103 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2104 (tex->target == PIPE_TEXTURE_1D ||
2105 tex->target == PIPE_TEXTURE_1D_ARRAY);
2106 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2107 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2108 tex->target == PIPE_TEXTURE_CUBE ||
2109 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2110 tex->target == PIPE_TEXTURE_3D;
2111 }
2112 break;
2113 }
2114 default:
2115 assert(0);
2116 }
2117
2118 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2119 memset(&key->opt, 0, sizeof(key->opt));
2120 }
2121
2122 static void si_build_shader_variant(struct si_shader *shader,
2123 int thread_index,
2124 bool low_priority)
2125 {
2126 struct si_shader_selector *sel = shader->selector;
2127 struct si_screen *sscreen = sel->screen;
2128 struct ac_llvm_compiler *compiler;
2129 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2130
2131 if (thread_index >= 0) {
2132 if (low_priority) {
2133 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2134 compiler = &sscreen->compiler_lowp[thread_index];
2135 } else {
2136 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2137 compiler = &sscreen->compiler[thread_index];
2138 }
2139 if (!debug->async)
2140 debug = NULL;
2141 } else {
2142 assert(!low_priority);
2143 compiler = shader->compiler_ctx_state.compiler;
2144 }
2145
2146 if (!compiler->passes)
2147 si_init_compiler(sscreen, compiler);
2148
2149 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2150 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2151 sel->type);
2152 shader->compilation_failed = true;
2153 return;
2154 }
2155
2156 if (shader->compiler_ctx_state.is_debug_context) {
2157 FILE *f = open_memstream(&shader->shader_log,
2158 &shader->shader_log_size);
2159 if (f) {
2160 si_shader_dump(sscreen, shader, NULL, f, false);
2161 fclose(f);
2162 }
2163 }
2164
2165 si_shader_init_pm4_state(sscreen, shader);
2166 }
2167
2168 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2169 {
2170 struct si_shader *shader = (struct si_shader *)job;
2171
2172 assert(thread_index >= 0);
2173
2174 si_build_shader_variant(shader, thread_index, true);
2175 }
2176
2177 static const struct si_shader_key zeroed;
2178
2179 static bool si_check_missing_main_part(struct si_screen *sscreen,
2180 struct si_shader_selector *sel,
2181 struct si_compiler_ctx_state *compiler_state,
2182 struct si_shader_key *key)
2183 {
2184 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2185
2186 if (!*mainp) {
2187 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2188
2189 if (!main_part)
2190 return false;
2191
2192 /* We can leave the fence as permanently signaled because the
2193 * main part becomes visible globally only after it has been
2194 * compiled. */
2195 util_queue_fence_init(&main_part->ready);
2196
2197 main_part->selector = sel;
2198 main_part->key.as_es = key->as_es;
2199 main_part->key.as_ls = key->as_ls;
2200 main_part->key.as_ngg = key->as_ngg;
2201 main_part->is_monolithic = false;
2202
2203 if (si_compile_shader(sscreen, compiler_state->compiler,
2204 main_part, &compiler_state->debug) != 0) {
2205 FREE(main_part);
2206 return false;
2207 }
2208 *mainp = main_part;
2209 }
2210 return true;
2211 }
2212
2213 /**
2214 * Select a shader variant according to the shader key.
2215 *
2216 * \param optimized_or_none If the key describes an optimized shader variant and
2217 * the compilation isn't finished, don't select any
2218 * shader and return an error.
2219 */
2220 int si_shader_select_with_key(struct si_screen *sscreen,
2221 struct si_shader_ctx_state *state,
2222 struct si_compiler_ctx_state *compiler_state,
2223 struct si_shader_key *key,
2224 int thread_index,
2225 bool optimized_or_none)
2226 {
2227 struct si_shader_selector *sel = state->cso;
2228 struct si_shader_selector *previous_stage_sel = NULL;
2229 struct si_shader *current = state->current;
2230 struct si_shader *iter, *shader = NULL;
2231
2232 again:
2233 /* Check if we don't need to change anything.
2234 * This path is also used for most shaders that don't need multiple
2235 * variants, it will cost just a computation of the key and this
2236 * test. */
2237 if (likely(current &&
2238 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2239 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2240 if (current->is_optimized) {
2241 if (optimized_or_none)
2242 return -1;
2243
2244 memset(&key->opt, 0, sizeof(key->opt));
2245 goto current_not_ready;
2246 }
2247
2248 util_queue_fence_wait(&current->ready);
2249 }
2250
2251 return current->compilation_failed ? -1 : 0;
2252 }
2253 current_not_ready:
2254
2255 /* This must be done before the mutex is locked, because async GS
2256 * compilation calls this function too, and therefore must enter
2257 * the mutex first.
2258 *
2259 * Only wait if we are in a draw call. Don't wait if we are
2260 * in a compiler thread.
2261 */
2262 if (thread_index < 0)
2263 util_queue_fence_wait(&sel->ready);
2264
2265 simple_mtx_lock(&sel->mutex);
2266
2267 /* Find the shader variant. */
2268 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2269 /* Don't check the "current" shader. We checked it above. */
2270 if (current != iter &&
2271 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2272 simple_mtx_unlock(&sel->mutex);
2273
2274 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2275 /* If it's an optimized shader and its compilation has
2276 * been started but isn't done, use the unoptimized
2277 * shader so as not to cause a stall due to compilation.
2278 */
2279 if (iter->is_optimized) {
2280 if (optimized_or_none)
2281 return -1;
2282 memset(&key->opt, 0, sizeof(key->opt));
2283 goto again;
2284 }
2285
2286 util_queue_fence_wait(&iter->ready);
2287 }
2288
2289 if (iter->compilation_failed) {
2290 return -1; /* skip the draw call */
2291 }
2292
2293 state->current = iter;
2294 return 0;
2295 }
2296 }
2297
2298 /* Build a new shader. */
2299 shader = CALLOC_STRUCT(si_shader);
2300 if (!shader) {
2301 simple_mtx_unlock(&sel->mutex);
2302 return -ENOMEM;
2303 }
2304
2305 util_queue_fence_init(&shader->ready);
2306
2307 shader->selector = sel;
2308 shader->key = *key;
2309 shader->compiler_ctx_state = *compiler_state;
2310
2311 /* If this is a merged shader, get the first shader's selector. */
2312 if (sscreen->info.chip_class >= GFX9) {
2313 if (sel->type == PIPE_SHADER_TESS_CTRL)
2314 previous_stage_sel = key->part.tcs.ls;
2315 else if (sel->type == PIPE_SHADER_GEOMETRY)
2316 previous_stage_sel = key->part.gs.es;
2317
2318 /* We need to wait for the previous shader. */
2319 if (previous_stage_sel && thread_index < 0)
2320 util_queue_fence_wait(&previous_stage_sel->ready);
2321 }
2322
2323 bool is_pure_monolithic =
2324 sscreen->use_monolithic_shaders ||
2325 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2326
2327 /* Compile the main shader part if it doesn't exist. This can happen
2328 * if the initial guess was wrong.
2329 *
2330 * The prim discard CS doesn't need the main shader part.
2331 */
2332 if (!is_pure_monolithic &&
2333 !key->opt.vs_as_prim_discard_cs) {
2334 bool ok = true;
2335
2336 /* Make sure the main shader part is present. This is needed
2337 * for shaders that can be compiled as VS, LS, or ES, and only
2338 * one of them is compiled at creation.
2339 *
2340 * It is also needed for GS, which can be compiled as non-NGG
2341 * and NGG.
2342 *
2343 * For merged shaders, check that the starting shader's main
2344 * part is present.
2345 */
2346 if (previous_stage_sel) {
2347 struct si_shader_key shader1_key = zeroed;
2348
2349 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2350 shader1_key.as_ls = 1;
2351 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2352 shader1_key.as_es = 1;
2353 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2354 } else {
2355 assert(0);
2356 }
2357
2358 simple_mtx_lock(&previous_stage_sel->mutex);
2359 ok = si_check_missing_main_part(sscreen,
2360 previous_stage_sel,
2361 compiler_state, &shader1_key);
2362 simple_mtx_unlock(&previous_stage_sel->mutex);
2363 }
2364
2365 if (ok) {
2366 ok = si_check_missing_main_part(sscreen, sel,
2367 compiler_state, key);
2368 }
2369
2370 if (!ok) {
2371 FREE(shader);
2372 simple_mtx_unlock(&sel->mutex);
2373 return -ENOMEM; /* skip the draw call */
2374 }
2375 }
2376
2377 /* Keep the reference to the 1st shader of merged shaders, so that
2378 * Gallium can't destroy it before we destroy the 2nd shader.
2379 *
2380 * Set sctx = NULL, because it's unused if we're not releasing
2381 * the shader, and we don't have any sctx here.
2382 */
2383 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2384 previous_stage_sel);
2385
2386 /* Monolithic-only shaders don't make a distinction between optimized
2387 * and unoptimized. */
2388 shader->is_monolithic =
2389 is_pure_monolithic ||
2390 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2391
2392 /* The prim discard CS is always optimized. */
2393 shader->is_optimized =
2394 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2395 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2396
2397 /* If it's an optimized shader, compile it asynchronously. */
2398 if (shader->is_optimized && thread_index < 0) {
2399 /* Compile it asynchronously. */
2400 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2401 shader, &shader->ready,
2402 si_build_shader_variant_low_priority, NULL,
2403 0);
2404
2405 /* Add only after the ready fence was reset, to guard against a
2406 * race with si_bind_XX_shader. */
2407 if (!sel->last_variant) {
2408 sel->first_variant = shader;
2409 sel->last_variant = shader;
2410 } else {
2411 sel->last_variant->next_variant = shader;
2412 sel->last_variant = shader;
2413 }
2414
2415 /* Use the default (unoptimized) shader for now. */
2416 memset(&key->opt, 0, sizeof(key->opt));
2417 simple_mtx_unlock(&sel->mutex);
2418
2419 if (sscreen->options.sync_compile)
2420 util_queue_fence_wait(&shader->ready);
2421
2422 if (optimized_or_none)
2423 return -1;
2424 goto again;
2425 }
2426
2427 /* Reset the fence before adding to the variant list. */
2428 util_queue_fence_reset(&shader->ready);
2429
2430 if (!sel->last_variant) {
2431 sel->first_variant = shader;
2432 sel->last_variant = shader;
2433 } else {
2434 sel->last_variant->next_variant = shader;
2435 sel->last_variant = shader;
2436 }
2437
2438 simple_mtx_unlock(&sel->mutex);
2439
2440 assert(!shader->is_optimized);
2441 si_build_shader_variant(shader, thread_index, false);
2442
2443 util_queue_fence_signal(&shader->ready);
2444
2445 if (!shader->compilation_failed)
2446 state->current = shader;
2447
2448 return shader->compilation_failed ? -1 : 0;
2449 }
2450
2451 static int si_shader_select(struct pipe_context *ctx,
2452 struct si_shader_ctx_state *state,
2453 union si_vgt_stages_key stages_key,
2454 struct si_compiler_ctx_state *compiler_state)
2455 {
2456 struct si_context *sctx = (struct si_context *)ctx;
2457 struct si_shader_key key;
2458
2459 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2460 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2461 &key, -1, false);
2462 }
2463
2464 static void si_parse_next_shader_property(const struct si_shader_info *info,
2465 bool streamout,
2466 struct si_shader_key *key)
2467 {
2468 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2469
2470 switch (info->processor) {
2471 case PIPE_SHADER_VERTEX:
2472 switch (next_shader) {
2473 case PIPE_SHADER_GEOMETRY:
2474 key->as_es = 1;
2475 break;
2476 case PIPE_SHADER_TESS_CTRL:
2477 case PIPE_SHADER_TESS_EVAL:
2478 key->as_ls = 1;
2479 break;
2480 default:
2481 /* If POSITION isn't written, it can only be a HW VS
2482 * if streamout is used. If streamout isn't used,
2483 * assume that it's a HW LS. (the next shader is TCS)
2484 * This heuristic is needed for separate shader objects.
2485 */
2486 if (!info->writes_position && !streamout)
2487 key->as_ls = 1;
2488 }
2489 break;
2490
2491 case PIPE_SHADER_TESS_EVAL:
2492 if (next_shader == PIPE_SHADER_GEOMETRY ||
2493 !info->writes_position)
2494 key->as_es = 1;
2495 break;
2496 }
2497 }
2498
2499 /**
2500 * Compile the main shader part or the monolithic shader as part of
2501 * si_shader_selector initialization. Since it can be done asynchronously,
2502 * there is no way to report compile failures to applications.
2503 */
2504 static void si_init_shader_selector_async(void *job, int thread_index)
2505 {
2506 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2507 struct si_screen *sscreen = sel->screen;
2508 struct ac_llvm_compiler *compiler;
2509 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2510
2511 assert(!debug->debug_message || debug->async);
2512 assert(thread_index >= 0);
2513 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2514 compiler = &sscreen->compiler[thread_index];
2515
2516 if (!compiler->passes)
2517 si_init_compiler(sscreen, compiler);
2518
2519 /* Serialize NIR to save memory. Monolithic shader variants
2520 * have to deserialize NIR before compilation.
2521 */
2522 if (sel->nir) {
2523 struct blob blob;
2524 size_t size;
2525
2526 blob_init(&blob);
2527 /* true = remove optional debugging data to increase
2528 * the likehood of getting more shader cache hits.
2529 * It also drops variable names, so we'll save more memory.
2530 */
2531 nir_serialize(&blob, sel->nir, true);
2532 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2533 sel->nir_size = size;
2534 }
2535
2536 /* Compile the main shader part for use with a prolog and/or epilog.
2537 * If this fails, the driver will try to compile a monolithic shader
2538 * on demand.
2539 */
2540 if (!sscreen->use_monolithic_shaders) {
2541 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2542 unsigned char ir_sha1_cache_key[20];
2543
2544 if (!shader) {
2545 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2546 return;
2547 }
2548
2549 /* We can leave the fence signaled because use of the default
2550 * main part is guarded by the selector's ready fence. */
2551 util_queue_fence_init(&shader->ready);
2552
2553 shader->selector = sel;
2554 shader->is_monolithic = false;
2555 si_parse_next_shader_property(&sel->info,
2556 sel->so.num_outputs != 0,
2557 &shader->key);
2558
2559 if (sscreen->use_ngg &&
2560 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2561 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2562 sel->type == PIPE_SHADER_TESS_EVAL ||
2563 sel->type == PIPE_SHADER_GEOMETRY))
2564 shader->key.as_ngg = 1;
2565
2566 if (sel->nir) {
2567 si_get_ir_cache_key(sel, shader->key.as_ngg,
2568 shader->key.as_es, ir_sha1_cache_key);
2569 }
2570
2571 /* Try to load the shader from the shader cache. */
2572 simple_mtx_lock(&sscreen->shader_cache_mutex);
2573
2574 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2575 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2576 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2577 } else {
2578 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2579
2580 /* Compile the shader if it hasn't been loaded from the cache. */
2581 if (si_compile_shader(sscreen, compiler, shader,
2582 debug) != 0) {
2583 FREE(shader);
2584 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2585 return;
2586 }
2587
2588 simple_mtx_lock(&sscreen->shader_cache_mutex);
2589 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
2590 shader, true);
2591 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2592 }
2593
2594 *si_get_main_shader_part(sel, &shader->key) = shader;
2595
2596 /* Unset "outputs_written" flags for outputs converted to
2597 * DEFAULT_VAL, so that later inter-shader optimizations don't
2598 * try to eliminate outputs that don't exist in the final
2599 * shader.
2600 *
2601 * This is only done if non-monolithic shaders are enabled.
2602 */
2603 if ((sel->type == PIPE_SHADER_VERTEX ||
2604 sel->type == PIPE_SHADER_TESS_EVAL) &&
2605 !shader->key.as_ls &&
2606 !shader->key.as_es) {
2607 unsigned i;
2608
2609 for (i = 0; i < sel->info.num_outputs; i++) {
2610 unsigned offset = shader->info.vs_output_param_offset[i];
2611
2612 if (offset <= AC_EXP_PARAM_OFFSET_31)
2613 continue;
2614
2615 unsigned name = sel->info.output_semantic_name[i];
2616 unsigned index = sel->info.output_semantic_index[i];
2617 unsigned id;
2618
2619 switch (name) {
2620 case TGSI_SEMANTIC_GENERIC:
2621 /* don't process indices the function can't handle */
2622 if (index >= SI_MAX_IO_GENERIC)
2623 break;
2624 /* fall through */
2625 default:
2626 id = si_shader_io_get_unique_index(name, index, true);
2627 sel->outputs_written_before_ps &= ~(1ull << id);
2628 break;
2629 case TGSI_SEMANTIC_POSITION: /* ignore these */
2630 case TGSI_SEMANTIC_PSIZE:
2631 case TGSI_SEMANTIC_CLIPVERTEX:
2632 case TGSI_SEMANTIC_EDGEFLAG:
2633 break;
2634 }
2635 }
2636 }
2637 }
2638
2639 /* The GS copy shader is always pre-compiled. */
2640 if (sel->type == PIPE_SHADER_GEOMETRY &&
2641 (!sscreen->use_ngg ||
2642 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2643 sel->tess_turns_off_ngg)) {
2644 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2645 if (!sel->gs_copy_shader) {
2646 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2647 return;
2648 }
2649
2650 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2651 }
2652
2653 /* Free NIR. We only keep serialized NIR after this point. */
2654 if (sel->nir) {
2655 ralloc_free(sel->nir);
2656 sel->nir = NULL;
2657 }
2658 }
2659
2660 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2661 struct util_queue_fence *ready_fence,
2662 struct si_compiler_ctx_state *compiler_ctx_state,
2663 void *job, util_queue_execute_func execute)
2664 {
2665 util_queue_fence_init(ready_fence);
2666
2667 struct util_async_debug_callback async_debug;
2668 bool debug =
2669 (sctx->debug.debug_message && !sctx->debug.async) ||
2670 sctx->is_debug ||
2671 si_can_dump_shader(sctx->screen, processor);
2672
2673 if (debug) {
2674 u_async_debug_init(&async_debug);
2675 compiler_ctx_state->debug = async_debug.base;
2676 }
2677
2678 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2679 ready_fence, execute, NULL, 0);
2680
2681 if (debug) {
2682 util_queue_fence_wait(ready_fence);
2683 u_async_debug_drain(&async_debug, &sctx->debug);
2684 u_async_debug_cleanup(&async_debug);
2685 }
2686
2687 if (sctx->screen->options.sync_compile)
2688 util_queue_fence_wait(ready_fence);
2689 }
2690
2691 /* Return descriptor slot usage masks from the given shader info. */
2692 void si_get_active_slot_masks(const struct si_shader_info *info,
2693 uint32_t *const_and_shader_buffers,
2694 uint64_t *samplers_and_images)
2695 {
2696 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2697
2698 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2699 num_constbufs = util_last_bit(info->const_buffers_declared);
2700 /* two 8-byte images share one 16-byte slot */
2701 num_images = align(util_last_bit(info->images_declared), 2);
2702 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2703 num_samplers = util_last_bit(info->samplers_declared);
2704
2705 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2706 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2707 *const_and_shader_buffers =
2708 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2709
2710 /* The layout is:
2711 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2712 * - image[last] ... image[0] go to [31-last .. 31]
2713 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2714 *
2715 * FMASKs for images are placed separately, because MSAA images are rare,
2716 * and so we can benefit from a better cache hit rate if we keep image
2717 * descriptors together.
2718 */
2719 if (num_msaa_images)
2720 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2721
2722 start = si_get_image_slot(num_images - 1) / 2;
2723 *samplers_and_images =
2724 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2725 }
2726
2727 static void *si_create_shader_selector(struct pipe_context *ctx,
2728 const struct pipe_shader_state *state)
2729 {
2730 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2731 struct si_context *sctx = (struct si_context*)ctx;
2732 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2733 int i;
2734
2735 if (!sel)
2736 return NULL;
2737
2738 pipe_reference_init(&sel->reference, 1);
2739 sel->screen = sscreen;
2740 sel->compiler_ctx_state.debug = sctx->debug;
2741 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2742
2743 sel->so = state->stream_output;
2744
2745 if (state->type == PIPE_SHADER_IR_TGSI) {
2746 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2747 } else {
2748 assert(state->type == PIPE_SHADER_IR_NIR);
2749 sel->nir = state->ir.nir;
2750 }
2751
2752 si_nir_scan_shader(sel->nir, &sel->info);
2753 si_nir_adjust_driver_locations(sel->nir);
2754
2755 sel->type = sel->info.processor;
2756 p_atomic_inc(&sscreen->num_shaders_created);
2757 si_get_active_slot_masks(&sel->info,
2758 &sel->active_const_and_shader_buffers,
2759 &sel->active_samplers_and_images);
2760
2761 /* Record which streamout buffers are enabled. */
2762 for (i = 0; i < sel->so.num_outputs; i++) {
2763 sel->enabled_streamout_buffer_mask |=
2764 (1 << sel->so.output[i].output_buffer) <<
2765 (sel->so.output[i].stream * 4);
2766 }
2767
2768 sel->num_vs_inputs = sel->type == PIPE_SHADER_VERTEX &&
2769 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] ?
2770 sel->info.num_inputs : 0;
2771 sel->num_vbos_in_user_sgprs =
2772 MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2773
2774 /* The prolog is a no-op if there are no inputs. */
2775 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2776 sel->info.num_inputs &&
2777 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2778
2779 sel->force_correct_derivs_after_kill =
2780 sel->type == PIPE_SHADER_FRAGMENT &&
2781 sel->info.uses_derivatives &&
2782 sel->info.uses_kill &&
2783 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2784
2785 sel->prim_discard_cs_allowed =
2786 sel->type == PIPE_SHADER_VERTEX &&
2787 !sel->info.uses_bindless_images &&
2788 !sel->info.uses_bindless_samplers &&
2789 !sel->info.writes_memory &&
2790 !sel->info.writes_viewport_index &&
2791 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2792 !sel->so.num_outputs;
2793
2794 switch (sel->type) {
2795 case PIPE_SHADER_GEOMETRY:
2796 sel->gs_output_prim =
2797 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2798
2799 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2800 sel->rast_prim = sel->gs_output_prim;
2801 if (util_rast_prim_is_triangles(sel->rast_prim))
2802 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2803
2804 sel->gs_max_out_vertices =
2805 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2806 sel->gs_num_invocations =
2807 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2808 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2809 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2810 sel->gs_max_out_vertices;
2811
2812 sel->max_gs_stream = 0;
2813 for (i = 0; i < sel->so.num_outputs; i++)
2814 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2815 sel->so.output[i].stream);
2816
2817 sel->gs_input_verts_per_prim =
2818 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2819
2820 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2821 sel->tess_turns_off_ngg =
2822 sscreen->info.chip_class == GFX10 &&
2823 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2824 break;
2825
2826 case PIPE_SHADER_TESS_CTRL:
2827 /* Always reserve space for these. */
2828 sel->patch_outputs_written |=
2829 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2830 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2831 /* fall through */
2832 case PIPE_SHADER_VERTEX:
2833 case PIPE_SHADER_TESS_EVAL:
2834 for (i = 0; i < sel->info.num_outputs; i++) {
2835 unsigned name = sel->info.output_semantic_name[i];
2836 unsigned index = sel->info.output_semantic_index[i];
2837
2838 switch (name) {
2839 case TGSI_SEMANTIC_TESSINNER:
2840 case TGSI_SEMANTIC_TESSOUTER:
2841 case TGSI_SEMANTIC_PATCH:
2842 sel->patch_outputs_written |=
2843 1ull << si_shader_io_get_unique_index_patch(name, index);
2844 break;
2845
2846 case TGSI_SEMANTIC_GENERIC:
2847 /* don't process indices the function can't handle */
2848 if (index >= SI_MAX_IO_GENERIC)
2849 break;
2850 /* fall through */
2851 default:
2852 sel->outputs_written |=
2853 1ull << si_shader_io_get_unique_index(name, index, false);
2854 sel->outputs_written_before_ps |=
2855 1ull << si_shader_io_get_unique_index(name, index, true);
2856 break;
2857 case TGSI_SEMANTIC_EDGEFLAG:
2858 break;
2859 }
2860 }
2861 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2862 sel->lshs_vertex_stride = sel->esgs_itemsize;
2863
2864 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2865 * will start on a different bank. (except for the maximum 32*16).
2866 */
2867 if (sel->lshs_vertex_stride < 32*16)
2868 sel->lshs_vertex_stride += 4;
2869
2870 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2871 * conflicts, i.e. each vertex will start at a different bank.
2872 */
2873 if (sctx->chip_class >= GFX9)
2874 sel->esgs_itemsize += 4;
2875
2876 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2877
2878 /* Only for TES: */
2879 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2880 sel->rast_prim = PIPE_PRIM_POINTS;
2881 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2882 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2883 else
2884 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2885 break;
2886
2887 case PIPE_SHADER_FRAGMENT:
2888 for (i = 0; i < sel->info.num_inputs; i++) {
2889 unsigned name = sel->info.input_semantic_name[i];
2890 unsigned index = sel->info.input_semantic_index[i];
2891
2892 switch (name) {
2893 case TGSI_SEMANTIC_GENERIC:
2894 /* don't process indices the function can't handle */
2895 if (index >= SI_MAX_IO_GENERIC)
2896 break;
2897 /* fall through */
2898 default:
2899 sel->inputs_read |=
2900 1ull << si_shader_io_get_unique_index(name, index, true);
2901 break;
2902 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2903 break;
2904 }
2905 }
2906
2907 for (i = 0; i < 8; i++)
2908 if (sel->info.colors_written & (1 << i))
2909 sel->colors_written_4bit |= 0xf << (4 * i);
2910
2911 for (i = 0; i < sel->info.num_inputs; i++) {
2912 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2913 int index = sel->info.input_semantic_index[i];
2914 sel->color_attr_index[index] = i;
2915 }
2916 }
2917 break;
2918 default:;
2919 }
2920
2921 /* PA_CL_VS_OUT_CNTL */
2922 if (sctx->chip_class <= GFX9)
2923 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2924
2925 sel->clipdist_mask = sel->info.writes_clipvertex ?
2926 SIX_BITS : sel->info.clipdist_writemask;
2927 sel->culldist_mask = sel->info.culldist_writemask <<
2928 sel->info.num_written_clipdistance;
2929
2930 /* DB_SHADER_CONTROL */
2931 sel->db_shader_control =
2932 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2933 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2934 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2935 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2936
2937 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2938 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2939 sel->db_shader_control |=
2940 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2941 break;
2942 case TGSI_FS_DEPTH_LAYOUT_LESS:
2943 sel->db_shader_control |=
2944 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2945 break;
2946 }
2947
2948 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2949 *
2950 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2951 * --|-----------|------------|------------|--------------------|-------------------|-------------
2952 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2953 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2954 * 2 | false | true | n/a | LateZ | 1 | 0
2955 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2956 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2957 *
2958 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2959 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2960 *
2961 * Don't use ReZ without profiling !!!
2962 *
2963 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2964 * shaders.
2965 */
2966 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2967 /* Cases 3, 4. */
2968 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2969 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2970 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2971 } else if (sel->info.writes_memory) {
2972 /* Case 2. */
2973 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2974 S_02880C_EXEC_ON_HIER_FAIL(1);
2975 } else {
2976 /* Case 1. */
2977 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2978 }
2979
2980 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2981 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2982
2983 (void) simple_mtx_init(&sel->mutex, mtx_plain);
2984
2985 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2986 &sel->compiler_ctx_state, sel,
2987 si_init_shader_selector_async);
2988 return sel;
2989 }
2990
2991 static void si_update_streamout_state(struct si_context *sctx)
2992 {
2993 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2994
2995 if (!shader_with_so)
2996 return;
2997
2998 sctx->streamout.enabled_stream_buffers_mask =
2999 shader_with_so->enabled_streamout_buffer_mask;
3000 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
3001 }
3002
3003 static void si_update_clip_regs(struct si_context *sctx,
3004 struct si_shader_selector *old_hw_vs,
3005 struct si_shader *old_hw_vs_variant,
3006 struct si_shader_selector *next_hw_vs,
3007 struct si_shader *next_hw_vs_variant)
3008 {
3009 if (next_hw_vs &&
3010 (!old_hw_vs ||
3011 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
3012 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
3013 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
3014 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
3015 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
3016 !old_hw_vs_variant ||
3017 !next_hw_vs_variant ||
3018 old_hw_vs_variant->key.opt.clip_disable !=
3019 next_hw_vs_variant->key.opt.clip_disable))
3020 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3021 }
3022
3023 static void si_update_common_shader_state(struct si_context *sctx)
3024 {
3025 sctx->uses_bindless_samplers =
3026 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
3027 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
3028 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
3029 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
3030 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
3031 sctx->uses_bindless_images =
3032 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
3033 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
3034 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
3035 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3036 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3037 sctx->do_update_shaders = true;
3038 }
3039
3040 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3041 {
3042 struct si_context *sctx = (struct si_context *)ctx;
3043 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3044 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3045 struct si_shader_selector *sel = state;
3046
3047 if (sctx->vs_shader.cso == sel)
3048 return;
3049
3050 sctx->vs_shader.cso = sel;
3051 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3052 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3053
3054 if (si_update_ngg(sctx))
3055 si_shader_change_notify(sctx);
3056
3057 si_update_common_shader_state(sctx);
3058 si_update_vs_viewport_state(sctx);
3059 si_set_active_descriptors_for_shader(sctx, sel);
3060 si_update_streamout_state(sctx);
3061 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3062 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3063 }
3064
3065 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3066 {
3067 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3068 (sctx->tes_shader.cso &&
3069 sctx->tes_shader.cso->info.uses_primid) ||
3070 (sctx->tcs_shader.cso &&
3071 sctx->tcs_shader.cso->info.uses_primid) ||
3072 (sctx->gs_shader.cso &&
3073 sctx->gs_shader.cso->info.uses_primid) ||
3074 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3075 sctx->ps_shader.cso->info.uses_primid);
3076 }
3077
3078 bool si_update_ngg(struct si_context *sctx)
3079 {
3080 if (!sctx->screen->use_ngg) {
3081 assert(!sctx->ngg);
3082 return false;
3083 }
3084
3085 bool new_ngg = true;
3086
3087 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3088 sctx->gs_shader.cso->tess_turns_off_ngg) {
3089 new_ngg = false;
3090 } else if (!sctx->screen->use_ngg_streamout) {
3091 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3092
3093 if ((last && last->so.num_outputs) ||
3094 sctx->streamout.prims_gen_query_enabled)
3095 new_ngg = false;
3096 }
3097
3098 if (new_ngg != sctx->ngg) {
3099 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3100 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3101 * pointers are set.
3102 */
3103 if ((sctx->family == CHIP_NAVI10 ||
3104 sctx->family == CHIP_NAVI12 ||
3105 sctx->family == CHIP_NAVI14) &&
3106 !new_ngg)
3107 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3108
3109 sctx->ngg = new_ngg;
3110 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3111 return true;
3112 }
3113 return false;
3114 }
3115
3116 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3117 {
3118 struct si_context *sctx = (struct si_context *)ctx;
3119 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3120 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3121 struct si_shader_selector *sel = state;
3122 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3123 bool ngg_changed;
3124
3125 if (sctx->gs_shader.cso == sel)
3126 return;
3127
3128 sctx->gs_shader.cso = sel;
3129 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3130 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3131
3132 si_update_common_shader_state(sctx);
3133 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3134
3135 ngg_changed = si_update_ngg(sctx);
3136 if (ngg_changed || enable_changed)
3137 si_shader_change_notify(sctx);
3138 if (enable_changed) {
3139 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3140 si_update_tess_uses_prim_id(sctx);
3141 }
3142 si_update_vs_viewport_state(sctx);
3143 si_set_active_descriptors_for_shader(sctx, sel);
3144 si_update_streamout_state(sctx);
3145 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3146 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3147 }
3148
3149 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3150 {
3151 struct si_context *sctx = (struct si_context *)ctx;
3152 struct si_shader_selector *sel = state;
3153 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3154
3155 if (sctx->tcs_shader.cso == sel)
3156 return;
3157
3158 sctx->tcs_shader.cso = sel;
3159 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3160 si_update_tess_uses_prim_id(sctx);
3161
3162 si_update_common_shader_state(sctx);
3163
3164 if (enable_changed)
3165 sctx->last_tcs = NULL; /* invalidate derived tess state */
3166
3167 si_set_active_descriptors_for_shader(sctx, sel);
3168 }
3169
3170 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3171 {
3172 struct si_context *sctx = (struct si_context *)ctx;
3173 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3174 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3175 struct si_shader_selector *sel = state;
3176 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3177
3178 if (sctx->tes_shader.cso == sel)
3179 return;
3180
3181 sctx->tes_shader.cso = sel;
3182 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3183 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3184 si_update_tess_uses_prim_id(sctx);
3185
3186 si_update_common_shader_state(sctx);
3187 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3188
3189 bool ngg_changed = si_update_ngg(sctx);
3190 if (ngg_changed || enable_changed)
3191 si_shader_change_notify(sctx);
3192 if (enable_changed)
3193 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3194 si_update_vs_viewport_state(sctx);
3195 si_set_active_descriptors_for_shader(sctx, sel);
3196 si_update_streamout_state(sctx);
3197 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3198 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3199 }
3200
3201 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3202 {
3203 struct si_context *sctx = (struct si_context *)ctx;
3204 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3205 struct si_shader_selector *sel = state;
3206
3207 /* skip if supplied shader is one already in use */
3208 if (old_sel == sel)
3209 return;
3210
3211 sctx->ps_shader.cso = sel;
3212 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3213
3214 si_update_common_shader_state(sctx);
3215 if (sel) {
3216 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3217 si_update_tess_uses_prim_id(sctx);
3218
3219 if (!old_sel ||
3220 old_sel->info.colors_written != sel->info.colors_written)
3221 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3222
3223 if (sctx->screen->has_out_of_order_rast &&
3224 (!old_sel ||
3225 old_sel->info.writes_memory != sel->info.writes_memory ||
3226 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3227 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3228 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3229 }
3230 si_set_active_descriptors_for_shader(sctx, sel);
3231 si_update_ps_colorbuf0_slot(sctx);
3232 }
3233
3234 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3235 {
3236 if (shader->is_optimized) {
3237 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3238 &shader->ready);
3239 }
3240
3241 util_queue_fence_destroy(&shader->ready);
3242
3243 if (shader->pm4) {
3244 /* If destroyed shaders were not unbound, the next compiled
3245 * shader variant could get the same pointer address and so
3246 * binding it to the same shader stage would be considered
3247 * a no-op, causing random behavior.
3248 */
3249 switch (shader->selector->type) {
3250 case PIPE_SHADER_VERTEX:
3251 if (shader->key.as_ls) {
3252 assert(sctx->chip_class <= GFX8);
3253 si_pm4_delete_state(sctx, ls, shader->pm4);
3254 } else if (shader->key.as_es) {
3255 assert(sctx->chip_class <= GFX8);
3256 si_pm4_delete_state(sctx, es, shader->pm4);
3257 } else if (shader->key.as_ngg) {
3258 si_pm4_delete_state(sctx, gs, shader->pm4);
3259 } else {
3260 si_pm4_delete_state(sctx, vs, shader->pm4);
3261 }
3262 break;
3263 case PIPE_SHADER_TESS_CTRL:
3264 si_pm4_delete_state(sctx, hs, shader->pm4);
3265 break;
3266 case PIPE_SHADER_TESS_EVAL:
3267 if (shader->key.as_es) {
3268 assert(sctx->chip_class <= GFX8);
3269 si_pm4_delete_state(sctx, es, shader->pm4);
3270 } else if (shader->key.as_ngg) {
3271 si_pm4_delete_state(sctx, gs, shader->pm4);
3272 } else {
3273 si_pm4_delete_state(sctx, vs, shader->pm4);
3274 }
3275 break;
3276 case PIPE_SHADER_GEOMETRY:
3277 if (shader->is_gs_copy_shader)
3278 si_pm4_delete_state(sctx, vs, shader->pm4);
3279 else
3280 si_pm4_delete_state(sctx, gs, shader->pm4);
3281 break;
3282 case PIPE_SHADER_FRAGMENT:
3283 si_pm4_delete_state(sctx, ps, shader->pm4);
3284 break;
3285 default:;
3286 }
3287 }
3288
3289 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3290 si_shader_destroy(shader);
3291 free(shader);
3292 }
3293
3294 void si_destroy_shader_selector(struct si_context *sctx,
3295 struct si_shader_selector *sel)
3296 {
3297 struct si_shader *p = sel->first_variant, *c;
3298 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3299 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3300 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3301 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3302 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3303 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3304 };
3305
3306 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3307
3308 if (current_shader[sel->type]->cso == sel) {
3309 current_shader[sel->type]->cso = NULL;
3310 current_shader[sel->type]->current = NULL;
3311 }
3312
3313 while (p) {
3314 c = p->next_variant;
3315 si_delete_shader(sctx, p);
3316 p = c;
3317 }
3318
3319 if (sel->main_shader_part)
3320 si_delete_shader(sctx, sel->main_shader_part);
3321 if (sel->main_shader_part_ls)
3322 si_delete_shader(sctx, sel->main_shader_part_ls);
3323 if (sel->main_shader_part_es)
3324 si_delete_shader(sctx, sel->main_shader_part_es);
3325 if (sel->main_shader_part_ngg)
3326 si_delete_shader(sctx, sel->main_shader_part_ngg);
3327 if (sel->gs_copy_shader)
3328 si_delete_shader(sctx, sel->gs_copy_shader);
3329
3330 util_queue_fence_destroy(&sel->ready);
3331 simple_mtx_destroy(&sel->mutex);
3332 ralloc_free(sel->nir);
3333 free(sel->nir_binary);
3334 free(sel);
3335 }
3336
3337 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3338 {
3339 struct si_context *sctx = (struct si_context *)ctx;
3340 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3341
3342 si_shader_selector_reference(sctx, &sel, NULL);
3343 }
3344
3345 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3346 struct si_shader *vs, unsigned name,
3347 unsigned index, unsigned interpolate)
3348 {
3349 struct si_shader_info *vsinfo = &vs->selector->info;
3350 unsigned j, offset, ps_input_cntl = 0;
3351
3352 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3353 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3354 name == TGSI_SEMANTIC_PRIMID)
3355 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3356
3357 if (name == TGSI_SEMANTIC_PCOORD ||
3358 (name == TGSI_SEMANTIC_TEXCOORD &&
3359 sctx->sprite_coord_enable & (1 << index))) {
3360 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3361 }
3362
3363 for (j = 0; j < vsinfo->num_outputs; j++) {
3364 if (name == vsinfo->output_semantic_name[j] &&
3365 index == vsinfo->output_semantic_index[j]) {
3366 offset = vs->info.vs_output_param_offset[j];
3367
3368 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3369 /* The input is loaded from parameter memory. */
3370 ps_input_cntl |= S_028644_OFFSET(offset);
3371 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3372 if (offset == AC_EXP_PARAM_UNDEFINED) {
3373 /* This can happen with depth-only rendering. */
3374 offset = 0;
3375 } else {
3376 /* The input is a DEFAULT_VAL constant. */
3377 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3378 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3379 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3380 }
3381
3382 ps_input_cntl = S_028644_OFFSET(0x20) |
3383 S_028644_DEFAULT_VAL(offset);
3384 }
3385 break;
3386 }
3387 }
3388
3389 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3390 /* PrimID is written after the last output when HW VS is used. */
3391 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3392 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3393 /* No corresponding output found, load defaults into input.
3394 * Don't set any other bits.
3395 * (FLAT_SHADE=1 completely changes behavior) */
3396 ps_input_cntl = S_028644_OFFSET(0x20);
3397 /* D3D 9 behaviour. GL is undefined */
3398 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3399 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3400 }
3401 return ps_input_cntl;
3402 }
3403
3404 static void si_emit_spi_map(struct si_context *sctx)
3405 {
3406 struct si_shader *ps = sctx->ps_shader.current;
3407 struct si_shader *vs = si_get_vs_state(sctx);
3408 struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3409 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3410 unsigned spi_ps_input_cntl[32];
3411
3412 if (!ps || !ps->selector->info.num_inputs)
3413 return;
3414
3415 num_interp = si_get_ps_num_interp(ps);
3416 assert(num_interp > 0);
3417
3418 for (i = 0; i < psinfo->num_inputs; i++) {
3419 unsigned name = psinfo->input_semantic_name[i];
3420 unsigned index = psinfo->input_semantic_index[i];
3421 unsigned interpolate = psinfo->input_interpolate[i];
3422
3423 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3424 index, interpolate);
3425
3426 if (name == TGSI_SEMANTIC_COLOR) {
3427 assert(index < ARRAY_SIZE(bcol_interp));
3428 bcol_interp[index] = interpolate;
3429 }
3430 }
3431
3432 if (ps->key.part.ps.prolog.color_two_side) {
3433 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3434
3435 for (i = 0; i < 2; i++) {
3436 if (!(psinfo->colors_read & (0xf << (i * 4))))
3437 continue;
3438
3439 spi_ps_input_cntl[num_written++] =
3440 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3441
3442 }
3443 }
3444 assert(num_interp == num_written);
3445
3446 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3447 /* Dota 2: Only ~16% of SPI map updates set different values. */
3448 /* Talos: Only ~9% of SPI map updates set different values. */
3449 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3450 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3451 spi_ps_input_cntl,
3452 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3453
3454 if (initial_cdw != sctx->gfx_cs->current.cdw)
3455 sctx->context_roll = true;
3456 }
3457
3458 /**
3459 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3460 */
3461 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3462 {
3463 if (sctx->init_config_has_vgt_flush)
3464 return;
3465
3466 /* Done by Vulkan before VGT_FLUSH. */
3467 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3468 si_pm4_cmd_add(sctx->init_config,
3469 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3470 si_pm4_cmd_end(sctx->init_config, false);
3471
3472 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3473 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3474 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3475 si_pm4_cmd_end(sctx->init_config, false);
3476 sctx->init_config_has_vgt_flush = true;
3477 }
3478
3479 /* Initialize state related to ESGS / GSVS ring buffers */
3480 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3481 {
3482 struct si_shader_selector *es =
3483 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3484 struct si_shader_selector *gs = sctx->gs_shader.cso;
3485 struct si_pm4_state *pm4;
3486
3487 /* Chip constants. */
3488 unsigned num_se = sctx->screen->info.max_se;
3489 unsigned wave_size = 64;
3490 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3491 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3492 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3493 */
3494 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3495 unsigned alignment = 256 * num_se;
3496 /* The maximum size is 63.999 MB per SE. */
3497 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3498
3499 /* Calculate the minimum size. */
3500 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3501 wave_size, alignment);
3502
3503 /* These are recommended sizes, not minimum sizes. */
3504 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3505 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3506 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3507 gs->max_gsvs_emit_size;
3508
3509 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3510 esgs_ring_size = align(esgs_ring_size, alignment);
3511 gsvs_ring_size = align(gsvs_ring_size, alignment);
3512
3513 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3514 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3515
3516 /* Some rings don't have to be allocated if shaders don't use them.
3517 * (e.g. no varyings between ES and GS or GS and VS)
3518 *
3519 * GFX9 doesn't have the ESGS ring.
3520 */
3521 bool update_esgs = sctx->chip_class <= GFX8 &&
3522 esgs_ring_size &&
3523 (!sctx->esgs_ring ||
3524 sctx->esgs_ring->width0 < esgs_ring_size);
3525 bool update_gsvs = gsvs_ring_size &&
3526 (!sctx->gsvs_ring ||
3527 sctx->gsvs_ring->width0 < gsvs_ring_size);
3528
3529 if (!update_esgs && !update_gsvs)
3530 return true;
3531
3532 if (update_esgs) {
3533 pipe_resource_reference(&sctx->esgs_ring, NULL);
3534 sctx->esgs_ring =
3535 pipe_aligned_buffer_create(sctx->b.screen,
3536 SI_RESOURCE_FLAG_UNMAPPABLE,
3537 PIPE_USAGE_DEFAULT,
3538 esgs_ring_size,
3539 sctx->screen->info.pte_fragment_size);
3540 if (!sctx->esgs_ring)
3541 return false;
3542 }
3543
3544 if (update_gsvs) {
3545 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3546 sctx->gsvs_ring =
3547 pipe_aligned_buffer_create(sctx->b.screen,
3548 SI_RESOURCE_FLAG_UNMAPPABLE,
3549 PIPE_USAGE_DEFAULT,
3550 gsvs_ring_size,
3551 sctx->screen->info.pte_fragment_size);
3552 if (!sctx->gsvs_ring)
3553 return false;
3554 }
3555
3556 /* Create the "init_config_gs_rings" state. */
3557 pm4 = CALLOC_STRUCT(si_pm4_state);
3558 if (!pm4)
3559 return false;
3560
3561 if (sctx->chip_class >= GFX7) {
3562 if (sctx->esgs_ring) {
3563 assert(sctx->chip_class <= GFX8);
3564 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3565 sctx->esgs_ring->width0 / 256);
3566 }
3567 if (sctx->gsvs_ring)
3568 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3569 sctx->gsvs_ring->width0 / 256);
3570 } else {
3571 if (sctx->esgs_ring)
3572 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3573 sctx->esgs_ring->width0 / 256);
3574 if (sctx->gsvs_ring)
3575 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3576 sctx->gsvs_ring->width0 / 256);
3577 }
3578
3579 /* Set the state. */
3580 if (sctx->init_config_gs_rings)
3581 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3582 sctx->init_config_gs_rings = pm4;
3583
3584 if (!sctx->init_config_has_vgt_flush) {
3585 si_init_config_add_vgt_flush(sctx);
3586 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3587 }
3588
3589 /* Flush the context to re-emit both init_config states. */
3590 sctx->initial_gfx_cs_size = 0; /* force flush */
3591 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3592
3593 /* Set ring bindings. */
3594 if (sctx->esgs_ring) {
3595 assert(sctx->chip_class <= GFX8);
3596 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3597 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3598 true, true, 4, 64, 0);
3599 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3600 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3601 false, false, 0, 0, 0);
3602 }
3603 if (sctx->gsvs_ring) {
3604 si_set_ring_buffer(sctx, SI_RING_GSVS,
3605 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3606 false, false, 0, 0, 0);
3607 }
3608
3609 return true;
3610 }
3611
3612 static void si_shader_lock(struct si_shader *shader)
3613 {
3614 simple_mtx_lock(&shader->selector->mutex);
3615 if (shader->previous_stage_sel) {
3616 assert(shader->previous_stage_sel != shader->selector);
3617 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3618 }
3619 }
3620
3621 static void si_shader_unlock(struct si_shader *shader)
3622 {
3623 if (shader->previous_stage_sel)
3624 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3625 simple_mtx_unlock(&shader->selector->mutex);
3626 }
3627
3628 /**
3629 * @returns 1 if \p sel has been updated to use a new scratch buffer
3630 * 0 if not
3631 * < 0 if there was a failure
3632 */
3633 static int si_update_scratch_buffer(struct si_context *sctx,
3634 struct si_shader *shader)
3635 {
3636 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3637
3638 if (!shader)
3639 return 0;
3640
3641 /* This shader doesn't need a scratch buffer */
3642 if (shader->config.scratch_bytes_per_wave == 0)
3643 return 0;
3644
3645 /* Prevent race conditions when updating:
3646 * - si_shader::scratch_bo
3647 * - si_shader::binary::code
3648 * - si_shader::previous_stage::binary::code.
3649 */
3650 si_shader_lock(shader);
3651
3652 /* This shader is already configured to use the current
3653 * scratch buffer. */
3654 if (shader->scratch_bo == sctx->scratch_buffer) {
3655 si_shader_unlock(shader);
3656 return 0;
3657 }
3658
3659 assert(sctx->scratch_buffer);
3660
3661 /* Replace the shader bo with a new bo that has the relocs applied. */
3662 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3663 si_shader_unlock(shader);
3664 return -1;
3665 }
3666
3667 /* Update the shader state to use the new shader bo. */
3668 si_shader_init_pm4_state(sctx->screen, shader);
3669
3670 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3671
3672 si_shader_unlock(shader);
3673 return 1;
3674 }
3675
3676 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3677 {
3678 return shader ? shader->config.scratch_bytes_per_wave : 0;
3679 }
3680
3681 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3682 {
3683 if (!sctx->tes_shader.cso)
3684 return NULL; /* tessellation disabled */
3685
3686 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3687 sctx->fixed_func_tcs_shader.current;
3688 }
3689
3690 static bool si_update_scratch_relocs(struct si_context *sctx)
3691 {
3692 struct si_shader *tcs = si_get_tcs_current(sctx);
3693 int r;
3694
3695 /* Update the shaders, so that they are using the latest scratch.
3696 * The scratch buffer may have been changed since these shaders were
3697 * last used, so we still need to try to update them, even if they
3698 * require scratch buffers smaller than the current size.
3699 */
3700 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3701 if (r < 0)
3702 return false;
3703 if (r == 1)
3704 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3705
3706 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3707 if (r < 0)
3708 return false;
3709 if (r == 1)
3710 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3711
3712 r = si_update_scratch_buffer(sctx, tcs);
3713 if (r < 0)
3714 return false;
3715 if (r == 1)
3716 si_pm4_bind_state(sctx, hs, tcs->pm4);
3717
3718 /* VS can be bound as LS, ES, or VS. */
3719 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3720 if (r < 0)
3721 return false;
3722 if (r == 1) {
3723 if (sctx->vs_shader.current->key.as_ls)
3724 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3725 else if (sctx->vs_shader.current->key.as_es)
3726 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3727 else if (sctx->vs_shader.current->key.as_ngg)
3728 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3729 else
3730 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3731 }
3732
3733 /* TES can be bound as ES or VS. */
3734 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3735 if (r < 0)
3736 return false;
3737 if (r == 1) {
3738 if (sctx->tes_shader.current->key.as_es)
3739 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3740 else if (sctx->tes_shader.current->key.as_ngg)
3741 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3742 else
3743 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3744 }
3745
3746 return true;
3747 }
3748
3749 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3750 {
3751 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3752 * There are 2 cases to handle:
3753 *
3754 * - If the current needed size is less than the maximum seen size,
3755 * use the maximum seen size, so that WAVESIZE remains the same.
3756 *
3757 * - If the current needed size is greater than the maximum seen size,
3758 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3759 *
3760 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3761 * Otherwise, the number of waves that can use scratch is
3762 * SPI_TMPRING_SIZE.WAVES.
3763 */
3764 unsigned bytes = 0;
3765
3766 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3767 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3768 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3769
3770 if (sctx->tes_shader.cso) {
3771 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3772 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3773 }
3774
3775 sctx->max_seen_scratch_bytes_per_wave =
3776 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3777
3778 unsigned scratch_needed_size =
3779 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3780 unsigned spi_tmpring_size;
3781
3782 if (scratch_needed_size > 0) {
3783 if (!sctx->scratch_buffer ||
3784 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3785 /* Create a bigger scratch buffer */
3786 si_resource_reference(&sctx->scratch_buffer, NULL);
3787
3788 sctx->scratch_buffer =
3789 si_aligned_buffer_create(&sctx->screen->b,
3790 SI_RESOURCE_FLAG_UNMAPPABLE,
3791 PIPE_USAGE_DEFAULT,
3792 scratch_needed_size,
3793 sctx->screen->info.pte_fragment_size);
3794 if (!sctx->scratch_buffer)
3795 return false;
3796
3797 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3798 si_context_add_resource_size(sctx,
3799 &sctx->scratch_buffer->b.b);
3800 }
3801
3802 if (!si_update_scratch_relocs(sctx))
3803 return false;
3804 }
3805
3806 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3807 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3808 "scratch size should already be aligned correctly.");
3809
3810 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3811 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3812 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3813 sctx->spi_tmpring_size = spi_tmpring_size;
3814 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3815 }
3816 return true;
3817 }
3818
3819 static void si_init_tess_factor_ring(struct si_context *sctx)
3820 {
3821 assert(!sctx->tess_rings);
3822 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3823
3824 /* The address must be aligned to 2^19, because the shader only
3825 * receives the high 13 bits.
3826 */
3827 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3828 SI_RESOURCE_FLAG_32BIT,
3829 PIPE_USAGE_DEFAULT,
3830 sctx->screen->tess_offchip_ring_size +
3831 sctx->screen->tess_factor_ring_size,
3832 1 << 19);
3833 if (!sctx->tess_rings)
3834 return;
3835
3836 si_init_config_add_vgt_flush(sctx);
3837
3838 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3839 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3840
3841 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3842 sctx->screen->tess_offchip_ring_size;
3843
3844 /* Append these registers to the init config state. */
3845 if (sctx->chip_class >= GFX7) {
3846 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3847 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3848 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3849 factor_va >> 8);
3850 if (sctx->chip_class >= GFX10)
3851 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3852 S_030984_BASE_HI(factor_va >> 40));
3853 else if (sctx->chip_class == GFX9)
3854 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3855 S_030944_BASE_HI(factor_va >> 40));
3856 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3857 sctx->screen->vgt_hs_offchip_param);
3858 } else {
3859 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3860 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3861 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3862 factor_va >> 8);
3863 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3864 sctx->screen->vgt_hs_offchip_param);
3865 }
3866
3867 /* Flush the context to re-emit the init_config state.
3868 * This is done only once in a lifetime of a context.
3869 */
3870 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3871 sctx->initial_gfx_cs_size = 0; /* force flush */
3872 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3873 }
3874
3875 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3876 union si_vgt_stages_key key)
3877 {
3878 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3879 uint32_t stages = 0;
3880
3881 if (key.u.tess) {
3882 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3883 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3884
3885 if (key.u.gs)
3886 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3887 S_028B54_GS_EN(1);
3888 else if (key.u.ngg)
3889 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3890 else
3891 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3892 } else if (key.u.gs) {
3893 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3894 S_028B54_GS_EN(1);
3895 } else if (key.u.ngg) {
3896 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3897 }
3898
3899 if (key.u.ngg) {
3900 stages |= S_028B54_PRIMGEN_EN(1) |
3901 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3902 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3903 } else if (key.u.gs)
3904 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3905
3906 if (screen->info.chip_class >= GFX9)
3907 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3908
3909 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3910 stages |= S_028B54_HS_W32_EN(1) |
3911 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3912 S_028B54_VS_W32_EN(1);
3913 }
3914
3915 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3916 return pm4;
3917 }
3918
3919 static void si_update_vgt_shader_config(struct si_context *sctx,
3920 union si_vgt_stages_key key)
3921 {
3922 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3923
3924 if (unlikely(!*pm4))
3925 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3926 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3927 }
3928
3929 bool si_update_shaders(struct si_context *sctx)
3930 {
3931 struct pipe_context *ctx = (struct pipe_context*)sctx;
3932 struct si_compiler_ctx_state compiler_state;
3933 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3934 struct si_shader *old_vs = si_get_vs_state(sctx);
3935 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3936 struct si_shader *old_ps = sctx->ps_shader.current;
3937 union si_vgt_stages_key key;
3938 unsigned old_spi_shader_col_format =
3939 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3940 int r;
3941
3942 if (!sctx->compiler.passes)
3943 si_init_compiler(sctx->screen, &sctx->compiler);
3944
3945 compiler_state.compiler = &sctx->compiler;
3946 compiler_state.debug = sctx->debug;
3947 compiler_state.is_debug_context = sctx->is_debug;
3948
3949 key.index = 0;
3950
3951 if (sctx->tes_shader.cso)
3952 key.u.tess = 1;
3953 if (sctx->gs_shader.cso)
3954 key.u.gs = 1;
3955
3956 if (sctx->ngg) {
3957 key.u.ngg = 1;
3958 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3959 }
3960
3961 /* Update TCS and TES. */
3962 if (sctx->tes_shader.cso) {
3963 if (!sctx->tess_rings) {
3964 si_init_tess_factor_ring(sctx);
3965 if (!sctx->tess_rings)
3966 return false;
3967 }
3968
3969 if (sctx->tcs_shader.cso) {
3970 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3971 &compiler_state);
3972 if (r)
3973 return false;
3974 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3975 } else {
3976 if (!sctx->fixed_func_tcs_shader.cso) {
3977 sctx->fixed_func_tcs_shader.cso =
3978 si_create_fixed_func_tcs(sctx);
3979 if (!sctx->fixed_func_tcs_shader.cso)
3980 return false;
3981 }
3982
3983 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3984 key, &compiler_state);
3985 if (r)
3986 return false;
3987 si_pm4_bind_state(sctx, hs,
3988 sctx->fixed_func_tcs_shader.current->pm4);
3989 }
3990
3991 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3992 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3993 if (r)
3994 return false;
3995
3996 if (sctx->gs_shader.cso) {
3997 /* TES as ES */
3998 assert(sctx->chip_class <= GFX8);
3999 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
4000 } else if (key.u.ngg) {
4001 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
4002 } else {
4003 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
4004 }
4005 }
4006 } else {
4007 if (sctx->chip_class <= GFX8)
4008 si_pm4_bind_state(sctx, ls, NULL);
4009 si_pm4_bind_state(sctx, hs, NULL);
4010 }
4011
4012 /* Update GS. */
4013 if (sctx->gs_shader.cso) {
4014 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
4015 if (r)
4016 return false;
4017 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
4018 if (!key.u.ngg) {
4019 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
4020
4021 if (!si_update_gs_ring_buffers(sctx))
4022 return false;
4023 } else {
4024 si_pm4_bind_state(sctx, vs, NULL);
4025 }
4026 } else {
4027 if (!key.u.ngg) {
4028 si_pm4_bind_state(sctx, gs, NULL);
4029 if (sctx->chip_class <= GFX8)
4030 si_pm4_bind_state(sctx, es, NULL);
4031 }
4032 }
4033
4034 /* Update VS. */
4035 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
4036 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
4037 if (r)
4038 return false;
4039
4040 if (!key.u.tess && !key.u.gs) {
4041 if (key.u.ngg) {
4042 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
4043 si_pm4_bind_state(sctx, vs, NULL);
4044 } else {
4045 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4046 }
4047 } else if (sctx->tes_shader.cso) {
4048 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4049 } else {
4050 assert(sctx->gs_shader.cso);
4051 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4052 }
4053 }
4054
4055 /* This must be done after the shader variant is selected. */
4056 if (sctx->ngg)
4057 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(si_get_vs(sctx)->current);
4058
4059 si_update_vgt_shader_config(sctx, key);
4060
4061 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4062 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4063
4064 if (sctx->ps_shader.cso) {
4065 unsigned db_shader_control;
4066
4067 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4068 if (r)
4069 return false;
4070 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4071
4072 db_shader_control =
4073 sctx->ps_shader.cso->db_shader_control |
4074 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4075
4076 if (si_pm4_state_changed(sctx, ps) ||
4077 si_pm4_state_changed(sctx, vs) ||
4078 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4079 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4080 sctx->flatshade != rs->flatshade) {
4081 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4082 sctx->flatshade = rs->flatshade;
4083 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4084 }
4085
4086 if (sctx->screen->info.rbplus_allowed &&
4087 si_pm4_state_changed(sctx, ps) &&
4088 (!old_ps ||
4089 old_spi_shader_col_format !=
4090 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4091 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4092
4093 if (sctx->ps_db_shader_control != db_shader_control) {
4094 sctx->ps_db_shader_control = db_shader_control;
4095 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4096 if (sctx->screen->dpbb_allowed)
4097 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4098 }
4099
4100 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4101 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4102 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4103
4104 if (sctx->chip_class == GFX6)
4105 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4106
4107 if (sctx->framebuffer.nr_samples <= 1)
4108 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4109 }
4110 }
4111
4112 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4113 si_pm4_state_enabled_and_changed(sctx, hs) ||
4114 si_pm4_state_enabled_and_changed(sctx, es) ||
4115 si_pm4_state_enabled_and_changed(sctx, gs) ||
4116 si_pm4_state_enabled_and_changed(sctx, vs) ||
4117 si_pm4_state_enabled_and_changed(sctx, ps)) {
4118 if (!si_update_spi_tmpring_size(sctx))
4119 return false;
4120 }
4121
4122 if (sctx->chip_class >= GFX7) {
4123 if (si_pm4_state_enabled_and_changed(sctx, ls))
4124 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4125 else if (!sctx->queued.named.ls)
4126 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4127
4128 if (si_pm4_state_enabled_and_changed(sctx, hs))
4129 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4130 else if (!sctx->queued.named.hs)
4131 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4132
4133 if (si_pm4_state_enabled_and_changed(sctx, es))
4134 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4135 else if (!sctx->queued.named.es)
4136 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4137
4138 if (si_pm4_state_enabled_and_changed(sctx, gs))
4139 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4140 else if (!sctx->queued.named.gs)
4141 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4142
4143 if (si_pm4_state_enabled_and_changed(sctx, vs))
4144 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4145 else if (!sctx->queued.named.vs)
4146 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4147
4148 if (si_pm4_state_enabled_and_changed(sctx, ps))
4149 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4150 else if (!sctx->queued.named.ps)
4151 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4152 }
4153
4154 sctx->do_update_shaders = false;
4155 return true;
4156 }
4157
4158 static void si_emit_scratch_state(struct si_context *sctx)
4159 {
4160 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4161
4162 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4163 sctx->spi_tmpring_size);
4164
4165 if (sctx->scratch_buffer) {
4166 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4167 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4168 RADEON_PRIO_SCRATCH_BUFFER);
4169 }
4170 }
4171
4172 void si_init_shader_functions(struct si_context *sctx)
4173 {
4174 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4175 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4176
4177 sctx->b.create_vs_state = si_create_shader_selector;
4178 sctx->b.create_tcs_state = si_create_shader_selector;
4179 sctx->b.create_tes_state = si_create_shader_selector;
4180 sctx->b.create_gs_state = si_create_shader_selector;
4181 sctx->b.create_fs_state = si_create_shader_selector;
4182
4183 sctx->b.bind_vs_state = si_bind_vs_shader;
4184 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4185 sctx->b.bind_tes_state = si_bind_tes_shader;
4186 sctx->b.bind_gs_state = si_bind_gs_shader;
4187 sctx->b.bind_fs_state = si_bind_ps_shader;
4188
4189 sctx->b.delete_vs_state = si_delete_shader_selector;
4190 sctx->b.delete_tcs_state = si_delete_shader_selector;
4191 sctx->b.delete_tes_state = si_delete_shader_selector;
4192 sctx->b.delete_gs_state = si_delete_shader_selector;
4193 sctx->b.delete_fs_state = si_delete_shader_selector;
4194 }