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radeonsi: merge si_tessctrl_info into si_shader_info
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR key for the shader cache.
45 */
46 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
47 unsigned char ir_sha1_cache_key[20])
48 {
49 struct blob blob = {};
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->nir_binary) {
54 ir_binary = sel->nir_binary;
55 ir_size = sel->nir_size;
56 } else {
57 assert(sel->nir);
58
59 blob_init(&blob);
60 nir_serialize(&blob, sel->nir, true);
61 ir_binary = blob.data;
62 ir_size = blob.size;
63 }
64
65 /* These settings affect the compilation, but they are not derived
66 * from the input shader IR.
67 */
68 unsigned shader_variant_flags = 0;
69
70 if (ngg)
71 shader_variant_flags |= 1 << 0;
72 if (sel->nir)
73 shader_variant_flags |= 1 << 1;
74 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
75 shader_variant_flags |= 1 << 2;
76 if (sel->force_correct_derivs_after_kill)
77 shader_variant_flags |= 1 << 3;
78
79 struct mesa_sha1 ctx;
80 _mesa_sha1_init(&ctx);
81 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
82 _mesa_sha1_update(&ctx, ir_binary, ir_size);
83 if (sel->type == PIPE_SHADER_VERTEX ||
84 sel->type == PIPE_SHADER_TESS_EVAL ||
85 sel->type == PIPE_SHADER_GEOMETRY)
86 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
87 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
88
89 if (ir_binary == blob.data)
90 blob_finish(&blob);
91 }
92
93 /** Copy "data" to "ptr" and return the next dword following copied data. */
94 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
95 {
96 /* data may be NULL if size == 0 */
97 if (size)
98 memcpy(ptr, data, size);
99 ptr += DIV_ROUND_UP(size, 4);
100 return ptr;
101 }
102
103 /** Read data from "ptr". Return the next dword following the data. */
104 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
105 {
106 memcpy(data, ptr, size);
107 ptr += DIV_ROUND_UP(size, 4);
108 return ptr;
109 }
110
111 /**
112 * Write the size as uint followed by the data. Return the next dword
113 * following the copied data.
114 */
115 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
116 {
117 *ptr++ = size;
118 return write_data(ptr, data, size);
119 }
120
121 /**
122 * Read the size as uint followed by the data. Return both via parameters.
123 * Return the next dword following the data.
124 */
125 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
126 {
127 *size = *ptr++;
128 assert(*data == NULL);
129 if (!*size)
130 return ptr;
131 *data = malloc(*size);
132 return read_data(ptr, *data, *size);
133 }
134
135 /**
136 * Return the shader binary in a buffer. The first 4 bytes contain its size
137 * as integer.
138 */
139 static void *si_get_shader_binary(struct si_shader *shader)
140 {
141 /* There is always a size of data followed by the data itself. */
142 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
143 strlen(shader->binary.llvm_ir_string) + 1 : 0;
144
145 /* Refuse to allocate overly large buffers and guard against integer
146 * overflow. */
147 if (shader->binary.elf_size > UINT_MAX / 4 ||
148 llvm_ir_size > UINT_MAX / 4)
149 return NULL;
150
151 unsigned size =
152 4 + /* total size */
153 4 + /* CRC32 of the data below */
154 align(sizeof(shader->config), 4) +
155 align(sizeof(shader->info), 4) +
156 4 + align(shader->binary.elf_size, 4) +
157 4 + align(llvm_ir_size, 4);
158 void *buffer = CALLOC(1, size);
159 uint32_t *ptr = (uint32_t*)buffer;
160
161 if (!buffer)
162 return NULL;
163
164 *ptr++ = size;
165 ptr++; /* CRC32 is calculated at the end. */
166
167 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
168 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
169 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
170 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
171 assert((char *)ptr - (char *)buffer == size);
172
173 /* Compute CRC32. */
174 ptr = (uint32_t*)buffer;
175 ptr++;
176 *ptr = util_hash_crc32(ptr + 1, size - 8);
177
178 return buffer;
179 }
180
181 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
182 {
183 uint32_t *ptr = (uint32_t*)binary;
184 uint32_t size = *ptr++;
185 uint32_t crc32 = *ptr++;
186 unsigned chunk_size;
187 unsigned elf_size;
188
189 if (util_hash_crc32(ptr, size - 8) != crc32) {
190 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
191 return false;
192 }
193
194 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
195 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
196 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
197 &elf_size);
198 shader->binary.elf_size = elf_size;
199 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
200
201 return true;
202 }
203
204 /**
205 * Insert a shader into the cache. It's assumed the shader is not in the cache.
206 * Use si_shader_cache_load_shader before calling this.
207 */
208 void si_shader_cache_insert_shader(struct si_screen *sscreen,
209 unsigned char ir_sha1_cache_key[20],
210 struct si_shader *shader,
211 bool insert_into_disk_cache)
212 {
213 void *hw_binary;
214 struct hash_entry *entry;
215 uint8_t key[CACHE_KEY_SIZE];
216
217 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
218 if (entry)
219 return; /* already added */
220
221 hw_binary = si_get_shader_binary(shader);
222 if (!hw_binary)
223 return;
224
225 if (_mesa_hash_table_insert(sscreen->shader_cache,
226 mem_dup(ir_sha1_cache_key, 20),
227 hw_binary) == NULL) {
228 FREE(hw_binary);
229 return;
230 }
231
232 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
233 disk_cache_compute_key(sscreen->disk_shader_cache,
234 ir_sha1_cache_key, 20, key);
235 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
236 *((uint32_t *) hw_binary), NULL);
237 }
238 }
239
240 bool si_shader_cache_load_shader(struct si_screen *sscreen,
241 unsigned char ir_sha1_cache_key[20],
242 struct si_shader *shader)
243 {
244 struct hash_entry *entry =
245 _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
246 if (!entry) {
247 if (sscreen->disk_shader_cache) {
248 unsigned char sha1[CACHE_KEY_SIZE];
249
250 disk_cache_compute_key(sscreen->disk_shader_cache,
251 ir_sha1_cache_key, 20, sha1);
252
253 size_t binary_size;
254 uint8_t *buffer =
255 disk_cache_get(sscreen->disk_shader_cache,
256 sha1, &binary_size);
257 if (!buffer)
258 return false;
259
260 if (binary_size < sizeof(uint32_t) ||
261 *((uint32_t*)buffer) != binary_size) {
262 /* Something has gone wrong discard the item
263 * from the cache and rebuild/link from
264 * source.
265 */
266 assert(!"Invalid radeonsi shader disk cache "
267 "item!");
268
269 disk_cache_remove(sscreen->disk_shader_cache,
270 sha1);
271 free(buffer);
272
273 return false;
274 }
275
276 if (!si_load_shader_binary(shader, buffer)) {
277 free(buffer);
278 return false;
279 }
280 free(buffer);
281
282 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
283 shader, false);
284 } else {
285 return false;
286 }
287 } else {
288 if (!si_load_shader_binary(shader, entry->data))
289 return false;
290 }
291 p_atomic_inc(&sscreen->num_shader_cache_hits);
292 return true;
293 }
294
295 static uint32_t si_shader_cache_key_hash(const void *key)
296 {
297 /* Take the first dword of SHA1. */
298 return *(uint32_t*)key;
299 }
300
301 static bool si_shader_cache_key_equals(const void *a, const void *b)
302 {
303 /* Compare SHA1s. */
304 return memcmp(a, b, 20) == 0;
305 }
306
307 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
308 {
309 FREE((void*)entry->key);
310 FREE(entry->data);
311 }
312
313 bool si_init_shader_cache(struct si_screen *sscreen)
314 {
315 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
316 sscreen->shader_cache =
317 _mesa_hash_table_create(NULL,
318 si_shader_cache_key_hash,
319 si_shader_cache_key_equals);
320
321 return sscreen->shader_cache != NULL;
322 }
323
324 void si_destroy_shader_cache(struct si_screen *sscreen)
325 {
326 if (sscreen->shader_cache)
327 _mesa_hash_table_destroy(sscreen->shader_cache,
328 si_destroy_shader_cache_entry);
329 simple_mtx_destroy(&sscreen->shader_cache_mutex);
330 }
331
332 /* SHADER STATES */
333
334 static void si_set_tesseval_regs(struct si_screen *sscreen,
335 const struct si_shader_selector *tes,
336 struct si_pm4_state *pm4)
337 {
338 const struct si_shader_info *info = &tes->info;
339 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
340 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
341 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
342 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
343 unsigned type, partitioning, topology, distribution_mode;
344
345 switch (tes_prim_mode) {
346 case PIPE_PRIM_LINES:
347 type = V_028B6C_TESS_ISOLINE;
348 break;
349 case PIPE_PRIM_TRIANGLES:
350 type = V_028B6C_TESS_TRIANGLE;
351 break;
352 case PIPE_PRIM_QUADS:
353 type = V_028B6C_TESS_QUAD;
354 break;
355 default:
356 assert(0);
357 return;
358 }
359
360 switch (tes_spacing) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
362 partitioning = V_028B6C_PART_FRAC_ODD;
363 break;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
365 partitioning = V_028B6C_PART_FRAC_EVEN;
366 break;
367 case PIPE_TESS_SPACING_EQUAL:
368 partitioning = V_028B6C_PART_INTEGER;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 if (tes_point_mode)
376 topology = V_028B6C_OUTPUT_POINT;
377 else if (tes_prim_mode == PIPE_PRIM_LINES)
378 topology = V_028B6C_OUTPUT_LINE;
379 else if (tes_vertex_order_cw)
380 /* for some reason, this must be the other way around */
381 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
382 else
383 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
384
385 if (sscreen->info.has_distributed_tess) {
386 if (sscreen->info.family == CHIP_FIJI ||
387 sscreen->info.family >= CHIP_POLARIS10)
388 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
389 else
390 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
391 } else
392 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
393
394 assert(pm4->shader);
395 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
396 S_028B6C_PARTITIONING(partitioning) |
397 S_028B6C_TOPOLOGY(topology) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
399 }
400
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
403 *
404 * Possible VGT configurations and which state should set the register:
405 *
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
408 * VS as VS | VS | 30
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 *
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 */
415 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
416 struct si_shader_selector *sel,
417 struct si_shader *shader,
418 struct si_pm4_state *pm4)
419 {
420 unsigned type = sel->type;
421
422 if (sscreen->info.family < CHIP_POLARIS10 ||
423 sscreen->info.chip_class >= GFX10)
424 return;
425
426 /* VS as VS, or VS as ES: */
427 if ((type == PIPE_SHADER_VERTEX &&
428 (!shader ||
429 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
430 /* TES as VS, or TES as ES: */
431 type == PIPE_SHADER_TESS_EVAL) {
432 unsigned vtx_reuse_depth = 30;
433
434 if (type == PIPE_SHADER_TESS_EVAL &&
435 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD)
437 vtx_reuse_depth = 14;
438
439 assert(pm4->shader);
440 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
441 }
442 }
443
444 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
445 {
446 if (shader->pm4)
447 si_pm4_clear_state(shader->pm4);
448 else
449 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
450
451 if (shader->pm4) {
452 shader->pm4->shader = shader;
453 return shader->pm4;
454 } else {
455 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
456 return NULL;
457 }
458 }
459
460 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
461 unsigned num_always_on_user_sgprs)
462 {
463 struct si_shader_selector *vs = shader->previous_stage_sel ?
464 shader->previous_stage_sel : shader->selector;
465 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
466
467 /* 1 SGPR is reserved for the vertex buffer pointer. */
468 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
469
470 if (num_vbos_in_user_sgprs)
471 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
472
473 /* Add the pointer to VBO descriptors. */
474 return num_always_on_user_sgprs + 1;
475 }
476
477 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
478 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
479 struct si_shader *shader, bool legacy_vs_prim_id)
480 {
481 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
482 (shader->previous_stage_sel &&
483 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
484
485 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
486 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
487 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
488 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
489 */
490 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
491
492 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
493 return 3;
494 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
495 return 2;
496 else if (is_ls || shader->info.uses_instanceid)
497 return 1;
498 else
499 return 0;
500 }
501
502 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
503 {
504 struct si_pm4_state *pm4;
505 uint64_t va;
506
507 assert(sscreen->info.chip_class <= GFX8);
508
509 pm4 = si_get_shader_pm4_state(shader);
510 if (!pm4)
511 return;
512
513 va = shader->bo->gpu_address;
514 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
515
516 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
518
519 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
520 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
521 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
522 S_00B528_DX10_CLAMP(1) |
523 S_00B528_FLOAT_MODE(shader->config.float_mode);
524 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
525 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
526 }
527
528 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
529 {
530 struct si_pm4_state *pm4;
531 uint64_t va;
532
533 pm4 = si_get_shader_pm4_state(shader);
534 if (!pm4)
535 return;
536
537 va = shader->bo->gpu_address;
538 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
539
540 if (sscreen->info.chip_class >= GFX9) {
541 if (sscreen->info.chip_class >= GFX10) {
542 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
543 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
544 } else {
545 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
546 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
547 }
548
549 unsigned num_user_sgprs =
550 si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
551
552 shader->config.rsrc2 =
553 S_00B42C_USER_SGPR(num_user_sgprs) |
554 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
555
556 if (sscreen->info.chip_class >= GFX10)
557 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
558 else
559 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
560 } else {
561 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
562 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
563
564 shader->config.rsrc2 =
565 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
566 S_00B42C_OC_LDS_EN(1) |
567 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
568 }
569
570 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
571 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
572 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
573 (sscreen->info.chip_class <= GFX9 ?
574 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
575 S_00B428_DX10_CLAMP(1) |
576 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
577 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
578 S_00B428_FLOAT_MODE(shader->config.float_mode) |
579 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
580 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
581
582 if (sscreen->info.chip_class <= GFX8) {
583 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
584 shader->config.rsrc2);
585 }
586 }
587
588 static void si_emit_shader_es(struct si_context *sctx)
589 {
590 struct si_shader *shader = sctx->queued.named.es->shader;
591 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
592
593 if (!shader)
594 return;
595
596 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
597 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
598 shader->selector->esgs_itemsize / 4);
599
600 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
601 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
602 SI_TRACKED_VGT_TF_PARAM,
603 shader->vgt_tf_param);
604
605 if (shader->vgt_vertex_reuse_block_cntl)
606 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
607 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
608 shader->vgt_vertex_reuse_block_cntl);
609
610 if (initial_cdw != sctx->gfx_cs->current.cdw)
611 sctx->context_roll = true;
612 }
613
614 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
615 {
616 struct si_pm4_state *pm4;
617 unsigned num_user_sgprs;
618 unsigned vgpr_comp_cnt;
619 uint64_t va;
620 unsigned oc_lds_en;
621
622 assert(sscreen->info.chip_class <= GFX8);
623
624 pm4 = si_get_shader_pm4_state(shader);
625 if (!pm4)
626 return;
627
628 pm4->atom.emit = si_emit_shader_es;
629 va = shader->bo->gpu_address;
630 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
631
632 if (shader->selector->type == PIPE_SHADER_VERTEX) {
633 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
634 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
635 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
636 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
637 num_user_sgprs = SI_TES_NUM_USER_SGPR;
638 } else
639 unreachable("invalid shader selector type");
640
641 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
642
643 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
644 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
645 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
646 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
647 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
648 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
649 S_00B328_DX10_CLAMP(1) |
650 S_00B328_FLOAT_MODE(shader->config.float_mode));
651 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
652 S_00B32C_USER_SGPR(num_user_sgprs) |
653 S_00B32C_OC_LDS_EN(oc_lds_en) |
654 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
655
656 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
657 si_set_tesseval_regs(sscreen, shader->selector, pm4);
658
659 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
660 }
661
662 void gfx9_get_gs_info(struct si_shader_selector *es,
663 struct si_shader_selector *gs,
664 struct gfx9_gs_info *out)
665 {
666 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
667 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
668 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
669 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
670
671 /* All these are in dwords: */
672 /* We can't allow using the whole LDS, because GS waves compete with
673 * other shader stages for LDS space. */
674 const unsigned max_lds_size = 8 * 1024;
675 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
676 unsigned esgs_lds_size;
677
678 /* All these are per subgroup: */
679 const unsigned max_out_prims = 32 * 1024;
680 const unsigned max_es_verts = 255;
681 const unsigned ideal_gs_prims = 64;
682 unsigned max_gs_prims, gs_prims;
683 unsigned min_es_verts, es_verts, worst_case_es_verts;
684
685 if (uses_adjacency || gs_num_invocations > 1)
686 max_gs_prims = 127 / gs_num_invocations;
687 else
688 max_gs_prims = 255;
689
690 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
691 * Make sure we don't go over the maximum value.
692 */
693 if (gs->gs_max_out_vertices > 0) {
694 max_gs_prims = MIN2(max_gs_prims,
695 max_out_prims /
696 (gs->gs_max_out_vertices * gs_num_invocations));
697 }
698 assert(max_gs_prims > 0);
699
700 /* If the primitive has adjacency, halve the number of vertices
701 * that will be reused in multiple primitives.
702 */
703 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
704
705 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
706 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
707
708 /* Compute ESGS LDS size based on the worst case number of ES vertices
709 * needed to create the target number of GS prims per subgroup.
710 */
711 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
712
713 /* If total LDS usage is too big, refactor partitions based on ratio
714 * of ESGS item sizes.
715 */
716 if (esgs_lds_size > max_lds_size) {
717 /* Our target GS Prims Per Subgroup was too large. Calculate
718 * the maximum number of GS Prims Per Subgroup that will fit
719 * into LDS, capped by the maximum that the hardware can support.
720 */
721 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
722 max_gs_prims);
723 assert(gs_prims > 0);
724 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
725 max_es_verts);
726
727 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
728 assert(esgs_lds_size <= max_lds_size);
729 }
730
731 /* Now calculate remaining ESGS information. */
732 if (esgs_lds_size)
733 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
734 else
735 es_verts = max_es_verts;
736
737 /* Vertices for adjacency primitives are not always reused, so restore
738 * it for ES_VERTS_PER_SUBGRP.
739 */
740 min_es_verts = gs->gs_input_verts_per_prim;
741
742 /* For normal primitives, the VGT only checks if they are past the ES
743 * verts per subgroup after allocating a full GS primitive and if they
744 * are, kick off a new subgroup. But if those additional ES verts are
745 * unique (e.g. not reused) we need to make sure there is enough LDS
746 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
747 */
748 es_verts -= min_es_verts - 1;
749
750 out->es_verts_per_subgroup = es_verts;
751 out->gs_prims_per_subgroup = gs_prims;
752 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
753 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
754 gs->gs_max_out_vertices;
755 out->esgs_ring_size = 4 * esgs_lds_size;
756
757 assert(out->max_prims_per_subgroup <= max_out_prims);
758 }
759
760 static void si_emit_shader_gs(struct si_context *sctx)
761 {
762 struct si_shader *shader = sctx->queued.named.gs->shader;
763 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
764
765 if (!shader)
766 return;
767
768 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
769 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
770 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
771 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
772 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
773 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
774 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
775
776 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
777 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
778 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
779 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
780
781 /* R_028B38_VGT_GS_MAX_VERT_OUT */
782 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
783 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
784 shader->ctx_reg.gs.vgt_gs_max_vert_out);
785
786 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
787 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
788 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
789 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
790 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
791 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
792 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
793 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
794
795 /* R_028B90_VGT_GS_INSTANCE_CNT */
796 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
797 SI_TRACKED_VGT_GS_INSTANCE_CNT,
798 shader->ctx_reg.gs.vgt_gs_instance_cnt);
799
800 if (sctx->chip_class >= GFX9) {
801 /* R_028A44_VGT_GS_ONCHIP_CNTL */
802 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
803 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
804 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
805 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
806 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
807 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
808 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
809 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
810 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
811 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
812 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
813
814 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
815 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
816 SI_TRACKED_VGT_TF_PARAM,
817 shader->vgt_tf_param);
818 if (shader->vgt_vertex_reuse_block_cntl)
819 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
820 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
821 shader->vgt_vertex_reuse_block_cntl);
822 }
823
824 if (initial_cdw != sctx->gfx_cs->current.cdw)
825 sctx->context_roll = true;
826 }
827
828 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
829 {
830 struct si_shader_selector *sel = shader->selector;
831 const ubyte *num_components = sel->info.num_stream_output_components;
832 unsigned gs_num_invocations = sel->gs_num_invocations;
833 struct si_pm4_state *pm4;
834 uint64_t va;
835 unsigned max_stream = sel->max_gs_stream;
836 unsigned offset;
837
838 pm4 = si_get_shader_pm4_state(shader);
839 if (!pm4)
840 return;
841
842 pm4->atom.emit = si_emit_shader_gs;
843
844 offset = num_components[0] * sel->gs_max_out_vertices;
845 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
846
847 if (max_stream >= 1)
848 offset += num_components[1] * sel->gs_max_out_vertices;
849 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
850
851 if (max_stream >= 2)
852 offset += num_components[2] * sel->gs_max_out_vertices;
853 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
854
855 if (max_stream >= 3)
856 offset += num_components[3] * sel->gs_max_out_vertices;
857 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
858
859 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
860 assert(offset < (1 << 15));
861
862 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
863
864 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
865 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
866 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
867 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
868
869 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
870 S_028B90_ENABLE(gs_num_invocations > 0);
871
872 va = shader->bo->gpu_address;
873 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
874
875 if (sscreen->info.chip_class >= GFX9) {
876 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
877 unsigned es_type = shader->key.part.gs.es->type;
878 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
879
880 if (es_type == PIPE_SHADER_VERTEX) {
881 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
882 } else if (es_type == PIPE_SHADER_TESS_EVAL)
883 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
884 else
885 unreachable("invalid shader selector type");
886
887 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
888 * VGPR[0:4] are always loaded.
889 */
890 if (sel->info.uses_invocationid)
891 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
892 else if (sel->info.uses_primid)
893 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
894 else if (input_prim >= PIPE_PRIM_TRIANGLES)
895 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
896 else
897 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
898
899 unsigned num_user_sgprs;
900 if (es_type == PIPE_SHADER_VERTEX)
901 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
902 else
903 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
904
905 if (sscreen->info.chip_class >= GFX10) {
906 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
907 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
908 } else {
909 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
910 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
911 }
912
913 uint32_t rsrc1 =
914 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
915 S_00B228_DX10_CLAMP(1) |
916 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
917 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
918 S_00B228_FLOAT_MODE(shader->config.float_mode) |
919 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
920 uint32_t rsrc2 =
921 S_00B22C_USER_SGPR(num_user_sgprs) |
922 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
923 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
924 S_00B22C_LDS_SIZE(shader->config.lds_size) |
925 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
926
927 if (sscreen->info.chip_class >= GFX10) {
928 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
929 } else {
930 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
931 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
932 }
933
934 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
935 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
936
937 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
938 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
939 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
940 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
941 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
942 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
943 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
944 shader->key.part.gs.es->esgs_itemsize / 4;
945
946 if (es_type == PIPE_SHADER_TESS_EVAL)
947 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
948
949 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
950 NULL, pm4);
951 } else {
952 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
953 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
954
955 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
956 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
957 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
958 S_00B228_DX10_CLAMP(1) |
959 S_00B228_FLOAT_MODE(shader->config.float_mode));
960 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
961 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
962 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
963 }
964 }
965
966 /* Common tail code for NGG primitive shaders. */
967 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
968 struct si_shader *shader,
969 unsigned initial_cdw)
970 {
971 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
972 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
973 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
974 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
975 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
976 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
977 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
978 SI_TRACKED_VGT_PRIMITIVEID_EN,
979 shader->ctx_reg.ngg.vgt_primitiveid_en);
980 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
981 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
982 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
983 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
984 SI_TRACKED_VGT_GS_INSTANCE_CNT,
985 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
986 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
987 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
988 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
989 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
990 SI_TRACKED_SPI_VS_OUT_CONFIG,
991 shader->ctx_reg.ngg.spi_vs_out_config);
992 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
993 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
994 shader->ctx_reg.ngg.spi_shader_idx_format,
995 shader->ctx_reg.ngg.spi_shader_pos_format);
996 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
997 SI_TRACKED_PA_CL_VTE_CNTL,
998 shader->ctx_reg.ngg.pa_cl_vte_cntl);
999 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1000 SI_TRACKED_PA_CL_NGG_CNTL,
1001 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1002
1003 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1004 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1005 shader->pa_cl_vs_out_cntl,
1006 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1007
1008 if (initial_cdw != sctx->gfx_cs->current.cdw)
1009 sctx->context_roll = true;
1010 }
1011
1012 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1013 {
1014 struct si_shader *shader = sctx->queued.named.gs->shader;
1015 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1016
1017 if (!shader)
1018 return;
1019
1020 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1021 }
1022
1023 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1024 {
1025 struct si_shader *shader = sctx->queued.named.gs->shader;
1026 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1027
1028 if (!shader)
1029 return;
1030
1031 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1032 SI_TRACKED_VGT_TF_PARAM,
1033 shader->vgt_tf_param);
1034
1035 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1036 }
1037
1038 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1039 {
1040 struct si_shader *shader = sctx->queued.named.gs->shader;
1041 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1042
1043 if (!shader)
1044 return;
1045
1046 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1047 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1048 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1049
1050 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1051 }
1052
1053 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1054 {
1055 struct si_shader *shader = sctx->queued.named.gs->shader;
1056 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1057
1058 if (!shader)
1059 return;
1060
1061 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1062 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1063 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1064 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1065 SI_TRACKED_VGT_TF_PARAM,
1066 shader->vgt_tf_param);
1067
1068 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1069 }
1070
1071 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1072 {
1073 if (gs->type == PIPE_SHADER_GEOMETRY)
1074 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1075
1076 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1077 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1078 return PIPE_PRIM_POINTS;
1079 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1080 return PIPE_PRIM_LINES;
1081 return PIPE_PRIM_TRIANGLES;
1082 }
1083
1084 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1085 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1086 }
1087
1088 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1089 {
1090 bool misc_vec_ena =
1091 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1092 sel->info.writes_layer || sel->info.writes_viewport_index;
1093 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1094 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1095 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1096 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1097 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1098 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1099 }
1100
1101 /**
1102 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1103 * in NGG mode.
1104 */
1105 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1106 {
1107 const struct si_shader_selector *gs_sel = shader->selector;
1108 const struct si_shader_info *gs_info = &gs_sel->info;
1109 enum pipe_shader_type gs_type = shader->selector->type;
1110 const struct si_shader_selector *es_sel =
1111 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1112 const struct si_shader_info *es_info = &es_sel->info;
1113 enum pipe_shader_type es_type = es_sel->type;
1114 unsigned num_user_sgprs;
1115 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1116 uint64_t va;
1117 unsigned window_space =
1118 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1119 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1120 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1121 unsigned input_prim = si_get_input_prim(gs_sel);
1122 bool break_wave_at_eoi = false;
1123 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1124 if (!pm4)
1125 return;
1126
1127 if (es_type == PIPE_SHADER_TESS_EVAL) {
1128 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1129 : gfx10_emit_shader_ngg_tess_nogs;
1130 } else {
1131 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1132 : gfx10_emit_shader_ngg_notess_nogs;
1133 }
1134
1135 va = shader->bo->gpu_address;
1136 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1137
1138 if (es_type == PIPE_SHADER_VERTEX) {
1139 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1140
1141 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1142 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1143 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1144 } else {
1145 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1146 }
1147 } else {
1148 assert(es_type == PIPE_SHADER_TESS_EVAL);
1149 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1150 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1151
1152 if (es_enable_prim_id || gs_info->uses_primid)
1153 break_wave_at_eoi = true;
1154 }
1155
1156 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1157 * VGPR[0:4] are always loaded.
1158 *
1159 * Vertex shaders always need to load VGPR3, because they need to
1160 * pass edge flags for decomposed primitives (such as quads) to the PA
1161 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1162 */
1163 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1164 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1165 else if (gs_info->uses_primid)
1166 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1167 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1168 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1169 else
1170 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1171
1172 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1173 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1174 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1175 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1176 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1177 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1178 S_00B228_DX10_CLAMP(1) |
1179 S_00B228_MEM_ORDERED(1) |
1180 S_00B228_WGP_MODE(1) |
1181 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1182 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1183 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1184 S_00B22C_USER_SGPR(num_user_sgprs) |
1185 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1186 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1187 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1188 S_00B22C_LDS_SIZE(shader->config.lds_size));
1189
1190 nparams = MAX2(shader->info.nr_param_exports, 1);
1191 shader->ctx_reg.ngg.spi_vs_out_config =
1192 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1193 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1194
1195 shader->ctx_reg.ngg.spi_shader_idx_format =
1196 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1197 shader->ctx_reg.ngg.spi_shader_pos_format =
1198 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1199 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1200 V_02870C_SPI_SHADER_4COMP :
1201 V_02870C_SPI_SHADER_NONE) |
1202 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1203 V_02870C_SPI_SHADER_4COMP :
1204 V_02870C_SPI_SHADER_NONE) |
1205 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1206 V_02870C_SPI_SHADER_4COMP :
1207 V_02870C_SPI_SHADER_NONE);
1208
1209 shader->ctx_reg.ngg.vgt_primitiveid_en =
1210 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1211 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1212 gs_sel->info.writes_primid);
1213
1214 if (gs_type == PIPE_SHADER_GEOMETRY) {
1215 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1216 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1217 } else {
1218 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1219 }
1220
1221 if (es_type == PIPE_SHADER_TESS_EVAL)
1222 si_set_tesseval_regs(sscreen, es_sel, pm4);
1223
1224 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1225 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1226 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1227 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1228 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1229 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1230 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1231 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1232 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1233 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1234 S_028B90_CNT(gs_num_invocations) |
1235 S_028B90_ENABLE(gs_num_invocations > 1) |
1236 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1237 shader->ngg.max_vert_out_per_gs_instance);
1238
1239 /* Always output hw-generated edge flags and pass them via the prim
1240 * export to prevent drawing lines on internal edges of decomposed
1241 * primitives (such as quads) with polygon mode = lines. Only VS needs
1242 * this.
1243 */
1244 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1245 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1246 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1247
1248 shader->ge_cntl =
1249 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1250 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1251 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1252
1253 /* Bug workaround for a possible hang with non-tessellation cases.
1254 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1255 *
1256 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1257 */
1258 if ((sscreen->info.family == CHIP_NAVI10 ||
1259 sscreen->info.family == CHIP_NAVI12 ||
1260 sscreen->info.family == CHIP_NAVI14) &&
1261 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1262 shader->ngg.hw_max_esverts != 256) {
1263 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1264
1265 if (shader->ngg.hw_max_esverts > 5) {
1266 shader->ge_cntl |=
1267 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1268 }
1269 }
1270
1271 if (window_space) {
1272 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1273 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1274 } else {
1275 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1276 S_028818_VTX_W0_FMT(1) |
1277 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1278 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1279 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1280 }
1281 }
1282
1283 static void si_emit_shader_vs(struct si_context *sctx)
1284 {
1285 struct si_shader *shader = sctx->queued.named.vs->shader;
1286 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1287
1288 if (!shader)
1289 return;
1290
1291 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1292 SI_TRACKED_VGT_GS_MODE,
1293 shader->ctx_reg.vs.vgt_gs_mode);
1294 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1295 SI_TRACKED_VGT_PRIMITIVEID_EN,
1296 shader->ctx_reg.vs.vgt_primitiveid_en);
1297
1298 if (sctx->chip_class <= GFX8) {
1299 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1300 SI_TRACKED_VGT_REUSE_OFF,
1301 shader->ctx_reg.vs.vgt_reuse_off);
1302 }
1303
1304 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1305 SI_TRACKED_SPI_VS_OUT_CONFIG,
1306 shader->ctx_reg.vs.spi_vs_out_config);
1307
1308 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1309 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1310 shader->ctx_reg.vs.spi_shader_pos_format);
1311
1312 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1313 SI_TRACKED_PA_CL_VTE_CNTL,
1314 shader->ctx_reg.vs.pa_cl_vte_cntl);
1315
1316 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1317 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1318 SI_TRACKED_VGT_TF_PARAM,
1319 shader->vgt_tf_param);
1320
1321 if (shader->vgt_vertex_reuse_block_cntl)
1322 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1323 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1324 shader->vgt_vertex_reuse_block_cntl);
1325
1326 /* Required programming for tessellation. (legacy pipeline only) */
1327 if (sctx->chip_class == GFX10 &&
1328 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1329 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1330 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1331 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1332 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1333 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1334 }
1335
1336 if (sctx->chip_class >= GFX10) {
1337 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1338 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1339 shader->pa_cl_vs_out_cntl,
1340 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1341 }
1342
1343 if (initial_cdw != sctx->gfx_cs->current.cdw)
1344 sctx->context_roll = true;
1345 }
1346
1347 /**
1348 * Compute the state for \p shader, which will run as a vertex shader on the
1349 * hardware.
1350 *
1351 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1352 * is the copy shader.
1353 */
1354 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1355 struct si_shader_selector *gs)
1356 {
1357 const struct si_shader_info *info = &shader->selector->info;
1358 struct si_pm4_state *pm4;
1359 unsigned num_user_sgprs, vgpr_comp_cnt;
1360 uint64_t va;
1361 unsigned nparams, oc_lds_en;
1362 unsigned window_space =
1363 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1364 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1365
1366 pm4 = si_get_shader_pm4_state(shader);
1367 if (!pm4)
1368 return;
1369
1370 pm4->atom.emit = si_emit_shader_vs;
1371
1372 /* We always write VGT_GS_MODE in the VS state, because every switch
1373 * between different shader pipelines involving a different GS or no
1374 * GS at all involves a switch of the VS (different GS use different
1375 * copy shaders). On the other hand, when the API switches from a GS to
1376 * no GS and then back to the same GS used originally, the GS state is
1377 * not sent again.
1378 */
1379 if (!gs) {
1380 unsigned mode = V_028A40_GS_OFF;
1381
1382 /* PrimID needs GS scenario A. */
1383 if (enable_prim_id)
1384 mode = V_028A40_GS_SCENARIO_A;
1385
1386 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1387 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1388 } else {
1389 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1390 sscreen->info.chip_class);
1391 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1392 }
1393
1394 if (sscreen->info.chip_class <= GFX8) {
1395 /* Reuse needs to be set off if we write oViewport. */
1396 shader->ctx_reg.vs.vgt_reuse_off =
1397 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1398 }
1399
1400 va = shader->bo->gpu_address;
1401 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1402
1403 if (gs) {
1404 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1405 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1406 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1407 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1408
1409 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1410 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1411 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1412 } else {
1413 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1414 }
1415 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1416 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1417 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1418 } else
1419 unreachable("invalid shader selector type");
1420
1421 /* VS is required to export at least one param. */
1422 nparams = MAX2(shader->info.nr_param_exports, 1);
1423 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1424
1425 if (sscreen->info.chip_class >= GFX10) {
1426 shader->ctx_reg.vs.spi_vs_out_config |=
1427 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1428 }
1429
1430 shader->ctx_reg.vs.spi_shader_pos_format =
1431 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1432 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1433 V_02870C_SPI_SHADER_4COMP :
1434 V_02870C_SPI_SHADER_NONE) |
1435 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1436 V_02870C_SPI_SHADER_4COMP :
1437 V_02870C_SPI_SHADER_NONE) |
1438 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1439 V_02870C_SPI_SHADER_4COMP :
1440 V_02870C_SPI_SHADER_NONE);
1441 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1442
1443 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1444
1445 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1446 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1447
1448 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1449 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1450 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1451 S_00B128_DX10_CLAMP(1) |
1452 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1453 S_00B128_FLOAT_MODE(shader->config.float_mode);
1454 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1455 S_00B12C_OC_LDS_EN(oc_lds_en) |
1456 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1457
1458 if (sscreen->info.chip_class >= GFX10)
1459 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1460 else if (sscreen->info.chip_class == GFX9)
1461 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1462
1463 if (sscreen->info.chip_class <= GFX9)
1464 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1465
1466 if (!sscreen->use_ngg_streamout) {
1467 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1468 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1469 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1470 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1471 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1472 }
1473
1474 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1475 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1476
1477 if (window_space)
1478 shader->ctx_reg.vs.pa_cl_vte_cntl =
1479 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1480 else
1481 shader->ctx_reg.vs.pa_cl_vte_cntl =
1482 S_028818_VTX_W0_FMT(1) |
1483 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1484 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1485 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1486
1487 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1488 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1489
1490 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1491 }
1492
1493 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1494 {
1495 struct si_shader_info *info = &ps->selector->info;
1496 unsigned num_colors = !!(info->colors_read & 0x0f) +
1497 !!(info->colors_read & 0xf0);
1498 unsigned num_interp = ps->selector->info.num_inputs +
1499 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1500
1501 assert(num_interp <= 32);
1502 return MIN2(num_interp, 32);
1503 }
1504
1505 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1506 {
1507 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1508 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1509
1510 /* If the i-th target format is set, all previous target formats must
1511 * be non-zero to avoid hangs.
1512 */
1513 for (i = 0; i < num_targets; i++)
1514 if (!(value & (0xf << (i * 4))))
1515 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1516
1517 return value;
1518 }
1519
1520 static void si_emit_shader_ps(struct si_context *sctx)
1521 {
1522 struct si_shader *shader = sctx->queued.named.ps->shader;
1523 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1524
1525 if (!shader)
1526 return;
1527
1528 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1529 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1530 SI_TRACKED_SPI_PS_INPUT_ENA,
1531 shader->ctx_reg.ps.spi_ps_input_ena,
1532 shader->ctx_reg.ps.spi_ps_input_addr);
1533
1534 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1535 SI_TRACKED_SPI_BARYC_CNTL,
1536 shader->ctx_reg.ps.spi_baryc_cntl);
1537 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1538 SI_TRACKED_SPI_PS_IN_CONTROL,
1539 shader->ctx_reg.ps.spi_ps_in_control);
1540
1541 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1542 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1543 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1544 shader->ctx_reg.ps.spi_shader_z_format,
1545 shader->ctx_reg.ps.spi_shader_col_format);
1546
1547 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1548 SI_TRACKED_CB_SHADER_MASK,
1549 shader->ctx_reg.ps.cb_shader_mask);
1550
1551 if (initial_cdw != sctx->gfx_cs->current.cdw)
1552 sctx->context_roll = true;
1553 }
1554
1555 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1556 {
1557 struct si_shader_info *info = &shader->selector->info;
1558 struct si_pm4_state *pm4;
1559 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1560 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1561 uint64_t va;
1562 unsigned input_ena = shader->config.spi_ps_input_ena;
1563
1564 /* we need to enable at least one of them, otherwise we hang the GPU */
1565 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1566 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1567 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1568 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1569 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1570 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1571 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1572 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1573 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1574 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1575 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1576 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1577 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1578 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1579
1580 /* Validate interpolation optimization flags (read as implications). */
1581 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1582 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1583 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1584 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1585 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1586 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1587 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1588 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1589 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1590 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1591 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1592 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1593 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1594 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1595 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1596 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1597 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1598 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1599
1600 /* Validate cases when the optimizations are off (read as implications). */
1601 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1602 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1603 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1604 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1605 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1606 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1607
1608 pm4 = si_get_shader_pm4_state(shader);
1609 if (!pm4)
1610 return;
1611
1612 pm4->atom.emit = si_emit_shader_ps;
1613
1614 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1615 * Possible vaules:
1616 * 0 -> Position = pixel center
1617 * 1 -> Position = pixel centroid
1618 * 2 -> Position = at sample position
1619 *
1620 * From GLSL 4.5 specification, section 7.1:
1621 * "The variable gl_FragCoord is available as an input variable from
1622 * within fragment shaders and it holds the window relative coordinates
1623 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1624 * value can be for any location within the pixel, or one of the
1625 * fragment samples. The use of centroid does not further restrict
1626 * this value to be inside the current primitive."
1627 *
1628 * Meaning that centroid has no effect and we can return anything within
1629 * the pixel. Thus, return the value at sample position, because that's
1630 * the most accurate one shaders can get.
1631 */
1632 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1633
1634 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1635 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1636 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1637
1638 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1639 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1640
1641 /* Ensure that some export memory is always allocated, for two reasons:
1642 *
1643 * 1) Correctness: The hardware ignores the EXEC mask if no export
1644 * memory is allocated, so KILL and alpha test do not work correctly
1645 * without this.
1646 * 2) Performance: Every shader needs at least a NULL export, even when
1647 * it writes no color/depth output. The NULL export instruction
1648 * stalls without this setting.
1649 *
1650 * Don't add this to CB_SHADER_MASK.
1651 *
1652 * GFX10 supports pixel shaders without exports by setting both
1653 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1654 * instructions if any are present.
1655 */
1656 if ((sscreen->info.chip_class <= GFX9 ||
1657 info->uses_kill ||
1658 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1659 !spi_shader_col_format &&
1660 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1661 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1662
1663 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1664 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1665
1666 /* Set interpolation controls. */
1667 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1668 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1669
1670 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1671 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1672 shader->ctx_reg.ps.spi_shader_z_format =
1673 ac_get_spi_shader_z_format(info->writes_z,
1674 info->writes_stencil,
1675 info->writes_samplemask);
1676 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1677 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1678
1679 va = shader->bo->gpu_address;
1680 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1681 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1682 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1683
1684 uint32_t rsrc1 =
1685 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1686 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1687 S_00B028_DX10_CLAMP(1) |
1688 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1689 S_00B028_FLOAT_MODE(shader->config.float_mode);
1690
1691 if (sscreen->info.chip_class < GFX10) {
1692 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1693 }
1694
1695 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1696 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1697 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1698 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1699 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1700 }
1701
1702 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1703 struct si_shader *shader)
1704 {
1705 switch (shader->selector->type) {
1706 case PIPE_SHADER_VERTEX:
1707 if (shader->key.as_ls)
1708 si_shader_ls(sscreen, shader);
1709 else if (shader->key.as_es)
1710 si_shader_es(sscreen, shader);
1711 else if (shader->key.as_ngg)
1712 gfx10_shader_ngg(sscreen, shader);
1713 else
1714 si_shader_vs(sscreen, shader, NULL);
1715 break;
1716 case PIPE_SHADER_TESS_CTRL:
1717 si_shader_hs(sscreen, shader);
1718 break;
1719 case PIPE_SHADER_TESS_EVAL:
1720 if (shader->key.as_es)
1721 si_shader_es(sscreen, shader);
1722 else if (shader->key.as_ngg)
1723 gfx10_shader_ngg(sscreen, shader);
1724 else
1725 si_shader_vs(sscreen, shader, NULL);
1726 break;
1727 case PIPE_SHADER_GEOMETRY:
1728 if (shader->key.as_ngg)
1729 gfx10_shader_ngg(sscreen, shader);
1730 else
1731 si_shader_gs(sscreen, shader);
1732 break;
1733 case PIPE_SHADER_FRAGMENT:
1734 si_shader_ps(sscreen, shader);
1735 break;
1736 default:
1737 assert(0);
1738 }
1739 }
1740
1741 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1742 {
1743 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1744 return sctx->queued.named.dsa->alpha_func;
1745 }
1746
1747 void si_shader_selector_key_vs(struct si_context *sctx,
1748 struct si_shader_selector *vs,
1749 struct si_shader_key *key,
1750 struct si_vs_prolog_bits *prolog_key)
1751 {
1752 if (!sctx->vertex_elements ||
1753 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1754 return;
1755
1756 struct si_vertex_elements *elts = sctx->vertex_elements;
1757
1758 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1759 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1760 prolog_key->unpack_instance_id_from_vertex_id =
1761 sctx->prim_discard_cs_instancing;
1762
1763 /* Prefer a monolithic shader to allow scheduling divisions around
1764 * VBO loads. */
1765 if (prolog_key->instance_divisor_is_fetched)
1766 key->opt.prefer_mono = 1;
1767
1768 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1769 unsigned count_mask = (1 << count) - 1;
1770 unsigned fix = elts->fix_fetch_always & count_mask;
1771 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1772
1773 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1774 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1775 while (mask) {
1776 unsigned i = u_bit_scan(&mask);
1777 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1778 unsigned vbidx = elts->vertex_buffer_index[i];
1779 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1780 unsigned align_mask = (1 << log_hw_load_size) - 1;
1781 if (vb->buffer_offset & align_mask ||
1782 vb->stride & align_mask) {
1783 fix |= 1 << i;
1784 opencode |= 1 << i;
1785 }
1786 }
1787 }
1788
1789 while (fix) {
1790 unsigned i = u_bit_scan(&fix);
1791 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1792 }
1793 key->mono.vs_fetch_opencode = opencode;
1794 }
1795
1796 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1797 struct si_shader_selector *vs,
1798 struct si_shader_key *key)
1799 {
1800 struct si_shader_selector *ps = sctx->ps_shader.cso;
1801
1802 key->opt.clip_disable =
1803 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1804 (vs->info.clipdist_writemask ||
1805 vs->info.writes_clipvertex) &&
1806 !vs->info.culldist_writemask;
1807
1808 /* Find out if PS is disabled. */
1809 bool ps_disabled = true;
1810 if (ps) {
1811 bool ps_modifies_zs = ps->info.uses_kill ||
1812 ps->info.writes_z ||
1813 ps->info.writes_stencil ||
1814 ps->info.writes_samplemask ||
1815 sctx->queued.named.blend->alpha_to_coverage ||
1816 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1817 unsigned ps_colormask = si_get_total_colormask(sctx);
1818
1819 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1820 (!ps_colormask &&
1821 !ps_modifies_zs &&
1822 !ps->info.writes_memory);
1823 }
1824
1825 /* Find out which VS outputs aren't used by the PS. */
1826 uint64_t outputs_written = vs->outputs_written_before_ps;
1827 uint64_t inputs_read = 0;
1828
1829 /* Ignore outputs that are not passed from VS to PS. */
1830 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1831 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1832 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1833
1834 if (!ps_disabled) {
1835 inputs_read = ps->inputs_read;
1836 }
1837
1838 uint64_t linked = outputs_written & inputs_read;
1839
1840 key->opt.kill_outputs = ~linked & outputs_written;
1841 }
1842
1843 /* Compute the key for the hw shader variant */
1844 static inline void si_shader_selector_key(struct pipe_context *ctx,
1845 struct si_shader_selector *sel,
1846 union si_vgt_stages_key stages_key,
1847 struct si_shader_key *key)
1848 {
1849 struct si_context *sctx = (struct si_context *)ctx;
1850
1851 memset(key, 0, sizeof(*key));
1852
1853 switch (sel->type) {
1854 case PIPE_SHADER_VERTEX:
1855 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1856
1857 if (sctx->tes_shader.cso)
1858 key->as_ls = 1;
1859 else if (sctx->gs_shader.cso) {
1860 key->as_es = 1;
1861 key->as_ngg = stages_key.u.ngg;
1862 } else {
1863 key->as_ngg = stages_key.u.ngg;
1864 si_shader_selector_key_hw_vs(sctx, sel, key);
1865
1866 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1867 key->mono.u.vs_export_prim_id = 1;
1868 }
1869 break;
1870 case PIPE_SHADER_TESS_CTRL:
1871 if (sctx->chip_class >= GFX9) {
1872 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1873 key, &key->part.tcs.ls_prolog);
1874 key->part.tcs.ls = sctx->vs_shader.cso;
1875
1876 /* When the LS VGPR fix is needed, monolithic shaders
1877 * can:
1878 * - avoid initializing EXEC in both the LS prolog
1879 * and the LS main part when !vs_needs_prolog
1880 * - remove the fixup for unused input VGPRs
1881 */
1882 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1883
1884 /* The LS output / HS input layout can be communicated
1885 * directly instead of via user SGPRs for merged LS-HS.
1886 * The LS VGPR fix prefers this too.
1887 */
1888 key->opt.prefer_mono = 1;
1889 }
1890
1891 key->part.tcs.epilog.prim_mode =
1892 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1893 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1894 sel->info.tessfactors_are_def_in_all_invocs;
1895 key->part.tcs.epilog.tes_reads_tess_factors =
1896 sctx->tes_shader.cso->info.reads_tess_factors;
1897
1898 if (sel == sctx->fixed_func_tcs_shader.cso)
1899 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1900 break;
1901 case PIPE_SHADER_TESS_EVAL:
1902 key->as_ngg = stages_key.u.ngg;
1903
1904 if (sctx->gs_shader.cso)
1905 key->as_es = 1;
1906 else {
1907 si_shader_selector_key_hw_vs(sctx, sel, key);
1908
1909 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1910 key->mono.u.vs_export_prim_id = 1;
1911 }
1912 break;
1913 case PIPE_SHADER_GEOMETRY:
1914 if (sctx->chip_class >= GFX9) {
1915 if (sctx->tes_shader.cso) {
1916 key->part.gs.es = sctx->tes_shader.cso;
1917 } else {
1918 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1919 key, &key->part.gs.vs_prolog);
1920 key->part.gs.es = sctx->vs_shader.cso;
1921 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1922 }
1923
1924 key->as_ngg = stages_key.u.ngg;
1925
1926 /* Merged ES-GS can have unbalanced wave usage.
1927 *
1928 * ES threads are per-vertex, while GS threads are
1929 * per-primitive. So without any amplification, there
1930 * are fewer GS threads than ES threads, which can result
1931 * in empty (no-op) GS waves. With too much amplification,
1932 * there are more GS threads than ES threads, which
1933 * can result in empty (no-op) ES waves.
1934 *
1935 * Non-monolithic shaders are implemented by setting EXEC
1936 * at the beginning of shader parts, and don't jump to
1937 * the end if EXEC is 0.
1938 *
1939 * Monolithic shaders use conditional blocks, so they can
1940 * jump and skip empty waves of ES or GS. So set this to
1941 * always use optimized variants, which are monolithic.
1942 */
1943 key->opt.prefer_mono = 1;
1944 }
1945 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1946 break;
1947 case PIPE_SHADER_FRAGMENT: {
1948 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1949 struct si_state_blend *blend = sctx->queued.named.blend;
1950
1951 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1952 sel->info.colors_written == 0x1)
1953 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1954
1955 /* Select the shader color format based on whether
1956 * blending or alpha are needed.
1957 */
1958 key->part.ps.epilog.spi_shader_col_format =
1959 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1960 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1961 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1962 sctx->framebuffer.spi_shader_col_format_blend) |
1963 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1964 sctx->framebuffer.spi_shader_col_format_alpha) |
1965 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1966 sctx->framebuffer.spi_shader_col_format);
1967 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1968
1969 /* The output for dual source blending should have
1970 * the same format as the first output.
1971 */
1972 if (blend->dual_src_blend) {
1973 key->part.ps.epilog.spi_shader_col_format |=
1974 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1975 }
1976
1977 /* If alpha-to-coverage is enabled, we have to export alpha
1978 * even if there is no color buffer.
1979 */
1980 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1981 blend->alpha_to_coverage)
1982 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1983
1984 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1985 * to the range supported by the type if a channel has less
1986 * than 16 bits and the export format is 16_ABGR.
1987 */
1988 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1989 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1990 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1991 }
1992
1993 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1994 if (!key->part.ps.epilog.last_cbuf) {
1995 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1996 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1997 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1998 }
1999
2000 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
2001 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
2002
2003 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
2004 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
2005
2006 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
2007 rs->multisample_enable;
2008
2009 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
2010 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
2011 (is_line && rs->line_smooth)) &&
2012 sctx->framebuffer.nr_samples <= 1;
2013 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2014
2015 if (sctx->ps_iter_samples > 1 &&
2016 sel->info.reads_samplemask) {
2017 key->part.ps.prolog.samplemask_log_ps_iter =
2018 util_logbase2(sctx->ps_iter_samples);
2019 }
2020
2021 if (rs->force_persample_interp &&
2022 rs->multisample_enable &&
2023 sctx->framebuffer.nr_samples > 1 &&
2024 sctx->ps_iter_samples > 1) {
2025 key->part.ps.prolog.force_persp_sample_interp =
2026 sel->info.uses_persp_center ||
2027 sel->info.uses_persp_centroid;
2028
2029 key->part.ps.prolog.force_linear_sample_interp =
2030 sel->info.uses_linear_center ||
2031 sel->info.uses_linear_centroid;
2032 } else if (rs->multisample_enable &&
2033 sctx->framebuffer.nr_samples > 1) {
2034 key->part.ps.prolog.bc_optimize_for_persp =
2035 sel->info.uses_persp_center &&
2036 sel->info.uses_persp_centroid;
2037 key->part.ps.prolog.bc_optimize_for_linear =
2038 sel->info.uses_linear_center &&
2039 sel->info.uses_linear_centroid;
2040 } else {
2041 /* Make sure SPI doesn't compute more than 1 pair
2042 * of (i,j), which is the optimization here. */
2043 key->part.ps.prolog.force_persp_center_interp =
2044 sel->info.uses_persp_center +
2045 sel->info.uses_persp_centroid +
2046 sel->info.uses_persp_sample > 1;
2047
2048 key->part.ps.prolog.force_linear_center_interp =
2049 sel->info.uses_linear_center +
2050 sel->info.uses_linear_centroid +
2051 sel->info.uses_linear_sample > 1;
2052
2053 if (sel->info.uses_persp_opcode_interp_sample ||
2054 sel->info.uses_linear_opcode_interp_sample)
2055 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2056 }
2057
2058 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2059
2060 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2061 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2062 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2063 struct pipe_resource *tex = cb0->texture;
2064
2065 /* 1D textures are allocated and used as 2D on GFX9. */
2066 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2067 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2068 (tex->target == PIPE_TEXTURE_1D ||
2069 tex->target == PIPE_TEXTURE_1D_ARRAY);
2070 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2071 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2072 tex->target == PIPE_TEXTURE_CUBE ||
2073 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2074 tex->target == PIPE_TEXTURE_3D;
2075 }
2076 break;
2077 }
2078 default:
2079 assert(0);
2080 }
2081
2082 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2083 memset(&key->opt, 0, sizeof(key->opt));
2084 }
2085
2086 static void si_build_shader_variant(struct si_shader *shader,
2087 int thread_index,
2088 bool low_priority)
2089 {
2090 struct si_shader_selector *sel = shader->selector;
2091 struct si_screen *sscreen = sel->screen;
2092 struct ac_llvm_compiler *compiler;
2093 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2094
2095 if (thread_index >= 0) {
2096 if (low_priority) {
2097 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2098 compiler = &sscreen->compiler_lowp[thread_index];
2099 } else {
2100 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2101 compiler = &sscreen->compiler[thread_index];
2102 }
2103 if (!debug->async)
2104 debug = NULL;
2105 } else {
2106 assert(!low_priority);
2107 compiler = shader->compiler_ctx_state.compiler;
2108 }
2109
2110 if (!compiler->passes)
2111 si_init_compiler(sscreen, compiler);
2112
2113 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2114 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2115 sel->type);
2116 shader->compilation_failed = true;
2117 return;
2118 }
2119
2120 if (shader->compiler_ctx_state.is_debug_context) {
2121 FILE *f = open_memstream(&shader->shader_log,
2122 &shader->shader_log_size);
2123 if (f) {
2124 si_shader_dump(sscreen, shader, NULL, f, false);
2125 fclose(f);
2126 }
2127 }
2128
2129 si_shader_init_pm4_state(sscreen, shader);
2130 }
2131
2132 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2133 {
2134 struct si_shader *shader = (struct si_shader *)job;
2135
2136 assert(thread_index >= 0);
2137
2138 si_build_shader_variant(shader, thread_index, true);
2139 }
2140
2141 static const struct si_shader_key zeroed;
2142
2143 static bool si_check_missing_main_part(struct si_screen *sscreen,
2144 struct si_shader_selector *sel,
2145 struct si_compiler_ctx_state *compiler_state,
2146 struct si_shader_key *key)
2147 {
2148 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2149
2150 if (!*mainp) {
2151 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2152
2153 if (!main_part)
2154 return false;
2155
2156 /* We can leave the fence as permanently signaled because the
2157 * main part becomes visible globally only after it has been
2158 * compiled. */
2159 util_queue_fence_init(&main_part->ready);
2160
2161 main_part->selector = sel;
2162 main_part->key.as_es = key->as_es;
2163 main_part->key.as_ls = key->as_ls;
2164 main_part->key.as_ngg = key->as_ngg;
2165 main_part->is_monolithic = false;
2166
2167 if (si_compile_shader(sscreen, compiler_state->compiler,
2168 main_part, &compiler_state->debug) != 0) {
2169 FREE(main_part);
2170 return false;
2171 }
2172 *mainp = main_part;
2173 }
2174 return true;
2175 }
2176
2177 /**
2178 * Select a shader variant according to the shader key.
2179 *
2180 * \param optimized_or_none If the key describes an optimized shader variant and
2181 * the compilation isn't finished, don't select any
2182 * shader and return an error.
2183 */
2184 int si_shader_select_with_key(struct si_screen *sscreen,
2185 struct si_shader_ctx_state *state,
2186 struct si_compiler_ctx_state *compiler_state,
2187 struct si_shader_key *key,
2188 int thread_index,
2189 bool optimized_or_none)
2190 {
2191 struct si_shader_selector *sel = state->cso;
2192 struct si_shader_selector *previous_stage_sel = NULL;
2193 struct si_shader *current = state->current;
2194 struct si_shader *iter, *shader = NULL;
2195
2196 again:
2197 /* Check if we don't need to change anything.
2198 * This path is also used for most shaders that don't need multiple
2199 * variants, it will cost just a computation of the key and this
2200 * test. */
2201 if (likely(current &&
2202 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2203 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2204 if (current->is_optimized) {
2205 if (optimized_or_none)
2206 return -1;
2207
2208 memset(&key->opt, 0, sizeof(key->opt));
2209 goto current_not_ready;
2210 }
2211
2212 util_queue_fence_wait(&current->ready);
2213 }
2214
2215 return current->compilation_failed ? -1 : 0;
2216 }
2217 current_not_ready:
2218
2219 /* This must be done before the mutex is locked, because async GS
2220 * compilation calls this function too, and therefore must enter
2221 * the mutex first.
2222 *
2223 * Only wait if we are in a draw call. Don't wait if we are
2224 * in a compiler thread.
2225 */
2226 if (thread_index < 0)
2227 util_queue_fence_wait(&sel->ready);
2228
2229 simple_mtx_lock(&sel->mutex);
2230
2231 /* Find the shader variant. */
2232 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2233 /* Don't check the "current" shader. We checked it above. */
2234 if (current != iter &&
2235 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2236 simple_mtx_unlock(&sel->mutex);
2237
2238 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2239 /* If it's an optimized shader and its compilation has
2240 * been started but isn't done, use the unoptimized
2241 * shader so as not to cause a stall due to compilation.
2242 */
2243 if (iter->is_optimized) {
2244 if (optimized_or_none)
2245 return -1;
2246 memset(&key->opt, 0, sizeof(key->opt));
2247 goto again;
2248 }
2249
2250 util_queue_fence_wait(&iter->ready);
2251 }
2252
2253 if (iter->compilation_failed) {
2254 return -1; /* skip the draw call */
2255 }
2256
2257 state->current = iter;
2258 return 0;
2259 }
2260 }
2261
2262 /* Build a new shader. */
2263 shader = CALLOC_STRUCT(si_shader);
2264 if (!shader) {
2265 simple_mtx_unlock(&sel->mutex);
2266 return -ENOMEM;
2267 }
2268
2269 util_queue_fence_init(&shader->ready);
2270
2271 shader->selector = sel;
2272 shader->key = *key;
2273 shader->compiler_ctx_state = *compiler_state;
2274
2275 /* If this is a merged shader, get the first shader's selector. */
2276 if (sscreen->info.chip_class >= GFX9) {
2277 if (sel->type == PIPE_SHADER_TESS_CTRL)
2278 previous_stage_sel = key->part.tcs.ls;
2279 else if (sel->type == PIPE_SHADER_GEOMETRY)
2280 previous_stage_sel = key->part.gs.es;
2281
2282 /* We need to wait for the previous shader. */
2283 if (previous_stage_sel && thread_index < 0)
2284 util_queue_fence_wait(&previous_stage_sel->ready);
2285 }
2286
2287 bool is_pure_monolithic =
2288 sscreen->use_monolithic_shaders ||
2289 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2290
2291 /* Compile the main shader part if it doesn't exist. This can happen
2292 * if the initial guess was wrong.
2293 *
2294 * The prim discard CS doesn't need the main shader part.
2295 */
2296 if (!is_pure_monolithic &&
2297 !key->opt.vs_as_prim_discard_cs) {
2298 bool ok = true;
2299
2300 /* Make sure the main shader part is present. This is needed
2301 * for shaders that can be compiled as VS, LS, or ES, and only
2302 * one of them is compiled at creation.
2303 *
2304 * It is also needed for GS, which can be compiled as non-NGG
2305 * and NGG.
2306 *
2307 * For merged shaders, check that the starting shader's main
2308 * part is present.
2309 */
2310 if (previous_stage_sel) {
2311 struct si_shader_key shader1_key = zeroed;
2312
2313 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2314 shader1_key.as_ls = 1;
2315 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2316 shader1_key.as_es = 1;
2317 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2318 } else {
2319 assert(0);
2320 }
2321
2322 simple_mtx_lock(&previous_stage_sel->mutex);
2323 ok = si_check_missing_main_part(sscreen,
2324 previous_stage_sel,
2325 compiler_state, &shader1_key);
2326 simple_mtx_unlock(&previous_stage_sel->mutex);
2327 }
2328
2329 if (ok) {
2330 ok = si_check_missing_main_part(sscreen, sel,
2331 compiler_state, key);
2332 }
2333
2334 if (!ok) {
2335 FREE(shader);
2336 simple_mtx_unlock(&sel->mutex);
2337 return -ENOMEM; /* skip the draw call */
2338 }
2339 }
2340
2341 /* Keep the reference to the 1st shader of merged shaders, so that
2342 * Gallium can't destroy it before we destroy the 2nd shader.
2343 *
2344 * Set sctx = NULL, because it's unused if we're not releasing
2345 * the shader, and we don't have any sctx here.
2346 */
2347 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2348 previous_stage_sel);
2349
2350 /* Monolithic-only shaders don't make a distinction between optimized
2351 * and unoptimized. */
2352 shader->is_monolithic =
2353 is_pure_monolithic ||
2354 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2355
2356 /* The prim discard CS is always optimized. */
2357 shader->is_optimized =
2358 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2359 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2360
2361 /* If it's an optimized shader, compile it asynchronously. */
2362 if (shader->is_optimized && thread_index < 0) {
2363 /* Compile it asynchronously. */
2364 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2365 shader, &shader->ready,
2366 si_build_shader_variant_low_priority, NULL,
2367 0);
2368
2369 /* Add only after the ready fence was reset, to guard against a
2370 * race with si_bind_XX_shader. */
2371 if (!sel->last_variant) {
2372 sel->first_variant = shader;
2373 sel->last_variant = shader;
2374 } else {
2375 sel->last_variant->next_variant = shader;
2376 sel->last_variant = shader;
2377 }
2378
2379 /* Use the default (unoptimized) shader for now. */
2380 memset(&key->opt, 0, sizeof(key->opt));
2381 simple_mtx_unlock(&sel->mutex);
2382
2383 if (sscreen->options.sync_compile)
2384 util_queue_fence_wait(&shader->ready);
2385
2386 if (optimized_or_none)
2387 return -1;
2388 goto again;
2389 }
2390
2391 /* Reset the fence before adding to the variant list. */
2392 util_queue_fence_reset(&shader->ready);
2393
2394 if (!sel->last_variant) {
2395 sel->first_variant = shader;
2396 sel->last_variant = shader;
2397 } else {
2398 sel->last_variant->next_variant = shader;
2399 sel->last_variant = shader;
2400 }
2401
2402 simple_mtx_unlock(&sel->mutex);
2403
2404 assert(!shader->is_optimized);
2405 si_build_shader_variant(shader, thread_index, false);
2406
2407 util_queue_fence_signal(&shader->ready);
2408
2409 if (!shader->compilation_failed)
2410 state->current = shader;
2411
2412 return shader->compilation_failed ? -1 : 0;
2413 }
2414
2415 static int si_shader_select(struct pipe_context *ctx,
2416 struct si_shader_ctx_state *state,
2417 union si_vgt_stages_key stages_key,
2418 struct si_compiler_ctx_state *compiler_state)
2419 {
2420 struct si_context *sctx = (struct si_context *)ctx;
2421 struct si_shader_key key;
2422
2423 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2424 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2425 &key, -1, false);
2426 }
2427
2428 static void si_parse_next_shader_property(const struct si_shader_info *info,
2429 bool streamout,
2430 struct si_shader_key *key)
2431 {
2432 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2433
2434 switch (info->processor) {
2435 case PIPE_SHADER_VERTEX:
2436 switch (next_shader) {
2437 case PIPE_SHADER_GEOMETRY:
2438 key->as_es = 1;
2439 break;
2440 case PIPE_SHADER_TESS_CTRL:
2441 case PIPE_SHADER_TESS_EVAL:
2442 key->as_ls = 1;
2443 break;
2444 default:
2445 /* If POSITION isn't written, it can only be a HW VS
2446 * if streamout is used. If streamout isn't used,
2447 * assume that it's a HW LS. (the next shader is TCS)
2448 * This heuristic is needed for separate shader objects.
2449 */
2450 if (!info->writes_position && !streamout)
2451 key->as_ls = 1;
2452 }
2453 break;
2454
2455 case PIPE_SHADER_TESS_EVAL:
2456 if (next_shader == PIPE_SHADER_GEOMETRY ||
2457 !info->writes_position)
2458 key->as_es = 1;
2459 break;
2460 }
2461 }
2462
2463 /**
2464 * Compile the main shader part or the monolithic shader as part of
2465 * si_shader_selector initialization. Since it can be done asynchronously,
2466 * there is no way to report compile failures to applications.
2467 */
2468 static void si_init_shader_selector_async(void *job, int thread_index)
2469 {
2470 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2471 struct si_screen *sscreen = sel->screen;
2472 struct ac_llvm_compiler *compiler;
2473 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2474
2475 assert(!debug->debug_message || debug->async);
2476 assert(thread_index >= 0);
2477 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2478 compiler = &sscreen->compiler[thread_index];
2479
2480 if (!compiler->passes)
2481 si_init_compiler(sscreen, compiler);
2482
2483 /* Serialize NIR to save memory. Monolithic shader variants
2484 * have to deserialize NIR before compilation.
2485 */
2486 if (sel->nir) {
2487 struct blob blob;
2488 size_t size;
2489
2490 blob_init(&blob);
2491 /* true = remove optional debugging data to increase
2492 * the likehood of getting more shader cache hits.
2493 * It also drops variable names, so we'll save more memory.
2494 */
2495 nir_serialize(&blob, sel->nir, true);
2496 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2497 sel->nir_size = size;
2498 }
2499
2500 /* Compile the main shader part for use with a prolog and/or epilog.
2501 * If this fails, the driver will try to compile a monolithic shader
2502 * on demand.
2503 */
2504 if (!sscreen->use_monolithic_shaders) {
2505 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2506 unsigned char ir_sha1_cache_key[20];
2507
2508 if (!shader) {
2509 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2510 return;
2511 }
2512
2513 /* We can leave the fence signaled because use of the default
2514 * main part is guarded by the selector's ready fence. */
2515 util_queue_fence_init(&shader->ready);
2516
2517 shader->selector = sel;
2518 shader->is_monolithic = false;
2519 si_parse_next_shader_property(&sel->info,
2520 sel->so.num_outputs != 0,
2521 &shader->key);
2522
2523 if (sscreen->use_ngg &&
2524 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2525 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2526 sel->type == PIPE_SHADER_TESS_EVAL ||
2527 sel->type == PIPE_SHADER_GEOMETRY))
2528 shader->key.as_ngg = 1;
2529
2530 if (sel->nir) {
2531 si_get_ir_cache_key(sel, shader->key.as_ngg,
2532 shader->key.as_es, ir_sha1_cache_key);
2533 }
2534
2535 /* Try to load the shader from the shader cache. */
2536 simple_mtx_lock(&sscreen->shader_cache_mutex);
2537
2538 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2539 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2540 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2541 } else {
2542 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2543
2544 /* Compile the shader if it hasn't been loaded from the cache. */
2545 if (si_compile_shader(sscreen, compiler, shader,
2546 debug) != 0) {
2547 FREE(shader);
2548 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2549 return;
2550 }
2551
2552 simple_mtx_lock(&sscreen->shader_cache_mutex);
2553 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
2554 shader, true);
2555 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2556 }
2557
2558 *si_get_main_shader_part(sel, &shader->key) = shader;
2559
2560 /* Unset "outputs_written" flags for outputs converted to
2561 * DEFAULT_VAL, so that later inter-shader optimizations don't
2562 * try to eliminate outputs that don't exist in the final
2563 * shader.
2564 *
2565 * This is only done if non-monolithic shaders are enabled.
2566 */
2567 if ((sel->type == PIPE_SHADER_VERTEX ||
2568 sel->type == PIPE_SHADER_TESS_EVAL) &&
2569 !shader->key.as_ls &&
2570 !shader->key.as_es) {
2571 unsigned i;
2572
2573 for (i = 0; i < sel->info.num_outputs; i++) {
2574 unsigned offset = shader->info.vs_output_param_offset[i];
2575
2576 if (offset <= AC_EXP_PARAM_OFFSET_31)
2577 continue;
2578
2579 unsigned name = sel->info.output_semantic_name[i];
2580 unsigned index = sel->info.output_semantic_index[i];
2581 unsigned id;
2582
2583 switch (name) {
2584 case TGSI_SEMANTIC_GENERIC:
2585 /* don't process indices the function can't handle */
2586 if (index >= SI_MAX_IO_GENERIC)
2587 break;
2588 /* fall through */
2589 default:
2590 id = si_shader_io_get_unique_index(name, index, true);
2591 sel->outputs_written_before_ps &= ~(1ull << id);
2592 break;
2593 case TGSI_SEMANTIC_POSITION: /* ignore these */
2594 case TGSI_SEMANTIC_PSIZE:
2595 case TGSI_SEMANTIC_CLIPVERTEX:
2596 case TGSI_SEMANTIC_EDGEFLAG:
2597 break;
2598 }
2599 }
2600 }
2601 }
2602
2603 /* The GS copy shader is always pre-compiled. */
2604 if (sel->type == PIPE_SHADER_GEOMETRY &&
2605 (!sscreen->use_ngg ||
2606 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2607 sel->tess_turns_off_ngg)) {
2608 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2609 if (!sel->gs_copy_shader) {
2610 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2611 return;
2612 }
2613
2614 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2615 }
2616
2617 /* Free NIR. We only keep serialized NIR after this point. */
2618 if (sel->nir) {
2619 ralloc_free(sel->nir);
2620 sel->nir = NULL;
2621 }
2622 }
2623
2624 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2625 struct util_queue_fence *ready_fence,
2626 struct si_compiler_ctx_state *compiler_ctx_state,
2627 void *job, util_queue_execute_func execute)
2628 {
2629 util_queue_fence_init(ready_fence);
2630
2631 struct util_async_debug_callback async_debug;
2632 bool debug =
2633 (sctx->debug.debug_message && !sctx->debug.async) ||
2634 sctx->is_debug ||
2635 si_can_dump_shader(sctx->screen, processor);
2636
2637 if (debug) {
2638 u_async_debug_init(&async_debug);
2639 compiler_ctx_state->debug = async_debug.base;
2640 }
2641
2642 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2643 ready_fence, execute, NULL, 0);
2644
2645 if (debug) {
2646 util_queue_fence_wait(ready_fence);
2647 u_async_debug_drain(&async_debug, &sctx->debug);
2648 u_async_debug_cleanup(&async_debug);
2649 }
2650
2651 if (sctx->screen->options.sync_compile)
2652 util_queue_fence_wait(ready_fence);
2653 }
2654
2655 /* Return descriptor slot usage masks from the given shader info. */
2656 void si_get_active_slot_masks(const struct si_shader_info *info,
2657 uint32_t *const_and_shader_buffers,
2658 uint64_t *samplers_and_images)
2659 {
2660 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2661
2662 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2663 num_constbufs = util_last_bit(info->const_buffers_declared);
2664 /* two 8-byte images share one 16-byte slot */
2665 num_images = align(util_last_bit(info->images_declared), 2);
2666 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2667 num_samplers = util_last_bit(info->samplers_declared);
2668
2669 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2670 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2671 *const_and_shader_buffers =
2672 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2673
2674 /* The layout is:
2675 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2676 * - image[last] ... image[0] go to [31-last .. 31]
2677 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2678 *
2679 * FMASKs for images are placed separately, because MSAA images are rare,
2680 * and so we can benefit from a better cache hit rate if we keep image
2681 * descriptors together.
2682 */
2683 if (num_msaa_images)
2684 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2685
2686 start = si_get_image_slot(num_images - 1) / 2;
2687 *samplers_and_images =
2688 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2689 }
2690
2691 static void *si_create_shader_selector(struct pipe_context *ctx,
2692 const struct pipe_shader_state *state)
2693 {
2694 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2695 struct si_context *sctx = (struct si_context*)ctx;
2696 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2697 int i;
2698
2699 if (!sel)
2700 return NULL;
2701
2702 pipe_reference_init(&sel->reference, 1);
2703 sel->screen = sscreen;
2704 sel->compiler_ctx_state.debug = sctx->debug;
2705 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2706
2707 sel->so = state->stream_output;
2708
2709 if (state->type == PIPE_SHADER_IR_TGSI) {
2710 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2711 } else {
2712 assert(state->type == PIPE_SHADER_IR_NIR);
2713 sel->nir = state->ir.nir;
2714 }
2715
2716 si_nir_scan_shader(sel->nir, &sel->info);
2717 si_nir_adjust_driver_locations(sel->nir);
2718
2719 sel->type = sel->info.processor;
2720 p_atomic_inc(&sscreen->num_shaders_created);
2721 si_get_active_slot_masks(&sel->info,
2722 &sel->active_const_and_shader_buffers,
2723 &sel->active_samplers_and_images);
2724
2725 /* Record which streamout buffers are enabled. */
2726 for (i = 0; i < sel->so.num_outputs; i++) {
2727 sel->enabled_streamout_buffer_mask |=
2728 (1 << sel->so.output[i].output_buffer) <<
2729 (sel->so.output[i].stream * 4);
2730 }
2731
2732 sel->num_vs_inputs = sel->type == PIPE_SHADER_VERTEX &&
2733 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] ?
2734 sel->info.num_inputs : 0;
2735 sel->num_vbos_in_user_sgprs =
2736 MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2737
2738 /* The prolog is a no-op if there are no inputs. */
2739 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2740 sel->info.num_inputs &&
2741 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2742
2743 sel->force_correct_derivs_after_kill =
2744 sel->type == PIPE_SHADER_FRAGMENT &&
2745 sel->info.uses_derivatives &&
2746 sel->info.uses_kill &&
2747 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2748
2749 sel->prim_discard_cs_allowed =
2750 sel->type == PIPE_SHADER_VERTEX &&
2751 !sel->info.uses_bindless_images &&
2752 !sel->info.uses_bindless_samplers &&
2753 !sel->info.writes_memory &&
2754 !sel->info.writes_viewport_index &&
2755 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2756 !sel->so.num_outputs;
2757
2758 switch (sel->type) {
2759 case PIPE_SHADER_GEOMETRY:
2760 sel->gs_output_prim =
2761 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2762
2763 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2764 sel->rast_prim = sel->gs_output_prim;
2765 if (util_rast_prim_is_triangles(sel->rast_prim))
2766 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2767
2768 sel->gs_max_out_vertices =
2769 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2770 sel->gs_num_invocations =
2771 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2772 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2773 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2774 sel->gs_max_out_vertices;
2775
2776 sel->max_gs_stream = 0;
2777 for (i = 0; i < sel->so.num_outputs; i++)
2778 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2779 sel->so.output[i].stream);
2780
2781 sel->gs_input_verts_per_prim =
2782 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2783
2784 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2785 sel->tess_turns_off_ngg =
2786 sscreen->info.chip_class == GFX10 &&
2787 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2788 break;
2789
2790 case PIPE_SHADER_TESS_CTRL:
2791 /* Always reserve space for these. */
2792 sel->patch_outputs_written |=
2793 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2794 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2795 /* fall through */
2796 case PIPE_SHADER_VERTEX:
2797 case PIPE_SHADER_TESS_EVAL:
2798 for (i = 0; i < sel->info.num_outputs; i++) {
2799 unsigned name = sel->info.output_semantic_name[i];
2800 unsigned index = sel->info.output_semantic_index[i];
2801
2802 switch (name) {
2803 case TGSI_SEMANTIC_TESSINNER:
2804 case TGSI_SEMANTIC_TESSOUTER:
2805 case TGSI_SEMANTIC_PATCH:
2806 sel->patch_outputs_written |=
2807 1ull << si_shader_io_get_unique_index_patch(name, index);
2808 break;
2809
2810 case TGSI_SEMANTIC_GENERIC:
2811 /* don't process indices the function can't handle */
2812 if (index >= SI_MAX_IO_GENERIC)
2813 break;
2814 /* fall through */
2815 default:
2816 sel->outputs_written |=
2817 1ull << si_shader_io_get_unique_index(name, index, false);
2818 sel->outputs_written_before_ps |=
2819 1ull << si_shader_io_get_unique_index(name, index, true);
2820 break;
2821 case TGSI_SEMANTIC_EDGEFLAG:
2822 break;
2823 }
2824 }
2825 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2826 sel->lshs_vertex_stride = sel->esgs_itemsize;
2827
2828 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2829 * will start on a different bank. (except for the maximum 32*16).
2830 */
2831 if (sel->lshs_vertex_stride < 32*16)
2832 sel->lshs_vertex_stride += 4;
2833
2834 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2835 * conflicts, i.e. each vertex will start at a different bank.
2836 */
2837 if (sctx->chip_class >= GFX9)
2838 sel->esgs_itemsize += 4;
2839
2840 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2841
2842 /* Only for TES: */
2843 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2844 sel->rast_prim = PIPE_PRIM_POINTS;
2845 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2846 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2847 else
2848 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2849 break;
2850
2851 case PIPE_SHADER_FRAGMENT:
2852 for (i = 0; i < sel->info.num_inputs; i++) {
2853 unsigned name = sel->info.input_semantic_name[i];
2854 unsigned index = sel->info.input_semantic_index[i];
2855
2856 switch (name) {
2857 case TGSI_SEMANTIC_GENERIC:
2858 /* don't process indices the function can't handle */
2859 if (index >= SI_MAX_IO_GENERIC)
2860 break;
2861 /* fall through */
2862 default:
2863 sel->inputs_read |=
2864 1ull << si_shader_io_get_unique_index(name, index, true);
2865 break;
2866 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2867 break;
2868 }
2869 }
2870
2871 for (i = 0; i < 8; i++)
2872 if (sel->info.colors_written & (1 << i))
2873 sel->colors_written_4bit |= 0xf << (4 * i);
2874
2875 for (i = 0; i < sel->info.num_inputs; i++) {
2876 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2877 int index = sel->info.input_semantic_index[i];
2878 sel->color_attr_index[index] = i;
2879 }
2880 }
2881 break;
2882 default:;
2883 }
2884
2885 /* PA_CL_VS_OUT_CNTL */
2886 if (sctx->chip_class <= GFX9)
2887 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2888
2889 sel->clipdist_mask = sel->info.writes_clipvertex ?
2890 SIX_BITS : sel->info.clipdist_writemask;
2891 sel->culldist_mask = sel->info.culldist_writemask <<
2892 sel->info.num_written_clipdistance;
2893
2894 /* DB_SHADER_CONTROL */
2895 sel->db_shader_control =
2896 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2897 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2898 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2899 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2900
2901 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2902 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2903 sel->db_shader_control |=
2904 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2905 break;
2906 case TGSI_FS_DEPTH_LAYOUT_LESS:
2907 sel->db_shader_control |=
2908 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2909 break;
2910 }
2911
2912 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2913 *
2914 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2915 * --|-----------|------------|------------|--------------------|-------------------|-------------
2916 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2917 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2918 * 2 | false | true | n/a | LateZ | 1 | 0
2919 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2920 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2921 *
2922 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2923 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2924 *
2925 * Don't use ReZ without profiling !!!
2926 *
2927 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2928 * shaders.
2929 */
2930 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2931 /* Cases 3, 4. */
2932 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2933 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2934 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2935 } else if (sel->info.writes_memory) {
2936 /* Case 2. */
2937 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2938 S_02880C_EXEC_ON_HIER_FAIL(1);
2939 } else {
2940 /* Case 1. */
2941 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2942 }
2943
2944 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2945 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2946
2947 (void) simple_mtx_init(&sel->mutex, mtx_plain);
2948
2949 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2950 &sel->compiler_ctx_state, sel,
2951 si_init_shader_selector_async);
2952 return sel;
2953 }
2954
2955 static void si_update_streamout_state(struct si_context *sctx)
2956 {
2957 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2958
2959 if (!shader_with_so)
2960 return;
2961
2962 sctx->streamout.enabled_stream_buffers_mask =
2963 shader_with_so->enabled_streamout_buffer_mask;
2964 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2965 }
2966
2967 static void si_update_clip_regs(struct si_context *sctx,
2968 struct si_shader_selector *old_hw_vs,
2969 struct si_shader *old_hw_vs_variant,
2970 struct si_shader_selector *next_hw_vs,
2971 struct si_shader *next_hw_vs_variant)
2972 {
2973 if (next_hw_vs &&
2974 (!old_hw_vs ||
2975 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2976 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2977 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2978 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2979 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2980 !old_hw_vs_variant ||
2981 !next_hw_vs_variant ||
2982 old_hw_vs_variant->key.opt.clip_disable !=
2983 next_hw_vs_variant->key.opt.clip_disable))
2984 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2985 }
2986
2987 static void si_update_common_shader_state(struct si_context *sctx)
2988 {
2989 sctx->uses_bindless_samplers =
2990 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2991 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2992 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2993 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2994 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2995 sctx->uses_bindless_images =
2996 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2997 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2998 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2999 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3000 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3001 sctx->do_update_shaders = true;
3002 }
3003
3004 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3005 {
3006 struct si_context *sctx = (struct si_context *)ctx;
3007 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3008 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3009 struct si_shader_selector *sel = state;
3010
3011 if (sctx->vs_shader.cso == sel)
3012 return;
3013
3014 sctx->vs_shader.cso = sel;
3015 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3016 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3017
3018 if (si_update_ngg(sctx))
3019 si_shader_change_notify(sctx);
3020
3021 si_update_common_shader_state(sctx);
3022 si_update_vs_viewport_state(sctx);
3023 si_set_active_descriptors_for_shader(sctx, sel);
3024 si_update_streamout_state(sctx);
3025 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3026 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3027 }
3028
3029 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3030 {
3031 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3032 (sctx->tes_shader.cso &&
3033 sctx->tes_shader.cso->info.uses_primid) ||
3034 (sctx->tcs_shader.cso &&
3035 sctx->tcs_shader.cso->info.uses_primid) ||
3036 (sctx->gs_shader.cso &&
3037 sctx->gs_shader.cso->info.uses_primid) ||
3038 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3039 sctx->ps_shader.cso->info.uses_primid);
3040 }
3041
3042 bool si_update_ngg(struct si_context *sctx)
3043 {
3044 if (!sctx->screen->use_ngg) {
3045 assert(!sctx->ngg);
3046 return false;
3047 }
3048
3049 bool new_ngg = true;
3050
3051 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3052 sctx->gs_shader.cso->tess_turns_off_ngg) {
3053 new_ngg = false;
3054 } else if (!sctx->screen->use_ngg_streamout) {
3055 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3056
3057 if ((last && last->so.num_outputs) ||
3058 sctx->streamout.prims_gen_query_enabled)
3059 new_ngg = false;
3060 }
3061
3062 if (new_ngg != sctx->ngg) {
3063 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3064 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3065 * pointers are set.
3066 */
3067 if ((sctx->family == CHIP_NAVI10 ||
3068 sctx->family == CHIP_NAVI12 ||
3069 sctx->family == CHIP_NAVI14) &&
3070 !new_ngg)
3071 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3072
3073 sctx->ngg = new_ngg;
3074 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3075 return true;
3076 }
3077 return false;
3078 }
3079
3080 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3081 {
3082 struct si_context *sctx = (struct si_context *)ctx;
3083 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3084 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3085 struct si_shader_selector *sel = state;
3086 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3087 bool ngg_changed;
3088
3089 if (sctx->gs_shader.cso == sel)
3090 return;
3091
3092 sctx->gs_shader.cso = sel;
3093 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3094 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3095
3096 si_update_common_shader_state(sctx);
3097 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3098
3099 ngg_changed = si_update_ngg(sctx);
3100 if (ngg_changed || enable_changed)
3101 si_shader_change_notify(sctx);
3102 if (enable_changed) {
3103 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3104 si_update_tess_uses_prim_id(sctx);
3105 }
3106 si_update_vs_viewport_state(sctx);
3107 si_set_active_descriptors_for_shader(sctx, sel);
3108 si_update_streamout_state(sctx);
3109 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3110 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3111 }
3112
3113 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3114 {
3115 struct si_context *sctx = (struct si_context *)ctx;
3116 struct si_shader_selector *sel = state;
3117 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3118
3119 if (sctx->tcs_shader.cso == sel)
3120 return;
3121
3122 sctx->tcs_shader.cso = sel;
3123 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3124 si_update_tess_uses_prim_id(sctx);
3125
3126 si_update_common_shader_state(sctx);
3127
3128 if (enable_changed)
3129 sctx->last_tcs = NULL; /* invalidate derived tess state */
3130
3131 si_set_active_descriptors_for_shader(sctx, sel);
3132 }
3133
3134 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3135 {
3136 struct si_context *sctx = (struct si_context *)ctx;
3137 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3138 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3139 struct si_shader_selector *sel = state;
3140 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3141
3142 if (sctx->tes_shader.cso == sel)
3143 return;
3144
3145 sctx->tes_shader.cso = sel;
3146 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3147 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3148 si_update_tess_uses_prim_id(sctx);
3149
3150 si_update_common_shader_state(sctx);
3151 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3152
3153 bool ngg_changed = si_update_ngg(sctx);
3154 if (ngg_changed || enable_changed)
3155 si_shader_change_notify(sctx);
3156 if (enable_changed)
3157 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3158 si_update_vs_viewport_state(sctx);
3159 si_set_active_descriptors_for_shader(sctx, sel);
3160 si_update_streamout_state(sctx);
3161 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3162 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3163 }
3164
3165 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3166 {
3167 struct si_context *sctx = (struct si_context *)ctx;
3168 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3169 struct si_shader_selector *sel = state;
3170
3171 /* skip if supplied shader is one already in use */
3172 if (old_sel == sel)
3173 return;
3174
3175 sctx->ps_shader.cso = sel;
3176 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3177
3178 si_update_common_shader_state(sctx);
3179 if (sel) {
3180 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3181 si_update_tess_uses_prim_id(sctx);
3182
3183 if (!old_sel ||
3184 old_sel->info.colors_written != sel->info.colors_written)
3185 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3186
3187 if (sctx->screen->has_out_of_order_rast &&
3188 (!old_sel ||
3189 old_sel->info.writes_memory != sel->info.writes_memory ||
3190 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3191 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3192 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3193 }
3194 si_set_active_descriptors_for_shader(sctx, sel);
3195 si_update_ps_colorbuf0_slot(sctx);
3196 }
3197
3198 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3199 {
3200 if (shader->is_optimized) {
3201 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3202 &shader->ready);
3203 }
3204
3205 util_queue_fence_destroy(&shader->ready);
3206
3207 if (shader->pm4) {
3208 /* If destroyed shaders were not unbound, the next compiled
3209 * shader variant could get the same pointer address and so
3210 * binding it to the same shader stage would be considered
3211 * a no-op, causing random behavior.
3212 */
3213 switch (shader->selector->type) {
3214 case PIPE_SHADER_VERTEX:
3215 if (shader->key.as_ls) {
3216 assert(sctx->chip_class <= GFX8);
3217 si_pm4_delete_state(sctx, ls, shader->pm4);
3218 } else if (shader->key.as_es) {
3219 assert(sctx->chip_class <= GFX8);
3220 si_pm4_delete_state(sctx, es, shader->pm4);
3221 } else if (shader->key.as_ngg) {
3222 si_pm4_delete_state(sctx, gs, shader->pm4);
3223 } else {
3224 si_pm4_delete_state(sctx, vs, shader->pm4);
3225 }
3226 break;
3227 case PIPE_SHADER_TESS_CTRL:
3228 si_pm4_delete_state(sctx, hs, shader->pm4);
3229 break;
3230 case PIPE_SHADER_TESS_EVAL:
3231 if (shader->key.as_es) {
3232 assert(sctx->chip_class <= GFX8);
3233 si_pm4_delete_state(sctx, es, shader->pm4);
3234 } else if (shader->key.as_ngg) {
3235 si_pm4_delete_state(sctx, gs, shader->pm4);
3236 } else {
3237 si_pm4_delete_state(sctx, vs, shader->pm4);
3238 }
3239 break;
3240 case PIPE_SHADER_GEOMETRY:
3241 if (shader->is_gs_copy_shader)
3242 si_pm4_delete_state(sctx, vs, shader->pm4);
3243 else
3244 si_pm4_delete_state(sctx, gs, shader->pm4);
3245 break;
3246 case PIPE_SHADER_FRAGMENT:
3247 si_pm4_delete_state(sctx, ps, shader->pm4);
3248 break;
3249 default:;
3250 }
3251 }
3252
3253 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3254 si_shader_destroy(shader);
3255 free(shader);
3256 }
3257
3258 void si_destroy_shader_selector(struct si_context *sctx,
3259 struct si_shader_selector *sel)
3260 {
3261 struct si_shader *p = sel->first_variant, *c;
3262 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3263 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3264 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3265 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3266 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3267 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3268 };
3269
3270 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3271
3272 if (current_shader[sel->type]->cso == sel) {
3273 current_shader[sel->type]->cso = NULL;
3274 current_shader[sel->type]->current = NULL;
3275 }
3276
3277 while (p) {
3278 c = p->next_variant;
3279 si_delete_shader(sctx, p);
3280 p = c;
3281 }
3282
3283 if (sel->main_shader_part)
3284 si_delete_shader(sctx, sel->main_shader_part);
3285 if (sel->main_shader_part_ls)
3286 si_delete_shader(sctx, sel->main_shader_part_ls);
3287 if (sel->main_shader_part_es)
3288 si_delete_shader(sctx, sel->main_shader_part_es);
3289 if (sel->main_shader_part_ngg)
3290 si_delete_shader(sctx, sel->main_shader_part_ngg);
3291 if (sel->gs_copy_shader)
3292 si_delete_shader(sctx, sel->gs_copy_shader);
3293
3294 util_queue_fence_destroy(&sel->ready);
3295 simple_mtx_destroy(&sel->mutex);
3296 ralloc_free(sel->nir);
3297 free(sel->nir_binary);
3298 free(sel);
3299 }
3300
3301 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3302 {
3303 struct si_context *sctx = (struct si_context *)ctx;
3304 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3305
3306 si_shader_selector_reference(sctx, &sel, NULL);
3307 }
3308
3309 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3310 struct si_shader *vs, unsigned name,
3311 unsigned index, unsigned interpolate)
3312 {
3313 struct si_shader_info *vsinfo = &vs->selector->info;
3314 unsigned j, offset, ps_input_cntl = 0;
3315
3316 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3317 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3318 name == TGSI_SEMANTIC_PRIMID)
3319 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3320
3321 if (name == TGSI_SEMANTIC_PCOORD ||
3322 (name == TGSI_SEMANTIC_TEXCOORD &&
3323 sctx->sprite_coord_enable & (1 << index))) {
3324 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3325 }
3326
3327 for (j = 0; j < vsinfo->num_outputs; j++) {
3328 if (name == vsinfo->output_semantic_name[j] &&
3329 index == vsinfo->output_semantic_index[j]) {
3330 offset = vs->info.vs_output_param_offset[j];
3331
3332 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3333 /* The input is loaded from parameter memory. */
3334 ps_input_cntl |= S_028644_OFFSET(offset);
3335 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3336 if (offset == AC_EXP_PARAM_UNDEFINED) {
3337 /* This can happen with depth-only rendering. */
3338 offset = 0;
3339 } else {
3340 /* The input is a DEFAULT_VAL constant. */
3341 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3342 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3343 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3344 }
3345
3346 ps_input_cntl = S_028644_OFFSET(0x20) |
3347 S_028644_DEFAULT_VAL(offset);
3348 }
3349 break;
3350 }
3351 }
3352
3353 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3354 /* PrimID is written after the last output when HW VS is used. */
3355 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3356 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3357 /* No corresponding output found, load defaults into input.
3358 * Don't set any other bits.
3359 * (FLAT_SHADE=1 completely changes behavior) */
3360 ps_input_cntl = S_028644_OFFSET(0x20);
3361 /* D3D 9 behaviour. GL is undefined */
3362 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3363 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3364 }
3365 return ps_input_cntl;
3366 }
3367
3368 static void si_emit_spi_map(struct si_context *sctx)
3369 {
3370 struct si_shader *ps = sctx->ps_shader.current;
3371 struct si_shader *vs = si_get_vs_state(sctx);
3372 struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3373 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3374 unsigned spi_ps_input_cntl[32];
3375
3376 if (!ps || !ps->selector->info.num_inputs)
3377 return;
3378
3379 num_interp = si_get_ps_num_interp(ps);
3380 assert(num_interp > 0);
3381
3382 for (i = 0; i < psinfo->num_inputs; i++) {
3383 unsigned name = psinfo->input_semantic_name[i];
3384 unsigned index = psinfo->input_semantic_index[i];
3385 unsigned interpolate = psinfo->input_interpolate[i];
3386
3387 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3388 index, interpolate);
3389
3390 if (name == TGSI_SEMANTIC_COLOR) {
3391 assert(index < ARRAY_SIZE(bcol_interp));
3392 bcol_interp[index] = interpolate;
3393 }
3394 }
3395
3396 if (ps->key.part.ps.prolog.color_two_side) {
3397 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3398
3399 for (i = 0; i < 2; i++) {
3400 if (!(psinfo->colors_read & (0xf << (i * 4))))
3401 continue;
3402
3403 spi_ps_input_cntl[num_written++] =
3404 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3405
3406 }
3407 }
3408 assert(num_interp == num_written);
3409
3410 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3411 /* Dota 2: Only ~16% of SPI map updates set different values. */
3412 /* Talos: Only ~9% of SPI map updates set different values. */
3413 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3414 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3415 spi_ps_input_cntl,
3416 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3417
3418 if (initial_cdw != sctx->gfx_cs->current.cdw)
3419 sctx->context_roll = true;
3420 }
3421
3422 /**
3423 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3424 */
3425 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3426 {
3427 if (sctx->init_config_has_vgt_flush)
3428 return;
3429
3430 /* Done by Vulkan before VGT_FLUSH. */
3431 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3432 si_pm4_cmd_add(sctx->init_config,
3433 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3434 si_pm4_cmd_end(sctx->init_config, false);
3435
3436 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3437 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3438 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3439 si_pm4_cmd_end(sctx->init_config, false);
3440 sctx->init_config_has_vgt_flush = true;
3441 }
3442
3443 /* Initialize state related to ESGS / GSVS ring buffers */
3444 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3445 {
3446 struct si_shader_selector *es =
3447 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3448 struct si_shader_selector *gs = sctx->gs_shader.cso;
3449 struct si_pm4_state *pm4;
3450
3451 /* Chip constants. */
3452 unsigned num_se = sctx->screen->info.max_se;
3453 unsigned wave_size = 64;
3454 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3455 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3456 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3457 */
3458 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3459 unsigned alignment = 256 * num_se;
3460 /* The maximum size is 63.999 MB per SE. */
3461 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3462
3463 /* Calculate the minimum size. */
3464 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3465 wave_size, alignment);
3466
3467 /* These are recommended sizes, not minimum sizes. */
3468 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3469 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3470 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3471 gs->max_gsvs_emit_size;
3472
3473 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3474 esgs_ring_size = align(esgs_ring_size, alignment);
3475 gsvs_ring_size = align(gsvs_ring_size, alignment);
3476
3477 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3478 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3479
3480 /* Some rings don't have to be allocated if shaders don't use them.
3481 * (e.g. no varyings between ES and GS or GS and VS)
3482 *
3483 * GFX9 doesn't have the ESGS ring.
3484 */
3485 bool update_esgs = sctx->chip_class <= GFX8 &&
3486 esgs_ring_size &&
3487 (!sctx->esgs_ring ||
3488 sctx->esgs_ring->width0 < esgs_ring_size);
3489 bool update_gsvs = gsvs_ring_size &&
3490 (!sctx->gsvs_ring ||
3491 sctx->gsvs_ring->width0 < gsvs_ring_size);
3492
3493 if (!update_esgs && !update_gsvs)
3494 return true;
3495
3496 if (update_esgs) {
3497 pipe_resource_reference(&sctx->esgs_ring, NULL);
3498 sctx->esgs_ring =
3499 pipe_aligned_buffer_create(sctx->b.screen,
3500 SI_RESOURCE_FLAG_UNMAPPABLE,
3501 PIPE_USAGE_DEFAULT,
3502 esgs_ring_size,
3503 sctx->screen->info.pte_fragment_size);
3504 if (!sctx->esgs_ring)
3505 return false;
3506 }
3507
3508 if (update_gsvs) {
3509 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3510 sctx->gsvs_ring =
3511 pipe_aligned_buffer_create(sctx->b.screen,
3512 SI_RESOURCE_FLAG_UNMAPPABLE,
3513 PIPE_USAGE_DEFAULT,
3514 gsvs_ring_size,
3515 sctx->screen->info.pte_fragment_size);
3516 if (!sctx->gsvs_ring)
3517 return false;
3518 }
3519
3520 /* Create the "init_config_gs_rings" state. */
3521 pm4 = CALLOC_STRUCT(si_pm4_state);
3522 if (!pm4)
3523 return false;
3524
3525 if (sctx->chip_class >= GFX7) {
3526 if (sctx->esgs_ring) {
3527 assert(sctx->chip_class <= GFX8);
3528 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3529 sctx->esgs_ring->width0 / 256);
3530 }
3531 if (sctx->gsvs_ring)
3532 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3533 sctx->gsvs_ring->width0 / 256);
3534 } else {
3535 if (sctx->esgs_ring)
3536 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3537 sctx->esgs_ring->width0 / 256);
3538 if (sctx->gsvs_ring)
3539 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3540 sctx->gsvs_ring->width0 / 256);
3541 }
3542
3543 /* Set the state. */
3544 if (sctx->init_config_gs_rings)
3545 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3546 sctx->init_config_gs_rings = pm4;
3547
3548 if (!sctx->init_config_has_vgt_flush) {
3549 si_init_config_add_vgt_flush(sctx);
3550 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3551 }
3552
3553 /* Flush the context to re-emit both init_config states. */
3554 sctx->initial_gfx_cs_size = 0; /* force flush */
3555 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3556
3557 /* Set ring bindings. */
3558 if (sctx->esgs_ring) {
3559 assert(sctx->chip_class <= GFX8);
3560 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3561 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3562 true, true, 4, 64, 0);
3563 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3564 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3565 false, false, 0, 0, 0);
3566 }
3567 if (sctx->gsvs_ring) {
3568 si_set_ring_buffer(sctx, SI_RING_GSVS,
3569 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3570 false, false, 0, 0, 0);
3571 }
3572
3573 return true;
3574 }
3575
3576 static void si_shader_lock(struct si_shader *shader)
3577 {
3578 simple_mtx_lock(&shader->selector->mutex);
3579 if (shader->previous_stage_sel) {
3580 assert(shader->previous_stage_sel != shader->selector);
3581 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3582 }
3583 }
3584
3585 static void si_shader_unlock(struct si_shader *shader)
3586 {
3587 if (shader->previous_stage_sel)
3588 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3589 simple_mtx_unlock(&shader->selector->mutex);
3590 }
3591
3592 /**
3593 * @returns 1 if \p sel has been updated to use a new scratch buffer
3594 * 0 if not
3595 * < 0 if there was a failure
3596 */
3597 static int si_update_scratch_buffer(struct si_context *sctx,
3598 struct si_shader *shader)
3599 {
3600 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3601
3602 if (!shader)
3603 return 0;
3604
3605 /* This shader doesn't need a scratch buffer */
3606 if (shader->config.scratch_bytes_per_wave == 0)
3607 return 0;
3608
3609 /* Prevent race conditions when updating:
3610 * - si_shader::scratch_bo
3611 * - si_shader::binary::code
3612 * - si_shader::previous_stage::binary::code.
3613 */
3614 si_shader_lock(shader);
3615
3616 /* This shader is already configured to use the current
3617 * scratch buffer. */
3618 if (shader->scratch_bo == sctx->scratch_buffer) {
3619 si_shader_unlock(shader);
3620 return 0;
3621 }
3622
3623 assert(sctx->scratch_buffer);
3624
3625 /* Replace the shader bo with a new bo that has the relocs applied. */
3626 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3627 si_shader_unlock(shader);
3628 return -1;
3629 }
3630
3631 /* Update the shader state to use the new shader bo. */
3632 si_shader_init_pm4_state(sctx->screen, shader);
3633
3634 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3635
3636 si_shader_unlock(shader);
3637 return 1;
3638 }
3639
3640 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3641 {
3642 return shader ? shader->config.scratch_bytes_per_wave : 0;
3643 }
3644
3645 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3646 {
3647 if (!sctx->tes_shader.cso)
3648 return NULL; /* tessellation disabled */
3649
3650 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3651 sctx->fixed_func_tcs_shader.current;
3652 }
3653
3654 static bool si_update_scratch_relocs(struct si_context *sctx)
3655 {
3656 struct si_shader *tcs = si_get_tcs_current(sctx);
3657 int r;
3658
3659 /* Update the shaders, so that they are using the latest scratch.
3660 * The scratch buffer may have been changed since these shaders were
3661 * last used, so we still need to try to update them, even if they
3662 * require scratch buffers smaller than the current size.
3663 */
3664 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3665 if (r < 0)
3666 return false;
3667 if (r == 1)
3668 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3669
3670 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3671 if (r < 0)
3672 return false;
3673 if (r == 1)
3674 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3675
3676 r = si_update_scratch_buffer(sctx, tcs);
3677 if (r < 0)
3678 return false;
3679 if (r == 1)
3680 si_pm4_bind_state(sctx, hs, tcs->pm4);
3681
3682 /* VS can be bound as LS, ES, or VS. */
3683 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3684 if (r < 0)
3685 return false;
3686 if (r == 1) {
3687 if (sctx->vs_shader.current->key.as_ls)
3688 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3689 else if (sctx->vs_shader.current->key.as_es)
3690 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3691 else if (sctx->vs_shader.current->key.as_ngg)
3692 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3693 else
3694 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3695 }
3696
3697 /* TES can be bound as ES or VS. */
3698 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3699 if (r < 0)
3700 return false;
3701 if (r == 1) {
3702 if (sctx->tes_shader.current->key.as_es)
3703 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3704 else if (sctx->tes_shader.current->key.as_ngg)
3705 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3706 else
3707 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3708 }
3709
3710 return true;
3711 }
3712
3713 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3714 {
3715 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3716 * There are 2 cases to handle:
3717 *
3718 * - If the current needed size is less than the maximum seen size,
3719 * use the maximum seen size, so that WAVESIZE remains the same.
3720 *
3721 * - If the current needed size is greater than the maximum seen size,
3722 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3723 *
3724 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3725 * Otherwise, the number of waves that can use scratch is
3726 * SPI_TMPRING_SIZE.WAVES.
3727 */
3728 unsigned bytes = 0;
3729
3730 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3731 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3732 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3733
3734 if (sctx->tes_shader.cso) {
3735 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3736 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3737 }
3738
3739 sctx->max_seen_scratch_bytes_per_wave =
3740 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3741
3742 unsigned scratch_needed_size =
3743 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3744 unsigned spi_tmpring_size;
3745
3746 if (scratch_needed_size > 0) {
3747 if (!sctx->scratch_buffer ||
3748 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3749 /* Create a bigger scratch buffer */
3750 si_resource_reference(&sctx->scratch_buffer, NULL);
3751
3752 sctx->scratch_buffer =
3753 si_aligned_buffer_create(&sctx->screen->b,
3754 SI_RESOURCE_FLAG_UNMAPPABLE,
3755 PIPE_USAGE_DEFAULT,
3756 scratch_needed_size,
3757 sctx->screen->info.pte_fragment_size);
3758 if (!sctx->scratch_buffer)
3759 return false;
3760
3761 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3762 si_context_add_resource_size(sctx,
3763 &sctx->scratch_buffer->b.b);
3764 }
3765
3766 if (!si_update_scratch_relocs(sctx))
3767 return false;
3768 }
3769
3770 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3771 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3772 "scratch size should already be aligned correctly.");
3773
3774 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3775 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3776 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3777 sctx->spi_tmpring_size = spi_tmpring_size;
3778 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3779 }
3780 return true;
3781 }
3782
3783 static void si_init_tess_factor_ring(struct si_context *sctx)
3784 {
3785 assert(!sctx->tess_rings);
3786 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3787
3788 /* The address must be aligned to 2^19, because the shader only
3789 * receives the high 13 bits.
3790 */
3791 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3792 SI_RESOURCE_FLAG_32BIT,
3793 PIPE_USAGE_DEFAULT,
3794 sctx->screen->tess_offchip_ring_size +
3795 sctx->screen->tess_factor_ring_size,
3796 1 << 19);
3797 if (!sctx->tess_rings)
3798 return;
3799
3800 si_init_config_add_vgt_flush(sctx);
3801
3802 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3803 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3804
3805 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3806 sctx->screen->tess_offchip_ring_size;
3807
3808 /* Append these registers to the init config state. */
3809 if (sctx->chip_class >= GFX7) {
3810 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3811 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3812 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3813 factor_va >> 8);
3814 if (sctx->chip_class >= GFX10)
3815 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3816 S_030984_BASE_HI(factor_va >> 40));
3817 else if (sctx->chip_class == GFX9)
3818 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3819 S_030944_BASE_HI(factor_va >> 40));
3820 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3821 sctx->screen->vgt_hs_offchip_param);
3822 } else {
3823 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3824 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3825 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3826 factor_va >> 8);
3827 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3828 sctx->screen->vgt_hs_offchip_param);
3829 }
3830
3831 /* Flush the context to re-emit the init_config state.
3832 * This is done only once in a lifetime of a context.
3833 */
3834 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3835 sctx->initial_gfx_cs_size = 0; /* force flush */
3836 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3837 }
3838
3839 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3840 union si_vgt_stages_key key)
3841 {
3842 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3843 uint32_t stages = 0;
3844
3845 if (key.u.tess) {
3846 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3847 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3848
3849 if (key.u.gs)
3850 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3851 S_028B54_GS_EN(1);
3852 else if (key.u.ngg)
3853 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3854 else
3855 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3856 } else if (key.u.gs) {
3857 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3858 S_028B54_GS_EN(1);
3859 } else if (key.u.ngg) {
3860 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3861 }
3862
3863 if (key.u.ngg) {
3864 stages |= S_028B54_PRIMGEN_EN(1) |
3865 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3866 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3867 } else if (key.u.gs)
3868 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3869
3870 if (screen->info.chip_class >= GFX9)
3871 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3872
3873 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3874 stages |= S_028B54_HS_W32_EN(1) |
3875 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3876 S_028B54_VS_W32_EN(1);
3877 }
3878
3879 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3880 return pm4;
3881 }
3882
3883 static void si_update_vgt_shader_config(struct si_context *sctx,
3884 union si_vgt_stages_key key)
3885 {
3886 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3887
3888 if (unlikely(!*pm4))
3889 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3890 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3891 }
3892
3893 bool si_update_shaders(struct si_context *sctx)
3894 {
3895 struct pipe_context *ctx = (struct pipe_context*)sctx;
3896 struct si_compiler_ctx_state compiler_state;
3897 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3898 struct si_shader *old_vs = si_get_vs_state(sctx);
3899 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3900 struct si_shader *old_ps = sctx->ps_shader.current;
3901 union si_vgt_stages_key key;
3902 unsigned old_spi_shader_col_format =
3903 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3904 int r;
3905
3906 if (!sctx->compiler.passes)
3907 si_init_compiler(sctx->screen, &sctx->compiler);
3908
3909 compiler_state.compiler = &sctx->compiler;
3910 compiler_state.debug = sctx->debug;
3911 compiler_state.is_debug_context = sctx->is_debug;
3912
3913 key.index = 0;
3914
3915 if (sctx->tes_shader.cso)
3916 key.u.tess = 1;
3917 if (sctx->gs_shader.cso)
3918 key.u.gs = 1;
3919
3920 if (sctx->ngg) {
3921 key.u.ngg = 1;
3922 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3923 }
3924
3925 /* Update TCS and TES. */
3926 if (sctx->tes_shader.cso) {
3927 if (!sctx->tess_rings) {
3928 si_init_tess_factor_ring(sctx);
3929 if (!sctx->tess_rings)
3930 return false;
3931 }
3932
3933 if (sctx->tcs_shader.cso) {
3934 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3935 &compiler_state);
3936 if (r)
3937 return false;
3938 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3939 } else {
3940 if (!sctx->fixed_func_tcs_shader.cso) {
3941 sctx->fixed_func_tcs_shader.cso =
3942 si_create_fixed_func_tcs(sctx);
3943 if (!sctx->fixed_func_tcs_shader.cso)
3944 return false;
3945 }
3946
3947 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3948 key, &compiler_state);
3949 if (r)
3950 return false;
3951 si_pm4_bind_state(sctx, hs,
3952 sctx->fixed_func_tcs_shader.current->pm4);
3953 }
3954
3955 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3956 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3957 if (r)
3958 return false;
3959
3960 if (sctx->gs_shader.cso) {
3961 /* TES as ES */
3962 assert(sctx->chip_class <= GFX8);
3963 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3964 } else if (key.u.ngg) {
3965 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3966 } else {
3967 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3968 }
3969 }
3970 } else {
3971 if (sctx->chip_class <= GFX8)
3972 si_pm4_bind_state(sctx, ls, NULL);
3973 si_pm4_bind_state(sctx, hs, NULL);
3974 }
3975
3976 /* Update GS. */
3977 if (sctx->gs_shader.cso) {
3978 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3979 if (r)
3980 return false;
3981 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3982 if (!key.u.ngg) {
3983 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3984
3985 if (!si_update_gs_ring_buffers(sctx))
3986 return false;
3987 } else {
3988 si_pm4_bind_state(sctx, vs, NULL);
3989 }
3990 } else {
3991 if (!key.u.ngg) {
3992 si_pm4_bind_state(sctx, gs, NULL);
3993 if (sctx->chip_class <= GFX8)
3994 si_pm4_bind_state(sctx, es, NULL);
3995 }
3996 }
3997
3998 /* Update VS. */
3999 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
4000 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
4001 if (r)
4002 return false;
4003
4004 if (!key.u.tess && !key.u.gs) {
4005 if (key.u.ngg) {
4006 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
4007 si_pm4_bind_state(sctx, vs, NULL);
4008 } else {
4009 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4010 }
4011 } else if (sctx->tes_shader.cso) {
4012 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4013 } else {
4014 assert(sctx->gs_shader.cso);
4015 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4016 }
4017 }
4018
4019 /* This must be done after the shader variant is selected. */
4020 if (sctx->ngg)
4021 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(si_get_vs(sctx)->current);
4022
4023 si_update_vgt_shader_config(sctx, key);
4024
4025 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4026 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4027
4028 if (sctx->ps_shader.cso) {
4029 unsigned db_shader_control;
4030
4031 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4032 if (r)
4033 return false;
4034 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4035
4036 db_shader_control =
4037 sctx->ps_shader.cso->db_shader_control |
4038 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4039
4040 if (si_pm4_state_changed(sctx, ps) ||
4041 si_pm4_state_changed(sctx, vs) ||
4042 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4043 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4044 sctx->flatshade != rs->flatshade) {
4045 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4046 sctx->flatshade = rs->flatshade;
4047 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4048 }
4049
4050 if (sctx->screen->info.rbplus_allowed &&
4051 si_pm4_state_changed(sctx, ps) &&
4052 (!old_ps ||
4053 old_spi_shader_col_format !=
4054 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4055 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4056
4057 if (sctx->ps_db_shader_control != db_shader_control) {
4058 sctx->ps_db_shader_control = db_shader_control;
4059 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4060 if (sctx->screen->dpbb_allowed)
4061 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4062 }
4063
4064 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4065 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4066 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4067
4068 if (sctx->chip_class == GFX6)
4069 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4070
4071 if (sctx->framebuffer.nr_samples <= 1)
4072 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4073 }
4074 }
4075
4076 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4077 si_pm4_state_enabled_and_changed(sctx, hs) ||
4078 si_pm4_state_enabled_and_changed(sctx, es) ||
4079 si_pm4_state_enabled_and_changed(sctx, gs) ||
4080 si_pm4_state_enabled_and_changed(sctx, vs) ||
4081 si_pm4_state_enabled_and_changed(sctx, ps)) {
4082 if (!si_update_spi_tmpring_size(sctx))
4083 return false;
4084 }
4085
4086 if (sctx->chip_class >= GFX7) {
4087 if (si_pm4_state_enabled_and_changed(sctx, ls))
4088 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4089 else if (!sctx->queued.named.ls)
4090 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4091
4092 if (si_pm4_state_enabled_and_changed(sctx, hs))
4093 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4094 else if (!sctx->queued.named.hs)
4095 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4096
4097 if (si_pm4_state_enabled_and_changed(sctx, es))
4098 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4099 else if (!sctx->queued.named.es)
4100 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4101
4102 if (si_pm4_state_enabled_and_changed(sctx, gs))
4103 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4104 else if (!sctx->queued.named.gs)
4105 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4106
4107 if (si_pm4_state_enabled_and_changed(sctx, vs))
4108 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4109 else if (!sctx->queued.named.vs)
4110 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4111
4112 if (si_pm4_state_enabled_and_changed(sctx, ps))
4113 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4114 else if (!sctx->queued.named.ps)
4115 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4116 }
4117
4118 sctx->do_update_shaders = false;
4119 return true;
4120 }
4121
4122 static void si_emit_scratch_state(struct si_context *sctx)
4123 {
4124 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4125
4126 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4127 sctx->spi_tmpring_size);
4128
4129 if (sctx->scratch_buffer) {
4130 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4131 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4132 RADEON_PRIO_SCRATCH_BUFFER);
4133 }
4134 }
4135
4136 void si_init_shader_functions(struct si_context *sctx)
4137 {
4138 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4139 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4140
4141 sctx->b.create_vs_state = si_create_shader_selector;
4142 sctx->b.create_tcs_state = si_create_shader_selector;
4143 sctx->b.create_tes_state = si_create_shader_selector;
4144 sctx->b.create_gs_state = si_create_shader_selector;
4145 sctx->b.create_fs_state = si_create_shader_selector;
4146
4147 sctx->b.bind_vs_state = si_bind_vs_shader;
4148 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4149 sctx->b.bind_tes_state = si_bind_tes_shader;
4150 sctx->b.bind_gs_state = si_bind_gs_shader;
4151 sctx->b.bind_fs_state = si_bind_ps_shader;
4152
4153 sctx->b.delete_vs_state = si_delete_shader_selector;
4154 sctx->b.delete_tcs_state = si_delete_shader_selector;
4155 sctx->b.delete_tes_state = si_delete_shader_selector;
4156 sctx->b.delete_gs_state = si_delete_shader_selector;
4157 sctx->b.delete_fs_state = si_delete_shader_selector;
4158 }