2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
47 void *si_get_ir_binary(struct si_shader_selector
*sel
)
54 ir_binary
= sel
->tokens
;
55 ir_size
= tgsi_num_tokens(sel
->tokens
) *
56 sizeof(struct tgsi_token
);
61 nir_serialize(&blob
, sel
->nir
);
62 ir_binary
= blob
.data
;
66 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
67 char *result
= (char*)MALLOC(size
);
71 *((uint32_t*)result
) = size
;
72 memcpy(result
+ 4, ir_binary
, ir_size
);
73 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
84 /* data may be NULL if size == 0 */
86 memcpy(ptr
, data
, size
);
87 ptr
+= DIV_ROUND_UP(size
, 4);
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
94 memcpy(data
, ptr
, size
);
95 ptr
+= DIV_ROUND_UP(size
, 4);
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
103 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
106 return write_data(ptr
, data
, size
);
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
113 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
116 assert(*data
== NULL
);
119 *data
= malloc(*size
);
120 return read_data(ptr
, *data
, *size
);
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
127 static void *si_get_shader_binary(struct si_shader
*shader
)
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
131 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
133 /* Refuse to allocate overly large buffers and guard against integer
135 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
136 llvm_ir_size
> UINT_MAX
/ 4)
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader
->config
), 4) +
143 align(sizeof(shader
->info
), 4) +
144 4 + align(shader
->binary
.elf_size
, 4) +
145 4 + align(llvm_ir_size
, 4);
146 void *buffer
= CALLOC(1, size
);
147 uint32_t *ptr
= (uint32_t*)buffer
;
153 ptr
++; /* CRC32 is calculated at the end. */
155 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
156 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
157 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
158 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
159 assert((char *)ptr
- (char *)buffer
== size
);
162 ptr
= (uint32_t*)buffer
;
164 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
169 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
171 uint32_t *ptr
= (uint32_t*)binary
;
172 uint32_t size
= *ptr
++;
173 uint32_t crc32
= *ptr
++;
177 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
178 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
182 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
183 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
184 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
186 shader
->binary
.elf_size
= elf_size
;
187 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
196 * Returns false on failure, in which case the ir_binary should be freed.
198 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
199 struct si_shader
*shader
,
200 bool insert_into_disk_cache
)
203 struct hash_entry
*entry
;
204 uint8_t key
[CACHE_KEY_SIZE
];
206 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
208 return false; /* already added */
210 hw_binary
= si_get_shader_binary(shader
);
214 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
215 hw_binary
) == NULL
) {
220 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
221 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
222 *((uint32_t *)ir_binary
), key
);
223 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
224 *((uint32_t *) hw_binary
), NULL
);
230 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
231 struct si_shader
*shader
)
233 struct hash_entry
*entry
=
234 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
236 if (sscreen
->disk_shader_cache
) {
237 unsigned char sha1
[CACHE_KEY_SIZE
];
238 size_t tg_size
= *((uint32_t *) ir_binary
);
240 disk_cache_compute_key(sscreen
->disk_shader_cache
,
241 ir_binary
, tg_size
, sha1
);
245 disk_cache_get(sscreen
->disk_shader_cache
,
250 if (binary_size
< sizeof(uint32_t) ||
251 *((uint32_t*)buffer
) != binary_size
) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
256 assert(!"Invalid radeonsi shader disk cache "
259 disk_cache_remove(sscreen
->disk_shader_cache
,
266 if (!si_load_shader_binary(shader
, buffer
)) {
272 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
279 if (si_load_shader_binary(shader
, entry
->data
))
284 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
288 static uint32_t si_shader_cache_key_hash(const void *key
)
290 /* The first dword is the key size. */
291 return util_hash_crc32(key
, *(uint32_t*)key
);
294 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
296 uint32_t *keya
= (uint32_t*)a
;
297 uint32_t *keyb
= (uint32_t*)b
;
299 /* The first dword is the key size. */
303 return memcmp(keya
, keyb
, *keya
) == 0;
306 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
308 FREE((void*)entry
->key
);
312 bool si_init_shader_cache(struct si_screen
*sscreen
)
314 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
315 sscreen
->shader_cache
=
316 _mesa_hash_table_create(NULL
,
317 si_shader_cache_key_hash
,
318 si_shader_cache_key_equals
);
320 return sscreen
->shader_cache
!= NULL
;
323 void si_destroy_shader_cache(struct si_screen
*sscreen
)
325 if (sscreen
->shader_cache
)
326 _mesa_hash_table_destroy(sscreen
->shader_cache
,
327 si_destroy_shader_cache_entry
);
328 mtx_destroy(&sscreen
->shader_cache_mutex
);
333 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
334 const struct si_shader_selector
*tes
,
335 struct si_pm4_state
*pm4
)
337 const struct tgsi_shader_info
*info
= &tes
->info
;
338 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
339 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
340 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
341 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
342 unsigned type
, partitioning
, topology
, distribution_mode
;
344 switch (tes_prim_mode
) {
345 case PIPE_PRIM_LINES
:
346 type
= V_028B6C_TESS_ISOLINE
;
348 case PIPE_PRIM_TRIANGLES
:
349 type
= V_028B6C_TESS_TRIANGLE
;
351 case PIPE_PRIM_QUADS
:
352 type
= V_028B6C_TESS_QUAD
;
359 switch (tes_spacing
) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
361 partitioning
= V_028B6C_PART_FRAC_ODD
;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
364 partitioning
= V_028B6C_PART_FRAC_EVEN
;
366 case PIPE_TESS_SPACING_EQUAL
:
367 partitioning
= V_028B6C_PART_INTEGER
;
375 topology
= V_028B6C_OUTPUT_POINT
;
376 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
377 topology
= V_028B6C_OUTPUT_LINE
;
378 else if (tes_vertex_order_cw
)
379 /* for some reason, this must be the other way around */
380 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
382 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
384 if (sscreen
->has_distributed_tess
) {
385 if (sscreen
->info
.family
== CHIP_FIJI
||
386 sscreen
->info
.family
>= CHIP_POLARIS10
)
387 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
389 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
391 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
394 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
395 S_028B6C_PARTITIONING(partitioning
) |
396 S_028B6C_TOPOLOGY(topology
) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
403 * Possible VGT configurations and which state should set the register:
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
415 struct si_shader_selector
*sel
,
416 struct si_shader
*shader
,
417 struct si_pm4_state
*pm4
)
419 unsigned type
= sel
->type
;
421 if (sscreen
->info
.family
< CHIP_POLARIS10
||
422 sscreen
->info
.chip_class
>= GFX10
)
425 /* VS as VS, or VS as ES: */
426 if ((type
== PIPE_SHADER_VERTEX
&&
428 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
429 /* TES as VS, or TES as ES: */
430 type
== PIPE_SHADER_TESS_EVAL
) {
431 unsigned vtx_reuse_depth
= 30;
433 if (type
== PIPE_SHADER_TESS_EVAL
&&
434 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
435 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
436 vtx_reuse_depth
= 14;
439 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
443 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
446 si_pm4_clear_state(shader
->pm4
);
448 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
451 shader
->pm4
->shader
= shader
;
454 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
459 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
461 /* Add the pointer to VBO descriptors. */
462 return num_always_on_user_sgprs
+ 1;
465 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
467 struct si_pm4_state
*pm4
;
468 unsigned vgpr_comp_cnt
;
471 assert(sscreen
->info
.chip_class
<= GFX8
);
473 pm4
= si_get_shader_pm4_state(shader
);
477 va
= shader
->bo
->gpu_address
;
478 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
480 /* We need at least 2 components for LS.
481 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
482 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
484 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
486 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
487 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
489 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
490 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
491 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
492 S_00B528_DX10_CLAMP(1) |
493 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
494 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
495 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
498 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
500 struct si_pm4_state
*pm4
;
502 unsigned ls_vgpr_comp_cnt
= 0;
504 pm4
= si_get_shader_pm4_state(shader
);
508 va
= shader
->bo
->gpu_address
;
509 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
511 if (sscreen
->info
.chip_class
>= GFX9
) {
512 if (sscreen
->info
.chip_class
>= GFX10
) {
513 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
514 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
516 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
517 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
520 /* We need at least 2 components for LS.
521 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
522 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
523 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
526 ls_vgpr_comp_cnt
= 1;
527 if (shader
->info
.uses_instanceid
) {
528 if (sscreen
->info
.chip_class
>= GFX10
)
529 ls_vgpr_comp_cnt
= 3;
531 ls_vgpr_comp_cnt
= 2;
534 unsigned num_user_sgprs
=
535 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
537 shader
->config
.rsrc2
=
538 S_00B42C_USER_SGPR(num_user_sgprs
) |
539 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
541 if (sscreen
->info
.chip_class
>= GFX10
)
542 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
544 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
546 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
547 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
549 shader
->config
.rsrc2
=
550 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
551 S_00B42C_OC_LDS_EN(1) |
552 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
555 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
556 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
557 (sscreen
->info
.chip_class
<= GFX9
?
558 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) : 0) |
559 S_00B428_DX10_CLAMP(1) |
560 S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
561 S_00B428_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
562 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
563 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
565 if (sscreen
->info
.chip_class
<= GFX8
) {
566 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
567 shader
->config
.rsrc2
);
571 static void si_emit_shader_es(struct si_context
*sctx
)
573 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
574 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
579 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
580 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
581 shader
->selector
->esgs_itemsize
/ 4);
583 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
584 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
585 SI_TRACKED_VGT_TF_PARAM
,
586 shader
->vgt_tf_param
);
588 if (shader
->vgt_vertex_reuse_block_cntl
)
589 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
590 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
591 shader
->vgt_vertex_reuse_block_cntl
);
593 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
594 sctx
->context_roll
= true;
597 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
599 struct si_pm4_state
*pm4
;
600 unsigned num_user_sgprs
;
601 unsigned vgpr_comp_cnt
;
605 assert(sscreen
->info
.chip_class
<= GFX8
);
607 pm4
= si_get_shader_pm4_state(shader
);
611 pm4
->atom
.emit
= si_emit_shader_es
;
612 va
= shader
->bo
->gpu_address
;
613 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
615 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
616 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
617 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
618 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
619 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
620 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
621 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
623 unreachable("invalid shader selector type");
625 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
627 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
628 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
629 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
630 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
631 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
632 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
633 S_00B328_DX10_CLAMP(1) |
634 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
635 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
636 S_00B32C_USER_SGPR(num_user_sgprs
) |
637 S_00B32C_OC_LDS_EN(oc_lds_en
) |
638 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
640 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
641 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
643 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
646 void gfx9_get_gs_info(struct si_shader_selector
*es
,
647 struct si_shader_selector
*gs
,
648 struct gfx9_gs_info
*out
)
650 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
651 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
652 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
653 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
655 /* All these are in dwords: */
656 /* We can't allow using the whole LDS, because GS waves compete with
657 * other shader stages for LDS space. */
658 const unsigned max_lds_size
= 8 * 1024;
659 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
660 unsigned esgs_lds_size
;
662 /* All these are per subgroup: */
663 const unsigned max_out_prims
= 32 * 1024;
664 const unsigned max_es_verts
= 255;
665 const unsigned ideal_gs_prims
= 64;
666 unsigned max_gs_prims
, gs_prims
;
667 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
669 if (uses_adjacency
|| gs_num_invocations
> 1)
670 max_gs_prims
= 127 / gs_num_invocations
;
674 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
675 * Make sure we don't go over the maximum value.
677 if (gs
->gs_max_out_vertices
> 0) {
678 max_gs_prims
= MIN2(max_gs_prims
,
680 (gs
->gs_max_out_vertices
* gs_num_invocations
));
682 assert(max_gs_prims
> 0);
684 /* If the primitive has adjacency, halve the number of vertices
685 * that will be reused in multiple primitives.
687 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
689 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
690 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
692 /* Compute ESGS LDS size based on the worst case number of ES vertices
693 * needed to create the target number of GS prims per subgroup.
695 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
697 /* If total LDS usage is too big, refactor partitions based on ratio
698 * of ESGS item sizes.
700 if (esgs_lds_size
> max_lds_size
) {
701 /* Our target GS Prims Per Subgroup was too large. Calculate
702 * the maximum number of GS Prims Per Subgroup that will fit
703 * into LDS, capped by the maximum that the hardware can support.
705 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
707 assert(gs_prims
> 0);
708 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
711 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
712 assert(esgs_lds_size
<= max_lds_size
);
715 /* Now calculate remaining ESGS information. */
717 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
719 es_verts
= max_es_verts
;
721 /* Vertices for adjacency primitives are not always reused, so restore
722 * it for ES_VERTS_PER_SUBGRP.
724 min_es_verts
= gs
->gs_input_verts_per_prim
;
726 /* For normal primitives, the VGT only checks if they are past the ES
727 * verts per subgroup after allocating a full GS primitive and if they
728 * are, kick off a new subgroup. But if those additional ES verts are
729 * unique (e.g. not reused) we need to make sure there is enough LDS
730 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
732 es_verts
-= min_es_verts
- 1;
734 out
->es_verts_per_subgroup
= es_verts
;
735 out
->gs_prims_per_subgroup
= gs_prims
;
736 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
737 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
738 gs
->gs_max_out_vertices
;
739 out
->esgs_ring_size
= 4 * esgs_lds_size
;
741 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
744 static void si_emit_shader_gs(struct si_context
*sctx
)
746 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
747 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
752 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
753 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
754 radeon_opt_set_context_reg3(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
755 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
756 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
757 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
758 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
760 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
761 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
762 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
763 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
765 /* R_028B38_VGT_GS_MAX_VERT_OUT */
766 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
767 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
768 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
770 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
771 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
772 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
773 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
774 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
775 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
776 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
777 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
779 /* R_028B90_VGT_GS_INSTANCE_CNT */
780 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
781 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
782 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
784 if (sctx
->chip_class
>= GFX9
) {
785 /* R_028A44_VGT_GS_ONCHIP_CNTL */
786 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
787 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
788 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
789 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
790 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
791 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
792 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
793 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
794 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
795 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
796 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
798 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
799 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
800 SI_TRACKED_VGT_TF_PARAM
,
801 shader
->vgt_tf_param
);
802 if (shader
->vgt_vertex_reuse_block_cntl
)
803 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
804 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
805 shader
->vgt_vertex_reuse_block_cntl
);
808 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
809 sctx
->context_roll
= true;
812 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
814 struct si_shader_selector
*sel
= shader
->selector
;
815 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
816 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
817 struct si_pm4_state
*pm4
;
819 unsigned max_stream
= sel
->max_gs_stream
;
822 pm4
= si_get_shader_pm4_state(shader
);
826 pm4
->atom
.emit
= si_emit_shader_gs
;
828 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
829 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
832 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
833 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
836 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
837 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
840 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
841 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
843 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
844 assert(offset
< (1 << 15));
846 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
848 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
849 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
850 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
851 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
853 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
854 S_028B90_ENABLE(gs_num_invocations
> 0);
856 va
= shader
->bo
->gpu_address
;
857 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
859 if (sscreen
->info
.chip_class
>= GFX9
) {
860 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
861 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
862 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
864 if (es_type
== PIPE_SHADER_VERTEX
)
865 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
866 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
867 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
868 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
870 unreachable("invalid shader selector type");
872 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
873 * VGPR[0:4] are always loaded.
875 if (sel
->info
.uses_invocationid
)
876 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
877 else if (sel
->info
.uses_primid
)
878 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
879 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
880 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
882 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
884 unsigned num_user_sgprs
;
885 if (es_type
== PIPE_SHADER_VERTEX
)
886 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
888 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
890 if (sscreen
->info
.chip_class
>= GFX10
) {
891 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
892 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
894 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
895 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
899 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
900 S_00B228_DX10_CLAMP(1) |
901 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
902 S_00B228_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
903 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
904 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
906 S_00B22C_USER_SGPR(num_user_sgprs
) |
907 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
908 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
909 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
910 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
912 if (sscreen
->info
.chip_class
>= GFX10
) {
913 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
915 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
916 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
919 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
920 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
922 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
923 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
924 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
925 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
926 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
927 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
928 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
929 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
931 if (es_type
== PIPE_SHADER_TESS_EVAL
)
932 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
934 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
937 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
938 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
940 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
941 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
942 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
943 S_00B228_DX10_CLAMP(1) |
944 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
945 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
946 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
947 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
951 /* Common tail code for NGG primitive shaders. */
952 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
,
953 struct si_shader
*shader
,
954 unsigned initial_cdw
)
956 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
957 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
958 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
959 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
960 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
961 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
962 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
963 SI_TRACKED_VGT_PRIMITIVEID_EN
,
964 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
965 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
966 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
967 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
968 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
969 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
970 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
971 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
972 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
973 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
974 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
975 SI_TRACKED_VGT_REUSE_OFF
,
976 shader
->ctx_reg
.ngg
.vgt_reuse_off
);
977 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
978 SI_TRACKED_SPI_VS_OUT_CONFIG
,
979 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
980 radeon_opt_set_context_reg2(sctx
, R_028708_SPI_SHADER_IDX_FORMAT
,
981 SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
982 shader
->ctx_reg
.ngg
.spi_shader_idx_format
,
983 shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
984 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
985 SI_TRACKED_PA_CL_VTE_CNTL
,
986 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
987 radeon_opt_set_context_reg(sctx
, R_028838_PA_CL_NGG_CNTL
,
988 SI_TRACKED_PA_CL_NGG_CNTL
,
989 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
);
991 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
992 sctx
->context_roll
= true;
995 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
997 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
998 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1003 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1006 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
1008 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1009 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1014 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1015 SI_TRACKED_VGT_TF_PARAM
,
1016 shader
->vgt_tf_param
);
1018 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1021 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
1023 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1024 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1029 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1030 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1031 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1033 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1036 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1038 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1039 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1044 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1045 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1046 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1047 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1048 SI_TRACKED_VGT_TF_PARAM
,
1049 shader
->vgt_tf_param
);
1051 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1054 static void si_set_ge_pc_alloc(struct si_screen
*sscreen
,
1055 struct si_pm4_state
*pm4
, bool culling
)
1057 si_pm4_set_reg(pm4
, R_030980_GE_PC_ALLOC
,
1058 S_030980_OVERSUB_EN(1) |
1059 S_030980_NUM_PC_LINES((culling
? 256 : 128) * sscreen
->info
.max_se
- 1));
1062 unsigned si_get_input_prim(const struct si_shader_selector
*gs
,
1063 unsigned default_worst_case
)
1065 if (gs
->type
== PIPE_SHADER_GEOMETRY
)
1066 return gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
1068 if (gs
->type
== PIPE_SHADER_TESS_EVAL
) {
1069 if (gs
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1070 return PIPE_PRIM_POINTS
;
1071 if (gs
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
1072 return PIPE_PRIM_LINES
;
1073 return PIPE_PRIM_TRIANGLES
;
1076 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1077 return default_worst_case
;
1081 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1084 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1086 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1087 const struct tgsi_shader_info
*gs_info
= &gs_sel
->info
;
1088 enum pipe_shader_type gs_type
= shader
->selector
->type
;
1089 const struct si_shader_selector
*es_sel
=
1090 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1091 const struct tgsi_shader_info
*es_info
= &es_sel
->info
;
1092 enum pipe_shader_type es_type
= es_sel
->type
;
1093 unsigned num_user_sgprs
;
1094 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1096 unsigned window_space
=
1097 gs_info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1098 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1099 unsigned gs_num_invocations
= MAX2(gs_sel
->gs_num_invocations
, 1);
1100 /* Anything above TRIANGLES has the same effect as TRIANGLES here. */
1101 unsigned input_prim
= si_get_input_prim(gs_sel
, PIPE_PRIM_TRIANGLES
);
1102 bool break_wave_at_eoi
= false;
1103 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1107 if (es_type
== PIPE_SHADER_TESS_EVAL
) {
1108 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1109 : gfx10_emit_shader_ngg_tess_nogs
;
1111 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1112 : gfx10_emit_shader_ngg_notess_nogs
;
1115 va
= shader
->bo
->gpu_address
;
1116 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1118 if (es_type
== PIPE_SHADER_VERTEX
) {
1119 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1120 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
1122 if (es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1123 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1124 es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1126 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
1129 assert(es_type
== PIPE_SHADER_TESS_EVAL
);
1130 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1131 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1133 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1134 break_wave_at_eoi
= true;
1137 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1138 * VGPR[0:4] are always loaded.
1140 * Vertex shaders always need to load VGPR3, because they need to
1141 * pass edge flags for decomposed primitives (such as quads) to the PA
1142 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1144 if (gs_info
->uses_invocationid
|| gs_type
== PIPE_SHADER_VERTEX
)
1145 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID, edge flags. */
1146 else if (gs_info
->uses_primid
)
1147 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1148 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
1149 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1151 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1153 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1154 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1155 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1156 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1157 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
1158 S_00B228_DX10_CLAMP(1) |
1159 S_00B228_MEM_ORDERED(1) |
1160 S_00B228_WGP_MODE(1) |
1161 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1162 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1163 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1164 S_00B22C_USER_SGPR(num_user_sgprs
) |
1165 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1166 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1167 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
1168 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1169 si_set_ge_pc_alloc(sscreen
, pm4
, false);
1171 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1172 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1173 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
1174 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1176 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1177 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1178 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1179 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1180 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1181 V_02870C_SPI_SHADER_4COMP
:
1182 V_02870C_SPI_SHADER_NONE
) |
1183 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1184 V_02870C_SPI_SHADER_4COMP
:
1185 V_02870C_SPI_SHADER_NONE
) |
1186 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1187 V_02870C_SPI_SHADER_4COMP
:
1188 V_02870C_SPI_SHADER_NONE
);
1190 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1191 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1192 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
);
1194 if (gs_type
== PIPE_SHADER_GEOMETRY
) {
1195 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1196 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->gs_max_out_vertices
;
1198 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1201 if (es_type
== PIPE_SHADER_TESS_EVAL
)
1202 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1204 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1205 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1206 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1207 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1208 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1209 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1210 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
=
1211 S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1212 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1213 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1214 S_028B90_CNT(gs_num_invocations
) |
1215 S_028B90_ENABLE(gs_num_invocations
> 1) |
1216 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1217 shader
->ngg
.max_vert_out_per_gs_instance
);
1219 /* Always output hw-generated edge flags and pass them via the prim
1220 * export to prevent drawing lines on internal edges of decomposed
1221 * primitives (such as quads) with polygon mode = lines. Only VS needs
1224 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
=
1225 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type
== PIPE_SHADER_VERTEX
);
1228 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1229 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
) |
1230 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1233 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1234 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1236 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1237 S_028818_VTX_W0_FMT(1) |
1238 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1239 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1240 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1243 shader
->ctx_reg
.ngg
.vgt_reuse_off
=
1244 S_028AB4_REUSE_OFF(sscreen
->info
.family
== CHIP_NAVI10
&&
1245 sscreen
->info
.chip_external_rev
== 0x1 &&
1246 es_type
== PIPE_SHADER_TESS_EVAL
);
1249 static void si_emit_shader_vs(struct si_context
*sctx
)
1251 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1252 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1257 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
1258 SI_TRACKED_VGT_GS_MODE
,
1259 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1260 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1261 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1262 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1264 if (sctx
->chip_class
<= GFX8
) {
1265 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
1266 SI_TRACKED_VGT_REUSE_OFF
,
1267 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1270 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1271 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1272 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1274 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1275 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1276 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1278 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1279 SI_TRACKED_PA_CL_VTE_CNTL
,
1280 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1282 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1283 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1284 SI_TRACKED_VGT_TF_PARAM
,
1285 shader
->vgt_tf_param
);
1287 if (shader
->vgt_vertex_reuse_block_cntl
)
1288 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1289 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1290 shader
->vgt_vertex_reuse_block_cntl
);
1292 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1293 sctx
->context_roll
= true;
1297 * Compute the state for \p shader, which will run as a vertex shader on the
1300 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1301 * is the copy shader.
1303 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1304 struct si_shader_selector
*gs
)
1306 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1307 struct si_pm4_state
*pm4
;
1308 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1310 unsigned nparams
, oc_lds_en
;
1311 unsigned window_space
=
1312 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1313 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1315 pm4
= si_get_shader_pm4_state(shader
);
1319 pm4
->atom
.emit
= si_emit_shader_vs
;
1321 /* We always write VGT_GS_MODE in the VS state, because every switch
1322 * between different shader pipelines involving a different GS or no
1323 * GS at all involves a switch of the VS (different GS use different
1324 * copy shaders). On the other hand, when the API switches from a GS to
1325 * no GS and then back to the same GS used originally, the GS state is
1329 unsigned mode
= V_028A40_GS_OFF
;
1331 /* PrimID needs GS scenario A. */
1333 mode
= V_028A40_GS_SCENARIO_A
;
1335 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1336 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1338 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1339 sscreen
->info
.chip_class
);
1340 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1343 if (sscreen
->info
.chip_class
<= GFX8
) {
1344 /* Reuse needs to be set off if we write oViewport. */
1345 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1346 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1349 va
= shader
->bo
->gpu_address
;
1350 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1353 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1354 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1355 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1356 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1357 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1358 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1360 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
1362 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1363 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1364 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1366 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1368 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1369 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1370 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1372 unreachable("invalid shader selector type");
1374 /* VS is required to export at least one param. */
1375 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1376 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1378 if (sscreen
->info
.chip_class
>= GFX10
) {
1379 shader
->ctx_reg
.vs
.spi_vs_out_config
|=
1380 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1383 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1384 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1385 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1386 V_02870C_SPI_SHADER_4COMP
:
1387 V_02870C_SPI_SHADER_NONE
) |
1388 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1389 V_02870C_SPI_SHADER_4COMP
:
1390 V_02870C_SPI_SHADER_NONE
) |
1391 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1392 V_02870C_SPI_SHADER_4COMP
:
1393 V_02870C_SPI_SHADER_NONE
);
1395 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1397 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1398 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1399 if (sscreen
->info
.chip_class
>= GFX10
)
1400 si_set_ge_pc_alloc(sscreen
, pm4
, false);
1402 uint32_t rsrc1
= S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1403 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1404 S_00B128_DX10_CLAMP(1) |
1405 S_00B128_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1406 S_00B128_FLOAT_MODE(shader
->config
.float_mode
);
1407 uint32_t rsrc2
= S_00B12C_USER_SGPR(num_user_sgprs
) |
1408 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1409 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
1411 if (sscreen
->info
.chip_class
<= GFX9
) {
1412 rsrc1
|= S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1413 rsrc2
|= S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1414 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1415 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1416 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1417 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
);
1420 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
, rsrc1
);
1421 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
, rsrc2
);
1424 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1425 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1427 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1428 S_028818_VTX_W0_FMT(1) |
1429 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1430 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1431 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1433 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1434 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1436 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1439 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1441 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1442 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1443 !!(info
->colors_read
& 0xf0);
1444 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1445 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1447 assert(num_interp
<= 32);
1448 return MIN2(num_interp
, 32);
1451 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1453 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1454 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1456 /* If the i-th target format is set, all previous target formats must
1457 * be non-zero to avoid hangs.
1459 for (i
= 0; i
< num_targets
; i
++)
1460 if (!(value
& (0xf << (i
* 4))))
1461 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1466 static void si_emit_shader_ps(struct si_context
*sctx
)
1468 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1469 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1474 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1475 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1476 SI_TRACKED_SPI_PS_INPUT_ENA
,
1477 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1478 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1480 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1481 SI_TRACKED_SPI_BARYC_CNTL
,
1482 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1483 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1484 SI_TRACKED_SPI_PS_IN_CONTROL
,
1485 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1487 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1488 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1489 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1490 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1491 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1493 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1494 SI_TRACKED_CB_SHADER_MASK
,
1495 shader
->ctx_reg
.ps
.cb_shader_mask
);
1497 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1498 sctx
->context_roll
= true;
1501 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1503 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1504 struct si_pm4_state
*pm4
;
1505 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1506 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1508 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1510 /* we need to enable at least one of them, otherwise we hang the GPU */
1511 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1512 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1513 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1514 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1515 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1516 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1517 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1518 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1519 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1520 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1521 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1522 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1523 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1524 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1526 /* Validate interpolation optimization flags (read as implications). */
1527 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1528 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1529 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1530 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1531 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1532 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1533 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1534 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1535 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1536 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1537 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1538 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1539 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1540 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1541 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1542 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1543 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1544 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1546 /* Validate cases when the optimizations are off (read as implications). */
1547 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1548 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1549 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1550 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1551 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1552 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1554 pm4
= si_get_shader_pm4_state(shader
);
1558 pm4
->atom
.emit
= si_emit_shader_ps
;
1560 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1562 * 0 -> Position = pixel center
1563 * 1 -> Position = pixel centroid
1564 * 2 -> Position = at sample position
1566 * From GLSL 4.5 specification, section 7.1:
1567 * "The variable gl_FragCoord is available as an input variable from
1568 * within fragment shaders and it holds the window relative coordinates
1569 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1570 * value can be for any location within the pixel, or one of the
1571 * fragment samples. The use of centroid does not further restrict
1572 * this value to be inside the current primitive."
1574 * Meaning that centroid has no effect and we can return anything within
1575 * the pixel. Thus, return the value at sample position, because that's
1576 * the most accurate one shaders can get.
1578 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1580 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1581 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1582 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1584 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1585 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1587 /* Ensure that some export memory is always allocated, for two reasons:
1589 * 1) Correctness: The hardware ignores the EXEC mask if no export
1590 * memory is allocated, so KILL and alpha test do not work correctly
1592 * 2) Performance: Every shader needs at least a NULL export, even when
1593 * it writes no color/depth output. The NULL export instruction
1594 * stalls without this setting.
1596 * Don't add this to CB_SHADER_MASK.
1598 * GFX10 supports pixel shaders without exports by setting both
1599 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1600 * instructions if any are present.
1602 if ((sscreen
->info
.chip_class
<= GFX9
||
1604 shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
) &&
1605 !spi_shader_col_format
&&
1606 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1607 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1609 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1610 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1612 /* Set interpolation controls. */
1613 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
));
1615 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1616 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1617 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1618 ac_get_spi_shader_z_format(info
->writes_z
,
1619 info
->writes_stencil
,
1620 info
->writes_samplemask
);
1621 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1622 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1624 va
= shader
->bo
->gpu_address
;
1625 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1626 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1627 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1630 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
1631 S_00B028_DX10_CLAMP(1) |
1632 S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1633 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1635 if (sscreen
->info
.chip_class
< GFX10
) {
1636 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1639 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1640 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1641 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1642 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1643 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1646 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1647 struct si_shader
*shader
)
1649 switch (shader
->selector
->type
) {
1650 case PIPE_SHADER_VERTEX
:
1651 if (shader
->key
.as_ls
)
1652 si_shader_ls(sscreen
, shader
);
1653 else if (shader
->key
.as_es
)
1654 si_shader_es(sscreen
, shader
);
1655 else if (shader
->key
.as_ngg
)
1656 gfx10_shader_ngg(sscreen
, shader
);
1658 si_shader_vs(sscreen
, shader
, NULL
);
1660 case PIPE_SHADER_TESS_CTRL
:
1661 si_shader_hs(sscreen
, shader
);
1663 case PIPE_SHADER_TESS_EVAL
:
1664 if (shader
->key
.as_es
)
1665 si_shader_es(sscreen
, shader
);
1666 else if (shader
->key
.as_ngg
)
1667 gfx10_shader_ngg(sscreen
, shader
);
1669 si_shader_vs(sscreen
, shader
, NULL
);
1671 case PIPE_SHADER_GEOMETRY
:
1672 if (shader
->key
.as_ngg
)
1673 gfx10_shader_ngg(sscreen
, shader
);
1675 si_shader_gs(sscreen
, shader
);
1677 case PIPE_SHADER_FRAGMENT
:
1678 si_shader_ps(sscreen
, shader
);
1685 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1687 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1688 if (sctx
->queued
.named
.dsa
)
1689 return sctx
->queued
.named
.dsa
->alpha_func
;
1691 return PIPE_FUNC_ALWAYS
;
1694 void si_shader_selector_key_vs(struct si_context
*sctx
,
1695 struct si_shader_selector
*vs
,
1696 struct si_shader_key
*key
,
1697 struct si_vs_prolog_bits
*prolog_key
)
1699 if (!sctx
->vertex_elements
||
1700 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
])
1703 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1705 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1706 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1707 prolog_key
->unpack_instance_id_from_vertex_id
=
1708 sctx
->prim_discard_cs_instancing
;
1710 /* Prefer a monolithic shader to allow scheduling divisions around
1712 if (prolog_key
->instance_divisor_is_fetched
)
1713 key
->opt
.prefer_mono
= 1;
1715 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1716 unsigned count_mask
= (1 << count
) - 1;
1717 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1718 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1720 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1721 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1723 unsigned i
= u_bit_scan(&mask
);
1724 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1725 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1726 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1727 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1728 if (vb
->buffer_offset
& align_mask
||
1729 vb
->stride
& align_mask
) {
1737 unsigned i
= u_bit_scan(&fix
);
1738 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1740 key
->mono
.vs_fetch_opencode
= opencode
;
1743 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1744 struct si_shader_selector
*vs
,
1745 struct si_shader_key
*key
)
1747 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1749 key
->opt
.clip_disable
=
1750 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1751 (vs
->info
.clipdist_writemask
||
1752 vs
->info
.writes_clipvertex
) &&
1753 !vs
->info
.culldist_writemask
;
1755 /* Find out if PS is disabled. */
1756 bool ps_disabled
= true;
1758 const struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1759 bool alpha_to_coverage
= blend
&& blend
->alpha_to_coverage
;
1760 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1761 ps
->info
.writes_z
||
1762 ps
->info
.writes_stencil
||
1763 ps
->info
.writes_samplemask
||
1764 alpha_to_coverage
||
1765 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1766 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1768 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1771 !ps
->info
.writes_memory
);
1774 /* Find out which VS outputs aren't used by the PS. */
1775 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1776 uint64_t inputs_read
= 0;
1778 /* Ignore outputs that are not passed from VS to PS. */
1779 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1780 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1781 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1784 inputs_read
= ps
->inputs_read
;
1787 uint64_t linked
= outputs_written
& inputs_read
;
1789 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1792 /* Compute the key for the hw shader variant */
1793 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1794 struct si_shader_selector
*sel
,
1795 union si_vgt_stages_key stages_key
,
1796 struct si_shader_key
*key
)
1798 struct si_context
*sctx
= (struct si_context
*)ctx
;
1800 memset(key
, 0, sizeof(*key
));
1802 switch (sel
->type
) {
1803 case PIPE_SHADER_VERTEX
:
1804 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1806 if (sctx
->tes_shader
.cso
)
1808 else if (sctx
->gs_shader
.cso
)
1811 key
->as_ngg
= stages_key
.u
.ngg
;
1812 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1814 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1815 key
->mono
.u
.vs_export_prim_id
= 1;
1818 case PIPE_SHADER_TESS_CTRL
:
1819 if (sctx
->chip_class
>= GFX9
) {
1820 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1821 key
, &key
->part
.tcs
.ls_prolog
);
1822 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1824 /* When the LS VGPR fix is needed, monolithic shaders
1826 * - avoid initializing EXEC in both the LS prolog
1827 * and the LS main part when !vs_needs_prolog
1828 * - remove the fixup for unused input VGPRs
1830 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1832 /* The LS output / HS input layout can be communicated
1833 * directly instead of via user SGPRs for merged LS-HS.
1834 * The LS VGPR fix prefers this too.
1836 key
->opt
.prefer_mono
= 1;
1839 key
->part
.tcs
.epilog
.prim_mode
=
1840 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1841 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1842 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1843 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1844 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1846 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1847 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1849 case PIPE_SHADER_TESS_EVAL
:
1850 if (sctx
->gs_shader
.cso
)
1853 key
->as_ngg
= stages_key
.u
.ngg
;
1854 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1856 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1857 key
->mono
.u
.vs_export_prim_id
= 1;
1860 case PIPE_SHADER_GEOMETRY
:
1861 if (sctx
->chip_class
>= GFX9
) {
1862 if (sctx
->tes_shader
.cso
) {
1863 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1865 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1866 key
, &key
->part
.gs
.vs_prolog
);
1867 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1868 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1871 key
->as_ngg
= stages_key
.u
.ngg
;
1873 /* Merged ES-GS can have unbalanced wave usage.
1875 * ES threads are per-vertex, while GS threads are
1876 * per-primitive. So without any amplification, there
1877 * are fewer GS threads than ES threads, which can result
1878 * in empty (no-op) GS waves. With too much amplification,
1879 * there are more GS threads than ES threads, which
1880 * can result in empty (no-op) ES waves.
1882 * Non-monolithic shaders are implemented by setting EXEC
1883 * at the beginning of shader parts, and don't jump to
1884 * the end if EXEC is 0.
1886 * Monolithic shaders use conditional blocks, so they can
1887 * jump and skip empty waves of ES or GS. So set this to
1888 * always use optimized variants, which are monolithic.
1890 key
->opt
.prefer_mono
= 1;
1892 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1894 case PIPE_SHADER_FRAGMENT
: {
1895 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1896 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1898 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1899 sel
->info
.colors_written
== 0x1)
1900 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1903 /* Select the shader color format based on whether
1904 * blending or alpha are needed.
1906 key
->part
.ps
.epilog
.spi_shader_col_format
=
1907 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1908 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1909 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1910 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1911 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1912 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1913 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1914 sctx
->framebuffer
.spi_shader_col_format
);
1915 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1917 /* The output for dual source blending should have
1918 * the same format as the first output.
1920 if (blend
->dual_src_blend
)
1921 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1922 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1924 key
->part
.ps
.epilog
.spi_shader_col_format
= sctx
->framebuffer
.spi_shader_col_format
;
1926 /* If alpha-to-coverage is enabled, we have to export alpha
1927 * even if there is no color buffer.
1929 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1930 blend
&& blend
->alpha_to_coverage
)
1931 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1933 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1934 * to the range supported by the type if a channel has less
1935 * than 16 bits and the export format is 16_ABGR.
1937 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1938 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1939 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1942 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1943 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1944 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1945 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1946 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1949 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1950 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1952 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1953 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1955 if (sctx
->queued
.named
.blend
) {
1956 key
->part
.ps
.epilog
.alpha_to_one
= sctx
->queued
.named
.blend
->alpha_to_one
&&
1957 rs
->multisample_enable
;
1960 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1961 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1962 (is_line
&& rs
->line_smooth
)) &&
1963 sctx
->framebuffer
.nr_samples
<= 1;
1964 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1966 if (sctx
->ps_iter_samples
> 1 &&
1967 sel
->info
.reads_samplemask
) {
1968 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1969 util_logbase2(sctx
->ps_iter_samples
);
1972 if (rs
->force_persample_interp
&&
1973 rs
->multisample_enable
&&
1974 sctx
->framebuffer
.nr_samples
> 1 &&
1975 sctx
->ps_iter_samples
> 1) {
1976 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1977 sel
->info
.uses_persp_center
||
1978 sel
->info
.uses_persp_centroid
;
1980 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1981 sel
->info
.uses_linear_center
||
1982 sel
->info
.uses_linear_centroid
;
1983 } else if (rs
->multisample_enable
&&
1984 sctx
->framebuffer
.nr_samples
> 1) {
1985 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1986 sel
->info
.uses_persp_center
&&
1987 sel
->info
.uses_persp_centroid
;
1988 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1989 sel
->info
.uses_linear_center
&&
1990 sel
->info
.uses_linear_centroid
;
1992 /* Make sure SPI doesn't compute more than 1 pair
1993 * of (i,j), which is the optimization here. */
1994 key
->part
.ps
.prolog
.force_persp_center_interp
=
1995 sel
->info
.uses_persp_center
+
1996 sel
->info
.uses_persp_centroid
+
1997 sel
->info
.uses_persp_sample
> 1;
1999 key
->part
.ps
.prolog
.force_linear_center_interp
=
2000 sel
->info
.uses_linear_center
+
2001 sel
->info
.uses_linear_centroid
+
2002 sel
->info
.uses_linear_sample
> 1;
2004 if (sel
->info
.opcode_count
[TGSI_OPCODE_INTERP_SAMPLE
])
2005 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
2008 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
2010 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2011 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
2012 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
2013 struct pipe_resource
*tex
= cb0
->texture
;
2015 /* 1D textures are allocated and used as 2D on GFX9. */
2016 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
2017 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
2018 (tex
->target
== PIPE_TEXTURE_1D
||
2019 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
2020 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
2021 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
2022 tex
->target
== PIPE_TEXTURE_CUBE
||
2023 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2024 tex
->target
== PIPE_TEXTURE_3D
;
2032 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
2033 memset(&key
->opt
, 0, sizeof(key
->opt
));
2036 static void si_build_shader_variant(struct si_shader
*shader
,
2040 struct si_shader_selector
*sel
= shader
->selector
;
2041 struct si_screen
*sscreen
= sel
->screen
;
2042 struct ac_llvm_compiler
*compiler
;
2043 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
2045 if (thread_index
>= 0) {
2047 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
2048 compiler
= &sscreen
->compiler_lowp
[thread_index
];
2050 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2051 compiler
= &sscreen
->compiler
[thread_index
];
2056 assert(!low_priority
);
2057 compiler
= shader
->compiler_ctx_state
.compiler
;
2060 if (unlikely(!si_shader_create(sscreen
, compiler
, shader
, debug
))) {
2061 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2063 shader
->compilation_failed
= true;
2067 if (shader
->compiler_ctx_state
.is_debug_context
) {
2068 FILE *f
= open_memstream(&shader
->shader_log
,
2069 &shader
->shader_log_size
);
2071 si_shader_dump(sscreen
, shader
, NULL
, f
, false);
2076 si_shader_init_pm4_state(sscreen
, shader
);
2079 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2081 struct si_shader
*shader
= (struct si_shader
*)job
;
2083 assert(thread_index
>= 0);
2085 si_build_shader_variant(shader
, thread_index
, true);
2088 static const struct si_shader_key zeroed
;
2090 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
2091 struct si_shader_selector
*sel
,
2092 struct si_compiler_ctx_state
*compiler_state
,
2093 struct si_shader_key
*key
)
2095 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2098 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2103 /* We can leave the fence as permanently signaled because the
2104 * main part becomes visible globally only after it has been
2106 util_queue_fence_init(&main_part
->ready
);
2108 main_part
->selector
= sel
;
2109 main_part
->key
.as_es
= key
->as_es
;
2110 main_part
->key
.as_ls
= key
->as_ls
;
2111 main_part
->key
.as_ngg
= key
->as_ngg
;
2112 main_part
->is_monolithic
= false;
2114 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
2115 main_part
, &compiler_state
->debug
) != 0) {
2125 * Select a shader variant according to the shader key.
2127 * \param optimized_or_none If the key describes an optimized shader variant and
2128 * the compilation isn't finished, don't select any
2129 * shader and return an error.
2131 int si_shader_select_with_key(struct si_screen
*sscreen
,
2132 struct si_shader_ctx_state
*state
,
2133 struct si_compiler_ctx_state
*compiler_state
,
2134 struct si_shader_key
*key
,
2136 bool optimized_or_none
)
2138 struct si_shader_selector
*sel
= state
->cso
;
2139 struct si_shader_selector
*previous_stage_sel
= NULL
;
2140 struct si_shader
*current
= state
->current
;
2141 struct si_shader
*iter
, *shader
= NULL
;
2144 /* Check if we don't need to change anything.
2145 * This path is also used for most shaders that don't need multiple
2146 * variants, it will cost just a computation of the key and this
2148 if (likely(current
&&
2149 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2150 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2151 if (current
->is_optimized
) {
2152 if (optimized_or_none
)
2155 memset(&key
->opt
, 0, sizeof(key
->opt
));
2156 goto current_not_ready
;
2159 util_queue_fence_wait(¤t
->ready
);
2162 return current
->compilation_failed
? -1 : 0;
2166 /* This must be done before the mutex is locked, because async GS
2167 * compilation calls this function too, and therefore must enter
2170 * Only wait if we are in a draw call. Don't wait if we are
2171 * in a compiler thread.
2173 if (thread_index
< 0)
2174 util_queue_fence_wait(&sel
->ready
);
2176 mtx_lock(&sel
->mutex
);
2178 /* Find the shader variant. */
2179 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2180 /* Don't check the "current" shader. We checked it above. */
2181 if (current
!= iter
&&
2182 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2183 mtx_unlock(&sel
->mutex
);
2185 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2186 /* If it's an optimized shader and its compilation has
2187 * been started but isn't done, use the unoptimized
2188 * shader so as not to cause a stall due to compilation.
2190 if (iter
->is_optimized
) {
2191 if (optimized_or_none
)
2193 memset(&key
->opt
, 0, sizeof(key
->opt
));
2197 util_queue_fence_wait(&iter
->ready
);
2200 if (iter
->compilation_failed
) {
2201 return -1; /* skip the draw call */
2204 state
->current
= iter
;
2209 /* Build a new shader. */
2210 shader
= CALLOC_STRUCT(si_shader
);
2212 mtx_unlock(&sel
->mutex
);
2216 util_queue_fence_init(&shader
->ready
);
2218 shader
->selector
= sel
;
2220 shader
->compiler_ctx_state
= *compiler_state
;
2222 /* If this is a merged shader, get the first shader's selector. */
2223 if (sscreen
->info
.chip_class
>= GFX9
) {
2224 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2225 previous_stage_sel
= key
->part
.tcs
.ls
;
2226 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2227 previous_stage_sel
= key
->part
.gs
.es
;
2229 /* We need to wait for the previous shader. */
2230 if (previous_stage_sel
&& thread_index
< 0)
2231 util_queue_fence_wait(&previous_stage_sel
->ready
);
2234 bool is_pure_monolithic
=
2235 sscreen
->use_monolithic_shaders
||
2236 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2238 /* Compile the main shader part if it doesn't exist. This can happen
2239 * if the initial guess was wrong.
2241 * The prim discard CS doesn't need the main shader part.
2243 if (!is_pure_monolithic
&&
2244 !key
->opt
.vs_as_prim_discard_cs
) {
2247 /* Make sure the main shader part is present. This is needed
2248 * for shaders that can be compiled as VS, LS, or ES, and only
2249 * one of them is compiled at creation.
2251 * It is also needed for GS, which can be compiled as non-NGG
2254 * For merged shaders, check that the starting shader's main
2257 if (previous_stage_sel
) {
2258 struct si_shader_key shader1_key
= zeroed
;
2260 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2261 shader1_key
.as_ls
= 1;
2262 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2263 shader1_key
.as_es
= 1;
2267 mtx_lock(&previous_stage_sel
->mutex
);
2268 ok
= si_check_missing_main_part(sscreen
,
2270 compiler_state
, &shader1_key
);
2271 mtx_unlock(&previous_stage_sel
->mutex
);
2275 ok
= si_check_missing_main_part(sscreen
, sel
,
2276 compiler_state
, key
);
2281 mtx_unlock(&sel
->mutex
);
2282 return -ENOMEM
; /* skip the draw call */
2286 /* Keep the reference to the 1st shader of merged shaders, so that
2287 * Gallium can't destroy it before we destroy the 2nd shader.
2289 * Set sctx = NULL, because it's unused if we're not releasing
2290 * the shader, and we don't have any sctx here.
2292 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
2293 previous_stage_sel
);
2295 /* Monolithic-only shaders don't make a distinction between optimized
2296 * and unoptimized. */
2297 shader
->is_monolithic
=
2298 is_pure_monolithic
||
2299 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2301 /* The prim discard CS is always optimized. */
2302 shader
->is_optimized
=
2303 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2304 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2306 /* If it's an optimized shader, compile it asynchronously. */
2307 if (shader
->is_optimized
&& thread_index
< 0) {
2308 /* Compile it asynchronously. */
2309 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
2310 shader
, &shader
->ready
,
2311 si_build_shader_variant_low_priority
, NULL
);
2313 /* Add only after the ready fence was reset, to guard against a
2314 * race with si_bind_XX_shader. */
2315 if (!sel
->last_variant
) {
2316 sel
->first_variant
= shader
;
2317 sel
->last_variant
= shader
;
2319 sel
->last_variant
->next_variant
= shader
;
2320 sel
->last_variant
= shader
;
2323 /* Use the default (unoptimized) shader for now. */
2324 memset(&key
->opt
, 0, sizeof(key
->opt
));
2325 mtx_unlock(&sel
->mutex
);
2327 if (sscreen
->options
.sync_compile
)
2328 util_queue_fence_wait(&shader
->ready
);
2330 if (optimized_or_none
)
2335 /* Reset the fence before adding to the variant list. */
2336 util_queue_fence_reset(&shader
->ready
);
2338 if (!sel
->last_variant
) {
2339 sel
->first_variant
= shader
;
2340 sel
->last_variant
= shader
;
2342 sel
->last_variant
->next_variant
= shader
;
2343 sel
->last_variant
= shader
;
2346 mtx_unlock(&sel
->mutex
);
2348 assert(!shader
->is_optimized
);
2349 si_build_shader_variant(shader
, thread_index
, false);
2351 util_queue_fence_signal(&shader
->ready
);
2353 if (!shader
->compilation_failed
)
2354 state
->current
= shader
;
2356 return shader
->compilation_failed
? -1 : 0;
2359 static int si_shader_select(struct pipe_context
*ctx
,
2360 struct si_shader_ctx_state
*state
,
2361 union si_vgt_stages_key stages_key
,
2362 struct si_compiler_ctx_state
*compiler_state
)
2364 struct si_context
*sctx
= (struct si_context
*)ctx
;
2365 struct si_shader_key key
;
2367 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2368 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2372 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
2374 struct si_shader_key
*key
)
2376 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2378 switch (info
->processor
) {
2379 case PIPE_SHADER_VERTEX
:
2380 switch (next_shader
) {
2381 case PIPE_SHADER_GEOMETRY
:
2384 case PIPE_SHADER_TESS_CTRL
:
2385 case PIPE_SHADER_TESS_EVAL
:
2389 /* If POSITION isn't written, it can only be a HW VS
2390 * if streamout is used. If streamout isn't used,
2391 * assume that it's a HW LS. (the next shader is TCS)
2392 * This heuristic is needed for separate shader objects.
2394 if (!info
->writes_position
&& !streamout
)
2399 case PIPE_SHADER_TESS_EVAL
:
2400 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2401 !info
->writes_position
)
2408 * Compile the main shader part or the monolithic shader as part of
2409 * si_shader_selector initialization. Since it can be done asynchronously,
2410 * there is no way to report compile failures to applications.
2412 static void si_init_shader_selector_async(void *job
, int thread_index
)
2414 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2415 struct si_screen
*sscreen
= sel
->screen
;
2416 struct ac_llvm_compiler
*compiler
;
2417 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2419 assert(!debug
->debug_message
|| debug
->async
);
2420 assert(thread_index
>= 0);
2421 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2422 compiler
= &sscreen
->compiler
[thread_index
];
2427 /* Compile the main shader part for use with a prolog and/or epilog.
2428 * If this fails, the driver will try to compile a monolithic shader
2431 if (!sscreen
->use_monolithic_shaders
) {
2432 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2433 void *ir_binary
= NULL
;
2436 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2440 /* We can leave the fence signaled because use of the default
2441 * main part is guarded by the selector's ready fence. */
2442 util_queue_fence_init(&shader
->ready
);
2444 shader
->selector
= sel
;
2445 shader
->is_monolithic
= false;
2446 si_parse_next_shader_property(&sel
->info
,
2447 sel
->so
.num_outputs
!= 0,
2449 if (sscreen
->info
.chip_class
>= GFX10
&&
2450 !sscreen
->options
.disable_ngg
&&
2451 (((sel
->type
== PIPE_SHADER_VERTEX
||
2452 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2453 !shader
->key
.as_ls
&& !shader
->key
.as_es
) ||
2454 sel
->type
== PIPE_SHADER_GEOMETRY
))
2455 shader
->key
.as_ngg
= 1;
2457 if (sel
->tokens
|| sel
->nir
)
2458 ir_binary
= si_get_ir_binary(sel
);
2460 /* Try to load the shader from the shader cache. */
2461 mtx_lock(&sscreen
->shader_cache_mutex
);
2464 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
2465 mtx_unlock(&sscreen
->shader_cache_mutex
);
2466 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2468 mtx_unlock(&sscreen
->shader_cache_mutex
);
2470 /* Compile the shader if it hasn't been loaded from the cache. */
2471 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
2475 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2480 mtx_lock(&sscreen
->shader_cache_mutex
);
2481 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
2483 mtx_unlock(&sscreen
->shader_cache_mutex
);
2487 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2489 /* Unset "outputs_written" flags for outputs converted to
2490 * DEFAULT_VAL, so that later inter-shader optimizations don't
2491 * try to eliminate outputs that don't exist in the final
2494 * This is only done if non-monolithic shaders are enabled.
2496 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2497 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2498 !shader
->key
.as_ls
&&
2499 !shader
->key
.as_es
) {
2502 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2503 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2505 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2508 unsigned name
= sel
->info
.output_semantic_name
[i
];
2509 unsigned index
= sel
->info
.output_semantic_index
[i
];
2513 case TGSI_SEMANTIC_GENERIC
:
2514 /* don't process indices the function can't handle */
2515 if (index
>= SI_MAX_IO_GENERIC
)
2519 id
= si_shader_io_get_unique_index(name
, index
, true);
2520 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2522 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2523 case TGSI_SEMANTIC_PSIZE
:
2524 case TGSI_SEMANTIC_CLIPVERTEX
:
2525 case TGSI_SEMANTIC_EDGEFLAG
:
2532 /* The GS copy shader is always pre-compiled. */
2533 if (sel
->type
== PIPE_SHADER_GEOMETRY
&&
2534 (sscreen
->info
.chip_class
<= GFX9
|| sel
->tess_turns_off_ngg
)) {
2535 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2536 if (!sel
->gs_copy_shader
) {
2537 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2541 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2545 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2546 struct util_queue_fence
*ready_fence
,
2547 struct si_compiler_ctx_state
*compiler_ctx_state
,
2548 void *job
, util_queue_execute_func execute
)
2550 util_queue_fence_init(ready_fence
);
2552 struct util_async_debug_callback async_debug
;
2554 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2556 si_can_dump_shader(sctx
->screen
, processor
);
2559 u_async_debug_init(&async_debug
);
2560 compiler_ctx_state
->debug
= async_debug
.base
;
2563 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2564 ready_fence
, execute
, NULL
);
2567 util_queue_fence_wait(ready_fence
);
2568 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2569 u_async_debug_cleanup(&async_debug
);
2572 if (sctx
->screen
->options
.sync_compile
)
2573 util_queue_fence_wait(ready_fence
);
2576 /* Return descriptor slot usage masks from the given shader info. */
2577 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2578 uint32_t *const_and_shader_buffers
,
2579 uint64_t *samplers_and_images
)
2581 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2583 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2584 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2585 /* two 8-byte images share one 16-byte slot */
2586 num_images
= align(util_last_bit(info
->images_declared
), 2);
2587 num_samplers
= util_last_bit(info
->samplers_declared
);
2589 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2590 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2591 *const_and_shader_buffers
=
2592 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2594 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2595 start
= si_get_image_slot(num_images
- 1) / 2;
2596 *samplers_and_images
=
2597 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2600 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2601 const struct pipe_shader_state
*state
)
2603 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2604 struct si_context
*sctx
= (struct si_context
*)ctx
;
2605 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2611 pipe_reference_init(&sel
->reference
, 1);
2612 sel
->screen
= sscreen
;
2613 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2614 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2616 sel
->so
= state
->stream_output
;
2618 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2619 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2625 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2626 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2628 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2630 sel
->nir
= state
->ir
.nir
;
2632 si_nir_opts(sel
->nir
);
2633 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2634 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->tcs_info
);
2637 sel
->type
= sel
->info
.processor
;
2638 p_atomic_inc(&sscreen
->num_shaders_created
);
2639 si_get_active_slot_masks(&sel
->info
,
2640 &sel
->active_const_and_shader_buffers
,
2641 &sel
->active_samplers_and_images
);
2643 /* Record which streamout buffers are enabled. */
2644 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2645 sel
->enabled_streamout_buffer_mask
|=
2646 (1 << sel
->so
.output
[i
].output_buffer
) <<
2647 (sel
->so
.output
[i
].stream
* 4);
2650 /* The prolog is a no-op if there are no inputs. */
2651 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2652 sel
->info
.num_inputs
&&
2653 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2655 sel
->force_correct_derivs_after_kill
=
2656 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2657 sel
->info
.uses_derivatives
&&
2658 sel
->info
.uses_kill
&&
2659 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2661 sel
->prim_discard_cs_allowed
=
2662 sel
->type
== PIPE_SHADER_VERTEX
&&
2663 !sel
->info
.uses_bindless_images
&&
2664 !sel
->info
.uses_bindless_samplers
&&
2665 !sel
->info
.writes_memory
&&
2666 !sel
->info
.writes_viewport_index
&&
2667 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2668 !sel
->so
.num_outputs
;
2670 if (sel
->type
== PIPE_SHADER_VERTEX
&&
2671 sel
->info
.writes_edgeflag
) {
2672 if (sscreen
->info
.chip_class
>= GFX10
)
2673 sel
->ngg_writes_edgeflag
= true;
2675 sel
->pos_writes_edgeflag
= true;
2678 /* Set which opcode uses which (i,j) pair. */
2679 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2680 sel
->info
.uses_persp_centroid
= true;
2682 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2683 sel
->info
.uses_linear_centroid
= true;
2685 if (sel
->info
.uses_persp_opcode_interp_offset
||
2686 sel
->info
.uses_persp_opcode_interp_sample
)
2687 sel
->info
.uses_persp_center
= true;
2689 if (sel
->info
.uses_linear_opcode_interp_offset
||
2690 sel
->info
.uses_linear_opcode_interp_sample
)
2691 sel
->info
.uses_linear_center
= true;
2693 switch (sel
->type
) {
2694 case PIPE_SHADER_GEOMETRY
:
2695 sel
->gs_output_prim
=
2696 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2698 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2699 sel
->rast_prim
= sel
->gs_output_prim
;
2700 if (util_rast_prim_is_triangles(sel
->rast_prim
))
2701 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2703 sel
->gs_max_out_vertices
=
2704 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2705 sel
->gs_num_invocations
=
2706 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2707 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2708 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2709 sel
->gs_max_out_vertices
;
2711 sel
->max_gs_stream
= 0;
2712 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2713 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2714 sel
->so
.output
[i
].stream
);
2716 sel
->gs_input_verts_per_prim
=
2717 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2719 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2720 sel
->tess_turns_off_ngg
=
2721 (sscreen
->info
.family
== CHIP_NAVI10
||
2722 sscreen
->info
.family
== CHIP_NAVI12
||
2723 sscreen
->info
.family
== CHIP_NAVI14
) &&
2724 sel
->gs_num_invocations
* sel
->gs_max_out_vertices
> 256;
2727 case PIPE_SHADER_TESS_CTRL
:
2728 /* Always reserve space for these. */
2729 sel
->patch_outputs_written
|=
2730 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2731 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2733 case PIPE_SHADER_VERTEX
:
2734 case PIPE_SHADER_TESS_EVAL
:
2735 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2736 unsigned name
= sel
->info
.output_semantic_name
[i
];
2737 unsigned index
= sel
->info
.output_semantic_index
[i
];
2740 case TGSI_SEMANTIC_TESSINNER
:
2741 case TGSI_SEMANTIC_TESSOUTER
:
2742 case TGSI_SEMANTIC_PATCH
:
2743 sel
->patch_outputs_written
|=
2744 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2747 case TGSI_SEMANTIC_GENERIC
:
2748 /* don't process indices the function can't handle */
2749 if (index
>= SI_MAX_IO_GENERIC
)
2753 sel
->outputs_written
|=
2754 1ull << si_shader_io_get_unique_index(name
, index
, false);
2755 sel
->outputs_written_before_ps
|=
2756 1ull << si_shader_io_get_unique_index(name
, index
, true);
2758 case TGSI_SEMANTIC_EDGEFLAG
:
2762 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2763 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2765 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2766 * will start on a different bank. (except for the maximum 32*16).
2768 if (sel
->lshs_vertex_stride
< 32*16)
2769 sel
->lshs_vertex_stride
+= 4;
2771 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2772 * conflicts, i.e. each vertex will start at a different bank.
2774 if (sctx
->chip_class
>= GFX9
)
2775 sel
->esgs_itemsize
+= 4;
2777 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2780 if (sel
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
2781 sel
->rast_prim
= PIPE_PRIM_POINTS
;
2782 else if (sel
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
2783 sel
->rast_prim
= PIPE_PRIM_LINE_STRIP
;
2785 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2788 case PIPE_SHADER_FRAGMENT
:
2789 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2790 unsigned name
= sel
->info
.input_semantic_name
[i
];
2791 unsigned index
= sel
->info
.input_semantic_index
[i
];
2794 case TGSI_SEMANTIC_GENERIC
:
2795 /* don't process indices the function can't handle */
2796 if (index
>= SI_MAX_IO_GENERIC
)
2801 1ull << si_shader_io_get_unique_index(name
, index
, true);
2803 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2808 for (i
= 0; i
< 8; i
++)
2809 if (sel
->info
.colors_written
& (1 << i
))
2810 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2812 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2813 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2814 int index
= sel
->info
.input_semantic_index
[i
];
2815 sel
->color_attr_index
[index
] = i
;
2822 /* PA_CL_VS_OUT_CNTL */
2824 sel
->info
.writes_psize
|| sel
->pos_writes_edgeflag
||
2825 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2826 sel
->pa_cl_vs_out_cntl
=
2827 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2828 S_02881C_USE_VTX_EDGE_FLAG(sel
->pos_writes_edgeflag
) |
2829 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2830 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2831 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2832 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2833 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2834 SIX_BITS
: sel
->info
.clipdist_writemask
;
2835 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2836 sel
->info
.num_written_clipdistance
;
2838 /* DB_SHADER_CONTROL */
2839 sel
->db_shader_control
=
2840 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2841 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2842 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2843 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2845 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2846 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2847 sel
->db_shader_control
|=
2848 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2850 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2851 sel
->db_shader_control
|=
2852 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2856 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2858 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2859 * --|-----------|------------|------------|--------------------|-------------------|-------------
2860 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2861 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2862 * 2 | false | true | n/a | LateZ | 1 | 0
2863 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2864 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2866 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2867 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2869 * Don't use ReZ without profiling !!!
2871 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2874 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2876 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2877 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2878 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2879 } else if (sel
->info
.writes_memory
) {
2881 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2882 S_02880C_EXEC_ON_HIER_FAIL(1);
2885 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2888 if (sel
->info
.properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
])
2889 sel
->db_shader_control
|= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2891 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2893 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2894 &sel
->compiler_ctx_state
, sel
,
2895 si_init_shader_selector_async
);
2899 static void si_update_streamout_state(struct si_context
*sctx
)
2901 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2903 if (!shader_with_so
)
2906 sctx
->streamout
.enabled_stream_buffers_mask
=
2907 shader_with_so
->enabled_streamout_buffer_mask
;
2908 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2911 static void si_update_clip_regs(struct si_context
*sctx
,
2912 struct si_shader_selector
*old_hw_vs
,
2913 struct si_shader
*old_hw_vs_variant
,
2914 struct si_shader_selector
*next_hw_vs
,
2915 struct si_shader
*next_hw_vs_variant
)
2919 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2920 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2921 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2922 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2923 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2924 !old_hw_vs_variant
||
2925 !next_hw_vs_variant
||
2926 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2927 next_hw_vs_variant
->key
.opt
.clip_disable
))
2928 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2931 static void si_update_common_shader_state(struct si_context
*sctx
)
2933 sctx
->uses_bindless_samplers
=
2934 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2935 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2936 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2937 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2938 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2939 sctx
->uses_bindless_images
=
2940 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2941 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2942 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2943 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2944 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2945 sctx
->do_update_shaders
= true;
2948 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2950 struct si_context
*sctx
= (struct si_context
*)ctx
;
2951 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2952 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2953 struct si_shader_selector
*sel
= state
;
2955 if (sctx
->vs_shader
.cso
== sel
)
2958 sctx
->vs_shader
.cso
= sel
;
2959 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2960 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2962 si_update_common_shader_state(sctx
);
2963 si_update_vs_viewport_state(sctx
);
2964 si_set_active_descriptors_for_shader(sctx
, sel
);
2965 si_update_streamout_state(sctx
);
2966 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2967 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
2970 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2972 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2973 (sctx
->tes_shader
.cso
&&
2974 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2975 (sctx
->tcs_shader
.cso
&&
2976 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2977 (sctx
->gs_shader
.cso
&&
2978 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2979 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
2980 sctx
->ps_shader
.cso
->info
.uses_primid
);
2983 static bool si_update_ngg(struct si_context
*sctx
)
2985 if (sctx
->chip_class
<= GFX9
||
2986 sctx
->screen
->options
.disable_ngg
)
2989 bool new_ngg
= true;
2991 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&&
2992 sctx
->gs_shader
.cso
->tess_turns_off_ngg
)
2995 if (new_ngg
!= sctx
->ngg
) {
2996 sctx
->ngg
= new_ngg
;
2997 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3003 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
3005 struct si_context
*sctx
= (struct si_context
*)ctx
;
3006 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3007 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3008 struct si_shader_selector
*sel
= state
;
3009 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
3012 if (sctx
->gs_shader
.cso
== sel
)
3015 sctx
->gs_shader
.cso
= sel
;
3016 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3017 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
3019 si_update_common_shader_state(sctx
);
3020 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3022 ngg_changed
= si_update_ngg(sctx
);
3023 if (ngg_changed
|| enable_changed
)
3024 si_shader_change_notify(sctx
);
3025 if (enable_changed
) {
3026 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3027 si_update_tess_uses_prim_id(sctx
);
3029 si_update_vs_viewport_state(sctx
);
3030 si_set_active_descriptors_for_shader(sctx
, sel
);
3031 si_update_streamout_state(sctx
);
3032 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3033 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3036 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
3038 struct si_context
*sctx
= (struct si_context
*)ctx
;
3039 struct si_shader_selector
*sel
= state
;
3040 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
3042 if (sctx
->tcs_shader
.cso
== sel
)
3045 sctx
->tcs_shader
.cso
= sel
;
3046 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3047 si_update_tess_uses_prim_id(sctx
);
3049 si_update_common_shader_state(sctx
);
3052 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
3054 si_set_active_descriptors_for_shader(sctx
, sel
);
3057 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
3059 struct si_context
*sctx
= (struct si_context
*)ctx
;
3060 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3061 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3062 struct si_shader_selector
*sel
= state
;
3063 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
3065 if (sctx
->tes_shader
.cso
== sel
)
3068 sctx
->tes_shader
.cso
= sel
;
3069 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
3070 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
3071 si_update_tess_uses_prim_id(sctx
);
3073 si_update_common_shader_state(sctx
);
3074 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3076 if (enable_changed
) {
3077 si_update_ngg(sctx
);
3078 si_shader_change_notify(sctx
);
3079 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
3081 si_update_vs_viewport_state(sctx
);
3082 si_set_active_descriptors_for_shader(sctx
, sel
);
3083 si_update_streamout_state(sctx
);
3084 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3085 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3088 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3090 struct si_context
*sctx
= (struct si_context
*)ctx
;
3091 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3092 struct si_shader_selector
*sel
= state
;
3094 /* skip if supplied shader is one already in use */
3098 sctx
->ps_shader
.cso
= sel
;
3099 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3101 si_update_common_shader_state(sctx
);
3103 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3104 si_update_tess_uses_prim_id(sctx
);
3107 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3108 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3110 if (sctx
->screen
->has_out_of_order_rast
&&
3112 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
3113 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
3114 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
3115 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3117 si_set_active_descriptors_for_shader(sctx
, sel
);
3118 si_update_ps_colorbuf0_slot(sctx
);
3121 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3123 if (shader
->is_optimized
) {
3124 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
3128 util_queue_fence_destroy(&shader
->ready
);
3131 /* If destroyed shaders were not unbound, the next compiled
3132 * shader variant could get the same pointer address and so
3133 * binding it to the same shader stage would be considered
3134 * a no-op, causing random behavior.
3136 switch (shader
->selector
->type
) {
3137 case PIPE_SHADER_VERTEX
:
3138 if (shader
->key
.as_ls
) {
3139 assert(sctx
->chip_class
<= GFX8
);
3140 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3141 } else if (shader
->key
.as_es
) {
3142 assert(sctx
->chip_class
<= GFX8
);
3143 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3144 } else if (shader
->key
.as_ngg
) {
3145 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3147 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3150 case PIPE_SHADER_TESS_CTRL
:
3151 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3153 case PIPE_SHADER_TESS_EVAL
:
3154 if (shader
->key
.as_es
) {
3155 assert(sctx
->chip_class
<= GFX8
);
3156 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3157 } else if (shader
->key
.as_ngg
) {
3158 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3160 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3163 case PIPE_SHADER_GEOMETRY
:
3164 if (shader
->is_gs_copy_shader
)
3165 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3167 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3169 case PIPE_SHADER_FRAGMENT
:
3170 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3176 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3177 si_shader_destroy(shader
);
3181 void si_destroy_shader_selector(struct si_context
*sctx
,
3182 struct si_shader_selector
*sel
)
3184 struct si_shader
*p
= sel
->first_variant
, *c
;
3185 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3186 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
3187 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3188 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3189 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3190 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3193 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3195 if (current_shader
[sel
->type
]->cso
== sel
) {
3196 current_shader
[sel
->type
]->cso
= NULL
;
3197 current_shader
[sel
->type
]->current
= NULL
;
3201 c
= p
->next_variant
;
3202 si_delete_shader(sctx
, p
);
3206 if (sel
->main_shader_part
)
3207 si_delete_shader(sctx
, sel
->main_shader_part
);
3208 if (sel
->main_shader_part_ls
)
3209 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3210 if (sel
->main_shader_part_es
)
3211 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3212 if (sel
->main_shader_part_ngg
)
3213 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3214 if (sel
->gs_copy_shader
)
3215 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3217 util_queue_fence_destroy(&sel
->ready
);
3218 mtx_destroy(&sel
->mutex
);
3220 ralloc_free(sel
->nir
);
3224 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3226 struct si_context
*sctx
= (struct si_context
*)ctx
;
3227 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3229 si_shader_selector_reference(sctx
, &sel
, NULL
);
3232 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
3233 struct si_shader
*vs
, unsigned name
,
3234 unsigned index
, unsigned interpolate
)
3236 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
3237 unsigned j
, offset
, ps_input_cntl
= 0;
3239 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3240 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
3241 name
== TGSI_SEMANTIC_PRIMID
)
3242 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3244 if (name
== TGSI_SEMANTIC_PCOORD
||
3245 (name
== TGSI_SEMANTIC_TEXCOORD
&&
3246 sctx
->sprite_coord_enable
& (1 << index
))) {
3247 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3250 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
3251 if (name
== vsinfo
->output_semantic_name
[j
] &&
3252 index
== vsinfo
->output_semantic_index
[j
]) {
3253 offset
= vs
->info
.vs_output_param_offset
[j
];
3255 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3256 /* The input is loaded from parameter memory. */
3257 ps_input_cntl
|= S_028644_OFFSET(offset
);
3258 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3259 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3260 /* This can happen with depth-only rendering. */
3263 /* The input is a DEFAULT_VAL constant. */
3264 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3265 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3266 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3269 ps_input_cntl
= S_028644_OFFSET(0x20) |
3270 S_028644_DEFAULT_VAL(offset
);
3276 if (j
== vsinfo
->num_outputs
&& name
== TGSI_SEMANTIC_PRIMID
)
3277 /* PrimID is written after the last output when HW VS is used. */
3278 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3279 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3280 /* No corresponding output found, load defaults into input.
3281 * Don't set any other bits.
3282 * (FLAT_SHADE=1 completely changes behavior) */
3283 ps_input_cntl
= S_028644_OFFSET(0x20);
3284 /* D3D 9 behaviour. GL is undefined */
3285 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
3286 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3288 return ps_input_cntl
;
3291 static void si_emit_spi_map(struct si_context
*sctx
)
3293 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3294 struct si_shader
*vs
= si_get_vs_state(sctx
);
3295 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3296 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
3297 unsigned spi_ps_input_cntl
[32];
3299 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3302 num_interp
= si_get_ps_num_interp(ps
);
3303 assert(num_interp
> 0);
3305 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3306 unsigned name
= psinfo
->input_semantic_name
[i
];
3307 unsigned index
= psinfo
->input_semantic_index
[i
];
3308 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3310 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
3311 index
, interpolate
);
3313 if (name
== TGSI_SEMANTIC_COLOR
) {
3314 assert(index
< ARRAY_SIZE(bcol_interp
));
3315 bcol_interp
[index
] = interpolate
;
3319 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3320 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
3322 for (i
= 0; i
< 2; i
++) {
3323 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3326 spi_ps_input_cntl
[num_written
++] =
3327 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
3331 assert(num_interp
== num_written
);
3333 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3334 /* Dota 2: Only ~16% of SPI map updates set different values. */
3335 /* Talos: Only ~9% of SPI map updates set different values. */
3336 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3337 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
3339 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3341 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3342 sctx
->context_roll
= true;
3346 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3348 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
3350 if (sctx
->init_config_has_vgt_flush
)
3353 /* Done by Vulkan before VGT_FLUSH. */
3354 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3355 si_pm4_cmd_add(sctx
->init_config
,
3356 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3357 si_pm4_cmd_end(sctx
->init_config
, false);
3359 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3360 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3361 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3362 si_pm4_cmd_end(sctx
->init_config
, false);
3363 sctx
->init_config_has_vgt_flush
= true;
3366 /* Initialize state related to ESGS / GSVS ring buffers */
3367 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3369 struct si_shader_selector
*es
=
3370 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3371 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3372 struct si_pm4_state
*pm4
;
3374 /* Chip constants. */
3375 unsigned num_se
= sctx
->screen
->info
.max_se
;
3376 unsigned wave_size
= 64;
3377 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3378 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3379 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3381 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3382 unsigned alignment
= 256 * num_se
;
3383 /* The maximum size is 63.999 MB per SE. */
3384 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3386 /* Calculate the minimum size. */
3387 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
3388 wave_size
, alignment
);
3390 /* These are recommended sizes, not minimum sizes. */
3391 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
3392 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3393 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
3394 gs
->max_gsvs_emit_size
;
3396 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3397 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3398 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3400 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3401 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3403 /* Some rings don't have to be allocated if shaders don't use them.
3404 * (e.g. no varyings between ES and GS or GS and VS)
3406 * GFX9 doesn't have the ESGS ring.
3408 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
3410 (!sctx
->esgs_ring
||
3411 sctx
->esgs_ring
->width0
< esgs_ring_size
);
3412 bool update_gsvs
= gsvs_ring_size
&&
3413 (!sctx
->gsvs_ring
||
3414 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3416 if (!update_esgs
&& !update_gsvs
)
3420 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3422 pipe_aligned_buffer_create(sctx
->b
.screen
,
3423 SI_RESOURCE_FLAG_UNMAPPABLE
,
3425 esgs_ring_size
, alignment
);
3426 if (!sctx
->esgs_ring
)
3431 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3433 pipe_aligned_buffer_create(sctx
->b
.screen
,
3434 SI_RESOURCE_FLAG_UNMAPPABLE
,
3436 gsvs_ring_size
, alignment
);
3437 if (!sctx
->gsvs_ring
)
3441 /* Create the "init_config_gs_rings" state. */
3442 pm4
= CALLOC_STRUCT(si_pm4_state
);
3446 if (sctx
->chip_class
>= GFX7
) {
3447 if (sctx
->esgs_ring
) {
3448 assert(sctx
->chip_class
<= GFX8
);
3449 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3450 sctx
->esgs_ring
->width0
/ 256);
3452 if (sctx
->gsvs_ring
)
3453 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3454 sctx
->gsvs_ring
->width0
/ 256);
3456 if (sctx
->esgs_ring
)
3457 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3458 sctx
->esgs_ring
->width0
/ 256);
3459 if (sctx
->gsvs_ring
)
3460 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3461 sctx
->gsvs_ring
->width0
/ 256);
3464 /* Set the state. */
3465 if (sctx
->init_config_gs_rings
)
3466 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3467 sctx
->init_config_gs_rings
= pm4
;
3469 if (!sctx
->init_config_has_vgt_flush
) {
3470 si_init_config_add_vgt_flush(sctx
);
3471 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3474 /* Flush the context to re-emit both init_config states. */
3475 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3476 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3478 /* Set ring bindings. */
3479 if (sctx
->esgs_ring
) {
3480 assert(sctx
->chip_class
<= GFX8
);
3481 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3482 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3483 true, true, 4, 64, 0);
3484 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3485 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3486 false, false, 0, 0, 0);
3488 if (sctx
->gsvs_ring
) {
3489 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3490 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3491 false, false, 0, 0, 0);
3497 static void si_shader_lock(struct si_shader
*shader
)
3499 mtx_lock(&shader
->selector
->mutex
);
3500 if (shader
->previous_stage_sel
) {
3501 assert(shader
->previous_stage_sel
!= shader
->selector
);
3502 mtx_lock(&shader
->previous_stage_sel
->mutex
);
3506 static void si_shader_unlock(struct si_shader
*shader
)
3508 if (shader
->previous_stage_sel
)
3509 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3510 mtx_unlock(&shader
->selector
->mutex
);
3514 * @returns 1 if \p sel has been updated to use a new scratch buffer
3516 * < 0 if there was a failure
3518 static int si_update_scratch_buffer(struct si_context
*sctx
,
3519 struct si_shader
*shader
)
3521 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3526 /* This shader doesn't need a scratch buffer */
3527 if (shader
->config
.scratch_bytes_per_wave
== 0)
3530 /* Prevent race conditions when updating:
3531 * - si_shader::scratch_bo
3532 * - si_shader::binary::code
3533 * - si_shader::previous_stage::binary::code.
3535 si_shader_lock(shader
);
3537 /* This shader is already configured to use the current
3538 * scratch buffer. */
3539 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3540 si_shader_unlock(shader
);
3544 assert(sctx
->scratch_buffer
);
3546 /* Replace the shader bo with a new bo that has the relocs applied. */
3547 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3548 si_shader_unlock(shader
);
3552 /* Update the shader state to use the new shader bo. */
3553 si_shader_init_pm4_state(sctx
->screen
, shader
);
3555 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3557 si_shader_unlock(shader
);
3561 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
3563 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
3566 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3568 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3571 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3573 if (!sctx
->tes_shader
.cso
)
3574 return NULL
; /* tessellation disabled */
3576 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3577 sctx
->fixed_func_tcs_shader
.current
;
3580 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
3584 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3585 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3586 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3587 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3589 if (sctx
->tes_shader
.cso
) {
3590 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3592 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
3597 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3599 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3602 /* Update the shaders, so that they are using the latest scratch.
3603 * The scratch buffer may have been changed since these shaders were
3604 * last used, so we still need to try to update them, even if they
3605 * require scratch buffers smaller than the current size.
3607 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3611 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3613 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3617 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3619 r
= si_update_scratch_buffer(sctx
, tcs
);
3623 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3625 /* VS can be bound as LS, ES, or VS. */
3626 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3630 if (sctx
->vs_shader
.current
->key
.as_ls
)
3631 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3632 else if (sctx
->vs_shader
.current
->key
.as_es
)
3633 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3634 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3635 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3637 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3640 /* TES can be bound as ES or VS. */
3641 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3645 if (sctx
->tes_shader
.current
->key
.as_es
)
3646 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3647 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3648 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3650 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3656 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3658 unsigned current_scratch_buffer_size
=
3659 si_get_current_scratch_buffer_size(sctx
);
3660 unsigned scratch_bytes_per_wave
=
3661 si_get_max_scratch_bytes_per_wave(sctx
);
3662 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3663 sctx
->scratch_waves
;
3664 unsigned spi_tmpring_size
;
3666 if (scratch_needed_size
> 0) {
3667 if (scratch_needed_size
> current_scratch_buffer_size
) {
3668 /* Create a bigger scratch buffer */
3669 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3671 sctx
->scratch_buffer
=
3672 si_aligned_buffer_create(&sctx
->screen
->b
,
3673 SI_RESOURCE_FLAG_UNMAPPABLE
,
3675 scratch_needed_size
, 256);
3676 if (!sctx
->scratch_buffer
)
3679 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3680 si_context_add_resource_size(sctx
,
3681 &sctx
->scratch_buffer
->b
.b
);
3684 if (!si_update_scratch_relocs(sctx
))
3688 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3689 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3690 "scratch size should already be aligned correctly.");
3692 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3693 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3694 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3695 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3696 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3701 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3703 assert(!sctx
->tess_rings
);
3705 /* The address must be aligned to 2^19, because the shader only
3706 * receives the high 13 bits.
3708 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3709 SI_RESOURCE_FLAG_32BIT
,
3711 sctx
->screen
->tess_offchip_ring_size
+
3712 sctx
->screen
->tess_factor_ring_size
,
3714 if (!sctx
->tess_rings
)
3717 si_init_config_add_vgt_flush(sctx
);
3719 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3720 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3722 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3723 sctx
->screen
->tess_offchip_ring_size
;
3725 /* Append these registers to the init config state. */
3726 if (sctx
->chip_class
>= GFX7
) {
3727 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3728 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3729 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3731 if (sctx
->chip_class
>= GFX10
)
3732 si_pm4_set_reg(sctx
->init_config
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3733 S_030984_BASE_HI(factor_va
>> 40));
3734 else if (sctx
->chip_class
== GFX9
)
3735 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3736 S_030944_BASE_HI(factor_va
>> 40));
3737 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3738 sctx
->screen
->vgt_hs_offchip_param
);
3740 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3741 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3742 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3744 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3745 sctx
->screen
->vgt_hs_offchip_param
);
3748 /* Flush the context to re-emit the init_config state.
3749 * This is done only once in a lifetime of a context.
3751 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3752 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3753 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3756 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3757 union si_vgt_stages_key key
)
3759 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3760 uint32_t stages
= 0;
3763 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3764 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3767 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3770 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3772 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3773 } else if (key
.u
.gs
) {
3774 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3776 } else if (key
.u
.ngg
) {
3777 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3781 stages
|= S_028B54_PRIMGEN_EN(1);
3782 if (key
.u
.streamout
)
3783 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
3784 } else if (key
.u
.gs
)
3785 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3787 if (screen
->info
.chip_class
>= GFX9
)
3788 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3790 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3794 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3795 union si_vgt_stages_key key
)
3797 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3799 if (unlikely(!*pm4
))
3800 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3801 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3804 bool si_update_shaders(struct si_context
*sctx
)
3806 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3807 struct si_compiler_ctx_state compiler_state
;
3808 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3809 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3810 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3811 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3812 union si_vgt_stages_key key
;
3813 unsigned old_spi_shader_col_format
=
3814 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3817 compiler_state
.compiler
= &sctx
->compiler
;
3818 compiler_state
.debug
= sctx
->debug
;
3819 compiler_state
.is_debug_context
= sctx
->is_debug
;
3823 if (sctx
->tes_shader
.cso
)
3825 if (sctx
->gs_shader
.cso
)
3828 if (sctx
->chip_class
>= GFX10
) {
3829 key
.u
.ngg
= sctx
->ngg
;
3831 if (sctx
->gs_shader
.cso
)
3832 key
.u
.streamout
= !!sctx
->gs_shader
.cso
->so
.num_outputs
;
3833 else if (sctx
->tes_shader
.cso
)
3834 key
.u
.streamout
= !!sctx
->tes_shader
.cso
->so
.num_outputs
;
3836 key
.u
.streamout
= !!sctx
->vs_shader
.cso
->so
.num_outputs
;
3839 /* Update TCS and TES. */
3840 if (sctx
->tes_shader
.cso
) {
3841 if (!sctx
->tess_rings
) {
3842 si_init_tess_factor_ring(sctx
);
3843 if (!sctx
->tess_rings
)
3847 if (sctx
->tcs_shader
.cso
) {
3848 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
,
3852 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3854 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3855 sctx
->fixed_func_tcs_shader
.cso
=
3856 si_create_fixed_func_tcs(sctx
);
3857 if (!sctx
->fixed_func_tcs_shader
.cso
)
3861 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3862 key
, &compiler_state
);
3865 si_pm4_bind_state(sctx
, hs
,
3866 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3869 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
3870 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
3874 if (sctx
->gs_shader
.cso
) {
3876 assert(sctx
->chip_class
<= GFX8
);
3877 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3878 } else if (key
.u
.ngg
) {
3879 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3881 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3885 if (sctx
->chip_class
<= GFX8
)
3886 si_pm4_bind_state(sctx
, ls
, NULL
);
3887 si_pm4_bind_state(sctx
, hs
, NULL
);
3891 if (sctx
->gs_shader
.cso
) {
3892 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
3895 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3897 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3899 if (!si_update_gs_ring_buffers(sctx
))
3902 si_pm4_bind_state(sctx
, vs
, NULL
);
3906 si_pm4_bind_state(sctx
, gs
, NULL
);
3907 if (sctx
->chip_class
<= GFX8
)
3908 si_pm4_bind_state(sctx
, es
, NULL
);
3913 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
3914 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
3918 if (!key
.u
.tess
&& !key
.u
.gs
) {
3920 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3921 si_pm4_bind_state(sctx
, vs
, NULL
);
3923 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3925 } else if (sctx
->tes_shader
.cso
) {
3926 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3928 assert(sctx
->gs_shader
.cso
);
3929 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3933 si_update_vgt_shader_config(sctx
, key
);
3935 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3936 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3938 if (sctx
->ps_shader
.cso
) {
3939 unsigned db_shader_control
;
3941 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
3944 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3947 sctx
->ps_shader
.cso
->db_shader_control
|
3948 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3950 if (si_pm4_state_changed(sctx
, ps
) ||
3951 si_pm4_state_changed(sctx
, vs
) ||
3952 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
3953 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3954 sctx
->flatshade
!= rs
->flatshade
) {
3955 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3956 sctx
->flatshade
= rs
->flatshade
;
3957 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3960 if (sctx
->screen
->rbplus_allowed
&&
3961 si_pm4_state_changed(sctx
, ps
) &&
3963 old_spi_shader_col_format
!=
3964 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3965 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3967 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3968 sctx
->ps_db_shader_control
= db_shader_control
;
3969 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3970 if (sctx
->screen
->dpbb_allowed
)
3971 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3974 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3975 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3976 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3978 if (sctx
->chip_class
== GFX6
)
3979 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3981 if (sctx
->framebuffer
.nr_samples
<= 1)
3982 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3986 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
3987 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3988 si_pm4_state_enabled_and_changed(sctx
, es
) ||
3989 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3990 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
3991 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3992 if (!si_update_spi_tmpring_size(sctx
))
3996 if (sctx
->chip_class
>= GFX7
) {
3997 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3998 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3999 else if (!sctx
->queued
.named
.ls
)
4000 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
4002 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
4003 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
4004 else if (!sctx
->queued
.named
.hs
)
4005 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
4007 if (si_pm4_state_enabled_and_changed(sctx
, es
))
4008 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
4009 else if (!sctx
->queued
.named
.es
)
4010 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
4012 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
4013 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
4014 else if (!sctx
->queued
.named
.gs
)
4015 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
4017 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
4018 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
4019 else if (!sctx
->queued
.named
.vs
)
4020 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
4022 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
4023 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
4024 else if (!sctx
->queued
.named
.ps
)
4025 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
4028 sctx
->do_update_shaders
= false;
4032 static void si_emit_scratch_state(struct si_context
*sctx
)
4034 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4036 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
4037 sctx
->spi_tmpring_size
);
4039 if (sctx
->scratch_buffer
) {
4040 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
4041 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
4042 RADEON_PRIO_SCRATCH_BUFFER
);
4046 void si_init_shader_functions(struct si_context
*sctx
)
4048 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
4049 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
4051 sctx
->b
.create_vs_state
= si_create_shader_selector
;
4052 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
4053 sctx
->b
.create_tes_state
= si_create_shader_selector
;
4054 sctx
->b
.create_gs_state
= si_create_shader_selector
;
4055 sctx
->b
.create_fs_state
= si_create_shader_selector
;
4057 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
4058 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
4059 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
4060 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
4061 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
4063 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
4064 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
4065 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
4066 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
4067 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;