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radeonsi/nir: simplify si_lower_nir signature
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 void *si_get_ir_binary(struct si_shader_selector *sel, bool ngg, bool es)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir, true);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 /* These settings affect the compilation, but they are not derived
68 * from the input shader IR.
69 */
70 unsigned shader_variant_flags = 0;
71
72 if (ngg)
73 shader_variant_flags |= 1 << 0;
74 if (sel->nir)
75 shader_variant_flags |= 1 << 1;
76 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
77 shader_variant_flags |= 1 << 2;
78 if (sel->force_correct_derivs_after_kill)
79 shader_variant_flags |= 1 << 3;
80
81 unsigned size = 4 + 4 + ir_size + sizeof(sel->so);
82 char *result = (char*)MALLOC(size);
83 if (!result)
84 return NULL;
85
86 ((uint32_t*)result)[0] = size;
87 ((uint32_t*)result)[1] = shader_variant_flags;
88 memcpy(result + 8, ir_binary, ir_size);
89 memcpy(result + 8 + ir_size, &sel->so, sizeof(sel->so));
90
91 if (sel->nir)
92 blob_finish(&blob);
93
94 return result;
95 }
96
97 /** Copy "data" to "ptr" and return the next dword following copied data. */
98 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
99 {
100 /* data may be NULL if size == 0 */
101 if (size)
102 memcpy(ptr, data, size);
103 ptr += DIV_ROUND_UP(size, 4);
104 return ptr;
105 }
106
107 /** Read data from "ptr". Return the next dword following the data. */
108 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
109 {
110 memcpy(data, ptr, size);
111 ptr += DIV_ROUND_UP(size, 4);
112 return ptr;
113 }
114
115 /**
116 * Write the size as uint followed by the data. Return the next dword
117 * following the copied data.
118 */
119 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
120 {
121 *ptr++ = size;
122 return write_data(ptr, data, size);
123 }
124
125 /**
126 * Read the size as uint followed by the data. Return both via parameters.
127 * Return the next dword following the data.
128 */
129 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
130 {
131 *size = *ptr++;
132 assert(*data == NULL);
133 if (!*size)
134 return ptr;
135 *data = malloc(*size);
136 return read_data(ptr, *data, *size);
137 }
138
139 /**
140 * Return the shader binary in a buffer. The first 4 bytes contain its size
141 * as integer.
142 */
143 static void *si_get_shader_binary(struct si_shader *shader)
144 {
145 /* There is always a size of data followed by the data itself. */
146 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
147 strlen(shader->binary.llvm_ir_string) + 1 : 0;
148
149 /* Refuse to allocate overly large buffers and guard against integer
150 * overflow. */
151 if (shader->binary.elf_size > UINT_MAX / 4 ||
152 llvm_ir_size > UINT_MAX / 4)
153 return NULL;
154
155 unsigned size =
156 4 + /* total size */
157 4 + /* CRC32 of the data below */
158 align(sizeof(shader->config), 4) +
159 align(sizeof(shader->info), 4) +
160 4 + align(shader->binary.elf_size, 4) +
161 4 + align(llvm_ir_size, 4);
162 void *buffer = CALLOC(1, size);
163 uint32_t *ptr = (uint32_t*)buffer;
164
165 if (!buffer)
166 return NULL;
167
168 *ptr++ = size;
169 ptr++; /* CRC32 is calculated at the end. */
170
171 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
172 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
173 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
174 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
175 assert((char *)ptr - (char *)buffer == size);
176
177 /* Compute CRC32. */
178 ptr = (uint32_t*)buffer;
179 ptr++;
180 *ptr = util_hash_crc32(ptr + 1, size - 8);
181
182 return buffer;
183 }
184
185 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
186 {
187 uint32_t *ptr = (uint32_t*)binary;
188 uint32_t size = *ptr++;
189 uint32_t crc32 = *ptr++;
190 unsigned chunk_size;
191 unsigned elf_size;
192
193 if (util_hash_crc32(ptr, size - 8) != crc32) {
194 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
195 return false;
196 }
197
198 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
199 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
200 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
201 &elf_size);
202 shader->binary.elf_size = elf_size;
203 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
204
205 return true;
206 }
207
208 /**
209 * Insert a shader into the cache. It's assumed the shader is not in the cache.
210 * Use si_shader_cache_load_shader before calling this.
211 *
212 * Returns false on failure, in which case the ir_binary should be freed.
213 */
214 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
215 struct si_shader *shader,
216 bool insert_into_disk_cache)
217 {
218 void *hw_binary;
219 struct hash_entry *entry;
220 uint8_t key[CACHE_KEY_SIZE];
221
222 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
223 if (entry)
224 return false; /* already added */
225
226 hw_binary = si_get_shader_binary(shader);
227 if (!hw_binary)
228 return false;
229
230 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
231 hw_binary) == NULL) {
232 FREE(hw_binary);
233 return false;
234 }
235
236 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
237 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
238 *((uint32_t *)ir_binary), key);
239 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
240 *((uint32_t *) hw_binary), NULL);
241 }
242
243 return true;
244 }
245
246 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
247 struct si_shader *shader)
248 {
249 struct hash_entry *entry =
250 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
251 if (!entry) {
252 if (sscreen->disk_shader_cache) {
253 unsigned char sha1[CACHE_KEY_SIZE];
254 size_t tg_size = *((uint32_t *) ir_binary);
255
256 disk_cache_compute_key(sscreen->disk_shader_cache,
257 ir_binary, tg_size, sha1);
258
259 size_t binary_size;
260 uint8_t *buffer =
261 disk_cache_get(sscreen->disk_shader_cache,
262 sha1, &binary_size);
263 if (!buffer)
264 return false;
265
266 if (binary_size < sizeof(uint32_t) ||
267 *((uint32_t*)buffer) != binary_size) {
268 /* Something has gone wrong discard the item
269 * from the cache and rebuild/link from
270 * source.
271 */
272 assert(!"Invalid radeonsi shader disk cache "
273 "item!");
274
275 disk_cache_remove(sscreen->disk_shader_cache,
276 sha1);
277 free(buffer);
278
279 return false;
280 }
281
282 if (!si_load_shader_binary(shader, buffer)) {
283 free(buffer);
284 return false;
285 }
286 free(buffer);
287
288 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
289 shader, false))
290 FREE(ir_binary);
291 } else {
292 return false;
293 }
294 } else {
295 if (si_load_shader_binary(shader, entry->data))
296 FREE(ir_binary);
297 else
298 return false;
299 }
300 p_atomic_inc(&sscreen->num_shader_cache_hits);
301 return true;
302 }
303
304 static uint32_t si_shader_cache_key_hash(const void *key)
305 {
306 /* The first dword is the key size. */
307 return util_hash_crc32(key, *(uint32_t*)key);
308 }
309
310 static bool si_shader_cache_key_equals(const void *a, const void *b)
311 {
312 uint32_t *keya = (uint32_t*)a;
313 uint32_t *keyb = (uint32_t*)b;
314
315 /* The first dword is the key size. */
316 if (*keya != *keyb)
317 return false;
318
319 return memcmp(keya, keyb, *keya) == 0;
320 }
321
322 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
323 {
324 FREE((void*)entry->key);
325 FREE(entry->data);
326 }
327
328 bool si_init_shader_cache(struct si_screen *sscreen)
329 {
330 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
331 sscreen->shader_cache =
332 _mesa_hash_table_create(NULL,
333 si_shader_cache_key_hash,
334 si_shader_cache_key_equals);
335
336 return sscreen->shader_cache != NULL;
337 }
338
339 void si_destroy_shader_cache(struct si_screen *sscreen)
340 {
341 if (sscreen->shader_cache)
342 _mesa_hash_table_destroy(sscreen->shader_cache,
343 si_destroy_shader_cache_entry);
344 simple_mtx_destroy(&sscreen->shader_cache_mutex);
345 }
346
347 /* SHADER STATES */
348
349 static void si_set_tesseval_regs(struct si_screen *sscreen,
350 const struct si_shader_selector *tes,
351 struct si_pm4_state *pm4)
352 {
353 const struct tgsi_shader_info *info = &tes->info;
354 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
355 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
356 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
357 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
358 unsigned type, partitioning, topology, distribution_mode;
359
360 switch (tes_prim_mode) {
361 case PIPE_PRIM_LINES:
362 type = V_028B6C_TESS_ISOLINE;
363 break;
364 case PIPE_PRIM_TRIANGLES:
365 type = V_028B6C_TESS_TRIANGLE;
366 break;
367 case PIPE_PRIM_QUADS:
368 type = V_028B6C_TESS_QUAD;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 switch (tes_spacing) {
376 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
377 partitioning = V_028B6C_PART_FRAC_ODD;
378 break;
379 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
380 partitioning = V_028B6C_PART_FRAC_EVEN;
381 break;
382 case PIPE_TESS_SPACING_EQUAL:
383 partitioning = V_028B6C_PART_INTEGER;
384 break;
385 default:
386 assert(0);
387 return;
388 }
389
390 if (tes_point_mode)
391 topology = V_028B6C_OUTPUT_POINT;
392 else if (tes_prim_mode == PIPE_PRIM_LINES)
393 topology = V_028B6C_OUTPUT_LINE;
394 else if (tes_vertex_order_cw)
395 /* for some reason, this must be the other way around */
396 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
397 else
398 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
399
400 if (sscreen->info.has_distributed_tess) {
401 if (sscreen->info.family == CHIP_FIJI ||
402 sscreen->info.family >= CHIP_POLARIS10)
403 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
404 else
405 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
406 } else
407 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
408
409 assert(pm4->shader);
410 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
411 S_028B6C_PARTITIONING(partitioning) |
412 S_028B6C_TOPOLOGY(topology) |
413 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
414 }
415
416 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
417 * whether the "fractional odd" tessellation spacing is used.
418 *
419 * Possible VGT configurations and which state should set the register:
420 *
421 * Reg set in | VGT shader configuration | Value
422 * ------------------------------------------------------
423 * VS as VS | VS | 30
424 * VS as ES | ES -> GS -> VS | 30
425 * TES as VS | LS -> HS -> VS | 14 or 30
426 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
427 *
428 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
429 */
430 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
431 struct si_shader_selector *sel,
432 struct si_shader *shader,
433 struct si_pm4_state *pm4)
434 {
435 unsigned type = sel->type;
436
437 if (sscreen->info.family < CHIP_POLARIS10 ||
438 sscreen->info.chip_class >= GFX10)
439 return;
440
441 /* VS as VS, or VS as ES: */
442 if ((type == PIPE_SHADER_VERTEX &&
443 (!shader ||
444 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
445 /* TES as VS, or TES as ES: */
446 type == PIPE_SHADER_TESS_EVAL) {
447 unsigned vtx_reuse_depth = 30;
448
449 if (type == PIPE_SHADER_TESS_EVAL &&
450 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
451 PIPE_TESS_SPACING_FRACTIONAL_ODD)
452 vtx_reuse_depth = 14;
453
454 assert(pm4->shader);
455 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
456 }
457 }
458
459 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
460 {
461 if (shader->pm4)
462 si_pm4_clear_state(shader->pm4);
463 else
464 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
465
466 if (shader->pm4) {
467 shader->pm4->shader = shader;
468 return shader->pm4;
469 } else {
470 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
471 return NULL;
472 }
473 }
474
475 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
476 {
477 /* Add the pointer to VBO descriptors. */
478 return num_always_on_user_sgprs + 1;
479 }
480
481 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
482 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
483 struct si_shader *shader, bool legacy_vs_prim_id)
484 {
485 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
486 (shader->previous_stage_sel &&
487 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
488
489 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
490 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
491 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
492 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
493 */
494 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
495
496 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
497 return 3;
498 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
499 return 2;
500 else if (is_ls || shader->info.uses_instanceid)
501 return 1;
502 else
503 return 0;
504 }
505
506 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
507 {
508 struct si_pm4_state *pm4;
509 uint64_t va;
510
511 assert(sscreen->info.chip_class <= GFX8);
512
513 pm4 = si_get_shader_pm4_state(shader);
514 if (!pm4)
515 return;
516
517 va = shader->bo->gpu_address;
518 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
519
520 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
521 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
522
523 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
524 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
525 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
526 S_00B528_DX10_CLAMP(1) |
527 S_00B528_FLOAT_MODE(shader->config.float_mode);
528 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
529 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
530 }
531
532 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
533 {
534 struct si_pm4_state *pm4;
535 uint64_t va;
536
537 pm4 = si_get_shader_pm4_state(shader);
538 if (!pm4)
539 return;
540
541 va = shader->bo->gpu_address;
542 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
543
544 if (sscreen->info.chip_class >= GFX9) {
545 if (sscreen->info.chip_class >= GFX10) {
546 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
547 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
548 } else {
549 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
550 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
551 }
552
553 unsigned num_user_sgprs =
554 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
555
556 shader->config.rsrc2 =
557 S_00B42C_USER_SGPR(num_user_sgprs) |
558 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
559
560 if (sscreen->info.chip_class >= GFX10)
561 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
562 else
563 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
564 } else {
565 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
566 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
567
568 shader->config.rsrc2 =
569 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
570 S_00B42C_OC_LDS_EN(1) |
571 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
572 }
573
574 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
575 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
576 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
577 (sscreen->info.chip_class <= GFX9 ?
578 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
579 S_00B428_DX10_CLAMP(1) |
580 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
581 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
582 S_00B428_FLOAT_MODE(shader->config.float_mode) |
583 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
584 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
585
586 if (sscreen->info.chip_class <= GFX8) {
587 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
588 shader->config.rsrc2);
589 }
590 }
591
592 static void si_emit_shader_es(struct si_context *sctx)
593 {
594 struct si_shader *shader = sctx->queued.named.es->shader;
595 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
596
597 if (!shader)
598 return;
599
600 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
601 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
602 shader->selector->esgs_itemsize / 4);
603
604 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
605 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
606 SI_TRACKED_VGT_TF_PARAM,
607 shader->vgt_tf_param);
608
609 if (shader->vgt_vertex_reuse_block_cntl)
610 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
611 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
612 shader->vgt_vertex_reuse_block_cntl);
613
614 if (initial_cdw != sctx->gfx_cs->current.cdw)
615 sctx->context_roll = true;
616 }
617
618 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
619 {
620 struct si_pm4_state *pm4;
621 unsigned num_user_sgprs;
622 unsigned vgpr_comp_cnt;
623 uint64_t va;
624 unsigned oc_lds_en;
625
626 assert(sscreen->info.chip_class <= GFX8);
627
628 pm4 = si_get_shader_pm4_state(shader);
629 if (!pm4)
630 return;
631
632 pm4->atom.emit = si_emit_shader_es;
633 va = shader->bo->gpu_address;
634 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
635
636 if (shader->selector->type == PIPE_SHADER_VERTEX) {
637 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
638 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
639 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
640 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
641 num_user_sgprs = SI_TES_NUM_USER_SGPR;
642 } else
643 unreachable("invalid shader selector type");
644
645 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
646
647 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
648 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
649 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
650 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
651 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
652 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
653 S_00B328_DX10_CLAMP(1) |
654 S_00B328_FLOAT_MODE(shader->config.float_mode));
655 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
656 S_00B32C_USER_SGPR(num_user_sgprs) |
657 S_00B32C_OC_LDS_EN(oc_lds_en) |
658 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
659
660 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
661 si_set_tesseval_regs(sscreen, shader->selector, pm4);
662
663 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
664 }
665
666 void gfx9_get_gs_info(struct si_shader_selector *es,
667 struct si_shader_selector *gs,
668 struct gfx9_gs_info *out)
669 {
670 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
671 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
672 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
673 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
674
675 /* All these are in dwords: */
676 /* We can't allow using the whole LDS, because GS waves compete with
677 * other shader stages for LDS space. */
678 const unsigned max_lds_size = 8 * 1024;
679 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
680 unsigned esgs_lds_size;
681
682 /* All these are per subgroup: */
683 const unsigned max_out_prims = 32 * 1024;
684 const unsigned max_es_verts = 255;
685 const unsigned ideal_gs_prims = 64;
686 unsigned max_gs_prims, gs_prims;
687 unsigned min_es_verts, es_verts, worst_case_es_verts;
688
689 if (uses_adjacency || gs_num_invocations > 1)
690 max_gs_prims = 127 / gs_num_invocations;
691 else
692 max_gs_prims = 255;
693
694 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
695 * Make sure we don't go over the maximum value.
696 */
697 if (gs->gs_max_out_vertices > 0) {
698 max_gs_prims = MIN2(max_gs_prims,
699 max_out_prims /
700 (gs->gs_max_out_vertices * gs_num_invocations));
701 }
702 assert(max_gs_prims > 0);
703
704 /* If the primitive has adjacency, halve the number of vertices
705 * that will be reused in multiple primitives.
706 */
707 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
708
709 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
710 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
711
712 /* Compute ESGS LDS size based on the worst case number of ES vertices
713 * needed to create the target number of GS prims per subgroup.
714 */
715 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
716
717 /* If total LDS usage is too big, refactor partitions based on ratio
718 * of ESGS item sizes.
719 */
720 if (esgs_lds_size > max_lds_size) {
721 /* Our target GS Prims Per Subgroup was too large. Calculate
722 * the maximum number of GS Prims Per Subgroup that will fit
723 * into LDS, capped by the maximum that the hardware can support.
724 */
725 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
726 max_gs_prims);
727 assert(gs_prims > 0);
728 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
729 max_es_verts);
730
731 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
732 assert(esgs_lds_size <= max_lds_size);
733 }
734
735 /* Now calculate remaining ESGS information. */
736 if (esgs_lds_size)
737 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
738 else
739 es_verts = max_es_verts;
740
741 /* Vertices for adjacency primitives are not always reused, so restore
742 * it for ES_VERTS_PER_SUBGRP.
743 */
744 min_es_verts = gs->gs_input_verts_per_prim;
745
746 /* For normal primitives, the VGT only checks if they are past the ES
747 * verts per subgroup after allocating a full GS primitive and if they
748 * are, kick off a new subgroup. But if those additional ES verts are
749 * unique (e.g. not reused) we need to make sure there is enough LDS
750 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
751 */
752 es_verts -= min_es_verts - 1;
753
754 out->es_verts_per_subgroup = es_verts;
755 out->gs_prims_per_subgroup = gs_prims;
756 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
757 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
758 gs->gs_max_out_vertices;
759 out->esgs_ring_size = 4 * esgs_lds_size;
760
761 assert(out->max_prims_per_subgroup <= max_out_prims);
762 }
763
764 static void si_emit_shader_gs(struct si_context *sctx)
765 {
766 struct si_shader *shader = sctx->queued.named.gs->shader;
767 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
768
769 if (!shader)
770 return;
771
772 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
773 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
774 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
775 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
776 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
777 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
778 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
779
780 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
781 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
782 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
783 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
784
785 /* R_028B38_VGT_GS_MAX_VERT_OUT */
786 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
787 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
788 shader->ctx_reg.gs.vgt_gs_max_vert_out);
789
790 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
791 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
792 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
793 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
794 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
795 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
796 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
797 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
798
799 /* R_028B90_VGT_GS_INSTANCE_CNT */
800 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
801 SI_TRACKED_VGT_GS_INSTANCE_CNT,
802 shader->ctx_reg.gs.vgt_gs_instance_cnt);
803
804 if (sctx->chip_class >= GFX9) {
805 /* R_028A44_VGT_GS_ONCHIP_CNTL */
806 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
807 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
808 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
809 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
810 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
811 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
812 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
813 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
814 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
815 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
816 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
817
818 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
819 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
820 SI_TRACKED_VGT_TF_PARAM,
821 shader->vgt_tf_param);
822 if (shader->vgt_vertex_reuse_block_cntl)
823 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
824 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
825 shader->vgt_vertex_reuse_block_cntl);
826 }
827
828 if (initial_cdw != sctx->gfx_cs->current.cdw)
829 sctx->context_roll = true;
830 }
831
832 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
833 {
834 struct si_shader_selector *sel = shader->selector;
835 const ubyte *num_components = sel->info.num_stream_output_components;
836 unsigned gs_num_invocations = sel->gs_num_invocations;
837 struct si_pm4_state *pm4;
838 uint64_t va;
839 unsigned max_stream = sel->max_gs_stream;
840 unsigned offset;
841
842 pm4 = si_get_shader_pm4_state(shader);
843 if (!pm4)
844 return;
845
846 pm4->atom.emit = si_emit_shader_gs;
847
848 offset = num_components[0] * sel->gs_max_out_vertices;
849 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
850
851 if (max_stream >= 1)
852 offset += num_components[1] * sel->gs_max_out_vertices;
853 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
854
855 if (max_stream >= 2)
856 offset += num_components[2] * sel->gs_max_out_vertices;
857 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
858
859 if (max_stream >= 3)
860 offset += num_components[3] * sel->gs_max_out_vertices;
861 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
862
863 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
864 assert(offset < (1 << 15));
865
866 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
867
868 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
869 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
870 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
871 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
872
873 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
874 S_028B90_ENABLE(gs_num_invocations > 0);
875
876 va = shader->bo->gpu_address;
877 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
878
879 if (sscreen->info.chip_class >= GFX9) {
880 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
881 unsigned es_type = shader->key.part.gs.es->type;
882 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
883
884 if (es_type == PIPE_SHADER_VERTEX) {
885 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
886 } else if (es_type == PIPE_SHADER_TESS_EVAL)
887 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
888 else
889 unreachable("invalid shader selector type");
890
891 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
892 * VGPR[0:4] are always loaded.
893 */
894 if (sel->info.uses_invocationid)
895 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
896 else if (sel->info.uses_primid)
897 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
898 else if (input_prim >= PIPE_PRIM_TRIANGLES)
899 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
900 else
901 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
902
903 unsigned num_user_sgprs;
904 if (es_type == PIPE_SHADER_VERTEX)
905 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
906 else
907 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
908
909 if (sscreen->info.chip_class >= GFX10) {
910 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
911 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
912 } else {
913 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
914 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
915 }
916
917 uint32_t rsrc1 =
918 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
919 S_00B228_DX10_CLAMP(1) |
920 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
921 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
922 S_00B228_FLOAT_MODE(shader->config.float_mode) |
923 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
924 uint32_t rsrc2 =
925 S_00B22C_USER_SGPR(num_user_sgprs) |
926 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
927 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
928 S_00B22C_LDS_SIZE(shader->config.lds_size) |
929 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
930
931 if (sscreen->info.chip_class >= GFX10) {
932 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
933 } else {
934 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
935 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
936 }
937
938 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
939 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
940
941 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
942 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
943 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
944 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
945 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
946 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
947 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
948 shader->key.part.gs.es->esgs_itemsize / 4;
949
950 if (es_type == PIPE_SHADER_TESS_EVAL)
951 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
952
953 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
954 NULL, pm4);
955 } else {
956 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
957 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
958
959 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
960 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
961 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
962 S_00B228_DX10_CLAMP(1) |
963 S_00B228_FLOAT_MODE(shader->config.float_mode));
964 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
965 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
966 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
967 }
968 }
969
970 /* Common tail code for NGG primitive shaders. */
971 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
972 struct si_shader *shader,
973 unsigned initial_cdw)
974 {
975 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
976 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
977 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
978 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
979 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
980 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
981 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
982 SI_TRACKED_VGT_PRIMITIVEID_EN,
983 shader->ctx_reg.ngg.vgt_primitiveid_en);
984 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
985 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
986 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
987 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
988 SI_TRACKED_VGT_GS_INSTANCE_CNT,
989 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
990 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
991 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
992 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
993 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
994 SI_TRACKED_SPI_VS_OUT_CONFIG,
995 shader->ctx_reg.ngg.spi_vs_out_config);
996 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
997 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
998 shader->ctx_reg.ngg.spi_shader_idx_format,
999 shader->ctx_reg.ngg.spi_shader_pos_format);
1000 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1001 SI_TRACKED_PA_CL_VTE_CNTL,
1002 shader->ctx_reg.ngg.pa_cl_vte_cntl);
1003 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1004 SI_TRACKED_PA_CL_NGG_CNTL,
1005 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1006
1007 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1008 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1009 shader->pa_cl_vs_out_cntl,
1010 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1011
1012 if (initial_cdw != sctx->gfx_cs->current.cdw)
1013 sctx->context_roll = true;
1014 }
1015
1016 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1017 {
1018 struct si_shader *shader = sctx->queued.named.gs->shader;
1019 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1020
1021 if (!shader)
1022 return;
1023
1024 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1025 }
1026
1027 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1028 {
1029 struct si_shader *shader = sctx->queued.named.gs->shader;
1030 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1031
1032 if (!shader)
1033 return;
1034
1035 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1036 SI_TRACKED_VGT_TF_PARAM,
1037 shader->vgt_tf_param);
1038
1039 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1040 }
1041
1042 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1043 {
1044 struct si_shader *shader = sctx->queued.named.gs->shader;
1045 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1046
1047 if (!shader)
1048 return;
1049
1050 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1051 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1052 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1053
1054 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1055 }
1056
1057 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1058 {
1059 struct si_shader *shader = sctx->queued.named.gs->shader;
1060 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1061
1062 if (!shader)
1063 return;
1064
1065 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1066 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1067 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1068 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1069 SI_TRACKED_VGT_TF_PARAM,
1070 shader->vgt_tf_param);
1071
1072 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1073 }
1074
1075 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1076 {
1077 if (gs->type == PIPE_SHADER_GEOMETRY)
1078 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1079
1080 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1081 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1082 return PIPE_PRIM_POINTS;
1083 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1084 return PIPE_PRIM_LINES;
1085 return PIPE_PRIM_TRIANGLES;
1086 }
1087
1088 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1089 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1090 }
1091
1092 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1093 {
1094 bool misc_vec_ena =
1095 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1096 sel->info.writes_layer || sel->info.writes_viewport_index;
1097 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1098 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1099 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1100 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1101 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1102 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1103 }
1104
1105 /**
1106 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1107 * in NGG mode.
1108 */
1109 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1110 {
1111 const struct si_shader_selector *gs_sel = shader->selector;
1112 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1113 enum pipe_shader_type gs_type = shader->selector->type;
1114 const struct si_shader_selector *es_sel =
1115 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1116 const struct tgsi_shader_info *es_info = &es_sel->info;
1117 enum pipe_shader_type es_type = es_sel->type;
1118 unsigned num_user_sgprs;
1119 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1120 uint64_t va;
1121 unsigned window_space =
1122 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1123 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1124 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1125 unsigned input_prim = si_get_input_prim(gs_sel);
1126 bool break_wave_at_eoi = false;
1127 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1128 if (!pm4)
1129 return;
1130
1131 if (es_type == PIPE_SHADER_TESS_EVAL) {
1132 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1133 : gfx10_emit_shader_ngg_tess_nogs;
1134 } else {
1135 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1136 : gfx10_emit_shader_ngg_notess_nogs;
1137 }
1138
1139 va = shader->bo->gpu_address;
1140 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1141
1142 if (es_type == PIPE_SHADER_VERTEX) {
1143 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1144
1145 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1146 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1147 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1148 } else {
1149 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1150 }
1151 } else {
1152 assert(es_type == PIPE_SHADER_TESS_EVAL);
1153 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1154 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1155
1156 if (es_enable_prim_id || gs_info->uses_primid)
1157 break_wave_at_eoi = true;
1158 }
1159
1160 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1161 * VGPR[0:4] are always loaded.
1162 *
1163 * Vertex shaders always need to load VGPR3, because they need to
1164 * pass edge flags for decomposed primitives (such as quads) to the PA
1165 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1166 */
1167 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1168 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1169 else if (gs_info->uses_primid)
1170 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1171 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1172 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1173 else
1174 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1175
1176 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1177 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1178 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1179 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1180 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1181 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1182 S_00B228_DX10_CLAMP(1) |
1183 S_00B228_MEM_ORDERED(1) |
1184 S_00B228_WGP_MODE(1) |
1185 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1186 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1187 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1188 S_00B22C_USER_SGPR(num_user_sgprs) |
1189 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1190 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1191 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1192 S_00B22C_LDS_SIZE(shader->config.lds_size));
1193
1194 nparams = MAX2(shader->info.nr_param_exports, 1);
1195 shader->ctx_reg.ngg.spi_vs_out_config =
1196 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1197 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1198
1199 shader->ctx_reg.ngg.spi_shader_idx_format =
1200 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1201 shader->ctx_reg.ngg.spi_shader_pos_format =
1202 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1203 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1204 V_02870C_SPI_SHADER_4COMP :
1205 V_02870C_SPI_SHADER_NONE) |
1206 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1207 V_02870C_SPI_SHADER_4COMP :
1208 V_02870C_SPI_SHADER_NONE) |
1209 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1210 V_02870C_SPI_SHADER_4COMP :
1211 V_02870C_SPI_SHADER_NONE);
1212
1213 shader->ctx_reg.ngg.vgt_primitiveid_en =
1214 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1215 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1216
1217 if (gs_type == PIPE_SHADER_GEOMETRY) {
1218 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1219 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1220 } else {
1221 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1222 }
1223
1224 if (es_type == PIPE_SHADER_TESS_EVAL)
1225 si_set_tesseval_regs(sscreen, es_sel, pm4);
1226
1227 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1228 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1229 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1230 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1231 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1232 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1233 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1234 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1235 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1236 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1237 S_028B90_CNT(gs_num_invocations) |
1238 S_028B90_ENABLE(gs_num_invocations > 1) |
1239 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1240 shader->ngg.max_vert_out_per_gs_instance);
1241
1242 /* Always output hw-generated edge flags and pass them via the prim
1243 * export to prevent drawing lines on internal edges of decomposed
1244 * primitives (such as quads) with polygon mode = lines. Only VS needs
1245 * this.
1246 */
1247 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1248 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1249 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1250
1251 shader->ge_cntl =
1252 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1253 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1254 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1255
1256 /* Bug workaround for a possible hang with non-tessellation cases.
1257 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1258 *
1259 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1260 */
1261 if ((sscreen->info.family == CHIP_NAVI10 ||
1262 sscreen->info.family == CHIP_NAVI12 ||
1263 sscreen->info.family == CHIP_NAVI14) &&
1264 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1265 shader->ngg.hw_max_esverts != 256) {
1266 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1267
1268 if (shader->ngg.hw_max_esverts > 5) {
1269 shader->ge_cntl |=
1270 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1271 }
1272 }
1273
1274 if (window_space) {
1275 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1276 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1277 } else {
1278 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1279 S_028818_VTX_W0_FMT(1) |
1280 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1281 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1282 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1283 }
1284 }
1285
1286 static void si_emit_shader_vs(struct si_context *sctx)
1287 {
1288 struct si_shader *shader = sctx->queued.named.vs->shader;
1289 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1290
1291 if (!shader)
1292 return;
1293
1294 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1295 SI_TRACKED_VGT_GS_MODE,
1296 shader->ctx_reg.vs.vgt_gs_mode);
1297 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1298 SI_TRACKED_VGT_PRIMITIVEID_EN,
1299 shader->ctx_reg.vs.vgt_primitiveid_en);
1300
1301 if (sctx->chip_class <= GFX8) {
1302 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1303 SI_TRACKED_VGT_REUSE_OFF,
1304 shader->ctx_reg.vs.vgt_reuse_off);
1305 }
1306
1307 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1308 SI_TRACKED_SPI_VS_OUT_CONFIG,
1309 shader->ctx_reg.vs.spi_vs_out_config);
1310
1311 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1312 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1313 shader->ctx_reg.vs.spi_shader_pos_format);
1314
1315 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1316 SI_TRACKED_PA_CL_VTE_CNTL,
1317 shader->ctx_reg.vs.pa_cl_vte_cntl);
1318
1319 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1320 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1321 SI_TRACKED_VGT_TF_PARAM,
1322 shader->vgt_tf_param);
1323
1324 if (shader->vgt_vertex_reuse_block_cntl)
1325 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1326 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1327 shader->vgt_vertex_reuse_block_cntl);
1328
1329 if (initial_cdw != sctx->gfx_cs->current.cdw)
1330 sctx->context_roll = true;
1331
1332 /* Required programming for tessellation. (legacy pipeline only) */
1333 if (sctx->chip_class == GFX10 &&
1334 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1335 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1336 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1337 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1338 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1339 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1340 }
1341
1342 if (sctx->chip_class >= GFX10) {
1343 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1344 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1345 shader->pa_cl_vs_out_cntl,
1346 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1347 }
1348 }
1349
1350 /**
1351 * Compute the state for \p shader, which will run as a vertex shader on the
1352 * hardware.
1353 *
1354 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1355 * is the copy shader.
1356 */
1357 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1358 struct si_shader_selector *gs)
1359 {
1360 const struct tgsi_shader_info *info = &shader->selector->info;
1361 struct si_pm4_state *pm4;
1362 unsigned num_user_sgprs, vgpr_comp_cnt;
1363 uint64_t va;
1364 unsigned nparams, oc_lds_en;
1365 unsigned window_space =
1366 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1367 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1368
1369 pm4 = si_get_shader_pm4_state(shader);
1370 if (!pm4)
1371 return;
1372
1373 pm4->atom.emit = si_emit_shader_vs;
1374
1375 /* We always write VGT_GS_MODE in the VS state, because every switch
1376 * between different shader pipelines involving a different GS or no
1377 * GS at all involves a switch of the VS (different GS use different
1378 * copy shaders). On the other hand, when the API switches from a GS to
1379 * no GS and then back to the same GS used originally, the GS state is
1380 * not sent again.
1381 */
1382 if (!gs) {
1383 unsigned mode = V_028A40_GS_OFF;
1384
1385 /* PrimID needs GS scenario A. */
1386 if (enable_prim_id)
1387 mode = V_028A40_GS_SCENARIO_A;
1388
1389 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1390 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1391 } else {
1392 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1393 sscreen->info.chip_class);
1394 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1395 }
1396
1397 if (sscreen->info.chip_class <= GFX8) {
1398 /* Reuse needs to be set off if we write oViewport. */
1399 shader->ctx_reg.vs.vgt_reuse_off =
1400 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1401 }
1402
1403 va = shader->bo->gpu_address;
1404 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1405
1406 if (gs) {
1407 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1408 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1409 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1410 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1411
1412 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1413 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1414 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1415 } else {
1416 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1417 }
1418 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1419 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1420 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1421 } else
1422 unreachable("invalid shader selector type");
1423
1424 /* VS is required to export at least one param. */
1425 nparams = MAX2(shader->info.nr_param_exports, 1);
1426 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1427
1428 if (sscreen->info.chip_class >= GFX10) {
1429 shader->ctx_reg.vs.spi_vs_out_config |=
1430 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1431 }
1432
1433 shader->ctx_reg.vs.spi_shader_pos_format =
1434 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1435 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1436 V_02870C_SPI_SHADER_4COMP :
1437 V_02870C_SPI_SHADER_NONE) |
1438 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1439 V_02870C_SPI_SHADER_4COMP :
1440 V_02870C_SPI_SHADER_NONE) |
1441 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1442 V_02870C_SPI_SHADER_4COMP :
1443 V_02870C_SPI_SHADER_NONE);
1444 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1445
1446 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1447
1448 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1449 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1450
1451 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1452 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1453 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1454 S_00B128_DX10_CLAMP(1) |
1455 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1456 S_00B128_FLOAT_MODE(shader->config.float_mode);
1457 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1458 S_00B12C_OC_LDS_EN(oc_lds_en) |
1459 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1460
1461 if (sscreen->info.chip_class <= GFX9)
1462 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1463
1464 if (!sscreen->use_ngg_streamout) {
1465 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1466 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1467 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1468 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1469 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1470 }
1471
1472 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1473 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1474
1475 if (window_space)
1476 shader->ctx_reg.vs.pa_cl_vte_cntl =
1477 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1478 else
1479 shader->ctx_reg.vs.pa_cl_vte_cntl =
1480 S_028818_VTX_W0_FMT(1) |
1481 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1482 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1483 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1484
1485 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1486 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1487
1488 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1489 }
1490
1491 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1492 {
1493 struct tgsi_shader_info *info = &ps->selector->info;
1494 unsigned num_colors = !!(info->colors_read & 0x0f) +
1495 !!(info->colors_read & 0xf0);
1496 unsigned num_interp = ps->selector->info.num_inputs +
1497 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1498
1499 assert(num_interp <= 32);
1500 return MIN2(num_interp, 32);
1501 }
1502
1503 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1504 {
1505 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1506 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1507
1508 /* If the i-th target format is set, all previous target formats must
1509 * be non-zero to avoid hangs.
1510 */
1511 for (i = 0; i < num_targets; i++)
1512 if (!(value & (0xf << (i * 4))))
1513 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1514
1515 return value;
1516 }
1517
1518 static void si_emit_shader_ps(struct si_context *sctx)
1519 {
1520 struct si_shader *shader = sctx->queued.named.ps->shader;
1521 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1522
1523 if (!shader)
1524 return;
1525
1526 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1527 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1528 SI_TRACKED_SPI_PS_INPUT_ENA,
1529 shader->ctx_reg.ps.spi_ps_input_ena,
1530 shader->ctx_reg.ps.spi_ps_input_addr);
1531
1532 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1533 SI_TRACKED_SPI_BARYC_CNTL,
1534 shader->ctx_reg.ps.spi_baryc_cntl);
1535 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1536 SI_TRACKED_SPI_PS_IN_CONTROL,
1537 shader->ctx_reg.ps.spi_ps_in_control);
1538
1539 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1540 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1541 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1542 shader->ctx_reg.ps.spi_shader_z_format,
1543 shader->ctx_reg.ps.spi_shader_col_format);
1544
1545 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1546 SI_TRACKED_CB_SHADER_MASK,
1547 shader->ctx_reg.ps.cb_shader_mask);
1548
1549 if (initial_cdw != sctx->gfx_cs->current.cdw)
1550 sctx->context_roll = true;
1551 }
1552
1553 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1554 {
1555 struct tgsi_shader_info *info = &shader->selector->info;
1556 struct si_pm4_state *pm4;
1557 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1558 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1559 uint64_t va;
1560 unsigned input_ena = shader->config.spi_ps_input_ena;
1561
1562 /* we need to enable at least one of them, otherwise we hang the GPU */
1563 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1564 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1565 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1566 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1567 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1568 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1569 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1570 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1571 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1572 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1573 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1574 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1575 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1576 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1577
1578 /* Validate interpolation optimization flags (read as implications). */
1579 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1580 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1581 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1582 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1583 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1584 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1585 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1586 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1587 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1588 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1589 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1590 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1591 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1592 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1593 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1594 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1595 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1596 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1597
1598 /* Validate cases when the optimizations are off (read as implications). */
1599 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1600 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1601 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1602 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1603 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1604 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1605
1606 pm4 = si_get_shader_pm4_state(shader);
1607 if (!pm4)
1608 return;
1609
1610 pm4->atom.emit = si_emit_shader_ps;
1611
1612 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1613 * Possible vaules:
1614 * 0 -> Position = pixel center
1615 * 1 -> Position = pixel centroid
1616 * 2 -> Position = at sample position
1617 *
1618 * From GLSL 4.5 specification, section 7.1:
1619 * "The variable gl_FragCoord is available as an input variable from
1620 * within fragment shaders and it holds the window relative coordinates
1621 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1622 * value can be for any location within the pixel, or one of the
1623 * fragment samples. The use of centroid does not further restrict
1624 * this value to be inside the current primitive."
1625 *
1626 * Meaning that centroid has no effect and we can return anything within
1627 * the pixel. Thus, return the value at sample position, because that's
1628 * the most accurate one shaders can get.
1629 */
1630 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1631
1632 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1633 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1634 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1635
1636 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1637 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1638
1639 /* Ensure that some export memory is always allocated, for two reasons:
1640 *
1641 * 1) Correctness: The hardware ignores the EXEC mask if no export
1642 * memory is allocated, so KILL and alpha test do not work correctly
1643 * without this.
1644 * 2) Performance: Every shader needs at least a NULL export, even when
1645 * it writes no color/depth output. The NULL export instruction
1646 * stalls without this setting.
1647 *
1648 * Don't add this to CB_SHADER_MASK.
1649 *
1650 * GFX10 supports pixel shaders without exports by setting both
1651 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1652 * instructions if any are present.
1653 */
1654 if ((sscreen->info.chip_class <= GFX9 ||
1655 info->uses_kill ||
1656 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1657 !spi_shader_col_format &&
1658 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1659 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1660
1661 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1662 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1663
1664 /* Set interpolation controls. */
1665 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1666 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1667
1668 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1669 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1670 shader->ctx_reg.ps.spi_shader_z_format =
1671 ac_get_spi_shader_z_format(info->writes_z,
1672 info->writes_stencil,
1673 info->writes_samplemask);
1674 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1675 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1676
1677 va = shader->bo->gpu_address;
1678 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1679 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1680 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1681
1682 uint32_t rsrc1 =
1683 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1684 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1685 S_00B028_DX10_CLAMP(1) |
1686 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1687 S_00B028_FLOAT_MODE(shader->config.float_mode);
1688
1689 if (sscreen->info.chip_class < GFX10) {
1690 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1691 }
1692
1693 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1694 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1695 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1696 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1697 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1698 }
1699
1700 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1701 struct si_shader *shader)
1702 {
1703 switch (shader->selector->type) {
1704 case PIPE_SHADER_VERTEX:
1705 if (shader->key.as_ls)
1706 si_shader_ls(sscreen, shader);
1707 else if (shader->key.as_es)
1708 si_shader_es(sscreen, shader);
1709 else if (shader->key.as_ngg)
1710 gfx10_shader_ngg(sscreen, shader);
1711 else
1712 si_shader_vs(sscreen, shader, NULL);
1713 break;
1714 case PIPE_SHADER_TESS_CTRL:
1715 si_shader_hs(sscreen, shader);
1716 break;
1717 case PIPE_SHADER_TESS_EVAL:
1718 if (shader->key.as_es)
1719 si_shader_es(sscreen, shader);
1720 else if (shader->key.as_ngg)
1721 gfx10_shader_ngg(sscreen, shader);
1722 else
1723 si_shader_vs(sscreen, shader, NULL);
1724 break;
1725 case PIPE_SHADER_GEOMETRY:
1726 if (shader->key.as_ngg)
1727 gfx10_shader_ngg(sscreen, shader);
1728 else
1729 si_shader_gs(sscreen, shader);
1730 break;
1731 case PIPE_SHADER_FRAGMENT:
1732 si_shader_ps(sscreen, shader);
1733 break;
1734 default:
1735 assert(0);
1736 }
1737 }
1738
1739 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1740 {
1741 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1742 return sctx->queued.named.dsa->alpha_func;
1743 }
1744
1745 void si_shader_selector_key_vs(struct si_context *sctx,
1746 struct si_shader_selector *vs,
1747 struct si_shader_key *key,
1748 struct si_vs_prolog_bits *prolog_key)
1749 {
1750 if (!sctx->vertex_elements ||
1751 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1752 return;
1753
1754 struct si_vertex_elements *elts = sctx->vertex_elements;
1755
1756 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1757 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1758 prolog_key->unpack_instance_id_from_vertex_id =
1759 sctx->prim_discard_cs_instancing;
1760
1761 /* Prefer a monolithic shader to allow scheduling divisions around
1762 * VBO loads. */
1763 if (prolog_key->instance_divisor_is_fetched)
1764 key->opt.prefer_mono = 1;
1765
1766 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1767 unsigned count_mask = (1 << count) - 1;
1768 unsigned fix = elts->fix_fetch_always & count_mask;
1769 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1770
1771 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1772 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1773 while (mask) {
1774 unsigned i = u_bit_scan(&mask);
1775 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1776 unsigned vbidx = elts->vertex_buffer_index[i];
1777 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1778 unsigned align_mask = (1 << log_hw_load_size) - 1;
1779 if (vb->buffer_offset & align_mask ||
1780 vb->stride & align_mask) {
1781 fix |= 1 << i;
1782 opencode |= 1 << i;
1783 }
1784 }
1785 }
1786
1787 while (fix) {
1788 unsigned i = u_bit_scan(&fix);
1789 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1790 }
1791 key->mono.vs_fetch_opencode = opencode;
1792 }
1793
1794 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1795 struct si_shader_selector *vs,
1796 struct si_shader_key *key)
1797 {
1798 struct si_shader_selector *ps = sctx->ps_shader.cso;
1799
1800 key->opt.clip_disable =
1801 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1802 (vs->info.clipdist_writemask ||
1803 vs->info.writes_clipvertex) &&
1804 !vs->info.culldist_writemask;
1805
1806 /* Find out if PS is disabled. */
1807 bool ps_disabled = true;
1808 if (ps) {
1809 bool ps_modifies_zs = ps->info.uses_kill ||
1810 ps->info.writes_z ||
1811 ps->info.writes_stencil ||
1812 ps->info.writes_samplemask ||
1813 sctx->queued.named.blend->alpha_to_coverage ||
1814 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1815 unsigned ps_colormask = si_get_total_colormask(sctx);
1816
1817 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1818 (!ps_colormask &&
1819 !ps_modifies_zs &&
1820 !ps->info.writes_memory);
1821 }
1822
1823 /* Find out which VS outputs aren't used by the PS. */
1824 uint64_t outputs_written = vs->outputs_written_before_ps;
1825 uint64_t inputs_read = 0;
1826
1827 /* Ignore outputs that are not passed from VS to PS. */
1828 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1829 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1830 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1831
1832 if (!ps_disabled) {
1833 inputs_read = ps->inputs_read;
1834 }
1835
1836 uint64_t linked = outputs_written & inputs_read;
1837
1838 key->opt.kill_outputs = ~linked & outputs_written;
1839 }
1840
1841 /* Compute the key for the hw shader variant */
1842 static inline void si_shader_selector_key(struct pipe_context *ctx,
1843 struct si_shader_selector *sel,
1844 union si_vgt_stages_key stages_key,
1845 struct si_shader_key *key)
1846 {
1847 struct si_context *sctx = (struct si_context *)ctx;
1848
1849 memset(key, 0, sizeof(*key));
1850
1851 switch (sel->type) {
1852 case PIPE_SHADER_VERTEX:
1853 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1854
1855 if (sctx->tes_shader.cso)
1856 key->as_ls = 1;
1857 else if (sctx->gs_shader.cso) {
1858 key->as_es = 1;
1859 key->as_ngg = stages_key.u.ngg;
1860 } else {
1861 key->as_ngg = stages_key.u.ngg;
1862 si_shader_selector_key_hw_vs(sctx, sel, key);
1863
1864 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1865 key->mono.u.vs_export_prim_id = 1;
1866 }
1867 break;
1868 case PIPE_SHADER_TESS_CTRL:
1869 if (sctx->chip_class >= GFX9) {
1870 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1871 key, &key->part.tcs.ls_prolog);
1872 key->part.tcs.ls = sctx->vs_shader.cso;
1873
1874 /* When the LS VGPR fix is needed, monolithic shaders
1875 * can:
1876 * - avoid initializing EXEC in both the LS prolog
1877 * and the LS main part when !vs_needs_prolog
1878 * - remove the fixup for unused input VGPRs
1879 */
1880 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1881
1882 /* The LS output / HS input layout can be communicated
1883 * directly instead of via user SGPRs for merged LS-HS.
1884 * The LS VGPR fix prefers this too.
1885 */
1886 key->opt.prefer_mono = 1;
1887 }
1888
1889 key->part.tcs.epilog.prim_mode =
1890 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1891 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1892 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1893 key->part.tcs.epilog.tes_reads_tess_factors =
1894 sctx->tes_shader.cso->info.reads_tess_factors;
1895
1896 if (sel == sctx->fixed_func_tcs_shader.cso)
1897 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1898 break;
1899 case PIPE_SHADER_TESS_EVAL:
1900 key->as_ngg = stages_key.u.ngg;
1901
1902 if (sctx->gs_shader.cso)
1903 key->as_es = 1;
1904 else {
1905 si_shader_selector_key_hw_vs(sctx, sel, key);
1906
1907 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1908 key->mono.u.vs_export_prim_id = 1;
1909 }
1910 break;
1911 case PIPE_SHADER_GEOMETRY:
1912 if (sctx->chip_class >= GFX9) {
1913 if (sctx->tes_shader.cso) {
1914 key->part.gs.es = sctx->tes_shader.cso;
1915 } else {
1916 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1917 key, &key->part.gs.vs_prolog);
1918 key->part.gs.es = sctx->vs_shader.cso;
1919 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1920 }
1921
1922 key->as_ngg = stages_key.u.ngg;
1923
1924 /* Merged ES-GS can have unbalanced wave usage.
1925 *
1926 * ES threads are per-vertex, while GS threads are
1927 * per-primitive. So without any amplification, there
1928 * are fewer GS threads than ES threads, which can result
1929 * in empty (no-op) GS waves. With too much amplification,
1930 * there are more GS threads than ES threads, which
1931 * can result in empty (no-op) ES waves.
1932 *
1933 * Non-monolithic shaders are implemented by setting EXEC
1934 * at the beginning of shader parts, and don't jump to
1935 * the end if EXEC is 0.
1936 *
1937 * Monolithic shaders use conditional blocks, so they can
1938 * jump and skip empty waves of ES or GS. So set this to
1939 * always use optimized variants, which are monolithic.
1940 */
1941 key->opt.prefer_mono = 1;
1942 }
1943 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1944 break;
1945 case PIPE_SHADER_FRAGMENT: {
1946 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1947 struct si_state_blend *blend = sctx->queued.named.blend;
1948
1949 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1950 sel->info.colors_written == 0x1)
1951 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1952
1953 /* Select the shader color format based on whether
1954 * blending or alpha are needed.
1955 */
1956 key->part.ps.epilog.spi_shader_col_format =
1957 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1958 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1959 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1960 sctx->framebuffer.spi_shader_col_format_blend) |
1961 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1962 sctx->framebuffer.spi_shader_col_format_alpha) |
1963 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1964 sctx->framebuffer.spi_shader_col_format);
1965 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1966
1967 /* The output for dual source blending should have
1968 * the same format as the first output.
1969 */
1970 if (blend->dual_src_blend) {
1971 key->part.ps.epilog.spi_shader_col_format |=
1972 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1973 }
1974
1975 /* If alpha-to-coverage is enabled, we have to export alpha
1976 * even if there is no color buffer.
1977 */
1978 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1979 blend->alpha_to_coverage)
1980 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1981
1982 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1983 * to the range supported by the type if a channel has less
1984 * than 16 bits and the export format is 16_ABGR.
1985 */
1986 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1987 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1988 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1989 }
1990
1991 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1992 if (!key->part.ps.epilog.last_cbuf) {
1993 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1994 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1995 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1996 }
1997
1998 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1999 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
2000
2001 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
2002 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
2003
2004 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
2005 rs->multisample_enable;
2006
2007 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
2008 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
2009 (is_line && rs->line_smooth)) &&
2010 sctx->framebuffer.nr_samples <= 1;
2011 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2012
2013 if (sctx->ps_iter_samples > 1 &&
2014 sel->info.reads_samplemask) {
2015 key->part.ps.prolog.samplemask_log_ps_iter =
2016 util_logbase2(sctx->ps_iter_samples);
2017 }
2018
2019 if (rs->force_persample_interp &&
2020 rs->multisample_enable &&
2021 sctx->framebuffer.nr_samples > 1 &&
2022 sctx->ps_iter_samples > 1) {
2023 key->part.ps.prolog.force_persp_sample_interp =
2024 sel->info.uses_persp_center ||
2025 sel->info.uses_persp_centroid;
2026
2027 key->part.ps.prolog.force_linear_sample_interp =
2028 sel->info.uses_linear_center ||
2029 sel->info.uses_linear_centroid;
2030 } else if (rs->multisample_enable &&
2031 sctx->framebuffer.nr_samples > 1) {
2032 key->part.ps.prolog.bc_optimize_for_persp =
2033 sel->info.uses_persp_center &&
2034 sel->info.uses_persp_centroid;
2035 key->part.ps.prolog.bc_optimize_for_linear =
2036 sel->info.uses_linear_center &&
2037 sel->info.uses_linear_centroid;
2038 } else {
2039 /* Make sure SPI doesn't compute more than 1 pair
2040 * of (i,j), which is the optimization here. */
2041 key->part.ps.prolog.force_persp_center_interp =
2042 sel->info.uses_persp_center +
2043 sel->info.uses_persp_centroid +
2044 sel->info.uses_persp_sample > 1;
2045
2046 key->part.ps.prolog.force_linear_center_interp =
2047 sel->info.uses_linear_center +
2048 sel->info.uses_linear_centroid +
2049 sel->info.uses_linear_sample > 1;
2050
2051 if (sel->info.uses_persp_opcode_interp_sample ||
2052 sel->info.uses_linear_opcode_interp_sample)
2053 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2054 }
2055
2056 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2057
2058 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2059 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2060 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2061 struct pipe_resource *tex = cb0->texture;
2062
2063 /* 1D textures are allocated and used as 2D on GFX9. */
2064 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2065 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2066 (tex->target == PIPE_TEXTURE_1D ||
2067 tex->target == PIPE_TEXTURE_1D_ARRAY);
2068 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2069 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2070 tex->target == PIPE_TEXTURE_CUBE ||
2071 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2072 tex->target == PIPE_TEXTURE_3D;
2073 }
2074 break;
2075 }
2076 default:
2077 assert(0);
2078 }
2079
2080 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2081 memset(&key->opt, 0, sizeof(key->opt));
2082 }
2083
2084 static void si_build_shader_variant(struct si_shader *shader,
2085 int thread_index,
2086 bool low_priority)
2087 {
2088 struct si_shader_selector *sel = shader->selector;
2089 struct si_screen *sscreen = sel->screen;
2090 struct ac_llvm_compiler *compiler;
2091 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2092
2093 if (thread_index >= 0) {
2094 if (low_priority) {
2095 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2096 compiler = &sscreen->compiler_lowp[thread_index];
2097 } else {
2098 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2099 compiler = &sscreen->compiler[thread_index];
2100 }
2101 if (!debug->async)
2102 debug = NULL;
2103 } else {
2104 assert(!low_priority);
2105 compiler = shader->compiler_ctx_state.compiler;
2106 }
2107
2108 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2109 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2110 sel->type);
2111 shader->compilation_failed = true;
2112 return;
2113 }
2114
2115 if (shader->compiler_ctx_state.is_debug_context) {
2116 FILE *f = open_memstream(&shader->shader_log,
2117 &shader->shader_log_size);
2118 if (f) {
2119 si_shader_dump(sscreen, shader, NULL, f, false);
2120 fclose(f);
2121 }
2122 }
2123
2124 si_shader_init_pm4_state(sscreen, shader);
2125 }
2126
2127 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2128 {
2129 struct si_shader *shader = (struct si_shader *)job;
2130
2131 assert(thread_index >= 0);
2132
2133 si_build_shader_variant(shader, thread_index, true);
2134 }
2135
2136 static const struct si_shader_key zeroed;
2137
2138 static bool si_check_missing_main_part(struct si_screen *sscreen,
2139 struct si_shader_selector *sel,
2140 struct si_compiler_ctx_state *compiler_state,
2141 struct si_shader_key *key)
2142 {
2143 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2144
2145 if (!*mainp) {
2146 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2147
2148 if (!main_part)
2149 return false;
2150
2151 /* We can leave the fence as permanently signaled because the
2152 * main part becomes visible globally only after it has been
2153 * compiled. */
2154 util_queue_fence_init(&main_part->ready);
2155
2156 main_part->selector = sel;
2157 main_part->key.as_es = key->as_es;
2158 main_part->key.as_ls = key->as_ls;
2159 main_part->key.as_ngg = key->as_ngg;
2160 main_part->is_monolithic = false;
2161
2162 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2163 main_part, &compiler_state->debug) != 0) {
2164 FREE(main_part);
2165 return false;
2166 }
2167 *mainp = main_part;
2168 }
2169 return true;
2170 }
2171
2172 /**
2173 * Select a shader variant according to the shader key.
2174 *
2175 * \param optimized_or_none If the key describes an optimized shader variant and
2176 * the compilation isn't finished, don't select any
2177 * shader and return an error.
2178 */
2179 int si_shader_select_with_key(struct si_screen *sscreen,
2180 struct si_shader_ctx_state *state,
2181 struct si_compiler_ctx_state *compiler_state,
2182 struct si_shader_key *key,
2183 int thread_index,
2184 bool optimized_or_none)
2185 {
2186 struct si_shader_selector *sel = state->cso;
2187 struct si_shader_selector *previous_stage_sel = NULL;
2188 struct si_shader *current = state->current;
2189 struct si_shader *iter, *shader = NULL;
2190
2191 again:
2192 /* Check if we don't need to change anything.
2193 * This path is also used for most shaders that don't need multiple
2194 * variants, it will cost just a computation of the key and this
2195 * test. */
2196 if (likely(current &&
2197 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2198 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2199 if (current->is_optimized) {
2200 if (optimized_or_none)
2201 return -1;
2202
2203 memset(&key->opt, 0, sizeof(key->opt));
2204 goto current_not_ready;
2205 }
2206
2207 util_queue_fence_wait(&current->ready);
2208 }
2209
2210 return current->compilation_failed ? -1 : 0;
2211 }
2212 current_not_ready:
2213
2214 /* This must be done before the mutex is locked, because async GS
2215 * compilation calls this function too, and therefore must enter
2216 * the mutex first.
2217 *
2218 * Only wait if we are in a draw call. Don't wait if we are
2219 * in a compiler thread.
2220 */
2221 if (thread_index < 0)
2222 util_queue_fence_wait(&sel->ready);
2223
2224 simple_mtx_lock(&sel->mutex);
2225
2226 /* Find the shader variant. */
2227 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2228 /* Don't check the "current" shader. We checked it above. */
2229 if (current != iter &&
2230 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2231 simple_mtx_unlock(&sel->mutex);
2232
2233 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2234 /* If it's an optimized shader and its compilation has
2235 * been started but isn't done, use the unoptimized
2236 * shader so as not to cause a stall due to compilation.
2237 */
2238 if (iter->is_optimized) {
2239 if (optimized_or_none)
2240 return -1;
2241 memset(&key->opt, 0, sizeof(key->opt));
2242 goto again;
2243 }
2244
2245 util_queue_fence_wait(&iter->ready);
2246 }
2247
2248 if (iter->compilation_failed) {
2249 return -1; /* skip the draw call */
2250 }
2251
2252 state->current = iter;
2253 return 0;
2254 }
2255 }
2256
2257 /* Build a new shader. */
2258 shader = CALLOC_STRUCT(si_shader);
2259 if (!shader) {
2260 simple_mtx_unlock(&sel->mutex);
2261 return -ENOMEM;
2262 }
2263
2264 util_queue_fence_init(&shader->ready);
2265
2266 shader->selector = sel;
2267 shader->key = *key;
2268 shader->compiler_ctx_state = *compiler_state;
2269
2270 /* If this is a merged shader, get the first shader's selector. */
2271 if (sscreen->info.chip_class >= GFX9) {
2272 if (sel->type == PIPE_SHADER_TESS_CTRL)
2273 previous_stage_sel = key->part.tcs.ls;
2274 else if (sel->type == PIPE_SHADER_GEOMETRY)
2275 previous_stage_sel = key->part.gs.es;
2276
2277 /* We need to wait for the previous shader. */
2278 if (previous_stage_sel && thread_index < 0)
2279 util_queue_fence_wait(&previous_stage_sel->ready);
2280 }
2281
2282 bool is_pure_monolithic =
2283 sscreen->use_monolithic_shaders ||
2284 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2285
2286 /* Compile the main shader part if it doesn't exist. This can happen
2287 * if the initial guess was wrong.
2288 *
2289 * The prim discard CS doesn't need the main shader part.
2290 */
2291 if (!is_pure_monolithic &&
2292 !key->opt.vs_as_prim_discard_cs) {
2293 bool ok = true;
2294
2295 /* Make sure the main shader part is present. This is needed
2296 * for shaders that can be compiled as VS, LS, or ES, and only
2297 * one of them is compiled at creation.
2298 *
2299 * It is also needed for GS, which can be compiled as non-NGG
2300 * and NGG.
2301 *
2302 * For merged shaders, check that the starting shader's main
2303 * part is present.
2304 */
2305 if (previous_stage_sel) {
2306 struct si_shader_key shader1_key = zeroed;
2307
2308 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2309 shader1_key.as_ls = 1;
2310 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2311 shader1_key.as_es = 1;
2312 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2313 } else {
2314 assert(0);
2315 }
2316
2317 simple_mtx_lock(&previous_stage_sel->mutex);
2318 ok = si_check_missing_main_part(sscreen,
2319 previous_stage_sel,
2320 compiler_state, &shader1_key);
2321 simple_mtx_unlock(&previous_stage_sel->mutex);
2322 }
2323
2324 if (ok) {
2325 ok = si_check_missing_main_part(sscreen, sel,
2326 compiler_state, key);
2327 }
2328
2329 if (!ok) {
2330 FREE(shader);
2331 simple_mtx_unlock(&sel->mutex);
2332 return -ENOMEM; /* skip the draw call */
2333 }
2334 }
2335
2336 /* Keep the reference to the 1st shader of merged shaders, so that
2337 * Gallium can't destroy it before we destroy the 2nd shader.
2338 *
2339 * Set sctx = NULL, because it's unused if we're not releasing
2340 * the shader, and we don't have any sctx here.
2341 */
2342 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2343 previous_stage_sel);
2344
2345 /* Monolithic-only shaders don't make a distinction between optimized
2346 * and unoptimized. */
2347 shader->is_monolithic =
2348 is_pure_monolithic ||
2349 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2350
2351 /* The prim discard CS is always optimized. */
2352 shader->is_optimized =
2353 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2354 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2355
2356 /* If it's an optimized shader, compile it asynchronously. */
2357 if (shader->is_optimized && thread_index < 0) {
2358 /* Compile it asynchronously. */
2359 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2360 shader, &shader->ready,
2361 si_build_shader_variant_low_priority, NULL,
2362 0);
2363
2364 /* Add only after the ready fence was reset, to guard against a
2365 * race with si_bind_XX_shader. */
2366 if (!sel->last_variant) {
2367 sel->first_variant = shader;
2368 sel->last_variant = shader;
2369 } else {
2370 sel->last_variant->next_variant = shader;
2371 sel->last_variant = shader;
2372 }
2373
2374 /* Use the default (unoptimized) shader for now. */
2375 memset(&key->opt, 0, sizeof(key->opt));
2376 simple_mtx_unlock(&sel->mutex);
2377
2378 if (sscreen->options.sync_compile)
2379 util_queue_fence_wait(&shader->ready);
2380
2381 if (optimized_or_none)
2382 return -1;
2383 goto again;
2384 }
2385
2386 /* Reset the fence before adding to the variant list. */
2387 util_queue_fence_reset(&shader->ready);
2388
2389 if (!sel->last_variant) {
2390 sel->first_variant = shader;
2391 sel->last_variant = shader;
2392 } else {
2393 sel->last_variant->next_variant = shader;
2394 sel->last_variant = shader;
2395 }
2396
2397 simple_mtx_unlock(&sel->mutex);
2398
2399 assert(!shader->is_optimized);
2400 si_build_shader_variant(shader, thread_index, false);
2401
2402 util_queue_fence_signal(&shader->ready);
2403
2404 if (!shader->compilation_failed)
2405 state->current = shader;
2406
2407 return shader->compilation_failed ? -1 : 0;
2408 }
2409
2410 static int si_shader_select(struct pipe_context *ctx,
2411 struct si_shader_ctx_state *state,
2412 union si_vgt_stages_key stages_key,
2413 struct si_compiler_ctx_state *compiler_state)
2414 {
2415 struct si_context *sctx = (struct si_context *)ctx;
2416 struct si_shader_key key;
2417
2418 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2419 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2420 &key, -1, false);
2421 }
2422
2423 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2424 bool streamout,
2425 struct si_shader_key *key)
2426 {
2427 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2428
2429 switch (info->processor) {
2430 case PIPE_SHADER_VERTEX:
2431 switch (next_shader) {
2432 case PIPE_SHADER_GEOMETRY:
2433 key->as_es = 1;
2434 break;
2435 case PIPE_SHADER_TESS_CTRL:
2436 case PIPE_SHADER_TESS_EVAL:
2437 key->as_ls = 1;
2438 break;
2439 default:
2440 /* If POSITION isn't written, it can only be a HW VS
2441 * if streamout is used. If streamout isn't used,
2442 * assume that it's a HW LS. (the next shader is TCS)
2443 * This heuristic is needed for separate shader objects.
2444 */
2445 if (!info->writes_position && !streamout)
2446 key->as_ls = 1;
2447 }
2448 break;
2449
2450 case PIPE_SHADER_TESS_EVAL:
2451 if (next_shader == PIPE_SHADER_GEOMETRY ||
2452 !info->writes_position)
2453 key->as_es = 1;
2454 break;
2455 }
2456 }
2457
2458 /**
2459 * Compile the main shader part or the monolithic shader as part of
2460 * si_shader_selector initialization. Since it can be done asynchronously,
2461 * there is no way to report compile failures to applications.
2462 */
2463 static void si_init_shader_selector_async(void *job, int thread_index)
2464 {
2465 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2466 struct si_screen *sscreen = sel->screen;
2467 struct ac_llvm_compiler *compiler;
2468 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2469
2470 assert(!debug->debug_message || debug->async);
2471 assert(thread_index >= 0);
2472 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2473 compiler = &sscreen->compiler[thread_index];
2474
2475 if (sel->nir)
2476 si_lower_nir(sel->screen, sel->nir);
2477
2478 /* Compile the main shader part for use with a prolog and/or epilog.
2479 * If this fails, the driver will try to compile a monolithic shader
2480 * on demand.
2481 */
2482 if (!sscreen->use_monolithic_shaders) {
2483 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2484 void *ir_binary = NULL;
2485
2486 if (!shader) {
2487 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2488 return;
2489 }
2490
2491 /* We can leave the fence signaled because use of the default
2492 * main part is guarded by the selector's ready fence. */
2493 util_queue_fence_init(&shader->ready);
2494
2495 shader->selector = sel;
2496 shader->is_monolithic = false;
2497 si_parse_next_shader_property(&sel->info,
2498 sel->so.num_outputs != 0,
2499 &shader->key);
2500
2501 if (sscreen->use_ngg &&
2502 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2503 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2504 sel->type == PIPE_SHADER_TESS_EVAL ||
2505 sel->type == PIPE_SHADER_GEOMETRY))
2506 shader->key.as_ngg = 1;
2507
2508 if (sel->tokens || sel->nir) {
2509 ir_binary = si_get_ir_binary(sel, shader->key.as_ngg,
2510 shader->key.as_es);
2511 }
2512
2513 /* Try to load the shader from the shader cache. */
2514 simple_mtx_lock(&sscreen->shader_cache_mutex);
2515
2516 if (ir_binary &&
2517 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2518 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2519 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2520 } else {
2521 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2522
2523 /* Compile the shader if it hasn't been loaded from the cache. */
2524 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2525 debug) != 0) {
2526 FREE(shader);
2527 FREE(ir_binary);
2528 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2529 return;
2530 }
2531
2532 if (ir_binary) {
2533 simple_mtx_lock(&sscreen->shader_cache_mutex);
2534 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2535 FREE(ir_binary);
2536 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2537 }
2538 }
2539
2540 *si_get_main_shader_part(sel, &shader->key) = shader;
2541
2542 /* Unset "outputs_written" flags for outputs converted to
2543 * DEFAULT_VAL, so that later inter-shader optimizations don't
2544 * try to eliminate outputs that don't exist in the final
2545 * shader.
2546 *
2547 * This is only done if non-monolithic shaders are enabled.
2548 */
2549 if ((sel->type == PIPE_SHADER_VERTEX ||
2550 sel->type == PIPE_SHADER_TESS_EVAL) &&
2551 !shader->key.as_ls &&
2552 !shader->key.as_es) {
2553 unsigned i;
2554
2555 for (i = 0; i < sel->info.num_outputs; i++) {
2556 unsigned offset = shader->info.vs_output_param_offset[i];
2557
2558 if (offset <= AC_EXP_PARAM_OFFSET_31)
2559 continue;
2560
2561 unsigned name = sel->info.output_semantic_name[i];
2562 unsigned index = sel->info.output_semantic_index[i];
2563 unsigned id;
2564
2565 switch (name) {
2566 case TGSI_SEMANTIC_GENERIC:
2567 /* don't process indices the function can't handle */
2568 if (index >= SI_MAX_IO_GENERIC)
2569 break;
2570 /* fall through */
2571 default:
2572 id = si_shader_io_get_unique_index(name, index, true);
2573 sel->outputs_written_before_ps &= ~(1ull << id);
2574 break;
2575 case TGSI_SEMANTIC_POSITION: /* ignore these */
2576 case TGSI_SEMANTIC_PSIZE:
2577 case TGSI_SEMANTIC_CLIPVERTEX:
2578 case TGSI_SEMANTIC_EDGEFLAG:
2579 break;
2580 }
2581 }
2582 }
2583 }
2584
2585 /* The GS copy shader is always pre-compiled. */
2586 if (sel->type == PIPE_SHADER_GEOMETRY &&
2587 (!sscreen->use_ngg ||
2588 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2589 sel->tess_turns_off_ngg)) {
2590 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2591 if (!sel->gs_copy_shader) {
2592 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2593 return;
2594 }
2595
2596 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2597 }
2598 }
2599
2600 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2601 struct util_queue_fence *ready_fence,
2602 struct si_compiler_ctx_state *compiler_ctx_state,
2603 void *job, util_queue_execute_func execute)
2604 {
2605 util_queue_fence_init(ready_fence);
2606
2607 struct util_async_debug_callback async_debug;
2608 bool debug =
2609 (sctx->debug.debug_message && !sctx->debug.async) ||
2610 sctx->is_debug ||
2611 si_can_dump_shader(sctx->screen, processor);
2612
2613 if (debug) {
2614 u_async_debug_init(&async_debug);
2615 compiler_ctx_state->debug = async_debug.base;
2616 }
2617
2618 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2619 ready_fence, execute, NULL, 0);
2620
2621 if (debug) {
2622 util_queue_fence_wait(ready_fence);
2623 u_async_debug_drain(&async_debug, &sctx->debug);
2624 u_async_debug_cleanup(&async_debug);
2625 }
2626
2627 if (sctx->screen->options.sync_compile)
2628 util_queue_fence_wait(ready_fence);
2629 }
2630
2631 /* Return descriptor slot usage masks from the given shader info. */
2632 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2633 uint32_t *const_and_shader_buffers,
2634 uint64_t *samplers_and_images)
2635 {
2636 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2637
2638 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2639 num_constbufs = util_last_bit(info->const_buffers_declared);
2640 /* two 8-byte images share one 16-byte slot */
2641 num_images = align(util_last_bit(info->images_declared), 2);
2642 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2643 num_samplers = util_last_bit(info->samplers_declared);
2644
2645 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2646 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2647 *const_and_shader_buffers =
2648 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2649
2650 /* The layout is:
2651 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2652 * - image[last] ... image[0] go to [31-last .. 31]
2653 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2654 *
2655 * FMASKs for images are placed separately, because MSAA images are rare,
2656 * and so we can benefit from a better cache hit rate if we keep image
2657 * descriptors together.
2658 */
2659 if (num_msaa_images)
2660 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2661
2662 start = si_get_image_slot(num_images - 1) / 2;
2663 *samplers_and_images =
2664 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2665 }
2666
2667 static void *si_create_shader_selector(struct pipe_context *ctx,
2668 const struct pipe_shader_state *state)
2669 {
2670 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2671 struct si_context *sctx = (struct si_context*)ctx;
2672 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2673 int i;
2674
2675 if (!sel)
2676 return NULL;
2677
2678 pipe_reference_init(&sel->reference, 1);
2679 sel->screen = sscreen;
2680 sel->compiler_ctx_state.debug = sctx->debug;
2681 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2682
2683 sel->so = state->stream_output;
2684
2685 if (state->type == PIPE_SHADER_IR_TGSI &&
2686 !sscreen->options.enable_nir) {
2687 sel->tokens = tgsi_dup_tokens(state->tokens);
2688 if (!sel->tokens) {
2689 FREE(sel);
2690 return NULL;
2691 }
2692
2693 tgsi_scan_shader(state->tokens, &sel->info);
2694 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2695
2696 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2697 if (sel->info.uses_persp_opcode_interp_centroid)
2698 sel->info.uses_persp_centroid = true;
2699
2700 if (sel->info.uses_linear_opcode_interp_centroid)
2701 sel->info.uses_linear_centroid = true;
2702
2703 if (sel->info.uses_persp_opcode_interp_offset ||
2704 sel->info.uses_persp_opcode_interp_sample)
2705 sel->info.uses_persp_center = true;
2706
2707 if (sel->info.uses_linear_opcode_interp_offset ||
2708 sel->info.uses_linear_opcode_interp_sample)
2709 sel->info.uses_linear_center = true;
2710 } else {
2711 if (state->type == PIPE_SHADER_IR_TGSI) {
2712 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2713 } else {
2714 assert(state->type == PIPE_SHADER_IR_NIR);
2715 sel->nir = state->ir.nir;
2716 }
2717
2718 si_nir_lower_ps_inputs(sel->nir);
2719 si_nir_opts(sel->nir);
2720 si_nir_scan_shader(sel->nir, &sel->info);
2721 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2722 }
2723
2724 sel->type = sel->info.processor;
2725 p_atomic_inc(&sscreen->num_shaders_created);
2726 si_get_active_slot_masks(&sel->info,
2727 &sel->active_const_and_shader_buffers,
2728 &sel->active_samplers_and_images);
2729
2730 /* Record which streamout buffers are enabled. */
2731 for (i = 0; i < sel->so.num_outputs; i++) {
2732 sel->enabled_streamout_buffer_mask |=
2733 (1 << sel->so.output[i].output_buffer) <<
2734 (sel->so.output[i].stream * 4);
2735 }
2736
2737 /* The prolog is a no-op if there are no inputs. */
2738 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2739 sel->info.num_inputs &&
2740 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2741
2742 sel->force_correct_derivs_after_kill =
2743 sel->type == PIPE_SHADER_FRAGMENT &&
2744 sel->info.uses_derivatives &&
2745 sel->info.uses_kill &&
2746 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2747
2748 sel->prim_discard_cs_allowed =
2749 sel->type == PIPE_SHADER_VERTEX &&
2750 !sel->info.uses_bindless_images &&
2751 !sel->info.uses_bindless_samplers &&
2752 !sel->info.writes_memory &&
2753 !sel->info.writes_viewport_index &&
2754 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2755 !sel->so.num_outputs;
2756
2757 switch (sel->type) {
2758 case PIPE_SHADER_GEOMETRY:
2759 sel->gs_output_prim =
2760 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2761
2762 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2763 sel->rast_prim = sel->gs_output_prim;
2764 if (util_rast_prim_is_triangles(sel->rast_prim))
2765 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2766
2767 sel->gs_max_out_vertices =
2768 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2769 sel->gs_num_invocations =
2770 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2771 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2772 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2773 sel->gs_max_out_vertices;
2774
2775 sel->max_gs_stream = 0;
2776 for (i = 0; i < sel->so.num_outputs; i++)
2777 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2778 sel->so.output[i].stream);
2779
2780 sel->gs_input_verts_per_prim =
2781 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2782
2783 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2784 sel->tess_turns_off_ngg =
2785 (sscreen->info.family == CHIP_NAVI10 ||
2786 sscreen->info.family == CHIP_NAVI12 ||
2787 sscreen->info.family == CHIP_NAVI14) &&
2788 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2789 break;
2790
2791 case PIPE_SHADER_TESS_CTRL:
2792 /* Always reserve space for these. */
2793 sel->patch_outputs_written |=
2794 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2795 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2796 /* fall through */
2797 case PIPE_SHADER_VERTEX:
2798 case PIPE_SHADER_TESS_EVAL:
2799 for (i = 0; i < sel->info.num_outputs; i++) {
2800 unsigned name = sel->info.output_semantic_name[i];
2801 unsigned index = sel->info.output_semantic_index[i];
2802
2803 switch (name) {
2804 case TGSI_SEMANTIC_TESSINNER:
2805 case TGSI_SEMANTIC_TESSOUTER:
2806 case TGSI_SEMANTIC_PATCH:
2807 sel->patch_outputs_written |=
2808 1ull << si_shader_io_get_unique_index_patch(name, index);
2809 break;
2810
2811 case TGSI_SEMANTIC_GENERIC:
2812 /* don't process indices the function can't handle */
2813 if (index >= SI_MAX_IO_GENERIC)
2814 break;
2815 /* fall through */
2816 default:
2817 sel->outputs_written |=
2818 1ull << si_shader_io_get_unique_index(name, index, false);
2819 sel->outputs_written_before_ps |=
2820 1ull << si_shader_io_get_unique_index(name, index, true);
2821 break;
2822 case TGSI_SEMANTIC_EDGEFLAG:
2823 break;
2824 }
2825 }
2826 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2827 sel->lshs_vertex_stride = sel->esgs_itemsize;
2828
2829 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2830 * will start on a different bank. (except for the maximum 32*16).
2831 */
2832 if (sel->lshs_vertex_stride < 32*16)
2833 sel->lshs_vertex_stride += 4;
2834
2835 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2836 * conflicts, i.e. each vertex will start at a different bank.
2837 */
2838 if (sctx->chip_class >= GFX9)
2839 sel->esgs_itemsize += 4;
2840
2841 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2842
2843 /* Only for TES: */
2844 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2845 sel->rast_prim = PIPE_PRIM_POINTS;
2846 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2847 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2848 else
2849 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2850 break;
2851
2852 case PIPE_SHADER_FRAGMENT:
2853 for (i = 0; i < sel->info.num_inputs; i++) {
2854 unsigned name = sel->info.input_semantic_name[i];
2855 unsigned index = sel->info.input_semantic_index[i];
2856
2857 switch (name) {
2858 case TGSI_SEMANTIC_GENERIC:
2859 /* don't process indices the function can't handle */
2860 if (index >= SI_MAX_IO_GENERIC)
2861 break;
2862 /* fall through */
2863 default:
2864 sel->inputs_read |=
2865 1ull << si_shader_io_get_unique_index(name, index, true);
2866 break;
2867 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2868 break;
2869 }
2870 }
2871
2872 for (i = 0; i < 8; i++)
2873 if (sel->info.colors_written & (1 << i))
2874 sel->colors_written_4bit |= 0xf << (4 * i);
2875
2876 for (i = 0; i < sel->info.num_inputs; i++) {
2877 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2878 int index = sel->info.input_semantic_index[i];
2879 sel->color_attr_index[index] = i;
2880 }
2881 }
2882 break;
2883 default:;
2884 }
2885
2886 /* PA_CL_VS_OUT_CNTL */
2887 if (sctx->chip_class <= GFX9)
2888 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2889
2890 sel->clipdist_mask = sel->info.writes_clipvertex ?
2891 SIX_BITS : sel->info.clipdist_writemask;
2892 sel->culldist_mask = sel->info.culldist_writemask <<
2893 sel->info.num_written_clipdistance;
2894
2895 /* DB_SHADER_CONTROL */
2896 sel->db_shader_control =
2897 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2898 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2899 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2900 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2901
2902 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2903 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2904 sel->db_shader_control |=
2905 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2906 break;
2907 case TGSI_FS_DEPTH_LAYOUT_LESS:
2908 sel->db_shader_control |=
2909 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2910 break;
2911 }
2912
2913 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2914 *
2915 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2916 * --|-----------|------------|------------|--------------------|-------------------|-------------
2917 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2918 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2919 * 2 | false | true | n/a | LateZ | 1 | 0
2920 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2921 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2922 *
2923 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2924 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2925 *
2926 * Don't use ReZ without profiling !!!
2927 *
2928 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2929 * shaders.
2930 */
2931 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2932 /* Cases 3, 4. */
2933 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2934 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2935 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2936 } else if (sel->info.writes_memory) {
2937 /* Case 2. */
2938 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2939 S_02880C_EXEC_ON_HIER_FAIL(1);
2940 } else {
2941 /* Case 1. */
2942 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2943 }
2944
2945 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2946 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2947
2948 (void) simple_mtx_init(&sel->mutex, mtx_plain);
2949
2950 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2951 &sel->compiler_ctx_state, sel,
2952 si_init_shader_selector_async);
2953 return sel;
2954 }
2955
2956 static void si_update_streamout_state(struct si_context *sctx)
2957 {
2958 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2959
2960 if (!shader_with_so)
2961 return;
2962
2963 sctx->streamout.enabled_stream_buffers_mask =
2964 shader_with_so->enabled_streamout_buffer_mask;
2965 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2966 }
2967
2968 static void si_update_clip_regs(struct si_context *sctx,
2969 struct si_shader_selector *old_hw_vs,
2970 struct si_shader *old_hw_vs_variant,
2971 struct si_shader_selector *next_hw_vs,
2972 struct si_shader *next_hw_vs_variant)
2973 {
2974 if (next_hw_vs &&
2975 (!old_hw_vs ||
2976 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2977 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2978 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2979 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2980 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2981 !old_hw_vs_variant ||
2982 !next_hw_vs_variant ||
2983 old_hw_vs_variant->key.opt.clip_disable !=
2984 next_hw_vs_variant->key.opt.clip_disable))
2985 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2986 }
2987
2988 static void si_update_common_shader_state(struct si_context *sctx)
2989 {
2990 sctx->uses_bindless_samplers =
2991 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2992 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2993 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2994 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2995 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2996 sctx->uses_bindless_images =
2997 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2998 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2999 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
3000 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3001 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3002 sctx->do_update_shaders = true;
3003 }
3004
3005 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3006 {
3007 struct si_context *sctx = (struct si_context *)ctx;
3008 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3009 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3010 struct si_shader_selector *sel = state;
3011
3012 if (sctx->vs_shader.cso == sel)
3013 return;
3014
3015 sctx->vs_shader.cso = sel;
3016 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3017 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3018
3019 if (si_update_ngg(sctx))
3020 si_shader_change_notify(sctx);
3021
3022 si_update_common_shader_state(sctx);
3023 si_update_vs_viewport_state(sctx);
3024 si_set_active_descriptors_for_shader(sctx, sel);
3025 si_update_streamout_state(sctx);
3026 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3027 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3028 }
3029
3030 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3031 {
3032 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3033 (sctx->tes_shader.cso &&
3034 sctx->tes_shader.cso->info.uses_primid) ||
3035 (sctx->tcs_shader.cso &&
3036 sctx->tcs_shader.cso->info.uses_primid) ||
3037 (sctx->gs_shader.cso &&
3038 sctx->gs_shader.cso->info.uses_primid) ||
3039 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3040 sctx->ps_shader.cso->info.uses_primid);
3041 }
3042
3043 bool si_update_ngg(struct si_context *sctx)
3044 {
3045 if (!sctx->screen->use_ngg) {
3046 assert(!sctx->ngg);
3047 return false;
3048 }
3049
3050 bool new_ngg = true;
3051
3052 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3053 sctx->gs_shader.cso->tess_turns_off_ngg) {
3054 new_ngg = false;
3055 } else if (!sctx->screen->use_ngg_streamout) {
3056 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3057
3058 if ((last && last->so.num_outputs) ||
3059 sctx->streamout.prims_gen_query_enabled)
3060 new_ngg = false;
3061 }
3062
3063 if (new_ngg != sctx->ngg) {
3064 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3065 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3066 * pointers are set.
3067 */
3068 if ((sctx->family == CHIP_NAVI10 ||
3069 sctx->family == CHIP_NAVI12 ||
3070 sctx->family == CHIP_NAVI14) &&
3071 !new_ngg)
3072 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3073
3074 sctx->ngg = new_ngg;
3075 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3076 return true;
3077 }
3078 return false;
3079 }
3080
3081 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3082 {
3083 struct si_context *sctx = (struct si_context *)ctx;
3084 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3085 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3086 struct si_shader_selector *sel = state;
3087 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3088 bool ngg_changed;
3089
3090 if (sctx->gs_shader.cso == sel)
3091 return;
3092
3093 sctx->gs_shader.cso = sel;
3094 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3095 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3096
3097 si_update_common_shader_state(sctx);
3098 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3099
3100 ngg_changed = si_update_ngg(sctx);
3101 if (ngg_changed || enable_changed)
3102 si_shader_change_notify(sctx);
3103 if (enable_changed) {
3104 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3105 si_update_tess_uses_prim_id(sctx);
3106 }
3107 si_update_vs_viewport_state(sctx);
3108 si_set_active_descriptors_for_shader(sctx, sel);
3109 si_update_streamout_state(sctx);
3110 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3111 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3112 }
3113
3114 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3115 {
3116 struct si_context *sctx = (struct si_context *)ctx;
3117 struct si_shader_selector *sel = state;
3118 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3119
3120 if (sctx->tcs_shader.cso == sel)
3121 return;
3122
3123 sctx->tcs_shader.cso = sel;
3124 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3125 si_update_tess_uses_prim_id(sctx);
3126
3127 si_update_common_shader_state(sctx);
3128
3129 if (enable_changed)
3130 sctx->last_tcs = NULL; /* invalidate derived tess state */
3131
3132 si_set_active_descriptors_for_shader(sctx, sel);
3133 }
3134
3135 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3136 {
3137 struct si_context *sctx = (struct si_context *)ctx;
3138 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3139 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3140 struct si_shader_selector *sel = state;
3141 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3142
3143 if (sctx->tes_shader.cso == sel)
3144 return;
3145
3146 sctx->tes_shader.cso = sel;
3147 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3148 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3149 si_update_tess_uses_prim_id(sctx);
3150
3151 si_update_common_shader_state(sctx);
3152 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3153
3154 bool ngg_changed = si_update_ngg(sctx);
3155 if (ngg_changed || enable_changed)
3156 si_shader_change_notify(sctx);
3157 if (enable_changed)
3158 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3159 si_update_vs_viewport_state(sctx);
3160 si_set_active_descriptors_for_shader(sctx, sel);
3161 si_update_streamout_state(sctx);
3162 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3163 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3164 }
3165
3166 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3167 {
3168 struct si_context *sctx = (struct si_context *)ctx;
3169 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3170 struct si_shader_selector *sel = state;
3171
3172 /* skip if supplied shader is one already in use */
3173 if (old_sel == sel)
3174 return;
3175
3176 sctx->ps_shader.cso = sel;
3177 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3178
3179 si_update_common_shader_state(sctx);
3180 if (sel) {
3181 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3182 si_update_tess_uses_prim_id(sctx);
3183
3184 if (!old_sel ||
3185 old_sel->info.colors_written != sel->info.colors_written)
3186 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3187
3188 if (sctx->screen->has_out_of_order_rast &&
3189 (!old_sel ||
3190 old_sel->info.writes_memory != sel->info.writes_memory ||
3191 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3192 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3193 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3194 }
3195 si_set_active_descriptors_for_shader(sctx, sel);
3196 si_update_ps_colorbuf0_slot(sctx);
3197 }
3198
3199 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3200 {
3201 if (shader->is_optimized) {
3202 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3203 &shader->ready);
3204 }
3205
3206 util_queue_fence_destroy(&shader->ready);
3207
3208 if (shader->pm4) {
3209 /* If destroyed shaders were not unbound, the next compiled
3210 * shader variant could get the same pointer address and so
3211 * binding it to the same shader stage would be considered
3212 * a no-op, causing random behavior.
3213 */
3214 switch (shader->selector->type) {
3215 case PIPE_SHADER_VERTEX:
3216 if (shader->key.as_ls) {
3217 assert(sctx->chip_class <= GFX8);
3218 si_pm4_delete_state(sctx, ls, shader->pm4);
3219 } else if (shader->key.as_es) {
3220 assert(sctx->chip_class <= GFX8);
3221 si_pm4_delete_state(sctx, es, shader->pm4);
3222 } else if (shader->key.as_ngg) {
3223 si_pm4_delete_state(sctx, gs, shader->pm4);
3224 } else {
3225 si_pm4_delete_state(sctx, vs, shader->pm4);
3226 }
3227 break;
3228 case PIPE_SHADER_TESS_CTRL:
3229 si_pm4_delete_state(sctx, hs, shader->pm4);
3230 break;
3231 case PIPE_SHADER_TESS_EVAL:
3232 if (shader->key.as_es) {
3233 assert(sctx->chip_class <= GFX8);
3234 si_pm4_delete_state(sctx, es, shader->pm4);
3235 } else if (shader->key.as_ngg) {
3236 si_pm4_delete_state(sctx, gs, shader->pm4);
3237 } else {
3238 si_pm4_delete_state(sctx, vs, shader->pm4);
3239 }
3240 break;
3241 case PIPE_SHADER_GEOMETRY:
3242 if (shader->is_gs_copy_shader)
3243 si_pm4_delete_state(sctx, vs, shader->pm4);
3244 else
3245 si_pm4_delete_state(sctx, gs, shader->pm4);
3246 break;
3247 case PIPE_SHADER_FRAGMENT:
3248 si_pm4_delete_state(sctx, ps, shader->pm4);
3249 break;
3250 default:;
3251 }
3252 }
3253
3254 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3255 si_shader_destroy(shader);
3256 free(shader);
3257 }
3258
3259 void si_destroy_shader_selector(struct si_context *sctx,
3260 struct si_shader_selector *sel)
3261 {
3262 struct si_shader *p = sel->first_variant, *c;
3263 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3264 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3265 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3266 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3267 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3268 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3269 };
3270
3271 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3272
3273 if (current_shader[sel->type]->cso == sel) {
3274 current_shader[sel->type]->cso = NULL;
3275 current_shader[sel->type]->current = NULL;
3276 }
3277
3278 while (p) {
3279 c = p->next_variant;
3280 si_delete_shader(sctx, p);
3281 p = c;
3282 }
3283
3284 if (sel->main_shader_part)
3285 si_delete_shader(sctx, sel->main_shader_part);
3286 if (sel->main_shader_part_ls)
3287 si_delete_shader(sctx, sel->main_shader_part_ls);
3288 if (sel->main_shader_part_es)
3289 si_delete_shader(sctx, sel->main_shader_part_es);
3290 if (sel->main_shader_part_ngg)
3291 si_delete_shader(sctx, sel->main_shader_part_ngg);
3292 if (sel->gs_copy_shader)
3293 si_delete_shader(sctx, sel->gs_copy_shader);
3294
3295 util_queue_fence_destroy(&sel->ready);
3296 simple_mtx_destroy(&sel->mutex);
3297 free(sel->tokens);
3298 ralloc_free(sel->nir);
3299 free(sel);
3300 }
3301
3302 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3303 {
3304 struct si_context *sctx = (struct si_context *)ctx;
3305 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3306
3307 si_shader_selector_reference(sctx, &sel, NULL);
3308 }
3309
3310 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3311 struct si_shader *vs, unsigned name,
3312 unsigned index, unsigned interpolate)
3313 {
3314 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3315 unsigned j, offset, ps_input_cntl = 0;
3316
3317 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3318 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3319 name == TGSI_SEMANTIC_PRIMID)
3320 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3321
3322 if (name == TGSI_SEMANTIC_PCOORD ||
3323 (name == TGSI_SEMANTIC_TEXCOORD &&
3324 sctx->sprite_coord_enable & (1 << index))) {
3325 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3326 }
3327
3328 for (j = 0; j < vsinfo->num_outputs; j++) {
3329 if (name == vsinfo->output_semantic_name[j] &&
3330 index == vsinfo->output_semantic_index[j]) {
3331 offset = vs->info.vs_output_param_offset[j];
3332
3333 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3334 /* The input is loaded from parameter memory. */
3335 ps_input_cntl |= S_028644_OFFSET(offset);
3336 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3337 if (offset == AC_EXP_PARAM_UNDEFINED) {
3338 /* This can happen with depth-only rendering. */
3339 offset = 0;
3340 } else {
3341 /* The input is a DEFAULT_VAL constant. */
3342 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3343 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3344 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3345 }
3346
3347 ps_input_cntl = S_028644_OFFSET(0x20) |
3348 S_028644_DEFAULT_VAL(offset);
3349 }
3350 break;
3351 }
3352 }
3353
3354 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3355 /* PrimID is written after the last output when HW VS is used. */
3356 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3357 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3358 /* No corresponding output found, load defaults into input.
3359 * Don't set any other bits.
3360 * (FLAT_SHADE=1 completely changes behavior) */
3361 ps_input_cntl = S_028644_OFFSET(0x20);
3362 /* D3D 9 behaviour. GL is undefined */
3363 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3364 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3365 }
3366 return ps_input_cntl;
3367 }
3368
3369 static void si_emit_spi_map(struct si_context *sctx)
3370 {
3371 struct si_shader *ps = sctx->ps_shader.current;
3372 struct si_shader *vs = si_get_vs_state(sctx);
3373 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3374 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3375 unsigned spi_ps_input_cntl[32];
3376
3377 if (!ps || !ps->selector->info.num_inputs)
3378 return;
3379
3380 num_interp = si_get_ps_num_interp(ps);
3381 assert(num_interp > 0);
3382
3383 for (i = 0; i < psinfo->num_inputs; i++) {
3384 unsigned name = psinfo->input_semantic_name[i];
3385 unsigned index = psinfo->input_semantic_index[i];
3386 unsigned interpolate = psinfo->input_interpolate[i];
3387
3388 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3389 index, interpolate);
3390
3391 if (name == TGSI_SEMANTIC_COLOR) {
3392 assert(index < ARRAY_SIZE(bcol_interp));
3393 bcol_interp[index] = interpolate;
3394 }
3395 }
3396
3397 if (ps->key.part.ps.prolog.color_two_side) {
3398 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3399
3400 for (i = 0; i < 2; i++) {
3401 if (!(psinfo->colors_read & (0xf << (i * 4))))
3402 continue;
3403
3404 spi_ps_input_cntl[num_written++] =
3405 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3406
3407 }
3408 }
3409 assert(num_interp == num_written);
3410
3411 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3412 /* Dota 2: Only ~16% of SPI map updates set different values. */
3413 /* Talos: Only ~9% of SPI map updates set different values. */
3414 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3415 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3416 spi_ps_input_cntl,
3417 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3418
3419 if (initial_cdw != sctx->gfx_cs->current.cdw)
3420 sctx->context_roll = true;
3421 }
3422
3423 /**
3424 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3425 */
3426 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3427 {
3428 if (sctx->init_config_has_vgt_flush)
3429 return;
3430
3431 /* Done by Vulkan before VGT_FLUSH. */
3432 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3433 si_pm4_cmd_add(sctx->init_config,
3434 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3435 si_pm4_cmd_end(sctx->init_config, false);
3436
3437 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3438 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3439 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3440 si_pm4_cmd_end(sctx->init_config, false);
3441 sctx->init_config_has_vgt_flush = true;
3442 }
3443
3444 /* Initialize state related to ESGS / GSVS ring buffers */
3445 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3446 {
3447 struct si_shader_selector *es =
3448 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3449 struct si_shader_selector *gs = sctx->gs_shader.cso;
3450 struct si_pm4_state *pm4;
3451
3452 /* Chip constants. */
3453 unsigned num_se = sctx->screen->info.max_se;
3454 unsigned wave_size = 64;
3455 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3456 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3457 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3458 */
3459 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3460 unsigned alignment = 256 * num_se;
3461 /* The maximum size is 63.999 MB per SE. */
3462 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3463
3464 /* Calculate the minimum size. */
3465 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3466 wave_size, alignment);
3467
3468 /* These are recommended sizes, not minimum sizes. */
3469 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3470 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3471 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3472 gs->max_gsvs_emit_size;
3473
3474 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3475 esgs_ring_size = align(esgs_ring_size, alignment);
3476 gsvs_ring_size = align(gsvs_ring_size, alignment);
3477
3478 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3479 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3480
3481 /* Some rings don't have to be allocated if shaders don't use them.
3482 * (e.g. no varyings between ES and GS or GS and VS)
3483 *
3484 * GFX9 doesn't have the ESGS ring.
3485 */
3486 bool update_esgs = sctx->chip_class <= GFX8 &&
3487 esgs_ring_size &&
3488 (!sctx->esgs_ring ||
3489 sctx->esgs_ring->width0 < esgs_ring_size);
3490 bool update_gsvs = gsvs_ring_size &&
3491 (!sctx->gsvs_ring ||
3492 sctx->gsvs_ring->width0 < gsvs_ring_size);
3493
3494 if (!update_esgs && !update_gsvs)
3495 return true;
3496
3497 if (update_esgs) {
3498 pipe_resource_reference(&sctx->esgs_ring, NULL);
3499 sctx->esgs_ring =
3500 pipe_aligned_buffer_create(sctx->b.screen,
3501 SI_RESOURCE_FLAG_UNMAPPABLE,
3502 PIPE_USAGE_DEFAULT,
3503 esgs_ring_size,
3504 sctx->screen->info.pte_fragment_size);
3505 if (!sctx->esgs_ring)
3506 return false;
3507 }
3508
3509 if (update_gsvs) {
3510 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3511 sctx->gsvs_ring =
3512 pipe_aligned_buffer_create(sctx->b.screen,
3513 SI_RESOURCE_FLAG_UNMAPPABLE,
3514 PIPE_USAGE_DEFAULT,
3515 gsvs_ring_size,
3516 sctx->screen->info.pte_fragment_size);
3517 if (!sctx->gsvs_ring)
3518 return false;
3519 }
3520
3521 /* Create the "init_config_gs_rings" state. */
3522 pm4 = CALLOC_STRUCT(si_pm4_state);
3523 if (!pm4)
3524 return false;
3525
3526 if (sctx->chip_class >= GFX7) {
3527 if (sctx->esgs_ring) {
3528 assert(sctx->chip_class <= GFX8);
3529 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3530 sctx->esgs_ring->width0 / 256);
3531 }
3532 if (sctx->gsvs_ring)
3533 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3534 sctx->gsvs_ring->width0 / 256);
3535 } else {
3536 if (sctx->esgs_ring)
3537 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3538 sctx->esgs_ring->width0 / 256);
3539 if (sctx->gsvs_ring)
3540 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3541 sctx->gsvs_ring->width0 / 256);
3542 }
3543
3544 /* Set the state. */
3545 if (sctx->init_config_gs_rings)
3546 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3547 sctx->init_config_gs_rings = pm4;
3548
3549 if (!sctx->init_config_has_vgt_flush) {
3550 si_init_config_add_vgt_flush(sctx);
3551 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3552 }
3553
3554 /* Flush the context to re-emit both init_config states. */
3555 sctx->initial_gfx_cs_size = 0; /* force flush */
3556 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3557
3558 /* Set ring bindings. */
3559 if (sctx->esgs_ring) {
3560 assert(sctx->chip_class <= GFX8);
3561 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3562 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3563 true, true, 4, 64, 0);
3564 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3565 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3566 false, false, 0, 0, 0);
3567 }
3568 if (sctx->gsvs_ring) {
3569 si_set_ring_buffer(sctx, SI_RING_GSVS,
3570 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3571 false, false, 0, 0, 0);
3572 }
3573
3574 return true;
3575 }
3576
3577 static void si_shader_lock(struct si_shader *shader)
3578 {
3579 simple_mtx_lock(&shader->selector->mutex);
3580 if (shader->previous_stage_sel) {
3581 assert(shader->previous_stage_sel != shader->selector);
3582 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3583 }
3584 }
3585
3586 static void si_shader_unlock(struct si_shader *shader)
3587 {
3588 if (shader->previous_stage_sel)
3589 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3590 simple_mtx_unlock(&shader->selector->mutex);
3591 }
3592
3593 /**
3594 * @returns 1 if \p sel has been updated to use a new scratch buffer
3595 * 0 if not
3596 * < 0 if there was a failure
3597 */
3598 static int si_update_scratch_buffer(struct si_context *sctx,
3599 struct si_shader *shader)
3600 {
3601 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3602
3603 if (!shader)
3604 return 0;
3605
3606 /* This shader doesn't need a scratch buffer */
3607 if (shader->config.scratch_bytes_per_wave == 0)
3608 return 0;
3609
3610 /* Prevent race conditions when updating:
3611 * - si_shader::scratch_bo
3612 * - si_shader::binary::code
3613 * - si_shader::previous_stage::binary::code.
3614 */
3615 si_shader_lock(shader);
3616
3617 /* This shader is already configured to use the current
3618 * scratch buffer. */
3619 if (shader->scratch_bo == sctx->scratch_buffer) {
3620 si_shader_unlock(shader);
3621 return 0;
3622 }
3623
3624 assert(sctx->scratch_buffer);
3625
3626 /* Replace the shader bo with a new bo that has the relocs applied. */
3627 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3628 si_shader_unlock(shader);
3629 return -1;
3630 }
3631
3632 /* Update the shader state to use the new shader bo. */
3633 si_shader_init_pm4_state(sctx->screen, shader);
3634
3635 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3636
3637 si_shader_unlock(shader);
3638 return 1;
3639 }
3640
3641 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3642 {
3643 return shader ? shader->config.scratch_bytes_per_wave : 0;
3644 }
3645
3646 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3647 {
3648 if (!sctx->tes_shader.cso)
3649 return NULL; /* tessellation disabled */
3650
3651 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3652 sctx->fixed_func_tcs_shader.current;
3653 }
3654
3655 static bool si_update_scratch_relocs(struct si_context *sctx)
3656 {
3657 struct si_shader *tcs = si_get_tcs_current(sctx);
3658 int r;
3659
3660 /* Update the shaders, so that they are using the latest scratch.
3661 * The scratch buffer may have been changed since these shaders were
3662 * last used, so we still need to try to update them, even if they
3663 * require scratch buffers smaller than the current size.
3664 */
3665 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3666 if (r < 0)
3667 return false;
3668 if (r == 1)
3669 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3670
3671 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3672 if (r < 0)
3673 return false;
3674 if (r == 1)
3675 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3676
3677 r = si_update_scratch_buffer(sctx, tcs);
3678 if (r < 0)
3679 return false;
3680 if (r == 1)
3681 si_pm4_bind_state(sctx, hs, tcs->pm4);
3682
3683 /* VS can be bound as LS, ES, or VS. */
3684 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3685 if (r < 0)
3686 return false;
3687 if (r == 1) {
3688 if (sctx->vs_shader.current->key.as_ls)
3689 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3690 else if (sctx->vs_shader.current->key.as_es)
3691 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3692 else if (sctx->vs_shader.current->key.as_ngg)
3693 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3694 else
3695 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3696 }
3697
3698 /* TES can be bound as ES or VS. */
3699 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3700 if (r < 0)
3701 return false;
3702 if (r == 1) {
3703 if (sctx->tes_shader.current->key.as_es)
3704 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3705 else if (sctx->tes_shader.current->key.as_ngg)
3706 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3707 else
3708 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3709 }
3710
3711 return true;
3712 }
3713
3714 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3715 {
3716 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3717 * There are 2 cases to handle:
3718 *
3719 * - If the current needed size is less than the maximum seen size,
3720 * use the maximum seen size, so that WAVESIZE remains the same.
3721 *
3722 * - If the current needed size is greater than the maximum seen size,
3723 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3724 *
3725 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3726 * Otherwise, the number of waves that can use scratch is
3727 * SPI_TMPRING_SIZE.WAVES.
3728 */
3729 unsigned bytes = 0;
3730
3731 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3732 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3733 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3734
3735 if (sctx->tes_shader.cso) {
3736 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3737 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3738 }
3739
3740 sctx->max_seen_scratch_bytes_per_wave =
3741 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3742
3743 unsigned scratch_needed_size =
3744 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3745 unsigned spi_tmpring_size;
3746
3747 if (scratch_needed_size > 0) {
3748 if (!sctx->scratch_buffer ||
3749 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3750 /* Create a bigger scratch buffer */
3751 si_resource_reference(&sctx->scratch_buffer, NULL);
3752
3753 sctx->scratch_buffer =
3754 si_aligned_buffer_create(&sctx->screen->b,
3755 SI_RESOURCE_FLAG_UNMAPPABLE,
3756 PIPE_USAGE_DEFAULT,
3757 scratch_needed_size,
3758 sctx->screen->info.pte_fragment_size);
3759 if (!sctx->scratch_buffer)
3760 return false;
3761
3762 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3763 si_context_add_resource_size(sctx,
3764 &sctx->scratch_buffer->b.b);
3765 }
3766
3767 if (!si_update_scratch_relocs(sctx))
3768 return false;
3769 }
3770
3771 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3772 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3773 "scratch size should already be aligned correctly.");
3774
3775 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3776 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3777 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3778 sctx->spi_tmpring_size = spi_tmpring_size;
3779 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3780 }
3781 return true;
3782 }
3783
3784 static void si_init_tess_factor_ring(struct si_context *sctx)
3785 {
3786 assert(!sctx->tess_rings);
3787 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3788
3789 /* The address must be aligned to 2^19, because the shader only
3790 * receives the high 13 bits.
3791 */
3792 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3793 SI_RESOURCE_FLAG_32BIT,
3794 PIPE_USAGE_DEFAULT,
3795 sctx->screen->tess_offchip_ring_size +
3796 sctx->screen->tess_factor_ring_size,
3797 1 << 19);
3798 if (!sctx->tess_rings)
3799 return;
3800
3801 si_init_config_add_vgt_flush(sctx);
3802
3803 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3804 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3805
3806 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3807 sctx->screen->tess_offchip_ring_size;
3808
3809 /* Append these registers to the init config state. */
3810 if (sctx->chip_class >= GFX7) {
3811 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3812 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3813 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3814 factor_va >> 8);
3815 if (sctx->chip_class >= GFX10)
3816 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3817 S_030984_BASE_HI(factor_va >> 40));
3818 else if (sctx->chip_class == GFX9)
3819 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3820 S_030944_BASE_HI(factor_va >> 40));
3821 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3822 sctx->screen->vgt_hs_offchip_param);
3823 } else {
3824 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3825 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3826 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3827 factor_va >> 8);
3828 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3829 sctx->screen->vgt_hs_offchip_param);
3830 }
3831
3832 /* Flush the context to re-emit the init_config state.
3833 * This is done only once in a lifetime of a context.
3834 */
3835 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3836 sctx->initial_gfx_cs_size = 0; /* force flush */
3837 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3838 }
3839
3840 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3841 union si_vgt_stages_key key)
3842 {
3843 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3844 uint32_t stages = 0;
3845
3846 if (key.u.tess) {
3847 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3848 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3849
3850 if (key.u.gs)
3851 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3852 S_028B54_GS_EN(1);
3853 else if (key.u.ngg)
3854 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3855 else
3856 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3857 } else if (key.u.gs) {
3858 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3859 S_028B54_GS_EN(1);
3860 } else if (key.u.ngg) {
3861 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3862 }
3863
3864 if (key.u.ngg) {
3865 stages |= S_028B54_PRIMGEN_EN(1);
3866 if (key.u.streamout)
3867 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3868 } else if (key.u.gs)
3869 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3870
3871 if (screen->info.chip_class >= GFX9)
3872 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3873
3874 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3875 stages |= S_028B54_HS_W32_EN(1) |
3876 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3877 S_028B54_VS_W32_EN(1);
3878 }
3879
3880 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3881 return pm4;
3882 }
3883
3884 static void si_update_vgt_shader_config(struct si_context *sctx,
3885 union si_vgt_stages_key key)
3886 {
3887 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3888
3889 if (unlikely(!*pm4))
3890 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3891 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3892 }
3893
3894 bool si_update_shaders(struct si_context *sctx)
3895 {
3896 struct pipe_context *ctx = (struct pipe_context*)sctx;
3897 struct si_compiler_ctx_state compiler_state;
3898 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3899 struct si_shader *old_vs = si_get_vs_state(sctx);
3900 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3901 struct si_shader *old_ps = sctx->ps_shader.current;
3902 union si_vgt_stages_key key;
3903 unsigned old_spi_shader_col_format =
3904 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3905 int r;
3906
3907 compiler_state.compiler = &sctx->compiler;
3908 compiler_state.debug = sctx->debug;
3909 compiler_state.is_debug_context = sctx->is_debug;
3910
3911 key.index = 0;
3912
3913 if (sctx->tes_shader.cso)
3914 key.u.tess = 1;
3915 if (sctx->gs_shader.cso)
3916 key.u.gs = 1;
3917
3918 if (sctx->ngg) {
3919 key.u.ngg = 1;
3920 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3921 }
3922
3923 /* Update TCS and TES. */
3924 if (sctx->tes_shader.cso) {
3925 if (!sctx->tess_rings) {
3926 si_init_tess_factor_ring(sctx);
3927 if (!sctx->tess_rings)
3928 return false;
3929 }
3930
3931 if (sctx->tcs_shader.cso) {
3932 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3933 &compiler_state);
3934 if (r)
3935 return false;
3936 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3937 } else {
3938 if (!sctx->fixed_func_tcs_shader.cso) {
3939 sctx->fixed_func_tcs_shader.cso =
3940 si_create_fixed_func_tcs(sctx);
3941 if (!sctx->fixed_func_tcs_shader.cso)
3942 return false;
3943 }
3944
3945 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3946 key, &compiler_state);
3947 if (r)
3948 return false;
3949 si_pm4_bind_state(sctx, hs,
3950 sctx->fixed_func_tcs_shader.current->pm4);
3951 }
3952
3953 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3954 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3955 if (r)
3956 return false;
3957
3958 if (sctx->gs_shader.cso) {
3959 /* TES as ES */
3960 assert(sctx->chip_class <= GFX8);
3961 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3962 } else if (key.u.ngg) {
3963 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3964 } else {
3965 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3966 }
3967 }
3968 } else {
3969 if (sctx->chip_class <= GFX8)
3970 si_pm4_bind_state(sctx, ls, NULL);
3971 si_pm4_bind_state(sctx, hs, NULL);
3972 }
3973
3974 /* Update GS. */
3975 if (sctx->gs_shader.cso) {
3976 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3977 if (r)
3978 return false;
3979 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3980 if (!key.u.ngg) {
3981 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3982
3983 if (!si_update_gs_ring_buffers(sctx))
3984 return false;
3985 } else {
3986 si_pm4_bind_state(sctx, vs, NULL);
3987 }
3988 } else {
3989 if (!key.u.ngg) {
3990 si_pm4_bind_state(sctx, gs, NULL);
3991 if (sctx->chip_class <= GFX8)
3992 si_pm4_bind_state(sctx, es, NULL);
3993 }
3994 }
3995
3996 /* Update VS. */
3997 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3998 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3999 if (r)
4000 return false;
4001
4002 if (!key.u.tess && !key.u.gs) {
4003 if (key.u.ngg) {
4004 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
4005 si_pm4_bind_state(sctx, vs, NULL);
4006 } else {
4007 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4008 }
4009 } else if (sctx->tes_shader.cso) {
4010 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4011 } else {
4012 assert(sctx->gs_shader.cso);
4013 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4014 }
4015 }
4016
4017 si_update_vgt_shader_config(sctx, key);
4018
4019 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4020 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4021
4022 if (sctx->ps_shader.cso) {
4023 unsigned db_shader_control;
4024
4025 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4026 if (r)
4027 return false;
4028 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4029
4030 db_shader_control =
4031 sctx->ps_shader.cso->db_shader_control |
4032 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4033
4034 if (si_pm4_state_changed(sctx, ps) ||
4035 si_pm4_state_changed(sctx, vs) ||
4036 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4037 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4038 sctx->flatshade != rs->flatshade) {
4039 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4040 sctx->flatshade = rs->flatshade;
4041 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4042 }
4043
4044 if (sctx->screen->info.rbplus_allowed &&
4045 si_pm4_state_changed(sctx, ps) &&
4046 (!old_ps ||
4047 old_spi_shader_col_format !=
4048 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4049 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4050
4051 if (sctx->ps_db_shader_control != db_shader_control) {
4052 sctx->ps_db_shader_control = db_shader_control;
4053 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4054 if (sctx->screen->dpbb_allowed)
4055 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4056 }
4057
4058 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4059 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4060 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4061
4062 if (sctx->chip_class == GFX6)
4063 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4064
4065 if (sctx->framebuffer.nr_samples <= 1)
4066 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4067 }
4068 }
4069
4070 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4071 si_pm4_state_enabled_and_changed(sctx, hs) ||
4072 si_pm4_state_enabled_and_changed(sctx, es) ||
4073 si_pm4_state_enabled_and_changed(sctx, gs) ||
4074 si_pm4_state_enabled_and_changed(sctx, vs) ||
4075 si_pm4_state_enabled_and_changed(sctx, ps)) {
4076 if (!si_update_spi_tmpring_size(sctx))
4077 return false;
4078 }
4079
4080 if (sctx->chip_class >= GFX7) {
4081 if (si_pm4_state_enabled_and_changed(sctx, ls))
4082 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4083 else if (!sctx->queued.named.ls)
4084 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4085
4086 if (si_pm4_state_enabled_and_changed(sctx, hs))
4087 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4088 else if (!sctx->queued.named.hs)
4089 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4090
4091 if (si_pm4_state_enabled_and_changed(sctx, es))
4092 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4093 else if (!sctx->queued.named.es)
4094 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4095
4096 if (si_pm4_state_enabled_and_changed(sctx, gs))
4097 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4098 else if (!sctx->queued.named.gs)
4099 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4100
4101 if (si_pm4_state_enabled_and_changed(sctx, vs))
4102 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4103 else if (!sctx->queued.named.vs)
4104 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4105
4106 if (si_pm4_state_enabled_and_changed(sctx, ps))
4107 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4108 else if (!sctx->queued.named.ps)
4109 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4110 }
4111
4112 sctx->do_update_shaders = false;
4113 return true;
4114 }
4115
4116 static void si_emit_scratch_state(struct si_context *sctx)
4117 {
4118 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4119
4120 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4121 sctx->spi_tmpring_size);
4122
4123 if (sctx->scratch_buffer) {
4124 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4125 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4126 RADEON_PRIO_SCRATCH_BUFFER);
4127 }
4128 }
4129
4130 void si_init_shader_functions(struct si_context *sctx)
4131 {
4132 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4133 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4134
4135 sctx->b.create_vs_state = si_create_shader_selector;
4136 sctx->b.create_tcs_state = si_create_shader_selector;
4137 sctx->b.create_tes_state = si_create_shader_selector;
4138 sctx->b.create_gs_state = si_create_shader_selector;
4139 sctx->b.create_fs_state = si_create_shader_selector;
4140
4141 sctx->b.bind_vs_state = si_bind_vs_shader;
4142 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4143 sctx->b.bind_tes_state = si_bind_tes_shader;
4144 sctx->b.bind_gs_state = si_bind_gs_shader;
4145 sctx->b.bind_fs_state = si_bind_ps_shader;
4146
4147 sctx->b.delete_vs_state = si_delete_shader_selector;
4148 sctx->b.delete_tcs_state = si_delete_shader_selector;
4149 sctx->b.delete_tes_state = si_delete_shader_selector;
4150 sctx->b.delete_gs_state = si_delete_shader_selector;
4151 sctx->b.delete_fs_state = si_delete_shader_selector;
4152 }