2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
44 * Return the IR key for the shader cache.
46 void si_get_ir_cache_key(struct si_shader_selector
*sel
, bool ngg
, bool es
,
47 unsigned char ir_sha1_cache_key
[20])
49 struct blob blob
= {};
53 if (sel
->nir_binary
) {
54 ir_binary
= sel
->nir_binary
;
55 ir_size
= sel
->nir_size
;
60 nir_serialize(&blob
, sel
->nir
, true);
61 ir_binary
= blob
.data
;
65 /* These settings affect the compilation, but they are not derived
66 * from the input shader IR.
68 unsigned shader_variant_flags
= 0;
71 shader_variant_flags
|= 1 << 0;
73 shader_variant_flags
|= 1 << 1;
74 if (si_get_wave_size(sel
->screen
, sel
->type
, ngg
, es
) == 32)
75 shader_variant_flags
|= 1 << 2;
76 if (sel
->force_correct_derivs_after_kill
)
77 shader_variant_flags
|= 1 << 3;
80 _mesa_sha1_init(&ctx
);
81 _mesa_sha1_update(&ctx
, &shader_variant_flags
, 4);
82 _mesa_sha1_update(&ctx
, ir_binary
, ir_size
);
83 if (sel
->type
== PIPE_SHADER_VERTEX
||
84 sel
->type
== PIPE_SHADER_TESS_EVAL
||
85 sel
->type
== PIPE_SHADER_GEOMETRY
)
86 _mesa_sha1_update(&ctx
, &sel
->so
, sizeof(sel
->so
));
87 _mesa_sha1_final(&ctx
, ir_sha1_cache_key
);
89 if (ir_binary
== blob
.data
)
93 /** Copy "data" to "ptr" and return the next dword following copied data. */
94 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
96 /* data may be NULL if size == 0 */
98 memcpy(ptr
, data
, size
);
99 ptr
+= DIV_ROUND_UP(size
, 4);
103 /** Read data from "ptr". Return the next dword following the data. */
104 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
106 memcpy(data
, ptr
, size
);
107 ptr
+= DIV_ROUND_UP(size
, 4);
112 * Write the size as uint followed by the data. Return the next dword
113 * following the copied data.
115 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
118 return write_data(ptr
, data
, size
);
122 * Read the size as uint followed by the data. Return both via parameters.
123 * Return the next dword following the data.
125 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
128 assert(*data
== NULL
);
131 *data
= malloc(*size
);
132 return read_data(ptr
, *data
, *size
);
136 * Return the shader binary in a buffer. The first 4 bytes contain its size
139 static void *si_get_shader_binary(struct si_shader
*shader
)
141 /* There is always a size of data followed by the data itself. */
142 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
143 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
145 /* Refuse to allocate overly large buffers and guard against integer
147 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
148 llvm_ir_size
> UINT_MAX
/ 4)
153 4 + /* CRC32 of the data below */
154 align(sizeof(shader
->config
), 4) +
155 align(sizeof(shader
->info
), 4) +
156 4 + align(shader
->binary
.elf_size
, 4) +
157 4 + align(llvm_ir_size
, 4);
158 void *buffer
= CALLOC(1, size
);
159 uint32_t *ptr
= (uint32_t*)buffer
;
165 ptr
++; /* CRC32 is calculated at the end. */
167 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
168 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
169 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
170 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
171 assert((char *)ptr
- (char *)buffer
== size
);
174 ptr
= (uint32_t*)buffer
;
176 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
181 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
183 uint32_t *ptr
= (uint32_t*)binary
;
184 uint32_t size
= *ptr
++;
185 uint32_t crc32
= *ptr
++;
189 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
190 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
194 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
195 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
196 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
198 shader
->binary
.elf_size
= elf_size
;
199 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
205 * Insert a shader into the cache. It's assumed the shader is not in the cache.
206 * Use si_shader_cache_load_shader before calling this.
208 void si_shader_cache_insert_shader(struct si_screen
*sscreen
,
209 unsigned char ir_sha1_cache_key
[20],
210 struct si_shader
*shader
,
211 bool insert_into_disk_cache
)
214 struct hash_entry
*entry
;
215 uint8_t key
[CACHE_KEY_SIZE
];
217 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
219 return; /* already added */
221 hw_binary
= si_get_shader_binary(shader
);
225 if (_mesa_hash_table_insert(sscreen
->shader_cache
,
226 mem_dup(ir_sha1_cache_key
, 20),
227 hw_binary
) == NULL
) {
232 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
233 disk_cache_compute_key(sscreen
->disk_shader_cache
,
234 ir_sha1_cache_key
, 20, key
);
235 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
236 *((uint32_t *) hw_binary
), NULL
);
240 bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
241 unsigned char ir_sha1_cache_key
[20],
242 struct si_shader
*shader
)
244 struct hash_entry
*entry
=
245 _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
248 if (si_load_shader_binary(shader
, entry
->data
)) {
249 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
254 if (!sscreen
->disk_shader_cache
)
257 unsigned char sha1
[CACHE_KEY_SIZE
];
258 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_sha1_cache_key
,
262 uint8_t *buffer
= disk_cache_get(sscreen
->disk_shader_cache
, sha1
,
265 if (binary_size
>= sizeof(uint32_t) &&
266 *((uint32_t*)buffer
) == binary_size
) {
267 if (si_load_shader_binary(shader
, buffer
)) {
269 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
,
271 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
275 /* Something has gone wrong discard the item from the cache and
276 * rebuild/link from source.
278 assert(!"Invalid radeonsi shader disk cache item!");
279 disk_cache_remove(sscreen
->disk_shader_cache
, sha1
);
287 static uint32_t si_shader_cache_key_hash(const void *key
)
289 /* Take the first dword of SHA1. */
290 return *(uint32_t*)key
;
293 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
296 return memcmp(a
, b
, 20) == 0;
299 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
301 FREE((void*)entry
->key
);
305 bool si_init_shader_cache(struct si_screen
*sscreen
)
307 (void) simple_mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
308 sscreen
->shader_cache
=
309 _mesa_hash_table_create(NULL
,
310 si_shader_cache_key_hash
,
311 si_shader_cache_key_equals
);
313 return sscreen
->shader_cache
!= NULL
;
316 void si_destroy_shader_cache(struct si_screen
*sscreen
)
318 if (sscreen
->shader_cache
)
319 _mesa_hash_table_destroy(sscreen
->shader_cache
,
320 si_destroy_shader_cache_entry
);
321 simple_mtx_destroy(&sscreen
->shader_cache_mutex
);
326 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
327 const struct si_shader_selector
*tes
,
328 struct si_pm4_state
*pm4
)
330 const struct si_shader_info
*info
= &tes
->info
;
331 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
332 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
333 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
334 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
335 unsigned type
, partitioning
, topology
, distribution_mode
;
337 switch (tes_prim_mode
) {
338 case PIPE_PRIM_LINES
:
339 type
= V_028B6C_TESS_ISOLINE
;
341 case PIPE_PRIM_TRIANGLES
:
342 type
= V_028B6C_TESS_TRIANGLE
;
344 case PIPE_PRIM_QUADS
:
345 type
= V_028B6C_TESS_QUAD
;
352 switch (tes_spacing
) {
353 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
354 partitioning
= V_028B6C_PART_FRAC_ODD
;
356 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
357 partitioning
= V_028B6C_PART_FRAC_EVEN
;
359 case PIPE_TESS_SPACING_EQUAL
:
360 partitioning
= V_028B6C_PART_INTEGER
;
368 topology
= V_028B6C_OUTPUT_POINT
;
369 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
370 topology
= V_028B6C_OUTPUT_LINE
;
371 else if (tes_vertex_order_cw
)
372 /* for some reason, this must be the other way around */
373 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
375 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
377 if (sscreen
->info
.has_distributed_tess
) {
378 if (sscreen
->info
.family
== CHIP_FIJI
||
379 sscreen
->info
.family
>= CHIP_POLARIS10
)
380 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
382 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
384 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
387 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
388 S_028B6C_PARTITIONING(partitioning
) |
389 S_028B6C_TOPOLOGY(topology
) |
390 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
393 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
394 * whether the "fractional odd" tessellation spacing is used.
396 * Possible VGT configurations and which state should set the register:
398 * Reg set in | VGT shader configuration | Value
399 * ------------------------------------------------------
401 * VS as ES | ES -> GS -> VS | 30
402 * TES as VS | LS -> HS -> VS | 14 or 30
403 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
405 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
407 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
408 struct si_shader_selector
*sel
,
409 struct si_shader
*shader
,
410 struct si_pm4_state
*pm4
)
412 unsigned type
= sel
->type
;
414 if (sscreen
->info
.family
< CHIP_POLARIS10
||
415 sscreen
->info
.chip_class
>= GFX10
)
418 /* VS as VS, or VS as ES: */
419 if ((type
== PIPE_SHADER_VERTEX
&&
421 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
422 /* TES as VS, or TES as ES: */
423 type
== PIPE_SHADER_TESS_EVAL
) {
424 unsigned vtx_reuse_depth
= 30;
426 if (type
== PIPE_SHADER_TESS_EVAL
&&
427 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
428 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
429 vtx_reuse_depth
= 14;
432 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
436 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
439 si_pm4_clear_state(shader
->pm4
);
441 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
444 shader
->pm4
->shader
= shader
;
447 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
452 static unsigned si_get_num_vs_user_sgprs(struct si_shader
*shader
,
453 unsigned num_always_on_user_sgprs
)
455 struct si_shader_selector
*vs
= shader
->previous_stage_sel
?
456 shader
->previous_stage_sel
: shader
->selector
;
457 unsigned num_vbos_in_user_sgprs
= vs
->num_vbos_in_user_sgprs
;
459 /* 1 SGPR is reserved for the vertex buffer pointer. */
460 assert(num_always_on_user_sgprs
<= SI_SGPR_VS_VB_DESCRIPTOR_FIRST
- 1);
462 if (num_vbos_in_user_sgprs
)
463 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST
+ num_vbos_in_user_sgprs
* 4;
465 /* Add the pointer to VBO descriptors. */
466 return num_always_on_user_sgprs
+ 1;
469 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
470 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen
*sscreen
,
471 struct si_shader
*shader
, bool legacy_vs_prim_id
)
473 assert(shader
->selector
->type
== PIPE_SHADER_VERTEX
||
474 (shader
->previous_stage_sel
&&
475 shader
->previous_stage_sel
->type
== PIPE_SHADER_VERTEX
));
477 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
478 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
479 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
480 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
482 bool is_ls
= shader
->selector
->type
== PIPE_SHADER_TESS_CTRL
|| shader
->key
.as_ls
;
484 if (sscreen
->info
.chip_class
>= GFX10
&& shader
->info
.uses_instanceid
)
486 else if ((is_ls
&& shader
->info
.uses_instanceid
) || legacy_vs_prim_id
)
488 else if (is_ls
|| shader
->info
.uses_instanceid
)
494 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
496 struct si_pm4_state
*pm4
;
499 assert(sscreen
->info
.chip_class
<= GFX8
);
501 pm4
= si_get_shader_pm4_state(shader
);
505 va
= shader
->bo
->gpu_address
;
506 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
508 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
509 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
511 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
512 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
513 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false)) |
514 S_00B528_DX10_CLAMP(1) |
515 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
516 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
)) |
517 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
520 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
522 struct si_pm4_state
*pm4
;
525 pm4
= si_get_shader_pm4_state(shader
);
529 va
= shader
->bo
->gpu_address
;
530 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
532 if (sscreen
->info
.chip_class
>= GFX9
) {
533 if (sscreen
->info
.chip_class
>= GFX10
) {
534 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
535 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
537 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
538 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
541 unsigned num_user_sgprs
=
542 si_get_num_vs_user_sgprs(shader
, GFX9_TCS_NUM_USER_SGPR
);
544 shader
->config
.rsrc2
=
545 S_00B42C_USER_SGPR(num_user_sgprs
) |
546 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
548 if (sscreen
->info
.chip_class
>= GFX10
)
549 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
551 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
553 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
554 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
556 shader
->config
.rsrc2
=
557 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
558 S_00B42C_OC_LDS_EN(1) |
559 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
562 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
563 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) /
564 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
565 (sscreen
->info
.chip_class
<= GFX9
?
566 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) : 0) |
567 S_00B428_DX10_CLAMP(1) |
568 S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
569 S_00B428_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
570 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
571 S_00B428_LS_VGPR_COMP_CNT(sscreen
->info
.chip_class
>= GFX9
?
572 si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false) : 0));
574 if (sscreen
->info
.chip_class
<= GFX8
) {
575 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
576 shader
->config
.rsrc2
);
580 static void si_emit_shader_es(struct si_context
*sctx
)
582 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
583 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
588 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
589 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
590 shader
->selector
->esgs_itemsize
/ 4);
592 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
593 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
594 SI_TRACKED_VGT_TF_PARAM
,
595 shader
->vgt_tf_param
);
597 if (shader
->vgt_vertex_reuse_block_cntl
)
598 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
599 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
600 shader
->vgt_vertex_reuse_block_cntl
);
602 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
603 sctx
->context_roll
= true;
606 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
608 struct si_pm4_state
*pm4
;
609 unsigned num_user_sgprs
;
610 unsigned vgpr_comp_cnt
;
614 assert(sscreen
->info
.chip_class
<= GFX8
);
616 pm4
= si_get_shader_pm4_state(shader
);
620 pm4
->atom
.emit
= si_emit_shader_es
;
621 va
= shader
->bo
->gpu_address
;
622 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
624 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
625 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
626 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
);
627 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
628 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
629 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
631 unreachable("invalid shader selector type");
633 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
635 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
636 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
637 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
638 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
639 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
640 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
641 S_00B328_DX10_CLAMP(1) |
642 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
643 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
644 S_00B32C_USER_SGPR(num_user_sgprs
) |
645 S_00B32C_OC_LDS_EN(oc_lds_en
) |
646 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
648 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
649 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
651 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
654 void gfx9_get_gs_info(struct si_shader_selector
*es
,
655 struct si_shader_selector
*gs
,
656 struct gfx9_gs_info
*out
)
658 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
659 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
660 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
661 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
663 /* All these are in dwords: */
664 /* We can't allow using the whole LDS, because GS waves compete with
665 * other shader stages for LDS space. */
666 const unsigned max_lds_size
= 8 * 1024;
667 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
668 unsigned esgs_lds_size
;
670 /* All these are per subgroup: */
671 const unsigned max_out_prims
= 32 * 1024;
672 const unsigned max_es_verts
= 255;
673 const unsigned ideal_gs_prims
= 64;
674 unsigned max_gs_prims
, gs_prims
;
675 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
677 if (uses_adjacency
|| gs_num_invocations
> 1)
678 max_gs_prims
= 127 / gs_num_invocations
;
682 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
683 * Make sure we don't go over the maximum value.
685 if (gs
->gs_max_out_vertices
> 0) {
686 max_gs_prims
= MIN2(max_gs_prims
,
688 (gs
->gs_max_out_vertices
* gs_num_invocations
));
690 assert(max_gs_prims
> 0);
692 /* If the primitive has adjacency, halve the number of vertices
693 * that will be reused in multiple primitives.
695 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
697 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
698 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
700 /* Compute ESGS LDS size based on the worst case number of ES vertices
701 * needed to create the target number of GS prims per subgroup.
703 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
705 /* If total LDS usage is too big, refactor partitions based on ratio
706 * of ESGS item sizes.
708 if (esgs_lds_size
> max_lds_size
) {
709 /* Our target GS Prims Per Subgroup was too large. Calculate
710 * the maximum number of GS Prims Per Subgroup that will fit
711 * into LDS, capped by the maximum that the hardware can support.
713 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
715 assert(gs_prims
> 0);
716 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
719 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
720 assert(esgs_lds_size
<= max_lds_size
);
723 /* Now calculate remaining ESGS information. */
725 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
727 es_verts
= max_es_verts
;
729 /* Vertices for adjacency primitives are not always reused, so restore
730 * it for ES_VERTS_PER_SUBGRP.
732 min_es_verts
= gs
->gs_input_verts_per_prim
;
734 /* For normal primitives, the VGT only checks if they are past the ES
735 * verts per subgroup after allocating a full GS primitive and if they
736 * are, kick off a new subgroup. But if those additional ES verts are
737 * unique (e.g. not reused) we need to make sure there is enough LDS
738 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
740 es_verts
-= min_es_verts
- 1;
742 out
->es_verts_per_subgroup
= es_verts
;
743 out
->gs_prims_per_subgroup
= gs_prims
;
744 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
745 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
746 gs
->gs_max_out_vertices
;
747 out
->esgs_ring_size
= 4 * esgs_lds_size
;
749 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
752 static void si_emit_shader_gs(struct si_context
*sctx
)
754 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
755 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
760 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
761 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
762 radeon_opt_set_context_reg3(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
763 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
764 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
765 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
766 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
768 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
769 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
770 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
771 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
773 /* R_028B38_VGT_GS_MAX_VERT_OUT */
774 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
775 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
776 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
778 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
779 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
780 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
781 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
782 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
783 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
784 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
785 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
787 /* R_028B90_VGT_GS_INSTANCE_CNT */
788 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
789 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
790 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
792 if (sctx
->chip_class
>= GFX9
) {
793 /* R_028A44_VGT_GS_ONCHIP_CNTL */
794 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
795 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
796 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
797 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
798 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
799 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
800 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
801 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
802 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
803 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
804 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
806 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
807 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
808 SI_TRACKED_VGT_TF_PARAM
,
809 shader
->vgt_tf_param
);
810 if (shader
->vgt_vertex_reuse_block_cntl
)
811 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
812 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
813 shader
->vgt_vertex_reuse_block_cntl
);
816 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
817 sctx
->context_roll
= true;
820 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
822 struct si_shader_selector
*sel
= shader
->selector
;
823 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
824 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
825 struct si_pm4_state
*pm4
;
827 unsigned max_stream
= sel
->max_gs_stream
;
830 pm4
= si_get_shader_pm4_state(shader
);
834 pm4
->atom
.emit
= si_emit_shader_gs
;
836 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
837 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
840 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
841 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
844 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
845 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
848 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
849 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
851 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
852 assert(offset
< (1 << 15));
854 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
856 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
857 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
858 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
859 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
861 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
862 S_028B90_ENABLE(gs_num_invocations
> 0);
864 va
= shader
->bo
->gpu_address
;
865 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
867 if (sscreen
->info
.chip_class
>= GFX9
) {
868 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
869 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
870 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
872 if (es_type
== PIPE_SHADER_VERTEX
) {
873 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
874 } else if (es_type
== PIPE_SHADER_TESS_EVAL
)
875 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
877 unreachable("invalid shader selector type");
879 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
880 * VGPR[0:4] are always loaded.
882 if (sel
->info
.uses_invocationid
)
883 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
884 else if (sel
->info
.uses_primid
)
885 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
886 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
887 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
889 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
891 unsigned num_user_sgprs
;
892 if (es_type
== PIPE_SHADER_VERTEX
)
893 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, GFX9_VSGS_NUM_USER_SGPR
);
895 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
897 if (sscreen
->info
.chip_class
>= GFX10
) {
898 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
899 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
901 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
902 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
906 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
907 S_00B228_DX10_CLAMP(1) |
908 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
909 S_00B228_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
910 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
911 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
913 S_00B22C_USER_SGPR(num_user_sgprs
) |
914 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
915 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
916 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
917 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
919 if (sscreen
->info
.chip_class
>= GFX10
) {
920 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
922 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
923 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
926 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
927 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
929 if (sscreen
->info
.chip_class
>= GFX10
) {
930 si_pm4_set_reg(pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
931 S_00B204_CU_EN(0xffff) |
932 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
935 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
936 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
937 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
938 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
939 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
940 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
941 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
942 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
944 if (es_type
== PIPE_SHADER_TESS_EVAL
)
945 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
947 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
950 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
951 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
953 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
954 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
955 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
956 S_00B228_DX10_CLAMP(1) |
957 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
958 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
959 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
960 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
964 static void gfx10_emit_ge_pc_alloc(struct si_context
*sctx
, unsigned value
)
966 enum si_tracked_reg reg
= SI_TRACKED_GE_PC_ALLOC
;
968 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x1) != 0x1 ||
969 sctx
->tracked_regs
.reg_value
[reg
] != value
) {
970 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
972 if (sctx
->family
== CHIP_NAVI10
||
973 sctx
->family
== CHIP_NAVI12
||
974 sctx
->family
== CHIP_NAVI14
) {
975 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
976 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
977 radeon_emit(cs
, EVENT_TYPE(V_028A90_SQ_NON_EVENT
) | EVENT_INDEX(0));
980 radeon_set_uconfig_reg(cs
, R_030980_GE_PC_ALLOC
, value
);
982 sctx
->tracked_regs
.reg_saved
|= 0x1ull
<< reg
;
983 sctx
->tracked_regs
.reg_value
[reg
] = value
;
987 /* Common tail code for NGG primitive shaders. */
988 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
,
989 struct si_shader
*shader
,
990 unsigned initial_cdw
)
992 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
993 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
994 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
995 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
996 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
997 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
998 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
999 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1000 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
1001 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
1002 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
1003 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
1004 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
1005 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
1006 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
1007 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
1008 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
1009 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
1010 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1011 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1012 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
1013 radeon_opt_set_context_reg2(sctx
, R_028708_SPI_SHADER_IDX_FORMAT
,
1014 SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
1015 shader
->ctx_reg
.ngg
.spi_shader_idx_format
,
1016 shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
1017 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1018 SI_TRACKED_PA_CL_VTE_CNTL
,
1019 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
1020 radeon_opt_set_context_reg(sctx
, R_028838_PA_CL_NGG_CNTL
,
1021 SI_TRACKED_PA_CL_NGG_CNTL
,
1022 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
);
1024 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
1025 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
,
1026 shader
->pa_cl_vs_out_cntl
,
1027 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
1029 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1030 sctx
->context_roll
= true;
1032 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1033 gfx10_emit_ge_pc_alloc(sctx
, shader
->ctx_reg
.ngg
.ge_pc_alloc
);
1036 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
1038 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1039 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1044 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1047 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
1049 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1050 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1055 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1056 SI_TRACKED_VGT_TF_PARAM
,
1057 shader
->vgt_tf_param
);
1059 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1062 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
1064 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1065 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1070 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1071 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1072 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1074 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1077 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1079 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1080 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1085 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1086 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1087 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1088 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1089 SI_TRACKED_VGT_TF_PARAM
,
1090 shader
->vgt_tf_param
);
1092 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1095 unsigned si_get_input_prim(const struct si_shader_selector
*gs
)
1097 if (gs
->type
== PIPE_SHADER_GEOMETRY
)
1098 return gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
1100 if (gs
->type
== PIPE_SHADER_TESS_EVAL
) {
1101 if (gs
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1102 return PIPE_PRIM_POINTS
;
1103 if (gs
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
1104 return PIPE_PRIM_LINES
;
1105 return PIPE_PRIM_TRIANGLES
;
1108 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1109 return PIPE_PRIM_TRIANGLES
; /* worst case for all callers */
1112 static unsigned si_get_vs_out_cntl(const struct si_shader_selector
*sel
, bool ngg
)
1115 sel
->info
.writes_psize
|| (sel
->info
.writes_edgeflag
&& !ngg
) ||
1116 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
1117 return S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
1118 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
&& !ngg
) |
1119 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
1120 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
1121 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
1122 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
1126 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1129 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1131 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1132 const struct si_shader_info
*gs_info
= &gs_sel
->info
;
1133 enum pipe_shader_type gs_type
= shader
->selector
->type
;
1134 const struct si_shader_selector
*es_sel
=
1135 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1136 const struct si_shader_info
*es_info
= &es_sel
->info
;
1137 enum pipe_shader_type es_type
= es_sel
->type
;
1138 unsigned num_user_sgprs
;
1139 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1141 unsigned window_space
=
1142 gs_info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1143 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1144 unsigned gs_num_invocations
= MAX2(gs_sel
->gs_num_invocations
, 1);
1145 unsigned input_prim
= si_get_input_prim(gs_sel
);
1146 bool break_wave_at_eoi
= false;
1147 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1151 if (es_type
== PIPE_SHADER_TESS_EVAL
) {
1152 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1153 : gfx10_emit_shader_ngg_tess_nogs
;
1155 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1156 : gfx10_emit_shader_ngg_notess_nogs
;
1159 va
= shader
->bo
->gpu_address
;
1160 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1162 if (es_type
== PIPE_SHADER_VERTEX
) {
1163 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
1165 if (es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1166 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1167 es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1169 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, GFX9_VSGS_NUM_USER_SGPR
);
1172 assert(es_type
== PIPE_SHADER_TESS_EVAL
);
1173 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1174 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1176 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1177 break_wave_at_eoi
= true;
1180 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1181 * VGPR[0:4] are always loaded.
1183 * Vertex shaders always need to load VGPR3, because they need to
1184 * pass edge flags for decomposed primitives (such as quads) to the PA
1185 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1187 if (gs_info
->uses_invocationid
||
1188 (gs_type
== PIPE_SHADER_VERTEX
&& !gfx10_is_ngg_passthrough(shader
)))
1189 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID, edge flags. */
1190 else if ((gs_type
== PIPE_SHADER_GEOMETRY
&& gs_info
->uses_primid
) ||
1191 (gs_type
== PIPE_SHADER_VERTEX
&& shader
->key
.mono
.u
.vs_export_prim_id
))
1192 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1193 else if (input_prim
>= PIPE_PRIM_TRIANGLES
&& !gfx10_is_ngg_passthrough(shader
))
1194 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1196 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1198 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1199 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1200 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1201 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) /
1202 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1203 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
1204 S_00B228_DX10_CLAMP(1) |
1205 S_00B228_MEM_ORDERED(1) |
1206 S_00B228_WGP_MODE(1) |
1207 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1208 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1209 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1210 S_00B22C_USER_SGPR(num_user_sgprs
) |
1211 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1212 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1213 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
1214 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1216 /* Determine LATE_ALLOC_GS. */
1217 unsigned num_cu_per_sh
= sscreen
->info
.num_good_cu_per_sh
;
1218 unsigned late_alloc_wave64
; /* The limit is per SH. */
1220 /* For Wave32, the hw will launch twice the number of late
1221 * alloc waves, so 1 == 2x wave32.
1223 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1225 if (sscreen
->info
.family
== CHIP_NAVI14
)
1226 late_alloc_wave64
= 0;
1227 else if (num_cu_per_sh
<= 6)
1228 late_alloc_wave64
= num_cu_per_sh
- 2; /* All CUs enabled */
1229 else if (shader
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_ALL
)
1230 late_alloc_wave64
= (num_cu_per_sh
- 2) * 6;
1232 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
1234 si_pm4_set_reg(pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
1235 S_00B204_CU_EN(0xffff) |
1236 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64
));
1238 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1239 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1240 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
1241 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1243 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1244 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1245 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1246 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1247 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1248 V_02870C_SPI_SHADER_4COMP
:
1249 V_02870C_SPI_SHADER_NONE
) |
1250 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1251 V_02870C_SPI_SHADER_4COMP
:
1252 V_02870C_SPI_SHADER_NONE
) |
1253 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1254 V_02870C_SPI_SHADER_4COMP
:
1255 V_02870C_SPI_SHADER_NONE
);
1257 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1258 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1259 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader
->key
.mono
.u
.vs_export_prim_id
||
1260 gs_sel
->info
.writes_primid
);
1262 if (gs_type
== PIPE_SHADER_GEOMETRY
) {
1263 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1264 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->gs_max_out_vertices
;
1266 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1269 if (es_type
== PIPE_SHADER_TESS_EVAL
)
1270 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1272 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1273 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1274 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1275 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1276 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1277 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1278 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
=
1279 S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1280 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1281 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1282 S_028B90_CNT(gs_num_invocations
) |
1283 S_028B90_ENABLE(gs_num_invocations
> 1) |
1284 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1285 shader
->ngg
.max_vert_out_per_gs_instance
);
1287 /* Always output hw-generated edge flags and pass them via the prim
1288 * export to prevent drawing lines on internal edges of decomposed
1289 * primitives (such as quads) with polygon mode = lines. Only VS needs
1292 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
=
1293 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type
== PIPE_SHADER_VERTEX
);
1294 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(gs_sel
, true);
1296 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1297 float oversub_pc_factor
= 0.25;
1299 if (shader
->key
.opt
.ngg_culling
) {
1300 /* Be more aggressive with NGG culling. */
1301 if (shader
->info
.nr_param_exports
> 4)
1302 oversub_pc_factor
= 1;
1303 else if (shader
->info
.nr_param_exports
> 2)
1304 oversub_pc_factor
= 0.75;
1306 oversub_pc_factor
= 0.5;
1309 unsigned oversub_pc_lines
= sscreen
->info
.pc_lines
* oversub_pc_factor
;
1310 shader
->ctx_reg
.ngg
.ge_pc_alloc
= S_030980_OVERSUB_EN(1) |
1311 S_030980_NUM_PC_LINES(oversub_pc_lines
- 1);
1313 if (shader
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST
) {
1315 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1316 S_03096C_VERT_GRP_SIZE(shader
->ngg
.max_gsprims
* 3);
1317 } else if (shader
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP
) {
1319 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1320 S_03096C_VERT_GRP_SIZE(shader
->ngg
.max_gsprims
+ 2);
1323 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1324 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1325 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1327 /* Bug workaround for a possible hang with non-tessellation cases.
1328 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1330 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1332 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1333 sscreen
->info
.family
== CHIP_NAVI12
||
1334 sscreen
->info
.family
== CHIP_NAVI14
) &&
1335 (es_type
== PIPE_SHADER_VERTEX
|| gs_type
== PIPE_SHADER_VERTEX
) && /* = no tess */
1336 shader
->ngg
.hw_max_esverts
!= 256) {
1337 shader
->ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
1339 if (shader
->ngg
.hw_max_esverts
> 5) {
1341 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
- 5);
1347 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1348 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1350 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1351 S_028818_VTX_W0_FMT(1) |
1352 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1353 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1354 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1358 static void si_emit_shader_vs(struct si_context
*sctx
)
1360 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1361 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1366 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
1367 SI_TRACKED_VGT_GS_MODE
,
1368 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1369 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1370 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1371 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1373 if (sctx
->chip_class
<= GFX8
) {
1374 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
1375 SI_TRACKED_VGT_REUSE_OFF
,
1376 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1379 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1380 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1381 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1383 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1384 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1385 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1387 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1388 SI_TRACKED_PA_CL_VTE_CNTL
,
1389 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1391 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1392 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1393 SI_TRACKED_VGT_TF_PARAM
,
1394 shader
->vgt_tf_param
);
1396 if (shader
->vgt_vertex_reuse_block_cntl
)
1397 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1398 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1399 shader
->vgt_vertex_reuse_block_cntl
);
1401 /* Required programming for tessellation. (legacy pipeline only) */
1402 if (sctx
->chip_class
== GFX10
&&
1403 shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1404 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
1405 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
1406 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1407 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1408 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1411 if (sctx
->chip_class
>= GFX10
) {
1412 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
1413 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
,
1414 shader
->pa_cl_vs_out_cntl
,
1415 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
1418 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1419 sctx
->context_roll
= true;
1421 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1422 if (sctx
->chip_class
>= GFX10
)
1423 gfx10_emit_ge_pc_alloc(sctx
, shader
->ctx_reg
.vs
.ge_pc_alloc
);
1427 * Compute the state for \p shader, which will run as a vertex shader on the
1430 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1431 * is the copy shader.
1433 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1434 struct si_shader_selector
*gs
)
1436 const struct si_shader_info
*info
= &shader
->selector
->info
;
1437 struct si_pm4_state
*pm4
;
1438 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1440 unsigned nparams
, oc_lds_en
;
1441 unsigned window_space
=
1442 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1443 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1445 pm4
= si_get_shader_pm4_state(shader
);
1449 pm4
->atom
.emit
= si_emit_shader_vs
;
1451 /* We always write VGT_GS_MODE in the VS state, because every switch
1452 * between different shader pipelines involving a different GS or no
1453 * GS at all involves a switch of the VS (different GS use different
1454 * copy shaders). On the other hand, when the API switches from a GS to
1455 * no GS and then back to the same GS used originally, the GS state is
1459 unsigned mode
= V_028A40_GS_OFF
;
1461 /* PrimID needs GS scenario A. */
1463 mode
= V_028A40_GS_SCENARIO_A
;
1465 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1466 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1468 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1469 sscreen
->info
.chip_class
);
1470 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1473 if (sscreen
->info
.chip_class
<= GFX8
) {
1474 /* Reuse needs to be set off if we write oViewport. */
1475 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1476 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1479 va
= shader
->bo
->gpu_address
;
1480 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1483 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1484 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1485 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1486 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, enable_prim_id
);
1488 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1489 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1490 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1492 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
);
1494 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1495 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1496 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1498 unreachable("invalid shader selector type");
1500 /* VS is required to export at least one param. */
1501 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1502 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1504 if (sscreen
->info
.chip_class
>= GFX10
) {
1505 shader
->ctx_reg
.vs
.spi_vs_out_config
|=
1506 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1509 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1510 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1511 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1512 V_02870C_SPI_SHADER_4COMP
:
1513 V_02870C_SPI_SHADER_NONE
) |
1514 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1515 V_02870C_SPI_SHADER_4COMP
:
1516 V_02870C_SPI_SHADER_NONE
) |
1517 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1518 V_02870C_SPI_SHADER_4COMP
:
1519 V_02870C_SPI_SHADER_NONE
);
1520 shader
->ctx_reg
.vs
.ge_pc_alloc
= S_030980_OVERSUB_EN(1) |
1521 S_030980_NUM_PC_LINES(sscreen
->info
.pc_lines
/ 4 - 1);
1522 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(shader
->selector
, false);
1524 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1526 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1527 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1529 uint32_t rsrc1
= S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) /
1530 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1531 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1532 S_00B128_DX10_CLAMP(1) |
1533 S_00B128_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1534 S_00B128_FLOAT_MODE(shader
->config
.float_mode
);
1535 uint32_t rsrc2
= S_00B12C_USER_SGPR(num_user_sgprs
) |
1536 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1537 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
1539 if (sscreen
->info
.chip_class
>= GFX10
)
1540 rsrc2
|= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
1541 else if (sscreen
->info
.chip_class
== GFX9
)
1542 rsrc2
|= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
1544 if (sscreen
->info
.chip_class
<= GFX9
)
1545 rsrc1
|= S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1547 if (!sscreen
->use_ngg_streamout
) {
1548 rsrc2
|= S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1549 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1550 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1551 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1552 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
);
1555 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
, rsrc1
);
1556 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
, rsrc2
);
1559 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1560 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1562 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1563 S_028818_VTX_W0_FMT(1) |
1564 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1565 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1566 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1568 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1569 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1571 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1574 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1576 struct si_shader_info
*info
= &ps
->selector
->info
;
1577 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1578 !!(info
->colors_read
& 0xf0);
1579 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1580 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1582 assert(num_interp
<= 32);
1583 return MIN2(num_interp
, 32);
1586 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1588 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1589 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1591 /* If the i-th target format is set, all previous target formats must
1592 * be non-zero to avoid hangs.
1594 for (i
= 0; i
< num_targets
; i
++)
1595 if (!(value
& (0xf << (i
* 4))))
1596 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1601 static void si_emit_shader_ps(struct si_context
*sctx
)
1603 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1604 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1609 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1610 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1611 SI_TRACKED_SPI_PS_INPUT_ENA
,
1612 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1613 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1615 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1616 SI_TRACKED_SPI_BARYC_CNTL
,
1617 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1618 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1619 SI_TRACKED_SPI_PS_IN_CONTROL
,
1620 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1622 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1623 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1624 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1625 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1626 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1628 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1629 SI_TRACKED_CB_SHADER_MASK
,
1630 shader
->ctx_reg
.ps
.cb_shader_mask
);
1632 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1633 sctx
->context_roll
= true;
1636 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1638 struct si_shader_info
*info
= &shader
->selector
->info
;
1639 struct si_pm4_state
*pm4
;
1640 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1641 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1643 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1645 /* we need to enable at least one of them, otherwise we hang the GPU */
1646 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1647 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1648 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1649 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1650 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1651 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1652 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1653 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1654 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1655 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1656 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1657 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1658 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1659 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1661 /* Validate interpolation optimization flags (read as implications). */
1662 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1663 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1664 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1665 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1666 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1667 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1668 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1669 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1670 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1671 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1672 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1673 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1674 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1675 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1676 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1677 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1678 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1679 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1681 /* Validate cases when the optimizations are off (read as implications). */
1682 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1683 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1684 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1685 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1686 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1687 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1689 pm4
= si_get_shader_pm4_state(shader
);
1693 pm4
->atom
.emit
= si_emit_shader_ps
;
1695 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1697 * 0 -> Position = pixel center
1698 * 1 -> Position = pixel centroid
1699 * 2 -> Position = at sample position
1701 * From GLSL 4.5 specification, section 7.1:
1702 * "The variable gl_FragCoord is available as an input variable from
1703 * within fragment shaders and it holds the window relative coordinates
1704 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1705 * value can be for any location within the pixel, or one of the
1706 * fragment samples. The use of centroid does not further restrict
1707 * this value to be inside the current primitive."
1709 * Meaning that centroid has no effect and we can return anything within
1710 * the pixel. Thus, return the value at sample position, because that's
1711 * the most accurate one shaders can get.
1713 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1715 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1716 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1717 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1719 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1720 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1722 /* Ensure that some export memory is always allocated, for two reasons:
1724 * 1) Correctness: The hardware ignores the EXEC mask if no export
1725 * memory is allocated, so KILL and alpha test do not work correctly
1727 * 2) Performance: Every shader needs at least a NULL export, even when
1728 * it writes no color/depth output. The NULL export instruction
1729 * stalls without this setting.
1731 * Don't add this to CB_SHADER_MASK.
1733 * GFX10 supports pixel shaders without exports by setting both
1734 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1735 * instructions if any are present.
1737 if ((sscreen
->info
.chip_class
<= GFX9
||
1739 shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
) &&
1740 !spi_shader_col_format
&&
1741 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1742 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1744 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1745 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1747 /* Set interpolation controls. */
1748 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
)) |
1749 S_0286D8_PS_W32_EN(sscreen
->ps_wave_size
== 32);
1751 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1752 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1753 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1754 ac_get_spi_shader_z_format(info
->writes_z
,
1755 info
->writes_stencil
,
1756 info
->writes_samplemask
);
1757 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1758 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1760 va
= shader
->bo
->gpu_address
;
1761 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1762 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1763 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1766 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) /
1767 (sscreen
->ps_wave_size
== 32 ? 8 : 4)) |
1768 S_00B028_DX10_CLAMP(1) |
1769 S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1770 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1772 if (sscreen
->info
.chip_class
< GFX10
) {
1773 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1776 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1777 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1778 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1779 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1780 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1783 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1784 struct si_shader
*shader
)
1786 switch (shader
->selector
->type
) {
1787 case PIPE_SHADER_VERTEX
:
1788 if (shader
->key
.as_ls
)
1789 si_shader_ls(sscreen
, shader
);
1790 else if (shader
->key
.as_es
)
1791 si_shader_es(sscreen
, shader
);
1792 else if (shader
->key
.as_ngg
)
1793 gfx10_shader_ngg(sscreen
, shader
);
1795 si_shader_vs(sscreen
, shader
, NULL
);
1797 case PIPE_SHADER_TESS_CTRL
:
1798 si_shader_hs(sscreen
, shader
);
1800 case PIPE_SHADER_TESS_EVAL
:
1801 if (shader
->key
.as_es
)
1802 si_shader_es(sscreen
, shader
);
1803 else if (shader
->key
.as_ngg
)
1804 gfx10_shader_ngg(sscreen
, shader
);
1806 si_shader_vs(sscreen
, shader
, NULL
);
1808 case PIPE_SHADER_GEOMETRY
:
1809 if (shader
->key
.as_ngg
)
1810 gfx10_shader_ngg(sscreen
, shader
);
1812 si_shader_gs(sscreen
, shader
);
1814 case PIPE_SHADER_FRAGMENT
:
1815 si_shader_ps(sscreen
, shader
);
1822 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1824 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1825 return sctx
->queued
.named
.dsa
->alpha_func
;
1828 void si_shader_selector_key_vs(struct si_context
*sctx
,
1829 struct si_shader_selector
*vs
,
1830 struct si_shader_key
*key
,
1831 struct si_vs_prolog_bits
*prolog_key
)
1833 if (!sctx
->vertex_elements
||
1834 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
])
1837 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1839 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1840 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1841 prolog_key
->unpack_instance_id_from_vertex_id
=
1842 sctx
->prim_discard_cs_instancing
;
1844 /* Prefer a monolithic shader to allow scheduling divisions around
1846 if (prolog_key
->instance_divisor_is_fetched
)
1847 key
->opt
.prefer_mono
= 1;
1849 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1850 unsigned count_mask
= (1 << count
) - 1;
1851 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1852 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1854 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1855 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1857 unsigned i
= u_bit_scan(&mask
);
1858 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1859 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1860 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1861 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1862 if (vb
->buffer_offset
& align_mask
||
1863 vb
->stride
& align_mask
) {
1871 unsigned i
= u_bit_scan(&fix
);
1872 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1874 key
->mono
.vs_fetch_opencode
= opencode
;
1877 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1878 struct si_shader_selector
*vs
,
1879 struct si_shader_key
*key
)
1881 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1883 key
->opt
.clip_disable
=
1884 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1885 (vs
->info
.clipdist_writemask
||
1886 vs
->info
.writes_clipvertex
) &&
1887 !vs
->info
.culldist_writemask
;
1889 /* Find out if PS is disabled. */
1890 bool ps_disabled
= true;
1892 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1893 ps
->info
.writes_z
||
1894 ps
->info
.writes_stencil
||
1895 ps
->info
.writes_samplemask
||
1896 sctx
->queued
.named
.blend
->alpha_to_coverage
||
1897 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1898 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1900 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1903 !ps
->info
.writes_memory
);
1906 /* Find out which VS outputs aren't used by the PS. */
1907 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1908 uint64_t inputs_read
= 0;
1910 /* Ignore outputs that are not passed from VS to PS. */
1911 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1912 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1913 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1916 inputs_read
= ps
->inputs_read
;
1919 uint64_t linked
= outputs_written
& inputs_read
;
1921 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1922 key
->opt
.ngg_culling
= sctx
->ngg_culling
;
1925 /* Compute the key for the hw shader variant */
1926 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1927 struct si_shader_selector
*sel
,
1928 union si_vgt_stages_key stages_key
,
1929 struct si_shader_key
*key
)
1931 struct si_context
*sctx
= (struct si_context
*)ctx
;
1933 memset(key
, 0, sizeof(*key
));
1935 switch (sel
->type
) {
1936 case PIPE_SHADER_VERTEX
:
1937 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1939 if (sctx
->tes_shader
.cso
)
1941 else if (sctx
->gs_shader
.cso
) {
1943 key
->as_ngg
= stages_key
.u
.ngg
;
1945 key
->as_ngg
= stages_key
.u
.ngg
;
1946 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1948 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1949 key
->mono
.u
.vs_export_prim_id
= 1;
1952 case PIPE_SHADER_TESS_CTRL
:
1953 if (sctx
->chip_class
>= GFX9
) {
1954 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1955 key
, &key
->part
.tcs
.ls_prolog
);
1956 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1958 /* When the LS VGPR fix is needed, monolithic shaders
1960 * - avoid initializing EXEC in both the LS prolog
1961 * and the LS main part when !vs_needs_prolog
1962 * - remove the fixup for unused input VGPRs
1964 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1966 /* The LS output / HS input layout can be communicated
1967 * directly instead of via user SGPRs for merged LS-HS.
1968 * The LS VGPR fix prefers this too.
1970 key
->opt
.prefer_mono
= 1;
1973 key
->part
.tcs
.epilog
.prim_mode
=
1974 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1975 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1976 sel
->info
.tessfactors_are_def_in_all_invocs
;
1977 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1978 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1980 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1981 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1983 case PIPE_SHADER_TESS_EVAL
:
1984 key
->as_ngg
= stages_key
.u
.ngg
;
1986 if (sctx
->gs_shader
.cso
)
1989 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1991 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1992 key
->mono
.u
.vs_export_prim_id
= 1;
1995 case PIPE_SHADER_GEOMETRY
:
1996 if (sctx
->chip_class
>= GFX9
) {
1997 if (sctx
->tes_shader
.cso
) {
1998 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
2000 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
2001 key
, &key
->part
.gs
.vs_prolog
);
2002 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
2003 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
2006 key
->as_ngg
= stages_key
.u
.ngg
;
2008 /* Merged ES-GS can have unbalanced wave usage.
2010 * ES threads are per-vertex, while GS threads are
2011 * per-primitive. So without any amplification, there
2012 * are fewer GS threads than ES threads, which can result
2013 * in empty (no-op) GS waves. With too much amplification,
2014 * there are more GS threads than ES threads, which
2015 * can result in empty (no-op) ES waves.
2017 * Non-monolithic shaders are implemented by setting EXEC
2018 * at the beginning of shader parts, and don't jump to
2019 * the end if EXEC is 0.
2021 * Monolithic shaders use conditional blocks, so they can
2022 * jump and skip empty waves of ES or GS. So set this to
2023 * always use optimized variants, which are monolithic.
2025 key
->opt
.prefer_mono
= 1;
2027 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
2029 case PIPE_SHADER_FRAGMENT
: {
2030 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
2031 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
2033 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
2034 sel
->info
.colors_written
== 0x1)
2035 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
2037 /* Select the shader color format based on whether
2038 * blending or alpha are needed.
2040 key
->part
.ps
.epilog
.spi_shader_col_format
=
2041 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
2042 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
2043 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
2044 sctx
->framebuffer
.spi_shader_col_format_blend
) |
2045 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
2046 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
2047 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
2048 sctx
->framebuffer
.spi_shader_col_format
);
2049 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
2051 /* The output for dual source blending should have
2052 * the same format as the first output.
2054 if (blend
->dual_src_blend
) {
2055 key
->part
.ps
.epilog
.spi_shader_col_format
|=
2056 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
2059 /* If alpha-to-coverage is enabled, we have to export alpha
2060 * even if there is no color buffer.
2062 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
2063 blend
->alpha_to_coverage
)
2064 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
2066 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
2067 * to the range supported by the type if a channel has less
2068 * than 16 bits and the export format is 16_ABGR.
2070 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
2071 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
2072 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
2075 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
2076 if (!key
->part
.ps
.epilog
.last_cbuf
) {
2077 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
2078 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
2079 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
2082 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
2083 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
2085 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
2086 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
2088 key
->part
.ps
.epilog
.alpha_to_one
= blend
->alpha_to_one
&&
2089 rs
->multisample_enable
;
2091 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
2092 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
2093 (is_line
&& rs
->line_smooth
)) &&
2094 sctx
->framebuffer
.nr_samples
<= 1;
2095 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
2097 if (sctx
->ps_iter_samples
> 1 &&
2098 sel
->info
.reads_samplemask
) {
2099 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
2100 util_logbase2(sctx
->ps_iter_samples
);
2103 if (rs
->force_persample_interp
&&
2104 rs
->multisample_enable
&&
2105 sctx
->framebuffer
.nr_samples
> 1 &&
2106 sctx
->ps_iter_samples
> 1) {
2107 key
->part
.ps
.prolog
.force_persp_sample_interp
=
2108 sel
->info
.uses_persp_center
||
2109 sel
->info
.uses_persp_centroid
;
2111 key
->part
.ps
.prolog
.force_linear_sample_interp
=
2112 sel
->info
.uses_linear_center
||
2113 sel
->info
.uses_linear_centroid
;
2114 } else if (rs
->multisample_enable
&&
2115 sctx
->framebuffer
.nr_samples
> 1) {
2116 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
2117 sel
->info
.uses_persp_center
&&
2118 sel
->info
.uses_persp_centroid
;
2119 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
2120 sel
->info
.uses_linear_center
&&
2121 sel
->info
.uses_linear_centroid
;
2123 /* Make sure SPI doesn't compute more than 1 pair
2124 * of (i,j), which is the optimization here. */
2125 key
->part
.ps
.prolog
.force_persp_center_interp
=
2126 sel
->info
.uses_persp_center
+
2127 sel
->info
.uses_persp_centroid
+
2128 sel
->info
.uses_persp_sample
> 1;
2130 key
->part
.ps
.prolog
.force_linear_center_interp
=
2131 sel
->info
.uses_linear_center
+
2132 sel
->info
.uses_linear_centroid
+
2133 sel
->info
.uses_linear_sample
> 1;
2135 if (sel
->info
.uses_persp_opcode_interp_sample
||
2136 sel
->info
.uses_linear_opcode_interp_sample
)
2137 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
2140 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
2142 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2143 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
2144 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
2145 struct pipe_resource
*tex
= cb0
->texture
;
2147 /* 1D textures are allocated and used as 2D on GFX9. */
2148 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
2149 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
2150 (tex
->target
== PIPE_TEXTURE_1D
||
2151 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
2152 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
2153 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
2154 tex
->target
== PIPE_TEXTURE_CUBE
||
2155 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2156 tex
->target
== PIPE_TEXTURE_3D
;
2164 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
2165 memset(&key
->opt
, 0, sizeof(key
->opt
));
2168 static void si_build_shader_variant(struct si_shader
*shader
,
2172 struct si_shader_selector
*sel
= shader
->selector
;
2173 struct si_screen
*sscreen
= sel
->screen
;
2174 struct ac_llvm_compiler
*compiler
;
2175 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
2177 if (thread_index
>= 0) {
2179 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
2180 compiler
= &sscreen
->compiler_lowp
[thread_index
];
2182 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2183 compiler
= &sscreen
->compiler
[thread_index
];
2188 assert(!low_priority
);
2189 compiler
= shader
->compiler_ctx_state
.compiler
;
2192 if (!compiler
->passes
)
2193 si_init_compiler(sscreen
, compiler
);
2195 if (unlikely(!si_create_shader_variant(sscreen
, compiler
, shader
, debug
))) {
2196 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2198 shader
->compilation_failed
= true;
2202 if (shader
->compiler_ctx_state
.is_debug_context
) {
2203 FILE *f
= open_memstream(&shader
->shader_log
,
2204 &shader
->shader_log_size
);
2206 si_shader_dump(sscreen
, shader
, NULL
, f
, false);
2211 si_shader_init_pm4_state(sscreen
, shader
);
2214 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2216 struct si_shader
*shader
= (struct si_shader
*)job
;
2218 assert(thread_index
>= 0);
2220 si_build_shader_variant(shader
, thread_index
, true);
2223 static const struct si_shader_key zeroed
;
2225 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
2226 struct si_shader_selector
*sel
,
2227 struct si_compiler_ctx_state
*compiler_state
,
2228 struct si_shader_key
*key
)
2230 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2233 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2238 /* We can leave the fence as permanently signaled because the
2239 * main part becomes visible globally only after it has been
2241 util_queue_fence_init(&main_part
->ready
);
2243 main_part
->selector
= sel
;
2244 main_part
->key
.as_es
= key
->as_es
;
2245 main_part
->key
.as_ls
= key
->as_ls
;
2246 main_part
->key
.as_ngg
= key
->as_ngg
;
2247 main_part
->is_monolithic
= false;
2249 if (!si_compile_shader(sscreen
, compiler_state
->compiler
,
2250 main_part
, &compiler_state
->debug
)) {
2260 * Select a shader variant according to the shader key.
2262 * \param optimized_or_none If the key describes an optimized shader variant and
2263 * the compilation isn't finished, don't select any
2264 * shader and return an error.
2266 int si_shader_select_with_key(struct si_screen
*sscreen
,
2267 struct si_shader_ctx_state
*state
,
2268 struct si_compiler_ctx_state
*compiler_state
,
2269 struct si_shader_key
*key
,
2271 bool optimized_or_none
)
2273 struct si_shader_selector
*sel
= state
->cso
;
2274 struct si_shader_selector
*previous_stage_sel
= NULL
;
2275 struct si_shader
*current
= state
->current
;
2276 struct si_shader
*iter
, *shader
= NULL
;
2279 /* Check if we don't need to change anything.
2280 * This path is also used for most shaders that don't need multiple
2281 * variants, it will cost just a computation of the key and this
2283 if (likely(current
&&
2284 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2285 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2286 if (current
->is_optimized
) {
2287 if (optimized_or_none
)
2290 memset(&key
->opt
, 0, sizeof(key
->opt
));
2291 goto current_not_ready
;
2294 util_queue_fence_wait(¤t
->ready
);
2297 return current
->compilation_failed
? -1 : 0;
2301 /* This must be done before the mutex is locked, because async GS
2302 * compilation calls this function too, and therefore must enter
2305 * Only wait if we are in a draw call. Don't wait if we are
2306 * in a compiler thread.
2308 if (thread_index
< 0)
2309 util_queue_fence_wait(&sel
->ready
);
2311 simple_mtx_lock(&sel
->mutex
);
2313 /* Find the shader variant. */
2314 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2315 /* Don't check the "current" shader. We checked it above. */
2316 if (current
!= iter
&&
2317 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2318 simple_mtx_unlock(&sel
->mutex
);
2320 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2321 /* If it's an optimized shader and its compilation has
2322 * been started but isn't done, use the unoptimized
2323 * shader so as not to cause a stall due to compilation.
2325 if (iter
->is_optimized
) {
2326 if (optimized_or_none
)
2328 memset(&key
->opt
, 0, sizeof(key
->opt
));
2332 util_queue_fence_wait(&iter
->ready
);
2335 if (iter
->compilation_failed
) {
2336 return -1; /* skip the draw call */
2339 state
->current
= iter
;
2344 /* Build a new shader. */
2345 shader
= CALLOC_STRUCT(si_shader
);
2347 simple_mtx_unlock(&sel
->mutex
);
2351 util_queue_fence_init(&shader
->ready
);
2353 shader
->selector
= sel
;
2355 shader
->compiler_ctx_state
= *compiler_state
;
2357 /* If this is a merged shader, get the first shader's selector. */
2358 if (sscreen
->info
.chip_class
>= GFX9
) {
2359 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2360 previous_stage_sel
= key
->part
.tcs
.ls
;
2361 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2362 previous_stage_sel
= key
->part
.gs
.es
;
2364 /* We need to wait for the previous shader. */
2365 if (previous_stage_sel
&& thread_index
< 0)
2366 util_queue_fence_wait(&previous_stage_sel
->ready
);
2369 bool is_pure_monolithic
=
2370 sscreen
->use_monolithic_shaders
||
2371 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2373 /* Compile the main shader part if it doesn't exist. This can happen
2374 * if the initial guess was wrong.
2376 * The prim discard CS doesn't need the main shader part.
2378 if (!is_pure_monolithic
&&
2379 !key
->opt
.vs_as_prim_discard_cs
) {
2382 /* Make sure the main shader part is present. This is needed
2383 * for shaders that can be compiled as VS, LS, or ES, and only
2384 * one of them is compiled at creation.
2386 * It is also needed for GS, which can be compiled as non-NGG
2389 * For merged shaders, check that the starting shader's main
2392 if (previous_stage_sel
) {
2393 struct si_shader_key shader1_key
= zeroed
;
2395 if (sel
->type
== PIPE_SHADER_TESS_CTRL
) {
2396 shader1_key
.as_ls
= 1;
2397 } else if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
2398 shader1_key
.as_es
= 1;
2399 shader1_key
.as_ngg
= key
->as_ngg
; /* for Wave32 vs Wave64 */
2404 simple_mtx_lock(&previous_stage_sel
->mutex
);
2405 ok
= si_check_missing_main_part(sscreen
,
2407 compiler_state
, &shader1_key
);
2408 simple_mtx_unlock(&previous_stage_sel
->mutex
);
2412 ok
= si_check_missing_main_part(sscreen
, sel
,
2413 compiler_state
, key
);
2418 simple_mtx_unlock(&sel
->mutex
);
2419 return -ENOMEM
; /* skip the draw call */
2423 /* Keep the reference to the 1st shader of merged shaders, so that
2424 * Gallium can't destroy it before we destroy the 2nd shader.
2426 * Set sctx = NULL, because it's unused if we're not releasing
2427 * the shader, and we don't have any sctx here.
2429 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
2430 previous_stage_sel
);
2432 /* Monolithic-only shaders don't make a distinction between optimized
2433 * and unoptimized. */
2434 shader
->is_monolithic
=
2435 is_pure_monolithic
||
2436 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2438 /* The prim discard CS is always optimized. */
2439 shader
->is_optimized
=
2440 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2441 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2443 /* If it's an optimized shader, compile it asynchronously. */
2444 if (shader
->is_optimized
&& thread_index
< 0) {
2445 /* Compile it asynchronously. */
2446 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
2447 shader
, &shader
->ready
,
2448 si_build_shader_variant_low_priority
, NULL
,
2451 /* Add only after the ready fence was reset, to guard against a
2452 * race with si_bind_XX_shader. */
2453 if (!sel
->last_variant
) {
2454 sel
->first_variant
= shader
;
2455 sel
->last_variant
= shader
;
2457 sel
->last_variant
->next_variant
= shader
;
2458 sel
->last_variant
= shader
;
2461 /* Use the default (unoptimized) shader for now. */
2462 memset(&key
->opt
, 0, sizeof(key
->opt
));
2463 simple_mtx_unlock(&sel
->mutex
);
2465 if (sscreen
->options
.sync_compile
)
2466 util_queue_fence_wait(&shader
->ready
);
2468 if (optimized_or_none
)
2473 /* Reset the fence before adding to the variant list. */
2474 util_queue_fence_reset(&shader
->ready
);
2476 if (!sel
->last_variant
) {
2477 sel
->first_variant
= shader
;
2478 sel
->last_variant
= shader
;
2480 sel
->last_variant
->next_variant
= shader
;
2481 sel
->last_variant
= shader
;
2484 simple_mtx_unlock(&sel
->mutex
);
2486 assert(!shader
->is_optimized
);
2487 si_build_shader_variant(shader
, thread_index
, false);
2489 util_queue_fence_signal(&shader
->ready
);
2491 if (!shader
->compilation_failed
)
2492 state
->current
= shader
;
2494 return shader
->compilation_failed
? -1 : 0;
2497 static int si_shader_select(struct pipe_context
*ctx
,
2498 struct si_shader_ctx_state
*state
,
2499 union si_vgt_stages_key stages_key
,
2500 struct si_compiler_ctx_state
*compiler_state
)
2502 struct si_context
*sctx
= (struct si_context
*)ctx
;
2503 struct si_shader_key key
;
2505 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2506 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2510 static void si_parse_next_shader_property(const struct si_shader_info
*info
,
2512 struct si_shader_key
*key
)
2514 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2516 switch (info
->processor
) {
2517 case PIPE_SHADER_VERTEX
:
2518 switch (next_shader
) {
2519 case PIPE_SHADER_GEOMETRY
:
2522 case PIPE_SHADER_TESS_CTRL
:
2523 case PIPE_SHADER_TESS_EVAL
:
2527 /* If POSITION isn't written, it can only be a HW VS
2528 * if streamout is used. If streamout isn't used,
2529 * assume that it's a HW LS. (the next shader is TCS)
2530 * This heuristic is needed for separate shader objects.
2532 if (!info
->writes_position
&& !streamout
)
2537 case PIPE_SHADER_TESS_EVAL
:
2538 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2539 !info
->writes_position
)
2546 * Compile the main shader part or the monolithic shader as part of
2547 * si_shader_selector initialization. Since it can be done asynchronously,
2548 * there is no way to report compile failures to applications.
2550 static void si_init_shader_selector_async(void *job
, int thread_index
)
2552 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2553 struct si_screen
*sscreen
= sel
->screen
;
2554 struct ac_llvm_compiler
*compiler
;
2555 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2557 assert(!debug
->debug_message
|| debug
->async
);
2558 assert(thread_index
>= 0);
2559 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2560 compiler
= &sscreen
->compiler
[thread_index
];
2562 if (!compiler
->passes
)
2563 si_init_compiler(sscreen
, compiler
);
2565 /* Serialize NIR to save memory. Monolithic shader variants
2566 * have to deserialize NIR before compilation.
2573 /* true = remove optional debugging data to increase
2574 * the likehood of getting more shader cache hits.
2575 * It also drops variable names, so we'll save more memory.
2577 nir_serialize(&blob
, sel
->nir
, true);
2578 blob_finish_get_buffer(&blob
, &sel
->nir_binary
, &size
);
2579 sel
->nir_size
= size
;
2582 /* Compile the main shader part for use with a prolog and/or epilog.
2583 * If this fails, the driver will try to compile a monolithic shader
2586 if (!sscreen
->use_monolithic_shaders
) {
2587 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2588 unsigned char ir_sha1_cache_key
[20];
2591 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2595 /* We can leave the fence signaled because use of the default
2596 * main part is guarded by the selector's ready fence. */
2597 util_queue_fence_init(&shader
->ready
);
2599 shader
->selector
= sel
;
2600 shader
->is_monolithic
= false;
2601 si_parse_next_shader_property(&sel
->info
,
2602 sel
->so
.num_outputs
!= 0,
2605 if (sscreen
->use_ngg
&&
2606 (!sel
->so
.num_outputs
|| sscreen
->use_ngg_streamout
) &&
2607 ((sel
->type
== PIPE_SHADER_VERTEX
&& !shader
->key
.as_ls
) ||
2608 sel
->type
== PIPE_SHADER_TESS_EVAL
||
2609 sel
->type
== PIPE_SHADER_GEOMETRY
))
2610 shader
->key
.as_ngg
= 1;
2613 si_get_ir_cache_key(sel
, shader
->key
.as_ngg
,
2614 shader
->key
.as_es
, ir_sha1_cache_key
);
2617 /* Try to load the shader from the shader cache. */
2618 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2620 if (si_shader_cache_load_shader(sscreen
, ir_sha1_cache_key
, shader
)) {
2621 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2622 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2624 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2626 /* Compile the shader if it hasn't been loaded from the cache. */
2627 if (!si_compile_shader(sscreen
, compiler
, shader
, debug
)) {
2629 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2633 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2634 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
,
2636 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2639 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2641 /* Unset "outputs_written" flags for outputs converted to
2642 * DEFAULT_VAL, so that later inter-shader optimizations don't
2643 * try to eliminate outputs that don't exist in the final
2646 * This is only done if non-monolithic shaders are enabled.
2648 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2649 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2650 !shader
->key
.as_ls
&&
2651 !shader
->key
.as_es
) {
2654 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2655 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2657 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2660 unsigned name
= sel
->info
.output_semantic_name
[i
];
2661 unsigned index
= sel
->info
.output_semantic_index
[i
];
2665 case TGSI_SEMANTIC_GENERIC
:
2666 /* don't process indices the function can't handle */
2667 if (index
>= SI_MAX_IO_GENERIC
)
2671 id
= si_shader_io_get_unique_index(name
, index
, true);
2672 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2674 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2675 case TGSI_SEMANTIC_PSIZE
:
2676 case TGSI_SEMANTIC_CLIPVERTEX
:
2677 case TGSI_SEMANTIC_EDGEFLAG
:
2684 /* The GS copy shader is always pre-compiled. */
2685 if (sel
->type
== PIPE_SHADER_GEOMETRY
&&
2686 (!sscreen
->use_ngg
||
2687 !sscreen
->use_ngg_streamout
|| /* also for PRIMITIVES_GENERATED */
2688 sel
->tess_turns_off_ngg
)) {
2689 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2690 if (!sel
->gs_copy_shader
) {
2691 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2695 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2698 /* Free NIR. We only keep serialized NIR after this point. */
2700 ralloc_free(sel
->nir
);
2705 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2706 struct util_queue_fence
*ready_fence
,
2707 struct si_compiler_ctx_state
*compiler_ctx_state
,
2708 void *job
, util_queue_execute_func execute
)
2710 util_queue_fence_init(ready_fence
);
2712 struct util_async_debug_callback async_debug
;
2714 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2716 si_can_dump_shader(sctx
->screen
, processor
);
2719 u_async_debug_init(&async_debug
);
2720 compiler_ctx_state
->debug
= async_debug
.base
;
2723 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2724 ready_fence
, execute
, NULL
, 0);
2727 util_queue_fence_wait(ready_fence
);
2728 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2729 u_async_debug_cleanup(&async_debug
);
2732 if (sctx
->screen
->options
.sync_compile
)
2733 util_queue_fence_wait(ready_fence
);
2736 /* Return descriptor slot usage masks from the given shader info. */
2737 void si_get_active_slot_masks(const struct si_shader_info
*info
,
2738 uint32_t *const_and_shader_buffers
,
2739 uint64_t *samplers_and_images
)
2741 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_msaa_images
, num_samplers
;
2743 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2744 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2745 /* two 8-byte images share one 16-byte slot */
2746 num_images
= align(util_last_bit(info
->images_declared
), 2);
2747 num_msaa_images
= align(util_last_bit(info
->msaa_images_declared
), 2);
2748 num_samplers
= util_last_bit(info
->samplers_declared
);
2750 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2751 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2752 *const_and_shader_buffers
=
2753 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2756 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2757 * - image[last] ... image[0] go to [31-last .. 31]
2758 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2760 * FMASKs for images are placed separately, because MSAA images are rare,
2761 * and so we can benefit from a better cache hit rate if we keep image
2762 * descriptors together.
2764 if (num_msaa_images
)
2765 num_images
= SI_NUM_IMAGES
+ num_msaa_images
; /* add FMASK descriptors */
2767 start
= si_get_image_slot(num_images
- 1) / 2;
2768 *samplers_and_images
=
2769 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2772 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2773 const struct pipe_shader_state
*state
)
2775 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2776 struct si_context
*sctx
= (struct si_context
*)ctx
;
2777 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2783 sel
->screen
= sscreen
;
2784 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2785 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2787 sel
->so
= state
->stream_output
;
2789 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2790 sel
->nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
2792 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2793 sel
->nir
= state
->ir
.nir
;
2796 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2797 si_nir_adjust_driver_locations(sel
->nir
);
2799 sel
->type
= sel
->info
.processor
;
2800 p_atomic_inc(&sscreen
->num_shaders_created
);
2801 si_get_active_slot_masks(&sel
->info
,
2802 &sel
->active_const_and_shader_buffers
,
2803 &sel
->active_samplers_and_images
);
2805 /* Record which streamout buffers are enabled. */
2806 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2807 sel
->enabled_streamout_buffer_mask
|=
2808 (1 << sel
->so
.output
[i
].output_buffer
) <<
2809 (sel
->so
.output
[i
].stream
* 4);
2812 sel
->num_vs_inputs
= sel
->type
== PIPE_SHADER_VERTEX
&&
2813 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] ?
2814 sel
->info
.num_inputs
: 0;
2815 sel
->num_vbos_in_user_sgprs
=
2816 MIN2(sel
->num_vs_inputs
, sscreen
->num_vbos_in_user_sgprs
);
2818 /* The prolog is a no-op if there are no inputs. */
2819 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2820 sel
->info
.num_inputs
&&
2821 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
2823 sel
->force_correct_derivs_after_kill
=
2824 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2825 sel
->info
.uses_derivatives
&&
2826 sel
->info
.uses_kill
&&
2827 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2829 sel
->prim_discard_cs_allowed
=
2830 sel
->type
== PIPE_SHADER_VERTEX
&&
2831 !sel
->info
.uses_bindless_images
&&
2832 !sel
->info
.uses_bindless_samplers
&&
2833 !sel
->info
.writes_memory
&&
2834 !sel
->info
.writes_viewport_index
&&
2835 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2836 !sel
->so
.num_outputs
;
2838 switch (sel
->type
) {
2839 case PIPE_SHADER_GEOMETRY
:
2840 sel
->gs_output_prim
=
2841 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2843 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2844 sel
->rast_prim
= sel
->gs_output_prim
;
2845 if (util_rast_prim_is_triangles(sel
->rast_prim
))
2846 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2848 sel
->gs_max_out_vertices
=
2849 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2850 sel
->gs_num_invocations
=
2851 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2852 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2853 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2854 sel
->gs_max_out_vertices
;
2856 sel
->max_gs_stream
= 0;
2857 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2858 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2859 sel
->so
.output
[i
].stream
);
2861 sel
->gs_input_verts_per_prim
=
2862 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2864 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2865 sel
->tess_turns_off_ngg
=
2866 sscreen
->info
.chip_class
== GFX10
&&
2867 sel
->gs_num_invocations
* sel
->gs_max_out_vertices
> 256;
2870 case PIPE_SHADER_TESS_CTRL
:
2871 /* Always reserve space for these. */
2872 sel
->patch_outputs_written
|=
2873 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2874 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2876 case PIPE_SHADER_VERTEX
:
2877 case PIPE_SHADER_TESS_EVAL
:
2878 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2879 unsigned name
= sel
->info
.output_semantic_name
[i
];
2880 unsigned index
= sel
->info
.output_semantic_index
[i
];
2883 case TGSI_SEMANTIC_TESSINNER
:
2884 case TGSI_SEMANTIC_TESSOUTER
:
2885 case TGSI_SEMANTIC_PATCH
:
2886 sel
->patch_outputs_written
|=
2887 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2890 case TGSI_SEMANTIC_GENERIC
:
2891 /* don't process indices the function can't handle */
2892 if (index
>= SI_MAX_IO_GENERIC
)
2896 sel
->outputs_written
|=
2897 1ull << si_shader_io_get_unique_index(name
, index
, false);
2898 sel
->outputs_written_before_ps
|=
2899 1ull << si_shader_io_get_unique_index(name
, index
, true);
2901 case TGSI_SEMANTIC_EDGEFLAG
:
2905 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2906 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2908 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2909 * will start on a different bank. (except for the maximum 32*16).
2911 if (sel
->lshs_vertex_stride
< 32*16)
2912 sel
->lshs_vertex_stride
+= 4;
2914 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2915 * conflicts, i.e. each vertex will start at a different bank.
2917 if (sctx
->chip_class
>= GFX9
)
2918 sel
->esgs_itemsize
+= 4;
2920 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2923 if (sel
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
2924 sel
->rast_prim
= PIPE_PRIM_POINTS
;
2925 else if (sel
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
2926 sel
->rast_prim
= PIPE_PRIM_LINE_STRIP
;
2928 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2931 case PIPE_SHADER_FRAGMENT
:
2932 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2933 unsigned name
= sel
->info
.input_semantic_name
[i
];
2934 unsigned index
= sel
->info
.input_semantic_index
[i
];
2937 case TGSI_SEMANTIC_GENERIC
:
2938 /* don't process indices the function can't handle */
2939 if (index
>= SI_MAX_IO_GENERIC
)
2944 1ull << si_shader_io_get_unique_index(name
, index
, true);
2946 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2951 for (i
= 0; i
< 8; i
++)
2952 if (sel
->info
.colors_written
& (1 << i
))
2953 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2955 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2956 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2957 int index
= sel
->info
.input_semantic_index
[i
];
2958 sel
->color_attr_index
[index
] = i
;
2965 sel
->ngg_culling_allowed
=
2966 sscreen
->info
.chip_class
== GFX10
&&
2967 sscreen
->info
.has_dedicated_vram
&&
2968 sscreen
->use_ngg_culling
&&
2969 /* Disallow TES by default, because TessMark results are mixed. */
2970 (sel
->type
== PIPE_SHADER_VERTEX
||
2971 (sscreen
->always_use_ngg_culling
&& sel
->type
== PIPE_SHADER_TESS_EVAL
)) &&
2972 sel
->info
.writes_position
&&
2973 !sel
->info
.writes_viewport_index
&& /* cull only against viewport 0 */
2974 !sel
->info
.writes_memory
&&
2975 !sel
->so
.num_outputs
&&
2976 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] &&
2977 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
2979 /* PA_CL_VS_OUT_CNTL */
2980 if (sctx
->chip_class
<= GFX9
)
2981 sel
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(sel
, false);
2983 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2984 SIX_BITS
: sel
->info
.clipdist_writemask
;
2985 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2986 sel
->info
.num_written_clipdistance
;
2988 /* DB_SHADER_CONTROL */
2989 sel
->db_shader_control
=
2990 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2991 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2992 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2993 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2995 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2996 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2997 sel
->db_shader_control
|=
2998 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
3000 case TGSI_FS_DEPTH_LAYOUT_LESS
:
3001 sel
->db_shader_control
|=
3002 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
3006 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
3008 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
3009 * --|-----------|------------|------------|--------------------|-------------------|-------------
3010 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
3011 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
3012 * 2 | false | true | n/a | LateZ | 1 | 0
3013 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
3014 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
3016 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
3017 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
3019 * Don't use ReZ without profiling !!!
3021 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
3024 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
3026 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
3027 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
3028 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
3029 } else if (sel
->info
.writes_memory
) {
3031 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
3032 S_02880C_EXEC_ON_HIER_FAIL(1);
3035 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
3038 if (sel
->info
.properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
])
3039 sel
->db_shader_control
|= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
3041 (void) simple_mtx_init(&sel
->mutex
, mtx_plain
);
3043 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
3044 &sel
->compiler_ctx_state
, sel
,
3045 si_init_shader_selector_async
);
3049 static void *si_create_shader(struct pipe_context
*ctx
,
3050 const struct pipe_shader_state
*state
)
3052 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
3054 return util_live_shader_cache_get(ctx
, &sscreen
->live_shader_cache
, state
);
3057 static void si_update_streamout_state(struct si_context
*sctx
)
3059 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
3061 if (!shader_with_so
)
3064 sctx
->streamout
.enabled_stream_buffers_mask
=
3065 shader_with_so
->enabled_streamout_buffer_mask
;
3066 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
3069 static void si_update_clip_regs(struct si_context
*sctx
,
3070 struct si_shader_selector
*old_hw_vs
,
3071 struct si_shader
*old_hw_vs_variant
,
3072 struct si_shader_selector
*next_hw_vs
,
3073 struct si_shader
*next_hw_vs_variant
)
3077 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
3078 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
3079 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
3080 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
3081 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
3082 !old_hw_vs_variant
||
3083 !next_hw_vs_variant
||
3084 old_hw_vs_variant
->key
.opt
.clip_disable
!=
3085 next_hw_vs_variant
->key
.opt
.clip_disable
))
3086 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3089 static void si_update_common_shader_state(struct si_context
*sctx
)
3091 sctx
->uses_bindless_samplers
=
3092 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
3093 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
3094 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
3095 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
3096 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
3097 sctx
->uses_bindless_images
=
3098 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
3099 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
3100 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
3101 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
3102 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
3103 sctx
->do_update_shaders
= true;
3106 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
3108 struct si_context
*sctx
= (struct si_context
*)ctx
;
3109 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3110 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3111 struct si_shader_selector
*sel
= state
;
3113 if (sctx
->vs_shader
.cso
== sel
)
3116 sctx
->vs_shader
.cso
= sel
;
3117 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3118 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] : 0;
3120 if (si_update_ngg(sctx
))
3121 si_shader_change_notify(sctx
);
3123 si_update_common_shader_state(sctx
);
3124 si_update_vs_viewport_state(sctx
);
3125 si_set_active_descriptors_for_shader(sctx
, sel
);
3126 si_update_streamout_state(sctx
);
3127 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3128 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3131 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
3133 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
3134 (sctx
->tes_shader
.cso
&&
3135 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
3136 (sctx
->tcs_shader
.cso
&&
3137 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
3138 (sctx
->gs_shader
.cso
&&
3139 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
3140 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
3141 sctx
->ps_shader
.cso
->info
.uses_primid
);
3144 bool si_update_ngg(struct si_context
*sctx
)
3146 if (!sctx
->screen
->use_ngg
) {
3151 bool new_ngg
= true;
3153 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&&
3154 sctx
->gs_shader
.cso
->tess_turns_off_ngg
) {
3156 } else if (!sctx
->screen
->use_ngg_streamout
) {
3157 struct si_shader_selector
*last
= si_get_vs(sctx
)->cso
;
3159 if ((last
&& last
->so
.num_outputs
) ||
3160 sctx
->streamout
.prims_gen_query_enabled
)
3164 if (new_ngg
!= sctx
->ngg
) {
3165 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3166 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3169 if ((sctx
->family
== CHIP_NAVI10
||
3170 sctx
->family
== CHIP_NAVI12
||
3171 sctx
->family
== CHIP_NAVI14
) &&
3173 sctx
->flags
|= SI_CONTEXT_VGT_FLUSH
;
3175 sctx
->ngg
= new_ngg
;
3176 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
3182 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
3184 struct si_context
*sctx
= (struct si_context
*)ctx
;
3185 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3186 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3187 struct si_shader_selector
*sel
= state
;
3188 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
3191 if (sctx
->gs_shader
.cso
== sel
)
3194 sctx
->gs_shader
.cso
= sel
;
3195 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3196 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
3198 si_update_common_shader_state(sctx
);
3199 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
3201 ngg_changed
= si_update_ngg(sctx
);
3202 if (ngg_changed
|| enable_changed
)
3203 si_shader_change_notify(sctx
);
3204 if (enable_changed
) {
3205 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3206 si_update_tess_uses_prim_id(sctx
);
3208 si_update_vs_viewport_state(sctx
);
3209 si_set_active_descriptors_for_shader(sctx
, sel
);
3210 si_update_streamout_state(sctx
);
3211 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3212 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3215 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
3217 struct si_context
*sctx
= (struct si_context
*)ctx
;
3218 struct si_shader_selector
*sel
= state
;
3219 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
3221 if (sctx
->tcs_shader
.cso
== sel
)
3224 sctx
->tcs_shader
.cso
= sel
;
3225 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3226 si_update_tess_uses_prim_id(sctx
);
3228 si_update_common_shader_state(sctx
);
3231 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
3233 si_set_active_descriptors_for_shader(sctx
, sel
);
3236 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
3238 struct si_context
*sctx
= (struct si_context
*)ctx
;
3239 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3240 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3241 struct si_shader_selector
*sel
= state
;
3242 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
3244 if (sctx
->tes_shader
.cso
== sel
)
3247 sctx
->tes_shader
.cso
= sel
;
3248 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
3249 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
3250 si_update_tess_uses_prim_id(sctx
);
3252 si_update_common_shader_state(sctx
);
3253 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
3255 bool ngg_changed
= si_update_ngg(sctx
);
3256 if (ngg_changed
|| enable_changed
)
3257 si_shader_change_notify(sctx
);
3259 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
3260 si_update_vs_viewport_state(sctx
);
3261 si_set_active_descriptors_for_shader(sctx
, sel
);
3262 si_update_streamout_state(sctx
);
3263 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3264 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3267 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3269 struct si_context
*sctx
= (struct si_context
*)ctx
;
3270 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3271 struct si_shader_selector
*sel
= state
;
3273 /* skip if supplied shader is one already in use */
3277 sctx
->ps_shader
.cso
= sel
;
3278 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3280 si_update_common_shader_state(sctx
);
3282 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3283 si_update_tess_uses_prim_id(sctx
);
3286 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3287 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3289 if (sctx
->screen
->has_out_of_order_rast
&&
3291 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
3292 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
3293 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
3294 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3296 si_set_active_descriptors_for_shader(sctx
, sel
);
3297 si_update_ps_colorbuf0_slot(sctx
);
3300 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3302 if (shader
->is_optimized
) {
3303 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
3307 util_queue_fence_destroy(&shader
->ready
);
3310 /* If destroyed shaders were not unbound, the next compiled
3311 * shader variant could get the same pointer address and so
3312 * binding it to the same shader stage would be considered
3313 * a no-op, causing random behavior.
3315 switch (shader
->selector
->type
) {
3316 case PIPE_SHADER_VERTEX
:
3317 if (shader
->key
.as_ls
) {
3318 assert(sctx
->chip_class
<= GFX8
);
3319 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3320 } else if (shader
->key
.as_es
) {
3321 assert(sctx
->chip_class
<= GFX8
);
3322 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3323 } else if (shader
->key
.as_ngg
) {
3324 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3326 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3329 case PIPE_SHADER_TESS_CTRL
:
3330 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3332 case PIPE_SHADER_TESS_EVAL
:
3333 if (shader
->key
.as_es
) {
3334 assert(sctx
->chip_class
<= GFX8
);
3335 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3336 } else if (shader
->key
.as_ngg
) {
3337 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3339 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3342 case PIPE_SHADER_GEOMETRY
:
3343 if (shader
->is_gs_copy_shader
)
3344 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3346 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3348 case PIPE_SHADER_FRAGMENT
:
3349 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3355 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3356 si_shader_destroy(shader
);
3360 static void si_destroy_shader_selector(struct pipe_context
*ctx
, void *cso
)
3362 struct si_context
*sctx
= (struct si_context
*)ctx
;
3363 struct si_shader_selector
*sel
= (struct si_shader_selector
*)cso
;
3364 struct si_shader
*p
= sel
->first_variant
, *c
;
3365 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3366 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
3367 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3368 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3369 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3370 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3373 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3375 if (current_shader
[sel
->type
]->cso
== sel
) {
3376 current_shader
[sel
->type
]->cso
= NULL
;
3377 current_shader
[sel
->type
]->current
= NULL
;
3381 c
= p
->next_variant
;
3382 si_delete_shader(sctx
, p
);
3386 if (sel
->main_shader_part
)
3387 si_delete_shader(sctx
, sel
->main_shader_part
);
3388 if (sel
->main_shader_part_ls
)
3389 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3390 if (sel
->main_shader_part_es
)
3391 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3392 if (sel
->main_shader_part_ngg
)
3393 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3394 if (sel
->gs_copy_shader
)
3395 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3397 util_queue_fence_destroy(&sel
->ready
);
3398 simple_mtx_destroy(&sel
->mutex
);
3399 ralloc_free(sel
->nir
);
3400 free(sel
->nir_binary
);
3404 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3406 struct si_context
*sctx
= (struct si_context
*)ctx
;
3407 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3409 si_shader_selector_reference(sctx
, &sel
, NULL
);
3412 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
3413 struct si_shader
*vs
, unsigned name
,
3414 unsigned index
, unsigned interpolate
)
3416 struct si_shader_info
*vsinfo
= &vs
->selector
->info
;
3417 unsigned j
, offset
, ps_input_cntl
= 0;
3419 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3420 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
3421 name
== TGSI_SEMANTIC_PRIMID
)
3422 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3424 if (name
== TGSI_SEMANTIC_PCOORD
||
3425 (name
== TGSI_SEMANTIC_TEXCOORD
&&
3426 sctx
->sprite_coord_enable
& (1 << index
))) {
3427 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3430 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
3431 if (name
== vsinfo
->output_semantic_name
[j
] &&
3432 index
== vsinfo
->output_semantic_index
[j
]) {
3433 offset
= vs
->info
.vs_output_param_offset
[j
];
3435 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3436 /* The input is loaded from parameter memory. */
3437 ps_input_cntl
|= S_028644_OFFSET(offset
);
3438 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3439 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3440 /* This can happen with depth-only rendering. */
3443 /* The input is a DEFAULT_VAL constant. */
3444 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3445 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3446 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3449 ps_input_cntl
= S_028644_OFFSET(0x20) |
3450 S_028644_DEFAULT_VAL(offset
);
3456 if (j
== vsinfo
->num_outputs
&& name
== TGSI_SEMANTIC_PRIMID
)
3457 /* PrimID is written after the last output when HW VS is used. */
3458 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3459 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3460 /* No corresponding output found, load defaults into input.
3461 * Don't set any other bits.
3462 * (FLAT_SHADE=1 completely changes behavior) */
3463 ps_input_cntl
= S_028644_OFFSET(0x20);
3464 /* D3D 9 behaviour. GL is undefined */
3465 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
3466 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3468 return ps_input_cntl
;
3471 static void si_emit_spi_map(struct si_context
*sctx
)
3473 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3474 struct si_shader
*vs
= si_get_vs_state(sctx
);
3475 struct si_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3476 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
3477 unsigned spi_ps_input_cntl
[32];
3479 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3482 num_interp
= si_get_ps_num_interp(ps
);
3483 assert(num_interp
> 0);
3485 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3486 unsigned name
= psinfo
->input_semantic_name
[i
];
3487 unsigned index
= psinfo
->input_semantic_index
[i
];
3488 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3490 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
3491 index
, interpolate
);
3493 if (name
== TGSI_SEMANTIC_COLOR
) {
3494 assert(index
< ARRAY_SIZE(bcol_interp
));
3495 bcol_interp
[index
] = interpolate
;
3499 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3500 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
3502 for (i
= 0; i
< 2; i
++) {
3503 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3506 spi_ps_input_cntl
[num_written
++] =
3507 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
3511 assert(num_interp
== num_written
);
3513 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3514 /* Dota 2: Only ~16% of SPI map updates set different values. */
3515 /* Talos: Only ~9% of SPI map updates set different values. */
3516 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3517 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
3519 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3521 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3522 sctx
->context_roll
= true;
3526 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3528 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
3530 if (sctx
->init_config_has_vgt_flush
)
3533 /* Done by Vulkan before VGT_FLUSH. */
3534 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3535 si_pm4_cmd_add(sctx
->init_config
,
3536 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3537 si_pm4_cmd_end(sctx
->init_config
, false);
3539 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3540 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3541 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3542 si_pm4_cmd_end(sctx
->init_config
, false);
3543 sctx
->init_config_has_vgt_flush
= true;
3546 /* Initialize state related to ESGS / GSVS ring buffers */
3547 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3549 struct si_shader_selector
*es
=
3550 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3551 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3552 struct si_pm4_state
*pm4
;
3554 /* Chip constants. */
3555 unsigned num_se
= sctx
->screen
->info
.max_se
;
3556 unsigned wave_size
= 64;
3557 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3558 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3559 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3561 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3562 unsigned alignment
= 256 * num_se
;
3563 /* The maximum size is 63.999 MB per SE. */
3564 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3566 /* Calculate the minimum size. */
3567 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
3568 wave_size
, alignment
);
3570 /* These are recommended sizes, not minimum sizes. */
3571 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
3572 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3573 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
3574 gs
->max_gsvs_emit_size
;
3576 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3577 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3578 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3580 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3581 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3583 /* Some rings don't have to be allocated if shaders don't use them.
3584 * (e.g. no varyings between ES and GS or GS and VS)
3586 * GFX9 doesn't have the ESGS ring.
3588 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
3590 (!sctx
->esgs_ring
||
3591 sctx
->esgs_ring
->width0
< esgs_ring_size
);
3592 bool update_gsvs
= gsvs_ring_size
&&
3593 (!sctx
->gsvs_ring
||
3594 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3596 if (!update_esgs
&& !update_gsvs
)
3600 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3602 pipe_aligned_buffer_create(sctx
->b
.screen
,
3603 SI_RESOURCE_FLAG_UNMAPPABLE
,
3606 sctx
->screen
->info
.pte_fragment_size
);
3607 if (!sctx
->esgs_ring
)
3612 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3614 pipe_aligned_buffer_create(sctx
->b
.screen
,
3615 SI_RESOURCE_FLAG_UNMAPPABLE
,
3618 sctx
->screen
->info
.pte_fragment_size
);
3619 if (!sctx
->gsvs_ring
)
3623 /* Create the "init_config_gs_rings" state. */
3624 pm4
= CALLOC_STRUCT(si_pm4_state
);
3628 if (sctx
->chip_class
>= GFX7
) {
3629 if (sctx
->esgs_ring
) {
3630 assert(sctx
->chip_class
<= GFX8
);
3631 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3632 sctx
->esgs_ring
->width0
/ 256);
3634 if (sctx
->gsvs_ring
)
3635 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3636 sctx
->gsvs_ring
->width0
/ 256);
3638 if (sctx
->esgs_ring
)
3639 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3640 sctx
->esgs_ring
->width0
/ 256);
3641 if (sctx
->gsvs_ring
)
3642 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3643 sctx
->gsvs_ring
->width0
/ 256);
3646 /* Set the state. */
3647 if (sctx
->init_config_gs_rings
)
3648 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3649 sctx
->init_config_gs_rings
= pm4
;
3651 if (!sctx
->init_config_has_vgt_flush
) {
3652 si_init_config_add_vgt_flush(sctx
);
3653 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3656 /* Flush the context to re-emit both init_config states. */
3657 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3658 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3660 /* Set ring bindings. */
3661 if (sctx
->esgs_ring
) {
3662 assert(sctx
->chip_class
<= GFX8
);
3663 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3664 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3665 true, true, 4, 64, 0);
3666 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3667 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3668 false, false, 0, 0, 0);
3670 if (sctx
->gsvs_ring
) {
3671 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3672 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3673 false, false, 0, 0, 0);
3679 static void si_shader_lock(struct si_shader
*shader
)
3681 simple_mtx_lock(&shader
->selector
->mutex
);
3682 if (shader
->previous_stage_sel
) {
3683 assert(shader
->previous_stage_sel
!= shader
->selector
);
3684 simple_mtx_lock(&shader
->previous_stage_sel
->mutex
);
3688 static void si_shader_unlock(struct si_shader
*shader
)
3690 if (shader
->previous_stage_sel
)
3691 simple_mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3692 simple_mtx_unlock(&shader
->selector
->mutex
);
3696 * @returns 1 if \p sel has been updated to use a new scratch buffer
3698 * < 0 if there was a failure
3700 static int si_update_scratch_buffer(struct si_context
*sctx
,
3701 struct si_shader
*shader
)
3703 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3708 /* This shader doesn't need a scratch buffer */
3709 if (shader
->config
.scratch_bytes_per_wave
== 0)
3712 /* Prevent race conditions when updating:
3713 * - si_shader::scratch_bo
3714 * - si_shader::binary::code
3715 * - si_shader::previous_stage::binary::code.
3717 si_shader_lock(shader
);
3719 /* This shader is already configured to use the current
3720 * scratch buffer. */
3721 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3722 si_shader_unlock(shader
);
3726 assert(sctx
->scratch_buffer
);
3728 /* Replace the shader bo with a new bo that has the relocs applied. */
3729 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3730 si_shader_unlock(shader
);
3734 /* Update the shader state to use the new shader bo. */
3735 si_shader_init_pm4_state(sctx
->screen
, shader
);
3737 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3739 si_shader_unlock(shader
);
3743 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3745 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3748 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3750 if (!sctx
->tes_shader
.cso
)
3751 return NULL
; /* tessellation disabled */
3753 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3754 sctx
->fixed_func_tcs_shader
.current
;
3757 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3759 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3762 /* Update the shaders, so that they are using the latest scratch.
3763 * The scratch buffer may have been changed since these shaders were
3764 * last used, so we still need to try to update them, even if they
3765 * require scratch buffers smaller than the current size.
3767 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3771 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3773 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3777 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3779 r
= si_update_scratch_buffer(sctx
, tcs
);
3783 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3785 /* VS can be bound as LS, ES, or VS. */
3786 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3790 if (sctx
->vs_shader
.current
->key
.as_ls
)
3791 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3792 else if (sctx
->vs_shader
.current
->key
.as_es
)
3793 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3794 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3795 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3797 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3800 /* TES can be bound as ES or VS. */
3801 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3805 if (sctx
->tes_shader
.current
->key
.as_es
)
3806 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3807 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3808 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3810 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3816 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3818 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3819 * There are 2 cases to handle:
3821 * - If the current needed size is less than the maximum seen size,
3822 * use the maximum seen size, so that WAVESIZE remains the same.
3824 * - If the current needed size is greater than the maximum seen size,
3825 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3827 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3828 * Otherwise, the number of waves that can use scratch is
3829 * SPI_TMPRING_SIZE.WAVES.
3833 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3834 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3835 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3837 if (sctx
->tes_shader
.cso
) {
3838 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3839 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx
)));
3842 sctx
->max_seen_scratch_bytes_per_wave
=
3843 MAX2(sctx
->max_seen_scratch_bytes_per_wave
, bytes
);
3845 unsigned scratch_needed_size
=
3846 sctx
->max_seen_scratch_bytes_per_wave
* sctx
->scratch_waves
;
3847 unsigned spi_tmpring_size
;
3849 if (scratch_needed_size
> 0) {
3850 if (!sctx
->scratch_buffer
||
3851 scratch_needed_size
> sctx
->scratch_buffer
->b
.b
.width0
) {
3852 /* Create a bigger scratch buffer */
3853 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3855 sctx
->scratch_buffer
=
3856 si_aligned_buffer_create(&sctx
->screen
->b
,
3857 SI_RESOURCE_FLAG_UNMAPPABLE
,
3859 scratch_needed_size
,
3860 sctx
->screen
->info
.pte_fragment_size
);
3861 if (!sctx
->scratch_buffer
)
3864 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3865 si_context_add_resource_size(sctx
,
3866 &sctx
->scratch_buffer
->b
.b
);
3869 if (!si_update_scratch_relocs(sctx
))
3873 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3874 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3875 "scratch size should already be aligned correctly.");
3877 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3878 S_0286E8_WAVESIZE(sctx
->max_seen_scratch_bytes_per_wave
>> 10);
3879 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3880 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3881 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3886 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3888 assert(!sctx
->tess_rings
);
3889 assert(((sctx
->screen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
3891 /* The address must be aligned to 2^19, because the shader only
3892 * receives the high 13 bits.
3894 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3895 SI_RESOURCE_FLAG_32BIT
,
3897 sctx
->screen
->tess_offchip_ring_size
+
3898 sctx
->screen
->tess_factor_ring_size
,
3900 if (!sctx
->tess_rings
)
3903 si_init_config_add_vgt_flush(sctx
);
3905 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3906 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3908 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3909 sctx
->screen
->tess_offchip_ring_size
;
3911 /* Append these registers to the init config state. */
3912 if (sctx
->chip_class
>= GFX7
) {
3913 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3914 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3915 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3917 if (sctx
->chip_class
>= GFX10
)
3918 si_pm4_set_reg(sctx
->init_config
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3919 S_030984_BASE_HI(factor_va
>> 40));
3920 else if (sctx
->chip_class
== GFX9
)
3921 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3922 S_030944_BASE_HI(factor_va
>> 40));
3923 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3924 sctx
->screen
->vgt_hs_offchip_param
);
3926 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3927 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3928 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3930 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3931 sctx
->screen
->vgt_hs_offchip_param
);
3934 /* Flush the context to re-emit the init_config state.
3935 * This is done only once in a lifetime of a context.
3937 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3938 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3939 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3942 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3943 union si_vgt_stages_key key
)
3945 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3946 uint32_t stages
= 0;
3949 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3950 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3953 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3956 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3958 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3959 } else if (key
.u
.gs
) {
3960 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3962 } else if (key
.u
.ngg
) {
3963 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3967 stages
|= S_028B54_PRIMGEN_EN(1) |
3968 S_028B54_GS_FAST_LAUNCH(key
.u
.ngg_gs_fast_launch
) |
3969 S_028B54_NGG_WAVE_ID_EN(key
.u
.streamout
) |
3970 S_028B54_PRIMGEN_PASSTHRU_EN(key
.u
.ngg_passthrough
);
3971 } else if (key
.u
.gs
)
3972 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3974 if (screen
->info
.chip_class
>= GFX9
)
3975 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3977 if (screen
->info
.chip_class
>= GFX10
&& screen
->ge_wave_size
== 32) {
3978 stages
|= S_028B54_HS_W32_EN(1) |
3979 S_028B54_GS_W32_EN(key
.u
.ngg
) | /* legacy GS only supports Wave64 */
3980 S_028B54_VS_W32_EN(1);
3983 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3987 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3988 union si_vgt_stages_key key
)
3990 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3992 if (unlikely(!*pm4
))
3993 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3994 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3997 bool si_update_shaders(struct si_context
*sctx
)
3999 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
4000 struct si_compiler_ctx_state compiler_state
;
4001 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
4002 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
4003 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
4004 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
4005 union si_vgt_stages_key key
;
4006 unsigned old_spi_shader_col_format
=
4007 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
4010 if (!sctx
->compiler
.passes
)
4011 si_init_compiler(sctx
->screen
, &sctx
->compiler
);
4013 compiler_state
.compiler
= &sctx
->compiler
;
4014 compiler_state
.debug
= sctx
->debug
;
4015 compiler_state
.is_debug_context
= sctx
->is_debug
;
4019 if (sctx
->tes_shader
.cso
)
4021 if (sctx
->gs_shader
.cso
)
4026 key
.u
.streamout
= !!si_get_vs(sctx
)->cso
->so
.num_outputs
;
4029 /* Update TCS and TES. */
4030 if (sctx
->tes_shader
.cso
) {
4031 if (!sctx
->tess_rings
) {
4032 si_init_tess_factor_ring(sctx
);
4033 if (!sctx
->tess_rings
)
4037 if (sctx
->tcs_shader
.cso
) {
4038 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
,
4042 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
4044 if (!sctx
->fixed_func_tcs_shader
.cso
) {
4045 sctx
->fixed_func_tcs_shader
.cso
=
4046 si_create_fixed_func_tcs(sctx
);
4047 if (!sctx
->fixed_func_tcs_shader
.cso
)
4051 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
4052 key
, &compiler_state
);
4055 si_pm4_bind_state(sctx
, hs
,
4056 sctx
->fixed_func_tcs_shader
.current
->pm4
);
4059 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
4060 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
4064 if (sctx
->gs_shader
.cso
) {
4066 assert(sctx
->chip_class
<= GFX8
);
4067 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
4068 } else if (key
.u
.ngg
) {
4069 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
4071 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
4075 if (sctx
->chip_class
<= GFX8
)
4076 si_pm4_bind_state(sctx
, ls
, NULL
);
4077 si_pm4_bind_state(sctx
, hs
, NULL
);
4081 if (sctx
->gs_shader
.cso
) {
4082 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
4085 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
4087 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
4089 if (!si_update_gs_ring_buffers(sctx
))
4092 si_pm4_bind_state(sctx
, vs
, NULL
);
4096 si_pm4_bind_state(sctx
, gs
, NULL
);
4097 if (sctx
->chip_class
<= GFX8
)
4098 si_pm4_bind_state(sctx
, es
, NULL
);
4103 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
4104 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
4108 if (!key
.u
.tess
&& !key
.u
.gs
) {
4110 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
4111 si_pm4_bind_state(sctx
, vs
, NULL
);
4113 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
4115 } else if (sctx
->tes_shader
.cso
) {
4116 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
4118 assert(sctx
->gs_shader
.cso
);
4119 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
4123 /* This must be done after the shader variant is selected. */
4125 struct si_shader
*vs
= si_get_vs(sctx
)->current
;
4127 key
.u
.ngg_passthrough
= gfx10_is_ngg_passthrough(vs
);
4128 key
.u
.ngg_gs_fast_launch
= !!(vs
->key
.opt
.ngg_culling
&
4129 SI_NGG_CULL_GS_FAST_LAUNCH_ALL
);
4132 si_update_vgt_shader_config(sctx
, key
);
4134 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
4135 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
4137 if (sctx
->ps_shader
.cso
) {
4138 unsigned db_shader_control
;
4140 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
4143 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
4146 sctx
->ps_shader
.cso
->db_shader_control
|
4147 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
4149 if (si_pm4_state_changed(sctx
, ps
) ||
4150 si_pm4_state_changed(sctx
, vs
) ||
4151 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
4152 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
4153 sctx
->flatshade
!= rs
->flatshade
) {
4154 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
4155 sctx
->flatshade
= rs
->flatshade
;
4156 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
4159 if (sctx
->screen
->info
.rbplus_allowed
&&
4160 si_pm4_state_changed(sctx
, ps
) &&
4162 old_spi_shader_col_format
!=
4163 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
4164 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
4166 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
4167 sctx
->ps_db_shader_control
= db_shader_control
;
4168 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4169 if (sctx
->screen
->dpbb_allowed
)
4170 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
4173 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
4174 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
4175 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
4177 if (sctx
->chip_class
== GFX6
)
4178 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4180 if (sctx
->framebuffer
.nr_samples
<= 1)
4181 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
4185 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
4186 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
4187 si_pm4_state_enabled_and_changed(sctx
, es
) ||
4188 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
4189 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
4190 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
4191 if (!si_update_spi_tmpring_size(sctx
))
4195 if (sctx
->chip_class
>= GFX7
) {
4196 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
4197 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
4198 else if (!sctx
->queued
.named
.ls
)
4199 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
4201 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
4202 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
4203 else if (!sctx
->queued
.named
.hs
)
4204 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
4206 if (si_pm4_state_enabled_and_changed(sctx
, es
))
4207 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
4208 else if (!sctx
->queued
.named
.es
)
4209 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
4211 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
4212 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
4213 else if (!sctx
->queued
.named
.gs
)
4214 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
4216 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
4217 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
4218 else if (!sctx
->queued
.named
.vs
)
4219 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
4221 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
4222 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
4223 else if (!sctx
->queued
.named
.ps
)
4224 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
4227 sctx
->do_update_shaders
= false;
4231 static void si_emit_scratch_state(struct si_context
*sctx
)
4233 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4235 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
4236 sctx
->spi_tmpring_size
);
4238 if (sctx
->scratch_buffer
) {
4239 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
4240 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
4241 RADEON_PRIO_SCRATCH_BUFFER
);
4245 void si_init_screen_live_shader_cache(struct si_screen
*sscreen
)
4247 util_live_shader_cache_init(&sscreen
->live_shader_cache
,
4248 si_create_shader_selector
,
4249 si_destroy_shader_selector
);
4252 void si_init_shader_functions(struct si_context
*sctx
)
4254 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
4255 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
4257 sctx
->b
.create_vs_state
= si_create_shader
;
4258 sctx
->b
.create_tcs_state
= si_create_shader
;
4259 sctx
->b
.create_tes_state
= si_create_shader
;
4260 sctx
->b
.create_gs_state
= si_create_shader
;
4261 sctx
->b
.create_fs_state
= si_create_shader
;
4263 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
4264 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
4265 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
4266 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
4267 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
4269 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
4270 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
4271 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
4272 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
4273 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;