2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
45 * Return the IR key for the shader cache.
47 void si_get_ir_cache_key(struct si_shader_selector
*sel
, bool ngg
, bool es
,
48 unsigned char ir_sha1_cache_key
[20])
50 struct blob blob
= {};
55 ir_binary
= sel
->tokens
;
56 ir_size
= tgsi_num_tokens(sel
->tokens
) *
57 sizeof(struct tgsi_token
);
58 } else if (sel
->nir_binary
) {
59 ir_binary
= sel
->nir_binary
;
60 ir_size
= sel
->nir_size
;
65 nir_serialize(&blob
, sel
->nir
, true);
66 ir_binary
= blob
.data
;
70 /* These settings affect the compilation, but they are not derived
71 * from the input shader IR.
73 unsigned shader_variant_flags
= 0;
76 shader_variant_flags
|= 1 << 0;
78 shader_variant_flags
|= 1 << 1;
79 if (si_get_wave_size(sel
->screen
, sel
->type
, ngg
, es
) == 32)
80 shader_variant_flags
|= 1 << 2;
81 if (sel
->force_correct_derivs_after_kill
)
82 shader_variant_flags
|= 1 << 3;
85 _mesa_sha1_init(&ctx
);
86 _mesa_sha1_update(&ctx
, &shader_variant_flags
, 4);
87 _mesa_sha1_update(&ctx
, ir_binary
, ir_size
);
88 if (sel
->type
== PIPE_SHADER_VERTEX
||
89 sel
->type
== PIPE_SHADER_TESS_EVAL
||
90 sel
->type
== PIPE_SHADER_GEOMETRY
)
91 _mesa_sha1_update(&ctx
, &sel
->so
, sizeof(sel
->so
));
92 _mesa_sha1_final(&ctx
, ir_sha1_cache_key
);
94 if (ir_binary
== blob
.data
)
98 /** Copy "data" to "ptr" and return the next dword following copied data. */
99 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
101 /* data may be NULL if size == 0 */
103 memcpy(ptr
, data
, size
);
104 ptr
+= DIV_ROUND_UP(size
, 4);
108 /** Read data from "ptr". Return the next dword following the data. */
109 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
111 memcpy(data
, ptr
, size
);
112 ptr
+= DIV_ROUND_UP(size
, 4);
117 * Write the size as uint followed by the data. Return the next dword
118 * following the copied data.
120 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
123 return write_data(ptr
, data
, size
);
127 * Read the size as uint followed by the data. Return both via parameters.
128 * Return the next dword following the data.
130 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
133 assert(*data
== NULL
);
136 *data
= malloc(*size
);
137 return read_data(ptr
, *data
, *size
);
141 * Return the shader binary in a buffer. The first 4 bytes contain its size
144 static void *si_get_shader_binary(struct si_shader
*shader
)
146 /* There is always a size of data followed by the data itself. */
147 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
148 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
150 /* Refuse to allocate overly large buffers and guard against integer
152 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
153 llvm_ir_size
> UINT_MAX
/ 4)
158 4 + /* CRC32 of the data below */
159 align(sizeof(shader
->config
), 4) +
160 align(sizeof(shader
->info
), 4) +
161 4 + align(shader
->binary
.elf_size
, 4) +
162 4 + align(llvm_ir_size
, 4);
163 void *buffer
= CALLOC(1, size
);
164 uint32_t *ptr
= (uint32_t*)buffer
;
170 ptr
++; /* CRC32 is calculated at the end. */
172 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
173 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
174 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
175 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
176 assert((char *)ptr
- (char *)buffer
== size
);
179 ptr
= (uint32_t*)buffer
;
181 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
186 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
188 uint32_t *ptr
= (uint32_t*)binary
;
189 uint32_t size
= *ptr
++;
190 uint32_t crc32
= *ptr
++;
194 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
195 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
199 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
200 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
201 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
203 shader
->binary
.elf_size
= elf_size
;
204 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
210 * Insert a shader into the cache. It's assumed the shader is not in the cache.
211 * Use si_shader_cache_load_shader before calling this.
213 void si_shader_cache_insert_shader(struct si_screen
*sscreen
,
214 unsigned char ir_sha1_cache_key
[20],
215 struct si_shader
*shader
,
216 bool insert_into_disk_cache
)
219 struct hash_entry
*entry
;
220 uint8_t key
[CACHE_KEY_SIZE
];
222 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
224 return; /* already added */
226 hw_binary
= si_get_shader_binary(shader
);
230 if (_mesa_hash_table_insert(sscreen
->shader_cache
,
231 mem_dup(ir_sha1_cache_key
, 20),
232 hw_binary
) == NULL
) {
237 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
238 disk_cache_compute_key(sscreen
->disk_shader_cache
,
239 ir_sha1_cache_key
, 20, key
);
240 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
241 *((uint32_t *) hw_binary
), NULL
);
245 bool si_shader_cache_load_shader(struct si_screen
*sscreen
,
246 unsigned char ir_sha1_cache_key
[20],
247 struct si_shader
*shader
)
249 struct hash_entry
*entry
=
250 _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
252 if (sscreen
->disk_shader_cache
) {
253 unsigned char sha1
[CACHE_KEY_SIZE
];
255 disk_cache_compute_key(sscreen
->disk_shader_cache
,
256 ir_sha1_cache_key
, 20, sha1
);
260 disk_cache_get(sscreen
->disk_shader_cache
,
265 if (binary_size
< sizeof(uint32_t) ||
266 *((uint32_t*)buffer
) != binary_size
) {
267 /* Something has gone wrong discard the item
268 * from the cache and rebuild/link from
271 assert(!"Invalid radeonsi shader disk cache "
274 disk_cache_remove(sscreen
->disk_shader_cache
,
281 if (!si_load_shader_binary(shader
, buffer
)) {
287 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
,
293 if (!si_load_shader_binary(shader
, entry
->data
))
296 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
300 static uint32_t si_shader_cache_key_hash(const void *key
)
302 /* Take the first dword of SHA1. */
303 return *(uint32_t*)key
;
306 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
309 return memcmp(a
, b
, 20) == 0;
312 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
314 FREE((void*)entry
->key
);
318 bool si_init_shader_cache(struct si_screen
*sscreen
)
320 (void) simple_mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
321 sscreen
->shader_cache
=
322 _mesa_hash_table_create(NULL
,
323 si_shader_cache_key_hash
,
324 si_shader_cache_key_equals
);
326 return sscreen
->shader_cache
!= NULL
;
329 void si_destroy_shader_cache(struct si_screen
*sscreen
)
331 if (sscreen
->shader_cache
)
332 _mesa_hash_table_destroy(sscreen
->shader_cache
,
333 si_destroy_shader_cache_entry
);
334 simple_mtx_destroy(&sscreen
->shader_cache_mutex
);
339 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
340 const struct si_shader_selector
*tes
,
341 struct si_pm4_state
*pm4
)
343 const struct tgsi_shader_info
*info
= &tes
->info
;
344 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
345 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
346 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
347 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
348 unsigned type
, partitioning
, topology
, distribution_mode
;
350 switch (tes_prim_mode
) {
351 case PIPE_PRIM_LINES
:
352 type
= V_028B6C_TESS_ISOLINE
;
354 case PIPE_PRIM_TRIANGLES
:
355 type
= V_028B6C_TESS_TRIANGLE
;
357 case PIPE_PRIM_QUADS
:
358 type
= V_028B6C_TESS_QUAD
;
365 switch (tes_spacing
) {
366 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
367 partitioning
= V_028B6C_PART_FRAC_ODD
;
369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
370 partitioning
= V_028B6C_PART_FRAC_EVEN
;
372 case PIPE_TESS_SPACING_EQUAL
:
373 partitioning
= V_028B6C_PART_INTEGER
;
381 topology
= V_028B6C_OUTPUT_POINT
;
382 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
383 topology
= V_028B6C_OUTPUT_LINE
;
384 else if (tes_vertex_order_cw
)
385 /* for some reason, this must be the other way around */
386 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
388 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
390 if (sscreen
->info
.has_distributed_tess
) {
391 if (sscreen
->info
.family
== CHIP_FIJI
||
392 sscreen
->info
.family
>= CHIP_POLARIS10
)
393 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
395 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
397 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
400 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
401 S_028B6C_PARTITIONING(partitioning
) |
402 S_028B6C_TOPOLOGY(topology
) |
403 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
407 * whether the "fractional odd" tessellation spacing is used.
409 * Possible VGT configurations and which state should set the register:
411 * Reg set in | VGT shader configuration | Value
412 * ------------------------------------------------------
414 * VS as ES | ES -> GS -> VS | 30
415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
420 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
421 struct si_shader_selector
*sel
,
422 struct si_shader
*shader
,
423 struct si_pm4_state
*pm4
)
425 unsigned type
= sel
->type
;
427 if (sscreen
->info
.family
< CHIP_POLARIS10
||
428 sscreen
->info
.chip_class
>= GFX10
)
431 /* VS as VS, or VS as ES: */
432 if ((type
== PIPE_SHADER_VERTEX
&&
434 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
435 /* TES as VS, or TES as ES: */
436 type
== PIPE_SHADER_TESS_EVAL
) {
437 unsigned vtx_reuse_depth
= 30;
439 if (type
== PIPE_SHADER_TESS_EVAL
&&
440 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
441 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
442 vtx_reuse_depth
= 14;
445 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
449 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
452 si_pm4_clear_state(shader
->pm4
);
454 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
457 shader
->pm4
->shader
= shader
;
460 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
465 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
467 /* Add the pointer to VBO descriptors. */
468 return num_always_on_user_sgprs
+ 1;
471 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
472 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen
*sscreen
,
473 struct si_shader
*shader
, bool legacy_vs_prim_id
)
475 assert(shader
->selector
->type
== PIPE_SHADER_VERTEX
||
476 (shader
->previous_stage_sel
&&
477 shader
->previous_stage_sel
->type
== PIPE_SHADER_VERTEX
));
479 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
480 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
481 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
482 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
484 bool is_ls
= shader
->selector
->type
== PIPE_SHADER_TESS_CTRL
|| shader
->key
.as_ls
;
486 if (sscreen
->info
.chip_class
>= GFX10
&& shader
->info
.uses_instanceid
)
488 else if ((is_ls
&& shader
->info
.uses_instanceid
) || legacy_vs_prim_id
)
490 else if (is_ls
|| shader
->info
.uses_instanceid
)
496 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
498 struct si_pm4_state
*pm4
;
501 assert(sscreen
->info
.chip_class
<= GFX8
);
503 pm4
= si_get_shader_pm4_state(shader
);
507 va
= shader
->bo
->gpu_address
;
508 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
510 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
511 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
513 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
514 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
515 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false)) |
516 S_00B528_DX10_CLAMP(1) |
517 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
518 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
519 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
522 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
524 struct si_pm4_state
*pm4
;
527 pm4
= si_get_shader_pm4_state(shader
);
531 va
= shader
->bo
->gpu_address
;
532 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
534 if (sscreen
->info
.chip_class
>= GFX9
) {
535 if (sscreen
->info
.chip_class
>= GFX10
) {
536 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
537 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
539 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
540 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
543 unsigned num_user_sgprs
=
544 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
546 shader
->config
.rsrc2
=
547 S_00B42C_USER_SGPR(num_user_sgprs
) |
548 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
550 if (sscreen
->info
.chip_class
>= GFX10
)
551 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
553 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
555 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
556 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
558 shader
->config
.rsrc2
=
559 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
560 S_00B42C_OC_LDS_EN(1) |
561 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
564 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
565 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) /
566 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
567 (sscreen
->info
.chip_class
<= GFX9
?
568 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) : 0) |
569 S_00B428_DX10_CLAMP(1) |
570 S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
571 S_00B428_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
572 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
573 S_00B428_LS_VGPR_COMP_CNT(sscreen
->info
.chip_class
>= GFX9
?
574 si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false) : 0));
576 if (sscreen
->info
.chip_class
<= GFX8
) {
577 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
578 shader
->config
.rsrc2
);
582 static void si_emit_shader_es(struct si_context
*sctx
)
584 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
585 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
590 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
591 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
592 shader
->selector
->esgs_itemsize
/ 4);
594 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
595 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
596 SI_TRACKED_VGT_TF_PARAM
,
597 shader
->vgt_tf_param
);
599 if (shader
->vgt_vertex_reuse_block_cntl
)
600 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
601 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
602 shader
->vgt_vertex_reuse_block_cntl
);
604 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
605 sctx
->context_roll
= true;
608 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
610 struct si_pm4_state
*pm4
;
611 unsigned num_user_sgprs
;
612 unsigned vgpr_comp_cnt
;
616 assert(sscreen
->info
.chip_class
<= GFX8
);
618 pm4
= si_get_shader_pm4_state(shader
);
622 pm4
->atom
.emit
= si_emit_shader_es
;
623 va
= shader
->bo
->gpu_address
;
624 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
626 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
627 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
628 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
629 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
630 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
631 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
633 unreachable("invalid shader selector type");
635 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
637 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
638 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
639 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
640 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
641 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
642 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
643 S_00B328_DX10_CLAMP(1) |
644 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
645 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
646 S_00B32C_USER_SGPR(num_user_sgprs
) |
647 S_00B32C_OC_LDS_EN(oc_lds_en
) |
648 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
650 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
651 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
653 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
656 void gfx9_get_gs_info(struct si_shader_selector
*es
,
657 struct si_shader_selector
*gs
,
658 struct gfx9_gs_info
*out
)
660 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
661 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
662 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
663 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
665 /* All these are in dwords: */
666 /* We can't allow using the whole LDS, because GS waves compete with
667 * other shader stages for LDS space. */
668 const unsigned max_lds_size
= 8 * 1024;
669 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
670 unsigned esgs_lds_size
;
672 /* All these are per subgroup: */
673 const unsigned max_out_prims
= 32 * 1024;
674 const unsigned max_es_verts
= 255;
675 const unsigned ideal_gs_prims
= 64;
676 unsigned max_gs_prims
, gs_prims
;
677 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
679 if (uses_adjacency
|| gs_num_invocations
> 1)
680 max_gs_prims
= 127 / gs_num_invocations
;
684 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
685 * Make sure we don't go over the maximum value.
687 if (gs
->gs_max_out_vertices
> 0) {
688 max_gs_prims
= MIN2(max_gs_prims
,
690 (gs
->gs_max_out_vertices
* gs_num_invocations
));
692 assert(max_gs_prims
> 0);
694 /* If the primitive has adjacency, halve the number of vertices
695 * that will be reused in multiple primitives.
697 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
699 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
700 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
702 /* Compute ESGS LDS size based on the worst case number of ES vertices
703 * needed to create the target number of GS prims per subgroup.
705 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
707 /* If total LDS usage is too big, refactor partitions based on ratio
708 * of ESGS item sizes.
710 if (esgs_lds_size
> max_lds_size
) {
711 /* Our target GS Prims Per Subgroup was too large. Calculate
712 * the maximum number of GS Prims Per Subgroup that will fit
713 * into LDS, capped by the maximum that the hardware can support.
715 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
717 assert(gs_prims
> 0);
718 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
721 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
722 assert(esgs_lds_size
<= max_lds_size
);
725 /* Now calculate remaining ESGS information. */
727 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
729 es_verts
= max_es_verts
;
731 /* Vertices for adjacency primitives are not always reused, so restore
732 * it for ES_VERTS_PER_SUBGRP.
734 min_es_verts
= gs
->gs_input_verts_per_prim
;
736 /* For normal primitives, the VGT only checks if they are past the ES
737 * verts per subgroup after allocating a full GS primitive and if they
738 * are, kick off a new subgroup. But if those additional ES verts are
739 * unique (e.g. not reused) we need to make sure there is enough LDS
740 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
742 es_verts
-= min_es_verts
- 1;
744 out
->es_verts_per_subgroup
= es_verts
;
745 out
->gs_prims_per_subgroup
= gs_prims
;
746 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
747 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
748 gs
->gs_max_out_vertices
;
749 out
->esgs_ring_size
= 4 * esgs_lds_size
;
751 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
754 static void si_emit_shader_gs(struct si_context
*sctx
)
756 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
757 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
762 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
763 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
764 radeon_opt_set_context_reg3(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
765 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
766 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
767 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
768 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
770 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
771 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
772 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
773 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
775 /* R_028B38_VGT_GS_MAX_VERT_OUT */
776 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
777 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
778 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
780 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
781 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
782 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
783 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
784 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
785 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
786 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
787 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
789 /* R_028B90_VGT_GS_INSTANCE_CNT */
790 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
791 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
792 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
794 if (sctx
->chip_class
>= GFX9
) {
795 /* R_028A44_VGT_GS_ONCHIP_CNTL */
796 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
797 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
798 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
799 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
800 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
801 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
802 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
803 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
804 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
805 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
806 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
808 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
809 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
810 SI_TRACKED_VGT_TF_PARAM
,
811 shader
->vgt_tf_param
);
812 if (shader
->vgt_vertex_reuse_block_cntl
)
813 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
814 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
815 shader
->vgt_vertex_reuse_block_cntl
);
818 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
819 sctx
->context_roll
= true;
822 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
824 struct si_shader_selector
*sel
= shader
->selector
;
825 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
826 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
827 struct si_pm4_state
*pm4
;
829 unsigned max_stream
= sel
->max_gs_stream
;
832 pm4
= si_get_shader_pm4_state(shader
);
836 pm4
->atom
.emit
= si_emit_shader_gs
;
838 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
839 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
842 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
843 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
846 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
847 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
850 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
851 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
853 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
854 assert(offset
< (1 << 15));
856 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
858 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
859 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
860 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
861 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
863 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
864 S_028B90_ENABLE(gs_num_invocations
> 0);
866 va
= shader
->bo
->gpu_address
;
867 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
869 if (sscreen
->info
.chip_class
>= GFX9
) {
870 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
871 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
872 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
874 if (es_type
== PIPE_SHADER_VERTEX
) {
875 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
876 } else if (es_type
== PIPE_SHADER_TESS_EVAL
)
877 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
879 unreachable("invalid shader selector type");
881 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
882 * VGPR[0:4] are always loaded.
884 if (sel
->info
.uses_invocationid
)
885 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
886 else if (sel
->info
.uses_primid
)
887 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
888 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
889 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
891 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
893 unsigned num_user_sgprs
;
894 if (es_type
== PIPE_SHADER_VERTEX
)
895 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
897 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
899 if (sscreen
->info
.chip_class
>= GFX10
) {
900 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
901 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
903 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
904 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
908 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
909 S_00B228_DX10_CLAMP(1) |
910 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
911 S_00B228_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
912 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
913 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
915 S_00B22C_USER_SGPR(num_user_sgprs
) |
916 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
917 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
918 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
919 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
921 if (sscreen
->info
.chip_class
>= GFX10
) {
922 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
924 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
925 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
928 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
929 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
931 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
932 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
933 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
934 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
935 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
936 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
937 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
938 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
940 if (es_type
== PIPE_SHADER_TESS_EVAL
)
941 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
943 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
946 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
947 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
949 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
950 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
951 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
952 S_00B228_DX10_CLAMP(1) |
953 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
954 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
955 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
956 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
960 /* Common tail code for NGG primitive shaders. */
961 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
,
962 struct si_shader
*shader
,
963 unsigned initial_cdw
)
965 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
966 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
967 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
968 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
969 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
970 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
971 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
972 SI_TRACKED_VGT_PRIMITIVEID_EN
,
973 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
974 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
975 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
976 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
977 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
978 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
979 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
980 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
981 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
982 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
983 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
984 SI_TRACKED_SPI_VS_OUT_CONFIG
,
985 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
986 radeon_opt_set_context_reg2(sctx
, R_028708_SPI_SHADER_IDX_FORMAT
,
987 SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
988 shader
->ctx_reg
.ngg
.spi_shader_idx_format
,
989 shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
990 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
991 SI_TRACKED_PA_CL_VTE_CNTL
,
992 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
993 radeon_opt_set_context_reg(sctx
, R_028838_PA_CL_NGG_CNTL
,
994 SI_TRACKED_PA_CL_NGG_CNTL
,
995 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
);
997 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
998 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
,
999 shader
->pa_cl_vs_out_cntl
,
1000 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
1002 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1003 sctx
->context_roll
= true;
1006 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
1008 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1009 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1014 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1017 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
1019 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1020 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1025 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1026 SI_TRACKED_VGT_TF_PARAM
,
1027 shader
->vgt_tf_param
);
1029 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1032 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
1034 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1035 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1040 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1041 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1042 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1044 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1047 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1049 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1050 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1055 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1056 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1057 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1058 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1059 SI_TRACKED_VGT_TF_PARAM
,
1060 shader
->vgt_tf_param
);
1062 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1065 unsigned si_get_input_prim(const struct si_shader_selector
*gs
)
1067 if (gs
->type
== PIPE_SHADER_GEOMETRY
)
1068 return gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
1070 if (gs
->type
== PIPE_SHADER_TESS_EVAL
) {
1071 if (gs
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1072 return PIPE_PRIM_POINTS
;
1073 if (gs
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
1074 return PIPE_PRIM_LINES
;
1075 return PIPE_PRIM_TRIANGLES
;
1078 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1079 return PIPE_PRIM_TRIANGLES
; /* worst case for all callers */
1082 static unsigned si_get_vs_out_cntl(const struct si_shader_selector
*sel
, bool ngg
)
1085 sel
->info
.writes_psize
|| (sel
->info
.writes_edgeflag
&& !ngg
) ||
1086 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
1087 return S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
1088 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
&& !ngg
) |
1089 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
1090 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
1091 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
1092 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
1096 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1099 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1101 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1102 const struct tgsi_shader_info
*gs_info
= &gs_sel
->info
;
1103 enum pipe_shader_type gs_type
= shader
->selector
->type
;
1104 const struct si_shader_selector
*es_sel
=
1105 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1106 const struct tgsi_shader_info
*es_info
= &es_sel
->info
;
1107 enum pipe_shader_type es_type
= es_sel
->type
;
1108 unsigned num_user_sgprs
;
1109 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1111 unsigned window_space
=
1112 gs_info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1113 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1114 unsigned gs_num_invocations
= MAX2(gs_sel
->gs_num_invocations
, 1);
1115 unsigned input_prim
= si_get_input_prim(gs_sel
);
1116 bool break_wave_at_eoi
= false;
1117 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1121 if (es_type
== PIPE_SHADER_TESS_EVAL
) {
1122 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1123 : gfx10_emit_shader_ngg_tess_nogs
;
1125 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1126 : gfx10_emit_shader_ngg_notess_nogs
;
1129 va
= shader
->bo
->gpu_address
;
1130 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1132 if (es_type
== PIPE_SHADER_VERTEX
) {
1133 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
1135 if (es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1136 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1137 es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1139 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
1142 assert(es_type
== PIPE_SHADER_TESS_EVAL
);
1143 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1144 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1146 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1147 break_wave_at_eoi
= true;
1150 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1151 * VGPR[0:4] are always loaded.
1153 * Vertex shaders always need to load VGPR3, because they need to
1154 * pass edge flags for decomposed primitives (such as quads) to the PA
1155 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1157 if (gs_info
->uses_invocationid
|| gs_type
== PIPE_SHADER_VERTEX
)
1158 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID, edge flags. */
1159 else if (gs_info
->uses_primid
)
1160 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1161 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
1162 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1164 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1166 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1167 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1168 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1169 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) /
1170 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1171 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
1172 S_00B228_DX10_CLAMP(1) |
1173 S_00B228_MEM_ORDERED(1) |
1174 S_00B228_WGP_MODE(1) |
1175 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1176 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1177 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1178 S_00B22C_USER_SGPR(num_user_sgprs
) |
1179 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1180 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1181 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
1182 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1184 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1185 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1186 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
1187 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1189 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1190 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1191 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1192 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1193 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1194 V_02870C_SPI_SHADER_4COMP
:
1195 V_02870C_SPI_SHADER_NONE
) |
1196 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1197 V_02870C_SPI_SHADER_4COMP
:
1198 V_02870C_SPI_SHADER_NONE
) |
1199 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1200 V_02870C_SPI_SHADER_4COMP
:
1201 V_02870C_SPI_SHADER_NONE
);
1203 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1204 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1205 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
);
1207 if (gs_type
== PIPE_SHADER_GEOMETRY
) {
1208 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1209 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->gs_max_out_vertices
;
1211 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1214 if (es_type
== PIPE_SHADER_TESS_EVAL
)
1215 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1217 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1218 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1219 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1220 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1221 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1222 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1223 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
=
1224 S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1225 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1226 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1227 S_028B90_CNT(gs_num_invocations
) |
1228 S_028B90_ENABLE(gs_num_invocations
> 1) |
1229 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1230 shader
->ngg
.max_vert_out_per_gs_instance
);
1232 /* Always output hw-generated edge flags and pass them via the prim
1233 * export to prevent drawing lines on internal edges of decomposed
1234 * primitives (such as quads) with polygon mode = lines. Only VS needs
1237 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
=
1238 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type
== PIPE_SHADER_VERTEX
);
1239 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(gs_sel
, true);
1242 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1243 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
) |
1244 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1246 /* Bug workaround for a possible hang with non-tessellation cases.
1247 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1249 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1251 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1252 sscreen
->info
.family
== CHIP_NAVI12
||
1253 sscreen
->info
.family
== CHIP_NAVI14
) &&
1254 (es_type
== PIPE_SHADER_VERTEX
|| gs_type
== PIPE_SHADER_VERTEX
) && /* = no tess */
1255 shader
->ngg
.hw_max_esverts
!= 256) {
1256 shader
->ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
1258 if (shader
->ngg
.hw_max_esverts
> 5) {
1260 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
- 5);
1265 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1266 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1268 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1269 S_028818_VTX_W0_FMT(1) |
1270 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1271 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1272 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1276 static void si_emit_shader_vs(struct si_context
*sctx
)
1278 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1279 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1284 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
1285 SI_TRACKED_VGT_GS_MODE
,
1286 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1287 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1288 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1289 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1291 if (sctx
->chip_class
<= GFX8
) {
1292 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
1293 SI_TRACKED_VGT_REUSE_OFF
,
1294 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1297 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1298 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1299 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1301 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1302 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1303 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1305 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1306 SI_TRACKED_PA_CL_VTE_CNTL
,
1307 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1309 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1310 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1311 SI_TRACKED_VGT_TF_PARAM
,
1312 shader
->vgt_tf_param
);
1314 if (shader
->vgt_vertex_reuse_block_cntl
)
1315 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1316 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1317 shader
->vgt_vertex_reuse_block_cntl
);
1319 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1320 sctx
->context_roll
= true;
1322 /* Required programming for tessellation. (legacy pipeline only) */
1323 if (sctx
->chip_class
== GFX10
&&
1324 shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1325 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
1326 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
1327 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1328 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1329 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1332 if (sctx
->chip_class
>= GFX10
) {
1333 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
1334 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
,
1335 shader
->pa_cl_vs_out_cntl
,
1336 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
1341 * Compute the state for \p shader, which will run as a vertex shader on the
1344 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1345 * is the copy shader.
1347 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1348 struct si_shader_selector
*gs
)
1350 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1351 struct si_pm4_state
*pm4
;
1352 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1354 unsigned nparams
, oc_lds_en
;
1355 unsigned window_space
=
1356 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1357 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1359 pm4
= si_get_shader_pm4_state(shader
);
1363 pm4
->atom
.emit
= si_emit_shader_vs
;
1365 /* We always write VGT_GS_MODE in the VS state, because every switch
1366 * between different shader pipelines involving a different GS or no
1367 * GS at all involves a switch of the VS (different GS use different
1368 * copy shaders). On the other hand, when the API switches from a GS to
1369 * no GS and then back to the same GS used originally, the GS state is
1373 unsigned mode
= V_028A40_GS_OFF
;
1375 /* PrimID needs GS scenario A. */
1377 mode
= V_028A40_GS_SCENARIO_A
;
1379 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1380 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1382 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1383 sscreen
->info
.chip_class
);
1384 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1387 if (sscreen
->info
.chip_class
<= GFX8
) {
1388 /* Reuse needs to be set off if we write oViewport. */
1389 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1390 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1393 va
= shader
->bo
->gpu_address
;
1394 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1397 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1398 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1399 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1400 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, enable_prim_id
);
1402 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
]) {
1403 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1404 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
1406 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1408 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1409 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1410 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1412 unreachable("invalid shader selector type");
1414 /* VS is required to export at least one param. */
1415 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1416 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1418 if (sscreen
->info
.chip_class
>= GFX10
) {
1419 shader
->ctx_reg
.vs
.spi_vs_out_config
|=
1420 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1423 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1424 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1425 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1426 V_02870C_SPI_SHADER_4COMP
:
1427 V_02870C_SPI_SHADER_NONE
) |
1428 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1429 V_02870C_SPI_SHADER_4COMP
:
1430 V_02870C_SPI_SHADER_NONE
) |
1431 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1432 V_02870C_SPI_SHADER_4COMP
:
1433 V_02870C_SPI_SHADER_NONE
);
1434 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(shader
->selector
, false);
1436 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1438 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1439 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1441 uint32_t rsrc1
= S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) /
1442 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1443 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1444 S_00B128_DX10_CLAMP(1) |
1445 S_00B128_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1446 S_00B128_FLOAT_MODE(shader
->config
.float_mode
);
1447 uint32_t rsrc2
= S_00B12C_USER_SGPR(num_user_sgprs
) |
1448 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1449 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
1451 if (sscreen
->info
.chip_class
<= GFX9
)
1452 rsrc1
|= S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1454 if (!sscreen
->use_ngg_streamout
) {
1455 rsrc2
|= S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1456 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1457 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1458 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1459 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
);
1462 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
, rsrc1
);
1463 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
, rsrc2
);
1466 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1467 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1469 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1470 S_028818_VTX_W0_FMT(1) |
1471 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1472 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1473 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1475 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1476 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1478 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1481 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1483 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1484 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1485 !!(info
->colors_read
& 0xf0);
1486 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1487 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1489 assert(num_interp
<= 32);
1490 return MIN2(num_interp
, 32);
1493 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1495 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1496 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1498 /* If the i-th target format is set, all previous target formats must
1499 * be non-zero to avoid hangs.
1501 for (i
= 0; i
< num_targets
; i
++)
1502 if (!(value
& (0xf << (i
* 4))))
1503 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1508 static void si_emit_shader_ps(struct si_context
*sctx
)
1510 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1511 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1516 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1517 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1518 SI_TRACKED_SPI_PS_INPUT_ENA
,
1519 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1520 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1522 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1523 SI_TRACKED_SPI_BARYC_CNTL
,
1524 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1525 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1526 SI_TRACKED_SPI_PS_IN_CONTROL
,
1527 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1529 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1530 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1531 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1532 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1533 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1535 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1536 SI_TRACKED_CB_SHADER_MASK
,
1537 shader
->ctx_reg
.ps
.cb_shader_mask
);
1539 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1540 sctx
->context_roll
= true;
1543 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1545 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1546 struct si_pm4_state
*pm4
;
1547 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1548 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1550 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1552 /* we need to enable at least one of them, otherwise we hang the GPU */
1553 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1554 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1555 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1556 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1557 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1558 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1559 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1560 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1561 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1562 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1563 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1564 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1565 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1566 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1568 /* Validate interpolation optimization flags (read as implications). */
1569 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1570 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1571 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1572 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1573 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1574 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1575 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1576 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1577 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1578 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1579 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1580 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1581 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1582 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1583 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1584 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1585 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1586 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1588 /* Validate cases when the optimizations are off (read as implications). */
1589 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1590 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1591 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1592 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1593 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1594 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1596 pm4
= si_get_shader_pm4_state(shader
);
1600 pm4
->atom
.emit
= si_emit_shader_ps
;
1602 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1604 * 0 -> Position = pixel center
1605 * 1 -> Position = pixel centroid
1606 * 2 -> Position = at sample position
1608 * From GLSL 4.5 specification, section 7.1:
1609 * "The variable gl_FragCoord is available as an input variable from
1610 * within fragment shaders and it holds the window relative coordinates
1611 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1612 * value can be for any location within the pixel, or one of the
1613 * fragment samples. The use of centroid does not further restrict
1614 * this value to be inside the current primitive."
1616 * Meaning that centroid has no effect and we can return anything within
1617 * the pixel. Thus, return the value at sample position, because that's
1618 * the most accurate one shaders can get.
1620 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1622 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1623 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1624 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1626 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1627 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1629 /* Ensure that some export memory is always allocated, for two reasons:
1631 * 1) Correctness: The hardware ignores the EXEC mask if no export
1632 * memory is allocated, so KILL and alpha test do not work correctly
1634 * 2) Performance: Every shader needs at least a NULL export, even when
1635 * it writes no color/depth output. The NULL export instruction
1636 * stalls without this setting.
1638 * Don't add this to CB_SHADER_MASK.
1640 * GFX10 supports pixel shaders without exports by setting both
1641 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1642 * instructions if any are present.
1644 if ((sscreen
->info
.chip_class
<= GFX9
||
1646 shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
) &&
1647 !spi_shader_col_format
&&
1648 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1649 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1651 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1652 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1654 /* Set interpolation controls. */
1655 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
)) |
1656 S_0286D8_PS_W32_EN(sscreen
->ps_wave_size
== 32);
1658 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1659 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1660 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1661 ac_get_spi_shader_z_format(info
->writes_z
,
1662 info
->writes_stencil
,
1663 info
->writes_samplemask
);
1664 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1665 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1667 va
= shader
->bo
->gpu_address
;
1668 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1669 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1670 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1673 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) /
1674 (sscreen
->ps_wave_size
== 32 ? 8 : 4)) |
1675 S_00B028_DX10_CLAMP(1) |
1676 S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1677 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1679 if (sscreen
->info
.chip_class
< GFX10
) {
1680 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1683 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1684 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1685 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1686 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1687 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1690 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1691 struct si_shader
*shader
)
1693 switch (shader
->selector
->type
) {
1694 case PIPE_SHADER_VERTEX
:
1695 if (shader
->key
.as_ls
)
1696 si_shader_ls(sscreen
, shader
);
1697 else if (shader
->key
.as_es
)
1698 si_shader_es(sscreen
, shader
);
1699 else if (shader
->key
.as_ngg
)
1700 gfx10_shader_ngg(sscreen
, shader
);
1702 si_shader_vs(sscreen
, shader
, NULL
);
1704 case PIPE_SHADER_TESS_CTRL
:
1705 si_shader_hs(sscreen
, shader
);
1707 case PIPE_SHADER_TESS_EVAL
:
1708 if (shader
->key
.as_es
)
1709 si_shader_es(sscreen
, shader
);
1710 else if (shader
->key
.as_ngg
)
1711 gfx10_shader_ngg(sscreen
, shader
);
1713 si_shader_vs(sscreen
, shader
, NULL
);
1715 case PIPE_SHADER_GEOMETRY
:
1716 if (shader
->key
.as_ngg
)
1717 gfx10_shader_ngg(sscreen
, shader
);
1719 si_shader_gs(sscreen
, shader
);
1721 case PIPE_SHADER_FRAGMENT
:
1722 si_shader_ps(sscreen
, shader
);
1729 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1731 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1732 return sctx
->queued
.named
.dsa
->alpha_func
;
1735 void si_shader_selector_key_vs(struct si_context
*sctx
,
1736 struct si_shader_selector
*vs
,
1737 struct si_shader_key
*key
,
1738 struct si_vs_prolog_bits
*prolog_key
)
1740 if (!sctx
->vertex_elements
||
1741 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
])
1744 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1746 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1747 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1748 prolog_key
->unpack_instance_id_from_vertex_id
=
1749 sctx
->prim_discard_cs_instancing
;
1751 /* Prefer a monolithic shader to allow scheduling divisions around
1753 if (prolog_key
->instance_divisor_is_fetched
)
1754 key
->opt
.prefer_mono
= 1;
1756 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1757 unsigned count_mask
= (1 << count
) - 1;
1758 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1759 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1761 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1762 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1764 unsigned i
= u_bit_scan(&mask
);
1765 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1766 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1767 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1768 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1769 if (vb
->buffer_offset
& align_mask
||
1770 vb
->stride
& align_mask
) {
1778 unsigned i
= u_bit_scan(&fix
);
1779 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1781 key
->mono
.vs_fetch_opencode
= opencode
;
1784 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1785 struct si_shader_selector
*vs
,
1786 struct si_shader_key
*key
)
1788 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1790 key
->opt
.clip_disable
=
1791 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1792 (vs
->info
.clipdist_writemask
||
1793 vs
->info
.writes_clipvertex
) &&
1794 !vs
->info
.culldist_writemask
;
1796 /* Find out if PS is disabled. */
1797 bool ps_disabled
= true;
1799 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1800 ps
->info
.writes_z
||
1801 ps
->info
.writes_stencil
||
1802 ps
->info
.writes_samplemask
||
1803 sctx
->queued
.named
.blend
->alpha_to_coverage
||
1804 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1805 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1807 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1810 !ps
->info
.writes_memory
);
1813 /* Find out which VS outputs aren't used by the PS. */
1814 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1815 uint64_t inputs_read
= 0;
1817 /* Ignore outputs that are not passed from VS to PS. */
1818 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1819 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1820 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1823 inputs_read
= ps
->inputs_read
;
1826 uint64_t linked
= outputs_written
& inputs_read
;
1828 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1831 /* Compute the key for the hw shader variant */
1832 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1833 struct si_shader_selector
*sel
,
1834 union si_vgt_stages_key stages_key
,
1835 struct si_shader_key
*key
)
1837 struct si_context
*sctx
= (struct si_context
*)ctx
;
1839 memset(key
, 0, sizeof(*key
));
1841 switch (sel
->type
) {
1842 case PIPE_SHADER_VERTEX
:
1843 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1845 if (sctx
->tes_shader
.cso
)
1847 else if (sctx
->gs_shader
.cso
) {
1849 key
->as_ngg
= stages_key
.u
.ngg
;
1851 key
->as_ngg
= stages_key
.u
.ngg
;
1852 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1854 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1855 key
->mono
.u
.vs_export_prim_id
= 1;
1858 case PIPE_SHADER_TESS_CTRL
:
1859 if (sctx
->chip_class
>= GFX9
) {
1860 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1861 key
, &key
->part
.tcs
.ls_prolog
);
1862 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1864 /* When the LS VGPR fix is needed, monolithic shaders
1866 * - avoid initializing EXEC in both the LS prolog
1867 * and the LS main part when !vs_needs_prolog
1868 * - remove the fixup for unused input VGPRs
1870 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1872 /* The LS output / HS input layout can be communicated
1873 * directly instead of via user SGPRs for merged LS-HS.
1874 * The LS VGPR fix prefers this too.
1876 key
->opt
.prefer_mono
= 1;
1879 key
->part
.tcs
.epilog
.prim_mode
=
1880 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1881 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1882 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1883 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1884 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1886 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1887 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1889 case PIPE_SHADER_TESS_EVAL
:
1890 key
->as_ngg
= stages_key
.u
.ngg
;
1892 if (sctx
->gs_shader
.cso
)
1895 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1897 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1898 key
->mono
.u
.vs_export_prim_id
= 1;
1901 case PIPE_SHADER_GEOMETRY
:
1902 if (sctx
->chip_class
>= GFX9
) {
1903 if (sctx
->tes_shader
.cso
) {
1904 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1906 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1907 key
, &key
->part
.gs
.vs_prolog
);
1908 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1909 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1912 key
->as_ngg
= stages_key
.u
.ngg
;
1914 /* Merged ES-GS can have unbalanced wave usage.
1916 * ES threads are per-vertex, while GS threads are
1917 * per-primitive. So without any amplification, there
1918 * are fewer GS threads than ES threads, which can result
1919 * in empty (no-op) GS waves. With too much amplification,
1920 * there are more GS threads than ES threads, which
1921 * can result in empty (no-op) ES waves.
1923 * Non-monolithic shaders are implemented by setting EXEC
1924 * at the beginning of shader parts, and don't jump to
1925 * the end if EXEC is 0.
1927 * Monolithic shaders use conditional blocks, so they can
1928 * jump and skip empty waves of ES or GS. So set this to
1929 * always use optimized variants, which are monolithic.
1931 key
->opt
.prefer_mono
= 1;
1933 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1935 case PIPE_SHADER_FRAGMENT
: {
1936 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1937 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1939 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1940 sel
->info
.colors_written
== 0x1)
1941 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1943 /* Select the shader color format based on whether
1944 * blending or alpha are needed.
1946 key
->part
.ps
.epilog
.spi_shader_col_format
=
1947 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1948 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1949 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1950 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1951 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1952 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1953 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1954 sctx
->framebuffer
.spi_shader_col_format
);
1955 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1957 /* The output for dual source blending should have
1958 * the same format as the first output.
1960 if (blend
->dual_src_blend
) {
1961 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1962 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1965 /* If alpha-to-coverage is enabled, we have to export alpha
1966 * even if there is no color buffer.
1968 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1969 blend
->alpha_to_coverage
)
1970 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1972 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1973 * to the range supported by the type if a channel has less
1974 * than 16 bits and the export format is 16_ABGR.
1976 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1977 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1978 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1981 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1982 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1983 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1984 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1985 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1988 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1989 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1991 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1992 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1994 key
->part
.ps
.epilog
.alpha_to_one
= blend
->alpha_to_one
&&
1995 rs
->multisample_enable
;
1997 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1998 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1999 (is_line
&& rs
->line_smooth
)) &&
2000 sctx
->framebuffer
.nr_samples
<= 1;
2001 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
2003 if (sctx
->ps_iter_samples
> 1 &&
2004 sel
->info
.reads_samplemask
) {
2005 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
2006 util_logbase2(sctx
->ps_iter_samples
);
2009 if (rs
->force_persample_interp
&&
2010 rs
->multisample_enable
&&
2011 sctx
->framebuffer
.nr_samples
> 1 &&
2012 sctx
->ps_iter_samples
> 1) {
2013 key
->part
.ps
.prolog
.force_persp_sample_interp
=
2014 sel
->info
.uses_persp_center
||
2015 sel
->info
.uses_persp_centroid
;
2017 key
->part
.ps
.prolog
.force_linear_sample_interp
=
2018 sel
->info
.uses_linear_center
||
2019 sel
->info
.uses_linear_centroid
;
2020 } else if (rs
->multisample_enable
&&
2021 sctx
->framebuffer
.nr_samples
> 1) {
2022 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
2023 sel
->info
.uses_persp_center
&&
2024 sel
->info
.uses_persp_centroid
;
2025 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
2026 sel
->info
.uses_linear_center
&&
2027 sel
->info
.uses_linear_centroid
;
2029 /* Make sure SPI doesn't compute more than 1 pair
2030 * of (i,j), which is the optimization here. */
2031 key
->part
.ps
.prolog
.force_persp_center_interp
=
2032 sel
->info
.uses_persp_center
+
2033 sel
->info
.uses_persp_centroid
+
2034 sel
->info
.uses_persp_sample
> 1;
2036 key
->part
.ps
.prolog
.force_linear_center_interp
=
2037 sel
->info
.uses_linear_center
+
2038 sel
->info
.uses_linear_centroid
+
2039 sel
->info
.uses_linear_sample
> 1;
2041 if (sel
->info
.uses_persp_opcode_interp_sample
||
2042 sel
->info
.uses_linear_opcode_interp_sample
)
2043 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
2046 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
2048 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2049 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
2050 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
2051 struct pipe_resource
*tex
= cb0
->texture
;
2053 /* 1D textures are allocated and used as 2D on GFX9. */
2054 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
2055 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
2056 (tex
->target
== PIPE_TEXTURE_1D
||
2057 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
2058 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
2059 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
2060 tex
->target
== PIPE_TEXTURE_CUBE
||
2061 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2062 tex
->target
== PIPE_TEXTURE_3D
;
2070 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
2071 memset(&key
->opt
, 0, sizeof(key
->opt
));
2074 static void si_build_shader_variant(struct si_shader
*shader
,
2078 struct si_shader_selector
*sel
= shader
->selector
;
2079 struct si_screen
*sscreen
= sel
->screen
;
2080 struct ac_llvm_compiler
*compiler
;
2081 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
2083 if (thread_index
>= 0) {
2085 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
2086 compiler
= &sscreen
->compiler_lowp
[thread_index
];
2088 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2089 compiler
= &sscreen
->compiler
[thread_index
];
2094 assert(!low_priority
);
2095 compiler
= shader
->compiler_ctx_state
.compiler
;
2098 if (!compiler
->passes
)
2099 si_init_compiler(sscreen
, compiler
);
2101 if (unlikely(!si_shader_create(sscreen
, compiler
, shader
, debug
))) {
2102 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2104 shader
->compilation_failed
= true;
2108 if (shader
->compiler_ctx_state
.is_debug_context
) {
2109 FILE *f
= open_memstream(&shader
->shader_log
,
2110 &shader
->shader_log_size
);
2112 si_shader_dump(sscreen
, shader
, NULL
, f
, false);
2117 si_shader_init_pm4_state(sscreen
, shader
);
2120 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2122 struct si_shader
*shader
= (struct si_shader
*)job
;
2124 assert(thread_index
>= 0);
2126 si_build_shader_variant(shader
, thread_index
, true);
2129 static const struct si_shader_key zeroed
;
2131 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
2132 struct si_shader_selector
*sel
,
2133 struct si_compiler_ctx_state
*compiler_state
,
2134 struct si_shader_key
*key
)
2136 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2139 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2144 /* We can leave the fence as permanently signaled because the
2145 * main part becomes visible globally only after it has been
2147 util_queue_fence_init(&main_part
->ready
);
2149 main_part
->selector
= sel
;
2150 main_part
->key
.as_es
= key
->as_es
;
2151 main_part
->key
.as_ls
= key
->as_ls
;
2152 main_part
->key
.as_ngg
= key
->as_ngg
;
2153 main_part
->is_monolithic
= false;
2155 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
2156 main_part
, &compiler_state
->debug
) != 0) {
2166 * Select a shader variant according to the shader key.
2168 * \param optimized_or_none If the key describes an optimized shader variant and
2169 * the compilation isn't finished, don't select any
2170 * shader and return an error.
2172 int si_shader_select_with_key(struct si_screen
*sscreen
,
2173 struct si_shader_ctx_state
*state
,
2174 struct si_compiler_ctx_state
*compiler_state
,
2175 struct si_shader_key
*key
,
2177 bool optimized_or_none
)
2179 struct si_shader_selector
*sel
= state
->cso
;
2180 struct si_shader_selector
*previous_stage_sel
= NULL
;
2181 struct si_shader
*current
= state
->current
;
2182 struct si_shader
*iter
, *shader
= NULL
;
2185 /* Check if we don't need to change anything.
2186 * This path is also used for most shaders that don't need multiple
2187 * variants, it will cost just a computation of the key and this
2189 if (likely(current
&&
2190 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2191 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2192 if (current
->is_optimized
) {
2193 if (optimized_or_none
)
2196 memset(&key
->opt
, 0, sizeof(key
->opt
));
2197 goto current_not_ready
;
2200 util_queue_fence_wait(¤t
->ready
);
2203 return current
->compilation_failed
? -1 : 0;
2207 /* This must be done before the mutex is locked, because async GS
2208 * compilation calls this function too, and therefore must enter
2211 * Only wait if we are in a draw call. Don't wait if we are
2212 * in a compiler thread.
2214 if (thread_index
< 0)
2215 util_queue_fence_wait(&sel
->ready
);
2217 simple_mtx_lock(&sel
->mutex
);
2219 /* Find the shader variant. */
2220 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2221 /* Don't check the "current" shader. We checked it above. */
2222 if (current
!= iter
&&
2223 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2224 simple_mtx_unlock(&sel
->mutex
);
2226 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2227 /* If it's an optimized shader and its compilation has
2228 * been started but isn't done, use the unoptimized
2229 * shader so as not to cause a stall due to compilation.
2231 if (iter
->is_optimized
) {
2232 if (optimized_or_none
)
2234 memset(&key
->opt
, 0, sizeof(key
->opt
));
2238 util_queue_fence_wait(&iter
->ready
);
2241 if (iter
->compilation_failed
) {
2242 return -1; /* skip the draw call */
2245 state
->current
= iter
;
2250 /* Build a new shader. */
2251 shader
= CALLOC_STRUCT(si_shader
);
2253 simple_mtx_unlock(&sel
->mutex
);
2257 util_queue_fence_init(&shader
->ready
);
2259 shader
->selector
= sel
;
2261 shader
->compiler_ctx_state
= *compiler_state
;
2263 /* If this is a merged shader, get the first shader's selector. */
2264 if (sscreen
->info
.chip_class
>= GFX9
) {
2265 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2266 previous_stage_sel
= key
->part
.tcs
.ls
;
2267 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2268 previous_stage_sel
= key
->part
.gs
.es
;
2270 /* We need to wait for the previous shader. */
2271 if (previous_stage_sel
&& thread_index
< 0)
2272 util_queue_fence_wait(&previous_stage_sel
->ready
);
2275 bool is_pure_monolithic
=
2276 sscreen
->use_monolithic_shaders
||
2277 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2279 /* Compile the main shader part if it doesn't exist. This can happen
2280 * if the initial guess was wrong.
2282 * The prim discard CS doesn't need the main shader part.
2284 if (!is_pure_monolithic
&&
2285 !key
->opt
.vs_as_prim_discard_cs
) {
2288 /* Make sure the main shader part is present. This is needed
2289 * for shaders that can be compiled as VS, LS, or ES, and only
2290 * one of them is compiled at creation.
2292 * It is also needed for GS, which can be compiled as non-NGG
2295 * For merged shaders, check that the starting shader's main
2298 if (previous_stage_sel
) {
2299 struct si_shader_key shader1_key
= zeroed
;
2301 if (sel
->type
== PIPE_SHADER_TESS_CTRL
) {
2302 shader1_key
.as_ls
= 1;
2303 } else if (sel
->type
== PIPE_SHADER_GEOMETRY
) {
2304 shader1_key
.as_es
= 1;
2305 shader1_key
.as_ngg
= key
->as_ngg
; /* for Wave32 vs Wave64 */
2310 simple_mtx_lock(&previous_stage_sel
->mutex
);
2311 ok
= si_check_missing_main_part(sscreen
,
2313 compiler_state
, &shader1_key
);
2314 simple_mtx_unlock(&previous_stage_sel
->mutex
);
2318 ok
= si_check_missing_main_part(sscreen
, sel
,
2319 compiler_state
, key
);
2324 simple_mtx_unlock(&sel
->mutex
);
2325 return -ENOMEM
; /* skip the draw call */
2329 /* Keep the reference to the 1st shader of merged shaders, so that
2330 * Gallium can't destroy it before we destroy the 2nd shader.
2332 * Set sctx = NULL, because it's unused if we're not releasing
2333 * the shader, and we don't have any sctx here.
2335 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
2336 previous_stage_sel
);
2338 /* Monolithic-only shaders don't make a distinction between optimized
2339 * and unoptimized. */
2340 shader
->is_monolithic
=
2341 is_pure_monolithic
||
2342 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2344 /* The prim discard CS is always optimized. */
2345 shader
->is_optimized
=
2346 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2347 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2349 /* If it's an optimized shader, compile it asynchronously. */
2350 if (shader
->is_optimized
&& thread_index
< 0) {
2351 /* Compile it asynchronously. */
2352 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
2353 shader
, &shader
->ready
,
2354 si_build_shader_variant_low_priority
, NULL
,
2357 /* Add only after the ready fence was reset, to guard against a
2358 * race with si_bind_XX_shader. */
2359 if (!sel
->last_variant
) {
2360 sel
->first_variant
= shader
;
2361 sel
->last_variant
= shader
;
2363 sel
->last_variant
->next_variant
= shader
;
2364 sel
->last_variant
= shader
;
2367 /* Use the default (unoptimized) shader for now. */
2368 memset(&key
->opt
, 0, sizeof(key
->opt
));
2369 simple_mtx_unlock(&sel
->mutex
);
2371 if (sscreen
->options
.sync_compile
)
2372 util_queue_fence_wait(&shader
->ready
);
2374 if (optimized_or_none
)
2379 /* Reset the fence before adding to the variant list. */
2380 util_queue_fence_reset(&shader
->ready
);
2382 if (!sel
->last_variant
) {
2383 sel
->first_variant
= shader
;
2384 sel
->last_variant
= shader
;
2386 sel
->last_variant
->next_variant
= shader
;
2387 sel
->last_variant
= shader
;
2390 simple_mtx_unlock(&sel
->mutex
);
2392 assert(!shader
->is_optimized
);
2393 si_build_shader_variant(shader
, thread_index
, false);
2395 util_queue_fence_signal(&shader
->ready
);
2397 if (!shader
->compilation_failed
)
2398 state
->current
= shader
;
2400 return shader
->compilation_failed
? -1 : 0;
2403 static int si_shader_select(struct pipe_context
*ctx
,
2404 struct si_shader_ctx_state
*state
,
2405 union si_vgt_stages_key stages_key
,
2406 struct si_compiler_ctx_state
*compiler_state
)
2408 struct si_context
*sctx
= (struct si_context
*)ctx
;
2409 struct si_shader_key key
;
2411 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2412 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2416 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
2418 struct si_shader_key
*key
)
2420 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2422 switch (info
->processor
) {
2423 case PIPE_SHADER_VERTEX
:
2424 switch (next_shader
) {
2425 case PIPE_SHADER_GEOMETRY
:
2428 case PIPE_SHADER_TESS_CTRL
:
2429 case PIPE_SHADER_TESS_EVAL
:
2433 /* If POSITION isn't written, it can only be a HW VS
2434 * if streamout is used. If streamout isn't used,
2435 * assume that it's a HW LS. (the next shader is TCS)
2436 * This heuristic is needed for separate shader objects.
2438 if (!info
->writes_position
&& !streamout
)
2443 case PIPE_SHADER_TESS_EVAL
:
2444 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2445 !info
->writes_position
)
2452 * Compile the main shader part or the monolithic shader as part of
2453 * si_shader_selector initialization. Since it can be done asynchronously,
2454 * there is no way to report compile failures to applications.
2456 static void si_init_shader_selector_async(void *job
, int thread_index
)
2458 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2459 struct si_screen
*sscreen
= sel
->screen
;
2460 struct ac_llvm_compiler
*compiler
;
2461 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2463 assert(!debug
->debug_message
|| debug
->async
);
2464 assert(thread_index
>= 0);
2465 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2466 compiler
= &sscreen
->compiler
[thread_index
];
2468 if (!compiler
->passes
)
2469 si_init_compiler(sscreen
, compiler
);
2471 /* Serialize NIR to save memory. Monolithic shader variants
2472 * have to deserialize NIR before compilation.
2479 /* true = remove optional debugging data to increase
2480 * the likehood of getting more shader cache hits.
2481 * It also drops variable names, so we'll save more memory.
2483 nir_serialize(&blob
, sel
->nir
, true);
2484 blob_finish_get_buffer(&blob
, &sel
->nir_binary
, &size
);
2485 sel
->nir_size
= size
;
2488 /* Compile the main shader part for use with a prolog and/or epilog.
2489 * If this fails, the driver will try to compile a monolithic shader
2492 if (!sscreen
->use_monolithic_shaders
) {
2493 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2494 unsigned char ir_sha1_cache_key
[20];
2497 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2501 /* We can leave the fence signaled because use of the default
2502 * main part is guarded by the selector's ready fence. */
2503 util_queue_fence_init(&shader
->ready
);
2505 shader
->selector
= sel
;
2506 shader
->is_monolithic
= false;
2507 si_parse_next_shader_property(&sel
->info
,
2508 sel
->so
.num_outputs
!= 0,
2511 if (sscreen
->use_ngg
&&
2512 (!sel
->so
.num_outputs
|| sscreen
->use_ngg_streamout
) &&
2513 ((sel
->type
== PIPE_SHADER_VERTEX
&& !shader
->key
.as_ls
) ||
2514 sel
->type
== PIPE_SHADER_TESS_EVAL
||
2515 sel
->type
== PIPE_SHADER_GEOMETRY
))
2516 shader
->key
.as_ngg
= 1;
2518 if (sel
->tokens
|| sel
->nir
) {
2519 si_get_ir_cache_key(sel
, shader
->key
.as_ngg
,
2520 shader
->key
.as_es
, ir_sha1_cache_key
);
2523 /* Try to load the shader from the shader cache. */
2524 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2526 if (si_shader_cache_load_shader(sscreen
, ir_sha1_cache_key
, shader
)) {
2527 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2528 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2530 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2532 /* Compile the shader if it hasn't been loaded from the cache. */
2533 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
2536 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2540 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2541 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
,
2543 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2546 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2548 /* Unset "outputs_written" flags for outputs converted to
2549 * DEFAULT_VAL, so that later inter-shader optimizations don't
2550 * try to eliminate outputs that don't exist in the final
2553 * This is only done if non-monolithic shaders are enabled.
2555 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2556 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2557 !shader
->key
.as_ls
&&
2558 !shader
->key
.as_es
) {
2561 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2562 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2564 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2567 unsigned name
= sel
->info
.output_semantic_name
[i
];
2568 unsigned index
= sel
->info
.output_semantic_index
[i
];
2572 case TGSI_SEMANTIC_GENERIC
:
2573 /* don't process indices the function can't handle */
2574 if (index
>= SI_MAX_IO_GENERIC
)
2578 id
= si_shader_io_get_unique_index(name
, index
, true);
2579 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2581 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2582 case TGSI_SEMANTIC_PSIZE
:
2583 case TGSI_SEMANTIC_CLIPVERTEX
:
2584 case TGSI_SEMANTIC_EDGEFLAG
:
2591 /* The GS copy shader is always pre-compiled. */
2592 if (sel
->type
== PIPE_SHADER_GEOMETRY
&&
2593 (!sscreen
->use_ngg
||
2594 !sscreen
->use_ngg_streamout
|| /* also for PRIMITIVES_GENERATED */
2595 sel
->tess_turns_off_ngg
)) {
2596 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2597 if (!sel
->gs_copy_shader
) {
2598 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2602 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2605 /* Free NIR. We only keep serialized NIR after this point. */
2607 ralloc_free(sel
->nir
);
2612 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2613 struct util_queue_fence
*ready_fence
,
2614 struct si_compiler_ctx_state
*compiler_ctx_state
,
2615 void *job
, util_queue_execute_func execute
)
2617 util_queue_fence_init(ready_fence
);
2619 struct util_async_debug_callback async_debug
;
2621 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2623 si_can_dump_shader(sctx
->screen
, processor
);
2626 u_async_debug_init(&async_debug
);
2627 compiler_ctx_state
->debug
= async_debug
.base
;
2630 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2631 ready_fence
, execute
, NULL
, 0);
2634 util_queue_fence_wait(ready_fence
);
2635 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2636 u_async_debug_cleanup(&async_debug
);
2639 if (sctx
->screen
->options
.sync_compile
)
2640 util_queue_fence_wait(ready_fence
);
2643 /* Return descriptor slot usage masks from the given shader info. */
2644 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2645 uint32_t *const_and_shader_buffers
,
2646 uint64_t *samplers_and_images
)
2648 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_msaa_images
, num_samplers
;
2650 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2651 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2652 /* two 8-byte images share one 16-byte slot */
2653 num_images
= align(util_last_bit(info
->images_declared
), 2);
2654 num_msaa_images
= align(util_last_bit(info
->msaa_images_declared
), 2);
2655 num_samplers
= util_last_bit(info
->samplers_declared
);
2657 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2658 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2659 *const_and_shader_buffers
=
2660 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2663 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2664 * - image[last] ... image[0] go to [31-last .. 31]
2665 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2667 * FMASKs for images are placed separately, because MSAA images are rare,
2668 * and so we can benefit from a better cache hit rate if we keep image
2669 * descriptors together.
2671 if (num_msaa_images
)
2672 num_images
= SI_NUM_IMAGES
+ num_msaa_images
; /* add FMASK descriptors */
2674 start
= si_get_image_slot(num_images
- 1) / 2;
2675 *samplers_and_images
=
2676 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2679 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2680 const struct pipe_shader_state
*state
)
2682 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2683 struct si_context
*sctx
= (struct si_context
*)ctx
;
2684 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2690 pipe_reference_init(&sel
->reference
, 1);
2691 sel
->screen
= sscreen
;
2692 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2693 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2695 sel
->so
= state
->stream_output
;
2697 if (state
->type
== PIPE_SHADER_IR_TGSI
&&
2698 !sscreen
->options
.enable_nir
) {
2699 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2705 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2706 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2708 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2709 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2710 sel
->info
.uses_persp_centroid
= true;
2712 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2713 sel
->info
.uses_linear_centroid
= true;
2715 if (sel
->info
.uses_persp_opcode_interp_offset
||
2716 sel
->info
.uses_persp_opcode_interp_sample
)
2717 sel
->info
.uses_persp_center
= true;
2719 if (sel
->info
.uses_linear_opcode_interp_offset
||
2720 sel
->info
.uses_linear_opcode_interp_sample
)
2721 sel
->info
.uses_linear_center
= true;
2723 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2724 sel
->nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
2726 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2727 sel
->nir
= state
->ir
.nir
;
2730 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2731 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->tcs_info
);
2732 si_nir_adjust_driver_locations(sel
->nir
);
2735 sel
->type
= sel
->info
.processor
;
2736 p_atomic_inc(&sscreen
->num_shaders_created
);
2737 si_get_active_slot_masks(&sel
->info
,
2738 &sel
->active_const_and_shader_buffers
,
2739 &sel
->active_samplers_and_images
);
2741 /* Record which streamout buffers are enabled. */
2742 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2743 sel
->enabled_streamout_buffer_mask
|=
2744 (1 << sel
->so
.output
[i
].output_buffer
) <<
2745 (sel
->so
.output
[i
].stream
* 4);
2748 /* The prolog is a no-op if there are no inputs. */
2749 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2750 sel
->info
.num_inputs
&&
2751 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
];
2753 sel
->force_correct_derivs_after_kill
=
2754 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2755 sel
->info
.uses_derivatives
&&
2756 sel
->info
.uses_kill
&&
2757 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2759 sel
->prim_discard_cs_allowed
=
2760 sel
->type
== PIPE_SHADER_VERTEX
&&
2761 !sel
->info
.uses_bindless_images
&&
2762 !sel
->info
.uses_bindless_samplers
&&
2763 !sel
->info
.writes_memory
&&
2764 !sel
->info
.writes_viewport_index
&&
2765 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2766 !sel
->so
.num_outputs
;
2768 switch (sel
->type
) {
2769 case PIPE_SHADER_GEOMETRY
:
2770 sel
->gs_output_prim
=
2771 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2773 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2774 sel
->rast_prim
= sel
->gs_output_prim
;
2775 if (util_rast_prim_is_triangles(sel
->rast_prim
))
2776 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2778 sel
->gs_max_out_vertices
=
2779 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2780 sel
->gs_num_invocations
=
2781 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2782 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2783 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2784 sel
->gs_max_out_vertices
;
2786 sel
->max_gs_stream
= 0;
2787 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2788 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2789 sel
->so
.output
[i
].stream
);
2791 sel
->gs_input_verts_per_prim
=
2792 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2794 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2795 sel
->tess_turns_off_ngg
=
2796 (sscreen
->info
.family
== CHIP_NAVI10
||
2797 sscreen
->info
.family
== CHIP_NAVI12
||
2798 sscreen
->info
.family
== CHIP_NAVI14
) &&
2799 sel
->gs_num_invocations
* sel
->gs_max_out_vertices
> 256;
2802 case PIPE_SHADER_TESS_CTRL
:
2803 /* Always reserve space for these. */
2804 sel
->patch_outputs_written
|=
2805 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2806 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2808 case PIPE_SHADER_VERTEX
:
2809 case PIPE_SHADER_TESS_EVAL
:
2810 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2811 unsigned name
= sel
->info
.output_semantic_name
[i
];
2812 unsigned index
= sel
->info
.output_semantic_index
[i
];
2815 case TGSI_SEMANTIC_TESSINNER
:
2816 case TGSI_SEMANTIC_TESSOUTER
:
2817 case TGSI_SEMANTIC_PATCH
:
2818 sel
->patch_outputs_written
|=
2819 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2822 case TGSI_SEMANTIC_GENERIC
:
2823 /* don't process indices the function can't handle */
2824 if (index
>= SI_MAX_IO_GENERIC
)
2828 sel
->outputs_written
|=
2829 1ull << si_shader_io_get_unique_index(name
, index
, false);
2830 sel
->outputs_written_before_ps
|=
2831 1ull << si_shader_io_get_unique_index(name
, index
, true);
2833 case TGSI_SEMANTIC_EDGEFLAG
:
2837 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2838 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2840 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2841 * will start on a different bank. (except for the maximum 32*16).
2843 if (sel
->lshs_vertex_stride
< 32*16)
2844 sel
->lshs_vertex_stride
+= 4;
2846 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2847 * conflicts, i.e. each vertex will start at a different bank.
2849 if (sctx
->chip_class
>= GFX9
)
2850 sel
->esgs_itemsize
+= 4;
2852 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2855 if (sel
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
2856 sel
->rast_prim
= PIPE_PRIM_POINTS
;
2857 else if (sel
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
2858 sel
->rast_prim
= PIPE_PRIM_LINE_STRIP
;
2860 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2863 case PIPE_SHADER_FRAGMENT
:
2864 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2865 unsigned name
= sel
->info
.input_semantic_name
[i
];
2866 unsigned index
= sel
->info
.input_semantic_index
[i
];
2869 case TGSI_SEMANTIC_GENERIC
:
2870 /* don't process indices the function can't handle */
2871 if (index
>= SI_MAX_IO_GENERIC
)
2876 1ull << si_shader_io_get_unique_index(name
, index
, true);
2878 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2883 for (i
= 0; i
< 8; i
++)
2884 if (sel
->info
.colors_written
& (1 << i
))
2885 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2887 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2888 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2889 int index
= sel
->info
.input_semantic_index
[i
];
2890 sel
->color_attr_index
[index
] = i
;
2897 /* PA_CL_VS_OUT_CNTL */
2898 if (sctx
->chip_class
<= GFX9
)
2899 sel
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(sel
, false);
2901 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2902 SIX_BITS
: sel
->info
.clipdist_writemask
;
2903 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2904 sel
->info
.num_written_clipdistance
;
2906 /* DB_SHADER_CONTROL */
2907 sel
->db_shader_control
=
2908 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2909 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2910 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2911 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2913 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2914 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2915 sel
->db_shader_control
|=
2916 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2918 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2919 sel
->db_shader_control
|=
2920 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2924 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2926 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2927 * --|-----------|------------|------------|--------------------|-------------------|-------------
2928 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2929 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2930 * 2 | false | true | n/a | LateZ | 1 | 0
2931 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2932 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2934 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2935 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2937 * Don't use ReZ without profiling !!!
2939 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2942 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2944 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2945 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2946 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2947 } else if (sel
->info
.writes_memory
) {
2949 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2950 S_02880C_EXEC_ON_HIER_FAIL(1);
2953 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2956 if (sel
->info
.properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
])
2957 sel
->db_shader_control
|= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2959 (void) simple_mtx_init(&sel
->mutex
, mtx_plain
);
2961 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2962 &sel
->compiler_ctx_state
, sel
,
2963 si_init_shader_selector_async
);
2967 static void si_update_streamout_state(struct si_context
*sctx
)
2969 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2971 if (!shader_with_so
)
2974 sctx
->streamout
.enabled_stream_buffers_mask
=
2975 shader_with_so
->enabled_streamout_buffer_mask
;
2976 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2979 static void si_update_clip_regs(struct si_context
*sctx
,
2980 struct si_shader_selector
*old_hw_vs
,
2981 struct si_shader
*old_hw_vs_variant
,
2982 struct si_shader_selector
*next_hw_vs
,
2983 struct si_shader
*next_hw_vs_variant
)
2987 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2988 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2989 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2990 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2991 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2992 !old_hw_vs_variant
||
2993 !next_hw_vs_variant
||
2994 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2995 next_hw_vs_variant
->key
.opt
.clip_disable
))
2996 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2999 static void si_update_common_shader_state(struct si_context
*sctx
)
3001 sctx
->uses_bindless_samplers
=
3002 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
3003 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
3004 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
3005 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
3006 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
3007 sctx
->uses_bindless_images
=
3008 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
3009 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
3010 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
3011 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
3012 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
3013 sctx
->do_update_shaders
= true;
3016 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
3018 struct si_context
*sctx
= (struct si_context
*)ctx
;
3019 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3020 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3021 struct si_shader_selector
*sel
= state
;
3023 if (sctx
->vs_shader
.cso
== sel
)
3026 sctx
->vs_shader
.cso
= sel
;
3027 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3028 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD
] : 0;
3030 if (si_update_ngg(sctx
))
3031 si_shader_change_notify(sctx
);
3033 si_update_common_shader_state(sctx
);
3034 si_update_vs_viewport_state(sctx
);
3035 si_set_active_descriptors_for_shader(sctx
, sel
);
3036 si_update_streamout_state(sctx
);
3037 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3038 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3041 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
3043 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
3044 (sctx
->tes_shader
.cso
&&
3045 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
3046 (sctx
->tcs_shader
.cso
&&
3047 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
3048 (sctx
->gs_shader
.cso
&&
3049 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
3050 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
3051 sctx
->ps_shader
.cso
->info
.uses_primid
);
3054 bool si_update_ngg(struct si_context
*sctx
)
3056 if (!sctx
->screen
->use_ngg
) {
3061 bool new_ngg
= true;
3063 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&&
3064 sctx
->gs_shader
.cso
->tess_turns_off_ngg
) {
3066 } else if (!sctx
->screen
->use_ngg_streamout
) {
3067 struct si_shader_selector
*last
= si_get_vs(sctx
)->cso
;
3069 if ((last
&& last
->so
.num_outputs
) ||
3070 sctx
->streamout
.prims_gen_query_enabled
)
3074 if (new_ngg
!= sctx
->ngg
) {
3075 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3076 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3079 if ((sctx
->family
== CHIP_NAVI10
||
3080 sctx
->family
== CHIP_NAVI12
||
3081 sctx
->family
== CHIP_NAVI14
) &&
3083 sctx
->flags
|= SI_CONTEXT_VGT_FLUSH
;
3085 sctx
->ngg
= new_ngg
;
3086 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3092 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
3094 struct si_context
*sctx
= (struct si_context
*)ctx
;
3095 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3096 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3097 struct si_shader_selector
*sel
= state
;
3098 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
3101 if (sctx
->gs_shader
.cso
== sel
)
3104 sctx
->gs_shader
.cso
= sel
;
3105 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3106 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
3108 si_update_common_shader_state(sctx
);
3109 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3111 ngg_changed
= si_update_ngg(sctx
);
3112 if (ngg_changed
|| enable_changed
)
3113 si_shader_change_notify(sctx
);
3114 if (enable_changed
) {
3115 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3116 si_update_tess_uses_prim_id(sctx
);
3118 si_update_vs_viewport_state(sctx
);
3119 si_set_active_descriptors_for_shader(sctx
, sel
);
3120 si_update_streamout_state(sctx
);
3121 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3122 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3125 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
3127 struct si_context
*sctx
= (struct si_context
*)ctx
;
3128 struct si_shader_selector
*sel
= state
;
3129 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
3131 if (sctx
->tcs_shader
.cso
== sel
)
3134 sctx
->tcs_shader
.cso
= sel
;
3135 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3136 si_update_tess_uses_prim_id(sctx
);
3138 si_update_common_shader_state(sctx
);
3141 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
3143 si_set_active_descriptors_for_shader(sctx
, sel
);
3146 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
3148 struct si_context
*sctx
= (struct si_context
*)ctx
;
3149 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3150 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3151 struct si_shader_selector
*sel
= state
;
3152 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
3154 if (sctx
->tes_shader
.cso
== sel
)
3157 sctx
->tes_shader
.cso
= sel
;
3158 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
3159 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
3160 si_update_tess_uses_prim_id(sctx
);
3162 si_update_common_shader_state(sctx
);
3163 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3165 bool ngg_changed
= si_update_ngg(sctx
);
3166 if (ngg_changed
|| enable_changed
)
3167 si_shader_change_notify(sctx
);
3169 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
3170 si_update_vs_viewport_state(sctx
);
3171 si_set_active_descriptors_for_shader(sctx
, sel
);
3172 si_update_streamout_state(sctx
);
3173 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3174 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3177 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3179 struct si_context
*sctx
= (struct si_context
*)ctx
;
3180 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3181 struct si_shader_selector
*sel
= state
;
3183 /* skip if supplied shader is one already in use */
3187 sctx
->ps_shader
.cso
= sel
;
3188 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3190 si_update_common_shader_state(sctx
);
3192 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3193 si_update_tess_uses_prim_id(sctx
);
3196 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3197 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3199 if (sctx
->screen
->has_out_of_order_rast
&&
3201 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
3202 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
3203 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
3204 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3206 si_set_active_descriptors_for_shader(sctx
, sel
);
3207 si_update_ps_colorbuf0_slot(sctx
);
3210 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3212 if (shader
->is_optimized
) {
3213 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
3217 util_queue_fence_destroy(&shader
->ready
);
3220 /* If destroyed shaders were not unbound, the next compiled
3221 * shader variant could get the same pointer address and so
3222 * binding it to the same shader stage would be considered
3223 * a no-op, causing random behavior.
3225 switch (shader
->selector
->type
) {
3226 case PIPE_SHADER_VERTEX
:
3227 if (shader
->key
.as_ls
) {
3228 assert(sctx
->chip_class
<= GFX8
);
3229 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3230 } else if (shader
->key
.as_es
) {
3231 assert(sctx
->chip_class
<= GFX8
);
3232 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3233 } else if (shader
->key
.as_ngg
) {
3234 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3236 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3239 case PIPE_SHADER_TESS_CTRL
:
3240 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3242 case PIPE_SHADER_TESS_EVAL
:
3243 if (shader
->key
.as_es
) {
3244 assert(sctx
->chip_class
<= GFX8
);
3245 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3246 } else if (shader
->key
.as_ngg
) {
3247 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3249 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3252 case PIPE_SHADER_GEOMETRY
:
3253 if (shader
->is_gs_copy_shader
)
3254 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3256 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3258 case PIPE_SHADER_FRAGMENT
:
3259 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3265 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3266 si_shader_destroy(shader
);
3270 void si_destroy_shader_selector(struct si_context
*sctx
,
3271 struct si_shader_selector
*sel
)
3273 struct si_shader
*p
= sel
->first_variant
, *c
;
3274 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3275 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
3276 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3277 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3278 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3279 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3282 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3284 if (current_shader
[sel
->type
]->cso
== sel
) {
3285 current_shader
[sel
->type
]->cso
= NULL
;
3286 current_shader
[sel
->type
]->current
= NULL
;
3290 c
= p
->next_variant
;
3291 si_delete_shader(sctx
, p
);
3295 if (sel
->main_shader_part
)
3296 si_delete_shader(sctx
, sel
->main_shader_part
);
3297 if (sel
->main_shader_part_ls
)
3298 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3299 if (sel
->main_shader_part_es
)
3300 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3301 if (sel
->main_shader_part_ngg
)
3302 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3303 if (sel
->gs_copy_shader
)
3304 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3306 util_queue_fence_destroy(&sel
->ready
);
3307 simple_mtx_destroy(&sel
->mutex
);
3309 ralloc_free(sel
->nir
);
3310 free(sel
->nir_binary
);
3314 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3316 struct si_context
*sctx
= (struct si_context
*)ctx
;
3317 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3319 si_shader_selector_reference(sctx
, &sel
, NULL
);
3322 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
3323 struct si_shader
*vs
, unsigned name
,
3324 unsigned index
, unsigned interpolate
)
3326 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
3327 unsigned j
, offset
, ps_input_cntl
= 0;
3329 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3330 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
3331 name
== TGSI_SEMANTIC_PRIMID
)
3332 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3334 if (name
== TGSI_SEMANTIC_PCOORD
||
3335 (name
== TGSI_SEMANTIC_TEXCOORD
&&
3336 sctx
->sprite_coord_enable
& (1 << index
))) {
3337 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3340 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
3341 if (name
== vsinfo
->output_semantic_name
[j
] &&
3342 index
== vsinfo
->output_semantic_index
[j
]) {
3343 offset
= vs
->info
.vs_output_param_offset
[j
];
3345 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3346 /* The input is loaded from parameter memory. */
3347 ps_input_cntl
|= S_028644_OFFSET(offset
);
3348 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3349 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3350 /* This can happen with depth-only rendering. */
3353 /* The input is a DEFAULT_VAL constant. */
3354 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3355 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3356 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3359 ps_input_cntl
= S_028644_OFFSET(0x20) |
3360 S_028644_DEFAULT_VAL(offset
);
3366 if (j
== vsinfo
->num_outputs
&& name
== TGSI_SEMANTIC_PRIMID
)
3367 /* PrimID is written after the last output when HW VS is used. */
3368 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3369 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3370 /* No corresponding output found, load defaults into input.
3371 * Don't set any other bits.
3372 * (FLAT_SHADE=1 completely changes behavior) */
3373 ps_input_cntl
= S_028644_OFFSET(0x20);
3374 /* D3D 9 behaviour. GL is undefined */
3375 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
3376 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3378 return ps_input_cntl
;
3381 static void si_emit_spi_map(struct si_context
*sctx
)
3383 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3384 struct si_shader
*vs
= si_get_vs_state(sctx
);
3385 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3386 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
3387 unsigned spi_ps_input_cntl
[32];
3389 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3392 num_interp
= si_get_ps_num_interp(ps
);
3393 assert(num_interp
> 0);
3395 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3396 unsigned name
= psinfo
->input_semantic_name
[i
];
3397 unsigned index
= psinfo
->input_semantic_index
[i
];
3398 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3400 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
3401 index
, interpolate
);
3403 if (name
== TGSI_SEMANTIC_COLOR
) {
3404 assert(index
< ARRAY_SIZE(bcol_interp
));
3405 bcol_interp
[index
] = interpolate
;
3409 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3410 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
3412 for (i
= 0; i
< 2; i
++) {
3413 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3416 spi_ps_input_cntl
[num_written
++] =
3417 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
3421 assert(num_interp
== num_written
);
3423 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3424 /* Dota 2: Only ~16% of SPI map updates set different values. */
3425 /* Talos: Only ~9% of SPI map updates set different values. */
3426 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3427 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
3429 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3431 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3432 sctx
->context_roll
= true;
3436 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3438 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
3440 if (sctx
->init_config_has_vgt_flush
)
3443 /* Done by Vulkan before VGT_FLUSH. */
3444 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3445 si_pm4_cmd_add(sctx
->init_config
,
3446 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3447 si_pm4_cmd_end(sctx
->init_config
, false);
3449 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3450 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3451 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3452 si_pm4_cmd_end(sctx
->init_config
, false);
3453 sctx
->init_config_has_vgt_flush
= true;
3456 /* Initialize state related to ESGS / GSVS ring buffers */
3457 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3459 struct si_shader_selector
*es
=
3460 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3461 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3462 struct si_pm4_state
*pm4
;
3464 /* Chip constants. */
3465 unsigned num_se
= sctx
->screen
->info
.max_se
;
3466 unsigned wave_size
= 64;
3467 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3468 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3469 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3471 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3472 unsigned alignment
= 256 * num_se
;
3473 /* The maximum size is 63.999 MB per SE. */
3474 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3476 /* Calculate the minimum size. */
3477 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
3478 wave_size
, alignment
);
3480 /* These are recommended sizes, not minimum sizes. */
3481 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
3482 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3483 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
3484 gs
->max_gsvs_emit_size
;
3486 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3487 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3488 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3490 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3491 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3493 /* Some rings don't have to be allocated if shaders don't use them.
3494 * (e.g. no varyings between ES and GS or GS and VS)
3496 * GFX9 doesn't have the ESGS ring.
3498 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
3500 (!sctx
->esgs_ring
||
3501 sctx
->esgs_ring
->width0
< esgs_ring_size
);
3502 bool update_gsvs
= gsvs_ring_size
&&
3503 (!sctx
->gsvs_ring
||
3504 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3506 if (!update_esgs
&& !update_gsvs
)
3510 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3512 pipe_aligned_buffer_create(sctx
->b
.screen
,
3513 SI_RESOURCE_FLAG_UNMAPPABLE
,
3516 sctx
->screen
->info
.pte_fragment_size
);
3517 if (!sctx
->esgs_ring
)
3522 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3524 pipe_aligned_buffer_create(sctx
->b
.screen
,
3525 SI_RESOURCE_FLAG_UNMAPPABLE
,
3528 sctx
->screen
->info
.pte_fragment_size
);
3529 if (!sctx
->gsvs_ring
)
3533 /* Create the "init_config_gs_rings" state. */
3534 pm4
= CALLOC_STRUCT(si_pm4_state
);
3538 if (sctx
->chip_class
>= GFX7
) {
3539 if (sctx
->esgs_ring
) {
3540 assert(sctx
->chip_class
<= GFX8
);
3541 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3542 sctx
->esgs_ring
->width0
/ 256);
3544 if (sctx
->gsvs_ring
)
3545 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3546 sctx
->gsvs_ring
->width0
/ 256);
3548 if (sctx
->esgs_ring
)
3549 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3550 sctx
->esgs_ring
->width0
/ 256);
3551 if (sctx
->gsvs_ring
)
3552 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3553 sctx
->gsvs_ring
->width0
/ 256);
3556 /* Set the state. */
3557 if (sctx
->init_config_gs_rings
)
3558 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3559 sctx
->init_config_gs_rings
= pm4
;
3561 if (!sctx
->init_config_has_vgt_flush
) {
3562 si_init_config_add_vgt_flush(sctx
);
3563 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3566 /* Flush the context to re-emit both init_config states. */
3567 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3568 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3570 /* Set ring bindings. */
3571 if (sctx
->esgs_ring
) {
3572 assert(sctx
->chip_class
<= GFX8
);
3573 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3574 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3575 true, true, 4, 64, 0);
3576 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3577 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3578 false, false, 0, 0, 0);
3580 if (sctx
->gsvs_ring
) {
3581 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3582 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3583 false, false, 0, 0, 0);
3589 static void si_shader_lock(struct si_shader
*shader
)
3591 simple_mtx_lock(&shader
->selector
->mutex
);
3592 if (shader
->previous_stage_sel
) {
3593 assert(shader
->previous_stage_sel
!= shader
->selector
);
3594 simple_mtx_lock(&shader
->previous_stage_sel
->mutex
);
3598 static void si_shader_unlock(struct si_shader
*shader
)
3600 if (shader
->previous_stage_sel
)
3601 simple_mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3602 simple_mtx_unlock(&shader
->selector
->mutex
);
3606 * @returns 1 if \p sel has been updated to use a new scratch buffer
3608 * < 0 if there was a failure
3610 static int si_update_scratch_buffer(struct si_context
*sctx
,
3611 struct si_shader
*shader
)
3613 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3618 /* This shader doesn't need a scratch buffer */
3619 if (shader
->config
.scratch_bytes_per_wave
== 0)
3622 /* Prevent race conditions when updating:
3623 * - si_shader::scratch_bo
3624 * - si_shader::binary::code
3625 * - si_shader::previous_stage::binary::code.
3627 si_shader_lock(shader
);
3629 /* This shader is already configured to use the current
3630 * scratch buffer. */
3631 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3632 si_shader_unlock(shader
);
3636 assert(sctx
->scratch_buffer
);
3638 /* Replace the shader bo with a new bo that has the relocs applied. */
3639 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3640 si_shader_unlock(shader
);
3644 /* Update the shader state to use the new shader bo. */
3645 si_shader_init_pm4_state(sctx
->screen
, shader
);
3647 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3649 si_shader_unlock(shader
);
3653 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3655 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3658 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3660 if (!sctx
->tes_shader
.cso
)
3661 return NULL
; /* tessellation disabled */
3663 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3664 sctx
->fixed_func_tcs_shader
.current
;
3667 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3669 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3672 /* Update the shaders, so that they are using the latest scratch.
3673 * The scratch buffer may have been changed since these shaders were
3674 * last used, so we still need to try to update them, even if they
3675 * require scratch buffers smaller than the current size.
3677 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3681 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3683 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3687 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3689 r
= si_update_scratch_buffer(sctx
, tcs
);
3693 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3695 /* VS can be bound as LS, ES, or VS. */
3696 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3700 if (sctx
->vs_shader
.current
->key
.as_ls
)
3701 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3702 else if (sctx
->vs_shader
.current
->key
.as_es
)
3703 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3704 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3705 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3707 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3710 /* TES can be bound as ES or VS. */
3711 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3715 if (sctx
->tes_shader
.current
->key
.as_es
)
3716 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3717 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3718 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3720 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3726 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3728 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3729 * There are 2 cases to handle:
3731 * - If the current needed size is less than the maximum seen size,
3732 * use the maximum seen size, so that WAVESIZE remains the same.
3734 * - If the current needed size is greater than the maximum seen size,
3735 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3737 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3738 * Otherwise, the number of waves that can use scratch is
3739 * SPI_TMPRING_SIZE.WAVES.
3743 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3744 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3745 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3747 if (sctx
->tes_shader
.cso
) {
3748 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3749 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx
)));
3752 sctx
->max_seen_scratch_bytes_per_wave
=
3753 MAX2(sctx
->max_seen_scratch_bytes_per_wave
, bytes
);
3755 unsigned scratch_needed_size
=
3756 sctx
->max_seen_scratch_bytes_per_wave
* sctx
->scratch_waves
;
3757 unsigned spi_tmpring_size
;
3759 if (scratch_needed_size
> 0) {
3760 if (!sctx
->scratch_buffer
||
3761 scratch_needed_size
> sctx
->scratch_buffer
->b
.b
.width0
) {
3762 /* Create a bigger scratch buffer */
3763 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3765 sctx
->scratch_buffer
=
3766 si_aligned_buffer_create(&sctx
->screen
->b
,
3767 SI_RESOURCE_FLAG_UNMAPPABLE
,
3769 scratch_needed_size
,
3770 sctx
->screen
->info
.pte_fragment_size
);
3771 if (!sctx
->scratch_buffer
)
3774 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3775 si_context_add_resource_size(sctx
,
3776 &sctx
->scratch_buffer
->b
.b
);
3779 if (!si_update_scratch_relocs(sctx
))
3783 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3784 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3785 "scratch size should already be aligned correctly.");
3787 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3788 S_0286E8_WAVESIZE(sctx
->max_seen_scratch_bytes_per_wave
>> 10);
3789 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3790 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3791 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3796 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3798 assert(!sctx
->tess_rings
);
3799 assert(((sctx
->screen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
3801 /* The address must be aligned to 2^19, because the shader only
3802 * receives the high 13 bits.
3804 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3805 SI_RESOURCE_FLAG_32BIT
,
3807 sctx
->screen
->tess_offchip_ring_size
+
3808 sctx
->screen
->tess_factor_ring_size
,
3810 if (!sctx
->tess_rings
)
3813 si_init_config_add_vgt_flush(sctx
);
3815 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3816 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3818 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3819 sctx
->screen
->tess_offchip_ring_size
;
3821 /* Append these registers to the init config state. */
3822 if (sctx
->chip_class
>= GFX7
) {
3823 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3824 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3825 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3827 if (sctx
->chip_class
>= GFX10
)
3828 si_pm4_set_reg(sctx
->init_config
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3829 S_030984_BASE_HI(factor_va
>> 40));
3830 else if (sctx
->chip_class
== GFX9
)
3831 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3832 S_030944_BASE_HI(factor_va
>> 40));
3833 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3834 sctx
->screen
->vgt_hs_offchip_param
);
3836 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3837 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3838 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3840 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3841 sctx
->screen
->vgt_hs_offchip_param
);
3844 /* Flush the context to re-emit the init_config state.
3845 * This is done only once in a lifetime of a context.
3847 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3848 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3849 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3852 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3853 union si_vgt_stages_key key
)
3855 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3856 uint32_t stages
= 0;
3859 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3860 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3863 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3866 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3868 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3869 } else if (key
.u
.gs
) {
3870 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3872 } else if (key
.u
.ngg
) {
3873 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3877 stages
|= S_028B54_PRIMGEN_EN(1);
3878 if (key
.u
.streamout
)
3879 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
3880 } else if (key
.u
.gs
)
3881 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3883 if (screen
->info
.chip_class
>= GFX9
)
3884 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3886 if (screen
->info
.chip_class
>= GFX10
&& screen
->ge_wave_size
== 32) {
3887 stages
|= S_028B54_HS_W32_EN(1) |
3888 S_028B54_GS_W32_EN(key
.u
.ngg
) | /* legacy GS only supports Wave64 */
3889 S_028B54_VS_W32_EN(1);
3892 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3896 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3897 union si_vgt_stages_key key
)
3899 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3901 if (unlikely(!*pm4
))
3902 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3903 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3906 bool si_update_shaders(struct si_context
*sctx
)
3908 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3909 struct si_compiler_ctx_state compiler_state
;
3910 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3911 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3912 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3913 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3914 union si_vgt_stages_key key
;
3915 unsigned old_spi_shader_col_format
=
3916 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3919 compiler_state
.compiler
= &sctx
->compiler
;
3920 compiler_state
.debug
= sctx
->debug
;
3921 compiler_state
.is_debug_context
= sctx
->is_debug
;
3925 if (sctx
->tes_shader
.cso
)
3927 if (sctx
->gs_shader
.cso
)
3932 key
.u
.streamout
= !!si_get_vs(sctx
)->cso
->so
.num_outputs
;
3935 /* Update TCS and TES. */
3936 if (sctx
->tes_shader
.cso
) {
3937 if (!sctx
->tess_rings
) {
3938 si_init_tess_factor_ring(sctx
);
3939 if (!sctx
->tess_rings
)
3943 if (sctx
->tcs_shader
.cso
) {
3944 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
,
3948 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3950 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3951 sctx
->fixed_func_tcs_shader
.cso
=
3952 si_create_fixed_func_tcs(sctx
);
3953 if (!sctx
->fixed_func_tcs_shader
.cso
)
3957 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3958 key
, &compiler_state
);
3961 si_pm4_bind_state(sctx
, hs
,
3962 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3965 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
3966 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
3970 if (sctx
->gs_shader
.cso
) {
3972 assert(sctx
->chip_class
<= GFX8
);
3973 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3974 } else if (key
.u
.ngg
) {
3975 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3977 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3981 if (sctx
->chip_class
<= GFX8
)
3982 si_pm4_bind_state(sctx
, ls
, NULL
);
3983 si_pm4_bind_state(sctx
, hs
, NULL
);
3987 if (sctx
->gs_shader
.cso
) {
3988 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
3991 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3993 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3995 if (!si_update_gs_ring_buffers(sctx
))
3998 si_pm4_bind_state(sctx
, vs
, NULL
);
4002 si_pm4_bind_state(sctx
, gs
, NULL
);
4003 if (sctx
->chip_class
<= GFX8
)
4004 si_pm4_bind_state(sctx
, es
, NULL
);
4009 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
4010 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
4014 if (!key
.u
.tess
&& !key
.u
.gs
) {
4016 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
4017 si_pm4_bind_state(sctx
, vs
, NULL
);
4019 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
4021 } else if (sctx
->tes_shader
.cso
) {
4022 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
4024 assert(sctx
->gs_shader
.cso
);
4025 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
4029 si_update_vgt_shader_config(sctx
, key
);
4031 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
4032 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
4034 if (sctx
->ps_shader
.cso
) {
4035 unsigned db_shader_control
;
4037 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
4040 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
4043 sctx
->ps_shader
.cso
->db_shader_control
|
4044 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
4046 if (si_pm4_state_changed(sctx
, ps
) ||
4047 si_pm4_state_changed(sctx
, vs
) ||
4048 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
4049 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
4050 sctx
->flatshade
!= rs
->flatshade
) {
4051 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
4052 sctx
->flatshade
= rs
->flatshade
;
4053 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
4056 if (sctx
->screen
->info
.rbplus_allowed
&&
4057 si_pm4_state_changed(sctx
, ps
) &&
4059 old_spi_shader_col_format
!=
4060 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
4061 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
4063 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
4064 sctx
->ps_db_shader_control
= db_shader_control
;
4065 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4066 if (sctx
->screen
->dpbb_allowed
)
4067 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
4070 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
4071 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
4072 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
4074 if (sctx
->chip_class
== GFX6
)
4075 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4077 if (sctx
->framebuffer
.nr_samples
<= 1)
4078 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
4082 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
4083 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
4084 si_pm4_state_enabled_and_changed(sctx
, es
) ||
4085 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
4086 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
4087 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
4088 if (!si_update_spi_tmpring_size(sctx
))
4092 if (sctx
->chip_class
>= GFX7
) {
4093 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
4094 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
4095 else if (!sctx
->queued
.named
.ls
)
4096 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
4098 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
4099 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
4100 else if (!sctx
->queued
.named
.hs
)
4101 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
4103 if (si_pm4_state_enabled_and_changed(sctx
, es
))
4104 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
4105 else if (!sctx
->queued
.named
.es
)
4106 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
4108 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
4109 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
4110 else if (!sctx
->queued
.named
.gs
)
4111 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
4113 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
4114 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
4115 else if (!sctx
->queued
.named
.vs
)
4116 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
4118 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
4119 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
4120 else if (!sctx
->queued
.named
.ps
)
4121 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
4124 sctx
->do_update_shaders
= false;
4128 static void si_emit_scratch_state(struct si_context
*sctx
)
4130 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4132 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
4133 sctx
->spi_tmpring_size
);
4135 if (sctx
->scratch_buffer
) {
4136 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
4137 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
4138 RADEON_PRIO_SCRATCH_BUFFER
);
4142 void si_init_shader_functions(struct si_context
*sctx
)
4144 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
4145 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
4147 sctx
->b
.create_vs_state
= si_create_shader_selector
;
4148 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
4149 sctx
->b
.create_tes_state
= si_create_shader_selector
;
4150 sctx
->b
.create_gs_state
= si_create_shader_selector
;
4151 sctx
->b
.create_fs_state
= si_create_shader_selector
;
4153 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
4154 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
4155 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
4156 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
4157 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
4159 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
4160 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
4161 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
4162 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
4163 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;