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radeonsi/gfx10: set HS/GS/CS.WGP_MODE
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "tgsi/tgsi_parse.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
45 * size as integer.
46 */
47 void *si_get_ir_binary(struct si_shader_selector *sel)
48 {
49 struct blob blob;
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->tokens) {
54 ir_binary = sel->tokens;
55 ir_size = tgsi_num_tokens(sel->tokens) *
56 sizeof(struct tgsi_token);
57 } else {
58 assert(sel->nir);
59
60 blob_init(&blob);
61 nir_serialize(&blob, sel->nir);
62 ir_binary = blob.data;
63 ir_size = blob.size;
64 }
65
66 unsigned size = 4 + ir_size + sizeof(sel->so);
67 char *result = (char*)MALLOC(size);
68 if (!result)
69 return NULL;
70
71 *((uint32_t*)result) = size;
72 memcpy(result + 4, ir_binary, ir_size);
73 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
74
75 if (sel->nir)
76 blob_finish(&blob);
77
78 return result;
79 }
80
81 /** Copy "data" to "ptr" and return the next dword following copied data. */
82 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
83 {
84 /* data may be NULL if size == 0 */
85 if (size)
86 memcpy(ptr, data, size);
87 ptr += DIV_ROUND_UP(size, 4);
88 return ptr;
89 }
90
91 /** Read data from "ptr". Return the next dword following the data. */
92 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
93 {
94 memcpy(data, ptr, size);
95 ptr += DIV_ROUND_UP(size, 4);
96 return ptr;
97 }
98
99 /**
100 * Write the size as uint followed by the data. Return the next dword
101 * following the copied data.
102 */
103 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
104 {
105 *ptr++ = size;
106 return write_data(ptr, data, size);
107 }
108
109 /**
110 * Read the size as uint followed by the data. Return both via parameters.
111 * Return the next dword following the data.
112 */
113 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
114 {
115 *size = *ptr++;
116 assert(*data == NULL);
117 if (!*size)
118 return ptr;
119 *data = malloc(*size);
120 return read_data(ptr, *data, *size);
121 }
122
123 /**
124 * Return the shader binary in a buffer. The first 4 bytes contain its size
125 * as integer.
126 */
127 static void *si_get_shader_binary(struct si_shader *shader)
128 {
129 /* There is always a size of data followed by the data itself. */
130 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
131 strlen(shader->binary.llvm_ir_string) + 1 : 0;
132
133 /* Refuse to allocate overly large buffers and guard against integer
134 * overflow. */
135 if (shader->binary.elf_size > UINT_MAX / 4 ||
136 llvm_ir_size > UINT_MAX / 4)
137 return NULL;
138
139 unsigned size =
140 4 + /* total size */
141 4 + /* CRC32 of the data below */
142 align(sizeof(shader->config), 4) +
143 align(sizeof(shader->info), 4) +
144 4 + align(shader->binary.elf_size, 4) +
145 4 + align(llvm_ir_size, 4);
146 void *buffer = CALLOC(1, size);
147 uint32_t *ptr = (uint32_t*)buffer;
148
149 if (!buffer)
150 return NULL;
151
152 *ptr++ = size;
153 ptr++; /* CRC32 is calculated at the end. */
154
155 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
156 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
157 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
158 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
159 assert((char *)ptr - (char *)buffer == size);
160
161 /* Compute CRC32. */
162 ptr = (uint32_t*)buffer;
163 ptr++;
164 *ptr = util_hash_crc32(ptr + 1, size - 8);
165
166 return buffer;
167 }
168
169 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
170 {
171 uint32_t *ptr = (uint32_t*)binary;
172 uint32_t size = *ptr++;
173 uint32_t crc32 = *ptr++;
174 unsigned chunk_size;
175 unsigned elf_size;
176
177 if (util_hash_crc32(ptr, size - 8) != crc32) {
178 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
179 return false;
180 }
181
182 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
183 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
184 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
185 &elf_size);
186 shader->binary.elf_size = elf_size;
187 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
188
189 return true;
190 }
191
192 /**
193 * Insert a shader into the cache. It's assumed the shader is not in the cache.
194 * Use si_shader_cache_load_shader before calling this.
195 *
196 * Returns false on failure, in which case the ir_binary should be freed.
197 */
198 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
199 struct si_shader *shader,
200 bool insert_into_disk_cache)
201 {
202 void *hw_binary;
203 struct hash_entry *entry;
204 uint8_t key[CACHE_KEY_SIZE];
205
206 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
207 if (entry)
208 return false; /* already added */
209
210 hw_binary = si_get_shader_binary(shader);
211 if (!hw_binary)
212 return false;
213
214 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
215 hw_binary) == NULL) {
216 FREE(hw_binary);
217 return false;
218 }
219
220 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
221 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
222 *((uint32_t *)ir_binary), key);
223 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
224 *((uint32_t *) hw_binary), NULL);
225 }
226
227 return true;
228 }
229
230 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
231 struct si_shader *shader)
232 {
233 struct hash_entry *entry =
234 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
235 if (!entry) {
236 if (sscreen->disk_shader_cache) {
237 unsigned char sha1[CACHE_KEY_SIZE];
238 size_t tg_size = *((uint32_t *) ir_binary);
239
240 disk_cache_compute_key(sscreen->disk_shader_cache,
241 ir_binary, tg_size, sha1);
242
243 size_t binary_size;
244 uint8_t *buffer =
245 disk_cache_get(sscreen->disk_shader_cache,
246 sha1, &binary_size);
247 if (!buffer)
248 return false;
249
250 if (binary_size < sizeof(uint32_t) ||
251 *((uint32_t*)buffer) != binary_size) {
252 /* Something has gone wrong discard the item
253 * from the cache and rebuild/link from
254 * source.
255 */
256 assert(!"Invalid radeonsi shader disk cache "
257 "item!");
258
259 disk_cache_remove(sscreen->disk_shader_cache,
260 sha1);
261 free(buffer);
262
263 return false;
264 }
265
266 if (!si_load_shader_binary(shader, buffer)) {
267 free(buffer);
268 return false;
269 }
270 free(buffer);
271
272 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
273 shader, false))
274 FREE(ir_binary);
275 } else {
276 return false;
277 }
278 } else {
279 if (si_load_shader_binary(shader, entry->data))
280 FREE(ir_binary);
281 else
282 return false;
283 }
284 p_atomic_inc(&sscreen->num_shader_cache_hits);
285 return true;
286 }
287
288 static uint32_t si_shader_cache_key_hash(const void *key)
289 {
290 /* The first dword is the key size. */
291 return util_hash_crc32(key, *(uint32_t*)key);
292 }
293
294 static bool si_shader_cache_key_equals(const void *a, const void *b)
295 {
296 uint32_t *keya = (uint32_t*)a;
297 uint32_t *keyb = (uint32_t*)b;
298
299 /* The first dword is the key size. */
300 if (*keya != *keyb)
301 return false;
302
303 return memcmp(keya, keyb, *keya) == 0;
304 }
305
306 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
307 {
308 FREE((void*)entry->key);
309 FREE(entry->data);
310 }
311
312 bool si_init_shader_cache(struct si_screen *sscreen)
313 {
314 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
315 sscreen->shader_cache =
316 _mesa_hash_table_create(NULL,
317 si_shader_cache_key_hash,
318 si_shader_cache_key_equals);
319
320 return sscreen->shader_cache != NULL;
321 }
322
323 void si_destroy_shader_cache(struct si_screen *sscreen)
324 {
325 if (sscreen->shader_cache)
326 _mesa_hash_table_destroy(sscreen->shader_cache,
327 si_destroy_shader_cache_entry);
328 mtx_destroy(&sscreen->shader_cache_mutex);
329 }
330
331 /* SHADER STATES */
332
333 static void si_set_tesseval_regs(struct si_screen *sscreen,
334 const struct si_shader_selector *tes,
335 struct si_pm4_state *pm4)
336 {
337 const struct tgsi_shader_info *info = &tes->info;
338 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
339 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
340 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
341 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
342 unsigned type, partitioning, topology, distribution_mode;
343
344 switch (tes_prim_mode) {
345 case PIPE_PRIM_LINES:
346 type = V_028B6C_TESS_ISOLINE;
347 break;
348 case PIPE_PRIM_TRIANGLES:
349 type = V_028B6C_TESS_TRIANGLE;
350 break;
351 case PIPE_PRIM_QUADS:
352 type = V_028B6C_TESS_QUAD;
353 break;
354 default:
355 assert(0);
356 return;
357 }
358
359 switch (tes_spacing) {
360 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
361 partitioning = V_028B6C_PART_FRAC_ODD;
362 break;
363 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
364 partitioning = V_028B6C_PART_FRAC_EVEN;
365 break;
366 case PIPE_TESS_SPACING_EQUAL:
367 partitioning = V_028B6C_PART_INTEGER;
368 break;
369 default:
370 assert(0);
371 return;
372 }
373
374 if (tes_point_mode)
375 topology = V_028B6C_OUTPUT_POINT;
376 else if (tes_prim_mode == PIPE_PRIM_LINES)
377 topology = V_028B6C_OUTPUT_LINE;
378 else if (tes_vertex_order_cw)
379 /* for some reason, this must be the other way around */
380 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
381 else
382 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
383
384 if (sscreen->has_distributed_tess) {
385 if (sscreen->info.family == CHIP_FIJI ||
386 sscreen->info.family >= CHIP_POLARIS10)
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
388 else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
390 } else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
392
393 assert(pm4->shader);
394 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
395 S_028B6C_PARTITIONING(partitioning) |
396 S_028B6C_TOPOLOGY(topology) |
397 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
398 }
399
400 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
401 * whether the "fractional odd" tessellation spacing is used.
402 *
403 * Possible VGT configurations and which state should set the register:
404 *
405 * Reg set in | VGT shader configuration | Value
406 * ------------------------------------------------------
407 * VS as VS | VS | 30
408 * VS as ES | ES -> GS -> VS | 30
409 * TES as VS | LS -> HS -> VS | 14 or 30
410 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
411 *
412 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
413 */
414 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
415 struct si_shader_selector *sel,
416 struct si_shader *shader,
417 struct si_pm4_state *pm4)
418 {
419 unsigned type = sel->type;
420
421 if (sscreen->info.family < CHIP_POLARIS10 ||
422 sscreen->info.chip_class >= GFX10)
423 return;
424
425 /* VS as VS, or VS as ES: */
426 if ((type == PIPE_SHADER_VERTEX &&
427 (!shader ||
428 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
429 /* TES as VS, or TES as ES: */
430 type == PIPE_SHADER_TESS_EVAL) {
431 unsigned vtx_reuse_depth = 30;
432
433 if (type == PIPE_SHADER_TESS_EVAL &&
434 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
435 PIPE_TESS_SPACING_FRACTIONAL_ODD)
436 vtx_reuse_depth = 14;
437
438 assert(pm4->shader);
439 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
440 }
441 }
442
443 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
444 {
445 if (shader->pm4)
446 si_pm4_clear_state(shader->pm4);
447 else
448 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
449
450 if (shader->pm4) {
451 shader->pm4->shader = shader;
452 return shader->pm4;
453 } else {
454 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
455 return NULL;
456 }
457 }
458
459 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
460 {
461 /* Add the pointer to VBO descriptors. */
462 return num_always_on_user_sgprs + 1;
463 }
464
465 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
466 {
467 struct si_pm4_state *pm4;
468 unsigned vgpr_comp_cnt;
469 uint64_t va;
470
471 assert(sscreen->info.chip_class <= GFX8);
472
473 pm4 = si_get_shader_pm4_state(shader);
474 if (!pm4)
475 return;
476
477 va = shader->bo->gpu_address;
478 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
479
480 /* We need at least 2 components for LS.
481 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
482 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
483 */
484 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
485
486 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
487 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
488
489 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
490 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
491 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
492 S_00B528_DX10_CLAMP(1) |
493 S_00B528_FLOAT_MODE(shader->config.float_mode);
494 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
495 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
496 }
497
498 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
499 {
500 struct si_pm4_state *pm4;
501 uint64_t va;
502 unsigned ls_vgpr_comp_cnt = 0;
503
504 pm4 = si_get_shader_pm4_state(shader);
505 if (!pm4)
506 return;
507
508 va = shader->bo->gpu_address;
509 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
510
511 if (sscreen->info.chip_class >= GFX9) {
512 if (sscreen->info.chip_class >= GFX10) {
513 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
514 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
515 } else {
516 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
518 }
519
520 /* We need at least 2 components for LS.
521 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
522 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
523 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
524 * be loaded.
525 */
526 ls_vgpr_comp_cnt = 1;
527 if (shader->info.uses_instanceid) {
528 if (sscreen->info.chip_class >= GFX10)
529 ls_vgpr_comp_cnt = 3;
530 else
531 ls_vgpr_comp_cnt = 2;
532 }
533
534 unsigned num_user_sgprs =
535 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
536
537 shader->config.rsrc2 =
538 S_00B42C_USER_SGPR(num_user_sgprs) |
539 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
540
541 if (sscreen->info.chip_class >= GFX10)
542 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
543 else
544 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
545 } else {
546 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
547 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
548
549 shader->config.rsrc2 =
550 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
551 S_00B42C_OC_LDS_EN(1) |
552 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
553 }
554
555 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
556 S_00B428_VGPRS((shader->config.num_vgprs - 1) / 4) |
557 (sscreen->info.chip_class <= GFX9 ?
558 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
559 S_00B428_DX10_CLAMP(1) |
560 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
561 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
562 S_00B428_FLOAT_MODE(shader->config.float_mode) |
563 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
564
565 if (sscreen->info.chip_class <= GFX8) {
566 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
567 shader->config.rsrc2);
568 }
569 }
570
571 static void si_emit_shader_es(struct si_context *sctx)
572 {
573 struct si_shader *shader = sctx->queued.named.es->shader;
574 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
575
576 if (!shader)
577 return;
578
579 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
580 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
581 shader->selector->esgs_itemsize / 4);
582
583 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
584 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
585 SI_TRACKED_VGT_TF_PARAM,
586 shader->vgt_tf_param);
587
588 if (shader->vgt_vertex_reuse_block_cntl)
589 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
590 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
591 shader->vgt_vertex_reuse_block_cntl);
592
593 if (initial_cdw != sctx->gfx_cs->current.cdw)
594 sctx->context_roll = true;
595 }
596
597 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
598 {
599 struct si_pm4_state *pm4;
600 unsigned num_user_sgprs;
601 unsigned vgpr_comp_cnt;
602 uint64_t va;
603 unsigned oc_lds_en;
604
605 assert(sscreen->info.chip_class <= GFX8);
606
607 pm4 = si_get_shader_pm4_state(shader);
608 if (!pm4)
609 return;
610
611 pm4->atom.emit = si_emit_shader_es;
612 va = shader->bo->gpu_address;
613 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
614
615 if (shader->selector->type == PIPE_SHADER_VERTEX) {
616 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
617 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
618 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
619 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
620 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
621 num_user_sgprs = SI_TES_NUM_USER_SGPR;
622 } else
623 unreachable("invalid shader selector type");
624
625 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
626
627 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
628 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
629 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
630 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
631 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
632 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
633 S_00B328_DX10_CLAMP(1) |
634 S_00B328_FLOAT_MODE(shader->config.float_mode));
635 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
636 S_00B32C_USER_SGPR(num_user_sgprs) |
637 S_00B32C_OC_LDS_EN(oc_lds_en) |
638 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
639
640 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
641 si_set_tesseval_regs(sscreen, shader->selector, pm4);
642
643 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
644 }
645
646 void gfx9_get_gs_info(struct si_shader_selector *es,
647 struct si_shader_selector *gs,
648 struct gfx9_gs_info *out)
649 {
650 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
651 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
652 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
653 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
654
655 /* All these are in dwords: */
656 /* We can't allow using the whole LDS, because GS waves compete with
657 * other shader stages for LDS space. */
658 const unsigned max_lds_size = 8 * 1024;
659 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
660 unsigned esgs_lds_size;
661
662 /* All these are per subgroup: */
663 const unsigned max_out_prims = 32 * 1024;
664 const unsigned max_es_verts = 255;
665 const unsigned ideal_gs_prims = 64;
666 unsigned max_gs_prims, gs_prims;
667 unsigned min_es_verts, es_verts, worst_case_es_verts;
668
669 if (uses_adjacency || gs_num_invocations > 1)
670 max_gs_prims = 127 / gs_num_invocations;
671 else
672 max_gs_prims = 255;
673
674 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
675 * Make sure we don't go over the maximum value.
676 */
677 if (gs->gs_max_out_vertices > 0) {
678 max_gs_prims = MIN2(max_gs_prims,
679 max_out_prims /
680 (gs->gs_max_out_vertices * gs_num_invocations));
681 }
682 assert(max_gs_prims > 0);
683
684 /* If the primitive has adjacency, halve the number of vertices
685 * that will be reused in multiple primitives.
686 */
687 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
688
689 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
690 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
691
692 /* Compute ESGS LDS size based on the worst case number of ES vertices
693 * needed to create the target number of GS prims per subgroup.
694 */
695 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
696
697 /* If total LDS usage is too big, refactor partitions based on ratio
698 * of ESGS item sizes.
699 */
700 if (esgs_lds_size > max_lds_size) {
701 /* Our target GS Prims Per Subgroup was too large. Calculate
702 * the maximum number of GS Prims Per Subgroup that will fit
703 * into LDS, capped by the maximum that the hardware can support.
704 */
705 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
706 max_gs_prims);
707 assert(gs_prims > 0);
708 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
709 max_es_verts);
710
711 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
712 assert(esgs_lds_size <= max_lds_size);
713 }
714
715 /* Now calculate remaining ESGS information. */
716 if (esgs_lds_size)
717 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
718 else
719 es_verts = max_es_verts;
720
721 /* Vertices for adjacency primitives are not always reused, so restore
722 * it for ES_VERTS_PER_SUBGRP.
723 */
724 min_es_verts = gs->gs_input_verts_per_prim;
725
726 /* For normal primitives, the VGT only checks if they are past the ES
727 * verts per subgroup after allocating a full GS primitive and if they
728 * are, kick off a new subgroup. But if those additional ES verts are
729 * unique (e.g. not reused) we need to make sure there is enough LDS
730 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
731 */
732 es_verts -= min_es_verts - 1;
733
734 out->es_verts_per_subgroup = es_verts;
735 out->gs_prims_per_subgroup = gs_prims;
736 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
737 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
738 gs->gs_max_out_vertices;
739 out->esgs_ring_size = 4 * esgs_lds_size;
740
741 assert(out->max_prims_per_subgroup <= max_out_prims);
742 }
743
744 static void si_emit_shader_gs(struct si_context *sctx)
745 {
746 struct si_shader *shader = sctx->queued.named.gs->shader;
747 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
748
749 if (!shader)
750 return;
751
752 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
753 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
754 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
755 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
756 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
757 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
758 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
759
760 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
761 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
762 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
763 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
764
765 /* R_028B38_VGT_GS_MAX_VERT_OUT */
766 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
767 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
768 shader->ctx_reg.gs.vgt_gs_max_vert_out);
769
770 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
771 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
772 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
773 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
774 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
775 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
776 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
777 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
778
779 /* R_028B90_VGT_GS_INSTANCE_CNT */
780 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
781 SI_TRACKED_VGT_GS_INSTANCE_CNT,
782 shader->ctx_reg.gs.vgt_gs_instance_cnt);
783
784 if (sctx->chip_class >= GFX9) {
785 /* R_028A44_VGT_GS_ONCHIP_CNTL */
786 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
787 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
788 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
789 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
790 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
791 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
792 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
793 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
794 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
795 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
796 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
797
798 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
799 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
800 SI_TRACKED_VGT_TF_PARAM,
801 shader->vgt_tf_param);
802 if (shader->vgt_vertex_reuse_block_cntl)
803 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
804 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
805 shader->vgt_vertex_reuse_block_cntl);
806 }
807
808 if (initial_cdw != sctx->gfx_cs->current.cdw)
809 sctx->context_roll = true;
810 }
811
812 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
813 {
814 struct si_shader_selector *sel = shader->selector;
815 const ubyte *num_components = sel->info.num_stream_output_components;
816 unsigned gs_num_invocations = sel->gs_num_invocations;
817 struct si_pm4_state *pm4;
818 uint64_t va;
819 unsigned max_stream = sel->max_gs_stream;
820 unsigned offset;
821
822 pm4 = si_get_shader_pm4_state(shader);
823 if (!pm4)
824 return;
825
826 pm4->atom.emit = si_emit_shader_gs;
827
828 offset = num_components[0] * sel->gs_max_out_vertices;
829 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
830
831 if (max_stream >= 1)
832 offset += num_components[1] * sel->gs_max_out_vertices;
833 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
834
835 if (max_stream >= 2)
836 offset += num_components[2] * sel->gs_max_out_vertices;
837 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
838
839 if (max_stream >= 3)
840 offset += num_components[3] * sel->gs_max_out_vertices;
841 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
842
843 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
844 assert(offset < (1 << 15));
845
846 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
847
848 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
849 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
851 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
852
853 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
854 S_028B90_ENABLE(gs_num_invocations > 0);
855
856 va = shader->bo->gpu_address;
857 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
858
859 if (sscreen->info.chip_class >= GFX9) {
860 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
861 unsigned es_type = shader->key.part.gs.es->type;
862 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
863
864 if (es_type == PIPE_SHADER_VERTEX)
865 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
866 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
867 else if (es_type == PIPE_SHADER_TESS_EVAL)
868 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
869 else
870 unreachable("invalid shader selector type");
871
872 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
873 * VGPR[0:4] are always loaded.
874 */
875 if (sel->info.uses_invocationid)
876 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
877 else if (sel->info.uses_primid)
878 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
879 else if (input_prim >= PIPE_PRIM_TRIANGLES)
880 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
881 else
882 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
883
884 unsigned num_user_sgprs;
885 if (es_type == PIPE_SHADER_VERTEX)
886 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
887 else
888 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
889
890 if (sscreen->info.chip_class >= GFX10) {
891 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
892 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
893 } else {
894 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
895 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
896 }
897
898 uint32_t rsrc1 =
899 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
900 S_00B228_DX10_CLAMP(1) |
901 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
902 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
903 S_00B228_FLOAT_MODE(shader->config.float_mode) |
904 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
905 uint32_t rsrc2 =
906 S_00B22C_USER_SGPR(num_user_sgprs) |
907 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
908 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
909 S_00B22C_LDS_SIZE(shader->config.lds_size) |
910 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
911
912 if (sscreen->info.chip_class >= GFX10) {
913 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
914 } else {
915 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
916 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
917 }
918
919 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
920 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
921
922 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
923 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
924 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
925 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
926 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
927 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
928 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
929 shader->key.part.gs.es->esgs_itemsize / 4;
930
931 if (es_type == PIPE_SHADER_TESS_EVAL)
932 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
933
934 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
935 NULL, pm4);
936 } else {
937 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
938 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
939
940 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
941 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
942 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
943 S_00B228_DX10_CLAMP(1) |
944 S_00B228_FLOAT_MODE(shader->config.float_mode));
945 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
946 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
947 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
948 }
949 }
950
951 /* Common tail code for NGG primitive shaders. */
952 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
953 struct si_shader *shader,
954 unsigned initial_cdw)
955 {
956 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
957 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
958 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
959 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
960 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
961 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
962 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
963 SI_TRACKED_VGT_PRIMITIVEID_EN,
964 shader->ctx_reg.ngg.vgt_primitiveid_en);
965 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
966 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
967 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
968 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
969 SI_TRACKED_VGT_GS_INSTANCE_CNT,
970 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
971 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
972 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
973 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
974 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
975 SI_TRACKED_VGT_REUSE_OFF,
976 shader->ctx_reg.ngg.vgt_reuse_off);
977 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
978 SI_TRACKED_SPI_VS_OUT_CONFIG,
979 shader->ctx_reg.ngg.spi_vs_out_config);
980 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
981 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
982 shader->ctx_reg.ngg.spi_shader_idx_format,
983 shader->ctx_reg.ngg.spi_shader_pos_format);
984 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
985 SI_TRACKED_PA_CL_VTE_CNTL,
986 shader->ctx_reg.ngg.pa_cl_vte_cntl);
987 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
988 SI_TRACKED_PA_CL_NGG_CNTL,
989 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
990
991 if (initial_cdw != sctx->gfx_cs->current.cdw)
992 sctx->context_roll = true;
993
994 if (shader->ge_cntl != sctx->last_multi_vgt_param) {
995 radeon_set_uconfig_reg(sctx->gfx_cs, R_03096C_GE_CNTL, shader->ge_cntl);
996 sctx->last_multi_vgt_param = shader->ge_cntl;
997 }
998 }
999
1000 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1001 {
1002 struct si_shader *shader = sctx->queued.named.gs->shader;
1003 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1004
1005 if (!shader)
1006 return;
1007
1008 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1009 }
1010
1011 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1012 {
1013 struct si_shader *shader = sctx->queued.named.gs->shader;
1014 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1015
1016 if (!shader)
1017 return;
1018
1019 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1020 SI_TRACKED_VGT_TF_PARAM,
1021 shader->vgt_tf_param);
1022
1023 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1024 }
1025
1026 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1027 {
1028 struct si_shader *shader = sctx->queued.named.gs->shader;
1029 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1030
1031 if (!shader)
1032 return;
1033
1034 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1035 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1036 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1037
1038 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1039 }
1040
1041 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1042 {
1043 struct si_shader *shader = sctx->queued.named.gs->shader;
1044 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1045
1046 if (!shader)
1047 return;
1048
1049 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1050 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1051 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1052 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1053 SI_TRACKED_VGT_TF_PARAM,
1054 shader->vgt_tf_param);
1055
1056 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1057 }
1058
1059 static void si_set_ge_pc_alloc(struct si_screen *sscreen,
1060 struct si_pm4_state *pm4, bool culling)
1061 {
1062 si_pm4_set_reg(pm4, R_030980_GE_PC_ALLOC,
1063 S_030980_OVERSUB_EN(1) |
1064 S_030980_NUM_PC_LINES((culling ? 256 : 128) * sscreen->info.max_se - 1));
1065 }
1066
1067 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1068 {
1069 if (gs->type == PIPE_SHADER_GEOMETRY)
1070 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1071
1072 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1073 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1074 return PIPE_PRIM_POINTS;
1075 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1076 return PIPE_PRIM_LINES;
1077 return PIPE_PRIM_TRIANGLES;
1078 }
1079
1080 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1081 return PIPE_PRIM_TRIANGLES;
1082 }
1083
1084 /**
1085 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1086 * in NGG mode.
1087 */
1088 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1089 {
1090 const struct si_shader_selector *gs_sel = shader->selector;
1091 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1092 enum pipe_shader_type gs_type = shader->selector->type;
1093 const struct si_shader_selector *es_sel =
1094 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1095 const struct tgsi_shader_info *es_info = &es_sel->info;
1096 enum pipe_shader_type es_type = es_sel->type;
1097 unsigned num_user_sgprs;
1098 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1099 uint64_t va;
1100 unsigned window_space =
1101 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1102 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1103 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1104 unsigned input_prim = si_get_input_prim(gs_sel);
1105 bool break_wave_at_eoi = false;
1106 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1107 if (!pm4)
1108 return;
1109
1110 if (es_type == PIPE_SHADER_TESS_EVAL) {
1111 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1112 : gfx10_emit_shader_ngg_tess_nogs;
1113 } else {
1114 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1115 : gfx10_emit_shader_ngg_notess_nogs;
1116 }
1117
1118 va = shader->bo->gpu_address;
1119 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1120
1121 if (es_type == PIPE_SHADER_VERTEX) {
1122 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1123 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1124
1125 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1126 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1127 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1128 } else {
1129 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1130 }
1131 } else {
1132 assert(es_type == PIPE_SHADER_TESS_EVAL);
1133 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1134 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1135
1136 if (es_enable_prim_id || gs_info->uses_primid)
1137 break_wave_at_eoi = true;
1138 }
1139
1140 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1141 * VGPR[0:4] are always loaded.
1142 *
1143 * Vertex shaders always need to load VGPR3, because they need to
1144 * pass edge flags for decomposed primitives (such as quads) to the PA
1145 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1146 */
1147 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1148 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1149 else if (gs_info->uses_primid)
1150 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1151 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1152 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1153 else
1154 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1155
1156 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1157 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1158 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1159 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
1160 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1161 S_00B228_DX10_CLAMP(1) |
1162 S_00B228_MEM_ORDERED(1) |
1163 S_00B228_WGP_MODE(1) |
1164 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1165 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1166 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1167 S_00B22C_USER_SGPR(num_user_sgprs) |
1168 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1169 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1170 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1171 S_00B22C_LDS_SIZE(shader->config.lds_size));
1172 si_set_ge_pc_alloc(sscreen, pm4, false);
1173
1174 nparams = MAX2(shader->info.nr_param_exports, 1);
1175 shader->ctx_reg.ngg.spi_vs_out_config =
1176 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1177 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1178
1179 shader->ctx_reg.ngg.spi_shader_idx_format =
1180 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1181 shader->ctx_reg.ngg.spi_shader_pos_format =
1182 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1183 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1184 V_02870C_SPI_SHADER_4COMP :
1185 V_02870C_SPI_SHADER_NONE) |
1186 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1187 V_02870C_SPI_SHADER_4COMP :
1188 V_02870C_SPI_SHADER_NONE) |
1189 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1190 V_02870C_SPI_SHADER_4COMP :
1191 V_02870C_SPI_SHADER_NONE);
1192
1193 shader->ctx_reg.ngg.vgt_primitiveid_en =
1194 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1195 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1196
1197 if (gs_type == PIPE_SHADER_GEOMETRY) {
1198 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1199 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1200 } else {
1201 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1202 }
1203
1204 if (es_type == PIPE_SHADER_TESS_EVAL)
1205 si_set_tesseval_regs(sscreen, es_sel, pm4);
1206
1207 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1208 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1209 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1210 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1211 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1212 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1213 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1214 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1215 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1216 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1217 S_028B90_CNT(gs_num_invocations) |
1218 S_028B90_ENABLE(gs_num_invocations > 1) |
1219 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1220 shader->ngg.max_vert_out_per_gs_instance);
1221
1222 /* User edge flags are set by the pos exports. If user edge flags are
1223 * not used, we must use hw-generated edge flags and pass them via
1224 * the prim export to prevent drawing lines on internal edges of
1225 * decomposed primitives (such as quads) with polygon mode = lines.
1226 *
1227 * TODO: We should combine hw-generated edge flags with user edge
1228 * flags in the shader.
1229 */
1230 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1231 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX &&
1232 !gs_info->writes_edgeflag);
1233
1234 shader->ge_cntl =
1235 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1236 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1237 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1238
1239 if (window_space) {
1240 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1241 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1242 } else {
1243 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1244 S_028818_VTX_W0_FMT(1) |
1245 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1246 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1247 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1248 }
1249
1250 shader->ctx_reg.ngg.vgt_reuse_off =
1251 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1252 sscreen->info.chip_external_rev == 0x1 &&
1253 es_type == PIPE_SHADER_TESS_EVAL);
1254 }
1255
1256 static void si_emit_shader_vs(struct si_context *sctx)
1257 {
1258 struct si_shader *shader = sctx->queued.named.vs->shader;
1259 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1260
1261 if (!shader)
1262 return;
1263
1264 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1265 SI_TRACKED_VGT_GS_MODE,
1266 shader->ctx_reg.vs.vgt_gs_mode);
1267 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1268 SI_TRACKED_VGT_PRIMITIVEID_EN,
1269 shader->ctx_reg.vs.vgt_primitiveid_en);
1270
1271 if (sctx->chip_class <= GFX8) {
1272 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1273 SI_TRACKED_VGT_REUSE_OFF,
1274 shader->ctx_reg.vs.vgt_reuse_off);
1275 }
1276
1277 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1278 SI_TRACKED_SPI_VS_OUT_CONFIG,
1279 shader->ctx_reg.vs.spi_vs_out_config);
1280
1281 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1282 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1283 shader->ctx_reg.vs.spi_shader_pos_format);
1284
1285 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1286 SI_TRACKED_PA_CL_VTE_CNTL,
1287 shader->ctx_reg.vs.pa_cl_vte_cntl);
1288
1289 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1290 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1291 SI_TRACKED_VGT_TF_PARAM,
1292 shader->vgt_tf_param);
1293
1294 if (shader->vgt_vertex_reuse_block_cntl)
1295 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1296 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1297 shader->vgt_vertex_reuse_block_cntl);
1298
1299 if (initial_cdw != sctx->gfx_cs->current.cdw)
1300 sctx->context_roll = true;
1301 }
1302
1303 /**
1304 * Compute the state for \p shader, which will run as a vertex shader on the
1305 * hardware.
1306 *
1307 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1308 * is the copy shader.
1309 */
1310 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1311 struct si_shader_selector *gs)
1312 {
1313 const struct tgsi_shader_info *info = &shader->selector->info;
1314 struct si_pm4_state *pm4;
1315 unsigned num_user_sgprs, vgpr_comp_cnt;
1316 uint64_t va;
1317 unsigned nparams, oc_lds_en;
1318 unsigned window_space =
1319 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1320 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1321
1322 pm4 = si_get_shader_pm4_state(shader);
1323 if (!pm4)
1324 return;
1325
1326 pm4->atom.emit = si_emit_shader_vs;
1327
1328 /* We always write VGT_GS_MODE in the VS state, because every switch
1329 * between different shader pipelines involving a different GS or no
1330 * GS at all involves a switch of the VS (different GS use different
1331 * copy shaders). On the other hand, when the API switches from a GS to
1332 * no GS and then back to the same GS used originally, the GS state is
1333 * not sent again.
1334 */
1335 if (!gs) {
1336 unsigned mode = V_028A40_GS_OFF;
1337
1338 /* PrimID needs GS scenario A. */
1339 if (enable_prim_id)
1340 mode = V_028A40_GS_SCENARIO_A;
1341
1342 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1343 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1344 } else {
1345 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1346 sscreen->info.chip_class);
1347 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1348 }
1349
1350 if (sscreen->info.chip_class <= GFX8) {
1351 /* Reuse needs to be set off if we write oViewport. */
1352 shader->ctx_reg.vs.vgt_reuse_off =
1353 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1354 }
1355
1356 va = shader->bo->gpu_address;
1357 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1358
1359 if (gs) {
1360 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1361 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1362 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1363 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1364 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1365 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1366 */
1367 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1368
1369 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1370 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1371 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1372 } else {
1373 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1374 }
1375 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1376 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1377 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1378 } else
1379 unreachable("invalid shader selector type");
1380
1381 /* VS is required to export at least one param. */
1382 nparams = MAX2(shader->info.nr_param_exports, 1);
1383 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1384
1385 if (sscreen->info.chip_class >= GFX10) {
1386 shader->ctx_reg.vs.spi_vs_out_config |=
1387 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1388 }
1389
1390 shader->ctx_reg.vs.spi_shader_pos_format =
1391 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1392 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1393 V_02870C_SPI_SHADER_4COMP :
1394 V_02870C_SPI_SHADER_NONE) |
1395 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1396 V_02870C_SPI_SHADER_4COMP :
1397 V_02870C_SPI_SHADER_NONE) |
1398 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1399 V_02870C_SPI_SHADER_4COMP :
1400 V_02870C_SPI_SHADER_NONE);
1401
1402 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1403
1404 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1405 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1406 if (sscreen->info.chip_class >= GFX10)
1407 si_set_ge_pc_alloc(sscreen, pm4, false);
1408
1409 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) / 4) |
1410 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1411 S_00B128_DX10_CLAMP(1) |
1412 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1413 S_00B128_FLOAT_MODE(shader->config.float_mode);
1414 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1415 S_00B12C_OC_LDS_EN(oc_lds_en) |
1416 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1417
1418 if (sscreen->info.chip_class <= GFX9) {
1419 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1420 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1421 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1422 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1423 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1424 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1425 }
1426
1427 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1428 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1429
1430 if (window_space)
1431 shader->ctx_reg.vs.pa_cl_vte_cntl =
1432 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1433 else
1434 shader->ctx_reg.vs.pa_cl_vte_cntl =
1435 S_028818_VTX_W0_FMT(1) |
1436 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1437 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1438 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1439
1440 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1441 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1442
1443 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1444 }
1445
1446 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1447 {
1448 struct tgsi_shader_info *info = &ps->selector->info;
1449 unsigned num_colors = !!(info->colors_read & 0x0f) +
1450 !!(info->colors_read & 0xf0);
1451 unsigned num_interp = ps->selector->info.num_inputs +
1452 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1453
1454 assert(num_interp <= 32);
1455 return MIN2(num_interp, 32);
1456 }
1457
1458 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1459 {
1460 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1461 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1462
1463 /* If the i-th target format is set, all previous target formats must
1464 * be non-zero to avoid hangs.
1465 */
1466 for (i = 0; i < num_targets; i++)
1467 if (!(value & (0xf << (i * 4))))
1468 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1469
1470 return value;
1471 }
1472
1473 static void si_emit_shader_ps(struct si_context *sctx)
1474 {
1475 struct si_shader *shader = sctx->queued.named.ps->shader;
1476 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1477
1478 if (!shader)
1479 return;
1480
1481 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1482 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1483 SI_TRACKED_SPI_PS_INPUT_ENA,
1484 shader->ctx_reg.ps.spi_ps_input_ena,
1485 shader->ctx_reg.ps.spi_ps_input_addr);
1486
1487 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1488 SI_TRACKED_SPI_BARYC_CNTL,
1489 shader->ctx_reg.ps.spi_baryc_cntl);
1490 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1491 SI_TRACKED_SPI_PS_IN_CONTROL,
1492 shader->ctx_reg.ps.spi_ps_in_control);
1493
1494 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1495 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1496 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1497 shader->ctx_reg.ps.spi_shader_z_format,
1498 shader->ctx_reg.ps.spi_shader_col_format);
1499
1500 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1501 SI_TRACKED_CB_SHADER_MASK,
1502 shader->ctx_reg.ps.cb_shader_mask);
1503
1504 if (initial_cdw != sctx->gfx_cs->current.cdw)
1505 sctx->context_roll = true;
1506 }
1507
1508 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1509 {
1510 struct tgsi_shader_info *info = &shader->selector->info;
1511 struct si_pm4_state *pm4;
1512 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1513 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1514 uint64_t va;
1515 unsigned input_ena = shader->config.spi_ps_input_ena;
1516
1517 /* we need to enable at least one of them, otherwise we hang the GPU */
1518 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1519 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1520 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1521 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1522 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1523 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1524 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1525 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1526 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1527 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1528 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1529 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1530 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1531 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1532
1533 /* Validate interpolation optimization flags (read as implications). */
1534 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1535 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1536 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1537 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1538 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1539 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1540 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1541 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1542 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1543 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1544 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1545 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1546 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1547 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1548 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1549 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1550 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1551 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1552
1553 /* Validate cases when the optimizations are off (read as implications). */
1554 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1555 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1556 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1557 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1558 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1559 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1560
1561 pm4 = si_get_shader_pm4_state(shader);
1562 if (!pm4)
1563 return;
1564
1565 pm4->atom.emit = si_emit_shader_ps;
1566
1567 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1568 * Possible vaules:
1569 * 0 -> Position = pixel center
1570 * 1 -> Position = pixel centroid
1571 * 2 -> Position = at sample position
1572 *
1573 * From GLSL 4.5 specification, section 7.1:
1574 * "The variable gl_FragCoord is available as an input variable from
1575 * within fragment shaders and it holds the window relative coordinates
1576 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1577 * value can be for any location within the pixel, or one of the
1578 * fragment samples. The use of centroid does not further restrict
1579 * this value to be inside the current primitive."
1580 *
1581 * Meaning that centroid has no effect and we can return anything within
1582 * the pixel. Thus, return the value at sample position, because that's
1583 * the most accurate one shaders can get.
1584 */
1585 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1586
1587 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1588 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1589 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1590
1591 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1592 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1593
1594 /* Ensure that some export memory is always allocated, for two reasons:
1595 *
1596 * 1) Correctness: The hardware ignores the EXEC mask if no export
1597 * memory is allocated, so KILL and alpha test do not work correctly
1598 * without this.
1599 * 2) Performance: Every shader needs at least a NULL export, even when
1600 * it writes no color/depth output. The NULL export instruction
1601 * stalls without this setting.
1602 *
1603 * Don't add this to CB_SHADER_MASK.
1604 *
1605 * GFX10 supports pixel shaders without exports by setting both
1606 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1607 * instructions if any are present.
1608 */
1609 if ((sscreen->info.chip_class <= GFX9 ||
1610 info->uses_kill ||
1611 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1612 !spi_shader_col_format &&
1613 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1614 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1615
1616 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1617 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1618
1619 /* Set interpolation controls. */
1620 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader));
1621
1622 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1623 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1624 shader->ctx_reg.ps.spi_shader_z_format =
1625 ac_get_spi_shader_z_format(info->writes_z,
1626 info->writes_stencil,
1627 info->writes_samplemask);
1628 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1629 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1630
1631 va = shader->bo->gpu_address;
1632 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1633 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1634 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1635
1636 uint32_t rsrc1 =
1637 S_00B028_VGPRS((shader->config.num_vgprs - 1) / 4) |
1638 S_00B028_DX10_CLAMP(1) |
1639 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1640 S_00B028_FLOAT_MODE(shader->config.float_mode);
1641
1642 if (sscreen->info.chip_class < GFX10) {
1643 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1644 }
1645
1646 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1647 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1648 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1649 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1650 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1651 }
1652
1653 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1654 struct si_shader *shader)
1655 {
1656 switch (shader->selector->type) {
1657 case PIPE_SHADER_VERTEX:
1658 if (shader->key.as_ls)
1659 si_shader_ls(sscreen, shader);
1660 else if (shader->key.as_es)
1661 si_shader_es(sscreen, shader);
1662 else if (shader->key.as_ngg)
1663 gfx10_shader_ngg(sscreen, shader);
1664 else
1665 si_shader_vs(sscreen, shader, NULL);
1666 break;
1667 case PIPE_SHADER_TESS_CTRL:
1668 si_shader_hs(sscreen, shader);
1669 break;
1670 case PIPE_SHADER_TESS_EVAL:
1671 if (shader->key.as_es)
1672 si_shader_es(sscreen, shader);
1673 else if (shader->key.as_ngg)
1674 gfx10_shader_ngg(sscreen, shader);
1675 else
1676 si_shader_vs(sscreen, shader, NULL);
1677 break;
1678 case PIPE_SHADER_GEOMETRY:
1679 if (shader->key.as_ngg)
1680 gfx10_shader_ngg(sscreen, shader);
1681 else
1682 si_shader_gs(sscreen, shader);
1683 break;
1684 case PIPE_SHADER_FRAGMENT:
1685 si_shader_ps(sscreen, shader);
1686 break;
1687 default:
1688 assert(0);
1689 }
1690 }
1691
1692 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1693 {
1694 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1695 if (sctx->queued.named.dsa)
1696 return sctx->queued.named.dsa->alpha_func;
1697
1698 return PIPE_FUNC_ALWAYS;
1699 }
1700
1701 void si_shader_selector_key_vs(struct si_context *sctx,
1702 struct si_shader_selector *vs,
1703 struct si_shader_key *key,
1704 struct si_vs_prolog_bits *prolog_key)
1705 {
1706 if (!sctx->vertex_elements ||
1707 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1708 return;
1709
1710 struct si_vertex_elements *elts = sctx->vertex_elements;
1711
1712 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1713 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1714 prolog_key->unpack_instance_id_from_vertex_id =
1715 sctx->prim_discard_cs_instancing;
1716
1717 /* Prefer a monolithic shader to allow scheduling divisions around
1718 * VBO loads. */
1719 if (prolog_key->instance_divisor_is_fetched)
1720 key->opt.prefer_mono = 1;
1721
1722 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1723 unsigned count_mask = (1 << count) - 1;
1724 unsigned fix = elts->fix_fetch_always & count_mask;
1725 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1726
1727 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1728 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1729 while (mask) {
1730 unsigned i = u_bit_scan(&mask);
1731 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1732 unsigned vbidx = elts->vertex_buffer_index[i];
1733 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1734 unsigned align_mask = (1 << log_hw_load_size) - 1;
1735 if (vb->buffer_offset & align_mask ||
1736 vb->stride & align_mask) {
1737 fix |= 1 << i;
1738 opencode |= 1 << i;
1739 }
1740 }
1741 }
1742
1743 while (fix) {
1744 unsigned i = u_bit_scan(&fix);
1745 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1746 }
1747 key->mono.vs_fetch_opencode = opencode;
1748 }
1749
1750 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1751 struct si_shader_selector *vs,
1752 struct si_shader_key *key)
1753 {
1754 struct si_shader_selector *ps = sctx->ps_shader.cso;
1755
1756 key->opt.clip_disable =
1757 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1758 (vs->info.clipdist_writemask ||
1759 vs->info.writes_clipvertex) &&
1760 !vs->info.culldist_writemask;
1761
1762 /* Find out if PS is disabled. */
1763 bool ps_disabled = true;
1764 if (ps) {
1765 const struct si_state_blend *blend = sctx->queued.named.blend;
1766 bool alpha_to_coverage = blend && blend->alpha_to_coverage;
1767 bool ps_modifies_zs = ps->info.uses_kill ||
1768 ps->info.writes_z ||
1769 ps->info.writes_stencil ||
1770 ps->info.writes_samplemask ||
1771 alpha_to_coverage ||
1772 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1773 unsigned ps_colormask = si_get_total_colormask(sctx);
1774
1775 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1776 (!ps_colormask &&
1777 !ps_modifies_zs &&
1778 !ps->info.writes_memory);
1779 }
1780
1781 /* Find out which VS outputs aren't used by the PS. */
1782 uint64_t outputs_written = vs->outputs_written_before_ps;
1783 uint64_t inputs_read = 0;
1784
1785 /* Ignore outputs that are not passed from VS to PS. */
1786 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1787 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1788 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1789
1790 if (!ps_disabled) {
1791 inputs_read = ps->inputs_read;
1792 }
1793
1794 uint64_t linked = outputs_written & inputs_read;
1795
1796 key->opt.kill_outputs = ~linked & outputs_written;
1797 }
1798
1799 /* Compute the key for the hw shader variant */
1800 static inline void si_shader_selector_key(struct pipe_context *ctx,
1801 struct si_shader_selector *sel,
1802 union si_vgt_stages_key stages_key,
1803 struct si_shader_key *key)
1804 {
1805 struct si_context *sctx = (struct si_context *)ctx;
1806
1807 memset(key, 0, sizeof(*key));
1808
1809 switch (sel->type) {
1810 case PIPE_SHADER_VERTEX:
1811 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1812
1813 if (sctx->tes_shader.cso)
1814 key->as_ls = 1;
1815 else if (sctx->gs_shader.cso)
1816 key->as_es = 1;
1817 else {
1818 key->as_ngg = stages_key.u.ngg;
1819 si_shader_selector_key_hw_vs(sctx, sel, key);
1820
1821 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1822 key->mono.u.vs_export_prim_id = 1;
1823 }
1824 break;
1825 case PIPE_SHADER_TESS_CTRL:
1826 if (sctx->chip_class >= GFX9) {
1827 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1828 key, &key->part.tcs.ls_prolog);
1829 key->part.tcs.ls = sctx->vs_shader.cso;
1830
1831 /* When the LS VGPR fix is needed, monolithic shaders
1832 * can:
1833 * - avoid initializing EXEC in both the LS prolog
1834 * and the LS main part when !vs_needs_prolog
1835 * - remove the fixup for unused input VGPRs
1836 */
1837 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1838
1839 /* The LS output / HS input layout can be communicated
1840 * directly instead of via user SGPRs for merged LS-HS.
1841 * The LS VGPR fix prefers this too.
1842 */
1843 key->opt.prefer_mono = 1;
1844 }
1845
1846 key->part.tcs.epilog.prim_mode =
1847 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1848 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1849 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1850 key->part.tcs.epilog.tes_reads_tess_factors =
1851 sctx->tes_shader.cso->info.reads_tess_factors;
1852
1853 if (sel == sctx->fixed_func_tcs_shader.cso)
1854 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1855 break;
1856 case PIPE_SHADER_TESS_EVAL:
1857 if (sctx->gs_shader.cso)
1858 key->as_es = 1;
1859 else {
1860 key->as_ngg = stages_key.u.ngg;
1861 si_shader_selector_key_hw_vs(sctx, sel, key);
1862
1863 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1864 key->mono.u.vs_export_prim_id = 1;
1865 }
1866 break;
1867 case PIPE_SHADER_GEOMETRY:
1868 if (sctx->chip_class >= GFX9) {
1869 if (sctx->tes_shader.cso) {
1870 key->part.gs.es = sctx->tes_shader.cso;
1871 } else {
1872 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1873 key, &key->part.gs.vs_prolog);
1874 key->part.gs.es = sctx->vs_shader.cso;
1875 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1876 }
1877
1878 key->as_ngg = stages_key.u.ngg;
1879
1880 /* Merged ES-GS can have unbalanced wave usage.
1881 *
1882 * ES threads are per-vertex, while GS threads are
1883 * per-primitive. So without any amplification, there
1884 * are fewer GS threads than ES threads, which can result
1885 * in empty (no-op) GS waves. With too much amplification,
1886 * there are more GS threads than ES threads, which
1887 * can result in empty (no-op) ES waves.
1888 *
1889 * Non-monolithic shaders are implemented by setting EXEC
1890 * at the beginning of shader parts, and don't jump to
1891 * the end if EXEC is 0.
1892 *
1893 * Monolithic shaders use conditional blocks, so they can
1894 * jump and skip empty waves of ES or GS. So set this to
1895 * always use optimized variants, which are monolithic.
1896 */
1897 key->opt.prefer_mono = 1;
1898 }
1899 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1900 break;
1901 case PIPE_SHADER_FRAGMENT: {
1902 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1903 struct si_state_blend *blend = sctx->queued.named.blend;
1904
1905 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1906 sel->info.colors_written == 0x1)
1907 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1908
1909 if (blend) {
1910 /* Select the shader color format based on whether
1911 * blending or alpha are needed.
1912 */
1913 key->part.ps.epilog.spi_shader_col_format =
1914 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1915 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1916 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1917 sctx->framebuffer.spi_shader_col_format_blend) |
1918 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1919 sctx->framebuffer.spi_shader_col_format_alpha) |
1920 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1921 sctx->framebuffer.spi_shader_col_format);
1922 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1923
1924 /* The output for dual source blending should have
1925 * the same format as the first output.
1926 */
1927 if (blend->dual_src_blend)
1928 key->part.ps.epilog.spi_shader_col_format |=
1929 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1930 } else
1931 key->part.ps.epilog.spi_shader_col_format = sctx->framebuffer.spi_shader_col_format;
1932
1933 /* If alpha-to-coverage is enabled, we have to export alpha
1934 * even if there is no color buffer.
1935 */
1936 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1937 blend && blend->alpha_to_coverage)
1938 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1939
1940 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1941 * to the range supported by the type if a channel has less
1942 * than 16 bits and the export format is 16_ABGR.
1943 */
1944 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1945 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1946 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1947 }
1948
1949 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1950 if (!key->part.ps.epilog.last_cbuf) {
1951 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1952 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1953 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1954 }
1955
1956 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1957 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1958
1959 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1960 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1961
1962 if (sctx->queued.named.blend) {
1963 key->part.ps.epilog.alpha_to_one = sctx->queued.named.blend->alpha_to_one &&
1964 rs->multisample_enable;
1965 }
1966
1967 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1968 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1969 (is_line && rs->line_smooth)) &&
1970 sctx->framebuffer.nr_samples <= 1;
1971 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1972
1973 if (sctx->ps_iter_samples > 1 &&
1974 sel->info.reads_samplemask) {
1975 key->part.ps.prolog.samplemask_log_ps_iter =
1976 util_logbase2(sctx->ps_iter_samples);
1977 }
1978
1979 if (rs->force_persample_interp &&
1980 rs->multisample_enable &&
1981 sctx->framebuffer.nr_samples > 1 &&
1982 sctx->ps_iter_samples > 1) {
1983 key->part.ps.prolog.force_persp_sample_interp =
1984 sel->info.uses_persp_center ||
1985 sel->info.uses_persp_centroid;
1986
1987 key->part.ps.prolog.force_linear_sample_interp =
1988 sel->info.uses_linear_center ||
1989 sel->info.uses_linear_centroid;
1990 } else if (rs->multisample_enable &&
1991 sctx->framebuffer.nr_samples > 1) {
1992 key->part.ps.prolog.bc_optimize_for_persp =
1993 sel->info.uses_persp_center &&
1994 sel->info.uses_persp_centroid;
1995 key->part.ps.prolog.bc_optimize_for_linear =
1996 sel->info.uses_linear_center &&
1997 sel->info.uses_linear_centroid;
1998 } else {
1999 /* Make sure SPI doesn't compute more than 1 pair
2000 * of (i,j), which is the optimization here. */
2001 key->part.ps.prolog.force_persp_center_interp =
2002 sel->info.uses_persp_center +
2003 sel->info.uses_persp_centroid +
2004 sel->info.uses_persp_sample > 1;
2005
2006 key->part.ps.prolog.force_linear_center_interp =
2007 sel->info.uses_linear_center +
2008 sel->info.uses_linear_centroid +
2009 sel->info.uses_linear_sample > 1;
2010
2011 if (sel->info.opcode_count[TGSI_OPCODE_INTERP_SAMPLE])
2012 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2013 }
2014
2015 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2016
2017 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2018 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2019 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2020 struct pipe_resource *tex = cb0->texture;
2021
2022 /* 1D textures are allocated and used as 2D on GFX9. */
2023 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2024 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2025 (tex->target == PIPE_TEXTURE_1D ||
2026 tex->target == PIPE_TEXTURE_1D_ARRAY);
2027 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2028 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2029 tex->target == PIPE_TEXTURE_CUBE ||
2030 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2031 tex->target == PIPE_TEXTURE_3D;
2032 }
2033 break;
2034 }
2035 default:
2036 assert(0);
2037 }
2038
2039 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2040 memset(&key->opt, 0, sizeof(key->opt));
2041 }
2042
2043 static void si_build_shader_variant(struct si_shader *shader,
2044 int thread_index,
2045 bool low_priority)
2046 {
2047 struct si_shader_selector *sel = shader->selector;
2048 struct si_screen *sscreen = sel->screen;
2049 struct ac_llvm_compiler *compiler;
2050 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2051
2052 if (thread_index >= 0) {
2053 if (low_priority) {
2054 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2055 compiler = &sscreen->compiler_lowp[thread_index];
2056 } else {
2057 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2058 compiler = &sscreen->compiler[thread_index];
2059 }
2060 if (!debug->async)
2061 debug = NULL;
2062 } else {
2063 assert(!low_priority);
2064 compiler = shader->compiler_ctx_state.compiler;
2065 }
2066
2067 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2068 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2069 sel->type);
2070 shader->compilation_failed = true;
2071 return;
2072 }
2073
2074 if (shader->compiler_ctx_state.is_debug_context) {
2075 FILE *f = open_memstream(&shader->shader_log,
2076 &shader->shader_log_size);
2077 if (f) {
2078 si_shader_dump(sscreen, shader, NULL, f, false);
2079 fclose(f);
2080 }
2081 }
2082
2083 si_shader_init_pm4_state(sscreen, shader);
2084 }
2085
2086 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2087 {
2088 struct si_shader *shader = (struct si_shader *)job;
2089
2090 assert(thread_index >= 0);
2091
2092 si_build_shader_variant(shader, thread_index, true);
2093 }
2094
2095 static const struct si_shader_key zeroed;
2096
2097 static bool si_check_missing_main_part(struct si_screen *sscreen,
2098 struct si_shader_selector *sel,
2099 struct si_compiler_ctx_state *compiler_state,
2100 struct si_shader_key *key)
2101 {
2102 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2103
2104 if (!*mainp) {
2105 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2106
2107 if (!main_part)
2108 return false;
2109
2110 /* We can leave the fence as permanently signaled because the
2111 * main part becomes visible globally only after it has been
2112 * compiled. */
2113 util_queue_fence_init(&main_part->ready);
2114
2115 main_part->selector = sel;
2116 main_part->key.as_es = key->as_es;
2117 main_part->key.as_ls = key->as_ls;
2118 main_part->key.as_ngg = key->as_ngg;
2119 main_part->is_monolithic = false;
2120
2121 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2122 main_part, &compiler_state->debug) != 0) {
2123 FREE(main_part);
2124 return false;
2125 }
2126 *mainp = main_part;
2127 }
2128 return true;
2129 }
2130
2131 /**
2132 * Select a shader variant according to the shader key.
2133 *
2134 * \param optimized_or_none If the key describes an optimized shader variant and
2135 * the compilation isn't finished, don't select any
2136 * shader and return an error.
2137 */
2138 int si_shader_select_with_key(struct si_screen *sscreen,
2139 struct si_shader_ctx_state *state,
2140 struct si_compiler_ctx_state *compiler_state,
2141 struct si_shader_key *key,
2142 int thread_index,
2143 bool optimized_or_none)
2144 {
2145 struct si_shader_selector *sel = state->cso;
2146 struct si_shader_selector *previous_stage_sel = NULL;
2147 struct si_shader *current = state->current;
2148 struct si_shader *iter, *shader = NULL;
2149
2150 again:
2151 /* Check if we don't need to change anything.
2152 * This path is also used for most shaders that don't need multiple
2153 * variants, it will cost just a computation of the key and this
2154 * test. */
2155 if (likely(current &&
2156 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2157 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2158 if (current->is_optimized) {
2159 if (optimized_or_none)
2160 return -1;
2161
2162 memset(&key->opt, 0, sizeof(key->opt));
2163 goto current_not_ready;
2164 }
2165
2166 util_queue_fence_wait(&current->ready);
2167 }
2168
2169 return current->compilation_failed ? -1 : 0;
2170 }
2171 current_not_ready:
2172
2173 /* This must be done before the mutex is locked, because async GS
2174 * compilation calls this function too, and therefore must enter
2175 * the mutex first.
2176 *
2177 * Only wait if we are in a draw call. Don't wait if we are
2178 * in a compiler thread.
2179 */
2180 if (thread_index < 0)
2181 util_queue_fence_wait(&sel->ready);
2182
2183 mtx_lock(&sel->mutex);
2184
2185 /* Find the shader variant. */
2186 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2187 /* Don't check the "current" shader. We checked it above. */
2188 if (current != iter &&
2189 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2190 mtx_unlock(&sel->mutex);
2191
2192 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2193 /* If it's an optimized shader and its compilation has
2194 * been started but isn't done, use the unoptimized
2195 * shader so as not to cause a stall due to compilation.
2196 */
2197 if (iter->is_optimized) {
2198 if (optimized_or_none)
2199 return -1;
2200 memset(&key->opt, 0, sizeof(key->opt));
2201 goto again;
2202 }
2203
2204 util_queue_fence_wait(&iter->ready);
2205 }
2206
2207 if (iter->compilation_failed) {
2208 return -1; /* skip the draw call */
2209 }
2210
2211 state->current = iter;
2212 return 0;
2213 }
2214 }
2215
2216 /* Build a new shader. */
2217 shader = CALLOC_STRUCT(si_shader);
2218 if (!shader) {
2219 mtx_unlock(&sel->mutex);
2220 return -ENOMEM;
2221 }
2222
2223 util_queue_fence_init(&shader->ready);
2224
2225 shader->selector = sel;
2226 shader->key = *key;
2227 shader->compiler_ctx_state = *compiler_state;
2228
2229 /* If this is a merged shader, get the first shader's selector. */
2230 if (sscreen->info.chip_class >= GFX9) {
2231 if (sel->type == PIPE_SHADER_TESS_CTRL)
2232 previous_stage_sel = key->part.tcs.ls;
2233 else if (sel->type == PIPE_SHADER_GEOMETRY)
2234 previous_stage_sel = key->part.gs.es;
2235
2236 /* We need to wait for the previous shader. */
2237 if (previous_stage_sel && thread_index < 0)
2238 util_queue_fence_wait(&previous_stage_sel->ready);
2239 }
2240
2241 bool is_pure_monolithic =
2242 sscreen->use_monolithic_shaders ||
2243 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2244
2245 /* Compile the main shader part if it doesn't exist. This can happen
2246 * if the initial guess was wrong.
2247 *
2248 * The prim discard CS doesn't need the main shader part.
2249 */
2250 if (!is_pure_monolithic &&
2251 !key->opt.vs_as_prim_discard_cs) {
2252 bool ok = true;
2253
2254 /* Make sure the main shader part is present. This is needed
2255 * for shaders that can be compiled as VS, LS, or ES, and only
2256 * one of them is compiled at creation.
2257 *
2258 * It is also needed for GS, which can be compiled as non-NGG
2259 * and NGG.
2260 *
2261 * For merged shaders, check that the starting shader's main
2262 * part is present.
2263 */
2264 if (previous_stage_sel) {
2265 struct si_shader_key shader1_key = zeroed;
2266
2267 if (sel->type == PIPE_SHADER_TESS_CTRL)
2268 shader1_key.as_ls = 1;
2269 else if (sel->type == PIPE_SHADER_GEOMETRY)
2270 shader1_key.as_es = 1;
2271 else
2272 assert(0);
2273
2274 mtx_lock(&previous_stage_sel->mutex);
2275 ok = si_check_missing_main_part(sscreen,
2276 previous_stage_sel,
2277 compiler_state, &shader1_key);
2278 mtx_unlock(&previous_stage_sel->mutex);
2279 }
2280
2281 if (ok) {
2282 ok = si_check_missing_main_part(sscreen, sel,
2283 compiler_state, key);
2284 }
2285
2286 if (!ok) {
2287 FREE(shader);
2288 mtx_unlock(&sel->mutex);
2289 return -ENOMEM; /* skip the draw call */
2290 }
2291 }
2292
2293 /* Keep the reference to the 1st shader of merged shaders, so that
2294 * Gallium can't destroy it before we destroy the 2nd shader.
2295 *
2296 * Set sctx = NULL, because it's unused if we're not releasing
2297 * the shader, and we don't have any sctx here.
2298 */
2299 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2300 previous_stage_sel);
2301
2302 /* Monolithic-only shaders don't make a distinction between optimized
2303 * and unoptimized. */
2304 shader->is_monolithic =
2305 is_pure_monolithic ||
2306 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2307
2308 /* The prim discard CS is always optimized. */
2309 shader->is_optimized =
2310 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2311 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2312
2313 /* If it's an optimized shader, compile it asynchronously. */
2314 if (shader->is_optimized && thread_index < 0) {
2315 /* Compile it asynchronously. */
2316 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2317 shader, &shader->ready,
2318 si_build_shader_variant_low_priority, NULL);
2319
2320 /* Add only after the ready fence was reset, to guard against a
2321 * race with si_bind_XX_shader. */
2322 if (!sel->last_variant) {
2323 sel->first_variant = shader;
2324 sel->last_variant = shader;
2325 } else {
2326 sel->last_variant->next_variant = shader;
2327 sel->last_variant = shader;
2328 }
2329
2330 /* Use the default (unoptimized) shader for now. */
2331 memset(&key->opt, 0, sizeof(key->opt));
2332 mtx_unlock(&sel->mutex);
2333
2334 if (sscreen->options.sync_compile)
2335 util_queue_fence_wait(&shader->ready);
2336
2337 if (optimized_or_none)
2338 return -1;
2339 goto again;
2340 }
2341
2342 /* Reset the fence before adding to the variant list. */
2343 util_queue_fence_reset(&shader->ready);
2344
2345 if (!sel->last_variant) {
2346 sel->first_variant = shader;
2347 sel->last_variant = shader;
2348 } else {
2349 sel->last_variant->next_variant = shader;
2350 sel->last_variant = shader;
2351 }
2352
2353 mtx_unlock(&sel->mutex);
2354
2355 assert(!shader->is_optimized);
2356 si_build_shader_variant(shader, thread_index, false);
2357
2358 util_queue_fence_signal(&shader->ready);
2359
2360 if (!shader->compilation_failed)
2361 state->current = shader;
2362
2363 return shader->compilation_failed ? -1 : 0;
2364 }
2365
2366 static int si_shader_select(struct pipe_context *ctx,
2367 struct si_shader_ctx_state *state,
2368 union si_vgt_stages_key stages_key,
2369 struct si_compiler_ctx_state *compiler_state)
2370 {
2371 struct si_context *sctx = (struct si_context *)ctx;
2372 struct si_shader_key key;
2373
2374 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2375 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2376 &key, -1, false);
2377 }
2378
2379 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2380 bool streamout,
2381 struct si_shader_key *key)
2382 {
2383 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2384
2385 switch (info->processor) {
2386 case PIPE_SHADER_VERTEX:
2387 switch (next_shader) {
2388 case PIPE_SHADER_GEOMETRY:
2389 key->as_es = 1;
2390 break;
2391 case PIPE_SHADER_TESS_CTRL:
2392 case PIPE_SHADER_TESS_EVAL:
2393 key->as_ls = 1;
2394 break;
2395 default:
2396 /* If POSITION isn't written, it can only be a HW VS
2397 * if streamout is used. If streamout isn't used,
2398 * assume that it's a HW LS. (the next shader is TCS)
2399 * This heuristic is needed for separate shader objects.
2400 */
2401 if (!info->writes_position && !streamout)
2402 key->as_ls = 1;
2403 }
2404 break;
2405
2406 case PIPE_SHADER_TESS_EVAL:
2407 if (next_shader == PIPE_SHADER_GEOMETRY ||
2408 !info->writes_position)
2409 key->as_es = 1;
2410 break;
2411 }
2412 }
2413
2414 /**
2415 * Compile the main shader part or the monolithic shader as part of
2416 * si_shader_selector initialization. Since it can be done asynchronously,
2417 * there is no way to report compile failures to applications.
2418 */
2419 static void si_init_shader_selector_async(void *job, int thread_index)
2420 {
2421 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2422 struct si_screen *sscreen = sel->screen;
2423 struct ac_llvm_compiler *compiler;
2424 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2425
2426 assert(!debug->debug_message || debug->async);
2427 assert(thread_index >= 0);
2428 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2429 compiler = &sscreen->compiler[thread_index];
2430
2431 if (sel->nir)
2432 si_lower_nir(sel);
2433
2434 /* Compile the main shader part for use with a prolog and/or epilog.
2435 * If this fails, the driver will try to compile a monolithic shader
2436 * on demand.
2437 */
2438 if (!sscreen->use_monolithic_shaders) {
2439 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2440 void *ir_binary = NULL;
2441
2442 if (!shader) {
2443 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2444 return;
2445 }
2446
2447 /* We can leave the fence signaled because use of the default
2448 * main part is guarded by the selector's ready fence. */
2449 util_queue_fence_init(&shader->ready);
2450
2451 shader->selector = sel;
2452 shader->is_monolithic = false;
2453 si_parse_next_shader_property(&sel->info,
2454 sel->so.num_outputs != 0,
2455 &shader->key);
2456 if (sscreen->info.chip_class >= GFX10 &&
2457 !sscreen->options.disable_ngg &&
2458 (((sel->type == PIPE_SHADER_VERTEX ||
2459 sel->type == PIPE_SHADER_TESS_EVAL) &&
2460 !shader->key.as_ls && !shader->key.as_es) ||
2461 sel->type == PIPE_SHADER_GEOMETRY))
2462 shader->key.as_ngg = 1;
2463
2464 if (sel->tokens || sel->nir)
2465 ir_binary = si_get_ir_binary(sel);
2466
2467 /* Try to load the shader from the shader cache. */
2468 mtx_lock(&sscreen->shader_cache_mutex);
2469
2470 if (ir_binary &&
2471 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2472 mtx_unlock(&sscreen->shader_cache_mutex);
2473 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2474 } else {
2475 mtx_unlock(&sscreen->shader_cache_mutex);
2476
2477 /* Compile the shader if it hasn't been loaded from the cache. */
2478 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2479 debug) != 0) {
2480 FREE(shader);
2481 FREE(ir_binary);
2482 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2483 return;
2484 }
2485
2486 if (ir_binary) {
2487 mtx_lock(&sscreen->shader_cache_mutex);
2488 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2489 FREE(ir_binary);
2490 mtx_unlock(&sscreen->shader_cache_mutex);
2491 }
2492 }
2493
2494 *si_get_main_shader_part(sel, &shader->key) = shader;
2495
2496 /* Unset "outputs_written" flags for outputs converted to
2497 * DEFAULT_VAL, so that later inter-shader optimizations don't
2498 * try to eliminate outputs that don't exist in the final
2499 * shader.
2500 *
2501 * This is only done if non-monolithic shaders are enabled.
2502 */
2503 if ((sel->type == PIPE_SHADER_VERTEX ||
2504 sel->type == PIPE_SHADER_TESS_EVAL) &&
2505 !shader->key.as_ls &&
2506 !shader->key.as_es) {
2507 unsigned i;
2508
2509 for (i = 0; i < sel->info.num_outputs; i++) {
2510 unsigned offset = shader->info.vs_output_param_offset[i];
2511
2512 if (offset <= AC_EXP_PARAM_OFFSET_31)
2513 continue;
2514
2515 unsigned name = sel->info.output_semantic_name[i];
2516 unsigned index = sel->info.output_semantic_index[i];
2517 unsigned id;
2518
2519 switch (name) {
2520 case TGSI_SEMANTIC_GENERIC:
2521 /* don't process indices the function can't handle */
2522 if (index >= SI_MAX_IO_GENERIC)
2523 break;
2524 /* fall through */
2525 default:
2526 id = si_shader_io_get_unique_index(name, index, true);
2527 sel->outputs_written_before_ps &= ~(1ull << id);
2528 break;
2529 case TGSI_SEMANTIC_POSITION: /* ignore these */
2530 case TGSI_SEMANTIC_PSIZE:
2531 case TGSI_SEMANTIC_CLIPVERTEX:
2532 case TGSI_SEMANTIC_EDGEFLAG:
2533 break;
2534 }
2535 }
2536 }
2537 }
2538
2539 /* The GS copy shader is always pre-compiled.
2540 *
2541 * TODO-GFX10: We could compile the GS copy shader on demand, since it
2542 * is only used in the (rare) non-NGG case.
2543 */
2544 if (sel->type == PIPE_SHADER_GEOMETRY) {
2545 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2546 if (!sel->gs_copy_shader) {
2547 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2548 return;
2549 }
2550
2551 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2552 }
2553 }
2554
2555 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2556 struct util_queue_fence *ready_fence,
2557 struct si_compiler_ctx_state *compiler_ctx_state,
2558 void *job, util_queue_execute_func execute)
2559 {
2560 util_queue_fence_init(ready_fence);
2561
2562 struct util_async_debug_callback async_debug;
2563 bool debug =
2564 (sctx->debug.debug_message && !sctx->debug.async) ||
2565 sctx->is_debug ||
2566 si_can_dump_shader(sctx->screen, processor);
2567
2568 if (debug) {
2569 u_async_debug_init(&async_debug);
2570 compiler_ctx_state->debug = async_debug.base;
2571 }
2572
2573 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2574 ready_fence, execute, NULL);
2575
2576 if (debug) {
2577 util_queue_fence_wait(ready_fence);
2578 u_async_debug_drain(&async_debug, &sctx->debug);
2579 u_async_debug_cleanup(&async_debug);
2580 }
2581
2582 if (sctx->screen->options.sync_compile)
2583 util_queue_fence_wait(ready_fence);
2584 }
2585
2586 /* Return descriptor slot usage masks from the given shader info. */
2587 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2588 uint32_t *const_and_shader_buffers,
2589 uint64_t *samplers_and_images)
2590 {
2591 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2592
2593 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2594 num_constbufs = util_last_bit(info->const_buffers_declared);
2595 /* two 8-byte images share one 16-byte slot */
2596 num_images = align(util_last_bit(info->images_declared), 2);
2597 num_samplers = util_last_bit(info->samplers_declared);
2598
2599 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2600 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2601 *const_and_shader_buffers =
2602 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2603
2604 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2605 start = si_get_image_slot(num_images - 1) / 2;
2606 *samplers_and_images =
2607 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2608 }
2609
2610 static void *si_create_shader_selector(struct pipe_context *ctx,
2611 const struct pipe_shader_state *state)
2612 {
2613 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2614 struct si_context *sctx = (struct si_context*)ctx;
2615 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2616 int i;
2617
2618 if (!sel)
2619 return NULL;
2620
2621 pipe_reference_init(&sel->reference, 1);
2622 sel->screen = sscreen;
2623 sel->compiler_ctx_state.debug = sctx->debug;
2624 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2625
2626 sel->so = state->stream_output;
2627
2628 if (state->type == PIPE_SHADER_IR_TGSI) {
2629 sel->tokens = tgsi_dup_tokens(state->tokens);
2630 if (!sel->tokens) {
2631 FREE(sel);
2632 return NULL;
2633 }
2634
2635 tgsi_scan_shader(state->tokens, &sel->info);
2636 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2637 } else {
2638 assert(state->type == PIPE_SHADER_IR_NIR);
2639
2640 sel->nir = state->ir.nir;
2641
2642 si_nir_opts(sel->nir);
2643 si_nir_scan_shader(sel->nir, &sel->info);
2644 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2645 }
2646
2647 sel->type = sel->info.processor;
2648 p_atomic_inc(&sscreen->num_shaders_created);
2649 si_get_active_slot_masks(&sel->info,
2650 &sel->active_const_and_shader_buffers,
2651 &sel->active_samplers_and_images);
2652
2653 /* Record which streamout buffers are enabled. */
2654 for (i = 0; i < sel->so.num_outputs; i++) {
2655 sel->enabled_streamout_buffer_mask |=
2656 (1 << sel->so.output[i].output_buffer) <<
2657 (sel->so.output[i].stream * 4);
2658 }
2659
2660 /* The prolog is a no-op if there are no inputs. */
2661 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2662 sel->info.num_inputs &&
2663 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2664
2665 sel->force_correct_derivs_after_kill =
2666 sel->type == PIPE_SHADER_FRAGMENT &&
2667 sel->info.uses_derivatives &&
2668 sel->info.uses_kill &&
2669 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2670
2671 sel->prim_discard_cs_allowed =
2672 sel->type == PIPE_SHADER_VERTEX &&
2673 !sel->info.uses_bindless_images &&
2674 !sel->info.uses_bindless_samplers &&
2675 !sel->info.writes_memory &&
2676 !sel->info.writes_viewport_index &&
2677 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2678 !sel->so.num_outputs;
2679
2680 /* Set which opcode uses which (i,j) pair. */
2681 if (sel->info.uses_persp_opcode_interp_centroid)
2682 sel->info.uses_persp_centroid = true;
2683
2684 if (sel->info.uses_linear_opcode_interp_centroid)
2685 sel->info.uses_linear_centroid = true;
2686
2687 if (sel->info.uses_persp_opcode_interp_offset ||
2688 sel->info.uses_persp_opcode_interp_sample)
2689 sel->info.uses_persp_center = true;
2690
2691 if (sel->info.uses_linear_opcode_interp_offset ||
2692 sel->info.uses_linear_opcode_interp_sample)
2693 sel->info.uses_linear_center = true;
2694
2695 switch (sel->type) {
2696 case PIPE_SHADER_GEOMETRY:
2697 sel->gs_output_prim =
2698 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2699
2700 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2701 sel->rast_prim = sel->gs_output_prim;
2702 if (util_rast_prim_is_triangles(sel->rast_prim))
2703 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2704
2705 sel->gs_max_out_vertices =
2706 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2707 sel->gs_num_invocations =
2708 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2709 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2710 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2711 sel->gs_max_out_vertices;
2712
2713 sel->max_gs_stream = 0;
2714 for (i = 0; i < sel->so.num_outputs; i++)
2715 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2716 sel->so.output[i].stream);
2717
2718 sel->gs_input_verts_per_prim =
2719 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2720 break;
2721
2722 case PIPE_SHADER_TESS_CTRL:
2723 /* Always reserve space for these. */
2724 sel->patch_outputs_written |=
2725 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2726 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2727 /* fall through */
2728 case PIPE_SHADER_VERTEX:
2729 case PIPE_SHADER_TESS_EVAL:
2730 for (i = 0; i < sel->info.num_outputs; i++) {
2731 unsigned name = sel->info.output_semantic_name[i];
2732 unsigned index = sel->info.output_semantic_index[i];
2733
2734 switch (name) {
2735 case TGSI_SEMANTIC_TESSINNER:
2736 case TGSI_SEMANTIC_TESSOUTER:
2737 case TGSI_SEMANTIC_PATCH:
2738 sel->patch_outputs_written |=
2739 1ull << si_shader_io_get_unique_index_patch(name, index);
2740 break;
2741
2742 case TGSI_SEMANTIC_GENERIC:
2743 /* don't process indices the function can't handle */
2744 if (index >= SI_MAX_IO_GENERIC)
2745 break;
2746 /* fall through */
2747 default:
2748 sel->outputs_written |=
2749 1ull << si_shader_io_get_unique_index(name, index, false);
2750 sel->outputs_written_before_ps |=
2751 1ull << si_shader_io_get_unique_index(name, index, true);
2752 break;
2753 case TGSI_SEMANTIC_EDGEFLAG:
2754 break;
2755 }
2756 }
2757 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2758 sel->lshs_vertex_stride = sel->esgs_itemsize;
2759
2760 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2761 * will start on a different bank. (except for the maximum 32*16).
2762 */
2763 if (sel->lshs_vertex_stride < 32*16)
2764 sel->lshs_vertex_stride += 4;
2765
2766 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2767 * conflicts, i.e. each vertex will start at a different bank.
2768 */
2769 if (sctx->chip_class >= GFX9)
2770 sel->esgs_itemsize += 4;
2771
2772 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2773
2774 /* Only for TES: */
2775 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2776 sel->rast_prim = PIPE_PRIM_POINTS;
2777 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2778 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2779 else
2780 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2781 break;
2782
2783 case PIPE_SHADER_FRAGMENT:
2784 for (i = 0; i < sel->info.num_inputs; i++) {
2785 unsigned name = sel->info.input_semantic_name[i];
2786 unsigned index = sel->info.input_semantic_index[i];
2787
2788 switch (name) {
2789 case TGSI_SEMANTIC_GENERIC:
2790 /* don't process indices the function can't handle */
2791 if (index >= SI_MAX_IO_GENERIC)
2792 break;
2793 /* fall through */
2794 default:
2795 sel->inputs_read |=
2796 1ull << si_shader_io_get_unique_index(name, index, true);
2797 break;
2798 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2799 break;
2800 }
2801 }
2802
2803 for (i = 0; i < 8; i++)
2804 if (sel->info.colors_written & (1 << i))
2805 sel->colors_written_4bit |= 0xf << (4 * i);
2806
2807 for (i = 0; i < sel->info.num_inputs; i++) {
2808 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2809 int index = sel->info.input_semantic_index[i];
2810 sel->color_attr_index[index] = i;
2811 }
2812 }
2813 break;
2814 default:;
2815 }
2816
2817 /* PA_CL_VS_OUT_CNTL */
2818 bool misc_vec_ena =
2819 sel->info.writes_psize || sel->info.writes_edgeflag ||
2820 sel->info.writes_layer || sel->info.writes_viewport_index;
2821 sel->pa_cl_vs_out_cntl =
2822 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2823 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag) |
2824 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2825 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2826 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2827 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2828 sel->clipdist_mask = sel->info.writes_clipvertex ?
2829 SIX_BITS : sel->info.clipdist_writemask;
2830 sel->culldist_mask = sel->info.culldist_writemask <<
2831 sel->info.num_written_clipdistance;
2832
2833 /* DB_SHADER_CONTROL */
2834 sel->db_shader_control =
2835 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2836 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2837 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2838 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2839
2840 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2841 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2842 sel->db_shader_control |=
2843 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2844 break;
2845 case TGSI_FS_DEPTH_LAYOUT_LESS:
2846 sel->db_shader_control |=
2847 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2848 break;
2849 }
2850
2851 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2852 *
2853 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2854 * --|-----------|------------|------------|--------------------|-------------------|-------------
2855 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2856 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2857 * 2 | false | true | n/a | LateZ | 1 | 0
2858 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2859 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2860 *
2861 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2862 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2863 *
2864 * Don't use ReZ without profiling !!!
2865 *
2866 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2867 * shaders.
2868 */
2869 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2870 /* Cases 3, 4. */
2871 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2872 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2873 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2874 } else if (sel->info.writes_memory) {
2875 /* Case 2. */
2876 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2877 S_02880C_EXEC_ON_HIER_FAIL(1);
2878 } else {
2879 /* Case 1. */
2880 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2881 }
2882
2883 (void) mtx_init(&sel->mutex, mtx_plain);
2884
2885 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2886 &sel->compiler_ctx_state, sel,
2887 si_init_shader_selector_async);
2888 return sel;
2889 }
2890
2891 static void si_update_streamout_state(struct si_context *sctx)
2892 {
2893 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2894
2895 if (!shader_with_so)
2896 return;
2897
2898 sctx->streamout.enabled_stream_buffers_mask =
2899 shader_with_so->enabled_streamout_buffer_mask;
2900 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2901 }
2902
2903 static void si_update_clip_regs(struct si_context *sctx,
2904 struct si_shader_selector *old_hw_vs,
2905 struct si_shader *old_hw_vs_variant,
2906 struct si_shader_selector *next_hw_vs,
2907 struct si_shader *next_hw_vs_variant)
2908 {
2909 if (next_hw_vs &&
2910 (!old_hw_vs ||
2911 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2912 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2913 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2914 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2915 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2916 !old_hw_vs_variant ||
2917 !next_hw_vs_variant ||
2918 old_hw_vs_variant->key.opt.clip_disable !=
2919 next_hw_vs_variant->key.opt.clip_disable))
2920 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2921 }
2922
2923 static void si_update_common_shader_state(struct si_context *sctx)
2924 {
2925 sctx->uses_bindless_samplers =
2926 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2927 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2928 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2929 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2930 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2931 sctx->uses_bindless_images =
2932 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2933 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2934 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2935 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2936 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2937 sctx->do_update_shaders = true;
2938 }
2939
2940 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2941 {
2942 struct si_context *sctx = (struct si_context *)ctx;
2943 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2944 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2945 struct si_shader_selector *sel = state;
2946
2947 if (sctx->vs_shader.cso == sel)
2948 return;
2949
2950 sctx->vs_shader.cso = sel;
2951 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2952 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2953
2954 si_update_common_shader_state(sctx);
2955 si_update_vs_viewport_state(sctx);
2956 si_set_active_descriptors_for_shader(sctx, sel);
2957 si_update_streamout_state(sctx);
2958 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2959 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2960 }
2961
2962 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2963 {
2964 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2965 (sctx->tes_shader.cso &&
2966 sctx->tes_shader.cso->info.uses_primid) ||
2967 (sctx->tcs_shader.cso &&
2968 sctx->tcs_shader.cso->info.uses_primid) ||
2969 (sctx->gs_shader.cso &&
2970 sctx->gs_shader.cso->info.uses_primid) ||
2971 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2972 sctx->ps_shader.cso->info.uses_primid);
2973 }
2974
2975 static bool si_update_ngg(struct si_context *sctx)
2976 {
2977 if (sctx->chip_class <= GFX9 ||
2978 sctx->screen->options.disable_ngg)
2979 return false;
2980
2981 bool new_ngg = true;
2982
2983 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2984 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
2985 sctx->gs_shader.cso->gs_num_invocations * sctx->gs_shader.cso->gs_max_out_vertices > 256)
2986 new_ngg = false;
2987
2988 if (new_ngg != sctx->ngg) {
2989 sctx->ngg = new_ngg;
2990 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
2991 return true;
2992 }
2993 return false;
2994 }
2995
2996 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2997 {
2998 struct si_context *sctx = (struct si_context *)ctx;
2999 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3000 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3001 struct si_shader_selector *sel = state;
3002 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3003 bool ngg_changed;
3004
3005 if (sctx->gs_shader.cso == sel)
3006 return;
3007
3008 sctx->gs_shader.cso = sel;
3009 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3010 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3011
3012 si_update_common_shader_state(sctx);
3013 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3014
3015 ngg_changed = si_update_ngg(sctx);
3016 if (ngg_changed || enable_changed)
3017 si_shader_change_notify(sctx);
3018 if (enable_changed) {
3019 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3020 si_update_tess_uses_prim_id(sctx);
3021 }
3022 si_update_vs_viewport_state(sctx);
3023 si_set_active_descriptors_for_shader(sctx, sel);
3024 si_update_streamout_state(sctx);
3025 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3026 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3027 }
3028
3029 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3030 {
3031 struct si_context *sctx = (struct si_context *)ctx;
3032 struct si_shader_selector *sel = state;
3033 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3034
3035 if (sctx->tcs_shader.cso == sel)
3036 return;
3037
3038 sctx->tcs_shader.cso = sel;
3039 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3040 si_update_tess_uses_prim_id(sctx);
3041
3042 si_update_common_shader_state(sctx);
3043
3044 if (enable_changed)
3045 sctx->last_tcs = NULL; /* invalidate derived tess state */
3046
3047 si_set_active_descriptors_for_shader(sctx, sel);
3048 }
3049
3050 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3051 {
3052 struct si_context *sctx = (struct si_context *)ctx;
3053 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3054 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3055 struct si_shader_selector *sel = state;
3056 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3057
3058 if (sctx->tes_shader.cso == sel)
3059 return;
3060
3061 sctx->tes_shader.cso = sel;
3062 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3063 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3064 si_update_tess_uses_prim_id(sctx);
3065
3066 si_update_common_shader_state(sctx);
3067 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3068
3069 if (enable_changed) {
3070 si_update_ngg(sctx);
3071 si_shader_change_notify(sctx);
3072 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3073 }
3074 si_update_vs_viewport_state(sctx);
3075 si_set_active_descriptors_for_shader(sctx, sel);
3076 si_update_streamout_state(sctx);
3077 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3078 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3079 }
3080
3081 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3082 {
3083 struct si_context *sctx = (struct si_context *)ctx;
3084 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3085 struct si_shader_selector *sel = state;
3086
3087 /* skip if supplied shader is one already in use */
3088 if (old_sel == sel)
3089 return;
3090
3091 sctx->ps_shader.cso = sel;
3092 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3093
3094 si_update_common_shader_state(sctx);
3095 if (sel) {
3096 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3097 si_update_tess_uses_prim_id(sctx);
3098
3099 if (!old_sel ||
3100 old_sel->info.colors_written != sel->info.colors_written)
3101 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3102
3103 if (sctx->screen->has_out_of_order_rast &&
3104 (!old_sel ||
3105 old_sel->info.writes_memory != sel->info.writes_memory ||
3106 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3107 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3108 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3109 }
3110 si_set_active_descriptors_for_shader(sctx, sel);
3111 si_update_ps_colorbuf0_slot(sctx);
3112 }
3113
3114 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3115 {
3116 if (shader->is_optimized) {
3117 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3118 &shader->ready);
3119 }
3120
3121 util_queue_fence_destroy(&shader->ready);
3122
3123 if (shader->pm4) {
3124 /* If destroyed shaders were not unbound, the next compiled
3125 * shader variant could get the same pointer address and so
3126 * binding it to the same shader stage would be considered
3127 * a no-op, causing random behavior.
3128 */
3129 switch (shader->selector->type) {
3130 case PIPE_SHADER_VERTEX:
3131 if (shader->key.as_ls) {
3132 assert(sctx->chip_class <= GFX8);
3133 si_pm4_delete_state(sctx, ls, shader->pm4);
3134 } else if (shader->key.as_es) {
3135 assert(sctx->chip_class <= GFX8);
3136 si_pm4_delete_state(sctx, es, shader->pm4);
3137 } else if (shader->key.as_ngg) {
3138 si_pm4_delete_state(sctx, gs, shader->pm4);
3139 } else {
3140 si_pm4_delete_state(sctx, vs, shader->pm4);
3141 }
3142 break;
3143 case PIPE_SHADER_TESS_CTRL:
3144 si_pm4_delete_state(sctx, hs, shader->pm4);
3145 break;
3146 case PIPE_SHADER_TESS_EVAL:
3147 if (shader->key.as_es) {
3148 assert(sctx->chip_class <= GFX8);
3149 si_pm4_delete_state(sctx, es, shader->pm4);
3150 } else if (shader->key.as_ngg) {
3151 si_pm4_delete_state(sctx, gs, shader->pm4);
3152 } else {
3153 si_pm4_delete_state(sctx, vs, shader->pm4);
3154 }
3155 break;
3156 case PIPE_SHADER_GEOMETRY:
3157 if (shader->is_gs_copy_shader)
3158 si_pm4_delete_state(sctx, vs, shader->pm4);
3159 else
3160 si_pm4_delete_state(sctx, gs, shader->pm4);
3161 break;
3162 case PIPE_SHADER_FRAGMENT:
3163 si_pm4_delete_state(sctx, ps, shader->pm4);
3164 break;
3165 default:;
3166 }
3167 }
3168
3169 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3170 si_shader_destroy(shader);
3171 free(shader);
3172 }
3173
3174 void si_destroy_shader_selector(struct si_context *sctx,
3175 struct si_shader_selector *sel)
3176 {
3177 struct si_shader *p = sel->first_variant, *c;
3178 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3179 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3180 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3181 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3182 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3183 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3184 };
3185
3186 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3187
3188 if (current_shader[sel->type]->cso == sel) {
3189 current_shader[sel->type]->cso = NULL;
3190 current_shader[sel->type]->current = NULL;
3191 }
3192
3193 while (p) {
3194 c = p->next_variant;
3195 si_delete_shader(sctx, p);
3196 p = c;
3197 }
3198
3199 if (sel->main_shader_part)
3200 si_delete_shader(sctx, sel->main_shader_part);
3201 if (sel->main_shader_part_ls)
3202 si_delete_shader(sctx, sel->main_shader_part_ls);
3203 if (sel->main_shader_part_es)
3204 si_delete_shader(sctx, sel->main_shader_part_es);
3205 if (sel->main_shader_part_ngg)
3206 si_delete_shader(sctx, sel->main_shader_part_ngg);
3207 if (sel->gs_copy_shader)
3208 si_delete_shader(sctx, sel->gs_copy_shader);
3209
3210 util_queue_fence_destroy(&sel->ready);
3211 mtx_destroy(&sel->mutex);
3212 free(sel->tokens);
3213 ralloc_free(sel->nir);
3214 free(sel);
3215 }
3216
3217 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3218 {
3219 struct si_context *sctx = (struct si_context *)ctx;
3220 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3221
3222 si_shader_selector_reference(sctx, &sel, NULL);
3223 }
3224
3225 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3226 struct si_shader *vs, unsigned name,
3227 unsigned index, unsigned interpolate)
3228 {
3229 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3230 unsigned j, offset, ps_input_cntl = 0;
3231
3232 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3233 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3234 name == TGSI_SEMANTIC_PRIMID)
3235 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3236
3237 if (name == TGSI_SEMANTIC_PCOORD ||
3238 (name == TGSI_SEMANTIC_TEXCOORD &&
3239 sctx->sprite_coord_enable & (1 << index))) {
3240 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3241 }
3242
3243 for (j = 0; j < vsinfo->num_outputs; j++) {
3244 if (name == vsinfo->output_semantic_name[j] &&
3245 index == vsinfo->output_semantic_index[j]) {
3246 offset = vs->info.vs_output_param_offset[j];
3247
3248 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3249 /* The input is loaded from parameter memory. */
3250 ps_input_cntl |= S_028644_OFFSET(offset);
3251 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3252 if (offset == AC_EXP_PARAM_UNDEFINED) {
3253 /* This can happen with depth-only rendering. */
3254 offset = 0;
3255 } else {
3256 /* The input is a DEFAULT_VAL constant. */
3257 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3258 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3259 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3260 }
3261
3262 ps_input_cntl = S_028644_OFFSET(0x20) |
3263 S_028644_DEFAULT_VAL(offset);
3264 }
3265 break;
3266 }
3267 }
3268
3269 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3270 /* PrimID is written after the last output when HW VS is used. */
3271 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3272 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3273 /* No corresponding output found, load defaults into input.
3274 * Don't set any other bits.
3275 * (FLAT_SHADE=1 completely changes behavior) */
3276 ps_input_cntl = S_028644_OFFSET(0x20);
3277 /* D3D 9 behaviour. GL is undefined */
3278 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3279 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3280 }
3281 return ps_input_cntl;
3282 }
3283
3284 static void si_emit_spi_map(struct si_context *sctx)
3285 {
3286 struct si_shader *ps = sctx->ps_shader.current;
3287 struct si_shader *vs = si_get_vs_state(sctx);
3288 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3289 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3290 unsigned spi_ps_input_cntl[32];
3291
3292 if (!ps || !ps->selector->info.num_inputs)
3293 return;
3294
3295 num_interp = si_get_ps_num_interp(ps);
3296 assert(num_interp > 0);
3297
3298 for (i = 0; i < psinfo->num_inputs; i++) {
3299 unsigned name = psinfo->input_semantic_name[i];
3300 unsigned index = psinfo->input_semantic_index[i];
3301 unsigned interpolate = psinfo->input_interpolate[i];
3302
3303 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3304 index, interpolate);
3305
3306 if (name == TGSI_SEMANTIC_COLOR) {
3307 assert(index < ARRAY_SIZE(bcol_interp));
3308 bcol_interp[index] = interpolate;
3309 }
3310 }
3311
3312 if (ps->key.part.ps.prolog.color_two_side) {
3313 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3314
3315 for (i = 0; i < 2; i++) {
3316 if (!(psinfo->colors_read & (0xf << (i * 4))))
3317 continue;
3318
3319 spi_ps_input_cntl[num_written++] =
3320 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3321
3322 }
3323 }
3324 assert(num_interp == num_written);
3325
3326 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3327 /* Dota 2: Only ~16% of SPI map updates set different values. */
3328 /* Talos: Only ~9% of SPI map updates set different values. */
3329 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3330 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3331 spi_ps_input_cntl,
3332 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3333
3334 if (initial_cdw != sctx->gfx_cs->current.cdw)
3335 sctx->context_roll = true;
3336 }
3337
3338 /**
3339 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3340 */
3341 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3342 {
3343 if (sctx->init_config_has_vgt_flush)
3344 return;
3345
3346 /* Done by Vulkan before VGT_FLUSH. */
3347 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3348 si_pm4_cmd_add(sctx->init_config,
3349 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3350 si_pm4_cmd_end(sctx->init_config, false);
3351
3352 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3353 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3354 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3355 si_pm4_cmd_end(sctx->init_config, false);
3356 sctx->init_config_has_vgt_flush = true;
3357 }
3358
3359 /* Initialize state related to ESGS / GSVS ring buffers */
3360 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3361 {
3362 struct si_shader_selector *es =
3363 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3364 struct si_shader_selector *gs = sctx->gs_shader.cso;
3365 struct si_pm4_state *pm4;
3366
3367 /* Chip constants. */
3368 unsigned num_se = sctx->screen->info.max_se;
3369 unsigned wave_size = 64;
3370 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3371 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3372 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3373 */
3374 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3375 unsigned alignment = 256 * num_se;
3376 /* The maximum size is 63.999 MB per SE. */
3377 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3378
3379 /* Calculate the minimum size. */
3380 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3381 wave_size, alignment);
3382
3383 /* These are recommended sizes, not minimum sizes. */
3384 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3385 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3386 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3387 gs->max_gsvs_emit_size;
3388
3389 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3390 esgs_ring_size = align(esgs_ring_size, alignment);
3391 gsvs_ring_size = align(gsvs_ring_size, alignment);
3392
3393 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3394 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3395
3396 /* Some rings don't have to be allocated if shaders don't use them.
3397 * (e.g. no varyings between ES and GS or GS and VS)
3398 *
3399 * GFX9 doesn't have the ESGS ring.
3400 */
3401 bool update_esgs = sctx->chip_class <= GFX8 &&
3402 esgs_ring_size &&
3403 (!sctx->esgs_ring ||
3404 sctx->esgs_ring->width0 < esgs_ring_size);
3405 bool update_gsvs = gsvs_ring_size &&
3406 (!sctx->gsvs_ring ||
3407 sctx->gsvs_ring->width0 < gsvs_ring_size);
3408
3409 if (!update_esgs && !update_gsvs)
3410 return true;
3411
3412 if (update_esgs) {
3413 pipe_resource_reference(&sctx->esgs_ring, NULL);
3414 sctx->esgs_ring =
3415 pipe_aligned_buffer_create(sctx->b.screen,
3416 SI_RESOURCE_FLAG_UNMAPPABLE,
3417 PIPE_USAGE_DEFAULT,
3418 esgs_ring_size, alignment);
3419 if (!sctx->esgs_ring)
3420 return false;
3421 }
3422
3423 if (update_gsvs) {
3424 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3425 sctx->gsvs_ring =
3426 pipe_aligned_buffer_create(sctx->b.screen,
3427 SI_RESOURCE_FLAG_UNMAPPABLE,
3428 PIPE_USAGE_DEFAULT,
3429 gsvs_ring_size, alignment);
3430 if (!sctx->gsvs_ring)
3431 return false;
3432 }
3433
3434 /* Create the "init_config_gs_rings" state. */
3435 pm4 = CALLOC_STRUCT(si_pm4_state);
3436 if (!pm4)
3437 return false;
3438
3439 if (sctx->chip_class >= GFX7) {
3440 if (sctx->esgs_ring) {
3441 assert(sctx->chip_class <= GFX8);
3442 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3443 sctx->esgs_ring->width0 / 256);
3444 }
3445 if (sctx->gsvs_ring)
3446 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3447 sctx->gsvs_ring->width0 / 256);
3448 } else {
3449 if (sctx->esgs_ring)
3450 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3451 sctx->esgs_ring->width0 / 256);
3452 if (sctx->gsvs_ring)
3453 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3454 sctx->gsvs_ring->width0 / 256);
3455 }
3456
3457 /* Set the state. */
3458 if (sctx->init_config_gs_rings)
3459 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3460 sctx->init_config_gs_rings = pm4;
3461
3462 if (!sctx->init_config_has_vgt_flush) {
3463 si_init_config_add_vgt_flush(sctx);
3464 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3465 }
3466
3467 /* Flush the context to re-emit both init_config states. */
3468 sctx->initial_gfx_cs_size = 0; /* force flush */
3469 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3470
3471 /* Set ring bindings. */
3472 if (sctx->esgs_ring) {
3473 assert(sctx->chip_class <= GFX8);
3474 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3475 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3476 true, true, 4, 64, 0);
3477 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3478 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3479 false, false, 0, 0, 0);
3480 }
3481 if (sctx->gsvs_ring) {
3482 si_set_ring_buffer(sctx, SI_RING_GSVS,
3483 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3484 false, false, 0, 0, 0);
3485 }
3486
3487 return true;
3488 }
3489
3490 static void si_shader_lock(struct si_shader *shader)
3491 {
3492 mtx_lock(&shader->selector->mutex);
3493 if (shader->previous_stage_sel) {
3494 assert(shader->previous_stage_sel != shader->selector);
3495 mtx_lock(&shader->previous_stage_sel->mutex);
3496 }
3497 }
3498
3499 static void si_shader_unlock(struct si_shader *shader)
3500 {
3501 if (shader->previous_stage_sel)
3502 mtx_unlock(&shader->previous_stage_sel->mutex);
3503 mtx_unlock(&shader->selector->mutex);
3504 }
3505
3506 /**
3507 * @returns 1 if \p sel has been updated to use a new scratch buffer
3508 * 0 if not
3509 * < 0 if there was a failure
3510 */
3511 static int si_update_scratch_buffer(struct si_context *sctx,
3512 struct si_shader *shader)
3513 {
3514 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3515
3516 if (!shader)
3517 return 0;
3518
3519 /* This shader doesn't need a scratch buffer */
3520 if (shader->config.scratch_bytes_per_wave == 0)
3521 return 0;
3522
3523 /* Prevent race conditions when updating:
3524 * - si_shader::scratch_bo
3525 * - si_shader::binary::code
3526 * - si_shader::previous_stage::binary::code.
3527 */
3528 si_shader_lock(shader);
3529
3530 /* This shader is already configured to use the current
3531 * scratch buffer. */
3532 if (shader->scratch_bo == sctx->scratch_buffer) {
3533 si_shader_unlock(shader);
3534 return 0;
3535 }
3536
3537 assert(sctx->scratch_buffer);
3538
3539 /* Replace the shader bo with a new bo that has the relocs applied. */
3540 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3541 si_shader_unlock(shader);
3542 return -1;
3543 }
3544
3545 /* Update the shader state to use the new shader bo. */
3546 si_shader_init_pm4_state(sctx->screen, shader);
3547
3548 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3549
3550 si_shader_unlock(shader);
3551 return 1;
3552 }
3553
3554 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3555 {
3556 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3557 }
3558
3559 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3560 {
3561 return shader ? shader->config.scratch_bytes_per_wave : 0;
3562 }
3563
3564 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3565 {
3566 if (!sctx->tes_shader.cso)
3567 return NULL; /* tessellation disabled */
3568
3569 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3570 sctx->fixed_func_tcs_shader.current;
3571 }
3572
3573 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3574 {
3575 unsigned bytes = 0;
3576
3577 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3578 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3579 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3580 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3581
3582 if (sctx->tes_shader.cso) {
3583 struct si_shader *tcs = si_get_tcs_current(sctx);
3584
3585 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3586 }
3587 return bytes;
3588 }
3589
3590 static bool si_update_scratch_relocs(struct si_context *sctx)
3591 {
3592 struct si_shader *tcs = si_get_tcs_current(sctx);
3593 int r;
3594
3595 /* Update the shaders, so that they are using the latest scratch.
3596 * The scratch buffer may have been changed since these shaders were
3597 * last used, so we still need to try to update them, even if they
3598 * require scratch buffers smaller than the current size.
3599 */
3600 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3601 if (r < 0)
3602 return false;
3603 if (r == 1)
3604 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3605
3606 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3607 if (r < 0)
3608 return false;
3609 if (r == 1)
3610 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3611
3612 r = si_update_scratch_buffer(sctx, tcs);
3613 if (r < 0)
3614 return false;
3615 if (r == 1)
3616 si_pm4_bind_state(sctx, hs, tcs->pm4);
3617
3618 /* VS can be bound as LS, ES, or VS. */
3619 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3620 if (r < 0)
3621 return false;
3622 if (r == 1) {
3623 if (sctx->vs_shader.current->key.as_ls)
3624 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3625 else if (sctx->vs_shader.current->key.as_es)
3626 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3627 else if (sctx->vs_shader.current->key.as_ngg)
3628 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3629 else
3630 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3631 }
3632
3633 /* TES can be bound as ES or VS. */
3634 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3635 if (r < 0)
3636 return false;
3637 if (r == 1) {
3638 if (sctx->tes_shader.current->key.as_es)
3639 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3640 else if (sctx->tes_shader.current->key.as_ngg)
3641 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3642 else
3643 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3644 }
3645
3646 return true;
3647 }
3648
3649 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3650 {
3651 unsigned current_scratch_buffer_size =
3652 si_get_current_scratch_buffer_size(sctx);
3653 unsigned scratch_bytes_per_wave =
3654 si_get_max_scratch_bytes_per_wave(sctx);
3655 unsigned scratch_needed_size = scratch_bytes_per_wave *
3656 sctx->scratch_waves;
3657 unsigned spi_tmpring_size;
3658
3659 if (scratch_needed_size > 0) {
3660 if (scratch_needed_size > current_scratch_buffer_size) {
3661 /* Create a bigger scratch buffer */
3662 si_resource_reference(&sctx->scratch_buffer, NULL);
3663
3664 sctx->scratch_buffer =
3665 si_aligned_buffer_create(&sctx->screen->b,
3666 SI_RESOURCE_FLAG_UNMAPPABLE,
3667 PIPE_USAGE_DEFAULT,
3668 scratch_needed_size, 256);
3669 if (!sctx->scratch_buffer)
3670 return false;
3671
3672 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3673 si_context_add_resource_size(sctx,
3674 &sctx->scratch_buffer->b.b);
3675 }
3676
3677 if (!si_update_scratch_relocs(sctx))
3678 return false;
3679 }
3680
3681 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3682 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3683 "scratch size should already be aligned correctly.");
3684
3685 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3686 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3687 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3688 sctx->spi_tmpring_size = spi_tmpring_size;
3689 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3690 }
3691 return true;
3692 }
3693
3694 static void si_init_tess_factor_ring(struct si_context *sctx)
3695 {
3696 assert(!sctx->tess_rings);
3697
3698 /* The address must be aligned to 2^19, because the shader only
3699 * receives the high 13 bits.
3700 */
3701 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3702 SI_RESOURCE_FLAG_32BIT,
3703 PIPE_USAGE_DEFAULT,
3704 sctx->screen->tess_offchip_ring_size +
3705 sctx->screen->tess_factor_ring_size,
3706 1 << 19);
3707 if (!sctx->tess_rings)
3708 return;
3709
3710 si_init_config_add_vgt_flush(sctx);
3711
3712 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3713 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3714
3715 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3716 sctx->screen->tess_offchip_ring_size;
3717
3718 /* Append these registers to the init config state. */
3719 if (sctx->chip_class >= GFX7) {
3720 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3721 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3722 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3723 factor_va >> 8);
3724 if (sctx->chip_class >= GFX10)
3725 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3726 S_030984_BASE_HI(factor_va >> 40));
3727 else if (sctx->chip_class == GFX9)
3728 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3729 S_030944_BASE_HI(factor_va >> 40));
3730 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3731 sctx->screen->vgt_hs_offchip_param);
3732 } else {
3733 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3734 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3735 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3736 factor_va >> 8);
3737 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3738 sctx->screen->vgt_hs_offchip_param);
3739 }
3740
3741 /* Flush the context to re-emit the init_config state.
3742 * This is done only once in a lifetime of a context.
3743 */
3744 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3745 sctx->initial_gfx_cs_size = 0; /* force flush */
3746 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3747 }
3748
3749 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3750 union si_vgt_stages_key key)
3751 {
3752 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3753 uint32_t stages = 0;
3754
3755 if (key.u.tess) {
3756 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3757 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3758
3759 if (key.u.gs)
3760 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3761 S_028B54_GS_EN(1);
3762 else if (key.u.ngg)
3763 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3764 else
3765 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3766 } else if (key.u.gs) {
3767 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3768 S_028B54_GS_EN(1);
3769 } else if (key.u.ngg) {
3770 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3771 }
3772
3773 if (key.u.ngg) {
3774 stages |= S_028B54_PRIMGEN_EN(1);
3775 if (key.u.streamout)
3776 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3777 } else if (key.u.gs)
3778 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3779
3780 if (screen->info.chip_class >= GFX9)
3781 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3782
3783 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3784 return pm4;
3785 }
3786
3787 static void si_update_vgt_shader_config(struct si_context *sctx,
3788 union si_vgt_stages_key key)
3789 {
3790 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3791
3792 if (unlikely(!*pm4))
3793 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3794 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3795 }
3796
3797 bool si_update_shaders(struct si_context *sctx)
3798 {
3799 struct pipe_context *ctx = (struct pipe_context*)sctx;
3800 struct si_compiler_ctx_state compiler_state;
3801 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3802 struct si_shader *old_vs = si_get_vs_state(sctx);
3803 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3804 struct si_shader *old_ps = sctx->ps_shader.current;
3805 union si_vgt_stages_key key;
3806 unsigned old_spi_shader_col_format =
3807 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3808 int r;
3809
3810 compiler_state.compiler = &sctx->compiler;
3811 compiler_state.debug = sctx->debug;
3812 compiler_state.is_debug_context = sctx->is_debug;
3813
3814 key.index = 0;
3815
3816 if (sctx->tes_shader.cso)
3817 key.u.tess = 1;
3818 if (sctx->gs_shader.cso)
3819 key.u.gs = 1;
3820
3821 if (sctx->chip_class >= GFX10) {
3822 key.u.ngg = sctx->ngg;
3823
3824 if (sctx->gs_shader.cso)
3825 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3826 else if (sctx->tes_shader.cso)
3827 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3828 else
3829 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3830 }
3831
3832 /* Update TCS and TES. */
3833 if (sctx->tes_shader.cso) {
3834 if (!sctx->tess_rings) {
3835 si_init_tess_factor_ring(sctx);
3836 if (!sctx->tess_rings)
3837 return false;
3838 }
3839
3840 if (sctx->tcs_shader.cso) {
3841 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3842 &compiler_state);
3843 if (r)
3844 return false;
3845 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3846 } else {
3847 if (!sctx->fixed_func_tcs_shader.cso) {
3848 sctx->fixed_func_tcs_shader.cso =
3849 si_create_fixed_func_tcs(sctx);
3850 if (!sctx->fixed_func_tcs_shader.cso)
3851 return false;
3852 }
3853
3854 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3855 key, &compiler_state);
3856 if (r)
3857 return false;
3858 si_pm4_bind_state(sctx, hs,
3859 sctx->fixed_func_tcs_shader.current->pm4);
3860 }
3861
3862 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3863 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3864 if (r)
3865 return false;
3866
3867 if (sctx->gs_shader.cso) {
3868 /* TES as ES */
3869 assert(sctx->chip_class <= GFX8);
3870 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3871 } else if (key.u.ngg) {
3872 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3873 } else {
3874 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3875 }
3876 }
3877 } else {
3878 if (sctx->chip_class <= GFX8)
3879 si_pm4_bind_state(sctx, ls, NULL);
3880 si_pm4_bind_state(sctx, hs, NULL);
3881 }
3882
3883 /* Update GS. */
3884 if (sctx->gs_shader.cso) {
3885 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3886 if (r)
3887 return false;
3888 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3889 if (!key.u.ngg) {
3890 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3891
3892 if (!si_update_gs_ring_buffers(sctx))
3893 return false;
3894 } else {
3895 si_pm4_bind_state(sctx, vs, NULL);
3896 }
3897 } else {
3898 if (!key.u.ngg) {
3899 si_pm4_bind_state(sctx, gs, NULL);
3900 if (sctx->chip_class <= GFX8)
3901 si_pm4_bind_state(sctx, es, NULL);
3902 }
3903 }
3904
3905 /* Update VS. */
3906 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3907 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3908 if (r)
3909 return false;
3910
3911 if (!key.u.tess && !key.u.gs) {
3912 if (key.u.ngg) {
3913 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3914 si_pm4_bind_state(sctx, vs, NULL);
3915 } else {
3916 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3917 }
3918 } else if (sctx->tes_shader.cso) {
3919 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3920 } else {
3921 assert(sctx->gs_shader.cso);
3922 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3923 }
3924 }
3925
3926 si_update_vgt_shader_config(sctx, key);
3927
3928 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3929 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3930
3931 if (sctx->ps_shader.cso) {
3932 unsigned db_shader_control;
3933
3934 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3935 if (r)
3936 return false;
3937 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3938
3939 db_shader_control =
3940 sctx->ps_shader.cso->db_shader_control |
3941 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3942
3943 if (si_pm4_state_changed(sctx, ps) ||
3944 si_pm4_state_changed(sctx, vs) ||
3945 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3946 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3947 sctx->flatshade != rs->flatshade) {
3948 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3949 sctx->flatshade = rs->flatshade;
3950 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3951 }
3952
3953 if (sctx->screen->rbplus_allowed &&
3954 si_pm4_state_changed(sctx, ps) &&
3955 (!old_ps ||
3956 old_spi_shader_col_format !=
3957 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3958 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3959
3960 if (sctx->ps_db_shader_control != db_shader_control) {
3961 sctx->ps_db_shader_control = db_shader_control;
3962 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3963 if (sctx->screen->dpbb_allowed)
3964 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3965 }
3966
3967 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3968 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3969 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3970
3971 if (sctx->chip_class == GFX6)
3972 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3973
3974 if (sctx->framebuffer.nr_samples <= 1)
3975 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3976 }
3977 }
3978
3979 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3980 si_pm4_state_enabled_and_changed(sctx, hs) ||
3981 si_pm4_state_enabled_and_changed(sctx, es) ||
3982 si_pm4_state_enabled_and_changed(sctx, gs) ||
3983 si_pm4_state_enabled_and_changed(sctx, vs) ||
3984 si_pm4_state_enabled_and_changed(sctx, ps)) {
3985 if (!si_update_spi_tmpring_size(sctx))
3986 return false;
3987 }
3988
3989 if (sctx->chip_class >= GFX7) {
3990 if (si_pm4_state_enabled_and_changed(sctx, ls))
3991 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3992 else if (!sctx->queued.named.ls)
3993 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3994
3995 if (si_pm4_state_enabled_and_changed(sctx, hs))
3996 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3997 else if (!sctx->queued.named.hs)
3998 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3999
4000 if (si_pm4_state_enabled_and_changed(sctx, es))
4001 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4002 else if (!sctx->queued.named.es)
4003 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4004
4005 if (si_pm4_state_enabled_and_changed(sctx, gs))
4006 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4007 else if (!sctx->queued.named.gs)
4008 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4009
4010 if (si_pm4_state_enabled_and_changed(sctx, vs))
4011 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4012 else if (!sctx->queued.named.vs)
4013 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4014
4015 if (si_pm4_state_enabled_and_changed(sctx, ps))
4016 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4017 else if (!sctx->queued.named.ps)
4018 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4019 }
4020
4021 sctx->do_update_shaders = false;
4022 return true;
4023 }
4024
4025 static void si_emit_scratch_state(struct si_context *sctx)
4026 {
4027 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4028
4029 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4030 sctx->spi_tmpring_size);
4031
4032 if (sctx->scratch_buffer) {
4033 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4034 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4035 RADEON_PRIO_SCRATCH_BUFFER);
4036 }
4037 }
4038
4039 void si_init_shader_functions(struct si_context *sctx)
4040 {
4041 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4042 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4043
4044 sctx->b.create_vs_state = si_create_shader_selector;
4045 sctx->b.create_tcs_state = si_create_shader_selector;
4046 sctx->b.create_tes_state = si_create_shader_selector;
4047 sctx->b.create_gs_state = si_create_shader_selector;
4048 sctx->b.create_fs_state = si_create_shader_selector;
4049
4050 sctx->b.bind_vs_state = si_bind_vs_shader;
4051 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4052 sctx->b.bind_tes_state = si_bind_tes_shader;
4053 sctx->b.bind_gs_state = si_bind_gs_shader;
4054 sctx->b.bind_fs_state = si_bind_ps_shader;
4055
4056 sctx->b.delete_vs_state = si_delete_shader_selector;
4057 sctx->b.delete_tcs_state = si_delete_shader_selector;
4058 sctx->b.delete_tes_state = si_delete_shader_selector;
4059 sctx->b.delete_gs_state = si_delete_shader_selector;
4060 sctx->b.delete_fs_state = si_delete_shader_selector;
4061 }