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radeonsi: bump SI_NUM_SHADER_BUFFERS to 32
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "ac_exp_param.h"
26 #include "ac_shader_util.h"
27 #include "compiler/nir/nir_serialize.h"
28 #include "nir/tgsi_to_nir.h"
29 #include "si_build_pm4.h"
30 #include "sid.h"
31 #include "util/crc32.h"
32 #include "util/disk_cache.h"
33 #include "util/hash_table.h"
34 #include "util/mesa-sha1.h"
35 #include "util/u_async_debug.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38
39 /* SHADER_CACHE */
40
41 /**
42 * Return the IR key for the shader cache.
43 */
44 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
45 unsigned char ir_sha1_cache_key[20])
46 {
47 struct blob blob = {};
48 unsigned ir_size;
49 void *ir_binary;
50
51 if (sel->nir_binary) {
52 ir_binary = sel->nir_binary;
53 ir_size = sel->nir_size;
54 } else {
55 assert(sel->nir);
56
57 blob_init(&blob);
58 nir_serialize(&blob, sel->nir, true);
59 ir_binary = blob.data;
60 ir_size = blob.size;
61 }
62
63 /* These settings affect the compilation, but they are not derived
64 * from the input shader IR.
65 */
66 unsigned shader_variant_flags = 0;
67
68 if (ngg)
69 shader_variant_flags |= 1 << 0;
70 if (sel->nir)
71 shader_variant_flags |= 1 << 1;
72 if (si_get_wave_size(sel->screen, sel->type, ngg, es, false) == 32)
73 shader_variant_flags |= 1 << 2;
74 if (sel->type == PIPE_SHADER_FRAGMENT && sel->info.uses_derivatives && sel->info.uses_kill &&
75 sel->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
76 shader_variant_flags |= 1 << 3;
77
78 /* This varies depending on whether compute-based culling is enabled. */
79 shader_variant_flags |= sel->screen->num_vbos_in_user_sgprs << 4;
80
81 struct mesa_sha1 ctx;
82 _mesa_sha1_init(&ctx);
83 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
84 _mesa_sha1_update(&ctx, ir_binary, ir_size);
85 if (sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_TESS_EVAL ||
86 sel->type == PIPE_SHADER_GEOMETRY)
87 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
88 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
89
90 if (ir_binary == blob.data)
91 blob_finish(&blob);
92 }
93
94 /** Copy "data" to "ptr" and return the next dword following copied data. */
95 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
96 {
97 /* data may be NULL if size == 0 */
98 if (size)
99 memcpy(ptr, data, size);
100 ptr += DIV_ROUND_UP(size, 4);
101 return ptr;
102 }
103
104 /** Read data from "ptr". Return the next dword following the data. */
105 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
106 {
107 memcpy(data, ptr, size);
108 ptr += DIV_ROUND_UP(size, 4);
109 return ptr;
110 }
111
112 /**
113 * Write the size as uint followed by the data. Return the next dword
114 * following the copied data.
115 */
116 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
117 {
118 *ptr++ = size;
119 return write_data(ptr, data, size);
120 }
121
122 /**
123 * Read the size as uint followed by the data. Return both via parameters.
124 * Return the next dword following the data.
125 */
126 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
127 {
128 *size = *ptr++;
129 assert(*data == NULL);
130 if (!*size)
131 return ptr;
132 *data = malloc(*size);
133 return read_data(ptr, *data, *size);
134 }
135
136 /**
137 * Return the shader binary in a buffer. The first 4 bytes contain its size
138 * as integer.
139 */
140 static void *si_get_shader_binary(struct si_shader *shader)
141 {
142 /* There is always a size of data followed by the data itself. */
143 unsigned llvm_ir_size =
144 shader->binary.llvm_ir_string ? strlen(shader->binary.llvm_ir_string) + 1 : 0;
145
146 /* Refuse to allocate overly large buffers and guard against integer
147 * overflow. */
148 if (shader->binary.elf_size > UINT_MAX / 4 || llvm_ir_size > UINT_MAX / 4)
149 return NULL;
150
151 unsigned size = 4 + /* total size */
152 4 + /* CRC32 of the data below */
153 align(sizeof(shader->config), 4) + align(sizeof(shader->info), 4) + 4 +
154 align(shader->binary.elf_size, 4) + 4 + align(llvm_ir_size, 4);
155 void *buffer = CALLOC(1, size);
156 uint32_t *ptr = (uint32_t *)buffer;
157
158 if (!buffer)
159 return NULL;
160
161 *ptr++ = size;
162 ptr++; /* CRC32 is calculated at the end. */
163
164 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
165 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
166 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
167 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
168 assert((char *)ptr - (char *)buffer == size);
169
170 /* Compute CRC32. */
171 ptr = (uint32_t *)buffer;
172 ptr++;
173 *ptr = util_hash_crc32(ptr + 1, size - 8);
174
175 return buffer;
176 }
177
178 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
179 {
180 uint32_t *ptr = (uint32_t *)binary;
181 uint32_t size = *ptr++;
182 uint32_t crc32 = *ptr++;
183 unsigned chunk_size;
184 unsigned elf_size;
185
186 if (util_hash_crc32(ptr, size - 8) != crc32) {
187 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
188 return false;
189 }
190
191 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
192 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
193 ptr = read_chunk(ptr, (void **)&shader->binary.elf_buffer, &elf_size);
194 shader->binary.elf_size = elf_size;
195 ptr = read_chunk(ptr, (void **)&shader->binary.llvm_ir_string, &chunk_size);
196
197 return true;
198 }
199
200 /**
201 * Insert a shader into the cache. It's assumed the shader is not in the cache.
202 * Use si_shader_cache_load_shader before calling this.
203 */
204 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
205 struct si_shader *shader, bool insert_into_disk_cache)
206 {
207 void *hw_binary;
208 struct hash_entry *entry;
209 uint8_t key[CACHE_KEY_SIZE];
210
211 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
212 if (entry)
213 return; /* already added */
214
215 hw_binary = si_get_shader_binary(shader);
216 if (!hw_binary)
217 return;
218
219 if (_mesa_hash_table_insert(sscreen->shader_cache, mem_dup(ir_sha1_cache_key, 20), hw_binary) ==
220 NULL) {
221 FREE(hw_binary);
222 return;
223 }
224
225 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
226 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, key);
227 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary, *((uint32_t *)hw_binary), NULL);
228 }
229 }
230
231 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
232 struct si_shader *shader)
233 {
234 struct hash_entry *entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
235
236 if (entry) {
237 if (si_load_shader_binary(shader, entry->data)) {
238 p_atomic_inc(&sscreen->num_memory_shader_cache_hits);
239 return true;
240 }
241 }
242 p_atomic_inc(&sscreen->num_memory_shader_cache_misses);
243
244 if (!sscreen->disk_shader_cache)
245 return false;
246
247 unsigned char sha1[CACHE_KEY_SIZE];
248 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, sha1);
249
250 size_t binary_size;
251 uint8_t *buffer = disk_cache_get(sscreen->disk_shader_cache, sha1, &binary_size);
252 if (buffer) {
253 if (binary_size >= sizeof(uint32_t) && *((uint32_t *)buffer) == binary_size) {
254 if (si_load_shader_binary(shader, buffer)) {
255 free(buffer);
256 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, false);
257 p_atomic_inc(&sscreen->num_disk_shader_cache_hits);
258 return true;
259 }
260 } else {
261 /* Something has gone wrong discard the item from the cache and
262 * rebuild/link from source.
263 */
264 assert(!"Invalid radeonsi shader disk cache item!");
265 disk_cache_remove(sscreen->disk_shader_cache, sha1);
266 }
267 }
268
269 free(buffer);
270 p_atomic_inc(&sscreen->num_disk_shader_cache_misses);
271 return false;
272 }
273
274 static uint32_t si_shader_cache_key_hash(const void *key)
275 {
276 /* Take the first dword of SHA1. */
277 return *(uint32_t *)key;
278 }
279
280 static bool si_shader_cache_key_equals(const void *a, const void *b)
281 {
282 /* Compare SHA1s. */
283 return memcmp(a, b, 20) == 0;
284 }
285
286 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
287 {
288 FREE((void *)entry->key);
289 FREE(entry->data);
290 }
291
292 bool si_init_shader_cache(struct si_screen *sscreen)
293 {
294 (void)simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
295 sscreen->shader_cache =
296 _mesa_hash_table_create(NULL, si_shader_cache_key_hash, si_shader_cache_key_equals);
297
298 return sscreen->shader_cache != NULL;
299 }
300
301 void si_destroy_shader_cache(struct si_screen *sscreen)
302 {
303 if (sscreen->shader_cache)
304 _mesa_hash_table_destroy(sscreen->shader_cache, si_destroy_shader_cache_entry);
305 simple_mtx_destroy(&sscreen->shader_cache_mutex);
306 }
307
308 /* SHADER STATES */
309
310 static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shader_selector *tes,
311 struct si_pm4_state *pm4)
312 {
313 const struct si_shader_info *info = &tes->info;
314 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
315 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
316 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
317 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
318 unsigned type, partitioning, topology, distribution_mode;
319
320 switch (tes_prim_mode) {
321 case PIPE_PRIM_LINES:
322 type = V_028B6C_TESS_ISOLINE;
323 break;
324 case PIPE_PRIM_TRIANGLES:
325 type = V_028B6C_TESS_TRIANGLE;
326 break;
327 case PIPE_PRIM_QUADS:
328 type = V_028B6C_TESS_QUAD;
329 break;
330 default:
331 assert(0);
332 return;
333 }
334
335 switch (tes_spacing) {
336 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
337 partitioning = V_028B6C_PART_FRAC_ODD;
338 break;
339 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
340 partitioning = V_028B6C_PART_FRAC_EVEN;
341 break;
342 case PIPE_TESS_SPACING_EQUAL:
343 partitioning = V_028B6C_PART_INTEGER;
344 break;
345 default:
346 assert(0);
347 return;
348 }
349
350 if (tes_point_mode)
351 topology = V_028B6C_OUTPUT_POINT;
352 else if (tes_prim_mode == PIPE_PRIM_LINES)
353 topology = V_028B6C_OUTPUT_LINE;
354 else if (tes_vertex_order_cw)
355 /* for some reason, this must be the other way around */
356 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
357 else
358 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
359
360 if (sscreen->info.has_distributed_tess) {
361 if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10)
362 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
363 else
364 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
365 } else
366 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
367
368 assert(pm4->shader);
369 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
370 S_028B6C_TOPOLOGY(topology) |
371 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
372 }
373
374 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
375 * whether the "fractional odd" tessellation spacing is used.
376 *
377 * Possible VGT configurations and which state should set the register:
378 *
379 * Reg set in | VGT shader configuration | Value
380 * ------------------------------------------------------
381 * VS as VS | VS | 30
382 * VS as ES | ES -> GS -> VS | 30
383 * TES as VS | LS -> HS -> VS | 14 or 30
384 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
385 *
386 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
387 */
388 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_shader_selector *sel,
389 struct si_shader *shader, struct si_pm4_state *pm4)
390 {
391 unsigned type = sel->type;
392
393 if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.chip_class >= GFX10)
394 return;
395
396 /* VS as VS, or VS as ES: */
397 if ((type == PIPE_SHADER_VERTEX &&
398 (!shader || (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
399 /* TES as VS, or TES as ES: */
400 type == PIPE_SHADER_TESS_EVAL) {
401 unsigned vtx_reuse_depth = 30;
402
403 if (type == PIPE_SHADER_TESS_EVAL &&
404 sel->info.properties[TGSI_PROPERTY_TES_SPACING] == PIPE_TESS_SPACING_FRACTIONAL_ODD)
405 vtx_reuse_depth = 14;
406
407 assert(pm4->shader);
408 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
409 }
410 }
411
412 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
413 {
414 if (shader->pm4)
415 si_pm4_clear_state(shader->pm4);
416 else
417 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
418
419 if (shader->pm4) {
420 shader->pm4->shader = shader;
421 return shader->pm4;
422 } else {
423 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
424 return NULL;
425 }
426 }
427
428 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
429 unsigned num_always_on_user_sgprs)
430 {
431 struct si_shader_selector *vs =
432 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
433 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
434
435 /* 1 SGPR is reserved for the vertex buffer pointer. */
436 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
437
438 if (num_vbos_in_user_sgprs)
439 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
440
441 /* Add the pointer to VBO descriptors. */
442 return num_always_on_user_sgprs + 1;
443 }
444
445 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
446 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_shader *shader,
447 bool legacy_vs_prim_id)
448 {
449 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
450 (shader->previous_stage_sel && shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
451
452 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
453 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
454 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
455 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or
456 * InstanceID)
457 */
458 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
459
460 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
461 return 3;
462 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
463 return 2;
464 else if (is_ls || shader->info.uses_instanceid)
465 return 1;
466 else
467 return 0;
468 }
469
470 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
471 {
472 struct si_pm4_state *pm4;
473 uint64_t va;
474
475 assert(sscreen->info.chip_class <= GFX8);
476
477 pm4 = si_get_shader_pm4_state(shader);
478 if (!pm4)
479 return;
480
481 va = shader->bo->gpu_address;
482 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
483 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
484
485 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
486 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
487 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
488 S_00B528_DX10_CLAMP(1) | S_00B528_FLOAT_MODE(shader->config.float_mode);
489 shader->config.rsrc2 =
490 S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
491 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
492 }
493
494 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
495 {
496 struct si_pm4_state *pm4;
497 uint64_t va;
498
499 pm4 = si_get_shader_pm4_state(shader);
500 if (!pm4)
501 return;
502
503 va = shader->bo->gpu_address;
504
505 if (sscreen->info.chip_class >= GFX9) {
506 if (sscreen->info.chip_class >= GFX10) {
507 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
508 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
509 } else {
510 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
511 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
512 }
513
514 unsigned num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
515
516 shader->config.rsrc2 = S_00B42C_USER_SGPR(num_user_sgprs) |
517 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
518
519 if (sscreen->info.chip_class >= GFX10)
520 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
521 else
522 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
523 } else {
524 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
525 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
526
527 shader->config.rsrc2 = S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) | S_00B42C_OC_LDS_EN(1) |
528 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
529 }
530
531 si_pm4_set_reg(
532 pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
533 S_00B428_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
534 (sscreen->info.chip_class <= GFX9 ? S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8)
535 : 0) |
536 S_00B428_DX10_CLAMP(1) | S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
537 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
538 S_00B428_FLOAT_MODE(shader->config.float_mode) |
539 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9
540 ? si_get_vs_vgpr_comp_cnt(sscreen, shader, false)
541 : 0));
542
543 if (sscreen->info.chip_class <= GFX8) {
544 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2);
545 }
546 }
547
548 static void si_emit_shader_es(struct si_context *sctx)
549 {
550 struct si_shader *shader = sctx->queued.named.es->shader;
551 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
552
553 if (!shader)
554 return;
555
556 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
557 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
558 shader->selector->esgs_itemsize / 4);
559
560 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
561 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
562 shader->vgt_tf_param);
563
564 if (shader->vgt_vertex_reuse_block_cntl)
565 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
566 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
567 shader->vgt_vertex_reuse_block_cntl);
568
569 if (initial_cdw != sctx->gfx_cs->current.cdw)
570 sctx->context_roll = true;
571 }
572
573 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
574 {
575 struct si_pm4_state *pm4;
576 unsigned num_user_sgprs;
577 unsigned vgpr_comp_cnt;
578 uint64_t va;
579 unsigned oc_lds_en;
580
581 assert(sscreen->info.chip_class <= GFX8);
582
583 pm4 = si_get_shader_pm4_state(shader);
584 if (!pm4)
585 return;
586
587 pm4->atom.emit = si_emit_shader_es;
588 va = shader->bo->gpu_address;
589
590 if (shader->selector->type == PIPE_SHADER_VERTEX) {
591 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
592 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
593 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
594 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
595 num_user_sgprs = SI_TES_NUM_USER_SGPR;
596 } else
597 unreachable("invalid shader selector type");
598
599 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
600
601 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
602 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
603 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
604 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
605 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
606 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B328_DX10_CLAMP(1) |
607 S_00B328_FLOAT_MODE(shader->config.float_mode));
608 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
609 S_00B32C_USER_SGPR(num_user_sgprs) | S_00B32C_OC_LDS_EN(oc_lds_en) |
610 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
611
612 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
613 si_set_tesseval_regs(sscreen, shader->selector, pm4);
614
615 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
616 }
617
618 void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *gs,
619 struct gfx9_gs_info *out)
620 {
621 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
622 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
623 bool uses_adjacency =
624 input_prim >= PIPE_PRIM_LINES_ADJACENCY && input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
625
626 /* All these are in dwords: */
627 /* We can't allow using the whole LDS, because GS waves compete with
628 * other shader stages for LDS space. */
629 const unsigned max_lds_size = 8 * 1024;
630 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
631 unsigned esgs_lds_size;
632
633 /* All these are per subgroup: */
634 const unsigned max_out_prims = 32 * 1024;
635 const unsigned max_es_verts = 255;
636 const unsigned ideal_gs_prims = 64;
637 unsigned max_gs_prims, gs_prims;
638 unsigned min_es_verts, es_verts, worst_case_es_verts;
639
640 if (uses_adjacency || gs_num_invocations > 1)
641 max_gs_prims = 127 / gs_num_invocations;
642 else
643 max_gs_prims = 255;
644
645 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
646 * Make sure we don't go over the maximum value.
647 */
648 if (gs->gs_max_out_vertices > 0) {
649 max_gs_prims =
650 MIN2(max_gs_prims, max_out_prims / (gs->gs_max_out_vertices * gs_num_invocations));
651 }
652 assert(max_gs_prims > 0);
653
654 /* If the primitive has adjacency, halve the number of vertices
655 * that will be reused in multiple primitives.
656 */
657 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
658
659 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
660 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
661
662 /* Compute ESGS LDS size based on the worst case number of ES vertices
663 * needed to create the target number of GS prims per subgroup.
664 */
665 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
666
667 /* If total LDS usage is too big, refactor partitions based on ratio
668 * of ESGS item sizes.
669 */
670 if (esgs_lds_size > max_lds_size) {
671 /* Our target GS Prims Per Subgroup was too large. Calculate
672 * the maximum number of GS Prims Per Subgroup that will fit
673 * into LDS, capped by the maximum that the hardware can support.
674 */
675 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)), max_gs_prims);
676 assert(gs_prims > 0);
677 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
678
679 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
680 assert(esgs_lds_size <= max_lds_size);
681 }
682
683 /* Now calculate remaining ESGS information. */
684 if (esgs_lds_size)
685 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
686 else
687 es_verts = max_es_verts;
688
689 /* Vertices for adjacency primitives are not always reused, so restore
690 * it for ES_VERTS_PER_SUBGRP.
691 */
692 min_es_verts = gs->gs_input_verts_per_prim;
693
694 /* For normal primitives, the VGT only checks if they are past the ES
695 * verts per subgroup after allocating a full GS primitive and if they
696 * are, kick off a new subgroup. But if those additional ES verts are
697 * unique (e.g. not reused) we need to make sure there is enough LDS
698 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
699 */
700 es_verts -= min_es_verts - 1;
701
702 out->es_verts_per_subgroup = es_verts;
703 out->gs_prims_per_subgroup = gs_prims;
704 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
705 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup * gs->gs_max_out_vertices;
706 out->esgs_ring_size = 4 * esgs_lds_size;
707
708 assert(out->max_prims_per_subgroup <= max_out_prims);
709 }
710
711 static void si_emit_shader_gs(struct si_context *sctx)
712 {
713 struct si_shader *shader = sctx->queued.named.gs->shader;
714 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
715
716 if (!shader)
717 return;
718
719 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
720 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
721 radeon_opt_set_context_reg3(
722 sctx, R_028A60_VGT_GSVS_RING_OFFSET_1, SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
723 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1, shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
724 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
725
726 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
727 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
728 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
729 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
730
731 /* R_028B38_VGT_GS_MAX_VERT_OUT */
732 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
733 shader->ctx_reg.gs.vgt_gs_max_vert_out);
734
735 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
736 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
737 radeon_opt_set_context_reg4(
738 sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE, SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
739 shader->ctx_reg.gs.vgt_gs_vert_itemsize, shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
740 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2, shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
741
742 /* R_028B90_VGT_GS_INSTANCE_CNT */
743 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
744 shader->ctx_reg.gs.vgt_gs_instance_cnt);
745
746 if (sctx->chip_class >= GFX9) {
747 /* R_028A44_VGT_GS_ONCHIP_CNTL */
748 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
749 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
750 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
751 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
752 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
753 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
754 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
755 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
756 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
757 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
758
759 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
760 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
761 shader->vgt_tf_param);
762 if (shader->vgt_vertex_reuse_block_cntl)
763 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
764 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
765 shader->vgt_vertex_reuse_block_cntl);
766 }
767
768 if (initial_cdw != sctx->gfx_cs->current.cdw)
769 sctx->context_roll = true;
770 }
771
772 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
773 {
774 struct si_shader_selector *sel = shader->selector;
775 const ubyte *num_components = sel->info.num_stream_output_components;
776 unsigned gs_num_invocations = sel->gs_num_invocations;
777 struct si_pm4_state *pm4;
778 uint64_t va;
779 unsigned max_stream = sel->max_gs_stream;
780 unsigned offset;
781
782 pm4 = si_get_shader_pm4_state(shader);
783 if (!pm4)
784 return;
785
786 pm4->atom.emit = si_emit_shader_gs;
787
788 offset = num_components[0] * sel->gs_max_out_vertices;
789 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
790
791 if (max_stream >= 1)
792 offset += num_components[1] * sel->gs_max_out_vertices;
793 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
794
795 if (max_stream >= 2)
796 offset += num_components[2] * sel->gs_max_out_vertices;
797 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
798
799 if (max_stream >= 3)
800 offset += num_components[3] * sel->gs_max_out_vertices;
801 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
802
803 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
804 assert(offset < (1 << 15));
805
806 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
807
808 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
809 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
810 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
811 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
812
813 shader->ctx_reg.gs.vgt_gs_instance_cnt =
814 S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0);
815
816 va = shader->bo->gpu_address;
817
818 if (sscreen->info.chip_class >= GFX9) {
819 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
820 unsigned es_type = shader->key.part.gs.es->type;
821 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
822
823 if (es_type == PIPE_SHADER_VERTEX) {
824 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
825 } else if (es_type == PIPE_SHADER_TESS_EVAL)
826 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
827 else
828 unreachable("invalid shader selector type");
829
830 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
831 * VGPR[0:4] are always loaded.
832 */
833 if (sel->info.uses_invocationid)
834 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
835 else if (sel->info.uses_primid)
836 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
837 else if (input_prim >= PIPE_PRIM_TRIANGLES)
838 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
839 else
840 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
841
842 unsigned num_user_sgprs;
843 if (es_type == PIPE_SHADER_VERTEX)
844 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
845 else
846 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
847
848 if (sscreen->info.chip_class >= GFX10) {
849 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
850 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
851 } else {
852 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
853 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
854 }
855
856 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) |
857 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
858 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
859 S_00B228_FLOAT_MODE(shader->config.float_mode) |
860 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
861 uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) |
862 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
863 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
864 S_00B22C_LDS_SIZE(shader->config.lds_size) |
865 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
866
867 if (sscreen->info.chip_class >= GFX10) {
868 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
869 } else {
870 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
871 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
872 }
873
874 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
875 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
876
877 if (sscreen->info.chip_class >= GFX10) {
878 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
879 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
880 }
881
882 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
883 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
884 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
885 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
886 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
887 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
888 shader->ctx_reg.gs.vgt_esgs_ring_itemsize = shader->key.part.gs.es->esgs_itemsize / 4;
889
890 if (es_type == PIPE_SHADER_TESS_EVAL)
891 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
892
893 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es, NULL, pm4);
894 } else {
895 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
896 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
897
898 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
899 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
900 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
901 S_00B228_DX10_CLAMP(1) | S_00B228_FLOAT_MODE(shader->config.float_mode));
902 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
903 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
904 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
905 }
906 }
907
908 static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
909 {
910 enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
911
912 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
913 sctx->tracked_regs.reg_value[reg] != value) {
914 struct radeon_cmdbuf *cs = sctx->gfx_cs;
915
916 if (sctx->chip_class == GFX10) {
917 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
918 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
919 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
920 }
921
922 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
923
924 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
925 sctx->tracked_regs.reg_value[reg] = value;
926 }
927 }
928
929 /* Common tail code for NGG primitive shaders. */
930 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader *shader,
931 unsigned initial_cdw)
932 {
933 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
934 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
935 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
936 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
937 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
938 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
939 shader->ctx_reg.ngg.vgt_primitiveid_en);
940 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
941 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
942 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
943 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
944 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
945 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
946 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
947 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
948 shader->ctx_reg.ngg.spi_vs_out_config);
949 radeon_opt_set_context_reg2(
950 sctx, R_028708_SPI_SHADER_IDX_FORMAT, SI_TRACKED_SPI_SHADER_IDX_FORMAT,
951 shader->ctx_reg.ngg.spi_shader_idx_format, shader->ctx_reg.ngg.spi_shader_pos_format);
952 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
953 shader->ctx_reg.ngg.pa_cl_vte_cntl);
954 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
955 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
956
957 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
958 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, shader->pa_cl_vs_out_cntl,
959 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
960
961 if (initial_cdw != sctx->gfx_cs->current.cdw)
962 sctx->context_roll = true;
963
964 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
965 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
966 }
967
968 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
969 {
970 struct si_shader *shader = sctx->queued.named.gs->shader;
971 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
972
973 if (!shader)
974 return;
975
976 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
977 }
978
979 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
980 {
981 struct si_shader *shader = sctx->queued.named.gs->shader;
982 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
983
984 if (!shader)
985 return;
986
987 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
988 shader->vgt_tf_param);
989
990 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
991 }
992
993 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
994 {
995 struct si_shader *shader = sctx->queued.named.gs->shader;
996 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
997
998 if (!shader)
999 return;
1000
1001 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1002 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1003
1004 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1005 }
1006
1007 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1008 {
1009 struct si_shader *shader = sctx->queued.named.gs->shader;
1010 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1011
1012 if (!shader)
1013 return;
1014
1015 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1016 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1017 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1018 shader->vgt_tf_param);
1019
1020 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1021 }
1022
1023 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1024 {
1025 if (gs->type == PIPE_SHADER_GEOMETRY)
1026 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1027
1028 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1029 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1030 return PIPE_PRIM_POINTS;
1031 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1032 return PIPE_PRIM_LINES;
1033 return PIPE_PRIM_TRIANGLES;
1034 }
1035
1036 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1037 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1038 }
1039
1040 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1041 {
1042 bool misc_vec_ena = sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1043 sel->info.writes_layer || sel->info.writes_viewport_index;
1044 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1045 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1046 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1047 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1048 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1049 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1050 }
1051
1052 /**
1053 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1054 * in NGG mode.
1055 */
1056 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1057 {
1058 const struct si_shader_selector *gs_sel = shader->selector;
1059 const struct si_shader_info *gs_info = &gs_sel->info;
1060 enum pipe_shader_type gs_type = shader->selector->type;
1061 const struct si_shader_selector *es_sel =
1062 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1063 const struct si_shader_info *es_info = &es_sel->info;
1064 enum pipe_shader_type es_type = es_sel->type;
1065 unsigned num_user_sgprs;
1066 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1067 uint64_t va;
1068 unsigned window_space = gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1069 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1070 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1071 unsigned input_prim = si_get_input_prim(gs_sel);
1072 bool break_wave_at_eoi = false;
1073 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1074 if (!pm4)
1075 return;
1076
1077 if (es_type == PIPE_SHADER_TESS_EVAL) {
1078 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1079 : gfx10_emit_shader_ngg_tess_nogs;
1080 } else {
1081 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1082 : gfx10_emit_shader_ngg_notess_nogs;
1083 }
1084
1085 va = shader->bo->gpu_address;
1086
1087 if (es_type == PIPE_SHADER_VERTEX) {
1088 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1089
1090 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1091 num_user_sgprs =
1092 SI_SGPR_VS_BLIT_DATA + es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1093 } else {
1094 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1095 }
1096 } else {
1097 assert(es_type == PIPE_SHADER_TESS_EVAL);
1098 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1099 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1100
1101 if (es_enable_prim_id || gs_info->uses_primid)
1102 break_wave_at_eoi = true;
1103 }
1104
1105 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1106 * VGPR[0:4] are always loaded.
1107 *
1108 * Vertex shaders always need to load VGPR3, because they need to
1109 * pass edge flags for decomposed primitives (such as quads) to the PA
1110 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1111 */
1112 if (gs_info->uses_invocationid ||
1113 (gs_type == PIPE_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1114 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1115 else if ((gs_type == PIPE_SHADER_GEOMETRY && gs_info->uses_primid) ||
1116 (gs_type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1117 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1118 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1119 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1120 else
1121 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1122
1123 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1124 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1125 si_pm4_set_reg(
1126 pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1127 S_00B228_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1128 S_00B228_FLOAT_MODE(shader->config.float_mode) | S_00B228_DX10_CLAMP(1) |
1129 S_00B228_MEM_ORDERED(1) | S_00B228_WGP_MODE(1) |
1130 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1131 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1132 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1133 S_00B22C_USER_SGPR(num_user_sgprs) |
1134 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1135 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1136 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1137 S_00B22C_LDS_SIZE(shader->config.lds_size));
1138
1139 /* Determine LATE_ALLOC_GS. */
1140 unsigned num_cu_per_sh = sscreen->info.min_good_cu_per_sa;
1141 unsigned late_alloc_wave64; /* The limit is per SA. */
1142
1143 /* For Wave32, the hw will launch twice the number of late
1144 * alloc waves, so 1 == 2x wave32.
1145 *
1146 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1147 */
1148 if (sscreen->info.family == CHIP_NAVI14 || !sscreen->info.use_late_alloc)
1149 late_alloc_wave64 = 0;
1150 else if (num_cu_per_sh <= 6)
1151 late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
1152 else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
1153 late_alloc_wave64 = (num_cu_per_sh - 2) * 6;
1154 else
1155 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
1156
1157 /* Limit LATE_ALLOC_GS for prevent a hang (hw bug). */
1158 if (sscreen->info.chip_class == GFX10)
1159 late_alloc_wave64 = MIN2(late_alloc_wave64, 64);
1160
1161 si_pm4_set_reg(
1162 pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1163 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64));
1164
1165 nparams = MAX2(shader->info.nr_param_exports, 1);
1166 shader->ctx_reg.ngg.spi_vs_out_config =
1167 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1168 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1169
1170 shader->ctx_reg.ngg.spi_shader_idx_format =
1171 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1172 shader->ctx_reg.ngg.spi_shader_pos_format =
1173 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1174 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1175 : V_02870C_SPI_SHADER_NONE) |
1176 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1177 : V_02870C_SPI_SHADER_NONE) |
1178 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1179 : V_02870C_SPI_SHADER_NONE);
1180
1181 shader->ctx_reg.ngg.vgt_primitiveid_en =
1182 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1183 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1184 gs_sel->info.writes_primid);
1185
1186 if (gs_type == PIPE_SHADER_GEOMETRY) {
1187 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1188 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1189 } else {
1190 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1191 }
1192
1193 if (es_type == PIPE_SHADER_TESS_EVAL)
1194 si_set_tesseval_regs(sscreen, es_sel, pm4);
1195
1196 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1197 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1198 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1199 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1200 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1201 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1202 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl = S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1203 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1204 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1205 S_028B90_CNT(gs_num_invocations) | S_028B90_ENABLE(gs_num_invocations > 1) |
1206 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(shader->ngg.max_vert_out_per_gs_instance);
1207
1208 /* Always output hw-generated edge flags and pass them via the prim
1209 * export to prevent drawing lines on internal edges of decomposed
1210 * primitives (such as quads) with polygon mode = lines. Only VS needs
1211 * this.
1212 */
1213 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1214 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX) |
1215 /* Reuse for NGG. */
1216 S_028838_VERTEX_REUSE_DEPTH_GFX103(sscreen->info.chip_class >= GFX10_3 ? 30 : 0);
1217 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1218
1219 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1220 float oversub_pc_factor = 0.25;
1221
1222 if (shader->key.opt.ngg_culling) {
1223 /* Be more aggressive with NGG culling. */
1224 if (shader->info.nr_param_exports > 4)
1225 oversub_pc_factor = 1;
1226 else if (shader->info.nr_param_exports > 2)
1227 oversub_pc_factor = 0.75;
1228 else
1229 oversub_pc_factor = 0.5;
1230 }
1231
1232 unsigned oversub_pc_lines = sscreen->info.pc_lines * oversub_pc_factor;
1233 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
1234 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1235
1236 if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
1237 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1238 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims * 3);
1239 } else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP) {
1240 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1241 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims + 2);
1242 } else {
1243 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1244 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1245 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1246
1247 /* Bug workaround for a possible hang with non-tessellation cases.
1248 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1249 *
1250 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1251 */
1252 if ((sscreen->info.chip_class == GFX10) &&
1253 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1254 shader->ngg.hw_max_esverts != 256) {
1255 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1256
1257 if (shader->ngg.hw_max_esverts > 5) {
1258 shader->ge_cntl |= S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1259 }
1260 }
1261 }
1262
1263 if (window_space) {
1264 shader->ctx_reg.ngg.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1265 } else {
1266 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1267 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1268 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1269 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1270 }
1271 }
1272
1273 static void si_emit_shader_vs(struct si_context *sctx)
1274 {
1275 struct si_shader *shader = sctx->queued.named.vs->shader;
1276 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1277
1278 if (!shader)
1279 return;
1280
1281 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE, SI_TRACKED_VGT_GS_MODE,
1282 shader->ctx_reg.vs.vgt_gs_mode);
1283 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
1284 shader->ctx_reg.vs.vgt_primitiveid_en);
1285
1286 if (sctx->chip_class <= GFX8) {
1287 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
1288 shader->ctx_reg.vs.vgt_reuse_off);
1289 }
1290
1291 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
1292 shader->ctx_reg.vs.spi_vs_out_config);
1293
1294 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1295 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1296 shader->ctx_reg.vs.spi_shader_pos_format);
1297
1298 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1299 shader->ctx_reg.vs.pa_cl_vte_cntl);
1300
1301 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1302 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1303 shader->vgt_tf_param);
1304
1305 if (shader->vgt_vertex_reuse_block_cntl)
1306 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1307 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1308 shader->vgt_vertex_reuse_block_cntl);
1309
1310 /* Required programming for tessellation. (legacy pipeline only) */
1311 if (sctx->chip_class >= GFX10 && shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1312 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1313 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1314 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1315 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1316 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1317 }
1318
1319 if (sctx->chip_class >= GFX10) {
1320 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1321 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, shader->pa_cl_vs_out_cntl,
1322 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1323 }
1324
1325 if (initial_cdw != sctx->gfx_cs->current.cdw)
1326 sctx->context_roll = true;
1327
1328 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1329 if (sctx->chip_class >= GFX10)
1330 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
1331 }
1332
1333 /**
1334 * Compute the state for \p shader, which will run as a vertex shader on the
1335 * hardware.
1336 *
1337 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1338 * is the copy shader.
1339 */
1340 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1341 struct si_shader_selector *gs)
1342 {
1343 const struct si_shader_info *info = &shader->selector->info;
1344 struct si_pm4_state *pm4;
1345 unsigned num_user_sgprs, vgpr_comp_cnt;
1346 uint64_t va;
1347 unsigned nparams, oc_lds_en;
1348 unsigned window_space = info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1349 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1350
1351 pm4 = si_get_shader_pm4_state(shader);
1352 if (!pm4)
1353 return;
1354
1355 pm4->atom.emit = si_emit_shader_vs;
1356
1357 /* We always write VGT_GS_MODE in the VS state, because every switch
1358 * between different shader pipelines involving a different GS or no
1359 * GS at all involves a switch of the VS (different GS use different
1360 * copy shaders). On the other hand, when the API switches from a GS to
1361 * no GS and then back to the same GS used originally, the GS state is
1362 * not sent again.
1363 */
1364 if (!gs) {
1365 unsigned mode = V_028A40_GS_OFF;
1366
1367 /* PrimID needs GS scenario A. */
1368 if (enable_prim_id)
1369 mode = V_028A40_GS_SCENARIO_A;
1370
1371 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1372 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1373 } else {
1374 shader->ctx_reg.vs.vgt_gs_mode =
1375 ac_vgt_gs_mode(gs->gs_max_out_vertices, sscreen->info.chip_class);
1376 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1377 }
1378
1379 if (sscreen->info.chip_class <= GFX8) {
1380 /* Reuse needs to be set off if we write oViewport. */
1381 shader->ctx_reg.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(info->writes_viewport_index);
1382 }
1383
1384 va = shader->bo->gpu_address;
1385
1386 if (gs) {
1387 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1388 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1389 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1390 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1391
1392 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1393 num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1394 } else {
1395 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1396 }
1397 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1398 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1399 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1400 } else
1401 unreachable("invalid shader selector type");
1402
1403 /* VS is required to export at least one param. */
1404 nparams = MAX2(shader->info.nr_param_exports, 1);
1405 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1406
1407 if (sscreen->info.chip_class >= GFX10) {
1408 shader->ctx_reg.vs.spi_vs_out_config |=
1409 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1410 }
1411
1412 shader->ctx_reg.vs.spi_shader_pos_format =
1413 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1414 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1415 : V_02870C_SPI_SHADER_NONE) |
1416 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1417 : V_02870C_SPI_SHADER_NONE) |
1418 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1419 : V_02870C_SPI_SHADER_NONE);
1420 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
1421 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1422 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1423
1424 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1425
1426 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1427 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1428
1429 uint32_t rsrc1 =
1430 S_00B128_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1431 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B128_DX10_CLAMP(1) |
1432 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1433 S_00B128_FLOAT_MODE(shader->config.float_mode);
1434 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) | S_00B12C_OC_LDS_EN(oc_lds_en) |
1435 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1436
1437 if (sscreen->info.chip_class >= GFX10)
1438 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1439 else if (sscreen->info.chip_class == GFX9)
1440 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1441
1442 if (sscreen->info.chip_class <= GFX9)
1443 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1444
1445 if (!sscreen->use_ngg_streamout) {
1446 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1447 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1448 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1449 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1450 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1451 }
1452
1453 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1454 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1455
1456 if (window_space)
1457 shader->ctx_reg.vs.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1458 else
1459 shader->ctx_reg.vs.pa_cl_vte_cntl =
1460 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1461 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1462 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1463
1464 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1465 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1466
1467 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1468 }
1469
1470 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1471 {
1472 struct si_shader_info *info = &ps->selector->info;
1473 unsigned num_colors = !!(info->colors_read & 0x0f) + !!(info->colors_read & 0xf0);
1474 unsigned num_interp =
1475 ps->selector->info.num_inputs + (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1476
1477 assert(num_interp <= 32);
1478 return MIN2(num_interp, 32);
1479 }
1480
1481 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1482 {
1483 unsigned spi_shader_col_format = shader->key.part.ps.epilog.spi_shader_col_format;
1484 unsigned value = 0, num_mrts = 0;
1485 unsigned i, num_targets = (util_last_bit(spi_shader_col_format) + 3) / 4;
1486
1487 /* Remove holes in spi_shader_col_format. */
1488 for (i = 0; i < num_targets; i++) {
1489 unsigned spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
1490
1491 if (spi_format) {
1492 value |= spi_format << (num_mrts * 4);
1493 num_mrts++;
1494 }
1495 }
1496
1497 return value;
1498 }
1499
1500 static void si_emit_shader_ps(struct si_context *sctx)
1501 {
1502 struct si_shader *shader = sctx->queued.named.ps->shader;
1503 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1504
1505 if (!shader)
1506 return;
1507
1508 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1509 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
1510 shader->ctx_reg.ps.spi_ps_input_ena,
1511 shader->ctx_reg.ps.spi_ps_input_addr);
1512
1513 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
1514 shader->ctx_reg.ps.spi_baryc_cntl);
1515 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
1516 shader->ctx_reg.ps.spi_ps_in_control);
1517
1518 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1519 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
1520 shader->ctx_reg.ps.spi_shader_z_format,
1521 shader->ctx_reg.ps.spi_shader_col_format);
1522
1523 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
1524 shader->ctx_reg.ps.cb_shader_mask);
1525
1526 if (initial_cdw != sctx->gfx_cs->current.cdw)
1527 sctx->context_roll = true;
1528 }
1529
1530 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1531 {
1532 struct si_shader_info *info = &shader->selector->info;
1533 struct si_pm4_state *pm4;
1534 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1535 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1536 uint64_t va;
1537 unsigned input_ena = shader->config.spi_ps_input_ena;
1538
1539 /* we need to enable at least one of them, otherwise we hang the GPU */
1540 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) || G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1541 G_0286CC_PERSP_CENTROID_ENA(input_ena) || G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1542 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) || G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1543 G_0286CC_LINEAR_CENTROID_ENA(input_ena) || G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1544 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1545 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) || G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1546 G_0286CC_PERSP_CENTER_ENA(input_ena) || G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1547 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1548
1549 /* Validate interpolation optimization flags (read as implications). */
1550 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1551 (G_0286CC_PERSP_CENTER_ENA(input_ena) && G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1552 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1553 (G_0286CC_LINEAR_CENTER_ENA(input_ena) && G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1554 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1555 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1556 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1557 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1558 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1559 (!G_0286CC_PERSP_CENTER_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1560 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1561 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1562
1563 /* Validate cases when the optimizations are off (read as implications). */
1564 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1565 !G_0286CC_PERSP_CENTER_ENA(input_ena) || !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1566 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1567 !G_0286CC_LINEAR_CENTER_ENA(input_ena) || !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1568
1569 pm4 = si_get_shader_pm4_state(shader);
1570 if (!pm4)
1571 return;
1572
1573 pm4->atom.emit = si_emit_shader_ps;
1574
1575 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1576 * Possible vaules:
1577 * 0 -> Position = pixel center
1578 * 1 -> Position = pixel centroid
1579 * 2 -> Position = at sample position
1580 *
1581 * From GLSL 4.5 specification, section 7.1:
1582 * "The variable gl_FragCoord is available as an input variable from
1583 * within fragment shaders and it holds the window relative coordinates
1584 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1585 * value can be for any location within the pixel, or one of the
1586 * fragment samples. The use of centroid does not further restrict
1587 * this value to be inside the current primitive."
1588 *
1589 * Meaning that centroid has no effect and we can return anything within
1590 * the pixel. Thus, return the value at sample position, because that's
1591 * the most accurate one shaders can get.
1592 */
1593 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1594
1595 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] == TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1596 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1597
1598 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1599 cb_shader_mask = ac_get_cb_shader_mask(shader->key.part.ps.epilog.spi_shader_col_format);
1600
1601 /* Ensure that some export memory is always allocated, for two reasons:
1602 *
1603 * 1) Correctness: The hardware ignores the EXEC mask if no export
1604 * memory is allocated, so KILL and alpha test do not work correctly
1605 * without this.
1606 * 2) Performance: Every shader needs at least a NULL export, even when
1607 * it writes no color/depth output. The NULL export instruction
1608 * stalls without this setting.
1609 *
1610 * Don't add this to CB_SHADER_MASK.
1611 *
1612 * GFX10 supports pixel shaders without exports by setting both
1613 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1614 * instructions if any are present.
1615 */
1616 if ((sscreen->info.chip_class <= GFX9 || info->uses_kill ||
1617 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1618 !spi_shader_col_format && !info->writes_z && !info->writes_stencil &&
1619 !info->writes_samplemask)
1620 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1621
1622 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1623 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1624
1625 /* Set interpolation controls. */
1626 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1627 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1628
1629 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1630 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1631 shader->ctx_reg.ps.spi_shader_z_format =
1632 ac_get_spi_shader_z_format(info->writes_z, info->writes_stencil, info->writes_samplemask);
1633 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1634 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1635
1636 va = shader->bo->gpu_address;
1637 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1638 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1639
1640 uint32_t rsrc1 =
1641 S_00B028_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1642 S_00B028_DX10_CLAMP(1) | S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1643 S_00B028_FLOAT_MODE(shader->config.float_mode);
1644
1645 if (sscreen->info.chip_class < GFX10) {
1646 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1647 }
1648
1649 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1650 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1651 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1652 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1653 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1654 }
1655
1656 static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader *shader)
1657 {
1658 switch (shader->selector->type) {
1659 case PIPE_SHADER_VERTEX:
1660 if (shader->key.as_ls)
1661 si_shader_ls(sscreen, shader);
1662 else if (shader->key.as_es)
1663 si_shader_es(sscreen, shader);
1664 else if (shader->key.as_ngg)
1665 gfx10_shader_ngg(sscreen, shader);
1666 else
1667 si_shader_vs(sscreen, shader, NULL);
1668 break;
1669 case PIPE_SHADER_TESS_CTRL:
1670 si_shader_hs(sscreen, shader);
1671 break;
1672 case PIPE_SHADER_TESS_EVAL:
1673 if (shader->key.as_es)
1674 si_shader_es(sscreen, shader);
1675 else if (shader->key.as_ngg)
1676 gfx10_shader_ngg(sscreen, shader);
1677 else
1678 si_shader_vs(sscreen, shader, NULL);
1679 break;
1680 case PIPE_SHADER_GEOMETRY:
1681 if (shader->key.as_ngg)
1682 gfx10_shader_ngg(sscreen, shader);
1683 else
1684 si_shader_gs(sscreen, shader);
1685 break;
1686 case PIPE_SHADER_FRAGMENT:
1687 si_shader_ps(sscreen, shader);
1688 break;
1689 default:
1690 assert(0);
1691 }
1692 }
1693
1694 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1695 {
1696 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1697 return sctx->queued.named.dsa->alpha_func;
1698 }
1699
1700 void si_shader_selector_key_vs(struct si_context *sctx, struct si_shader_selector *vs,
1701 struct si_shader_key *key, struct si_vs_prolog_bits *prolog_key)
1702 {
1703 if (!sctx->vertex_elements || vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1704 return;
1705
1706 struct si_vertex_elements *elts = sctx->vertex_elements;
1707
1708 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1709 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1710 prolog_key->unpack_instance_id_from_vertex_id = sctx->prim_discard_cs_instancing;
1711
1712 /* Prefer a monolithic shader to allow scheduling divisions around
1713 * VBO loads. */
1714 if (prolog_key->instance_divisor_is_fetched)
1715 key->opt.prefer_mono = 1;
1716
1717 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1718 unsigned count_mask = (1 << count) - 1;
1719 unsigned fix = elts->fix_fetch_always & count_mask;
1720 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1721
1722 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1723 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1724 while (mask) {
1725 unsigned i = u_bit_scan(&mask);
1726 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1727 unsigned vbidx = elts->vertex_buffer_index[i];
1728 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1729 unsigned align_mask = (1 << log_hw_load_size) - 1;
1730 if (vb->buffer_offset & align_mask || vb->stride & align_mask) {
1731 fix |= 1 << i;
1732 opencode |= 1 << i;
1733 }
1734 }
1735 }
1736
1737 while (fix) {
1738 unsigned i = u_bit_scan(&fix);
1739 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1740 }
1741 key->mono.vs_fetch_opencode = opencode;
1742 }
1743
1744 static void si_shader_selector_key_hw_vs(struct si_context *sctx, struct si_shader_selector *vs,
1745 struct si_shader_key *key)
1746 {
1747 struct si_shader_selector *ps = sctx->ps_shader.cso;
1748
1749 key->opt.clip_disable = sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1750 (vs->info.clipdist_writemask || vs->info.writes_clipvertex) &&
1751 !vs->info.culldist_writemask;
1752
1753 /* Find out if PS is disabled. */
1754 bool ps_disabled = true;
1755 if (ps) {
1756 bool ps_modifies_zs = ps->info.uses_kill || ps->info.writes_z || ps->info.writes_stencil ||
1757 ps->info.writes_samplemask ||
1758 sctx->queued.named.blend->alpha_to_coverage ||
1759 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1760 unsigned ps_colormask = si_get_total_colormask(sctx);
1761
1762 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1763 (!ps_colormask && !ps_modifies_zs && !ps->info.writes_memory);
1764 }
1765
1766 /* Find out which VS outputs aren't used by the PS. */
1767 uint64_t outputs_written = vs->outputs_written_before_ps;
1768 uint64_t inputs_read = 0;
1769
1770 /* Ignore outputs that are not passed from VS to PS. */
1771 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1772 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1773 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1774
1775 if (!ps_disabled) {
1776 inputs_read = ps->inputs_read;
1777 }
1778
1779 uint64_t linked = outputs_written & inputs_read;
1780
1781 key->opt.kill_outputs = ~linked & outputs_written;
1782 key->opt.ngg_culling = sctx->ngg_culling;
1783 }
1784
1785 /* Compute the key for the hw shader variant */
1786 static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_shader_selector *sel,
1787 union si_vgt_stages_key stages_key,
1788 struct si_shader_key *key)
1789 {
1790 struct si_context *sctx = (struct si_context *)ctx;
1791
1792 memset(key, 0, sizeof(*key));
1793
1794 switch (sel->type) {
1795 case PIPE_SHADER_VERTEX:
1796 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1797
1798 if (sctx->tes_shader.cso)
1799 key->as_ls = 1;
1800 else if (sctx->gs_shader.cso) {
1801 key->as_es = 1;
1802 key->as_ngg = stages_key.u.ngg;
1803 } else {
1804 key->as_ngg = stages_key.u.ngg;
1805 si_shader_selector_key_hw_vs(sctx, sel, key);
1806
1807 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1808 key->mono.u.vs_export_prim_id = 1;
1809 }
1810 break;
1811 case PIPE_SHADER_TESS_CTRL:
1812 if (sctx->chip_class >= GFX9) {
1813 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.tcs.ls_prolog);
1814 key->part.tcs.ls = sctx->vs_shader.cso;
1815
1816 /* When the LS VGPR fix is needed, monolithic shaders
1817 * can:
1818 * - avoid initializing EXEC in both the LS prolog
1819 * and the LS main part when !vs_needs_prolog
1820 * - remove the fixup for unused input VGPRs
1821 */
1822 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1823
1824 /* The LS output / HS input layout can be communicated
1825 * directly instead of via user SGPRs for merged LS-HS.
1826 * The LS VGPR fix prefers this too.
1827 */
1828 key->opt.prefer_mono = 1;
1829 }
1830
1831 key->part.tcs.epilog.prim_mode =
1832 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1833 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1834 sel->info.tessfactors_are_def_in_all_invocs;
1835 key->part.tcs.epilog.tes_reads_tess_factors = sctx->tes_shader.cso->info.reads_tess_factors;
1836
1837 if (sel == sctx->fixed_func_tcs_shader.cso)
1838 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1839 break;
1840 case PIPE_SHADER_TESS_EVAL:
1841 key->as_ngg = stages_key.u.ngg;
1842
1843 if (sctx->gs_shader.cso)
1844 key->as_es = 1;
1845 else {
1846 si_shader_selector_key_hw_vs(sctx, sel, key);
1847
1848 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1849 key->mono.u.vs_export_prim_id = 1;
1850 }
1851 break;
1852 case PIPE_SHADER_GEOMETRY:
1853 if (sctx->chip_class >= GFX9) {
1854 if (sctx->tes_shader.cso) {
1855 key->part.gs.es = sctx->tes_shader.cso;
1856 } else {
1857 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.gs.vs_prolog);
1858 key->part.gs.es = sctx->vs_shader.cso;
1859 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1860 }
1861
1862 key->as_ngg = stages_key.u.ngg;
1863
1864 /* Merged ES-GS can have unbalanced wave usage.
1865 *
1866 * ES threads are per-vertex, while GS threads are
1867 * per-primitive. So without any amplification, there
1868 * are fewer GS threads than ES threads, which can result
1869 * in empty (no-op) GS waves. With too much amplification,
1870 * there are more GS threads than ES threads, which
1871 * can result in empty (no-op) ES waves.
1872 *
1873 * Non-monolithic shaders are implemented by setting EXEC
1874 * at the beginning of shader parts, and don't jump to
1875 * the end if EXEC is 0.
1876 *
1877 * Monolithic shaders use conditional blocks, so they can
1878 * jump and skip empty waves of ES or GS. So set this to
1879 * always use optimized variants, which are monolithic.
1880 */
1881 key->opt.prefer_mono = 1;
1882 }
1883 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1884 break;
1885 case PIPE_SHADER_FRAGMENT: {
1886 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1887 struct si_state_blend *blend = sctx->queued.named.blend;
1888
1889 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1890 sel->info.colors_written == 0x1)
1891 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1892
1893 /* Select the shader color format based on whether
1894 * blending or alpha are needed.
1895 */
1896 key->part.ps.epilog.spi_shader_col_format =
1897 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1898 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1899 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1900 sctx->framebuffer.spi_shader_col_format_blend) |
1901 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1902 sctx->framebuffer.spi_shader_col_format_alpha) |
1903 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1904 sctx->framebuffer.spi_shader_col_format);
1905 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1906
1907 /* The output for dual source blending should have
1908 * the same format as the first output.
1909 */
1910 if (blend->dual_src_blend) {
1911 key->part.ps.epilog.spi_shader_col_format |=
1912 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1913 }
1914
1915 /* If alpha-to-coverage is enabled, we have to export alpha
1916 * even if there is no color buffer.
1917 */
1918 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) && blend->alpha_to_coverage)
1919 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1920
1921 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1922 * to the range supported by the type if a channel has less
1923 * than 16 bits and the export format is 16_ABGR.
1924 */
1925 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1926 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1927 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1928 }
1929
1930 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1931 if (!key->part.ps.epilog.last_cbuf) {
1932 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1933 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1934 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1935 }
1936
1937 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1938 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1939
1940 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1941 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1942
1943 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one && rs->multisample_enable;
1944
1945 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1946 key->part.ps.epilog.poly_line_smoothing =
1947 ((is_poly && rs->poly_smooth) || (is_line && rs->line_smooth)) &&
1948 sctx->framebuffer.nr_samples <= 1;
1949 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1950
1951 if (sctx->ps_iter_samples > 1 && sel->info.reads_samplemask) {
1952 key->part.ps.prolog.samplemask_log_ps_iter = util_logbase2(sctx->ps_iter_samples);
1953 }
1954
1955 if (rs->force_persample_interp && rs->multisample_enable &&
1956 sctx->framebuffer.nr_samples > 1 && sctx->ps_iter_samples > 1) {
1957 key->part.ps.prolog.force_persp_sample_interp =
1958 sel->info.uses_persp_center || sel->info.uses_persp_centroid;
1959
1960 key->part.ps.prolog.force_linear_sample_interp =
1961 sel->info.uses_linear_center || sel->info.uses_linear_centroid;
1962 } else if (rs->multisample_enable && sctx->framebuffer.nr_samples > 1) {
1963 key->part.ps.prolog.bc_optimize_for_persp =
1964 sel->info.uses_persp_center && sel->info.uses_persp_centroid;
1965 key->part.ps.prolog.bc_optimize_for_linear =
1966 sel->info.uses_linear_center && sel->info.uses_linear_centroid;
1967 } else {
1968 /* Make sure SPI doesn't compute more than 1 pair
1969 * of (i,j), which is the optimization here. */
1970 key->part.ps.prolog.force_persp_center_interp = sel->info.uses_persp_center +
1971 sel->info.uses_persp_centroid +
1972 sel->info.uses_persp_sample >
1973 1;
1974
1975 key->part.ps.prolog.force_linear_center_interp = sel->info.uses_linear_center +
1976 sel->info.uses_linear_centroid +
1977 sel->info.uses_linear_sample >
1978 1;
1979
1980 if (sel->info.uses_persp_opcode_interp_sample ||
1981 sel->info.uses_linear_opcode_interp_sample)
1982 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1983 }
1984
1985 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1986
1987 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1988 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1989 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1990 struct pipe_resource *tex = cb0->texture;
1991
1992 /* 1D textures are allocated and used as 2D on GFX9. */
1993 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1994 key->mono.u.ps.fbfetch_is_1D =
1995 sctx->chip_class != GFX9 &&
1996 (tex->target == PIPE_TEXTURE_1D || tex->target == PIPE_TEXTURE_1D_ARRAY);
1997 key->mono.u.ps.fbfetch_layered =
1998 tex->target == PIPE_TEXTURE_1D_ARRAY || tex->target == PIPE_TEXTURE_2D_ARRAY ||
1999 tex->target == PIPE_TEXTURE_CUBE || tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2000 tex->target == PIPE_TEXTURE_3D;
2001 }
2002 break;
2003 }
2004 default:
2005 assert(0);
2006 }
2007
2008 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2009 memset(&key->opt, 0, sizeof(key->opt));
2010 }
2011
2012 static void si_build_shader_variant(struct si_shader *shader, int thread_index, bool low_priority)
2013 {
2014 struct si_shader_selector *sel = shader->selector;
2015 struct si_screen *sscreen = sel->screen;
2016 struct ac_llvm_compiler *compiler;
2017 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2018
2019 if (thread_index >= 0) {
2020 if (low_priority) {
2021 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2022 compiler = &sscreen->compiler_lowp[thread_index];
2023 } else {
2024 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2025 compiler = &sscreen->compiler[thread_index];
2026 }
2027 if (!debug->async)
2028 debug = NULL;
2029 } else {
2030 assert(!low_priority);
2031 compiler = shader->compiler_ctx_state.compiler;
2032 }
2033
2034 if (!compiler->passes)
2035 si_init_compiler(sscreen, compiler);
2036
2037 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2038 PRINT_ERR("Failed to build shader variant (type=%u)\n", sel->type);
2039 shader->compilation_failed = true;
2040 return;
2041 }
2042
2043 if (shader->compiler_ctx_state.is_debug_context) {
2044 FILE *f = open_memstream(&shader->shader_log, &shader->shader_log_size);
2045 if (f) {
2046 si_shader_dump(sscreen, shader, NULL, f, false);
2047 fclose(f);
2048 }
2049 }
2050
2051 si_shader_init_pm4_state(sscreen, shader);
2052 }
2053
2054 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2055 {
2056 struct si_shader *shader = (struct si_shader *)job;
2057
2058 assert(thread_index >= 0);
2059
2060 si_build_shader_variant(shader, thread_index, true);
2061 }
2062
2063 static const struct si_shader_key zeroed;
2064
2065 static bool si_check_missing_main_part(struct si_screen *sscreen, struct si_shader_selector *sel,
2066 struct si_compiler_ctx_state *compiler_state,
2067 struct si_shader_key *key)
2068 {
2069 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2070
2071 if (!*mainp) {
2072 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2073
2074 if (!main_part)
2075 return false;
2076
2077 /* We can leave the fence as permanently signaled because the
2078 * main part becomes visible globally only after it has been
2079 * compiled. */
2080 util_queue_fence_init(&main_part->ready);
2081
2082 main_part->selector = sel;
2083 main_part->key.as_es = key->as_es;
2084 main_part->key.as_ls = key->as_ls;
2085 main_part->key.as_ngg = key->as_ngg;
2086 main_part->is_monolithic = false;
2087
2088 if (!si_compile_shader(sscreen, compiler_state->compiler, main_part,
2089 &compiler_state->debug)) {
2090 FREE(main_part);
2091 return false;
2092 }
2093 *mainp = main_part;
2094 }
2095 return true;
2096 }
2097
2098 /**
2099 * Select a shader variant according to the shader key.
2100 *
2101 * \param optimized_or_none If the key describes an optimized shader variant and
2102 * the compilation isn't finished, don't select any
2103 * shader and return an error.
2104 */
2105 int si_shader_select_with_key(struct si_screen *sscreen, struct si_shader_ctx_state *state,
2106 struct si_compiler_ctx_state *compiler_state,
2107 struct si_shader_key *key, int thread_index, bool optimized_or_none)
2108 {
2109 struct si_shader_selector *sel = state->cso;
2110 struct si_shader_selector *previous_stage_sel = NULL;
2111 struct si_shader *current = state->current;
2112 struct si_shader *iter, *shader = NULL;
2113
2114 again:
2115 /* Check if we don't need to change anything.
2116 * This path is also used for most shaders that don't need multiple
2117 * variants, it will cost just a computation of the key and this
2118 * test. */
2119 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0)) {
2120 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2121 if (current->is_optimized) {
2122 if (optimized_or_none)
2123 return -1;
2124
2125 memset(&key->opt, 0, sizeof(key->opt));
2126 goto current_not_ready;
2127 }
2128
2129 util_queue_fence_wait(&current->ready);
2130 }
2131
2132 return current->compilation_failed ? -1 : 0;
2133 }
2134 current_not_ready:
2135
2136 /* This must be done before the mutex is locked, because async GS
2137 * compilation calls this function too, and therefore must enter
2138 * the mutex first.
2139 *
2140 * Only wait if we are in a draw call. Don't wait if we are
2141 * in a compiler thread.
2142 */
2143 if (thread_index < 0)
2144 util_queue_fence_wait(&sel->ready);
2145
2146 simple_mtx_lock(&sel->mutex);
2147
2148 /* Find the shader variant. */
2149 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2150 /* Don't check the "current" shader. We checked it above. */
2151 if (current != iter && memcmp(&iter->key, key, sizeof(*key)) == 0) {
2152 simple_mtx_unlock(&sel->mutex);
2153
2154 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2155 /* If it's an optimized shader and its compilation has
2156 * been started but isn't done, use the unoptimized
2157 * shader so as not to cause a stall due to compilation.
2158 */
2159 if (iter->is_optimized) {
2160 if (optimized_or_none)
2161 return -1;
2162 memset(&key->opt, 0, sizeof(key->opt));
2163 goto again;
2164 }
2165
2166 util_queue_fence_wait(&iter->ready);
2167 }
2168
2169 if (iter->compilation_failed) {
2170 return -1; /* skip the draw call */
2171 }
2172
2173 state->current = iter;
2174 return 0;
2175 }
2176 }
2177
2178 /* Build a new shader. */
2179 shader = CALLOC_STRUCT(si_shader);
2180 if (!shader) {
2181 simple_mtx_unlock(&sel->mutex);
2182 return -ENOMEM;
2183 }
2184
2185 util_queue_fence_init(&shader->ready);
2186
2187 shader->selector = sel;
2188 shader->key = *key;
2189 shader->compiler_ctx_state = *compiler_state;
2190
2191 /* If this is a merged shader, get the first shader's selector. */
2192 if (sscreen->info.chip_class >= GFX9) {
2193 if (sel->type == PIPE_SHADER_TESS_CTRL)
2194 previous_stage_sel = key->part.tcs.ls;
2195 else if (sel->type == PIPE_SHADER_GEOMETRY)
2196 previous_stage_sel = key->part.gs.es;
2197
2198 /* We need to wait for the previous shader. */
2199 if (previous_stage_sel && thread_index < 0)
2200 util_queue_fence_wait(&previous_stage_sel->ready);
2201 }
2202
2203 bool is_pure_monolithic =
2204 sscreen->use_monolithic_shaders || memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2205
2206 /* Compile the main shader part if it doesn't exist. This can happen
2207 * if the initial guess was wrong.
2208 *
2209 * The prim discard CS doesn't need the main shader part.
2210 */
2211 if (!is_pure_monolithic && !key->opt.vs_as_prim_discard_cs) {
2212 bool ok = true;
2213
2214 /* Make sure the main shader part is present. This is needed
2215 * for shaders that can be compiled as VS, LS, or ES, and only
2216 * one of them is compiled at creation.
2217 *
2218 * It is also needed for GS, which can be compiled as non-NGG
2219 * and NGG.
2220 *
2221 * For merged shaders, check that the starting shader's main
2222 * part is present.
2223 */
2224 if (previous_stage_sel) {
2225 struct si_shader_key shader1_key = zeroed;
2226
2227 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2228 shader1_key.as_ls = 1;
2229 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2230 shader1_key.as_es = 1;
2231 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2232 } else {
2233 assert(0);
2234 }
2235
2236 simple_mtx_lock(&previous_stage_sel->mutex);
2237 ok = si_check_missing_main_part(sscreen, previous_stage_sel, compiler_state, &shader1_key);
2238 simple_mtx_unlock(&previous_stage_sel->mutex);
2239 }
2240
2241 if (ok) {
2242 ok = si_check_missing_main_part(sscreen, sel, compiler_state, key);
2243 }
2244
2245 if (!ok) {
2246 FREE(shader);
2247 simple_mtx_unlock(&sel->mutex);
2248 return -ENOMEM; /* skip the draw call */
2249 }
2250 }
2251
2252 /* Keep the reference to the 1st shader of merged shaders, so that
2253 * Gallium can't destroy it before we destroy the 2nd shader.
2254 *
2255 * Set sctx = NULL, because it's unused if we're not releasing
2256 * the shader, and we don't have any sctx here.
2257 */
2258 si_shader_selector_reference(NULL, &shader->previous_stage_sel, previous_stage_sel);
2259
2260 /* Monolithic-only shaders don't make a distinction between optimized
2261 * and unoptimized. */
2262 shader->is_monolithic =
2263 is_pure_monolithic || memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2264
2265 /* The prim discard CS is always optimized. */
2266 shader->is_optimized = (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2267 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2268
2269 /* If it's an optimized shader, compile it asynchronously. */
2270 if (shader->is_optimized && thread_index < 0) {
2271 /* Compile it asynchronously. */
2272 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority, shader, &shader->ready,
2273 si_build_shader_variant_low_priority, NULL, 0);
2274
2275 /* Add only after the ready fence was reset, to guard against a
2276 * race with si_bind_XX_shader. */
2277 if (!sel->last_variant) {
2278 sel->first_variant = shader;
2279 sel->last_variant = shader;
2280 } else {
2281 sel->last_variant->next_variant = shader;
2282 sel->last_variant = shader;
2283 }
2284
2285 /* Use the default (unoptimized) shader for now. */
2286 memset(&key->opt, 0, sizeof(key->opt));
2287 simple_mtx_unlock(&sel->mutex);
2288
2289 if (sscreen->options.sync_compile)
2290 util_queue_fence_wait(&shader->ready);
2291
2292 if (optimized_or_none)
2293 return -1;
2294 goto again;
2295 }
2296
2297 /* Reset the fence before adding to the variant list. */
2298 util_queue_fence_reset(&shader->ready);
2299
2300 if (!sel->last_variant) {
2301 sel->first_variant = shader;
2302 sel->last_variant = shader;
2303 } else {
2304 sel->last_variant->next_variant = shader;
2305 sel->last_variant = shader;
2306 }
2307
2308 simple_mtx_unlock(&sel->mutex);
2309
2310 assert(!shader->is_optimized);
2311 si_build_shader_variant(shader, thread_index, false);
2312
2313 util_queue_fence_signal(&shader->ready);
2314
2315 if (!shader->compilation_failed)
2316 state->current = shader;
2317
2318 return shader->compilation_failed ? -1 : 0;
2319 }
2320
2321 static int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state,
2322 union si_vgt_stages_key stages_key,
2323 struct si_compiler_ctx_state *compiler_state)
2324 {
2325 struct si_context *sctx = (struct si_context *)ctx;
2326 struct si_shader_key key;
2327
2328 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2329 return si_shader_select_with_key(sctx->screen, state, compiler_state, &key, -1, false);
2330 }
2331
2332 static void si_parse_next_shader_property(const struct si_shader_info *info, bool streamout,
2333 struct si_shader_key *key)
2334 {
2335 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2336
2337 switch (info->processor) {
2338 case PIPE_SHADER_VERTEX:
2339 switch (next_shader) {
2340 case PIPE_SHADER_GEOMETRY:
2341 key->as_es = 1;
2342 break;
2343 case PIPE_SHADER_TESS_CTRL:
2344 case PIPE_SHADER_TESS_EVAL:
2345 key->as_ls = 1;
2346 break;
2347 default:
2348 /* If POSITION isn't written, it can only be a HW VS
2349 * if streamout is used. If streamout isn't used,
2350 * assume that it's a HW LS. (the next shader is TCS)
2351 * This heuristic is needed for separate shader objects.
2352 */
2353 if (!info->writes_position && !streamout)
2354 key->as_ls = 1;
2355 }
2356 break;
2357
2358 case PIPE_SHADER_TESS_EVAL:
2359 if (next_shader == PIPE_SHADER_GEOMETRY || !info->writes_position)
2360 key->as_es = 1;
2361 break;
2362 }
2363 }
2364
2365 /**
2366 * Compile the main shader part or the monolithic shader as part of
2367 * si_shader_selector initialization. Since it can be done asynchronously,
2368 * there is no way to report compile failures to applications.
2369 */
2370 static void si_init_shader_selector_async(void *job, int thread_index)
2371 {
2372 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2373 struct si_screen *sscreen = sel->screen;
2374 struct ac_llvm_compiler *compiler;
2375 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2376
2377 assert(!debug->debug_message || debug->async);
2378 assert(thread_index >= 0);
2379 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2380 compiler = &sscreen->compiler[thread_index];
2381
2382 if (!compiler->passes)
2383 si_init_compiler(sscreen, compiler);
2384
2385 /* Serialize NIR to save memory. Monolithic shader variants
2386 * have to deserialize NIR before compilation.
2387 */
2388 if (sel->nir) {
2389 struct blob blob;
2390 size_t size;
2391
2392 blob_init(&blob);
2393 /* true = remove optional debugging data to increase
2394 * the likehood of getting more shader cache hits.
2395 * It also drops variable names, so we'll save more memory.
2396 */
2397 nir_serialize(&blob, sel->nir, true);
2398 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2399 sel->nir_size = size;
2400 }
2401
2402 /* Compile the main shader part for use with a prolog and/or epilog.
2403 * If this fails, the driver will try to compile a monolithic shader
2404 * on demand.
2405 */
2406 if (!sscreen->use_monolithic_shaders) {
2407 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2408 unsigned char ir_sha1_cache_key[20];
2409
2410 if (!shader) {
2411 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2412 return;
2413 }
2414
2415 /* We can leave the fence signaled because use of the default
2416 * main part is guarded by the selector's ready fence. */
2417 util_queue_fence_init(&shader->ready);
2418
2419 shader->selector = sel;
2420 shader->is_monolithic = false;
2421 si_parse_next_shader_property(&sel->info, sel->so.num_outputs != 0, &shader->key);
2422
2423 if (sscreen->use_ngg && (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2424 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2425 sel->type == PIPE_SHADER_TESS_EVAL || sel->type == PIPE_SHADER_GEOMETRY))
2426 shader->key.as_ngg = 1;
2427
2428 if (sel->nir) {
2429 si_get_ir_cache_key(sel, shader->key.as_ngg, shader->key.as_es, ir_sha1_cache_key);
2430 }
2431
2432 /* Try to load the shader from the shader cache. */
2433 simple_mtx_lock(&sscreen->shader_cache_mutex);
2434
2435 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2436 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2437 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2438 } else {
2439 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2440
2441 /* Compile the shader if it hasn't been loaded from the cache. */
2442 if (!si_compile_shader(sscreen, compiler, shader, debug)) {
2443 FREE(shader);
2444 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2445 return;
2446 }
2447
2448 simple_mtx_lock(&sscreen->shader_cache_mutex);
2449 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
2450 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2451 }
2452
2453 *si_get_main_shader_part(sel, &shader->key) = shader;
2454
2455 /* Unset "outputs_written" flags for outputs converted to
2456 * DEFAULT_VAL, so that later inter-shader optimizations don't
2457 * try to eliminate outputs that don't exist in the final
2458 * shader.
2459 *
2460 * This is only done if non-monolithic shaders are enabled.
2461 */
2462 if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_TESS_EVAL) &&
2463 !shader->key.as_ls && !shader->key.as_es) {
2464 unsigned i;
2465
2466 for (i = 0; i < sel->info.num_outputs; i++) {
2467 unsigned offset = shader->info.vs_output_param_offset[i];
2468
2469 if (offset <= AC_EXP_PARAM_OFFSET_31)
2470 continue;
2471
2472 unsigned name = sel->info.output_semantic_name[i];
2473 unsigned index = sel->info.output_semantic_index[i];
2474 unsigned id;
2475
2476 switch (name) {
2477 case TGSI_SEMANTIC_GENERIC:
2478 /* don't process indices the function can't handle */
2479 if (index >= SI_MAX_IO_GENERIC)
2480 break;
2481 /* fall through */
2482 default:
2483 id = si_shader_io_get_unique_index(name, index, true);
2484 sel->outputs_written_before_ps &= ~(1ull << id);
2485 break;
2486 case TGSI_SEMANTIC_POSITION: /* ignore these */
2487 case TGSI_SEMANTIC_PSIZE:
2488 case TGSI_SEMANTIC_CLIPVERTEX:
2489 case TGSI_SEMANTIC_EDGEFLAG:
2490 break;
2491 }
2492 }
2493 }
2494 }
2495
2496 /* The GS copy shader is always pre-compiled. */
2497 if (sel->type == PIPE_SHADER_GEOMETRY &&
2498 (!sscreen->use_ngg || !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2499 sel->tess_turns_off_ngg)) {
2500 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2501 if (!sel->gs_copy_shader) {
2502 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2503 return;
2504 }
2505
2506 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2507 }
2508
2509 /* Free NIR. We only keep serialized NIR after this point. */
2510 if (sel->nir) {
2511 ralloc_free(sel->nir);
2512 sel->nir = NULL;
2513 }
2514 }
2515
2516 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2517 struct util_queue_fence *ready_fence,
2518 struct si_compiler_ctx_state *compiler_ctx_state, void *job,
2519 util_queue_execute_func execute)
2520 {
2521 util_queue_fence_init(ready_fence);
2522
2523 struct util_async_debug_callback async_debug;
2524 bool debug = (sctx->debug.debug_message && !sctx->debug.async) || sctx->is_debug ||
2525 si_can_dump_shader(sctx->screen, processor);
2526
2527 if (debug) {
2528 u_async_debug_init(&async_debug);
2529 compiler_ctx_state->debug = async_debug.base;
2530 }
2531
2532 util_queue_add_job(&sctx->screen->shader_compiler_queue, job, ready_fence, execute, NULL, 0);
2533
2534 if (debug) {
2535 util_queue_fence_wait(ready_fence);
2536 u_async_debug_drain(&async_debug, &sctx->debug);
2537 u_async_debug_cleanup(&async_debug);
2538 }
2539
2540 if (sctx->screen->options.sync_compile)
2541 util_queue_fence_wait(ready_fence);
2542 }
2543
2544 /* Return descriptor slot usage masks from the given shader info. */
2545 void si_get_active_slot_masks(const struct si_shader_info *info, uint64_t *const_and_shader_buffers,
2546 uint64_t *samplers_and_images)
2547 {
2548 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2549
2550 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2551 num_constbufs = util_last_bit(info->const_buffers_declared);
2552 /* two 8-byte images share one 16-byte slot */
2553 num_images = align(util_last_bit(info->images_declared), 2);
2554 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2555 num_samplers = util_last_bit(info->samplers_declared);
2556
2557 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2558 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2559 *const_and_shader_buffers = u_bit_consecutive64(start, num_shaderbufs + num_constbufs);
2560
2561 /* The layout is:
2562 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2563 * - image[last] ... image[0] go to [31-last .. 31]
2564 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2565 *
2566 * FMASKs for images are placed separately, because MSAA images are rare,
2567 * and so we can benefit from a better cache hit rate if we keep image
2568 * descriptors together.
2569 */
2570 if (num_msaa_images)
2571 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2572
2573 start = si_get_image_slot(num_images - 1) / 2;
2574 *samplers_and_images = u_bit_consecutive64(start, num_images / 2 + num_samplers);
2575 }
2576
2577 static void *si_create_shader_selector(struct pipe_context *ctx,
2578 const struct pipe_shader_state *state)
2579 {
2580 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2581 struct si_context *sctx = (struct si_context *)ctx;
2582 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2583 int i;
2584
2585 if (!sel)
2586 return NULL;
2587
2588 sel->screen = sscreen;
2589 sel->compiler_ctx_state.debug = sctx->debug;
2590 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2591
2592 sel->so = state->stream_output;
2593
2594 if (state->type == PIPE_SHADER_IR_TGSI) {
2595 sel->nir = tgsi_to_nir(state->tokens, ctx->screen, true);
2596 } else {
2597 assert(state->type == PIPE_SHADER_IR_NIR);
2598 sel->nir = state->ir.nir;
2599 }
2600
2601 si_nir_scan_shader(sel->nir, &sel->info);
2602 si_nir_adjust_driver_locations(sel->nir);
2603
2604 sel->type = sel->info.processor;
2605 p_atomic_inc(&sscreen->num_shaders_created);
2606 si_get_active_slot_masks(&sel->info, &sel->active_const_and_shader_buffers,
2607 &sel->active_samplers_and_images);
2608
2609 /* Record which streamout buffers are enabled. */
2610 for (i = 0; i < sel->so.num_outputs; i++) {
2611 sel->enabled_streamout_buffer_mask |= (1 << sel->so.output[i].output_buffer)
2612 << (sel->so.output[i].stream * 4);
2613 }
2614
2615 sel->num_vs_inputs =
2616 sel->type == PIPE_SHADER_VERTEX && !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]
2617 ? sel->info.num_inputs
2618 : 0;
2619 sel->num_vbos_in_user_sgprs = MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2620
2621 /* The prolog is a no-op if there are no inputs. */
2622 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX && sel->info.num_inputs &&
2623 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2624
2625 sel->prim_discard_cs_allowed =
2626 sel->type == PIPE_SHADER_VERTEX && !sel->info.uses_bindless_images &&
2627 !sel->info.uses_bindless_samplers && !sel->info.writes_memory &&
2628 !sel->info.writes_viewport_index &&
2629 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] && !sel->so.num_outputs;
2630
2631 switch (sel->type) {
2632 case PIPE_SHADER_GEOMETRY:
2633 sel->gs_output_prim = sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2634
2635 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2636 sel->rast_prim = sel->gs_output_prim;
2637 if (util_rast_prim_is_triangles(sel->rast_prim))
2638 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2639
2640 sel->gs_max_out_vertices = sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2641 sel->gs_num_invocations = sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2642 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2643 sel->max_gsvs_emit_size = sel->gsvs_vertex_size * sel->gs_max_out_vertices;
2644
2645 sel->max_gs_stream = 0;
2646 for (i = 0; i < sel->so.num_outputs; i++)
2647 sel->max_gs_stream = MAX2(sel->max_gs_stream, sel->so.output[i].stream);
2648
2649 sel->gs_input_verts_per_prim =
2650 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2651
2652 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2653 sel->tess_turns_off_ngg = sscreen->info.chip_class >= GFX10 &&
2654 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2655 break;
2656
2657 case PIPE_SHADER_TESS_CTRL:
2658 /* Always reserve space for these. */
2659 sel->patch_outputs_written |=
2660 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2661 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2662 /* fall through */
2663 case PIPE_SHADER_VERTEX:
2664 case PIPE_SHADER_TESS_EVAL:
2665 for (i = 0; i < sel->info.num_outputs; i++) {
2666 unsigned name = sel->info.output_semantic_name[i];
2667 unsigned index = sel->info.output_semantic_index[i];
2668
2669 switch (name) {
2670 case TGSI_SEMANTIC_TESSINNER:
2671 case TGSI_SEMANTIC_TESSOUTER:
2672 case TGSI_SEMANTIC_PATCH:
2673 sel->patch_outputs_written |= 1ull << si_shader_io_get_unique_index_patch(name, index);
2674 break;
2675
2676 case TGSI_SEMANTIC_GENERIC:
2677 /* don't process indices the function can't handle */
2678 if (index >= SI_MAX_IO_GENERIC)
2679 break;
2680 /* fall through */
2681 default:
2682 sel->outputs_written |= 1ull << si_shader_io_get_unique_index(name, index, false);
2683 sel->outputs_written_before_ps |= 1ull
2684 << si_shader_io_get_unique_index(name, index, true);
2685 break;
2686 case TGSI_SEMANTIC_EDGEFLAG:
2687 break;
2688 }
2689 }
2690 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2691 sel->lshs_vertex_stride = sel->esgs_itemsize;
2692
2693 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2694 * will start on a different bank. (except for the maximum 32*16).
2695 */
2696 if (sel->lshs_vertex_stride < 32 * 16)
2697 sel->lshs_vertex_stride += 4;
2698
2699 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2700 * conflicts, i.e. each vertex will start at a different bank.
2701 */
2702 if (sctx->chip_class >= GFX9)
2703 sel->esgs_itemsize += 4;
2704
2705 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2706
2707 /* Only for TES: */
2708 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2709 sel->rast_prim = PIPE_PRIM_POINTS;
2710 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2711 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2712 else
2713 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2714 break;
2715
2716 case PIPE_SHADER_FRAGMENT:
2717 for (i = 0; i < sel->info.num_inputs; i++) {
2718 unsigned name = sel->info.input_semantic_name[i];
2719 unsigned index = sel->info.input_semantic_index[i];
2720
2721 switch (name) {
2722 case TGSI_SEMANTIC_GENERIC:
2723 /* don't process indices the function can't handle */
2724 if (index >= SI_MAX_IO_GENERIC)
2725 break;
2726 /* fall through */
2727 default:
2728 sel->inputs_read |= 1ull << si_shader_io_get_unique_index(name, index, true);
2729 break;
2730 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2731 break;
2732 }
2733 }
2734
2735 for (i = 0; i < 8; i++)
2736 if (sel->info.colors_written & (1 << i))
2737 sel->colors_written_4bit |= 0xf << (4 * i);
2738
2739 for (i = 0; i < sel->info.num_inputs; i++) {
2740 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2741 int index = sel->info.input_semantic_index[i];
2742 sel->color_attr_index[index] = i;
2743 }
2744 }
2745 break;
2746 default:;
2747 }
2748
2749 sel->ngg_culling_allowed =
2750 sscreen->info.chip_class >= GFX10 &&
2751 sscreen->info.has_dedicated_vram &&
2752 sscreen->use_ngg_culling &&
2753 /* Disallow TES by default, because TessMark results are mixed. */
2754 (sel->type == PIPE_SHADER_VERTEX ||
2755 (sscreen->always_use_ngg_culling && sel->type == PIPE_SHADER_TESS_EVAL)) &&
2756 sel->info.writes_position &&
2757 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
2758 !sel->info.writes_memory && !sel->so.num_outputs &&
2759 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] &&
2760 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2761
2762 /* PA_CL_VS_OUT_CNTL */
2763 if (sctx->chip_class <= GFX9)
2764 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2765
2766 sel->clipdist_mask = sel->info.writes_clipvertex ? SIX_BITS : sel->info.clipdist_writemask;
2767 sel->culldist_mask = sel->info.culldist_writemask << sel->info.num_written_clipdistance;
2768
2769 /* DB_SHADER_CONTROL */
2770 sel->db_shader_control = S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2771 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2772 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2773 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2774
2775 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2776 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2777 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2778 break;
2779 case TGSI_FS_DEPTH_LAYOUT_LESS:
2780 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2781 break;
2782 }
2783
2784 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2785 *
2786 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2787 * --|-----------|------------|------------|--------------------|-------------------|-------------
2788 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2789 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2790 * 2 | false | true | n/a | LateZ | 1 | 0
2791 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2792 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2793 *
2794 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2795 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2796 *
2797 * Don't use ReZ without profiling !!!
2798 *
2799 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2800 * shaders.
2801 */
2802 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2803 /* Cases 3, 4. */
2804 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2805 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2806 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2807 } else if (sel->info.writes_memory) {
2808 /* Case 2. */
2809 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) | S_02880C_EXEC_ON_HIER_FAIL(1);
2810 } else {
2811 /* Case 1. */
2812 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2813 }
2814
2815 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2816 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2817
2818 (void)simple_mtx_init(&sel->mutex, mtx_plain);
2819
2820 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready, &sel->compiler_ctx_state,
2821 sel, si_init_shader_selector_async);
2822 return sel;
2823 }
2824
2825 static void *si_create_shader(struct pipe_context *ctx, const struct pipe_shader_state *state)
2826 {
2827 struct si_context *sctx = (struct si_context *)ctx;
2828 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2829 bool cache_hit;
2830 struct si_shader_selector *sel = (struct si_shader_selector *)util_live_shader_cache_get(
2831 ctx, &sscreen->live_shader_cache, state, &cache_hit);
2832
2833 if (sel && cache_hit && sctx->debug.debug_message) {
2834 if (sel->main_shader_part)
2835 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part, &sctx->debug);
2836 if (sel->main_shader_part_ls)
2837 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ls, &sctx->debug);
2838 if (sel->main_shader_part_es)
2839 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_es, &sctx->debug);
2840 if (sel->main_shader_part_ngg)
2841 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg, &sctx->debug);
2842 if (sel->main_shader_part_ngg_es)
2843 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg_es, &sctx->debug);
2844 }
2845 return sel;
2846 }
2847
2848 static void si_update_streamout_state(struct si_context *sctx)
2849 {
2850 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2851
2852 if (!shader_with_so)
2853 return;
2854
2855 sctx->streamout.enabled_stream_buffers_mask = shader_with_so->enabled_streamout_buffer_mask;
2856 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2857 }
2858
2859 static void si_update_clip_regs(struct si_context *sctx, struct si_shader_selector *old_hw_vs,
2860 struct si_shader *old_hw_vs_variant,
2861 struct si_shader_selector *next_hw_vs,
2862 struct si_shader *next_hw_vs_variant)
2863 {
2864 if (next_hw_vs &&
2865 (!old_hw_vs ||
2866 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2867 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2868 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2869 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2870 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask || !old_hw_vs_variant ||
2871 !next_hw_vs_variant ||
2872 old_hw_vs_variant->key.opt.clip_disable != next_hw_vs_variant->key.opt.clip_disable))
2873 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2874 }
2875
2876 static void si_update_common_shader_state(struct si_context *sctx)
2877 {
2878 sctx->uses_bindless_samplers = si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2879 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2880 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2881 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2882 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2883 sctx->uses_bindless_images = si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2884 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2885 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2886 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2887 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2888 sctx->do_update_shaders = true;
2889 }
2890
2891 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2892 {
2893 struct si_context *sctx = (struct si_context *)ctx;
2894 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2895 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2896 struct si_shader_selector *sel = state;
2897
2898 if (sctx->vs_shader.cso == sel)
2899 return;
2900
2901 sctx->vs_shader.cso = sel;
2902 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2903 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
2904
2905 if (si_update_ngg(sctx))
2906 si_shader_change_notify(sctx);
2907
2908 si_update_common_shader_state(sctx);
2909 si_update_vs_viewport_state(sctx);
2910 si_set_active_descriptors_for_shader(sctx, sel);
2911 si_update_streamout_state(sctx);
2912 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso,
2913 si_get_vs_state(sctx));
2914 }
2915
2916 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2917 {
2918 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2919 (sctx->tes_shader.cso && sctx->tes_shader.cso->info.uses_primid) ||
2920 (sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
2921 (sctx->gs_shader.cso && sctx->gs_shader.cso->info.uses_primid) ||
2922 (sctx->ps_shader.cso && !sctx->gs_shader.cso && sctx->ps_shader.cso->info.uses_primid);
2923 }
2924
2925 bool si_update_ngg(struct si_context *sctx)
2926 {
2927 if (!sctx->screen->use_ngg) {
2928 assert(!sctx->ngg);
2929 return false;
2930 }
2931
2932 bool new_ngg = true;
2933
2934 if (sctx->gs_shader.cso && sctx->tes_shader.cso && sctx->gs_shader.cso->tess_turns_off_ngg) {
2935 new_ngg = false;
2936 } else if (!sctx->screen->use_ngg_streamout) {
2937 struct si_shader_selector *last = si_get_vs(sctx)->cso;
2938
2939 if ((last && last->so.num_outputs) || sctx->streamout.prims_gen_query_enabled)
2940 new_ngg = false;
2941 }
2942
2943 if (new_ngg != sctx->ngg) {
2944 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
2945 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
2946 * pointers are set.
2947 */
2948 if (sctx->chip_class == GFX10 && !new_ngg)
2949 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
2950
2951 sctx->ngg = new_ngg;
2952 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
2953 return true;
2954 }
2955 return false;
2956 }
2957
2958 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2959 {
2960 struct si_context *sctx = (struct si_context *)ctx;
2961 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2962 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2963 struct si_shader_selector *sel = state;
2964 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2965 bool ngg_changed;
2966
2967 if (sctx->gs_shader.cso == sel)
2968 return;
2969
2970 sctx->gs_shader.cso = sel;
2971 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2972 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2973
2974 si_update_common_shader_state(sctx);
2975 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
2976
2977 ngg_changed = si_update_ngg(sctx);
2978 if (ngg_changed || enable_changed)
2979 si_shader_change_notify(sctx);
2980 if (enable_changed) {
2981 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2982 si_update_tess_uses_prim_id(sctx);
2983 }
2984 si_update_vs_viewport_state(sctx);
2985 si_set_active_descriptors_for_shader(sctx, sel);
2986 si_update_streamout_state(sctx);
2987 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso,
2988 si_get_vs_state(sctx));
2989 }
2990
2991 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
2992 {
2993 struct si_context *sctx = (struct si_context *)ctx;
2994 struct si_shader_selector *sel = state;
2995 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
2996
2997 if (sctx->tcs_shader.cso == sel)
2998 return;
2999
3000 sctx->tcs_shader.cso = sel;
3001 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3002 si_update_tess_uses_prim_id(sctx);
3003
3004 si_update_common_shader_state(sctx);
3005
3006 if (enable_changed)
3007 sctx->last_tcs = NULL; /* invalidate derived tess state */
3008
3009 si_set_active_descriptors_for_shader(sctx, sel);
3010 }
3011
3012 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3013 {
3014 struct si_context *sctx = (struct si_context *)ctx;
3015 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3016 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3017 struct si_shader_selector *sel = state;
3018 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3019
3020 if (sctx->tes_shader.cso == sel)
3021 return;
3022
3023 sctx->tes_shader.cso = sel;
3024 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3025 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3026 si_update_tess_uses_prim_id(sctx);
3027
3028 si_update_common_shader_state(sctx);
3029 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3030
3031 bool ngg_changed = si_update_ngg(sctx);
3032 if (ngg_changed || enable_changed)
3033 si_shader_change_notify(sctx);
3034 if (enable_changed)
3035 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3036 si_update_vs_viewport_state(sctx);
3037 si_set_active_descriptors_for_shader(sctx, sel);
3038 si_update_streamout_state(sctx);
3039 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso,
3040 si_get_vs_state(sctx));
3041 }
3042
3043 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3044 {
3045 struct si_context *sctx = (struct si_context *)ctx;
3046 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3047 struct si_shader_selector *sel = state;
3048
3049 /* skip if supplied shader is one already in use */
3050 if (old_sel == sel)
3051 return;
3052
3053 sctx->ps_shader.cso = sel;
3054 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3055
3056 si_update_common_shader_state(sctx);
3057 if (sel) {
3058 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3059 si_update_tess_uses_prim_id(sctx);
3060
3061 if (!old_sel || old_sel->info.colors_written != sel->info.colors_written)
3062 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3063
3064 if (sctx->screen->has_out_of_order_rast &&
3065 (!old_sel || old_sel->info.writes_memory != sel->info.writes_memory ||
3066 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3067 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3068 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3069 }
3070 si_set_active_descriptors_for_shader(sctx, sel);
3071 si_update_ps_colorbuf0_slot(sctx);
3072 }
3073
3074 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3075 {
3076 if (shader->is_optimized) {
3077 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority, &shader->ready);
3078 }
3079
3080 util_queue_fence_destroy(&shader->ready);
3081
3082 if (shader->pm4) {
3083 /* If destroyed shaders were not unbound, the next compiled
3084 * shader variant could get the same pointer address and so
3085 * binding it to the same shader stage would be considered
3086 * a no-op, causing random behavior.
3087 */
3088 switch (shader->selector->type) {
3089 case PIPE_SHADER_VERTEX:
3090 if (shader->key.as_ls) {
3091 assert(sctx->chip_class <= GFX8);
3092 si_pm4_delete_state(sctx, ls, shader->pm4);
3093 } else if (shader->key.as_es) {
3094 assert(sctx->chip_class <= GFX8);
3095 si_pm4_delete_state(sctx, es, shader->pm4);
3096 } else if (shader->key.as_ngg) {
3097 si_pm4_delete_state(sctx, gs, shader->pm4);
3098 } else {
3099 si_pm4_delete_state(sctx, vs, shader->pm4);
3100 }
3101 break;
3102 case PIPE_SHADER_TESS_CTRL:
3103 si_pm4_delete_state(sctx, hs, shader->pm4);
3104 break;
3105 case PIPE_SHADER_TESS_EVAL:
3106 if (shader->key.as_es) {
3107 assert(sctx->chip_class <= GFX8);
3108 si_pm4_delete_state(sctx, es, shader->pm4);
3109 } else if (shader->key.as_ngg) {
3110 si_pm4_delete_state(sctx, gs, shader->pm4);
3111 } else {
3112 si_pm4_delete_state(sctx, vs, shader->pm4);
3113 }
3114 break;
3115 case PIPE_SHADER_GEOMETRY:
3116 if (shader->is_gs_copy_shader)
3117 si_pm4_delete_state(sctx, vs, shader->pm4);
3118 else
3119 si_pm4_delete_state(sctx, gs, shader->pm4);
3120 break;
3121 case PIPE_SHADER_FRAGMENT:
3122 si_pm4_delete_state(sctx, ps, shader->pm4);
3123 break;
3124 default:;
3125 }
3126 }
3127
3128 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3129 si_shader_destroy(shader);
3130 free(shader);
3131 }
3132
3133 static void si_destroy_shader_selector(struct pipe_context *ctx, void *cso)
3134 {
3135 struct si_context *sctx = (struct si_context *)ctx;
3136 struct si_shader_selector *sel = (struct si_shader_selector *)cso;
3137 struct si_shader *p = sel->first_variant, *c;
3138 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3139 [PIPE_SHADER_VERTEX] = &sctx->vs_shader, [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3140 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader, [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3141 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3142 };
3143
3144 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3145
3146 if (current_shader[sel->type]->cso == sel) {
3147 current_shader[sel->type]->cso = NULL;
3148 current_shader[sel->type]->current = NULL;
3149 }
3150
3151 while (p) {
3152 c = p->next_variant;
3153 si_delete_shader(sctx, p);
3154 p = c;
3155 }
3156
3157 if (sel->main_shader_part)
3158 si_delete_shader(sctx, sel->main_shader_part);
3159 if (sel->main_shader_part_ls)
3160 si_delete_shader(sctx, sel->main_shader_part_ls);
3161 if (sel->main_shader_part_es)
3162 si_delete_shader(sctx, sel->main_shader_part_es);
3163 if (sel->main_shader_part_ngg)
3164 si_delete_shader(sctx, sel->main_shader_part_ngg);
3165 if (sel->gs_copy_shader)
3166 si_delete_shader(sctx, sel->gs_copy_shader);
3167
3168 util_queue_fence_destroy(&sel->ready);
3169 simple_mtx_destroy(&sel->mutex);
3170 ralloc_free(sel->nir);
3171 free(sel->nir_binary);
3172 free(sel);
3173 }
3174
3175 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3176 {
3177 struct si_context *sctx = (struct si_context *)ctx;
3178 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3179
3180 si_shader_selector_reference(sctx, &sel, NULL);
3181 }
3182
3183 static unsigned si_get_ps_input_cntl(struct si_context *sctx, struct si_shader *vs, unsigned name,
3184 unsigned index, unsigned interpolate)
3185 {
3186 struct si_shader_info *vsinfo = &vs->selector->info;
3187 unsigned j, offset, ps_input_cntl = 0;
3188
3189 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3190 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) || name == TGSI_SEMANTIC_PRIMID)
3191 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3192
3193 if (name == TGSI_SEMANTIC_PCOORD ||
3194 (name == TGSI_SEMANTIC_TEXCOORD && sctx->sprite_coord_enable & (1 << index))) {
3195 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3196 }
3197
3198 for (j = 0; j < vsinfo->num_outputs; j++) {
3199 if (name == vsinfo->output_semantic_name[j] && index == vsinfo->output_semantic_index[j]) {
3200 offset = vs->info.vs_output_param_offset[j];
3201
3202 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3203 /* The input is loaded from parameter memory. */
3204 ps_input_cntl |= S_028644_OFFSET(offset);
3205 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3206 if (offset == AC_EXP_PARAM_UNDEFINED) {
3207 /* This can happen with depth-only rendering. */
3208 offset = 0;
3209 } else {
3210 /* The input is a DEFAULT_VAL constant. */
3211 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3212 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3213 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3214 }
3215
3216 ps_input_cntl = S_028644_OFFSET(0x20) | S_028644_DEFAULT_VAL(offset);
3217 }
3218 break;
3219 }
3220 }
3221
3222 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3223 /* PrimID is written after the last output when HW VS is used. */
3224 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3225 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3226 /* No corresponding output found, load defaults into input.
3227 * Don't set any other bits.
3228 * (FLAT_SHADE=1 completely changes behavior) */
3229 ps_input_cntl = S_028644_OFFSET(0x20);
3230 /* D3D 9 behaviour. GL is undefined */
3231 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3232 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3233 }
3234 return ps_input_cntl;
3235 }
3236
3237 static void si_emit_spi_map(struct si_context *sctx)
3238 {
3239 struct si_shader *ps = sctx->ps_shader.current;
3240 struct si_shader *vs = si_get_vs_state(sctx);
3241 struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3242 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3243 unsigned spi_ps_input_cntl[32];
3244
3245 if (!ps || !ps->selector->info.num_inputs)
3246 return;
3247
3248 num_interp = si_get_ps_num_interp(ps);
3249 assert(num_interp > 0);
3250
3251 for (i = 0; i < psinfo->num_inputs; i++) {
3252 unsigned name = psinfo->input_semantic_name[i];
3253 unsigned index = psinfo->input_semantic_index[i];
3254 unsigned interpolate = psinfo->input_interpolate[i];
3255
3256 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name, index, interpolate);
3257
3258 if (name == TGSI_SEMANTIC_COLOR) {
3259 assert(index < ARRAY_SIZE(bcol_interp));
3260 bcol_interp[index] = interpolate;
3261 }
3262 }
3263
3264 if (ps->key.part.ps.prolog.color_two_side) {
3265 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3266
3267 for (i = 0; i < 2; i++) {
3268 if (!(psinfo->colors_read & (0xf << (i * 4))))
3269 continue;
3270
3271 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3272 }
3273 }
3274 assert(num_interp == num_written);
3275
3276 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3277 /* Dota 2: Only ~16% of SPI map updates set different values. */
3278 /* Talos: Only ~9% of SPI map updates set different values. */
3279 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3280 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
3281 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3282
3283 if (initial_cdw != sctx->gfx_cs->current.cdw)
3284 sctx->context_roll = true;
3285 }
3286
3287 /**
3288 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3289 */
3290 static void si_cs_preamble_add_vgt_flush(struct si_context *sctx)
3291 {
3292 if (sctx->cs_preamble_has_vgt_flush)
3293 return;
3294
3295 /* Done by Vulkan before VGT_FLUSH. */
3296 si_pm4_cmd_add(sctx->cs_preamble_state, PKT3(PKT3_EVENT_WRITE, 0, 0));
3297 si_pm4_cmd_add(sctx->cs_preamble_state, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3298
3299 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3300 si_pm4_cmd_add(sctx->cs_preamble_state, PKT3(PKT3_EVENT_WRITE, 0, 0));
3301 si_pm4_cmd_add(sctx->cs_preamble_state, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3302 sctx->cs_preamble_has_vgt_flush = true;
3303 }
3304
3305 /* Initialize state related to ESGS / GSVS ring buffers */
3306 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3307 {
3308 struct si_shader_selector *es =
3309 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3310 struct si_shader_selector *gs = sctx->gs_shader.cso;
3311 struct si_pm4_state *pm4;
3312
3313 /* Chip constants. */
3314 unsigned num_se = sctx->screen->info.max_se;
3315 unsigned wave_size = 64;
3316 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3317 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3318 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3319 */
3320 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3321 unsigned alignment = 256 * num_se;
3322 /* The maximum size is 63.999 MB per SE. */
3323 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3324
3325 /* Calculate the minimum size. */
3326 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse * wave_size, alignment);
3327
3328 /* These are recommended sizes, not minimum sizes. */
3329 unsigned esgs_ring_size =
3330 max_gs_waves * 2 * wave_size * es->esgs_itemsize * gs->gs_input_verts_per_prim;
3331 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * gs->max_gsvs_emit_size;
3332
3333 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3334 esgs_ring_size = align(esgs_ring_size, alignment);
3335 gsvs_ring_size = align(gsvs_ring_size, alignment);
3336
3337 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3338 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3339
3340 /* Some rings don't have to be allocated if shaders don't use them.
3341 * (e.g. no varyings between ES and GS or GS and VS)
3342 *
3343 * GFX9 doesn't have the ESGS ring.
3344 */
3345 bool update_esgs = sctx->chip_class <= GFX8 && esgs_ring_size &&
3346 (!sctx->esgs_ring || sctx->esgs_ring->width0 < esgs_ring_size);
3347 bool update_gsvs =
3348 gsvs_ring_size && (!sctx->gsvs_ring || sctx->gsvs_ring->width0 < gsvs_ring_size);
3349
3350 if (!update_esgs && !update_gsvs)
3351 return true;
3352
3353 if (update_esgs) {
3354 pipe_resource_reference(&sctx->esgs_ring, NULL);
3355 sctx->esgs_ring =
3356 pipe_aligned_buffer_create(sctx->b.screen, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
3357 esgs_ring_size, sctx->screen->info.pte_fragment_size);
3358 if (!sctx->esgs_ring)
3359 return false;
3360 }
3361
3362 if (update_gsvs) {
3363 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3364 sctx->gsvs_ring =
3365 pipe_aligned_buffer_create(sctx->b.screen, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
3366 gsvs_ring_size, sctx->screen->info.pte_fragment_size);
3367 if (!sctx->gsvs_ring)
3368 return false;
3369 }
3370
3371 /* Create the "cs_preamble_gs_rings" state. */
3372 pm4 = CALLOC_STRUCT(si_pm4_state);
3373 if (!pm4)
3374 return false;
3375
3376 if (sctx->chip_class >= GFX7) {
3377 if (sctx->esgs_ring) {
3378 assert(sctx->chip_class <= GFX8);
3379 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE, sctx->esgs_ring->width0 / 256);
3380 }
3381 if (sctx->gsvs_ring)
3382 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE, sctx->gsvs_ring->width0 / 256);
3383 } else {
3384 if (sctx->esgs_ring)
3385 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE, sctx->esgs_ring->width0 / 256);
3386 if (sctx->gsvs_ring)
3387 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE, sctx->gsvs_ring->width0 / 256);
3388 }
3389
3390 /* Set the state. */
3391 if (sctx->cs_preamble_gs_rings)
3392 si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0);
3393 sctx->cs_preamble_gs_rings = pm4;
3394
3395 if (!sctx->cs_preamble_has_vgt_flush) {
3396 si_cs_preamble_add_vgt_flush(sctx);
3397 }
3398
3399 /* Flush the context to re-emit both cs_preamble states. */
3400 sctx->initial_gfx_cs_size = 0; /* force flush */
3401 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3402
3403 /* Set ring bindings. */
3404 if (sctx->esgs_ring) {
3405 assert(sctx->chip_class <= GFX8);
3406 si_set_ring_buffer(sctx, SI_ES_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, true,
3407 true, 4, 64, 0);
3408 si_set_ring_buffer(sctx, SI_GS_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false,
3409 false, 0, 0, 0);
3410 }
3411 if (sctx->gsvs_ring) {
3412 si_set_ring_buffer(sctx, SI_RING_GSVS, sctx->gsvs_ring, 0, sctx->gsvs_ring->width0, false,
3413 false, 0, 0, 0);
3414 }
3415
3416 return true;
3417 }
3418
3419 static void si_shader_lock(struct si_shader *shader)
3420 {
3421 simple_mtx_lock(&shader->selector->mutex);
3422 if (shader->previous_stage_sel) {
3423 assert(shader->previous_stage_sel != shader->selector);
3424 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3425 }
3426 }
3427
3428 static void si_shader_unlock(struct si_shader *shader)
3429 {
3430 if (shader->previous_stage_sel)
3431 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3432 simple_mtx_unlock(&shader->selector->mutex);
3433 }
3434
3435 /**
3436 * @returns 1 if \p sel has been updated to use a new scratch buffer
3437 * 0 if not
3438 * < 0 if there was a failure
3439 */
3440 static int si_update_scratch_buffer(struct si_context *sctx, struct si_shader *shader)
3441 {
3442 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3443
3444 if (!shader)
3445 return 0;
3446
3447 /* This shader doesn't need a scratch buffer */
3448 if (shader->config.scratch_bytes_per_wave == 0)
3449 return 0;
3450
3451 /* Prevent race conditions when updating:
3452 * - si_shader::scratch_bo
3453 * - si_shader::binary::code
3454 * - si_shader::previous_stage::binary::code.
3455 */
3456 si_shader_lock(shader);
3457
3458 /* This shader is already configured to use the current
3459 * scratch buffer. */
3460 if (shader->scratch_bo == sctx->scratch_buffer) {
3461 si_shader_unlock(shader);
3462 return 0;
3463 }
3464
3465 assert(sctx->scratch_buffer);
3466
3467 /* Replace the shader bo with a new bo that has the relocs applied. */
3468 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3469 si_shader_unlock(shader);
3470 return -1;
3471 }
3472
3473 /* Update the shader state to use the new shader bo. */
3474 si_shader_init_pm4_state(sctx->screen, shader);
3475
3476 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3477
3478 si_shader_unlock(shader);
3479 return 1;
3480 }
3481
3482 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3483 {
3484 return shader ? shader->config.scratch_bytes_per_wave : 0;
3485 }
3486
3487 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3488 {
3489 if (!sctx->tes_shader.cso)
3490 return NULL; /* tessellation disabled */
3491
3492 return sctx->tcs_shader.cso ? sctx->tcs_shader.current : sctx->fixed_func_tcs_shader.current;
3493 }
3494
3495 static bool si_update_scratch_relocs(struct si_context *sctx)
3496 {
3497 struct si_shader *tcs = si_get_tcs_current(sctx);
3498 int r;
3499
3500 /* Update the shaders, so that they are using the latest scratch.
3501 * The scratch buffer may have been changed since these shaders were
3502 * last used, so we still need to try to update them, even if they
3503 * require scratch buffers smaller than the current size.
3504 */
3505 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3506 if (r < 0)
3507 return false;
3508 if (r == 1)
3509 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3510
3511 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3512 if (r < 0)
3513 return false;
3514 if (r == 1)
3515 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3516
3517 r = si_update_scratch_buffer(sctx, tcs);
3518 if (r < 0)
3519 return false;
3520 if (r == 1)
3521 si_pm4_bind_state(sctx, hs, tcs->pm4);
3522
3523 /* VS can be bound as LS, ES, or VS. */
3524 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3525 if (r < 0)
3526 return false;
3527 if (r == 1) {
3528 if (sctx->vs_shader.current->key.as_ls)
3529 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3530 else if (sctx->vs_shader.current->key.as_es)
3531 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3532 else if (sctx->vs_shader.current->key.as_ngg)
3533 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3534 else
3535 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3536 }
3537
3538 /* TES can be bound as ES or VS. */
3539 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3540 if (r < 0)
3541 return false;
3542 if (r == 1) {
3543 if (sctx->tes_shader.current->key.as_es)
3544 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3545 else if (sctx->tes_shader.current->key.as_ngg)
3546 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3547 else
3548 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3549 }
3550
3551 return true;
3552 }
3553
3554 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3555 {
3556 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3557 * There are 2 cases to handle:
3558 *
3559 * - If the current needed size is less than the maximum seen size,
3560 * use the maximum seen size, so that WAVESIZE remains the same.
3561 *
3562 * - If the current needed size is greater than the maximum seen size,
3563 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3564 *
3565 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3566 * Otherwise, the number of waves that can use scratch is
3567 * SPI_TMPRING_SIZE.WAVES.
3568 */
3569 unsigned bytes = 0;
3570
3571 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3572 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3573 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3574
3575 if (sctx->tes_shader.cso) {
3576 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3577 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3578 }
3579
3580 sctx->max_seen_scratch_bytes_per_wave = MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3581
3582 unsigned scratch_needed_size = sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3583 unsigned spi_tmpring_size;
3584
3585 if (scratch_needed_size > 0) {
3586 if (!sctx->scratch_buffer || scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3587 /* Create a bigger scratch buffer */
3588 si_resource_reference(&sctx->scratch_buffer, NULL);
3589
3590 sctx->scratch_buffer = si_aligned_buffer_create(
3591 &sctx->screen->b, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT, scratch_needed_size,
3592 sctx->screen->info.pte_fragment_size);
3593 if (!sctx->scratch_buffer)
3594 return false;
3595
3596 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3597 si_context_add_resource_size(sctx, &sctx->scratch_buffer->b.b);
3598 }
3599
3600 if (!si_update_scratch_relocs(sctx))
3601 return false;
3602 }
3603
3604 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3605 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3606 "scratch size should already be aligned correctly.");
3607
3608 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3609 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3610 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3611 sctx->spi_tmpring_size = spi_tmpring_size;
3612 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3613 }
3614 return true;
3615 }
3616
3617 static void si_init_tess_factor_ring(struct si_context *sctx)
3618 {
3619 assert(!sctx->tess_rings);
3620 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3621
3622 /* The address must be aligned to 2^19, because the shader only
3623 * receives the high 13 bits.
3624 */
3625 sctx->tess_rings = pipe_aligned_buffer_create(
3626 sctx->b.screen, SI_RESOURCE_FLAG_32BIT, PIPE_USAGE_DEFAULT,
3627 sctx->screen->tess_offchip_ring_size + sctx->screen->tess_factor_ring_size, 1 << 19);
3628 if (!sctx->tess_rings)
3629 return;
3630
3631 si_cs_preamble_add_vgt_flush(sctx);
3632
3633 uint64_t factor_va =
3634 si_resource(sctx->tess_rings)->gpu_address + sctx->screen->tess_offchip_ring_size;
3635
3636 /* Append these registers to the init config state. */
3637 if (sctx->chip_class >= GFX7) {
3638 si_pm4_set_reg(sctx->cs_preamble_state, R_030938_VGT_TF_RING_SIZE,
3639 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3640 si_pm4_set_reg(sctx->cs_preamble_state, R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8);
3641 if (sctx->chip_class >= GFX10)
3642 si_pm4_set_reg(sctx->cs_preamble_state, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3643 S_030984_BASE_HI(factor_va >> 40));
3644 else if (sctx->chip_class == GFX9)
3645 si_pm4_set_reg(sctx->cs_preamble_state, R_030944_VGT_TF_MEMORY_BASE_HI,
3646 S_030944_BASE_HI(factor_va >> 40));
3647 si_pm4_set_reg(sctx->cs_preamble_state, R_03093C_VGT_HS_OFFCHIP_PARAM,
3648 sctx->screen->vgt_hs_offchip_param);
3649 } else {
3650 si_pm4_set_reg(sctx->cs_preamble_state, R_008988_VGT_TF_RING_SIZE,
3651 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3652 si_pm4_set_reg(sctx->cs_preamble_state, R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8);
3653 si_pm4_set_reg(sctx->cs_preamble_state, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3654 sctx->screen->vgt_hs_offchip_param);
3655 }
3656
3657 /* Flush the context to re-emit the cs_preamble state.
3658 * This is done only once in a lifetime of a context.
3659 */
3660 sctx->initial_gfx_cs_size = 0; /* force flush */
3661 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3662 }
3663
3664 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3665 union si_vgt_stages_key key)
3666 {
3667 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3668 uint32_t stages = 0;
3669
3670 if (key.u.tess) {
3671 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) | S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3672
3673 if (key.u.gs)
3674 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) | S_028B54_GS_EN(1);
3675 else if (key.u.ngg)
3676 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3677 else
3678 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3679 } else if (key.u.gs) {
3680 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) | S_028B54_GS_EN(1);
3681 } else if (key.u.ngg) {
3682 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3683 }
3684
3685 if (key.u.ngg) {
3686 stages |= S_028B54_PRIMGEN_EN(1) | S_028B54_GS_FAST_LAUNCH(key.u.ngg_gs_fast_launch) |
3687 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3688 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3689 } else if (key.u.gs)
3690 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3691
3692 if (screen->info.chip_class >= GFX9)
3693 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3694
3695 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3696 stages |= S_028B54_HS_W32_EN(1) |
3697 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3698 S_028B54_VS_W32_EN(1);
3699 }
3700
3701 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3702 return pm4;
3703 }
3704
3705 static void si_update_vgt_shader_config(struct si_context *sctx, union si_vgt_stages_key key)
3706 {
3707 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3708
3709 if (unlikely(!*pm4))
3710 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3711 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3712 }
3713
3714 bool si_update_shaders(struct si_context *sctx)
3715 {
3716 struct pipe_context *ctx = (struct pipe_context *)sctx;
3717 struct si_compiler_ctx_state compiler_state;
3718 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3719 struct si_shader *old_vs = si_get_vs_state(sctx);
3720 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3721 struct si_shader *old_ps = sctx->ps_shader.current;
3722 union si_vgt_stages_key key;
3723 unsigned old_spi_shader_col_format =
3724 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3725 int r;
3726
3727 if (!sctx->compiler.passes)
3728 si_init_compiler(sctx->screen, &sctx->compiler);
3729
3730 compiler_state.compiler = &sctx->compiler;
3731 compiler_state.debug = sctx->debug;
3732 compiler_state.is_debug_context = sctx->is_debug;
3733
3734 key.index = 0;
3735
3736 if (sctx->tes_shader.cso)
3737 key.u.tess = 1;
3738 if (sctx->gs_shader.cso)
3739 key.u.gs = 1;
3740
3741 if (sctx->ngg) {
3742 key.u.ngg = 1;
3743 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3744 }
3745
3746 /* Update TCS and TES. */
3747 if (sctx->tes_shader.cso) {
3748 if (!sctx->tess_rings) {
3749 si_init_tess_factor_ring(sctx);
3750 if (!sctx->tess_rings)
3751 return false;
3752 }
3753
3754 if (sctx->tcs_shader.cso) {
3755 r = si_shader_select(ctx, &sctx->tcs_shader, key, &compiler_state);
3756 if (r)
3757 return false;
3758 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3759 } else {
3760 if (!sctx->fixed_func_tcs_shader.cso) {
3761 sctx->fixed_func_tcs_shader.cso = si_create_fixed_func_tcs(sctx);
3762 if (!sctx->fixed_func_tcs_shader.cso)
3763 return false;
3764 }
3765
3766 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader, key, &compiler_state);
3767 if (r)
3768 return false;
3769 si_pm4_bind_state(sctx, hs, sctx->fixed_func_tcs_shader.current->pm4);
3770 }
3771
3772 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3773 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3774 if (r)
3775 return false;
3776
3777 if (sctx->gs_shader.cso) {
3778 /* TES as ES */
3779 assert(sctx->chip_class <= GFX8);
3780 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3781 } else if (key.u.ngg) {
3782 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3783 } else {
3784 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3785 }
3786 }
3787 } else {
3788 if (sctx->chip_class <= GFX8)
3789 si_pm4_bind_state(sctx, ls, NULL);
3790 si_pm4_bind_state(sctx, hs, NULL);
3791 }
3792
3793 /* Update GS. */
3794 if (sctx->gs_shader.cso) {
3795 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3796 if (r)
3797 return false;
3798 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3799 if (!key.u.ngg) {
3800 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3801
3802 if (!si_update_gs_ring_buffers(sctx))
3803 return false;
3804 } else {
3805 si_pm4_bind_state(sctx, vs, NULL);
3806 }
3807 } else {
3808 if (!key.u.ngg) {
3809 si_pm4_bind_state(sctx, gs, NULL);
3810 if (sctx->chip_class <= GFX8)
3811 si_pm4_bind_state(sctx, es, NULL);
3812 }
3813 }
3814
3815 /* Update VS. */
3816 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3817 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3818 if (r)
3819 return false;
3820
3821 if (!key.u.tess && !key.u.gs) {
3822 if (key.u.ngg) {
3823 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3824 si_pm4_bind_state(sctx, vs, NULL);
3825 } else {
3826 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3827 }
3828 } else if (sctx->tes_shader.cso) {
3829 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3830 } else {
3831 assert(sctx->gs_shader.cso);
3832 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3833 }
3834 }
3835
3836 /* This must be done after the shader variant is selected. */
3837 if (sctx->ngg) {
3838 struct si_shader *vs = si_get_vs(sctx)->current;
3839
3840 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(vs);
3841 key.u.ngg_gs_fast_launch = !!(vs->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL);
3842 }
3843
3844 si_update_vgt_shader_config(sctx, key);
3845
3846 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3847 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3848
3849 if (sctx->ps_shader.cso) {
3850 unsigned db_shader_control;
3851
3852 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3853 if (r)
3854 return false;
3855 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3856
3857 db_shader_control = sctx->ps_shader.cso->db_shader_control |
3858 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3859
3860 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3861 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3862 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3863 sctx->flatshade != rs->flatshade) {
3864 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3865 sctx->flatshade = rs->flatshade;
3866 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3867 }
3868
3869 if (sctx->screen->info.rbplus_allowed && si_pm4_state_changed(sctx, ps) &&
3870 (!old_ps || old_spi_shader_col_format !=
3871 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3872 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3873
3874 if (sctx->ps_db_shader_control != db_shader_control) {
3875 sctx->ps_db_shader_control = db_shader_control;
3876 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3877 if (sctx->screen->dpbb_allowed)
3878 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3879 }
3880
3881 if (sctx->smoothing_enabled !=
3882 sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3883 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3884 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3885
3886 if (sctx->chip_class == GFX6)
3887 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3888
3889 if (sctx->framebuffer.nr_samples <= 1)
3890 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3891 }
3892 }
3893
3894 if (si_pm4_state_enabled_and_changed(sctx, ls) || si_pm4_state_enabled_and_changed(sctx, hs) ||
3895 si_pm4_state_enabled_and_changed(sctx, es) || si_pm4_state_enabled_and_changed(sctx, gs) ||
3896 si_pm4_state_enabled_and_changed(sctx, vs) || si_pm4_state_enabled_and_changed(sctx, ps)) {
3897 if (!si_update_spi_tmpring_size(sctx))
3898 return false;
3899 }
3900
3901 if (sctx->chip_class >= GFX7) {
3902 if (si_pm4_state_enabled_and_changed(sctx, ls))
3903 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3904 else if (!sctx->queued.named.ls)
3905 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3906
3907 if (si_pm4_state_enabled_and_changed(sctx, hs))
3908 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3909 else if (!sctx->queued.named.hs)
3910 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3911
3912 if (si_pm4_state_enabled_and_changed(sctx, es))
3913 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3914 else if (!sctx->queued.named.es)
3915 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3916
3917 if (si_pm4_state_enabled_and_changed(sctx, gs))
3918 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3919 else if (!sctx->queued.named.gs)
3920 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3921
3922 if (si_pm4_state_enabled_and_changed(sctx, vs))
3923 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3924 else if (!sctx->queued.named.vs)
3925 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
3926
3927 if (si_pm4_state_enabled_and_changed(sctx, ps))
3928 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
3929 else if (!sctx->queued.named.ps)
3930 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
3931 }
3932
3933 sctx->do_update_shaders = false;
3934 return true;
3935 }
3936
3937 static void si_emit_scratch_state(struct si_context *sctx)
3938 {
3939 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3940
3941 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size);
3942
3943 if (sctx->scratch_buffer) {
3944 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->scratch_buffer, RADEON_USAGE_READWRITE,
3945 RADEON_PRIO_SCRATCH_BUFFER);
3946 }
3947 }
3948
3949 void si_init_screen_live_shader_cache(struct si_screen *sscreen)
3950 {
3951 util_live_shader_cache_init(&sscreen->live_shader_cache, si_create_shader_selector,
3952 si_destroy_shader_selector);
3953 }
3954
3955 void si_init_shader_functions(struct si_context *sctx)
3956 {
3957 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
3958 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
3959
3960 sctx->b.create_vs_state = si_create_shader;
3961 sctx->b.create_tcs_state = si_create_shader;
3962 sctx->b.create_tes_state = si_create_shader;
3963 sctx->b.create_gs_state = si_create_shader;
3964 sctx->b.create_fs_state = si_create_shader;
3965
3966 sctx->b.bind_vs_state = si_bind_vs_shader;
3967 sctx->b.bind_tcs_state = si_bind_tcs_shader;
3968 sctx->b.bind_tes_state = si_bind_tes_shader;
3969 sctx->b.bind_gs_state = si_bind_gs_shader;
3970 sctx->b.bind_fs_state = si_bind_ps_shader;
3971
3972 sctx->b.delete_vs_state = si_delete_shader_selector;
3973 sctx->b.delete_tcs_state = si_delete_shader_selector;
3974 sctx->b.delete_tes_state = si_delete_shader_selector;
3975 sctx->b.delete_gs_state = si_delete_shader_selector;
3976 sctx->b.delete_fs_state = si_delete_shader_selector;
3977 }