2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "ac_exp_param.h"
26 #include "ac_shader_util.h"
27 #include "compiler/nir/nir_serialize.h"
28 #include "nir/tgsi_to_nir.h"
29 #include "si_build_pm4.h"
31 #include "util/crc32.h"
32 #include "util/disk_cache.h"
33 #include "util/hash_table.h"
34 #include "util/mesa-sha1.h"
35 #include "util/u_async_debug.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38 #include "tgsi/tgsi_from_mesa.h"
43 * Return the IR key for the shader cache.
45 void si_get_ir_cache_key(struct si_shader_selector
*sel
, bool ngg
, bool es
,
46 unsigned char ir_sha1_cache_key
[20])
48 struct blob blob
= {};
52 if (sel
->nir_binary
) {
53 ir_binary
= sel
->nir_binary
;
54 ir_size
= sel
->nir_size
;
59 nir_serialize(&blob
, sel
->nir
, true);
60 ir_binary
= blob
.data
;
64 /* These settings affect the compilation, but they are not derived
65 * from the input shader IR.
67 unsigned shader_variant_flags
= 0;
70 shader_variant_flags
|= 1 << 0;
72 shader_variant_flags
|= 1 << 1;
73 if (si_get_wave_size(sel
->screen
, sel
->info
.stage
, ngg
, es
, false, false) == 32)
74 shader_variant_flags
|= 1 << 2;
75 if (sel
->info
.stage
== MESA_SHADER_FRAGMENT
&&
76 /* Derivatives imply helper invocations so check for needs_helper_invocations. */
77 sel
->info
.base
.fs
.needs_helper_invocations
&&
78 sel
->info
.base
.fs
.uses_discard
&&
79 sel
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
))
80 shader_variant_flags
|= 1 << 3;
82 /* This varies depending on whether compute-based culling is enabled. */
83 shader_variant_flags
|= sel
->screen
->num_vbos_in_user_sgprs
<< 4;
86 _mesa_sha1_init(&ctx
);
87 _mesa_sha1_update(&ctx
, &shader_variant_flags
, 4);
88 _mesa_sha1_update(&ctx
, ir_binary
, ir_size
);
89 if (sel
->info
.stage
== MESA_SHADER_VERTEX
|| sel
->info
.stage
== MESA_SHADER_TESS_EVAL
||
90 sel
->info
.stage
== MESA_SHADER_GEOMETRY
)
91 _mesa_sha1_update(&ctx
, &sel
->so
, sizeof(sel
->so
));
92 _mesa_sha1_final(&ctx
, ir_sha1_cache_key
);
94 if (ir_binary
== blob
.data
)
98 /** Copy "data" to "ptr" and return the next dword following copied data. */
99 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
101 /* data may be NULL if size == 0 */
103 memcpy(ptr
, data
, size
);
104 ptr
+= DIV_ROUND_UP(size
, 4);
108 /** Read data from "ptr". Return the next dword following the data. */
109 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
111 memcpy(data
, ptr
, size
);
112 ptr
+= DIV_ROUND_UP(size
, 4);
117 * Write the size as uint followed by the data. Return the next dword
118 * following the copied data.
120 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
123 return write_data(ptr
, data
, size
);
127 * Read the size as uint followed by the data. Return both via parameters.
128 * Return the next dword following the data.
130 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
133 assert(*data
== NULL
);
136 *data
= malloc(*size
);
137 return read_data(ptr
, *data
, *size
);
141 * Return the shader binary in a buffer. The first 4 bytes contain its size
144 static void *si_get_shader_binary(struct si_shader
*shader
)
146 /* There is always a size of data followed by the data itself. */
147 unsigned llvm_ir_size
=
148 shader
->binary
.llvm_ir_string
? strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
150 /* Refuse to allocate overly large buffers and guard against integer
152 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 || llvm_ir_size
> UINT_MAX
/ 4)
155 unsigned size
= 4 + /* total size */
156 4 + /* CRC32 of the data below */
157 align(sizeof(shader
->config
), 4) + align(sizeof(shader
->info
), 4) + 4 +
158 align(shader
->binary
.elf_size
, 4) + 4 + align(llvm_ir_size
, 4);
159 void *buffer
= CALLOC(1, size
);
160 uint32_t *ptr
= (uint32_t *)buffer
;
166 ptr
++; /* CRC32 is calculated at the end. */
168 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
169 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
170 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
171 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
172 assert((char *)ptr
- (char *)buffer
== size
);
175 ptr
= (uint32_t *)buffer
;
177 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
182 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
184 uint32_t *ptr
= (uint32_t *)binary
;
185 uint32_t size
= *ptr
++;
186 uint32_t crc32
= *ptr
++;
190 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
191 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
195 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
196 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
197 ptr
= read_chunk(ptr
, (void **)&shader
->binary
.elf_buffer
, &elf_size
);
198 shader
->binary
.elf_size
= elf_size
;
199 ptr
= read_chunk(ptr
, (void **)&shader
->binary
.llvm_ir_string
, &chunk_size
);
205 * Insert a shader into the cache. It's assumed the shader is not in the cache.
206 * Use si_shader_cache_load_shader before calling this.
208 void si_shader_cache_insert_shader(struct si_screen
*sscreen
, unsigned char ir_sha1_cache_key
[20],
209 struct si_shader
*shader
, bool insert_into_disk_cache
)
212 struct hash_entry
*entry
;
213 uint8_t key
[CACHE_KEY_SIZE
];
215 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
217 return; /* already added */
219 hw_binary
= si_get_shader_binary(shader
);
223 if (_mesa_hash_table_insert(sscreen
->shader_cache
, mem_dup(ir_sha1_cache_key
, 20), hw_binary
) ==
229 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
230 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_sha1_cache_key
, 20, key
);
231 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
, *((uint32_t *)hw_binary
), NULL
);
235 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, unsigned char ir_sha1_cache_key
[20],
236 struct si_shader
*shader
)
238 struct hash_entry
*entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_sha1_cache_key
);
241 if (si_load_shader_binary(shader
, entry
->data
)) {
242 p_atomic_inc(&sscreen
->num_memory_shader_cache_hits
);
246 p_atomic_inc(&sscreen
->num_memory_shader_cache_misses
);
248 if (!sscreen
->disk_shader_cache
)
251 unsigned char sha1
[CACHE_KEY_SIZE
];
252 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_sha1_cache_key
, 20, sha1
);
255 uint8_t *buffer
= disk_cache_get(sscreen
->disk_shader_cache
, sha1
, &binary_size
);
257 if (binary_size
>= sizeof(uint32_t) && *((uint32_t *)buffer
) == binary_size
) {
258 if (si_load_shader_binary(shader
, buffer
)) {
260 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
, shader
, false);
261 p_atomic_inc(&sscreen
->num_disk_shader_cache_hits
);
265 /* Something has gone wrong discard the item from the cache and
266 * rebuild/link from source.
268 assert(!"Invalid radeonsi shader disk cache item!");
269 disk_cache_remove(sscreen
->disk_shader_cache
, sha1
);
274 p_atomic_inc(&sscreen
->num_disk_shader_cache_misses
);
278 static uint32_t si_shader_cache_key_hash(const void *key
)
280 /* Take the first dword of SHA1. */
281 return *(uint32_t *)key
;
284 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
287 return memcmp(a
, b
, 20) == 0;
290 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
292 FREE((void *)entry
->key
);
296 bool si_init_shader_cache(struct si_screen
*sscreen
)
298 (void)simple_mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
299 sscreen
->shader_cache
=
300 _mesa_hash_table_create(NULL
, si_shader_cache_key_hash
, si_shader_cache_key_equals
);
302 return sscreen
->shader_cache
!= NULL
;
305 void si_destroy_shader_cache(struct si_screen
*sscreen
)
307 if (sscreen
->shader_cache
)
308 _mesa_hash_table_destroy(sscreen
->shader_cache
, si_destroy_shader_cache_entry
);
309 simple_mtx_destroy(&sscreen
->shader_cache_mutex
);
314 static void si_set_tesseval_regs(struct si_screen
*sscreen
, const struct si_shader_selector
*tes
,
315 struct si_pm4_state
*pm4
)
317 const struct si_shader_info
*info
= &tes
->info
;
318 unsigned tes_prim_mode
= info
->base
.tess
.primitive_mode
;
319 unsigned tes_spacing
= info
->base
.tess
.spacing
;
320 bool tes_vertex_order_cw
= !info
->base
.tess
.ccw
;
321 bool tes_point_mode
= info
->base
.tess
.point_mode
;
322 unsigned type
, partitioning
, topology
, distribution_mode
;
324 switch (tes_prim_mode
) {
326 type
= V_028B6C_TESS_ISOLINE
;
329 type
= V_028B6C_TESS_TRIANGLE
;
332 type
= V_028B6C_TESS_QUAD
;
339 switch (tes_spacing
) {
340 case TESS_SPACING_FRACTIONAL_ODD
:
341 partitioning
= V_028B6C_PART_FRAC_ODD
;
343 case TESS_SPACING_FRACTIONAL_EVEN
:
344 partitioning
= V_028B6C_PART_FRAC_EVEN
;
346 case TESS_SPACING_EQUAL
:
347 partitioning
= V_028B6C_PART_INTEGER
;
355 topology
= V_028B6C_OUTPUT_POINT
;
356 else if (tes_prim_mode
== GL_LINES
)
357 topology
= V_028B6C_OUTPUT_LINE
;
358 else if (tes_vertex_order_cw
)
359 /* for some reason, this must be the other way around */
360 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
362 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
364 if (sscreen
->info
.has_distributed_tess
) {
365 if (sscreen
->info
.family
== CHIP_FIJI
|| sscreen
->info
.family
>= CHIP_POLARIS10
)
366 distribution_mode
= V_028B6C_TRAPEZOIDS
;
368 distribution_mode
= V_028B6C_DONUTS
;
370 distribution_mode
= V_028B6C_NO_DIST
;
373 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) | S_028B6C_PARTITIONING(partitioning
) |
374 S_028B6C_TOPOLOGY(topology
) |
375 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
378 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
379 * whether the "fractional odd" tessellation spacing is used.
381 * Possible VGT configurations and which state should set the register:
383 * Reg set in | VGT shader configuration | Value
384 * ------------------------------------------------------
386 * VS as ES | ES -> GS -> VS | 30
387 * TES as VS | LS -> HS -> VS | 14 or 30
388 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
390 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
392 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
, struct si_shader_selector
*sel
,
393 struct si_shader
*shader
, struct si_pm4_state
*pm4
)
395 if (sscreen
->info
.family
< CHIP_POLARIS10
|| sscreen
->info
.chip_class
>= GFX10
)
398 /* VS as VS, or VS as ES: */
399 if ((sel
->info
.stage
== MESA_SHADER_VERTEX
&&
400 (!shader
|| (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
401 /* TES as VS, or TES as ES: */
402 sel
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
403 unsigned vtx_reuse_depth
= 30;
405 if (sel
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
406 sel
->info
.base
.tess
.spacing
== TESS_SPACING_FRACTIONAL_ODD
)
407 vtx_reuse_depth
= 14;
410 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
414 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
417 si_pm4_clear_state(shader
->pm4
);
419 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
422 shader
->pm4
->shader
= shader
;
425 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
430 static unsigned si_get_num_vs_user_sgprs(struct si_shader
*shader
,
431 unsigned num_always_on_user_sgprs
)
433 struct si_shader_selector
*vs
=
434 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
435 unsigned num_vbos_in_user_sgprs
= vs
->num_vbos_in_user_sgprs
;
437 /* 1 SGPR is reserved for the vertex buffer pointer. */
438 assert(num_always_on_user_sgprs
<= SI_SGPR_VS_VB_DESCRIPTOR_FIRST
- 1);
440 if (num_vbos_in_user_sgprs
)
441 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST
+ num_vbos_in_user_sgprs
* 4;
443 /* Add the pointer to VBO descriptors. */
444 return num_always_on_user_sgprs
+ 1;
447 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
448 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen
*sscreen
, struct si_shader
*shader
,
449 bool legacy_vs_prim_id
)
451 assert(shader
->selector
->info
.stage
== MESA_SHADER_VERTEX
||
452 (shader
->previous_stage_sel
&& shader
->previous_stage_sel
->info
.stage
== MESA_SHADER_VERTEX
));
454 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
455 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
456 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
457 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or
460 bool is_ls
= shader
->selector
->info
.stage
== MESA_SHADER_TESS_CTRL
|| shader
->key
.as_ls
;
462 if (sscreen
->info
.chip_class
>= GFX10
&& shader
->info
.uses_instanceid
)
464 else if ((is_ls
&& shader
->info
.uses_instanceid
) || legacy_vs_prim_id
)
466 else if (is_ls
|| shader
->info
.uses_instanceid
)
472 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
474 struct si_pm4_state
*pm4
;
477 assert(sscreen
->info
.chip_class
<= GFX8
);
479 pm4
= si_get_shader_pm4_state(shader
);
483 va
= shader
->bo
->gpu_address
;
484 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
485 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
487 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
488 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
489 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false)) |
490 S_00B528_DX10_CLAMP(1) | S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
491 shader
->config
.rsrc2
=
492 S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
)) |
493 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
496 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
498 struct si_pm4_state
*pm4
;
501 pm4
= si_get_shader_pm4_state(shader
);
505 va
= shader
->bo
->gpu_address
;
507 if (sscreen
->info
.chip_class
>= GFX9
) {
508 if (sscreen
->info
.chip_class
>= GFX10
) {
509 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
510 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
512 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
513 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
516 unsigned num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, GFX9_TCS_NUM_USER_SGPR
);
518 shader
->config
.rsrc2
= S_00B42C_USER_SGPR(num_user_sgprs
) |
519 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
521 if (sscreen
->info
.chip_class
>= GFX10
)
522 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
524 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
526 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
527 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
529 shader
->config
.rsrc2
= S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) | S_00B42C_OC_LDS_EN(1) |
530 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
534 pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
535 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) / (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
536 (sscreen
->info
.chip_class
<= GFX9
? S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8)
538 S_00B428_DX10_CLAMP(1) | S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
539 S_00B428_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
540 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
541 S_00B428_LS_VGPR_COMP_CNT(sscreen
->info
.chip_class
>= GFX9
542 ? si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false)
545 if (sscreen
->info
.chip_class
<= GFX8
) {
546 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
, shader
->config
.rsrc2
);
550 static void si_emit_shader_es(struct si_context
*sctx
)
552 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
553 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
558 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
559 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
560 shader
->selector
->esgs_itemsize
/ 4);
562 if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
)
563 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
, SI_TRACKED_VGT_TF_PARAM
,
564 shader
->vgt_tf_param
);
566 if (shader
->vgt_vertex_reuse_block_cntl
)
567 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
568 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
569 shader
->vgt_vertex_reuse_block_cntl
);
571 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
572 sctx
->context_roll
= true;
575 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
577 struct si_pm4_state
*pm4
;
578 unsigned num_user_sgprs
;
579 unsigned vgpr_comp_cnt
;
583 assert(sscreen
->info
.chip_class
<= GFX8
);
585 pm4
= si_get_shader_pm4_state(shader
);
589 pm4
->atom
.emit
= si_emit_shader_es
;
590 va
= shader
->bo
->gpu_address
;
592 if (shader
->selector
->info
.stage
== MESA_SHADER_VERTEX
) {
593 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
594 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
);
595 } else if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
596 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
597 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
599 unreachable("invalid shader selector type");
601 oc_lds_en
= shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
? 1 : 0;
603 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
604 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
605 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
606 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
607 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
608 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) | S_00B328_DX10_CLAMP(1) |
609 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
610 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
611 S_00B32C_USER_SGPR(num_user_sgprs
) | S_00B32C_OC_LDS_EN(oc_lds_en
) |
612 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
614 if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
)
615 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
617 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
620 void gfx9_get_gs_info(struct si_shader_selector
*es
, struct si_shader_selector
*gs
,
621 struct gfx9_gs_info
*out
)
623 unsigned gs_num_invocations
= MAX2(gs
->info
.base
.gs
.invocations
, 1);
624 unsigned input_prim
= gs
->info
.base
.gs
.input_primitive
;
625 bool uses_adjacency
=
626 input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&& input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
628 /* All these are in dwords: */
629 /* We can't allow using the whole LDS, because GS waves compete with
630 * other shader stages for LDS space. */
631 const unsigned max_lds_size
= 8 * 1024;
632 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
633 unsigned esgs_lds_size
;
635 /* All these are per subgroup: */
636 const unsigned max_out_prims
= 32 * 1024;
637 const unsigned max_es_verts
= 255;
638 const unsigned ideal_gs_prims
= 64;
639 unsigned max_gs_prims
, gs_prims
;
640 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
642 if (uses_adjacency
|| gs_num_invocations
> 1)
643 max_gs_prims
= 127 / gs_num_invocations
;
647 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
648 * Make sure we don't go over the maximum value.
650 if (gs
->info
.base
.gs
.vertices_out
> 0) {
652 MIN2(max_gs_prims
, max_out_prims
/ (gs
->info
.base
.gs
.vertices_out
* gs_num_invocations
));
654 assert(max_gs_prims
> 0);
656 /* If the primitive has adjacency, halve the number of vertices
657 * that will be reused in multiple primitives.
659 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
661 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
662 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
664 /* Compute ESGS LDS size based on the worst case number of ES vertices
665 * needed to create the target number of GS prims per subgroup.
667 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
669 /* If total LDS usage is too big, refactor partitions based on ratio
670 * of ESGS item sizes.
672 if (esgs_lds_size
> max_lds_size
) {
673 /* Our target GS Prims Per Subgroup was too large. Calculate
674 * the maximum number of GS Prims Per Subgroup that will fit
675 * into LDS, capped by the maximum that the hardware can support.
677 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)), max_gs_prims
);
678 assert(gs_prims
> 0);
679 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
681 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
682 assert(esgs_lds_size
<= max_lds_size
);
685 /* Now calculate remaining ESGS information. */
687 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
689 es_verts
= max_es_verts
;
691 /* Vertices for adjacency primitives are not always reused, so restore
692 * it for ES_VERTS_PER_SUBGRP.
694 min_es_verts
= gs
->gs_input_verts_per_prim
;
696 /* For normal primitives, the VGT only checks if they are past the ES
697 * verts per subgroup after allocating a full GS primitive and if they
698 * are, kick off a new subgroup. But if those additional ES verts are
699 * unique (e.g. not reused) we need to make sure there is enough LDS
700 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
702 es_verts
-= min_es_verts
- 1;
704 out
->es_verts_per_subgroup
= es_verts
;
705 out
->gs_prims_per_subgroup
= gs_prims
;
706 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
707 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
* gs
->info
.base
.gs
.vertices_out
;
708 out
->esgs_ring_size
= esgs_lds_size
;
710 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
713 static void si_emit_shader_gs(struct si_context
*sctx
)
715 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
716 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
721 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
722 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
723 radeon_opt_set_context_reg3(
724 sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
, SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
725 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
, shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
726 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
728 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
729 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
730 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
731 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
733 /* R_028B38_VGT_GS_MAX_VERT_OUT */
734 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
, SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
735 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
737 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
738 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
739 radeon_opt_set_context_reg4(
740 sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
741 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
, shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
742 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
, shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
744 /* R_028B90_VGT_GS_INSTANCE_CNT */
745 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
, SI_TRACKED_VGT_GS_INSTANCE_CNT
,
746 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
748 if (sctx
->chip_class
>= GFX9
) {
749 /* R_028A44_VGT_GS_ONCHIP_CNTL */
750 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
, SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
751 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
752 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
753 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
754 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
755 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
756 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
757 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
758 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
759 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
761 if (shader
->key
.part
.gs
.es
->info
.stage
== MESA_SHADER_TESS_EVAL
)
762 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
, SI_TRACKED_VGT_TF_PARAM
,
763 shader
->vgt_tf_param
);
764 if (shader
->vgt_vertex_reuse_block_cntl
)
765 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
766 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
767 shader
->vgt_vertex_reuse_block_cntl
);
770 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
771 sctx
->context_roll
= true;
774 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
776 struct si_shader_selector
*sel
= shader
->selector
;
777 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
778 unsigned gs_num_invocations
= sel
->info
.base
.gs
.invocations
;
779 struct si_pm4_state
*pm4
;
781 unsigned max_stream
= util_last_bit(sel
->info
.base
.gs
.active_stream_mask
);
784 pm4
= si_get_shader_pm4_state(shader
);
788 pm4
->atom
.emit
= si_emit_shader_gs
;
790 offset
= num_components
[0] * sel
->info
.base
.gs
.vertices_out
;
791 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
794 offset
+= num_components
[1] * sel
->info
.base
.gs
.vertices_out
;
795 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
798 offset
+= num_components
[2] * sel
->info
.base
.gs
.vertices_out
;
799 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
802 offset
+= num_components
[3] * sel
->info
.base
.gs
.vertices_out
;
803 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
805 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
806 assert(offset
< (1 << 15));
808 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->info
.base
.gs
.vertices_out
;
810 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
811 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 2) ? num_components
[1] : 0;
812 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 3) ? num_components
[2] : 0;
813 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 4) ? num_components
[3] : 0;
815 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
=
816 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) | S_028B90_ENABLE(gs_num_invocations
> 0);
818 va
= shader
->bo
->gpu_address
;
820 if (sscreen
->info
.chip_class
>= GFX9
) {
821 unsigned input_prim
= sel
->info
.base
.gs
.input_primitive
;
822 gl_shader_stage es_stage
= shader
->key
.part
.gs
.es
->info
.stage
;
823 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
825 if (es_stage
== MESA_SHADER_VERTEX
) {
826 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
827 } else if (es_stage
== MESA_SHADER_TESS_EVAL
)
828 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
830 unreachable("invalid shader selector type");
832 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
833 * VGPR[0:4] are always loaded.
835 if (sel
->info
.uses_invocationid
)
836 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
837 else if (sel
->info
.uses_primid
)
838 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
839 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
840 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
842 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
844 unsigned num_user_sgprs
;
845 if (es_stage
== MESA_SHADER_VERTEX
)
846 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, GFX9_VSGS_NUM_USER_SGPR
);
848 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
850 if (sscreen
->info
.chip_class
>= GFX10
) {
851 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
852 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
854 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
855 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
858 uint32_t rsrc1
= S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) | S_00B228_DX10_CLAMP(1) |
859 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
860 S_00B228_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
861 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
862 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
863 uint32_t rsrc2
= S_00B22C_USER_SGPR(num_user_sgprs
) |
864 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
865 S_00B22C_OC_LDS_EN(es_stage
== MESA_SHADER_TESS_EVAL
) |
866 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
867 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
869 if (sscreen
->info
.chip_class
>= GFX10
) {
870 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
872 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
873 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
876 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
877 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
879 if (sscreen
->info
.chip_class
>= GFX10
) {
880 si_pm4_set_reg(pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
881 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
884 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
885 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
886 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
887 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
888 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
889 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
890 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
= shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
892 if (es_stage
== MESA_SHADER_TESS_EVAL
)
893 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
895 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
, NULL
, pm4
);
897 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
898 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
900 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
901 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
902 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
903 S_00B228_DX10_CLAMP(1) | S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
904 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
905 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
906 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
910 static void gfx10_emit_ge_pc_alloc(struct si_context
*sctx
, unsigned value
)
912 enum si_tracked_reg reg
= SI_TRACKED_GE_PC_ALLOC
;
914 if (((sctx
->tracked_regs
.reg_saved
>> reg
) & 0x1) != 0x1 ||
915 sctx
->tracked_regs
.reg_value
[reg
] != value
) {
916 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
918 if (sctx
->chip_class
== GFX10
) {
919 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
920 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
921 radeon_emit(cs
, EVENT_TYPE(V_028A90_SQ_NON_EVENT
) | EVENT_INDEX(0));
924 radeon_set_uconfig_reg(cs
, R_030980_GE_PC_ALLOC
, value
);
926 sctx
->tracked_regs
.reg_saved
|= 0x1ull
<< reg
;
927 sctx
->tracked_regs
.reg_value
[reg
] = value
;
931 /* Common tail code for NGG primitive shaders. */
932 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
, struct si_shader
*shader
,
933 unsigned initial_cdw
)
935 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
936 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
937 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
938 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
, SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
939 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
940 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
, SI_TRACKED_VGT_PRIMITIVEID_EN
,
941 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
942 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
, SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
943 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
944 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
, SI_TRACKED_VGT_GS_INSTANCE_CNT
,
945 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
946 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
947 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
948 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
949 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
, SI_TRACKED_SPI_VS_OUT_CONFIG
,
950 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
951 radeon_opt_set_context_reg2(
952 sctx
, R_028708_SPI_SHADER_IDX_FORMAT
, SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
953 shader
->ctx_reg
.ngg
.spi_shader_idx_format
, shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
954 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
, SI_TRACKED_PA_CL_VTE_CNTL
,
955 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
956 radeon_opt_set_context_reg(sctx
, R_028838_PA_CL_NGG_CNTL
, SI_TRACKED_PA_CL_NGG_CNTL
,
957 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
);
959 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
960 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
, shader
->pa_cl_vs_out_cntl
,
961 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
963 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
964 sctx
->context_roll
= true;
966 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
967 gfx10_emit_ge_pc_alloc(sctx
, shader
->ctx_reg
.ngg
.ge_pc_alloc
);
970 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
972 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
973 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
978 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
981 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
983 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
984 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
989 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
, SI_TRACKED_VGT_TF_PARAM
,
990 shader
->vgt_tf_param
);
992 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
995 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
997 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
998 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1003 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
, SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1004 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1006 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1009 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1011 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1012 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1017 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
, SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1018 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1019 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
, SI_TRACKED_VGT_TF_PARAM
,
1020 shader
->vgt_tf_param
);
1022 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1025 unsigned si_get_input_prim(const struct si_shader_selector
*gs
)
1027 if (gs
->info
.stage
== MESA_SHADER_GEOMETRY
)
1028 return gs
->info
.base
.gs
.input_primitive
;
1030 if (gs
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
1031 if (gs
->info
.base
.tess
.point_mode
)
1032 return PIPE_PRIM_POINTS
;
1033 if (gs
->info
.base
.tess
.primitive_mode
== GL_LINES
)
1034 return PIPE_PRIM_LINES
;
1035 return PIPE_PRIM_TRIANGLES
;
1038 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1039 return PIPE_PRIM_TRIANGLES
; /* worst case for all callers */
1042 static unsigned si_get_vs_out_cntl(const struct si_shader_selector
*sel
,
1043 const struct si_shader
*shader
, bool ngg
)
1045 bool writes_psize
= sel
->info
.writes_psize
;
1048 writes_psize
&= !shader
->key
.opt
.kill_pointsize
;
1050 bool misc_vec_ena
= writes_psize
|| (sel
->info
.writes_edgeflag
&& !ngg
) ||
1051 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
1052 return S_02881C_USE_VTX_POINT_SIZE(writes_psize
) |
1053 S_02881C_USE_VTX_EDGE_FLAG(sel
->info
.writes_edgeflag
&& !ngg
) |
1054 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
1055 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
1056 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
1057 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
1061 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1064 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1066 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1067 const struct si_shader_info
*gs_info
= &gs_sel
->info
;
1068 const gl_shader_stage gs_stage
= shader
->selector
->info
.stage
;
1069 const struct si_shader_selector
*es_sel
=
1070 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1071 const struct si_shader_info
*es_info
= &es_sel
->info
;
1072 const gl_shader_stage es_stage
= es_sel
->info
.stage
;
1073 unsigned num_user_sgprs
;
1074 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1076 bool window_space
= gs_info
->stage
== MESA_SHADER_VERTEX
?
1077 gs_info
->base
.vs
.window_space_position
: 0;
1078 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1079 unsigned gs_num_invocations
= MAX2(gs_sel
->info
.base
.gs
.invocations
, 1);
1080 unsigned input_prim
= si_get_input_prim(gs_sel
);
1081 bool break_wave_at_eoi
= false;
1082 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1086 if (es_stage
== MESA_SHADER_TESS_EVAL
) {
1087 pm4
->atom
.emit
= gs_stage
== MESA_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1088 : gfx10_emit_shader_ngg_tess_nogs
;
1090 pm4
->atom
.emit
= gs_stage
== MESA_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1091 : gfx10_emit_shader_ngg_notess_nogs
;
1094 va
= shader
->bo
->gpu_address
;
1096 if (es_stage
== MESA_SHADER_VERTEX
) {
1097 es_vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, false);
1099 if (es_info
->base
.vs
.blit_sgprs_amd
) {
1101 SI_SGPR_VS_BLIT_DATA
+ es_info
->base
.vs
.blit_sgprs_amd
;
1103 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, GFX9_VSGS_NUM_USER_SGPR
);
1106 assert(es_stage
== MESA_SHADER_TESS_EVAL
);
1107 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1108 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1110 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1111 break_wave_at_eoi
= true;
1114 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1115 * VGPR[0:4] are always loaded.
1117 * Vertex shaders always need to load VGPR3, because they need to
1118 * pass edge flags for decomposed primitives (such as quads) to the PA
1119 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1121 if (gs_info
->uses_invocationid
||
1122 (gs_stage
== MESA_SHADER_VERTEX
&& !gfx10_is_ngg_passthrough(shader
)))
1123 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID, edge flags. */
1124 else if ((gs_stage
== MESA_SHADER_GEOMETRY
&& gs_info
->uses_primid
) ||
1125 (gs_stage
== MESA_SHADER_VERTEX
&& shader
->key
.mono
.u
.vs_export_prim_id
))
1126 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1127 else if (input_prim
>= PIPE_PRIM_TRIANGLES
&& !gfx10_is_ngg_passthrough(shader
))
1128 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1130 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1132 unsigned wave_size
= si_get_shader_wave_size(shader
);
1134 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1135 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1137 pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1138 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / (wave_size
== 32 ? 8 : 4)) |
1139 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) | S_00B228_DX10_CLAMP(1) |
1140 S_00B228_MEM_ORDERED(1) | S_00B228_WGP_MODE(1) |
1141 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1142 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1143 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1144 S_00B22C_USER_SGPR(num_user_sgprs
) |
1145 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1146 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1147 S_00B22C_OC_LDS_EN(es_stage
== MESA_SHADER_TESS_EVAL
) |
1148 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1150 /* Determine LATE_ALLOC_GS. */
1151 unsigned num_cu_per_sh
= sscreen
->info
.min_good_cu_per_sa
;
1152 unsigned late_alloc_wave64
; /* The limit is per SA. */
1154 /* For Wave32, the hw will launch twice the number of late
1155 * alloc waves, so 1 == 2x wave32.
1157 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1159 if (sscreen
->info
.family
== CHIP_NAVI14
|| !sscreen
->info
.use_late_alloc
)
1160 late_alloc_wave64
= 0;
1161 else if (num_cu_per_sh
<= 6)
1162 late_alloc_wave64
= num_cu_per_sh
- 2; /* All CUs enabled */
1163 else if (shader
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_ALL
)
1164 late_alloc_wave64
= (num_cu_per_sh
- 2) * 6;
1166 late_alloc_wave64
= (num_cu_per_sh
- 2) * 4;
1168 /* Limit LATE_ALLOC_GS for prevent a hang (hw bug). */
1169 if (sscreen
->info
.chip_class
== GFX10
)
1170 late_alloc_wave64
= MIN2(late_alloc_wave64
, 64);
1173 pm4
, R_00B204_SPI_SHADER_PGM_RSRC4_GS
,
1174 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64
));
1176 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1177 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1178 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
1179 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1181 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1182 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1183 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1184 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1185 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ? V_02870C_SPI_SHADER_4COMP
1186 : V_02870C_SPI_SHADER_NONE
) |
1187 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ? V_02870C_SPI_SHADER_4COMP
1188 : V_02870C_SPI_SHADER_NONE
) |
1189 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ? V_02870C_SPI_SHADER_4COMP
1190 : V_02870C_SPI_SHADER_NONE
);
1192 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1193 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1194 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader
->key
.mono
.u
.vs_export_prim_id
||
1195 gs_sel
->info
.writes_primid
);
1197 if (gs_stage
== MESA_SHADER_GEOMETRY
) {
1198 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1199 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->info
.base
.gs
.vertices_out
;
1201 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1204 if (es_stage
== MESA_SHADER_TESS_EVAL
)
1205 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1207 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1208 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1209 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1210 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1211 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1212 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1213 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
= S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1214 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1215 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1216 S_028B90_CNT(gs_num_invocations
) | S_028B90_ENABLE(gs_num_invocations
> 1) |
1217 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(shader
->ngg
.max_vert_out_per_gs_instance
);
1219 /* Always output hw-generated edge flags and pass them via the prim
1220 * export to prevent drawing lines on internal edges of decomposed
1221 * primitives (such as quads) with polygon mode = lines. Only VS needs
1224 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
=
1225 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_stage
== MESA_SHADER_VERTEX
) |
1226 /* Reuse for NGG. */
1227 S_028838_VERTEX_REUSE_DEPTH(sscreen
->info
.chip_class
>= GFX10_3
? 30 : 0);
1228 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(shader
->selector
, shader
, true);
1230 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1231 float oversub_pc_factor
= 0.25;
1233 if (shader
->key
.opt
.ngg_culling
) {
1234 /* Be more aggressive with NGG culling. */
1235 if (shader
->info
.nr_param_exports
> 4)
1236 oversub_pc_factor
= 1;
1237 else if (shader
->info
.nr_param_exports
> 2)
1238 oversub_pc_factor
= 0.75;
1240 oversub_pc_factor
= 0.5;
1243 unsigned oversub_pc_lines
= sscreen
->info
.pc_lines
* oversub_pc_factor
;
1244 shader
->ctx_reg
.ngg
.ge_pc_alloc
= S_030980_OVERSUB_EN(sscreen
->info
.use_late_alloc
) |
1245 S_030980_NUM_PC_LINES(oversub_pc_lines
- 1);
1247 if (shader
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST
) {
1248 shader
->ge_cntl
= S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1249 S_03096C_VERT_GRP_SIZE(shader
->ngg
.max_gsprims
* 3);
1250 } else if (shader
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP
) {
1251 shader
->ge_cntl
= S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1252 S_03096C_VERT_GRP_SIZE(shader
->ngg
.max_gsprims
+ 2);
1254 shader
->ge_cntl
= S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1255 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1256 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1258 /* Bug workaround for a possible hang with non-tessellation cases.
1259 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1261 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1263 if ((sscreen
->info
.chip_class
== GFX10
) &&
1264 (es_stage
== MESA_SHADER_VERTEX
|| gs_stage
== MESA_SHADER_VERTEX
) && /* = no tess */
1265 shader
->ngg
.hw_max_esverts
!= 256) {
1266 shader
->ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
1268 if (shader
->ngg
.hw_max_esverts
> 5) {
1269 shader
->ge_cntl
|= S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
- 5);
1275 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
= S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1277 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1278 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1279 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1280 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1284 static void si_emit_shader_vs(struct si_context
*sctx
)
1286 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1287 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1292 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
, SI_TRACKED_VGT_GS_MODE
,
1293 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1294 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
, SI_TRACKED_VGT_PRIMITIVEID_EN
,
1295 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1297 if (sctx
->chip_class
<= GFX8
) {
1298 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
, SI_TRACKED_VGT_REUSE_OFF
,
1299 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1302 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
, SI_TRACKED_SPI_VS_OUT_CONFIG
,
1303 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1305 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1306 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1307 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1309 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
, SI_TRACKED_PA_CL_VTE_CNTL
,
1310 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1312 if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
)
1313 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
, SI_TRACKED_VGT_TF_PARAM
,
1314 shader
->vgt_tf_param
);
1316 if (shader
->vgt_vertex_reuse_block_cntl
)
1317 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1318 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1319 shader
->vgt_vertex_reuse_block_cntl
);
1321 /* Required programming for tessellation. (legacy pipeline only) */
1322 if (sctx
->chip_class
>= GFX10
&& shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
1323 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
1324 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
1325 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1326 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1327 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1330 if (sctx
->chip_class
>= GFX10
) {
1331 radeon_opt_set_context_reg_rmw(sctx
, R_02881C_PA_CL_VS_OUT_CNTL
,
1332 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS
, shader
->pa_cl_vs_out_cntl
,
1333 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK
);
1336 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1337 sctx
->context_roll
= true;
1339 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1340 if (sctx
->chip_class
>= GFX10
)
1341 gfx10_emit_ge_pc_alloc(sctx
, shader
->ctx_reg
.vs
.ge_pc_alloc
);
1345 * Compute the state for \p shader, which will run as a vertex shader on the
1348 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1349 * is the copy shader.
1351 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1352 struct si_shader_selector
*gs
)
1354 const struct si_shader_info
*info
= &shader
->selector
->info
;
1355 struct si_pm4_state
*pm4
;
1356 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1358 unsigned nparams
, oc_lds_en
;
1359 bool window_space
= info
->stage
== MESA_SHADER_VERTEX
?
1360 info
->base
.vs
.window_space_position
: 0;
1361 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1363 pm4
= si_get_shader_pm4_state(shader
);
1367 pm4
->atom
.emit
= si_emit_shader_vs
;
1369 /* We always write VGT_GS_MODE in the VS state, because every switch
1370 * between different shader pipelines involving a different GS or no
1371 * GS at all involves a switch of the VS (different GS use different
1372 * copy shaders). On the other hand, when the API switches from a GS to
1373 * no GS and then back to the same GS used originally, the GS state is
1377 unsigned mode
= V_028A40_GS_OFF
;
1379 /* PrimID needs GS scenario A. */
1381 mode
= V_028A40_GS_SCENARIO_A
;
1383 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1384 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1386 shader
->ctx_reg
.vs
.vgt_gs_mode
=
1387 ac_vgt_gs_mode(gs
->info
.base
.gs
.vertices_out
, sscreen
->info
.chip_class
);
1388 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1391 if (sscreen
->info
.chip_class
<= GFX8
) {
1392 /* Reuse needs to be set off if we write oViewport. */
1393 shader
->ctx_reg
.vs
.vgt_reuse_off
= S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1396 va
= shader
->bo
->gpu_address
;
1399 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1400 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1401 } else if (shader
->selector
->info
.stage
== MESA_SHADER_VERTEX
) {
1402 vgpr_comp_cnt
= si_get_vs_vgpr_comp_cnt(sscreen
, shader
, enable_prim_id
);
1404 if (info
->base
.vs
.blit_sgprs_amd
) {
1405 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+ info
->base
.vs
.blit_sgprs_amd
;
1407 num_user_sgprs
= si_get_num_vs_user_sgprs(shader
, SI_VS_NUM_USER_SGPR
);
1409 } else if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
1410 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1411 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1413 unreachable("invalid shader selector type");
1415 /* VS is required to export at least one param. */
1416 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1417 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1419 if (sscreen
->info
.chip_class
>= GFX10
) {
1420 shader
->ctx_reg
.vs
.spi_vs_out_config
|=
1421 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1424 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1425 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1426 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ? V_02870C_SPI_SHADER_4COMP
1427 : V_02870C_SPI_SHADER_NONE
) |
1428 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ? V_02870C_SPI_SHADER_4COMP
1429 : V_02870C_SPI_SHADER_NONE
) |
1430 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ? V_02870C_SPI_SHADER_4COMP
1431 : V_02870C_SPI_SHADER_NONE
);
1432 shader
->ctx_reg
.vs
.ge_pc_alloc
= S_030980_OVERSUB_EN(sscreen
->info
.use_late_alloc
) |
1433 S_030980_NUM_PC_LINES(sscreen
->info
.pc_lines
/ 4 - 1);
1434 shader
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(shader
->selector
, shader
, false);
1436 oc_lds_en
= shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
? 1 : 0;
1438 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1439 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1442 S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) / (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1443 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) | S_00B128_DX10_CLAMP(1) |
1444 S_00B128_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1445 S_00B128_FLOAT_MODE(shader
->config
.float_mode
);
1446 uint32_t rsrc2
= S_00B12C_USER_SGPR(num_user_sgprs
) | S_00B12C_OC_LDS_EN(oc_lds_en
) |
1447 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
1449 if (sscreen
->info
.chip_class
>= GFX10
)
1450 rsrc2
|= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
1451 else if (sscreen
->info
.chip_class
== GFX9
)
1452 rsrc2
|= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
1454 if (sscreen
->info
.chip_class
<= GFX9
)
1455 rsrc1
|= S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1457 if (!sscreen
->use_ngg_streamout
) {
1458 rsrc2
|= S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1459 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1460 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1461 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1462 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
);
1465 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
, rsrc1
);
1466 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
, rsrc2
);
1469 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
= S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1471 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1472 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1473 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1474 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1476 if (shader
->selector
->info
.stage
== MESA_SHADER_TESS_EVAL
)
1477 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1479 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1482 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1484 struct si_shader_info
*info
= &ps
->selector
->info
;
1485 unsigned num_colors
= !!(info
->colors_read
& 0x0f) + !!(info
->colors_read
& 0xf0);
1486 unsigned num_interp
=
1487 ps
->selector
->info
.num_inputs
+ (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1489 assert(num_interp
<= 32);
1490 return MIN2(num_interp
, 32);
1493 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1495 unsigned spi_shader_col_format
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1496 unsigned value
= 0, num_mrts
= 0;
1497 unsigned i
, num_targets
= (util_last_bit(spi_shader_col_format
) + 3) / 4;
1499 /* Remove holes in spi_shader_col_format. */
1500 for (i
= 0; i
< num_targets
; i
++) {
1501 unsigned spi_format
= (spi_shader_col_format
>> (i
* 4)) & 0xf;
1504 value
|= spi_format
<< (num_mrts
* 4);
1512 static void si_emit_shader_ps(struct si_context
*sctx
)
1514 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1515 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1520 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1521 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
, SI_TRACKED_SPI_PS_INPUT_ENA
,
1522 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1523 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1525 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
, SI_TRACKED_SPI_BARYC_CNTL
,
1526 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1527 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
, SI_TRACKED_SPI_PS_IN_CONTROL
,
1528 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1530 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1531 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
, SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1532 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1533 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1535 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
, SI_TRACKED_CB_SHADER_MASK
,
1536 shader
->ctx_reg
.ps
.cb_shader_mask
);
1538 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1539 sctx
->context_roll
= true;
1542 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1544 struct si_shader_info
*info
= &shader
->selector
->info
;
1545 struct si_pm4_state
*pm4
;
1546 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1547 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1549 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1551 /* we need to enable at least one of them, otherwise we hang the GPU */
1552 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) || G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1553 G_0286CC_PERSP_CENTROID_ENA(input_ena
) || G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1554 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) || G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1555 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) || G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1556 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1557 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) || G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1558 G_0286CC_PERSP_CENTER_ENA(input_ena
) || G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1559 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1561 /* Validate interpolation optimization flags (read as implications). */
1562 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1563 (G_0286CC_PERSP_CENTER_ENA(input_ena
) && G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1564 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1565 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) && G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1566 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1567 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) && !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1568 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1569 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1570 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1571 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) && !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1572 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1573 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1575 /* Validate cases when the optimizations are off (read as implications). */
1576 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1577 !G_0286CC_PERSP_CENTER_ENA(input_ena
) || !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1578 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1579 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) || !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1581 pm4
= si_get_shader_pm4_state(shader
);
1585 pm4
->atom
.emit
= si_emit_shader_ps
;
1587 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1589 * 0 -> Position = pixel center
1590 * 1 -> Position = pixel centroid
1591 * 2 -> Position = at sample position
1593 * From GLSL 4.5 specification, section 7.1:
1594 * "The variable gl_FragCoord is available as an input variable from
1595 * within fragment shaders and it holds the window relative coordinates
1596 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1597 * value can be for any location within the pixel, or one of the
1598 * fragment samples. The use of centroid does not further restrict
1599 * this value to be inside the current primitive."
1601 * Meaning that centroid has no effect and we can return anything within
1602 * the pixel. Thus, return the value at sample position, because that's
1603 * the most accurate one shaders can get.
1605 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1607 if (info
->base
.fs
.pixel_center_integer
)
1608 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1610 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1611 cb_shader_mask
= ac_get_cb_shader_mask(shader
->key
.part
.ps
.epilog
.spi_shader_col_format
);
1613 /* Ensure that some export memory is always allocated, for two reasons:
1615 * 1) Correctness: The hardware ignores the EXEC mask if no export
1616 * memory is allocated, so KILL and alpha test do not work correctly
1618 * 2) Performance: Every shader needs at least a NULL export, even when
1619 * it writes no color/depth output. The NULL export instruction
1620 * stalls without this setting.
1622 * Don't add this to CB_SHADER_MASK.
1624 * GFX10 supports pixel shaders without exports by setting both
1625 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1626 * instructions if any are present.
1628 if ((sscreen
->info
.chip_class
<= GFX9
|| info
->base
.fs
.uses_discard
||
1629 shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
) &&
1630 !spi_shader_col_format
&& !info
->writes_z
&& !info
->writes_stencil
&&
1631 !info
->writes_samplemask
)
1632 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1634 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1635 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1637 /* Set interpolation controls. */
1638 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
)) |
1639 S_0286D8_PS_W32_EN(sscreen
->ps_wave_size
== 32);
1641 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1642 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1643 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1644 ac_get_spi_shader_z_format(info
->writes_z
, info
->writes_stencil
, info
->writes_samplemask
);
1645 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1646 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1648 va
= shader
->bo
->gpu_address
;
1649 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1650 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1653 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) / (sscreen
->ps_wave_size
== 32 ? 8 : 4)) |
1654 S_00B028_DX10_CLAMP(1) | S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1655 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1657 if (sscreen
->info
.chip_class
< GFX10
) {
1658 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1661 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1662 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1663 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1664 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1665 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1668 static void si_shader_init_pm4_state(struct si_screen
*sscreen
, struct si_shader
*shader
)
1670 switch (shader
->selector
->info
.stage
) {
1671 case MESA_SHADER_VERTEX
:
1672 if (shader
->key
.as_ls
)
1673 si_shader_ls(sscreen
, shader
);
1674 else if (shader
->key
.as_es
)
1675 si_shader_es(sscreen
, shader
);
1676 else if (shader
->key
.as_ngg
)
1677 gfx10_shader_ngg(sscreen
, shader
);
1679 si_shader_vs(sscreen
, shader
, NULL
);
1681 case MESA_SHADER_TESS_CTRL
:
1682 si_shader_hs(sscreen
, shader
);
1684 case MESA_SHADER_TESS_EVAL
:
1685 if (shader
->key
.as_es
)
1686 si_shader_es(sscreen
, shader
);
1687 else if (shader
->key
.as_ngg
)
1688 gfx10_shader_ngg(sscreen
, shader
);
1690 si_shader_vs(sscreen
, shader
, NULL
);
1692 case MESA_SHADER_GEOMETRY
:
1693 if (shader
->key
.as_ngg
)
1694 gfx10_shader_ngg(sscreen
, shader
);
1696 si_shader_gs(sscreen
, shader
);
1698 case MESA_SHADER_FRAGMENT
:
1699 si_shader_ps(sscreen
, shader
);
1706 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1708 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1709 return sctx
->queued
.named
.dsa
->alpha_func
;
1712 void si_shader_selector_key_vs(struct si_context
*sctx
, struct si_shader_selector
*vs
,
1713 struct si_shader_key
*key
, struct si_vs_prolog_bits
*prolog_key
)
1715 if (!sctx
->vertex_elements
|| vs
->info
.base
.vs
.blit_sgprs_amd
)
1718 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1720 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1721 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1722 prolog_key
->unpack_instance_id_from_vertex_id
= sctx
->prim_discard_cs_instancing
;
1724 /* Prefer a monolithic shader to allow scheduling divisions around
1726 if (prolog_key
->instance_divisor_is_fetched
)
1727 key
->opt
.prefer_mono
= 1;
1729 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1730 unsigned count_mask
= (1 << count
) - 1;
1731 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1732 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1734 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1735 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1737 unsigned i
= u_bit_scan(&mask
);
1738 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1739 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1740 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1741 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1742 if (vb
->buffer_offset
& align_mask
|| vb
->stride
& align_mask
) {
1750 unsigned i
= u_bit_scan(&fix
);
1751 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1753 key
->mono
.vs_fetch_opencode
= opencode
;
1756 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
, struct si_shader_selector
*vs
,
1757 struct si_shader_key
*key
)
1759 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1761 key
->opt
.clip_disable
= sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1762 (vs
->info
.base
.clip_distance_array_size
|| vs
->info
.writes_clipvertex
) &&
1763 !vs
->info
.base
.cull_distance_array_size
;
1765 /* Find out if PS is disabled. */
1766 bool ps_disabled
= true;
1768 bool ps_modifies_zs
= ps
->info
.base
.fs
.uses_discard
|| ps
->info
.writes_z
|| ps
->info
.writes_stencil
||
1769 ps
->info
.writes_samplemask
||
1770 sctx
->queued
.named
.blend
->alpha_to_coverage
||
1771 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1772 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1774 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1775 (!ps_colormask
&& !ps_modifies_zs
&& !ps
->info
.base
.writes_memory
);
1778 /* Find out which VS outputs aren't used by the PS. */
1779 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1780 uint64_t inputs_read
= 0;
1782 /* Ignore outputs that are not passed from VS to PS. */
1783 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(VARYING_SLOT_POS
, true)) |
1784 (1ull << si_shader_io_get_unique_index(VARYING_SLOT_PSIZ
, true)) |
1785 (1ull << si_shader_io_get_unique_index(VARYING_SLOT_CLIP_VERTEX
, true)));
1788 inputs_read
= ps
->inputs_read
;
1791 uint64_t linked
= outputs_written
& inputs_read
;
1793 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1794 key
->opt
.ngg_culling
= sctx
->ngg_culling
;
1796 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1797 key
->mono
.u
.vs_export_prim_id
= 1;
1799 /* We need PKT3_CONTEXT_REG_RMW, which we currently only use on GFX10+. */
1800 if (sctx
->chip_class
>= GFX10
&&
1801 vs
->info
.writes_psize
&&
1802 sctx
->current_rast_prim
!= PIPE_PRIM_POINTS
&&
1803 !sctx
->queued
.named
.rasterizer
->polygon_mode_is_points
)
1804 key
->opt
.kill_pointsize
= 1;
1807 /* Compute the key for the hw shader variant */
1808 static inline void si_shader_selector_key(struct pipe_context
*ctx
, struct si_shader_selector
*sel
,
1809 union si_vgt_stages_key stages_key
,
1810 struct si_shader_key
*key
)
1812 struct si_context
*sctx
= (struct si_context
*)ctx
;
1814 memset(key
, 0, sizeof(*key
));
1816 switch (sel
->info
.stage
) {
1817 case MESA_SHADER_VERTEX
:
1818 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1820 if (sctx
->tes_shader
.cso
)
1822 else if (sctx
->gs_shader
.cso
) {
1824 key
->as_ngg
= stages_key
.u
.ngg
;
1826 key
->as_ngg
= stages_key
.u
.ngg
;
1827 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1830 case MESA_SHADER_TESS_CTRL
:
1831 if (sctx
->chip_class
>= GFX9
) {
1832 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
, key
, &key
->part
.tcs
.ls_prolog
);
1833 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1835 /* When the LS VGPR fix is needed, monolithic shaders
1837 * - avoid initializing EXEC in both the LS prolog
1838 * and the LS main part when !vs_needs_prolog
1839 * - remove the fixup for unused input VGPRs
1841 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1843 /* The LS output / HS input layout can be communicated
1844 * directly instead of via user SGPRs for merged LS-HS.
1845 * The LS VGPR fix prefers this too.
1847 key
->opt
.prefer_mono
= 1;
1850 key
->part
.tcs
.epilog
.prim_mode
=
1851 sctx
->tes_shader
.cso
->info
.base
.tess
.primitive_mode
;
1852 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1853 sel
->info
.tessfactors_are_def_in_all_invocs
;
1854 key
->part
.tcs
.epilog
.tes_reads_tess_factors
= sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1856 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1857 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1859 case MESA_SHADER_TESS_EVAL
:
1860 key
->as_ngg
= stages_key
.u
.ngg
;
1862 if (sctx
->gs_shader
.cso
)
1865 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1868 case MESA_SHADER_GEOMETRY
:
1869 if (sctx
->chip_class
>= GFX9
) {
1870 if (sctx
->tes_shader
.cso
) {
1871 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1873 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
, key
, &key
->part
.gs
.vs_prolog
);
1874 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1875 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1878 key
->as_ngg
= stages_key
.u
.ngg
;
1880 /* Merged ES-GS can have unbalanced wave usage.
1882 * ES threads are per-vertex, while GS threads are
1883 * per-primitive. So without any amplification, there
1884 * are fewer GS threads than ES threads, which can result
1885 * in empty (no-op) GS waves. With too much amplification,
1886 * there are more GS threads than ES threads, which
1887 * can result in empty (no-op) ES waves.
1889 * Non-monolithic shaders are implemented by setting EXEC
1890 * at the beginning of shader parts, and don't jump to
1891 * the end if EXEC is 0.
1893 * Monolithic shaders use conditional blocks, so they can
1894 * jump and skip empty waves of ES or GS. So set this to
1895 * always use optimized variants, which are monolithic.
1897 key
->opt
.prefer_mono
= 1;
1899 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1901 case MESA_SHADER_FRAGMENT
: {
1902 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1903 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1905 if (sel
->info
.color0_writes_all_cbufs
&&
1906 sel
->info
.colors_written
== 0x1)
1907 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1909 /* Select the shader color format based on whether
1910 * blending or alpha are needed.
1912 key
->part
.ps
.epilog
.spi_shader_col_format
=
1913 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1914 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1915 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1916 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1917 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1918 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1919 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1920 sctx
->framebuffer
.spi_shader_col_format
);
1921 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1923 /* The output for dual source blending should have
1924 * the same format as the first output.
1926 if (blend
->dual_src_blend
) {
1927 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1928 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1931 /* If alpha-to-coverage is enabled, we have to export alpha
1932 * even if there is no color buffer.
1934 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) && blend
->alpha_to_coverage
)
1935 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1937 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1938 * to the range supported by the type if a channel has less
1939 * than 16 bits and the export format is 16_ABGR.
1941 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1942 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1943 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1946 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1947 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1948 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1949 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1950 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1953 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1954 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1956 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1957 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1959 key
->part
.ps
.epilog
.alpha_to_one
= blend
->alpha_to_one
&& rs
->multisample_enable
;
1961 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1962 key
->part
.ps
.epilog
.poly_line_smoothing
=
1963 ((is_poly
&& rs
->poly_smooth
) || (is_line
&& rs
->line_smooth
)) &&
1964 sctx
->framebuffer
.nr_samples
<= 1;
1965 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1967 if (sctx
->ps_iter_samples
> 1 && sel
->info
.reads_samplemask
) {
1968 key
->part
.ps
.prolog
.samplemask_log_ps_iter
= util_logbase2(sctx
->ps_iter_samples
);
1971 if (rs
->force_persample_interp
&& rs
->multisample_enable
&&
1972 sctx
->framebuffer
.nr_samples
> 1 && sctx
->ps_iter_samples
> 1) {
1973 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1974 sel
->info
.uses_persp_center
|| sel
->info
.uses_persp_centroid
;
1976 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1977 sel
->info
.uses_linear_center
|| sel
->info
.uses_linear_centroid
;
1978 } else if (rs
->multisample_enable
&& sctx
->framebuffer
.nr_samples
> 1) {
1979 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
1980 sel
->info
.uses_persp_center
&& sel
->info
.uses_persp_centroid
;
1981 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
1982 sel
->info
.uses_linear_center
&& sel
->info
.uses_linear_centroid
;
1984 /* Make sure SPI doesn't compute more than 1 pair
1985 * of (i,j), which is the optimization here. */
1986 key
->part
.ps
.prolog
.force_persp_center_interp
= sel
->info
.uses_persp_center
+
1987 sel
->info
.uses_persp_centroid
+
1988 sel
->info
.uses_persp_sample
>
1991 key
->part
.ps
.prolog
.force_linear_center_interp
= sel
->info
.uses_linear_center
+
1992 sel
->info
.uses_linear_centroid
+
1993 sel
->info
.uses_linear_sample
>
1996 if (sel
->info
.uses_interp_at_sample
)
1997 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
2000 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
2002 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2003 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
2004 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
2005 struct pipe_resource
*tex
= cb0
->texture
;
2007 /* 1D textures are allocated and used as 2D on GFX9. */
2008 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
2009 key
->mono
.u
.ps
.fbfetch_is_1D
=
2010 sctx
->chip_class
!= GFX9
&&
2011 (tex
->target
== PIPE_TEXTURE_1D
|| tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
2012 key
->mono
.u
.ps
.fbfetch_layered
=
2013 tex
->target
== PIPE_TEXTURE_1D_ARRAY
|| tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
2014 tex
->target
== PIPE_TEXTURE_CUBE
|| tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2015 tex
->target
== PIPE_TEXTURE_3D
;
2023 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
2024 memset(&key
->opt
, 0, sizeof(key
->opt
));
2027 static void si_build_shader_variant(struct si_shader
*shader
, int thread_index
, bool low_priority
)
2029 struct si_shader_selector
*sel
= shader
->selector
;
2030 struct si_screen
*sscreen
= sel
->screen
;
2031 struct ac_llvm_compiler
*compiler
;
2032 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
2034 if (thread_index
>= 0) {
2036 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
2037 compiler
= &sscreen
->compiler_lowp
[thread_index
];
2039 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2040 compiler
= &sscreen
->compiler
[thread_index
];
2045 assert(!low_priority
);
2046 compiler
= shader
->compiler_ctx_state
.compiler
;
2049 if (!compiler
->passes
)
2050 si_init_compiler(sscreen
, compiler
);
2052 if (unlikely(!si_create_shader_variant(sscreen
, compiler
, shader
, debug
))) {
2053 PRINT_ERR("Failed to build shader variant (type=%u)\n", sel
->info
.stage
);
2054 shader
->compilation_failed
= true;
2058 if (shader
->compiler_ctx_state
.is_debug_context
) {
2059 FILE *f
= open_memstream(&shader
->shader_log
, &shader
->shader_log_size
);
2061 si_shader_dump(sscreen
, shader
, NULL
, f
, false);
2066 si_shader_init_pm4_state(sscreen
, shader
);
2069 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2071 struct si_shader
*shader
= (struct si_shader
*)job
;
2073 assert(thread_index
>= 0);
2075 si_build_shader_variant(shader
, thread_index
, true);
2078 static const struct si_shader_key zeroed
;
2080 static bool si_check_missing_main_part(struct si_screen
*sscreen
, struct si_shader_selector
*sel
,
2081 struct si_compiler_ctx_state
*compiler_state
,
2082 struct si_shader_key
*key
)
2084 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2087 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2092 /* We can leave the fence as permanently signaled because the
2093 * main part becomes visible globally only after it has been
2095 util_queue_fence_init(&main_part
->ready
);
2097 main_part
->selector
= sel
;
2098 main_part
->key
.as_es
= key
->as_es
;
2099 main_part
->key
.as_ls
= key
->as_ls
;
2100 main_part
->key
.as_ngg
= key
->as_ngg
;
2101 main_part
->is_monolithic
= false;
2103 if (!si_compile_shader(sscreen
, compiler_state
->compiler
, main_part
,
2104 &compiler_state
->debug
)) {
2114 * Select a shader variant according to the shader key.
2116 * \param optimized_or_none If the key describes an optimized shader variant and
2117 * the compilation isn't finished, don't select any
2118 * shader and return an error.
2120 int si_shader_select_with_key(struct si_screen
*sscreen
, struct si_shader_ctx_state
*state
,
2121 struct si_compiler_ctx_state
*compiler_state
,
2122 struct si_shader_key
*key
, int thread_index
, bool optimized_or_none
)
2124 struct si_shader_selector
*sel
= state
->cso
;
2125 struct si_shader_selector
*previous_stage_sel
= NULL
;
2126 struct si_shader
*current
= state
->current
;
2127 struct si_shader
*iter
, *shader
= NULL
;
2130 /* Check if we don't need to change anything.
2131 * This path is also used for most shaders that don't need multiple
2132 * variants, it will cost just a computation of the key and this
2134 if (likely(current
&& memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2135 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2136 if (current
->is_optimized
) {
2137 if (optimized_or_none
)
2140 memset(&key
->opt
, 0, sizeof(key
->opt
));
2141 goto current_not_ready
;
2144 util_queue_fence_wait(¤t
->ready
);
2147 return current
->compilation_failed
? -1 : 0;
2151 /* This must be done before the mutex is locked, because async GS
2152 * compilation calls this function too, and therefore must enter
2155 * Only wait if we are in a draw call. Don't wait if we are
2156 * in a compiler thread.
2158 if (thread_index
< 0)
2159 util_queue_fence_wait(&sel
->ready
);
2161 simple_mtx_lock(&sel
->mutex
);
2163 /* Find the shader variant. */
2164 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2165 /* Don't check the "current" shader. We checked it above. */
2166 if (current
!= iter
&& memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2167 simple_mtx_unlock(&sel
->mutex
);
2169 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2170 /* If it's an optimized shader and its compilation has
2171 * been started but isn't done, use the unoptimized
2172 * shader so as not to cause a stall due to compilation.
2174 if (iter
->is_optimized
) {
2175 if (optimized_or_none
)
2177 memset(&key
->opt
, 0, sizeof(key
->opt
));
2181 util_queue_fence_wait(&iter
->ready
);
2184 if (iter
->compilation_failed
) {
2185 return -1; /* skip the draw call */
2188 state
->current
= iter
;
2193 /* Build a new shader. */
2194 shader
= CALLOC_STRUCT(si_shader
);
2196 simple_mtx_unlock(&sel
->mutex
);
2200 util_queue_fence_init(&shader
->ready
);
2202 shader
->selector
= sel
;
2204 shader
->compiler_ctx_state
= *compiler_state
;
2206 /* If this is a merged shader, get the first shader's selector. */
2207 if (sscreen
->info
.chip_class
>= GFX9
) {
2208 if (sel
->info
.stage
== MESA_SHADER_TESS_CTRL
)
2209 previous_stage_sel
= key
->part
.tcs
.ls
;
2210 else if (sel
->info
.stage
== MESA_SHADER_GEOMETRY
)
2211 previous_stage_sel
= key
->part
.gs
.es
;
2213 /* We need to wait for the previous shader. */
2214 if (previous_stage_sel
&& thread_index
< 0)
2215 util_queue_fence_wait(&previous_stage_sel
->ready
);
2218 bool is_pure_monolithic
=
2219 sscreen
->use_monolithic_shaders
|| memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2221 /* Compile the main shader part if it doesn't exist. This can happen
2222 * if the initial guess was wrong.
2224 * The prim discard CS doesn't need the main shader part.
2226 if (!is_pure_monolithic
&& !key
->opt
.vs_as_prim_discard_cs
) {
2229 /* Make sure the main shader part is present. This is needed
2230 * for shaders that can be compiled as VS, LS, or ES, and only
2231 * one of them is compiled at creation.
2233 * It is also needed for GS, which can be compiled as non-NGG
2236 * For merged shaders, check that the starting shader's main
2239 if (previous_stage_sel
) {
2240 struct si_shader_key shader1_key
= zeroed
;
2242 if (sel
->info
.stage
== MESA_SHADER_TESS_CTRL
) {
2243 shader1_key
.as_ls
= 1;
2244 } else if (sel
->info
.stage
== MESA_SHADER_GEOMETRY
) {
2245 shader1_key
.as_es
= 1;
2246 shader1_key
.as_ngg
= key
->as_ngg
; /* for Wave32 vs Wave64 */
2251 simple_mtx_lock(&previous_stage_sel
->mutex
);
2252 ok
= si_check_missing_main_part(sscreen
, previous_stage_sel
, compiler_state
, &shader1_key
);
2253 simple_mtx_unlock(&previous_stage_sel
->mutex
);
2257 ok
= si_check_missing_main_part(sscreen
, sel
, compiler_state
, key
);
2262 simple_mtx_unlock(&sel
->mutex
);
2263 return -ENOMEM
; /* skip the draw call */
2267 /* Keep the reference to the 1st shader of merged shaders, so that
2268 * Gallium can't destroy it before we destroy the 2nd shader.
2270 * Set sctx = NULL, because it's unused if we're not releasing
2271 * the shader, and we don't have any sctx here.
2273 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
, previous_stage_sel
);
2275 /* Monolithic-only shaders don't make a distinction between optimized
2276 * and unoptimized. */
2277 shader
->is_monolithic
=
2278 is_pure_monolithic
|| memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2280 /* The prim discard CS is always optimized. */
2281 shader
->is_optimized
= (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2282 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2284 /* If it's an optimized shader, compile it asynchronously. */
2285 if (shader
->is_optimized
&& thread_index
< 0) {
2286 /* Compile it asynchronously. */
2287 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
, shader
, &shader
->ready
,
2288 si_build_shader_variant_low_priority
, NULL
, 0);
2290 /* Add only after the ready fence was reset, to guard against a
2291 * race with si_bind_XX_shader. */
2292 if (!sel
->last_variant
) {
2293 sel
->first_variant
= shader
;
2294 sel
->last_variant
= shader
;
2296 sel
->last_variant
->next_variant
= shader
;
2297 sel
->last_variant
= shader
;
2300 /* Use the default (unoptimized) shader for now. */
2301 memset(&key
->opt
, 0, sizeof(key
->opt
));
2302 simple_mtx_unlock(&sel
->mutex
);
2304 if (sscreen
->options
.sync_compile
)
2305 util_queue_fence_wait(&shader
->ready
);
2307 if (optimized_or_none
)
2312 /* Reset the fence before adding to the variant list. */
2313 util_queue_fence_reset(&shader
->ready
);
2315 if (!sel
->last_variant
) {
2316 sel
->first_variant
= shader
;
2317 sel
->last_variant
= shader
;
2319 sel
->last_variant
->next_variant
= shader
;
2320 sel
->last_variant
= shader
;
2323 simple_mtx_unlock(&sel
->mutex
);
2325 assert(!shader
->is_optimized
);
2326 si_build_shader_variant(shader
, thread_index
, false);
2328 util_queue_fence_signal(&shader
->ready
);
2330 if (!shader
->compilation_failed
)
2331 state
->current
= shader
;
2333 return shader
->compilation_failed
? -1 : 0;
2336 static int si_shader_select(struct pipe_context
*ctx
, struct si_shader_ctx_state
*state
,
2337 union si_vgt_stages_key stages_key
,
2338 struct si_compiler_ctx_state
*compiler_state
)
2340 struct si_context
*sctx
= (struct si_context
*)ctx
;
2341 struct si_shader_key key
;
2343 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2344 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
, &key
, -1, false);
2347 static void si_parse_next_shader_property(const struct si_shader_info
*info
, bool streamout
,
2348 struct si_shader_key
*key
)
2350 gl_shader_stage next_shader
= info
->base
.next_stage
;
2352 switch (info
->stage
) {
2353 case MESA_SHADER_VERTEX
:
2354 switch (next_shader
) {
2355 case MESA_SHADER_GEOMETRY
:
2358 case MESA_SHADER_TESS_CTRL
:
2359 case MESA_SHADER_TESS_EVAL
:
2363 /* If POSITION isn't written, it can only be a HW VS
2364 * if streamout is used. If streamout isn't used,
2365 * assume that it's a HW LS. (the next shader is TCS)
2366 * This heuristic is needed for separate shader objects.
2368 if (!info
->writes_position
&& !streamout
)
2373 case MESA_SHADER_TESS_EVAL
:
2374 if (next_shader
== MESA_SHADER_GEOMETRY
|| !info
->writes_position
)
2383 * Compile the main shader part or the monolithic shader as part of
2384 * si_shader_selector initialization. Since it can be done asynchronously,
2385 * there is no way to report compile failures to applications.
2387 static void si_init_shader_selector_async(void *job
, int thread_index
)
2389 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2390 struct si_screen
*sscreen
= sel
->screen
;
2391 struct ac_llvm_compiler
*compiler
;
2392 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2394 assert(!debug
->debug_message
|| debug
->async
);
2395 assert(thread_index
>= 0);
2396 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2397 compiler
= &sscreen
->compiler
[thread_index
];
2399 if (!compiler
->passes
)
2400 si_init_compiler(sscreen
, compiler
);
2402 /* Serialize NIR to save memory. Monolithic shader variants
2403 * have to deserialize NIR before compilation.
2410 /* true = remove optional debugging data to increase
2411 * the likehood of getting more shader cache hits.
2412 * It also drops variable names, so we'll save more memory.
2414 nir_serialize(&blob
, sel
->nir
, true);
2415 blob_finish_get_buffer(&blob
, &sel
->nir_binary
, &size
);
2416 sel
->nir_size
= size
;
2419 /* Compile the main shader part for use with a prolog and/or epilog.
2420 * If this fails, the driver will try to compile a monolithic shader
2423 if (!sscreen
->use_monolithic_shaders
) {
2424 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2425 unsigned char ir_sha1_cache_key
[20];
2428 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2432 /* We can leave the fence signaled because use of the default
2433 * main part is guarded by the selector's ready fence. */
2434 util_queue_fence_init(&shader
->ready
);
2436 shader
->selector
= sel
;
2437 shader
->is_monolithic
= false;
2438 si_parse_next_shader_property(&sel
->info
, sel
->so
.num_outputs
!= 0, &shader
->key
);
2440 if (sscreen
->use_ngg
&& (!sel
->so
.num_outputs
|| sscreen
->use_ngg_streamout
) &&
2441 ((sel
->info
.stage
== MESA_SHADER_VERTEX
&& !shader
->key
.as_ls
) ||
2442 sel
->info
.stage
== MESA_SHADER_TESS_EVAL
|| sel
->info
.stage
== MESA_SHADER_GEOMETRY
))
2443 shader
->key
.as_ngg
= 1;
2446 si_get_ir_cache_key(sel
, shader
->key
.as_ngg
, shader
->key
.as_es
, ir_sha1_cache_key
);
2449 /* Try to load the shader from the shader cache. */
2450 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2452 if (si_shader_cache_load_shader(sscreen
, ir_sha1_cache_key
, shader
)) {
2453 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2454 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2456 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2458 /* Compile the shader if it hasn't been loaded from the cache. */
2459 if (!si_compile_shader(sscreen
, compiler
, shader
, debug
)) {
2461 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2465 simple_mtx_lock(&sscreen
->shader_cache_mutex
);
2466 si_shader_cache_insert_shader(sscreen
, ir_sha1_cache_key
, shader
, true);
2467 simple_mtx_unlock(&sscreen
->shader_cache_mutex
);
2470 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2472 /* Unset "outputs_written" flags for outputs converted to
2473 * DEFAULT_VAL, so that later inter-shader optimizations don't
2474 * try to eliminate outputs that don't exist in the final
2477 * This is only done if non-monolithic shaders are enabled.
2479 if ((sel
->info
.stage
== MESA_SHADER_VERTEX
|| sel
->info
.stage
== MESA_SHADER_TESS_EVAL
) &&
2480 !shader
->key
.as_ls
&& !shader
->key
.as_es
) {
2483 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2484 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2486 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2489 unsigned semantic
= sel
->info
.output_semantic
[i
];
2492 if (semantic
< VARYING_SLOT_MAX
&&
2493 semantic
!= VARYING_SLOT_POS
&&
2494 semantic
!= VARYING_SLOT_PSIZ
&&
2495 semantic
!= VARYING_SLOT_CLIP_VERTEX
&&
2496 semantic
!= VARYING_SLOT_EDGE
) {
2497 id
= si_shader_io_get_unique_index(semantic
, true);
2498 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2504 /* The GS copy shader is always pre-compiled. */
2505 if (sel
->info
.stage
== MESA_SHADER_GEOMETRY
&&
2506 (!sscreen
->use_ngg
|| !sscreen
->use_ngg_streamout
|| /* also for PRIMITIVES_GENERATED */
2507 sel
->tess_turns_off_ngg
)) {
2508 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2509 if (!sel
->gs_copy_shader
) {
2510 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2514 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2517 /* Free NIR. We only keep serialized NIR after this point. */
2519 ralloc_free(sel
->nir
);
2524 void si_schedule_initial_compile(struct si_context
*sctx
, gl_shader_stage stage
,
2525 struct util_queue_fence
*ready_fence
,
2526 struct si_compiler_ctx_state
*compiler_ctx_state
, void *job
,
2527 util_queue_execute_func execute
)
2529 util_queue_fence_init(ready_fence
);
2531 struct util_async_debug_callback async_debug
;
2532 bool debug
= (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) || sctx
->is_debug
||
2533 si_can_dump_shader(sctx
->screen
, stage
);
2536 u_async_debug_init(&async_debug
);
2537 compiler_ctx_state
->debug
= async_debug
.base
;
2540 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
, ready_fence
, execute
, NULL
, 0);
2543 util_queue_fence_wait(ready_fence
);
2544 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2545 u_async_debug_cleanup(&async_debug
);
2548 if (sctx
->screen
->options
.sync_compile
)
2549 util_queue_fence_wait(ready_fence
);
2552 /* Return descriptor slot usage masks from the given shader info. */
2553 void si_get_active_slot_masks(const struct si_shader_info
*info
, uint64_t *const_and_shader_buffers
,
2554 uint64_t *samplers_and_images
)
2556 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_msaa_images
, num_samplers
;
2558 num_shaderbufs
= info
->base
.num_ssbos
;
2559 num_constbufs
= info
->base
.num_ubos
;
2560 /* two 8-byte images share one 16-byte slot */
2561 num_images
= align(info
->base
.num_images
, 2);
2562 num_msaa_images
= align(util_last_bit(info
->base
.msaa_images
), 2);
2563 num_samplers
= util_last_bit(info
->base
.textures_used
);
2565 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2566 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2567 *const_and_shader_buffers
= u_bit_consecutive64(start
, num_shaderbufs
+ num_constbufs
);
2570 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2571 * - image[last] ... image[0] go to [31-last .. 31]
2572 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2574 * FMASKs for images are placed separately, because MSAA images are rare,
2575 * and so we can benefit from a better cache hit rate if we keep image
2576 * descriptors together.
2578 if (num_msaa_images
)
2579 num_images
= SI_NUM_IMAGES
+ num_msaa_images
; /* add FMASK descriptors */
2581 start
= si_get_image_slot(num_images
- 1) / 2;
2582 *samplers_and_images
= u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2585 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2586 const struct pipe_shader_state
*state
)
2588 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2589 struct si_context
*sctx
= (struct si_context
*)ctx
;
2590 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2596 sel
->screen
= sscreen
;
2597 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2598 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2600 sel
->so
= state
->stream_output
;
2602 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2603 sel
->nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
, true);
2605 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2606 sel
->nir
= state
->ir
.nir
;
2609 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2611 const enum pipe_shader_type type
= pipe_shader_type_from_mesa(sel
->info
.stage
);
2612 sel
->const_and_shader_buf_descriptors_index
=
2613 si_const_and_shader_buffer_descriptors_idx(type
);
2614 sel
->sampler_and_images_descriptors_index
=
2615 si_sampler_and_image_descriptors_idx(type
);
2617 p_atomic_inc(&sscreen
->num_shaders_created
);
2618 si_get_active_slot_masks(&sel
->info
, &sel
->active_const_and_shader_buffers
,
2619 &sel
->active_samplers_and_images
);
2621 /* Record which streamout buffers are enabled. */
2622 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2623 sel
->enabled_streamout_buffer_mask
|= (1 << sel
->so
.output
[i
].output_buffer
)
2624 << (sel
->so
.output
[i
].stream
* 4);
2627 sel
->num_vs_inputs
=
2628 sel
->info
.stage
== MESA_SHADER_VERTEX
&& !sel
->info
.base
.vs
.blit_sgprs_amd
2629 ? sel
->info
.num_inputs
2631 sel
->num_vbos_in_user_sgprs
= MIN2(sel
->num_vs_inputs
, sscreen
->num_vbos_in_user_sgprs
);
2633 /* The prolog is a no-op if there are no inputs. */
2634 sel
->vs_needs_prolog
= sel
->info
.stage
== MESA_SHADER_VERTEX
&& sel
->info
.num_inputs
&&
2635 !sel
->info
.base
.vs
.blit_sgprs_amd
;
2637 sel
->prim_discard_cs_allowed
=
2638 sel
->info
.stage
== MESA_SHADER_VERTEX
&& !sel
->info
.uses_bindless_images
&&
2639 !sel
->info
.uses_bindless_samplers
&& !sel
->info
.base
.writes_memory
&&
2640 !sel
->info
.writes_viewport_index
&&
2641 !sel
->info
.base
.vs
.window_space_position
&& !sel
->so
.num_outputs
;
2643 switch (sel
->info
.stage
) {
2644 case MESA_SHADER_GEOMETRY
:
2645 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2646 sel
->rast_prim
= sel
->info
.base
.gs
.output_primitive
;
2647 if (util_rast_prim_is_triangles(sel
->rast_prim
))
2648 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2650 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2651 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
* sel
->info
.base
.gs
.vertices_out
;
2652 sel
->gs_input_verts_per_prim
=
2653 u_vertices_per_prim(sel
->info
.base
.gs
.input_primitive
);
2655 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation so
2656 * we can't split workgroups. Disable ngg if any of the following conditions is true:
2657 * - num_invocations * gs.vertices_out > 256
2658 * - LDS usage is too high
2660 sel
->tess_turns_off_ngg
= sscreen
->info
.chip_class
>= GFX10
&&
2661 (sel
->info
.base
.gs
.invocations
* sel
->info
.base
.gs
.vertices_out
> 256 ||
2662 sel
->info
.base
.gs
.invocations
* sel
->info
.base
.gs
.vertices_out
*
2663 (sel
->info
.num_outputs
* 4 + 1) > 6500 /* max dw per GS primitive */);
2666 case MESA_SHADER_TESS_CTRL
:
2667 /* Always reserve space for these. */
2668 sel
->patch_outputs_written
|=
2669 (1ull << si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_INNER
)) |
2670 (1ull << si_shader_io_get_unique_index_patch(VARYING_SLOT_TESS_LEVEL_OUTER
));
2672 case MESA_SHADER_VERTEX
:
2673 case MESA_SHADER_TESS_EVAL
:
2674 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2675 unsigned semantic
= sel
->info
.output_semantic
[i
];
2677 if (semantic
== VARYING_SLOT_TESS_LEVEL_INNER
||
2678 semantic
== VARYING_SLOT_TESS_LEVEL_OUTER
||
2679 (semantic
>= VARYING_SLOT_PATCH0
&& semantic
< VARYING_SLOT_TESS_MAX
)) {
2680 sel
->patch_outputs_written
|= 1ull << si_shader_io_get_unique_index_patch(semantic
);
2681 } else if (semantic
< VARYING_SLOT_MAX
&&
2682 semantic
!= VARYING_SLOT_EDGE
) {
2683 sel
->outputs_written
|= 1ull << si_shader_io_get_unique_index(semantic
, false);
2684 sel
->outputs_written_before_ps
|= 1ull
2685 << si_shader_io_get_unique_index(semantic
, true);
2688 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2689 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2691 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2692 * will start on a different bank. (except for the maximum 32*16).
2694 if (sel
->lshs_vertex_stride
< 32 * 16)
2695 sel
->lshs_vertex_stride
+= 4;
2697 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2698 * conflicts, i.e. each vertex will start at a different bank.
2700 if (sctx
->chip_class
>= GFX9
)
2701 sel
->esgs_itemsize
+= 4;
2703 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2706 if (sel
->info
.stage
== MESA_SHADER_TESS_EVAL
) {
2707 if (sel
->info
.base
.tess
.point_mode
)
2708 sel
->rast_prim
= PIPE_PRIM_POINTS
;
2709 else if (sel
->info
.base
.tess
.primitive_mode
== GL_LINES
)
2710 sel
->rast_prim
= PIPE_PRIM_LINE_STRIP
;
2712 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2714 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2718 case MESA_SHADER_FRAGMENT
:
2719 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2720 unsigned semantic
= sel
->info
.input_semantic
[i
];
2722 if (semantic
< VARYING_SLOT_MAX
&&
2723 semantic
!= VARYING_SLOT_PNTC
) {
2724 sel
->inputs_read
|= 1ull << si_shader_io_get_unique_index(semantic
, true);
2728 for (i
= 0; i
< 8; i
++)
2729 if (sel
->info
.colors_written
& (1 << i
))
2730 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2732 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2733 if (sel
->info
.input_semantic
[i
] == VARYING_SLOT_COL0
)
2734 sel
->color_attr_index
[0] = i
;
2735 else if (sel
->info
.input_semantic
[i
] == VARYING_SLOT_COL1
)
2736 sel
->color_attr_index
[1] = i
;
2742 sel
->ngg_culling_allowed
=
2743 sscreen
->info
.chip_class
>= GFX10
&&
2744 sscreen
->info
.has_dedicated_vram
&&
2745 sscreen
->use_ngg_culling
&&
2746 (sel
->info
.stage
== MESA_SHADER_VERTEX
||
2747 (sel
->info
.stage
== MESA_SHADER_TESS_EVAL
&&
2748 (sscreen
->always_use_ngg_culling_all
||
2749 sscreen
->always_use_ngg_culling_tess
))) &&
2750 sel
->info
.writes_position
&&
2751 !sel
->info
.writes_viewport_index
&& /* cull only against viewport 0 */
2752 !sel
->info
.base
.writes_memory
&& !sel
->so
.num_outputs
&&
2753 (sel
->info
.stage
!= MESA_SHADER_VERTEX
||
2754 (!sel
->info
.base
.vs
.blit_sgprs_amd
&&
2755 !sel
->info
.base
.vs
.window_space_position
));
2757 /* PA_CL_VS_OUT_CNTL */
2758 if (sctx
->chip_class
<= GFX9
)
2759 sel
->pa_cl_vs_out_cntl
= si_get_vs_out_cntl(sel
, NULL
, false);
2761 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
? SIX_BITS
:
2762 u_bit_consecutive(0, sel
->info
.base
.clip_distance_array_size
);
2763 sel
->culldist_mask
= u_bit_consecutive(0, sel
->info
.base
.cull_distance_array_size
) <<
2764 sel
->info
.base
.clip_distance_array_size
;
2766 /* DB_SHADER_CONTROL */
2767 sel
->db_shader_control
= S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2768 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2769 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2770 S_02880C_KILL_ENABLE(sel
->info
.base
.fs
.uses_discard
);
2772 if (sel
->info
.stage
== MESA_SHADER_FRAGMENT
) {
2773 switch (sel
->info
.base
.fs
.depth_layout
) {
2774 case FRAG_DEPTH_LAYOUT_GREATER
:
2775 sel
->db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2777 case FRAG_DEPTH_LAYOUT_LESS
:
2778 sel
->db_shader_control
|= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2783 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2785 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2786 * --|-----------|------------|------------|--------------------|-------------------|-------------
2787 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2788 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2789 * 2 | false | true | n/a | LateZ | 1 | 0
2790 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2791 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2793 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2794 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2796 * Don't use ReZ without profiling !!!
2798 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2801 if (sel
->info
.base
.fs
.early_fragment_tests
) {
2803 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2804 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2805 S_02880C_EXEC_ON_NOOP(sel
->info
.base
.writes_memory
);
2806 } else if (sel
->info
.base
.writes_memory
) {
2808 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) | S_02880C_EXEC_ON_HIER_FAIL(1);
2811 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2814 if (sel
->info
.base
.fs
.post_depth_coverage
)
2815 sel
->db_shader_control
|= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2818 (void)simple_mtx_init(&sel
->mutex
, mtx_plain
);
2820 si_schedule_initial_compile(sctx
, sel
->info
.stage
, &sel
->ready
, &sel
->compiler_ctx_state
,
2821 sel
, si_init_shader_selector_async
);
2825 static void *si_create_shader(struct pipe_context
*ctx
, const struct pipe_shader_state
*state
)
2827 struct si_context
*sctx
= (struct si_context
*)ctx
;
2828 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2830 struct si_shader_selector
*sel
= (struct si_shader_selector
*)util_live_shader_cache_get(
2831 ctx
, &sscreen
->live_shader_cache
, state
, &cache_hit
);
2833 if (sel
&& cache_hit
&& sctx
->debug
.debug_message
) {
2834 if (sel
->main_shader_part
)
2835 si_shader_dump_stats_for_shader_db(sscreen
, sel
->main_shader_part
, &sctx
->debug
);
2836 if (sel
->main_shader_part_ls
)
2837 si_shader_dump_stats_for_shader_db(sscreen
, sel
->main_shader_part_ls
, &sctx
->debug
);
2838 if (sel
->main_shader_part_es
)
2839 si_shader_dump_stats_for_shader_db(sscreen
, sel
->main_shader_part_es
, &sctx
->debug
);
2840 if (sel
->main_shader_part_ngg
)
2841 si_shader_dump_stats_for_shader_db(sscreen
, sel
->main_shader_part_ngg
, &sctx
->debug
);
2842 if (sel
->main_shader_part_ngg_es
)
2843 si_shader_dump_stats_for_shader_db(sscreen
, sel
->main_shader_part_ngg_es
, &sctx
->debug
);
2848 static void si_update_streamout_state(struct si_context
*sctx
)
2850 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2852 if (!shader_with_so
)
2855 sctx
->streamout
.enabled_stream_buffers_mask
= shader_with_so
->enabled_streamout_buffer_mask
;
2856 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2859 static void si_update_clip_regs(struct si_context
*sctx
, struct si_shader_selector
*old_hw_vs
,
2860 struct si_shader
*old_hw_vs_variant
,
2861 struct si_shader_selector
*next_hw_vs
,
2862 struct si_shader
*next_hw_vs_variant
)
2866 (old_hw_vs
->info
.stage
== MESA_SHADER_VERTEX
&& old_hw_vs
->info
.base
.vs
.window_space_position
) !=
2867 (next_hw_vs
->info
.stage
== MESA_SHADER_VERTEX
&& next_hw_vs
->info
.base
.vs
.window_space_position
) ||
2868 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2869 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2870 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
|| !old_hw_vs_variant
||
2871 !next_hw_vs_variant
||
2872 old_hw_vs_variant
->key
.opt
.clip_disable
!= next_hw_vs_variant
->key
.opt
.clip_disable
))
2873 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2876 static void si_update_common_shader_state(struct si_context
*sctx
)
2878 sctx
->uses_bindless_samplers
= si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2879 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2880 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2881 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2882 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2883 sctx
->uses_bindless_images
= si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2884 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2885 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2886 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2887 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2888 sctx
->do_update_shaders
= true;
2891 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2893 struct si_context
*sctx
= (struct si_context
*)ctx
;
2894 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2895 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2896 struct si_shader_selector
*sel
= state
;
2898 if (sctx
->vs_shader
.cso
== sel
)
2901 sctx
->vs_shader
.cso
= sel
;
2902 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2903 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.base
.vs
.blit_sgprs_amd
: 0;
2905 if (si_update_ngg(sctx
))
2906 si_shader_change_notify(sctx
);
2908 si_update_common_shader_state(sctx
);
2909 si_update_vs_viewport_state(sctx
);
2910 si_set_active_descriptors_for_shader(sctx
, sel
);
2911 si_update_streamout_state(sctx
);
2912 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
, si_get_vs(sctx
)->cso
,
2913 si_get_vs_state(sctx
));
2916 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
2918 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
2919 (sctx
->tes_shader
.cso
&& sctx
->tes_shader
.cso
->info
.uses_primid
) ||
2920 (sctx
->tcs_shader
.cso
&& sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
2921 (sctx
->gs_shader
.cso
&& sctx
->gs_shader
.cso
->info
.uses_primid
) ||
2922 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
);
2925 bool si_update_ngg(struct si_context
*sctx
)
2927 if (!sctx
->screen
->use_ngg
) {
2932 bool new_ngg
= true;
2934 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&& sctx
->gs_shader
.cso
->tess_turns_off_ngg
) {
2936 } else if (!sctx
->screen
->use_ngg_streamout
) {
2937 struct si_shader_selector
*last
= si_get_vs(sctx
)->cso
;
2939 if ((last
&& last
->so
.num_outputs
) || sctx
->streamout
.prims_gen_query_enabled
)
2943 if (new_ngg
!= sctx
->ngg
) {
2944 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
2945 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
2948 if (sctx
->chip_class
== GFX10
&& !new_ngg
)
2949 sctx
->flags
|= SI_CONTEXT_VGT_FLUSH
;
2951 sctx
->ngg
= new_ngg
;
2952 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
2958 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
2960 struct si_context
*sctx
= (struct si_context
*)ctx
;
2961 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2962 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2963 struct si_shader_selector
*sel
= state
;
2964 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
2967 if (sctx
->gs_shader
.cso
== sel
)
2970 sctx
->gs_shader
.cso
= sel
;
2971 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2972 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
2974 si_update_common_shader_state(sctx
);
2975 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
2977 ngg_changed
= si_update_ngg(sctx
);
2978 if (ngg_changed
|| enable_changed
)
2979 si_shader_change_notify(sctx
);
2980 if (enable_changed
) {
2981 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
2982 si_update_tess_uses_prim_id(sctx
);
2984 si_update_vs_viewport_state(sctx
);
2985 si_set_active_descriptors_for_shader(sctx
, sel
);
2986 si_update_streamout_state(sctx
);
2987 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
, si_get_vs(sctx
)->cso
,
2988 si_get_vs_state(sctx
));
2991 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
2993 struct si_context
*sctx
= (struct si_context
*)ctx
;
2994 struct si_shader_selector
*sel
= state
;
2995 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
2997 if (sctx
->tcs_shader
.cso
== sel
)
3000 sctx
->tcs_shader
.cso
= sel
;
3001 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3002 si_update_tess_uses_prim_id(sctx
);
3004 si_update_common_shader_state(sctx
);
3007 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
3009 si_set_active_descriptors_for_shader(sctx
, sel
);
3012 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
3014 struct si_context
*sctx
= (struct si_context
*)ctx
;
3015 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3016 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3017 struct si_shader_selector
*sel
= state
;
3018 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
3020 if (sctx
->tes_shader
.cso
== sel
)
3023 sctx
->tes_shader
.cso
= sel
;
3024 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
3025 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
3026 si_update_tess_uses_prim_id(sctx
);
3028 si_update_common_shader_state(sctx
);
3029 sctx
->last_gs_out_prim
= -1; /* reset this so that it gets updated */
3031 bool ngg_changed
= si_update_ngg(sctx
);
3032 if (ngg_changed
|| enable_changed
)
3033 si_shader_change_notify(sctx
);
3035 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
3036 si_update_vs_viewport_state(sctx
);
3037 si_set_active_descriptors_for_shader(sctx
, sel
);
3038 si_update_streamout_state(sctx
);
3039 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
, si_get_vs(sctx
)->cso
,
3040 si_get_vs_state(sctx
));
3043 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3045 struct si_context
*sctx
= (struct si_context
*)ctx
;
3046 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3047 struct si_shader_selector
*sel
= state
;
3049 /* skip if supplied shader is one already in use */
3053 sctx
->ps_shader
.cso
= sel
;
3054 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3056 si_update_common_shader_state(sctx
);
3058 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3059 si_update_tess_uses_prim_id(sctx
);
3061 if (!old_sel
|| old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3062 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3064 if (sctx
->screen
->has_out_of_order_rast
&&
3065 (!old_sel
|| old_sel
->info
.base
.writes_memory
!= sel
->info
.base
.writes_memory
||
3066 old_sel
->info
.base
.fs
.early_fragment_tests
!=
3067 sel
->info
.base
.fs
.early_fragment_tests
))
3068 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3070 si_set_active_descriptors_for_shader(sctx
, sel
);
3071 si_update_ps_colorbuf0_slot(sctx
);
3074 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3076 if (shader
->is_optimized
) {
3077 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
, &shader
->ready
);
3080 util_queue_fence_destroy(&shader
->ready
);
3083 /* If destroyed shaders were not unbound, the next compiled
3084 * shader variant could get the same pointer address and so
3085 * binding it to the same shader stage would be considered
3086 * a no-op, causing random behavior.
3088 switch (shader
->selector
->info
.stage
) {
3089 case MESA_SHADER_VERTEX
:
3090 if (shader
->key
.as_ls
) {
3091 assert(sctx
->chip_class
<= GFX8
);
3092 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3093 } else if (shader
->key
.as_es
) {
3094 assert(sctx
->chip_class
<= GFX8
);
3095 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3096 } else if (shader
->key
.as_ngg
) {
3097 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3099 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3102 case MESA_SHADER_TESS_CTRL
:
3103 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3105 case MESA_SHADER_TESS_EVAL
:
3106 if (shader
->key
.as_es
) {
3107 assert(sctx
->chip_class
<= GFX8
);
3108 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3109 } else if (shader
->key
.as_ngg
) {
3110 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3112 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3115 case MESA_SHADER_GEOMETRY
:
3116 if (shader
->is_gs_copy_shader
)
3117 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3119 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3121 case MESA_SHADER_FRAGMENT
:
3122 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3128 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3129 si_shader_destroy(shader
);
3133 static void si_destroy_shader_selector(struct pipe_context
*ctx
, void *cso
)
3135 struct si_context
*sctx
= (struct si_context
*)ctx
;
3136 struct si_shader_selector
*sel
= (struct si_shader_selector
*)cso
;
3137 struct si_shader
*p
= sel
->first_variant
, *c
;
3138 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3139 [MESA_SHADER_VERTEX
] = &sctx
->vs_shader
,
3140 [MESA_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3141 [MESA_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3142 [MESA_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3143 [MESA_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3146 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3148 if (current_shader
[sel
->info
.stage
]->cso
== sel
) {
3149 current_shader
[sel
->info
.stage
]->cso
= NULL
;
3150 current_shader
[sel
->info
.stage
]->current
= NULL
;
3154 c
= p
->next_variant
;
3155 si_delete_shader(sctx
, p
);
3159 if (sel
->main_shader_part
)
3160 si_delete_shader(sctx
, sel
->main_shader_part
);
3161 if (sel
->main_shader_part_ls
)
3162 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3163 if (sel
->main_shader_part_es
)
3164 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3165 if (sel
->main_shader_part_ngg
)
3166 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3167 if (sel
->gs_copy_shader
)
3168 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3170 util_queue_fence_destroy(&sel
->ready
);
3171 simple_mtx_destroy(&sel
->mutex
);
3172 ralloc_free(sel
->nir
);
3173 free(sel
->nir_binary
);
3177 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3179 struct si_context
*sctx
= (struct si_context
*)ctx
;
3180 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3182 si_shader_selector_reference(sctx
, &sel
, NULL
);
3185 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
, struct si_shader
*vs
,
3186 unsigned semantic
, enum glsl_interp_mode interpolate
)
3188 struct si_shader_info
*vsinfo
= &vs
->selector
->info
;
3189 unsigned offset
, ps_input_cntl
= 0;
3191 if (interpolate
== INTERP_MODE_FLAT
||
3192 (interpolate
== INTERP_MODE_COLOR
&& sctx
->flatshade
) ||
3193 semantic
== VARYING_SLOT_PRIMITIVE_ID
)
3194 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3196 if (semantic
== VARYING_SLOT_PNTC
||
3197 (semantic
>= VARYING_SLOT_TEX0
&& semantic
<= VARYING_SLOT_TEX7
&&
3198 sctx
->sprite_coord_enable
& (1 << (semantic
- VARYING_SLOT_TEX0
)))) {
3199 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3202 int vs_slot
= vsinfo
->output_semantic_to_slot
[semantic
];
3204 offset
= vs
->info
.vs_output_param_offset
[vs_slot
];
3206 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3207 /* The input is loaded from parameter memory. */
3208 ps_input_cntl
|= S_028644_OFFSET(offset
);
3209 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3210 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3211 /* This can happen with depth-only rendering. */
3214 /* The input is a DEFAULT_VAL constant. */
3215 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3216 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3217 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3220 ps_input_cntl
= S_028644_OFFSET(0x20) | S_028644_DEFAULT_VAL(offset
);
3223 /* VS output not found. */
3224 if (semantic
== VARYING_SLOT_PRIMITIVE_ID
) {
3225 /* PrimID is written after the last output when HW VS is used. */
3226 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3227 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3228 /* No corresponding output found, load defaults into input.
3229 * Don't set any other bits.
3230 * (FLAT_SHADE=1 completely changes behavior) */
3231 ps_input_cntl
= S_028644_OFFSET(0x20);
3232 /* D3D 9 behaviour. GL is undefined */
3233 if (semantic
== VARYING_SLOT_COL0
)
3234 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3238 return ps_input_cntl
;
3241 static void si_emit_spi_map(struct si_context
*sctx
)
3243 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3244 struct si_shader
*vs
= si_get_vs_state(sctx
);
3245 struct si_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3246 unsigned i
, num_interp
, num_written
= 0;
3247 unsigned spi_ps_input_cntl
[32];
3249 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3252 num_interp
= si_get_ps_num_interp(ps
);
3253 assert(num_interp
> 0);
3255 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3256 unsigned semantic
= psinfo
->input_semantic
[i
];
3257 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3259 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, semantic
, interpolate
);
3262 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3263 for (i
= 0; i
< 2; i
++) {
3264 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3267 unsigned semantic
= VARYING_SLOT_BFC0
+ i
;
3268 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, semantic
,
3269 psinfo
->color_interpolate
[i
]);
3272 assert(num_interp
== num_written
);
3274 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3275 /* Dota 2: Only ~16% of SPI map updates set different values. */
3276 /* Talos: Only ~9% of SPI map updates set different values. */
3277 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3278 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
, spi_ps_input_cntl
,
3279 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3281 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3282 sctx
->context_roll
= true;
3286 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3288 static void si_cs_preamble_add_vgt_flush(struct si_context
*sctx
)
3290 /* We shouldn't get here if registers are shadowed. */
3291 assert(!sctx
->shadowed_regs
);
3293 if (sctx
->cs_preamble_has_vgt_flush
)
3296 /* Done by Vulkan before VGT_FLUSH. */
3297 si_pm4_cmd_add(sctx
->cs_preamble_state
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3298 si_pm4_cmd_add(sctx
->cs_preamble_state
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3300 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3301 si_pm4_cmd_add(sctx
->cs_preamble_state
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3302 si_pm4_cmd_add(sctx
->cs_preamble_state
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3303 sctx
->cs_preamble_has_vgt_flush
= true;
3307 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3309 static void si_emit_vgt_flush(struct radeon_cmdbuf
*cs
)
3311 /* This is required before VGT_FLUSH. */
3312 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3313 radeon_emit(cs
, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3315 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3316 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3317 radeon_emit(cs
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3320 /* Initialize state related to ESGS / GSVS ring buffers */
3321 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3323 struct si_shader_selector
*es
=
3324 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3325 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3326 struct si_pm4_state
*pm4
;
3328 /* Chip constants. */
3329 unsigned num_se
= sctx
->screen
->info
.max_se
;
3330 unsigned wave_size
= 64;
3331 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3332 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3333 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3335 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3336 unsigned alignment
= 256 * num_se
;
3337 /* The maximum size is 63.999 MB per SE. */
3338 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3340 /* Calculate the minimum size. */
3341 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
* wave_size
, alignment
);
3343 /* These are recommended sizes, not minimum sizes. */
3344 unsigned esgs_ring_size
=
3345 max_gs_waves
* 2 * wave_size
* es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3346 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
* gs
->max_gsvs_emit_size
;
3348 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3349 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3350 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3352 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3353 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3355 /* Some rings don't have to be allocated if shaders don't use them.
3356 * (e.g. no varyings between ES and GS or GS and VS)
3358 * GFX9 doesn't have the ESGS ring.
3360 bool update_esgs
= sctx
->chip_class
<= GFX8
&& esgs_ring_size
&&
3361 (!sctx
->esgs_ring
|| sctx
->esgs_ring
->width0
< esgs_ring_size
);
3363 gsvs_ring_size
&& (!sctx
->gsvs_ring
|| sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3365 if (!update_esgs
&& !update_gsvs
)
3369 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3371 pipe_aligned_buffer_create(sctx
->b
.screen
, SI_RESOURCE_FLAG_UNMAPPABLE
, PIPE_USAGE_DEFAULT
,
3372 esgs_ring_size
, sctx
->screen
->info
.pte_fragment_size
);
3373 if (!sctx
->esgs_ring
)
3378 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3380 pipe_aligned_buffer_create(sctx
->b
.screen
, SI_RESOURCE_FLAG_UNMAPPABLE
, PIPE_USAGE_DEFAULT
,
3381 gsvs_ring_size
, sctx
->screen
->info
.pte_fragment_size
);
3382 if (!sctx
->gsvs_ring
)
3386 /* Set ring bindings. */
3387 if (sctx
->esgs_ring
) {
3388 assert(sctx
->chip_class
<= GFX8
);
3389 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
, sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
, true,
3391 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
, sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
, false,
3394 if (sctx
->gsvs_ring
) {
3395 si_set_ring_buffer(sctx
, SI_RING_GSVS
, sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
, false,
3399 if (sctx
->shadowed_regs
) {
3400 /* These registers will be shadowed, so set them only once. */
3401 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3403 assert(sctx
->chip_class
>= GFX7
);
3405 si_emit_vgt_flush(cs
);
3407 /* Set the GS registers. */
3408 if (sctx
->esgs_ring
) {
3409 assert(sctx
->chip_class
<= GFX8
);
3410 radeon_set_uconfig_reg(cs
, R_030900_VGT_ESGS_RING_SIZE
,
3411 sctx
->esgs_ring
->width0
/ 256);
3413 if (sctx
->gsvs_ring
) {
3414 radeon_set_uconfig_reg(cs
, R_030904_VGT_GSVS_RING_SIZE
,
3415 sctx
->gsvs_ring
->width0
/ 256);
3420 /* The codepath without register shadowing. */
3421 /* Create the "cs_preamble_gs_rings" state. */
3422 pm4
= CALLOC_STRUCT(si_pm4_state
);
3426 if (sctx
->chip_class
>= GFX7
) {
3427 if (sctx
->esgs_ring
) {
3428 assert(sctx
->chip_class
<= GFX8
);
3429 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
, sctx
->esgs_ring
->width0
/ 256);
3431 if (sctx
->gsvs_ring
)
3432 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
, sctx
->gsvs_ring
->width0
/ 256);
3434 if (sctx
->esgs_ring
)
3435 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
, sctx
->esgs_ring
->width0
/ 256);
3436 if (sctx
->gsvs_ring
)
3437 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
, sctx
->gsvs_ring
->width0
/ 256);
3440 /* Set the state. */
3441 if (sctx
->cs_preamble_gs_rings
)
3442 si_pm4_free_state(sctx
, sctx
->cs_preamble_gs_rings
, ~0);
3443 sctx
->cs_preamble_gs_rings
= pm4
;
3445 si_cs_preamble_add_vgt_flush(sctx
);
3447 /* Flush the context to re-emit both cs_preamble states. */
3448 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3449 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3454 static void si_shader_lock(struct si_shader
*shader
)
3456 simple_mtx_lock(&shader
->selector
->mutex
);
3457 if (shader
->previous_stage_sel
) {
3458 assert(shader
->previous_stage_sel
!= shader
->selector
);
3459 simple_mtx_lock(&shader
->previous_stage_sel
->mutex
);
3463 static void si_shader_unlock(struct si_shader
*shader
)
3465 if (shader
->previous_stage_sel
)
3466 simple_mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3467 simple_mtx_unlock(&shader
->selector
->mutex
);
3471 * @returns 1 if \p sel has been updated to use a new scratch buffer
3473 * < 0 if there was a failure
3475 static int si_update_scratch_buffer(struct si_context
*sctx
, struct si_shader
*shader
)
3477 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3482 /* This shader doesn't need a scratch buffer */
3483 if (shader
->config
.scratch_bytes_per_wave
== 0)
3486 /* Prevent race conditions when updating:
3487 * - si_shader::scratch_bo
3488 * - si_shader::binary::code
3489 * - si_shader::previous_stage::binary::code.
3491 si_shader_lock(shader
);
3493 /* This shader is already configured to use the current
3494 * scratch buffer. */
3495 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3496 si_shader_unlock(shader
);
3500 assert(sctx
->scratch_buffer
);
3502 /* Replace the shader bo with a new bo that has the relocs applied. */
3503 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3504 si_shader_unlock(shader
);
3508 /* Update the shader state to use the new shader bo. */
3509 si_shader_init_pm4_state(sctx
->screen
, shader
);
3511 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3513 si_shader_unlock(shader
);
3517 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3519 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3522 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3524 if (!sctx
->tes_shader
.cso
)
3525 return NULL
; /* tessellation disabled */
3527 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
: sctx
->fixed_func_tcs_shader
.current
;
3530 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3532 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3535 /* Update the shaders, so that they are using the latest scratch.
3536 * The scratch buffer may have been changed since these shaders were
3537 * last used, so we still need to try to update them, even if they
3538 * require scratch buffers smaller than the current size.
3540 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3544 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3546 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3550 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3552 r
= si_update_scratch_buffer(sctx
, tcs
);
3556 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3558 /* VS can be bound as LS, ES, or VS. */
3559 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3563 if (sctx
->vs_shader
.current
->key
.as_ls
)
3564 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3565 else if (sctx
->vs_shader
.current
->key
.as_es
)
3566 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3567 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3568 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3570 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3573 /* TES can be bound as ES or VS. */
3574 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3578 if (sctx
->tes_shader
.current
->key
.as_es
)
3579 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3580 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3581 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3583 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3589 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3591 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3592 * There are 2 cases to handle:
3594 * - If the current needed size is less than the maximum seen size,
3595 * use the maximum seen size, so that WAVESIZE remains the same.
3597 * - If the current needed size is greater than the maximum seen size,
3598 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3600 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3601 * Otherwise, the number of waves that can use scratch is
3602 * SPI_TMPRING_SIZE.WAVES.
3606 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3607 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3608 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3610 if (sctx
->tes_shader
.cso
) {
3611 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3612 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx
)));
3615 sctx
->max_seen_scratch_bytes_per_wave
= MAX2(sctx
->max_seen_scratch_bytes_per_wave
, bytes
);
3617 unsigned scratch_needed_size
= sctx
->max_seen_scratch_bytes_per_wave
* sctx
->scratch_waves
;
3618 unsigned spi_tmpring_size
;
3620 if (scratch_needed_size
> 0) {
3621 if (!sctx
->scratch_buffer
|| scratch_needed_size
> sctx
->scratch_buffer
->b
.b
.width0
) {
3622 /* Create a bigger scratch buffer */
3623 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3625 sctx
->scratch_buffer
= si_aligned_buffer_create(
3626 &sctx
->screen
->b
, SI_RESOURCE_FLAG_UNMAPPABLE
, PIPE_USAGE_DEFAULT
, scratch_needed_size
,
3627 sctx
->screen
->info
.pte_fragment_size
);
3628 if (!sctx
->scratch_buffer
)
3631 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3632 si_context_add_resource_size(sctx
, &sctx
->scratch_buffer
->b
.b
);
3635 if (!si_update_scratch_relocs(sctx
))
3639 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3640 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3641 "scratch size should already be aligned correctly.");
3643 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3644 S_0286E8_WAVESIZE(sctx
->max_seen_scratch_bytes_per_wave
>> 10);
3645 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3646 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3647 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3652 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3654 assert(!sctx
->tess_rings
);
3655 assert(((sctx
->screen
->tess_factor_ring_size
/ 4) & C_030938_SIZE
) == 0);
3657 /* The address must be aligned to 2^19, because the shader only
3658 * receives the high 13 bits.
3660 sctx
->tess_rings
= pipe_aligned_buffer_create(
3661 sctx
->b
.screen
, SI_RESOURCE_FLAG_32BIT
, PIPE_USAGE_DEFAULT
,
3662 sctx
->screen
->tess_offchip_ring_size
+ sctx
->screen
->tess_factor_ring_size
, 1 << 19);
3663 if (!sctx
->tess_rings
)
3666 uint64_t factor_va
=
3667 si_resource(sctx
->tess_rings
)->gpu_address
+ sctx
->screen
->tess_offchip_ring_size
;
3669 if (sctx
->shadowed_regs
) {
3670 /* These registers will be shadowed, so set them only once. */
3671 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
3673 assert(sctx
->chip_class
>= GFX7
);
3675 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, si_resource(sctx
->tess_rings
),
3676 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3677 si_emit_vgt_flush(cs
);
3679 /* Set tessellation registers. */
3680 radeon_set_uconfig_reg(cs
, R_030938_VGT_TF_RING_SIZE
,
3681 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3682 radeon_set_uconfig_reg(cs
, R_030940_VGT_TF_MEMORY_BASE
, factor_va
>> 8);
3683 if (sctx
->chip_class
>= GFX10
) {
3684 radeon_set_uconfig_reg(cs
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3685 S_030984_BASE_HI(factor_va
>> 40));
3686 } else if (sctx
->chip_class
== GFX9
) {
3687 radeon_set_uconfig_reg(cs
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3688 S_030944_BASE_HI(factor_va
>> 40));
3690 radeon_set_uconfig_reg(cs
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3691 sctx
->screen
->vgt_hs_offchip_param
);
3695 /* The codepath without register shadowing. */
3696 si_cs_preamble_add_vgt_flush(sctx
);
3698 /* Append these registers to the init config state. */
3699 if (sctx
->chip_class
>= GFX7
) {
3700 si_pm4_set_reg(sctx
->cs_preamble_state
, R_030938_VGT_TF_RING_SIZE
,
3701 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3702 si_pm4_set_reg(sctx
->cs_preamble_state
, R_030940_VGT_TF_MEMORY_BASE
, factor_va
>> 8);
3703 if (sctx
->chip_class
>= GFX10
)
3704 si_pm4_set_reg(sctx
->cs_preamble_state
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3705 S_030984_BASE_HI(factor_va
>> 40));
3706 else if (sctx
->chip_class
== GFX9
)
3707 si_pm4_set_reg(sctx
->cs_preamble_state
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3708 S_030944_BASE_HI(factor_va
>> 40));
3709 si_pm4_set_reg(sctx
->cs_preamble_state
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3710 sctx
->screen
->vgt_hs_offchip_param
);
3712 si_pm4_set_reg(sctx
->cs_preamble_state
, R_008988_VGT_TF_RING_SIZE
,
3713 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3714 si_pm4_set_reg(sctx
->cs_preamble_state
, R_0089B8_VGT_TF_MEMORY_BASE
, factor_va
>> 8);
3715 si_pm4_set_reg(sctx
->cs_preamble_state
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3716 sctx
->screen
->vgt_hs_offchip_param
);
3719 /* Flush the context to re-emit the cs_preamble state.
3720 * This is done only once in a lifetime of a context.
3722 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3723 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3726 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3727 union si_vgt_stages_key key
)
3729 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3730 uint32_t stages
= 0;
3733 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) | S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3736 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) | S_028B54_GS_EN(1);
3738 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3740 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3741 } else if (key
.u
.gs
) {
3742 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) | S_028B54_GS_EN(1);
3743 } else if (key
.u
.ngg
) {
3744 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3748 stages
|= S_028B54_PRIMGEN_EN(1) | S_028B54_GS_FAST_LAUNCH(key
.u
.ngg_gs_fast_launch
) |
3749 S_028B54_NGG_WAVE_ID_EN(key
.u
.streamout
) |
3750 S_028B54_PRIMGEN_PASSTHRU_EN(key
.u
.ngg_passthrough
);
3751 } else if (key
.u
.gs
)
3752 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3754 if (screen
->info
.chip_class
>= GFX9
)
3755 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3757 if (screen
->info
.chip_class
>= GFX10
&&
3758 /* GS fast launch hangs with Wave64, so always use Wave32. */
3759 (screen
->ge_wave_size
== 32 || (key
.u
.ngg
&& key
.u
.ngg_gs_fast_launch
))) {
3760 stages
|= S_028B54_HS_W32_EN(1) |
3761 S_028B54_GS_W32_EN(key
.u
.ngg
) | /* legacy GS only supports Wave64 */
3762 S_028B54_VS_W32_EN(1);
3765 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3769 static void si_update_vgt_shader_config(struct si_context
*sctx
, union si_vgt_stages_key key
)
3771 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3773 if (unlikely(!*pm4
))
3774 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3775 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3778 bool si_update_shaders(struct si_context
*sctx
)
3780 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3781 struct si_compiler_ctx_state compiler_state
;
3782 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3783 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3784 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3785 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3786 union si_vgt_stages_key key
;
3787 unsigned old_spi_shader_col_format
=
3788 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3791 if (!sctx
->compiler
.passes
)
3792 si_init_compiler(sctx
->screen
, &sctx
->compiler
);
3794 compiler_state
.compiler
= &sctx
->compiler
;
3795 compiler_state
.debug
= sctx
->debug
;
3796 compiler_state
.is_debug_context
= sctx
->is_debug
;
3800 if (sctx
->tes_shader
.cso
)
3802 if (sctx
->gs_shader
.cso
)
3807 key
.u
.streamout
= !!si_get_vs(sctx
)->cso
->so
.num_outputs
;
3810 /* Update TCS and TES. */
3811 if (sctx
->tes_shader
.cso
) {
3812 if (!sctx
->tess_rings
) {
3813 si_init_tess_factor_ring(sctx
);
3814 if (!sctx
->tess_rings
)
3818 if (sctx
->tcs_shader
.cso
) {
3819 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
, &compiler_state
);
3822 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3824 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3825 sctx
->fixed_func_tcs_shader
.cso
= si_create_fixed_func_tcs(sctx
);
3826 if (!sctx
->fixed_func_tcs_shader
.cso
)
3830 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
, key
, &compiler_state
);
3833 si_pm4_bind_state(sctx
, hs
, sctx
->fixed_func_tcs_shader
.current
->pm4
);
3836 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
3837 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
3841 if (sctx
->gs_shader
.cso
) {
3843 assert(sctx
->chip_class
<= GFX8
);
3844 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3845 } else if (key
.u
.ngg
) {
3846 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3848 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3852 if (sctx
->chip_class
<= GFX8
)
3853 si_pm4_bind_state(sctx
, ls
, NULL
);
3854 si_pm4_bind_state(sctx
, hs
, NULL
);
3858 if (sctx
->gs_shader
.cso
) {
3859 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
3862 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3864 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3866 if (!si_update_gs_ring_buffers(sctx
))
3869 si_pm4_bind_state(sctx
, vs
, NULL
);
3873 si_pm4_bind_state(sctx
, gs
, NULL
);
3874 if (sctx
->chip_class
<= GFX8
)
3875 si_pm4_bind_state(sctx
, es
, NULL
);
3880 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
3881 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
3885 if (!key
.u
.tess
&& !key
.u
.gs
) {
3887 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3888 si_pm4_bind_state(sctx
, vs
, NULL
);
3890 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3892 } else if (sctx
->tes_shader
.cso
) {
3893 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3895 assert(sctx
->gs_shader
.cso
);
3896 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3900 /* This must be done after the shader variant is selected. */
3902 struct si_shader
*vs
= si_get_vs(sctx
)->current
;
3904 key
.u
.ngg_passthrough
= gfx10_is_ngg_passthrough(vs
);
3905 key
.u
.ngg_gs_fast_launch
= !!(vs
->key
.opt
.ngg_culling
& SI_NGG_CULL_GS_FAST_LAUNCH_ALL
);
3908 si_update_vgt_shader_config(sctx
, key
);
3910 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3911 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3913 if (sctx
->ps_shader
.cso
) {
3914 unsigned db_shader_control
;
3916 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
3919 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3921 db_shader_control
= sctx
->ps_shader
.cso
->db_shader_control
|
3922 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3924 if (si_pm4_state_changed(sctx
, ps
) || si_pm4_state_changed(sctx
, vs
) ||
3925 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
3926 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3927 sctx
->flatshade
!= rs
->flatshade
) {
3928 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3929 sctx
->flatshade
= rs
->flatshade
;
3930 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3933 if (sctx
->screen
->info
.rbplus_allowed
&& si_pm4_state_changed(sctx
, ps
) &&
3934 (!old_ps
|| old_spi_shader_col_format
!=
3935 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
3936 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3938 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
3939 sctx
->ps_db_shader_control
= db_shader_control
;
3940 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3941 if (sctx
->screen
->dpbb_allowed
)
3942 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
3945 if (sctx
->smoothing_enabled
!=
3946 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
3947 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
3948 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3950 if (sctx
->chip_class
== GFX6
)
3951 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
3953 if (sctx
->framebuffer
.nr_samples
<= 1)
3954 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
3958 if (si_pm4_state_enabled_and_changed(sctx
, ls
) || si_pm4_state_enabled_and_changed(sctx
, hs
) ||
3959 si_pm4_state_enabled_and_changed(sctx
, es
) || si_pm4_state_enabled_and_changed(sctx
, gs
) ||
3960 si_pm4_state_enabled_and_changed(sctx
, vs
) || si_pm4_state_enabled_and_changed(sctx
, ps
)) {
3961 if (!si_update_spi_tmpring_size(sctx
))
3965 if (sctx
->chip_class
>= GFX7
) {
3966 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
3967 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
3968 else if (!sctx
->queued
.named
.ls
)
3969 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
3971 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
3972 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
3973 else if (!sctx
->queued
.named
.hs
)
3974 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
3976 if (si_pm4_state_enabled_and_changed(sctx
, es
))
3977 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
3978 else if (!sctx
->queued
.named
.es
)
3979 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
3981 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
3982 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
3983 else if (!sctx
->queued
.named
.gs
)
3984 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
3986 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
3987 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
3988 else if (!sctx
->queued
.named
.vs
)
3989 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
3991 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
3992 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
3993 else if (!sctx
->queued
.named
.ps
)
3994 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
3997 sctx
->do_update_shaders
= false;
4001 static void si_emit_scratch_state(struct si_context
*sctx
)
4003 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4005 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
, sctx
->spi_tmpring_size
);
4007 if (sctx
->scratch_buffer
) {
4008 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
, sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
4009 RADEON_PRIO_SCRATCH_BUFFER
);
4013 void si_init_screen_live_shader_cache(struct si_screen
*sscreen
)
4015 util_live_shader_cache_init(&sscreen
->live_shader_cache
, si_create_shader_selector
,
4016 si_destroy_shader_selector
);
4019 void si_init_shader_functions(struct si_context
*sctx
)
4021 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
4022 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
4024 sctx
->b
.create_vs_state
= si_create_shader
;
4025 sctx
->b
.create_tcs_state
= si_create_shader
;
4026 sctx
->b
.create_tes_state
= si_create_shader
;
4027 sctx
->b
.create_gs_state
= si_create_shader
;
4028 sctx
->b
.create_fs_state
= si_create_shader
;
4030 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
4031 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
4032 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
4033 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
4034 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
4036 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
4037 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
4038 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
4039 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
4040 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;