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radeonsi/gfx10: simplify NGG code in si_update_shaders
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 void *si_get_ir_binary(struct si_shader_selector *sel)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 unsigned size = 4 + ir_size + sizeof(sel->so);
68 char *result = (char*)MALLOC(size);
69 if (!result)
70 return NULL;
71
72 *((uint32_t*)result) = size;
73 memcpy(result + 4, ir_binary, ir_size);
74 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
75
76 if (sel->nir)
77 blob_finish(&blob);
78
79 return result;
80 }
81
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
84 {
85 /* data may be NULL if size == 0 */
86 if (size)
87 memcpy(ptr, data, size);
88 ptr += DIV_ROUND_UP(size, 4);
89 return ptr;
90 }
91
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
94 {
95 memcpy(data, ptr, size);
96 ptr += DIV_ROUND_UP(size, 4);
97 return ptr;
98 }
99
100 /**
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
103 */
104 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
105 {
106 *ptr++ = size;
107 return write_data(ptr, data, size);
108 }
109
110 /**
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
113 */
114 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
115 {
116 *size = *ptr++;
117 assert(*data == NULL);
118 if (!*size)
119 return ptr;
120 *data = malloc(*size);
121 return read_data(ptr, *data, *size);
122 }
123
124 /**
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
126 * as integer.
127 */
128 static void *si_get_shader_binary(struct si_shader *shader)
129 {
130 /* There is always a size of data followed by the data itself. */
131 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
132 strlen(shader->binary.llvm_ir_string) + 1 : 0;
133
134 /* Refuse to allocate overly large buffers and guard against integer
135 * overflow. */
136 if (shader->binary.elf_size > UINT_MAX / 4 ||
137 llvm_ir_size > UINT_MAX / 4)
138 return NULL;
139
140 unsigned size =
141 4 + /* total size */
142 4 + /* CRC32 of the data below */
143 align(sizeof(shader->config), 4) +
144 align(sizeof(shader->info), 4) +
145 4 + align(shader->binary.elf_size, 4) +
146 4 + align(llvm_ir_size, 4);
147 void *buffer = CALLOC(1, size);
148 uint32_t *ptr = (uint32_t*)buffer;
149
150 if (!buffer)
151 return NULL;
152
153 *ptr++ = size;
154 ptr++; /* CRC32 is calculated at the end. */
155
156 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
157 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
158 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
159 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
160 assert((char *)ptr - (char *)buffer == size);
161
162 /* Compute CRC32. */
163 ptr = (uint32_t*)buffer;
164 ptr++;
165 *ptr = util_hash_crc32(ptr + 1, size - 8);
166
167 return buffer;
168 }
169
170 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
171 {
172 uint32_t *ptr = (uint32_t*)binary;
173 uint32_t size = *ptr++;
174 uint32_t crc32 = *ptr++;
175 unsigned chunk_size;
176 unsigned elf_size;
177
178 if (util_hash_crc32(ptr, size - 8) != crc32) {
179 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
180 return false;
181 }
182
183 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
184 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
185 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
186 &elf_size);
187 shader->binary.elf_size = elf_size;
188 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
189
190 return true;
191 }
192
193 /**
194 * Insert a shader into the cache. It's assumed the shader is not in the cache.
195 * Use si_shader_cache_load_shader before calling this.
196 *
197 * Returns false on failure, in which case the ir_binary should be freed.
198 */
199 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
200 struct si_shader *shader,
201 bool insert_into_disk_cache)
202 {
203 void *hw_binary;
204 struct hash_entry *entry;
205 uint8_t key[CACHE_KEY_SIZE];
206
207 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
208 if (entry)
209 return false; /* already added */
210
211 hw_binary = si_get_shader_binary(shader);
212 if (!hw_binary)
213 return false;
214
215 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
216 hw_binary) == NULL) {
217 FREE(hw_binary);
218 return false;
219 }
220
221 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
222 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
223 *((uint32_t *)ir_binary), key);
224 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
225 *((uint32_t *) hw_binary), NULL);
226 }
227
228 return true;
229 }
230
231 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
232 struct si_shader *shader)
233 {
234 struct hash_entry *entry =
235 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
236 if (!entry) {
237 if (sscreen->disk_shader_cache) {
238 unsigned char sha1[CACHE_KEY_SIZE];
239 size_t tg_size = *((uint32_t *) ir_binary);
240
241 disk_cache_compute_key(sscreen->disk_shader_cache,
242 ir_binary, tg_size, sha1);
243
244 size_t binary_size;
245 uint8_t *buffer =
246 disk_cache_get(sscreen->disk_shader_cache,
247 sha1, &binary_size);
248 if (!buffer)
249 return false;
250
251 if (binary_size < sizeof(uint32_t) ||
252 *((uint32_t*)buffer) != binary_size) {
253 /* Something has gone wrong discard the item
254 * from the cache and rebuild/link from
255 * source.
256 */
257 assert(!"Invalid radeonsi shader disk cache "
258 "item!");
259
260 disk_cache_remove(sscreen->disk_shader_cache,
261 sha1);
262 free(buffer);
263
264 return false;
265 }
266
267 if (!si_load_shader_binary(shader, buffer)) {
268 free(buffer);
269 return false;
270 }
271 free(buffer);
272
273 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
274 shader, false))
275 FREE(ir_binary);
276 } else {
277 return false;
278 }
279 } else {
280 if (si_load_shader_binary(shader, entry->data))
281 FREE(ir_binary);
282 else
283 return false;
284 }
285 p_atomic_inc(&sscreen->num_shader_cache_hits);
286 return true;
287 }
288
289 static uint32_t si_shader_cache_key_hash(const void *key)
290 {
291 /* The first dword is the key size. */
292 return util_hash_crc32(key, *(uint32_t*)key);
293 }
294
295 static bool si_shader_cache_key_equals(const void *a, const void *b)
296 {
297 uint32_t *keya = (uint32_t*)a;
298 uint32_t *keyb = (uint32_t*)b;
299
300 /* The first dword is the key size. */
301 if (*keya != *keyb)
302 return false;
303
304 return memcmp(keya, keyb, *keya) == 0;
305 }
306
307 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
308 {
309 FREE((void*)entry->key);
310 FREE(entry->data);
311 }
312
313 bool si_init_shader_cache(struct si_screen *sscreen)
314 {
315 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
316 sscreen->shader_cache =
317 _mesa_hash_table_create(NULL,
318 si_shader_cache_key_hash,
319 si_shader_cache_key_equals);
320
321 return sscreen->shader_cache != NULL;
322 }
323
324 void si_destroy_shader_cache(struct si_screen *sscreen)
325 {
326 if (sscreen->shader_cache)
327 _mesa_hash_table_destroy(sscreen->shader_cache,
328 si_destroy_shader_cache_entry);
329 mtx_destroy(&sscreen->shader_cache_mutex);
330 }
331
332 /* SHADER STATES */
333
334 static void si_set_tesseval_regs(struct si_screen *sscreen,
335 const struct si_shader_selector *tes,
336 struct si_pm4_state *pm4)
337 {
338 const struct tgsi_shader_info *info = &tes->info;
339 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
340 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
341 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
342 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
343 unsigned type, partitioning, topology, distribution_mode;
344
345 switch (tes_prim_mode) {
346 case PIPE_PRIM_LINES:
347 type = V_028B6C_TESS_ISOLINE;
348 break;
349 case PIPE_PRIM_TRIANGLES:
350 type = V_028B6C_TESS_TRIANGLE;
351 break;
352 case PIPE_PRIM_QUADS:
353 type = V_028B6C_TESS_QUAD;
354 break;
355 default:
356 assert(0);
357 return;
358 }
359
360 switch (tes_spacing) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
362 partitioning = V_028B6C_PART_FRAC_ODD;
363 break;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
365 partitioning = V_028B6C_PART_FRAC_EVEN;
366 break;
367 case PIPE_TESS_SPACING_EQUAL:
368 partitioning = V_028B6C_PART_INTEGER;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 if (tes_point_mode)
376 topology = V_028B6C_OUTPUT_POINT;
377 else if (tes_prim_mode == PIPE_PRIM_LINES)
378 topology = V_028B6C_OUTPUT_LINE;
379 else if (tes_vertex_order_cw)
380 /* for some reason, this must be the other way around */
381 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
382 else
383 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
384
385 if (sscreen->has_distributed_tess) {
386 if (sscreen->info.family == CHIP_FIJI ||
387 sscreen->info.family >= CHIP_POLARIS10)
388 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
389 else
390 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
391 } else
392 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
393
394 assert(pm4->shader);
395 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
396 S_028B6C_PARTITIONING(partitioning) |
397 S_028B6C_TOPOLOGY(topology) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
399 }
400
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
403 *
404 * Possible VGT configurations and which state should set the register:
405 *
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
408 * VS as VS | VS | 30
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 *
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 */
415 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
416 struct si_shader_selector *sel,
417 struct si_shader *shader,
418 struct si_pm4_state *pm4)
419 {
420 unsigned type = sel->type;
421
422 if (sscreen->info.family < CHIP_POLARIS10 ||
423 sscreen->info.chip_class >= GFX10)
424 return;
425
426 /* VS as VS, or VS as ES: */
427 if ((type == PIPE_SHADER_VERTEX &&
428 (!shader ||
429 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
430 /* TES as VS, or TES as ES: */
431 type == PIPE_SHADER_TESS_EVAL) {
432 unsigned vtx_reuse_depth = 30;
433
434 if (type == PIPE_SHADER_TESS_EVAL &&
435 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD)
437 vtx_reuse_depth = 14;
438
439 assert(pm4->shader);
440 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
441 }
442 }
443
444 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
445 {
446 if (shader->pm4)
447 si_pm4_clear_state(shader->pm4);
448 else
449 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
450
451 if (shader->pm4) {
452 shader->pm4->shader = shader;
453 return shader->pm4;
454 } else {
455 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
456 return NULL;
457 }
458 }
459
460 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
461 {
462 /* Add the pointer to VBO descriptors. */
463 return num_always_on_user_sgprs + 1;
464 }
465
466 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
467 {
468 struct si_pm4_state *pm4;
469 unsigned vgpr_comp_cnt;
470 uint64_t va;
471
472 assert(sscreen->info.chip_class <= GFX8);
473
474 pm4 = si_get_shader_pm4_state(shader);
475 if (!pm4)
476 return;
477
478 va = shader->bo->gpu_address;
479 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
480
481 /* We need at least 2 components for LS.
482 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
483 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
484 */
485 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
486
487 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
488 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
489
490 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
491 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
492 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
493 S_00B528_DX10_CLAMP(1) |
494 S_00B528_FLOAT_MODE(shader->config.float_mode);
495 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
496 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
497 }
498
499 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
500 {
501 struct si_pm4_state *pm4;
502 uint64_t va;
503 unsigned ls_vgpr_comp_cnt = 0;
504
505 pm4 = si_get_shader_pm4_state(shader);
506 if (!pm4)
507 return;
508
509 va = shader->bo->gpu_address;
510 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
511
512 if (sscreen->info.chip_class >= GFX9) {
513 if (sscreen->info.chip_class >= GFX10) {
514 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
515 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
516 } else {
517 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
518 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
519 }
520
521 /* We need at least 2 components for LS.
522 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
523 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
524 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
525 * be loaded.
526 */
527 ls_vgpr_comp_cnt = 1;
528 if (shader->info.uses_instanceid) {
529 if (sscreen->info.chip_class >= GFX10)
530 ls_vgpr_comp_cnt = 3;
531 else
532 ls_vgpr_comp_cnt = 2;
533 }
534
535 unsigned num_user_sgprs =
536 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
537
538 shader->config.rsrc2 =
539 S_00B42C_USER_SGPR(num_user_sgprs) |
540 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
541
542 if (sscreen->info.chip_class >= GFX10)
543 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
544 else
545 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
546 } else {
547 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
548 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
549
550 shader->config.rsrc2 =
551 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
552 S_00B42C_OC_LDS_EN(1) |
553 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
554 }
555
556 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
557 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
558 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
559 (sscreen->info.chip_class <= GFX9 ?
560 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
561 S_00B428_DX10_CLAMP(1) |
562 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
563 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
564 S_00B428_FLOAT_MODE(shader->config.float_mode) |
565 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
566
567 if (sscreen->info.chip_class <= GFX8) {
568 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
569 shader->config.rsrc2);
570 }
571 }
572
573 static void si_emit_shader_es(struct si_context *sctx)
574 {
575 struct si_shader *shader = sctx->queued.named.es->shader;
576 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
577
578 if (!shader)
579 return;
580
581 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
582 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
583 shader->selector->esgs_itemsize / 4);
584
585 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
586 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
587 SI_TRACKED_VGT_TF_PARAM,
588 shader->vgt_tf_param);
589
590 if (shader->vgt_vertex_reuse_block_cntl)
591 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
592 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
593 shader->vgt_vertex_reuse_block_cntl);
594
595 if (initial_cdw != sctx->gfx_cs->current.cdw)
596 sctx->context_roll = true;
597 }
598
599 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
600 {
601 struct si_pm4_state *pm4;
602 unsigned num_user_sgprs;
603 unsigned vgpr_comp_cnt;
604 uint64_t va;
605 unsigned oc_lds_en;
606
607 assert(sscreen->info.chip_class <= GFX8);
608
609 pm4 = si_get_shader_pm4_state(shader);
610 if (!pm4)
611 return;
612
613 pm4->atom.emit = si_emit_shader_es;
614 va = shader->bo->gpu_address;
615 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
616
617 if (shader->selector->type == PIPE_SHADER_VERTEX) {
618 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
619 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
620 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
621 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
622 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
623 num_user_sgprs = SI_TES_NUM_USER_SGPR;
624 } else
625 unreachable("invalid shader selector type");
626
627 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
628
629 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
630 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
631 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
632 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
633 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
634 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
635 S_00B328_DX10_CLAMP(1) |
636 S_00B328_FLOAT_MODE(shader->config.float_mode));
637 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
638 S_00B32C_USER_SGPR(num_user_sgprs) |
639 S_00B32C_OC_LDS_EN(oc_lds_en) |
640 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
641
642 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
643 si_set_tesseval_regs(sscreen, shader->selector, pm4);
644
645 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
646 }
647
648 void gfx9_get_gs_info(struct si_shader_selector *es,
649 struct si_shader_selector *gs,
650 struct gfx9_gs_info *out)
651 {
652 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
653 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
654 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
655 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
656
657 /* All these are in dwords: */
658 /* We can't allow using the whole LDS, because GS waves compete with
659 * other shader stages for LDS space. */
660 const unsigned max_lds_size = 8 * 1024;
661 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
662 unsigned esgs_lds_size;
663
664 /* All these are per subgroup: */
665 const unsigned max_out_prims = 32 * 1024;
666 const unsigned max_es_verts = 255;
667 const unsigned ideal_gs_prims = 64;
668 unsigned max_gs_prims, gs_prims;
669 unsigned min_es_verts, es_verts, worst_case_es_verts;
670
671 if (uses_adjacency || gs_num_invocations > 1)
672 max_gs_prims = 127 / gs_num_invocations;
673 else
674 max_gs_prims = 255;
675
676 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
677 * Make sure we don't go over the maximum value.
678 */
679 if (gs->gs_max_out_vertices > 0) {
680 max_gs_prims = MIN2(max_gs_prims,
681 max_out_prims /
682 (gs->gs_max_out_vertices * gs_num_invocations));
683 }
684 assert(max_gs_prims > 0);
685
686 /* If the primitive has adjacency, halve the number of vertices
687 * that will be reused in multiple primitives.
688 */
689 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
690
691 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
692 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
693
694 /* Compute ESGS LDS size based on the worst case number of ES vertices
695 * needed to create the target number of GS prims per subgroup.
696 */
697 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
698
699 /* If total LDS usage is too big, refactor partitions based on ratio
700 * of ESGS item sizes.
701 */
702 if (esgs_lds_size > max_lds_size) {
703 /* Our target GS Prims Per Subgroup was too large. Calculate
704 * the maximum number of GS Prims Per Subgroup that will fit
705 * into LDS, capped by the maximum that the hardware can support.
706 */
707 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
708 max_gs_prims);
709 assert(gs_prims > 0);
710 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
711 max_es_verts);
712
713 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
714 assert(esgs_lds_size <= max_lds_size);
715 }
716
717 /* Now calculate remaining ESGS information. */
718 if (esgs_lds_size)
719 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
720 else
721 es_verts = max_es_verts;
722
723 /* Vertices for adjacency primitives are not always reused, so restore
724 * it for ES_VERTS_PER_SUBGRP.
725 */
726 min_es_verts = gs->gs_input_verts_per_prim;
727
728 /* For normal primitives, the VGT only checks if they are past the ES
729 * verts per subgroup after allocating a full GS primitive and if they
730 * are, kick off a new subgroup. But if those additional ES verts are
731 * unique (e.g. not reused) we need to make sure there is enough LDS
732 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
733 */
734 es_verts -= min_es_verts - 1;
735
736 out->es_verts_per_subgroup = es_verts;
737 out->gs_prims_per_subgroup = gs_prims;
738 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
739 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
740 gs->gs_max_out_vertices;
741 out->esgs_ring_size = 4 * esgs_lds_size;
742
743 assert(out->max_prims_per_subgroup <= max_out_prims);
744 }
745
746 static void si_emit_shader_gs(struct si_context *sctx)
747 {
748 struct si_shader *shader = sctx->queued.named.gs->shader;
749 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
750
751 if (!shader)
752 return;
753
754 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
755 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
756 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
757 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
758 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
759 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
760 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
761
762 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
763 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
764 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
765 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
766
767 /* R_028B38_VGT_GS_MAX_VERT_OUT */
768 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
769 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
770 shader->ctx_reg.gs.vgt_gs_max_vert_out);
771
772 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
773 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
774 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
775 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
776 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
777 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
778 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
779 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
780
781 /* R_028B90_VGT_GS_INSTANCE_CNT */
782 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
783 SI_TRACKED_VGT_GS_INSTANCE_CNT,
784 shader->ctx_reg.gs.vgt_gs_instance_cnt);
785
786 if (sctx->chip_class >= GFX9) {
787 /* R_028A44_VGT_GS_ONCHIP_CNTL */
788 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
789 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
790 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
791 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
792 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
793 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
794 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
795 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
796 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
797 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
798 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
799
800 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
801 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
802 SI_TRACKED_VGT_TF_PARAM,
803 shader->vgt_tf_param);
804 if (shader->vgt_vertex_reuse_block_cntl)
805 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
806 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
807 shader->vgt_vertex_reuse_block_cntl);
808 }
809
810 if (initial_cdw != sctx->gfx_cs->current.cdw)
811 sctx->context_roll = true;
812 }
813
814 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
815 {
816 struct si_shader_selector *sel = shader->selector;
817 const ubyte *num_components = sel->info.num_stream_output_components;
818 unsigned gs_num_invocations = sel->gs_num_invocations;
819 struct si_pm4_state *pm4;
820 uint64_t va;
821 unsigned max_stream = sel->max_gs_stream;
822 unsigned offset;
823
824 pm4 = si_get_shader_pm4_state(shader);
825 if (!pm4)
826 return;
827
828 pm4->atom.emit = si_emit_shader_gs;
829
830 offset = num_components[0] * sel->gs_max_out_vertices;
831 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
832
833 if (max_stream >= 1)
834 offset += num_components[1] * sel->gs_max_out_vertices;
835 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
836
837 if (max_stream >= 2)
838 offset += num_components[2] * sel->gs_max_out_vertices;
839 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
840
841 if (max_stream >= 3)
842 offset += num_components[3] * sel->gs_max_out_vertices;
843 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
844
845 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
846 assert(offset < (1 << 15));
847
848 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
849
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
851 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
852 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
853 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
854
855 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
856 S_028B90_ENABLE(gs_num_invocations > 0);
857
858 va = shader->bo->gpu_address;
859 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
860
861 if (sscreen->info.chip_class >= GFX9) {
862 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
863 unsigned es_type = shader->key.part.gs.es->type;
864 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
865
866 if (es_type == PIPE_SHADER_VERTEX)
867 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
868 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
869 else if (es_type == PIPE_SHADER_TESS_EVAL)
870 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
871 else
872 unreachable("invalid shader selector type");
873
874 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
875 * VGPR[0:4] are always loaded.
876 */
877 if (sel->info.uses_invocationid)
878 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
879 else if (sel->info.uses_primid)
880 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
881 else if (input_prim >= PIPE_PRIM_TRIANGLES)
882 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
883 else
884 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
885
886 unsigned num_user_sgprs;
887 if (es_type == PIPE_SHADER_VERTEX)
888 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
889 else
890 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
891
892 if (sscreen->info.chip_class >= GFX10) {
893 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
894 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
895 } else {
896 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
897 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
898 }
899
900 uint32_t rsrc1 =
901 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
902 S_00B228_DX10_CLAMP(1) |
903 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
904 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
905 S_00B228_FLOAT_MODE(shader->config.float_mode) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
907 uint32_t rsrc2 =
908 S_00B22C_USER_SGPR(num_user_sgprs) |
909 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
910 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
911 S_00B22C_LDS_SIZE(shader->config.lds_size) |
912 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
913
914 if (sscreen->info.chip_class >= GFX10) {
915 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
916 } else {
917 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
918 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
919 }
920
921 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
922 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
923
924 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
925 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
926 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
927 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
928 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
929 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
930 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
931 shader->key.part.gs.es->esgs_itemsize / 4;
932
933 if (es_type == PIPE_SHADER_TESS_EVAL)
934 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
935
936 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
937 NULL, pm4);
938 } else {
939 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
940 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
941
942 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
943 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
944 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
945 S_00B228_DX10_CLAMP(1) |
946 S_00B228_FLOAT_MODE(shader->config.float_mode));
947 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
948 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
949 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
950 }
951 }
952
953 /* Common tail code for NGG primitive shaders. */
954 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
955 struct si_shader *shader,
956 unsigned initial_cdw)
957 {
958 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
959 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
960 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
961 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
962 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
963 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
964 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
965 SI_TRACKED_VGT_PRIMITIVEID_EN,
966 shader->ctx_reg.ngg.vgt_primitiveid_en);
967 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
968 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
969 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
970 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
971 SI_TRACKED_VGT_GS_INSTANCE_CNT,
972 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
973 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
974 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
975 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
976 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
977 SI_TRACKED_VGT_REUSE_OFF,
978 shader->ctx_reg.ngg.vgt_reuse_off);
979 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
980 SI_TRACKED_SPI_VS_OUT_CONFIG,
981 shader->ctx_reg.ngg.spi_vs_out_config);
982 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
983 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
984 shader->ctx_reg.ngg.spi_shader_idx_format,
985 shader->ctx_reg.ngg.spi_shader_pos_format);
986 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
987 SI_TRACKED_PA_CL_VTE_CNTL,
988 shader->ctx_reg.ngg.pa_cl_vte_cntl);
989 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
990 SI_TRACKED_PA_CL_NGG_CNTL,
991 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
992
993 if (initial_cdw != sctx->gfx_cs->current.cdw)
994 sctx->context_roll = true;
995 }
996
997 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
998 {
999 struct si_shader *shader = sctx->queued.named.gs->shader;
1000 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1001
1002 if (!shader)
1003 return;
1004
1005 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1006 }
1007
1008 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1009 {
1010 struct si_shader *shader = sctx->queued.named.gs->shader;
1011 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1012
1013 if (!shader)
1014 return;
1015
1016 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1017 SI_TRACKED_VGT_TF_PARAM,
1018 shader->vgt_tf_param);
1019
1020 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1021 }
1022
1023 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1024 {
1025 struct si_shader *shader = sctx->queued.named.gs->shader;
1026 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1027
1028 if (!shader)
1029 return;
1030
1031 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1032 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1033 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1034
1035 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1036 }
1037
1038 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1039 {
1040 struct si_shader *shader = sctx->queued.named.gs->shader;
1041 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1042
1043 if (!shader)
1044 return;
1045
1046 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1047 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1048 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1049 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1050 SI_TRACKED_VGT_TF_PARAM,
1051 shader->vgt_tf_param);
1052
1053 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1054 }
1055
1056 static void si_set_ge_pc_alloc(struct si_screen *sscreen,
1057 struct si_pm4_state *pm4, bool culling)
1058 {
1059 si_pm4_set_reg(pm4, R_030980_GE_PC_ALLOC,
1060 S_030980_OVERSUB_EN(1) |
1061 S_030980_NUM_PC_LINES((culling ? 256 : 128) * sscreen->info.max_se - 1));
1062 }
1063
1064 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1065 {
1066 if (gs->type == PIPE_SHADER_GEOMETRY)
1067 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1068
1069 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1070 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1071 return PIPE_PRIM_POINTS;
1072 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1073 return PIPE_PRIM_LINES;
1074 return PIPE_PRIM_TRIANGLES;
1075 }
1076
1077 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1078 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1079 }
1080
1081 /**
1082 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1083 * in NGG mode.
1084 */
1085 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1086 {
1087 const struct si_shader_selector *gs_sel = shader->selector;
1088 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1089 enum pipe_shader_type gs_type = shader->selector->type;
1090 const struct si_shader_selector *es_sel =
1091 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1092 const struct tgsi_shader_info *es_info = &es_sel->info;
1093 enum pipe_shader_type es_type = es_sel->type;
1094 unsigned num_user_sgprs;
1095 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1096 uint64_t va;
1097 unsigned window_space =
1098 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1099 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1100 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1101 unsigned input_prim = si_get_input_prim(gs_sel);
1102 bool break_wave_at_eoi = false;
1103 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1104 if (!pm4)
1105 return;
1106
1107 if (es_type == PIPE_SHADER_TESS_EVAL) {
1108 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1109 : gfx10_emit_shader_ngg_tess_nogs;
1110 } else {
1111 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1112 : gfx10_emit_shader_ngg_notess_nogs;
1113 }
1114
1115 va = shader->bo->gpu_address;
1116 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1117
1118 if (es_type == PIPE_SHADER_VERTEX) {
1119 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1120 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1121
1122 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1123 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1124 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1125 } else {
1126 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1127 }
1128 } else {
1129 assert(es_type == PIPE_SHADER_TESS_EVAL);
1130 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1131 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1132
1133 if (es_enable_prim_id || gs_info->uses_primid)
1134 break_wave_at_eoi = true;
1135 }
1136
1137 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1138 * VGPR[0:4] are always loaded.
1139 *
1140 * Vertex shaders always need to load VGPR3, because they need to
1141 * pass edge flags for decomposed primitives (such as quads) to the PA
1142 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1143 */
1144 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1145 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1146 else if (gs_info->uses_primid)
1147 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1148 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1149 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1150 else
1151 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1152
1153 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1154 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1155 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1156 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1157 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1158 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1159 S_00B228_DX10_CLAMP(1) |
1160 S_00B228_MEM_ORDERED(1) |
1161 S_00B228_WGP_MODE(1) |
1162 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1163 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1164 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1165 S_00B22C_USER_SGPR(num_user_sgprs) |
1166 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1167 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1168 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1169 S_00B22C_LDS_SIZE(shader->config.lds_size));
1170 si_set_ge_pc_alloc(sscreen, pm4, false);
1171
1172 nparams = MAX2(shader->info.nr_param_exports, 1);
1173 shader->ctx_reg.ngg.spi_vs_out_config =
1174 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1175 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1176
1177 shader->ctx_reg.ngg.spi_shader_idx_format =
1178 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1179 shader->ctx_reg.ngg.spi_shader_pos_format =
1180 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1181 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1182 V_02870C_SPI_SHADER_4COMP :
1183 V_02870C_SPI_SHADER_NONE) |
1184 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1185 V_02870C_SPI_SHADER_4COMP :
1186 V_02870C_SPI_SHADER_NONE) |
1187 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1188 V_02870C_SPI_SHADER_4COMP :
1189 V_02870C_SPI_SHADER_NONE);
1190
1191 shader->ctx_reg.ngg.vgt_primitiveid_en =
1192 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1193 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1194
1195 if (gs_type == PIPE_SHADER_GEOMETRY) {
1196 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1197 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1198 } else {
1199 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1200 }
1201
1202 if (es_type == PIPE_SHADER_TESS_EVAL)
1203 si_set_tesseval_regs(sscreen, es_sel, pm4);
1204
1205 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1206 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1207 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1208 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1209 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1210 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1211 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1212 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1213 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1214 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1215 S_028B90_CNT(gs_num_invocations) |
1216 S_028B90_ENABLE(gs_num_invocations > 1) |
1217 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1218 shader->ngg.max_vert_out_per_gs_instance);
1219
1220 /* Always output hw-generated edge flags and pass them via the prim
1221 * export to prevent drawing lines on internal edges of decomposed
1222 * primitives (such as quads) with polygon mode = lines. Only VS needs
1223 * this.
1224 */
1225 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1226 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1227
1228 shader->ge_cntl =
1229 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1230 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1231 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1232
1233 if (window_space) {
1234 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1235 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1236 } else {
1237 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1238 S_028818_VTX_W0_FMT(1) |
1239 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1240 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1241 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1242 }
1243
1244 shader->ctx_reg.ngg.vgt_reuse_off =
1245 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1246 sscreen->info.chip_external_rev == 0x1 &&
1247 es_type == PIPE_SHADER_TESS_EVAL);
1248 }
1249
1250 static void si_emit_shader_vs(struct si_context *sctx)
1251 {
1252 struct si_shader *shader = sctx->queued.named.vs->shader;
1253 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1254
1255 if (!shader)
1256 return;
1257
1258 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1259 SI_TRACKED_VGT_GS_MODE,
1260 shader->ctx_reg.vs.vgt_gs_mode);
1261 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1262 SI_TRACKED_VGT_PRIMITIVEID_EN,
1263 shader->ctx_reg.vs.vgt_primitiveid_en);
1264
1265 if (sctx->chip_class <= GFX8) {
1266 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1267 SI_TRACKED_VGT_REUSE_OFF,
1268 shader->ctx_reg.vs.vgt_reuse_off);
1269 }
1270
1271 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1272 SI_TRACKED_SPI_VS_OUT_CONFIG,
1273 shader->ctx_reg.vs.spi_vs_out_config);
1274
1275 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1276 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1277 shader->ctx_reg.vs.spi_shader_pos_format);
1278
1279 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1280 SI_TRACKED_PA_CL_VTE_CNTL,
1281 shader->ctx_reg.vs.pa_cl_vte_cntl);
1282
1283 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1284 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1285 SI_TRACKED_VGT_TF_PARAM,
1286 shader->vgt_tf_param);
1287
1288 if (shader->vgt_vertex_reuse_block_cntl)
1289 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1290 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1291 shader->vgt_vertex_reuse_block_cntl);
1292
1293 if (initial_cdw != sctx->gfx_cs->current.cdw)
1294 sctx->context_roll = true;
1295 }
1296
1297 /**
1298 * Compute the state for \p shader, which will run as a vertex shader on the
1299 * hardware.
1300 *
1301 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1302 * is the copy shader.
1303 */
1304 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1305 struct si_shader_selector *gs)
1306 {
1307 const struct tgsi_shader_info *info = &shader->selector->info;
1308 struct si_pm4_state *pm4;
1309 unsigned num_user_sgprs, vgpr_comp_cnt;
1310 uint64_t va;
1311 unsigned nparams, oc_lds_en;
1312 unsigned window_space =
1313 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1314 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1315
1316 pm4 = si_get_shader_pm4_state(shader);
1317 if (!pm4)
1318 return;
1319
1320 pm4->atom.emit = si_emit_shader_vs;
1321
1322 /* We always write VGT_GS_MODE in the VS state, because every switch
1323 * between different shader pipelines involving a different GS or no
1324 * GS at all involves a switch of the VS (different GS use different
1325 * copy shaders). On the other hand, when the API switches from a GS to
1326 * no GS and then back to the same GS used originally, the GS state is
1327 * not sent again.
1328 */
1329 if (!gs) {
1330 unsigned mode = V_028A40_GS_OFF;
1331
1332 /* PrimID needs GS scenario A. */
1333 if (enable_prim_id)
1334 mode = V_028A40_GS_SCENARIO_A;
1335
1336 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1337 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1338 } else {
1339 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1340 sscreen->info.chip_class);
1341 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1342 }
1343
1344 if (sscreen->info.chip_class <= GFX8) {
1345 /* Reuse needs to be set off if we write oViewport. */
1346 shader->ctx_reg.vs.vgt_reuse_off =
1347 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1348 }
1349
1350 va = shader->bo->gpu_address;
1351 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1352
1353 if (gs) {
1354 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1355 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1356 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1357 if (sscreen->info.chip_class >= GFX10) {
1358 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
1359 } else {
1360 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1361 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1362 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1363 */
1364 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1365 }
1366
1367 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1368 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1369 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1370 } else {
1371 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1372 }
1373 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1374 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1375 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1376 } else
1377 unreachable("invalid shader selector type");
1378
1379 /* VS is required to export at least one param. */
1380 nparams = MAX2(shader->info.nr_param_exports, 1);
1381 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1382
1383 if (sscreen->info.chip_class >= GFX10) {
1384 shader->ctx_reg.vs.spi_vs_out_config |=
1385 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1386 }
1387
1388 shader->ctx_reg.vs.spi_shader_pos_format =
1389 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1390 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1391 V_02870C_SPI_SHADER_4COMP :
1392 V_02870C_SPI_SHADER_NONE) |
1393 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1394 V_02870C_SPI_SHADER_4COMP :
1395 V_02870C_SPI_SHADER_NONE) |
1396 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1397 V_02870C_SPI_SHADER_4COMP :
1398 V_02870C_SPI_SHADER_NONE);
1399
1400 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1401
1402 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1403 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1404 if (sscreen->info.chip_class >= GFX10)
1405 si_set_ge_pc_alloc(sscreen, pm4, false);
1406
1407 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1408 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1409 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1410 S_00B128_DX10_CLAMP(1) |
1411 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1412 S_00B128_FLOAT_MODE(shader->config.float_mode);
1413 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1414 S_00B12C_OC_LDS_EN(oc_lds_en) |
1415 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1416
1417 if (sscreen->info.chip_class <= GFX9) {
1418 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1419 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1420 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1421 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1422 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1423 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1424 }
1425
1426 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1427 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1428
1429 if (window_space)
1430 shader->ctx_reg.vs.pa_cl_vte_cntl =
1431 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1432 else
1433 shader->ctx_reg.vs.pa_cl_vte_cntl =
1434 S_028818_VTX_W0_FMT(1) |
1435 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1436 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1437 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1438
1439 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1440 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1441
1442 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1443 }
1444
1445 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1446 {
1447 struct tgsi_shader_info *info = &ps->selector->info;
1448 unsigned num_colors = !!(info->colors_read & 0x0f) +
1449 !!(info->colors_read & 0xf0);
1450 unsigned num_interp = ps->selector->info.num_inputs +
1451 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1452
1453 assert(num_interp <= 32);
1454 return MIN2(num_interp, 32);
1455 }
1456
1457 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1458 {
1459 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1460 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1461
1462 /* If the i-th target format is set, all previous target formats must
1463 * be non-zero to avoid hangs.
1464 */
1465 for (i = 0; i < num_targets; i++)
1466 if (!(value & (0xf << (i * 4))))
1467 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1468
1469 return value;
1470 }
1471
1472 static void si_emit_shader_ps(struct si_context *sctx)
1473 {
1474 struct si_shader *shader = sctx->queued.named.ps->shader;
1475 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1476
1477 if (!shader)
1478 return;
1479
1480 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1481 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1482 SI_TRACKED_SPI_PS_INPUT_ENA,
1483 shader->ctx_reg.ps.spi_ps_input_ena,
1484 shader->ctx_reg.ps.spi_ps_input_addr);
1485
1486 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1487 SI_TRACKED_SPI_BARYC_CNTL,
1488 shader->ctx_reg.ps.spi_baryc_cntl);
1489 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1490 SI_TRACKED_SPI_PS_IN_CONTROL,
1491 shader->ctx_reg.ps.spi_ps_in_control);
1492
1493 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1494 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1495 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1496 shader->ctx_reg.ps.spi_shader_z_format,
1497 shader->ctx_reg.ps.spi_shader_col_format);
1498
1499 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1500 SI_TRACKED_CB_SHADER_MASK,
1501 shader->ctx_reg.ps.cb_shader_mask);
1502
1503 if (initial_cdw != sctx->gfx_cs->current.cdw)
1504 sctx->context_roll = true;
1505 }
1506
1507 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1508 {
1509 struct tgsi_shader_info *info = &shader->selector->info;
1510 struct si_pm4_state *pm4;
1511 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1512 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1513 uint64_t va;
1514 unsigned input_ena = shader->config.spi_ps_input_ena;
1515
1516 /* we need to enable at least one of them, otherwise we hang the GPU */
1517 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1518 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1519 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1520 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1521 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1522 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1523 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1524 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1525 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1526 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1527 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1528 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1529 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1530 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1531
1532 /* Validate interpolation optimization flags (read as implications). */
1533 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1534 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1535 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1536 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1537 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1538 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1539 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1540 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1541 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1542 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1543 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1544 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1545 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1546 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1547 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1548 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1549 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1550 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1551
1552 /* Validate cases when the optimizations are off (read as implications). */
1553 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1554 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1555 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1556 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1557 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1558 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1559
1560 pm4 = si_get_shader_pm4_state(shader);
1561 if (!pm4)
1562 return;
1563
1564 pm4->atom.emit = si_emit_shader_ps;
1565
1566 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1567 * Possible vaules:
1568 * 0 -> Position = pixel center
1569 * 1 -> Position = pixel centroid
1570 * 2 -> Position = at sample position
1571 *
1572 * From GLSL 4.5 specification, section 7.1:
1573 * "The variable gl_FragCoord is available as an input variable from
1574 * within fragment shaders and it holds the window relative coordinates
1575 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1576 * value can be for any location within the pixel, or one of the
1577 * fragment samples. The use of centroid does not further restrict
1578 * this value to be inside the current primitive."
1579 *
1580 * Meaning that centroid has no effect and we can return anything within
1581 * the pixel. Thus, return the value at sample position, because that's
1582 * the most accurate one shaders can get.
1583 */
1584 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1585
1586 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1587 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1588 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1589
1590 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1591 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1592
1593 /* Ensure that some export memory is always allocated, for two reasons:
1594 *
1595 * 1) Correctness: The hardware ignores the EXEC mask if no export
1596 * memory is allocated, so KILL and alpha test do not work correctly
1597 * without this.
1598 * 2) Performance: Every shader needs at least a NULL export, even when
1599 * it writes no color/depth output. The NULL export instruction
1600 * stalls without this setting.
1601 *
1602 * Don't add this to CB_SHADER_MASK.
1603 *
1604 * GFX10 supports pixel shaders without exports by setting both
1605 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1606 * instructions if any are present.
1607 */
1608 if ((sscreen->info.chip_class <= GFX9 ||
1609 info->uses_kill ||
1610 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1611 !spi_shader_col_format &&
1612 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1613 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1614
1615 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1616 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1617
1618 /* Set interpolation controls. */
1619 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1620 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1621
1622 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1623 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1624 shader->ctx_reg.ps.spi_shader_z_format =
1625 ac_get_spi_shader_z_format(info->writes_z,
1626 info->writes_stencil,
1627 info->writes_samplemask);
1628 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1629 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1630
1631 va = shader->bo->gpu_address;
1632 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1633 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1634 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1635
1636 uint32_t rsrc1 =
1637 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1638 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1639 S_00B028_DX10_CLAMP(1) |
1640 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1641 S_00B028_FLOAT_MODE(shader->config.float_mode);
1642
1643 if (sscreen->info.chip_class < GFX10) {
1644 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1645 }
1646
1647 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1648 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1649 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1650 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1651 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1652 }
1653
1654 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1655 struct si_shader *shader)
1656 {
1657 switch (shader->selector->type) {
1658 case PIPE_SHADER_VERTEX:
1659 if (shader->key.as_ls)
1660 si_shader_ls(sscreen, shader);
1661 else if (shader->key.as_es)
1662 si_shader_es(sscreen, shader);
1663 else if (shader->key.as_ngg)
1664 gfx10_shader_ngg(sscreen, shader);
1665 else
1666 si_shader_vs(sscreen, shader, NULL);
1667 break;
1668 case PIPE_SHADER_TESS_CTRL:
1669 si_shader_hs(sscreen, shader);
1670 break;
1671 case PIPE_SHADER_TESS_EVAL:
1672 if (shader->key.as_es)
1673 si_shader_es(sscreen, shader);
1674 else if (shader->key.as_ngg)
1675 gfx10_shader_ngg(sscreen, shader);
1676 else
1677 si_shader_vs(sscreen, shader, NULL);
1678 break;
1679 case PIPE_SHADER_GEOMETRY:
1680 if (shader->key.as_ngg)
1681 gfx10_shader_ngg(sscreen, shader);
1682 else
1683 si_shader_gs(sscreen, shader);
1684 break;
1685 case PIPE_SHADER_FRAGMENT:
1686 si_shader_ps(sscreen, shader);
1687 break;
1688 default:
1689 assert(0);
1690 }
1691 }
1692
1693 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1694 {
1695 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1696 return sctx->queued.named.dsa->alpha_func;
1697 }
1698
1699 void si_shader_selector_key_vs(struct si_context *sctx,
1700 struct si_shader_selector *vs,
1701 struct si_shader_key *key,
1702 struct si_vs_prolog_bits *prolog_key)
1703 {
1704 if (!sctx->vertex_elements ||
1705 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1706 return;
1707
1708 struct si_vertex_elements *elts = sctx->vertex_elements;
1709
1710 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1711 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1712 prolog_key->unpack_instance_id_from_vertex_id =
1713 sctx->prim_discard_cs_instancing;
1714
1715 /* Prefer a monolithic shader to allow scheduling divisions around
1716 * VBO loads. */
1717 if (prolog_key->instance_divisor_is_fetched)
1718 key->opt.prefer_mono = 1;
1719
1720 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1721 unsigned count_mask = (1 << count) - 1;
1722 unsigned fix = elts->fix_fetch_always & count_mask;
1723 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1724
1725 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1726 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1727 while (mask) {
1728 unsigned i = u_bit_scan(&mask);
1729 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1730 unsigned vbidx = elts->vertex_buffer_index[i];
1731 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1732 unsigned align_mask = (1 << log_hw_load_size) - 1;
1733 if (vb->buffer_offset & align_mask ||
1734 vb->stride & align_mask) {
1735 fix |= 1 << i;
1736 opencode |= 1 << i;
1737 }
1738 }
1739 }
1740
1741 while (fix) {
1742 unsigned i = u_bit_scan(&fix);
1743 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1744 }
1745 key->mono.vs_fetch_opencode = opencode;
1746 }
1747
1748 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1749 struct si_shader_selector *vs,
1750 struct si_shader_key *key)
1751 {
1752 struct si_shader_selector *ps = sctx->ps_shader.cso;
1753
1754 key->opt.clip_disable =
1755 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1756 (vs->info.clipdist_writemask ||
1757 vs->info.writes_clipvertex) &&
1758 !vs->info.culldist_writemask;
1759
1760 /* Find out if PS is disabled. */
1761 bool ps_disabled = true;
1762 if (ps) {
1763 bool ps_modifies_zs = ps->info.uses_kill ||
1764 ps->info.writes_z ||
1765 ps->info.writes_stencil ||
1766 ps->info.writes_samplemask ||
1767 sctx->queued.named.blend->alpha_to_coverage ||
1768 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1769 unsigned ps_colormask = si_get_total_colormask(sctx);
1770
1771 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1772 (!ps_colormask &&
1773 !ps_modifies_zs &&
1774 !ps->info.writes_memory);
1775 }
1776
1777 /* Find out which VS outputs aren't used by the PS. */
1778 uint64_t outputs_written = vs->outputs_written_before_ps;
1779 uint64_t inputs_read = 0;
1780
1781 /* Ignore outputs that are not passed from VS to PS. */
1782 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1783 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1784 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1785
1786 if (!ps_disabled) {
1787 inputs_read = ps->inputs_read;
1788 }
1789
1790 uint64_t linked = outputs_written & inputs_read;
1791
1792 key->opt.kill_outputs = ~linked & outputs_written;
1793 }
1794
1795 /* Compute the key for the hw shader variant */
1796 static inline void si_shader_selector_key(struct pipe_context *ctx,
1797 struct si_shader_selector *sel,
1798 union si_vgt_stages_key stages_key,
1799 struct si_shader_key *key)
1800 {
1801 struct si_context *sctx = (struct si_context *)ctx;
1802
1803 memset(key, 0, sizeof(*key));
1804
1805 switch (sel->type) {
1806 case PIPE_SHADER_VERTEX:
1807 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1808
1809 if (sctx->tes_shader.cso)
1810 key->as_ls = 1;
1811 else if (sctx->gs_shader.cso)
1812 key->as_es = 1;
1813 else {
1814 key->as_ngg = stages_key.u.ngg;
1815 si_shader_selector_key_hw_vs(sctx, sel, key);
1816
1817 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1818 key->mono.u.vs_export_prim_id = 1;
1819 }
1820 break;
1821 case PIPE_SHADER_TESS_CTRL:
1822 if (sctx->chip_class >= GFX9) {
1823 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1824 key, &key->part.tcs.ls_prolog);
1825 key->part.tcs.ls = sctx->vs_shader.cso;
1826
1827 /* When the LS VGPR fix is needed, monolithic shaders
1828 * can:
1829 * - avoid initializing EXEC in both the LS prolog
1830 * and the LS main part when !vs_needs_prolog
1831 * - remove the fixup for unused input VGPRs
1832 */
1833 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1834
1835 /* The LS output / HS input layout can be communicated
1836 * directly instead of via user SGPRs for merged LS-HS.
1837 * The LS VGPR fix prefers this too.
1838 */
1839 key->opt.prefer_mono = 1;
1840 }
1841
1842 key->part.tcs.epilog.prim_mode =
1843 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1844 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1845 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1846 key->part.tcs.epilog.tes_reads_tess_factors =
1847 sctx->tes_shader.cso->info.reads_tess_factors;
1848
1849 if (sel == sctx->fixed_func_tcs_shader.cso)
1850 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1851 break;
1852 case PIPE_SHADER_TESS_EVAL:
1853 key->as_ngg = stages_key.u.ngg;
1854
1855 if (sctx->gs_shader.cso)
1856 key->as_es = 1;
1857 else {
1858 si_shader_selector_key_hw_vs(sctx, sel, key);
1859
1860 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1861 key->mono.u.vs_export_prim_id = 1;
1862 }
1863 break;
1864 case PIPE_SHADER_GEOMETRY:
1865 if (sctx->chip_class >= GFX9) {
1866 if (sctx->tes_shader.cso) {
1867 key->part.gs.es = sctx->tes_shader.cso;
1868 } else {
1869 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1870 key, &key->part.gs.vs_prolog);
1871 key->part.gs.es = sctx->vs_shader.cso;
1872 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1873 }
1874
1875 key->as_ngg = stages_key.u.ngg;
1876
1877 /* Merged ES-GS can have unbalanced wave usage.
1878 *
1879 * ES threads are per-vertex, while GS threads are
1880 * per-primitive. So without any amplification, there
1881 * are fewer GS threads than ES threads, which can result
1882 * in empty (no-op) GS waves. With too much amplification,
1883 * there are more GS threads than ES threads, which
1884 * can result in empty (no-op) ES waves.
1885 *
1886 * Non-monolithic shaders are implemented by setting EXEC
1887 * at the beginning of shader parts, and don't jump to
1888 * the end if EXEC is 0.
1889 *
1890 * Monolithic shaders use conditional blocks, so they can
1891 * jump and skip empty waves of ES or GS. So set this to
1892 * always use optimized variants, which are monolithic.
1893 */
1894 key->opt.prefer_mono = 1;
1895 }
1896 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1897 break;
1898 case PIPE_SHADER_FRAGMENT: {
1899 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1900 struct si_state_blend *blend = sctx->queued.named.blend;
1901
1902 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1903 sel->info.colors_written == 0x1)
1904 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1905
1906 /* Select the shader color format based on whether
1907 * blending or alpha are needed.
1908 */
1909 key->part.ps.epilog.spi_shader_col_format =
1910 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1911 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1912 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1913 sctx->framebuffer.spi_shader_col_format_blend) |
1914 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1915 sctx->framebuffer.spi_shader_col_format_alpha) |
1916 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1917 sctx->framebuffer.spi_shader_col_format);
1918 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1919
1920 /* The output for dual source blending should have
1921 * the same format as the first output.
1922 */
1923 if (blend->dual_src_blend) {
1924 key->part.ps.epilog.spi_shader_col_format |=
1925 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1926 }
1927
1928 /* If alpha-to-coverage is enabled, we have to export alpha
1929 * even if there is no color buffer.
1930 */
1931 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1932 blend->alpha_to_coverage)
1933 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1934
1935 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1936 * to the range supported by the type if a channel has less
1937 * than 16 bits and the export format is 16_ABGR.
1938 */
1939 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1940 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1941 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1942 }
1943
1944 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1945 if (!key->part.ps.epilog.last_cbuf) {
1946 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1947 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1948 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1949 }
1950
1951 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1952 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1953
1954 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1955 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1956
1957 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
1958 rs->multisample_enable;
1959
1960 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1961 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1962 (is_line && rs->line_smooth)) &&
1963 sctx->framebuffer.nr_samples <= 1;
1964 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1965
1966 if (sctx->ps_iter_samples > 1 &&
1967 sel->info.reads_samplemask) {
1968 key->part.ps.prolog.samplemask_log_ps_iter =
1969 util_logbase2(sctx->ps_iter_samples);
1970 }
1971
1972 if (rs->force_persample_interp &&
1973 rs->multisample_enable &&
1974 sctx->framebuffer.nr_samples > 1 &&
1975 sctx->ps_iter_samples > 1) {
1976 key->part.ps.prolog.force_persp_sample_interp =
1977 sel->info.uses_persp_center ||
1978 sel->info.uses_persp_centroid;
1979
1980 key->part.ps.prolog.force_linear_sample_interp =
1981 sel->info.uses_linear_center ||
1982 sel->info.uses_linear_centroid;
1983 } else if (rs->multisample_enable &&
1984 sctx->framebuffer.nr_samples > 1) {
1985 key->part.ps.prolog.bc_optimize_for_persp =
1986 sel->info.uses_persp_center &&
1987 sel->info.uses_persp_centroid;
1988 key->part.ps.prolog.bc_optimize_for_linear =
1989 sel->info.uses_linear_center &&
1990 sel->info.uses_linear_centroid;
1991 } else {
1992 /* Make sure SPI doesn't compute more than 1 pair
1993 * of (i,j), which is the optimization here. */
1994 key->part.ps.prolog.force_persp_center_interp =
1995 sel->info.uses_persp_center +
1996 sel->info.uses_persp_centroid +
1997 sel->info.uses_persp_sample > 1;
1998
1999 key->part.ps.prolog.force_linear_center_interp =
2000 sel->info.uses_linear_center +
2001 sel->info.uses_linear_centroid +
2002 sel->info.uses_linear_sample > 1;
2003
2004 if (sel->info.uses_persp_opcode_interp_sample ||
2005 sel->info.uses_linear_opcode_interp_sample)
2006 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2007 }
2008
2009 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2010
2011 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2012 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2013 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2014 struct pipe_resource *tex = cb0->texture;
2015
2016 /* 1D textures are allocated and used as 2D on GFX9. */
2017 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2018 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2019 (tex->target == PIPE_TEXTURE_1D ||
2020 tex->target == PIPE_TEXTURE_1D_ARRAY);
2021 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2022 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2023 tex->target == PIPE_TEXTURE_CUBE ||
2024 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2025 tex->target == PIPE_TEXTURE_3D;
2026 }
2027 break;
2028 }
2029 default:
2030 assert(0);
2031 }
2032
2033 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2034 memset(&key->opt, 0, sizeof(key->opt));
2035 }
2036
2037 static void si_build_shader_variant(struct si_shader *shader,
2038 int thread_index,
2039 bool low_priority)
2040 {
2041 struct si_shader_selector *sel = shader->selector;
2042 struct si_screen *sscreen = sel->screen;
2043 struct ac_llvm_compiler *compiler;
2044 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2045
2046 if (thread_index >= 0) {
2047 if (low_priority) {
2048 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2049 compiler = &sscreen->compiler_lowp[thread_index];
2050 } else {
2051 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2052 compiler = &sscreen->compiler[thread_index];
2053 }
2054 if (!debug->async)
2055 debug = NULL;
2056 } else {
2057 assert(!low_priority);
2058 compiler = shader->compiler_ctx_state.compiler;
2059 }
2060
2061 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2062 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2063 sel->type);
2064 shader->compilation_failed = true;
2065 return;
2066 }
2067
2068 if (shader->compiler_ctx_state.is_debug_context) {
2069 FILE *f = open_memstream(&shader->shader_log,
2070 &shader->shader_log_size);
2071 if (f) {
2072 si_shader_dump(sscreen, shader, NULL, f, false);
2073 fclose(f);
2074 }
2075 }
2076
2077 si_shader_init_pm4_state(sscreen, shader);
2078 }
2079
2080 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2081 {
2082 struct si_shader *shader = (struct si_shader *)job;
2083
2084 assert(thread_index >= 0);
2085
2086 si_build_shader_variant(shader, thread_index, true);
2087 }
2088
2089 static const struct si_shader_key zeroed;
2090
2091 static bool si_check_missing_main_part(struct si_screen *sscreen,
2092 struct si_shader_selector *sel,
2093 struct si_compiler_ctx_state *compiler_state,
2094 struct si_shader_key *key)
2095 {
2096 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2097
2098 if (!*mainp) {
2099 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2100
2101 if (!main_part)
2102 return false;
2103
2104 /* We can leave the fence as permanently signaled because the
2105 * main part becomes visible globally only after it has been
2106 * compiled. */
2107 util_queue_fence_init(&main_part->ready);
2108
2109 main_part->selector = sel;
2110 main_part->key.as_es = key->as_es;
2111 main_part->key.as_ls = key->as_ls;
2112 main_part->key.as_ngg = key->as_ngg;
2113 main_part->is_monolithic = false;
2114
2115 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2116 main_part, &compiler_state->debug) != 0) {
2117 FREE(main_part);
2118 return false;
2119 }
2120 *mainp = main_part;
2121 }
2122 return true;
2123 }
2124
2125 /**
2126 * Select a shader variant according to the shader key.
2127 *
2128 * \param optimized_or_none If the key describes an optimized shader variant and
2129 * the compilation isn't finished, don't select any
2130 * shader and return an error.
2131 */
2132 int si_shader_select_with_key(struct si_screen *sscreen,
2133 struct si_shader_ctx_state *state,
2134 struct si_compiler_ctx_state *compiler_state,
2135 struct si_shader_key *key,
2136 int thread_index,
2137 bool optimized_or_none)
2138 {
2139 struct si_shader_selector *sel = state->cso;
2140 struct si_shader_selector *previous_stage_sel = NULL;
2141 struct si_shader *current = state->current;
2142 struct si_shader *iter, *shader = NULL;
2143
2144 again:
2145 /* Check if we don't need to change anything.
2146 * This path is also used for most shaders that don't need multiple
2147 * variants, it will cost just a computation of the key and this
2148 * test. */
2149 if (likely(current &&
2150 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2151 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2152 if (current->is_optimized) {
2153 if (optimized_or_none)
2154 return -1;
2155
2156 memset(&key->opt, 0, sizeof(key->opt));
2157 goto current_not_ready;
2158 }
2159
2160 util_queue_fence_wait(&current->ready);
2161 }
2162
2163 return current->compilation_failed ? -1 : 0;
2164 }
2165 current_not_ready:
2166
2167 /* This must be done before the mutex is locked, because async GS
2168 * compilation calls this function too, and therefore must enter
2169 * the mutex first.
2170 *
2171 * Only wait if we are in a draw call. Don't wait if we are
2172 * in a compiler thread.
2173 */
2174 if (thread_index < 0)
2175 util_queue_fence_wait(&sel->ready);
2176
2177 mtx_lock(&sel->mutex);
2178
2179 /* Find the shader variant. */
2180 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2181 /* Don't check the "current" shader. We checked it above. */
2182 if (current != iter &&
2183 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2184 mtx_unlock(&sel->mutex);
2185
2186 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2187 /* If it's an optimized shader and its compilation has
2188 * been started but isn't done, use the unoptimized
2189 * shader so as not to cause a stall due to compilation.
2190 */
2191 if (iter->is_optimized) {
2192 if (optimized_or_none)
2193 return -1;
2194 memset(&key->opt, 0, sizeof(key->opt));
2195 goto again;
2196 }
2197
2198 util_queue_fence_wait(&iter->ready);
2199 }
2200
2201 if (iter->compilation_failed) {
2202 return -1; /* skip the draw call */
2203 }
2204
2205 state->current = iter;
2206 return 0;
2207 }
2208 }
2209
2210 /* Build a new shader. */
2211 shader = CALLOC_STRUCT(si_shader);
2212 if (!shader) {
2213 mtx_unlock(&sel->mutex);
2214 return -ENOMEM;
2215 }
2216
2217 util_queue_fence_init(&shader->ready);
2218
2219 shader->selector = sel;
2220 shader->key = *key;
2221 shader->compiler_ctx_state = *compiler_state;
2222
2223 /* If this is a merged shader, get the first shader's selector. */
2224 if (sscreen->info.chip_class >= GFX9) {
2225 if (sel->type == PIPE_SHADER_TESS_CTRL)
2226 previous_stage_sel = key->part.tcs.ls;
2227 else if (sel->type == PIPE_SHADER_GEOMETRY)
2228 previous_stage_sel = key->part.gs.es;
2229
2230 /* We need to wait for the previous shader. */
2231 if (previous_stage_sel && thread_index < 0)
2232 util_queue_fence_wait(&previous_stage_sel->ready);
2233 }
2234
2235 bool is_pure_monolithic =
2236 sscreen->use_monolithic_shaders ||
2237 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2238
2239 /* Compile the main shader part if it doesn't exist. This can happen
2240 * if the initial guess was wrong.
2241 *
2242 * The prim discard CS doesn't need the main shader part.
2243 */
2244 if (!is_pure_monolithic &&
2245 !key->opt.vs_as_prim_discard_cs) {
2246 bool ok = true;
2247
2248 /* Make sure the main shader part is present. This is needed
2249 * for shaders that can be compiled as VS, LS, or ES, and only
2250 * one of them is compiled at creation.
2251 *
2252 * It is also needed for GS, which can be compiled as non-NGG
2253 * and NGG.
2254 *
2255 * For merged shaders, check that the starting shader's main
2256 * part is present.
2257 */
2258 if (previous_stage_sel) {
2259 struct si_shader_key shader1_key = zeroed;
2260
2261 if (sel->type == PIPE_SHADER_TESS_CTRL)
2262 shader1_key.as_ls = 1;
2263 else if (sel->type == PIPE_SHADER_GEOMETRY)
2264 shader1_key.as_es = 1;
2265 else
2266 assert(0);
2267
2268 if (sel->type == PIPE_SHADER_GEOMETRY &&
2269 previous_stage_sel->type == PIPE_SHADER_TESS_EVAL)
2270 shader1_key.as_ngg = key->as_ngg;
2271
2272 mtx_lock(&previous_stage_sel->mutex);
2273 ok = si_check_missing_main_part(sscreen,
2274 previous_stage_sel,
2275 compiler_state, &shader1_key);
2276 mtx_unlock(&previous_stage_sel->mutex);
2277 }
2278
2279 if (ok) {
2280 ok = si_check_missing_main_part(sscreen, sel,
2281 compiler_state, key);
2282 }
2283
2284 if (!ok) {
2285 FREE(shader);
2286 mtx_unlock(&sel->mutex);
2287 return -ENOMEM; /* skip the draw call */
2288 }
2289 }
2290
2291 /* Keep the reference to the 1st shader of merged shaders, so that
2292 * Gallium can't destroy it before we destroy the 2nd shader.
2293 *
2294 * Set sctx = NULL, because it's unused if we're not releasing
2295 * the shader, and we don't have any sctx here.
2296 */
2297 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2298 previous_stage_sel);
2299
2300 /* Monolithic-only shaders don't make a distinction between optimized
2301 * and unoptimized. */
2302 shader->is_monolithic =
2303 is_pure_monolithic ||
2304 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2305
2306 /* The prim discard CS is always optimized. */
2307 shader->is_optimized =
2308 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2309 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2310
2311 /* If it's an optimized shader, compile it asynchronously. */
2312 if (shader->is_optimized && thread_index < 0) {
2313 /* Compile it asynchronously. */
2314 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2315 shader, &shader->ready,
2316 si_build_shader_variant_low_priority, NULL);
2317
2318 /* Add only after the ready fence was reset, to guard against a
2319 * race with si_bind_XX_shader. */
2320 if (!sel->last_variant) {
2321 sel->first_variant = shader;
2322 sel->last_variant = shader;
2323 } else {
2324 sel->last_variant->next_variant = shader;
2325 sel->last_variant = shader;
2326 }
2327
2328 /* Use the default (unoptimized) shader for now. */
2329 memset(&key->opt, 0, sizeof(key->opt));
2330 mtx_unlock(&sel->mutex);
2331
2332 if (sscreen->options.sync_compile)
2333 util_queue_fence_wait(&shader->ready);
2334
2335 if (optimized_or_none)
2336 return -1;
2337 goto again;
2338 }
2339
2340 /* Reset the fence before adding to the variant list. */
2341 util_queue_fence_reset(&shader->ready);
2342
2343 if (!sel->last_variant) {
2344 sel->first_variant = shader;
2345 sel->last_variant = shader;
2346 } else {
2347 sel->last_variant->next_variant = shader;
2348 sel->last_variant = shader;
2349 }
2350
2351 mtx_unlock(&sel->mutex);
2352
2353 assert(!shader->is_optimized);
2354 si_build_shader_variant(shader, thread_index, false);
2355
2356 util_queue_fence_signal(&shader->ready);
2357
2358 if (!shader->compilation_failed)
2359 state->current = shader;
2360
2361 return shader->compilation_failed ? -1 : 0;
2362 }
2363
2364 static int si_shader_select(struct pipe_context *ctx,
2365 struct si_shader_ctx_state *state,
2366 union si_vgt_stages_key stages_key,
2367 struct si_compiler_ctx_state *compiler_state)
2368 {
2369 struct si_context *sctx = (struct si_context *)ctx;
2370 struct si_shader_key key;
2371
2372 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2373 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2374 &key, -1, false);
2375 }
2376
2377 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2378 bool streamout,
2379 struct si_shader_key *key)
2380 {
2381 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2382
2383 switch (info->processor) {
2384 case PIPE_SHADER_VERTEX:
2385 switch (next_shader) {
2386 case PIPE_SHADER_GEOMETRY:
2387 key->as_es = 1;
2388 break;
2389 case PIPE_SHADER_TESS_CTRL:
2390 case PIPE_SHADER_TESS_EVAL:
2391 key->as_ls = 1;
2392 break;
2393 default:
2394 /* If POSITION isn't written, it can only be a HW VS
2395 * if streamout is used. If streamout isn't used,
2396 * assume that it's a HW LS. (the next shader is TCS)
2397 * This heuristic is needed for separate shader objects.
2398 */
2399 if (!info->writes_position && !streamout)
2400 key->as_ls = 1;
2401 }
2402 break;
2403
2404 case PIPE_SHADER_TESS_EVAL:
2405 if (next_shader == PIPE_SHADER_GEOMETRY ||
2406 !info->writes_position)
2407 key->as_es = 1;
2408 break;
2409 }
2410 }
2411
2412 /**
2413 * Compile the main shader part or the monolithic shader as part of
2414 * si_shader_selector initialization. Since it can be done asynchronously,
2415 * there is no way to report compile failures to applications.
2416 */
2417 static void si_init_shader_selector_async(void *job, int thread_index)
2418 {
2419 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2420 struct si_screen *sscreen = sel->screen;
2421 struct ac_llvm_compiler *compiler;
2422 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2423
2424 assert(!debug->debug_message || debug->async);
2425 assert(thread_index >= 0);
2426 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2427 compiler = &sscreen->compiler[thread_index];
2428
2429 if (sel->nir) {
2430 /* TODO: GS always sets wave size = default. Legacy GS will have
2431 * incorrect subgroup_size and ballot_bit_size. */
2432 si_lower_nir(sel, si_get_wave_size(sscreen, sel->type, true, false));
2433 }
2434
2435 /* Compile the main shader part for use with a prolog and/or epilog.
2436 * If this fails, the driver will try to compile a monolithic shader
2437 * on demand.
2438 */
2439 if (!sscreen->use_monolithic_shaders) {
2440 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2441 void *ir_binary = NULL;
2442
2443 if (!shader) {
2444 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2445 return;
2446 }
2447
2448 /* We can leave the fence signaled because use of the default
2449 * main part is guarded by the selector's ready fence. */
2450 util_queue_fence_init(&shader->ready);
2451
2452 shader->selector = sel;
2453 shader->is_monolithic = false;
2454 si_parse_next_shader_property(&sel->info,
2455 sel->so.num_outputs != 0,
2456 &shader->key);
2457 if (sscreen->info.chip_class >= GFX10 &&
2458 ((sel->type == PIPE_SHADER_VERTEX &&
2459 !shader->key.as_ls && !shader->key.as_es) ||
2460 sel->type == PIPE_SHADER_TESS_EVAL ||
2461 sel->type == PIPE_SHADER_GEOMETRY))
2462 shader->key.as_ngg = 1;
2463
2464 if (sel->tokens || sel->nir)
2465 ir_binary = si_get_ir_binary(sel);
2466
2467 /* Try to load the shader from the shader cache. */
2468 mtx_lock(&sscreen->shader_cache_mutex);
2469
2470 if (ir_binary &&
2471 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2472 mtx_unlock(&sscreen->shader_cache_mutex);
2473 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2474 } else {
2475 mtx_unlock(&sscreen->shader_cache_mutex);
2476
2477 /* Compile the shader if it hasn't been loaded from the cache. */
2478 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2479 debug) != 0) {
2480 FREE(shader);
2481 FREE(ir_binary);
2482 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2483 return;
2484 }
2485
2486 if (ir_binary) {
2487 mtx_lock(&sscreen->shader_cache_mutex);
2488 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2489 FREE(ir_binary);
2490 mtx_unlock(&sscreen->shader_cache_mutex);
2491 }
2492 }
2493
2494 *si_get_main_shader_part(sel, &shader->key) = shader;
2495
2496 /* Unset "outputs_written" flags for outputs converted to
2497 * DEFAULT_VAL, so that later inter-shader optimizations don't
2498 * try to eliminate outputs that don't exist in the final
2499 * shader.
2500 *
2501 * This is only done if non-monolithic shaders are enabled.
2502 */
2503 if ((sel->type == PIPE_SHADER_VERTEX ||
2504 sel->type == PIPE_SHADER_TESS_EVAL) &&
2505 !shader->key.as_ls &&
2506 !shader->key.as_es) {
2507 unsigned i;
2508
2509 for (i = 0; i < sel->info.num_outputs; i++) {
2510 unsigned offset = shader->info.vs_output_param_offset[i];
2511
2512 if (offset <= AC_EXP_PARAM_OFFSET_31)
2513 continue;
2514
2515 unsigned name = sel->info.output_semantic_name[i];
2516 unsigned index = sel->info.output_semantic_index[i];
2517 unsigned id;
2518
2519 switch (name) {
2520 case TGSI_SEMANTIC_GENERIC:
2521 /* don't process indices the function can't handle */
2522 if (index >= SI_MAX_IO_GENERIC)
2523 break;
2524 /* fall through */
2525 default:
2526 id = si_shader_io_get_unique_index(name, index, true);
2527 sel->outputs_written_before_ps &= ~(1ull << id);
2528 break;
2529 case TGSI_SEMANTIC_POSITION: /* ignore these */
2530 case TGSI_SEMANTIC_PSIZE:
2531 case TGSI_SEMANTIC_CLIPVERTEX:
2532 case TGSI_SEMANTIC_EDGEFLAG:
2533 break;
2534 }
2535 }
2536 }
2537 }
2538
2539 /* The GS copy shader is always pre-compiled. */
2540 if (sel->type == PIPE_SHADER_GEOMETRY &&
2541 (sscreen->info.chip_class <= GFX9 || sel->tess_turns_off_ngg)) {
2542 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2543 if (!sel->gs_copy_shader) {
2544 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2545 return;
2546 }
2547
2548 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2549 }
2550 }
2551
2552 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2553 struct util_queue_fence *ready_fence,
2554 struct si_compiler_ctx_state *compiler_ctx_state,
2555 void *job, util_queue_execute_func execute)
2556 {
2557 util_queue_fence_init(ready_fence);
2558
2559 struct util_async_debug_callback async_debug;
2560 bool debug =
2561 (sctx->debug.debug_message && !sctx->debug.async) ||
2562 sctx->is_debug ||
2563 si_can_dump_shader(sctx->screen, processor);
2564
2565 if (debug) {
2566 u_async_debug_init(&async_debug);
2567 compiler_ctx_state->debug = async_debug.base;
2568 }
2569
2570 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2571 ready_fence, execute, NULL);
2572
2573 if (debug) {
2574 util_queue_fence_wait(ready_fence);
2575 u_async_debug_drain(&async_debug, &sctx->debug);
2576 u_async_debug_cleanup(&async_debug);
2577 }
2578
2579 if (sctx->screen->options.sync_compile)
2580 util_queue_fence_wait(ready_fence);
2581 }
2582
2583 /* Return descriptor slot usage masks from the given shader info. */
2584 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2585 uint32_t *const_and_shader_buffers,
2586 uint64_t *samplers_and_images)
2587 {
2588 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2589
2590 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2591 num_constbufs = util_last_bit(info->const_buffers_declared);
2592 /* two 8-byte images share one 16-byte slot */
2593 num_images = align(util_last_bit(info->images_declared), 2);
2594 num_samplers = util_last_bit(info->samplers_declared);
2595
2596 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2597 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2598 *const_and_shader_buffers =
2599 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2600
2601 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2602 start = si_get_image_slot(num_images - 1) / 2;
2603 *samplers_and_images =
2604 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2605 }
2606
2607 static void *si_create_shader_selector(struct pipe_context *ctx,
2608 const struct pipe_shader_state *state)
2609 {
2610 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2611 struct si_context *sctx = (struct si_context*)ctx;
2612 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2613 int i;
2614
2615 if (!sel)
2616 return NULL;
2617
2618 pipe_reference_init(&sel->reference, 1);
2619 sel->screen = sscreen;
2620 sel->compiler_ctx_state.debug = sctx->debug;
2621 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2622
2623 sel->so = state->stream_output;
2624
2625 if (state->type == PIPE_SHADER_IR_TGSI &&
2626 !sscreen->options.always_nir) {
2627 sel->tokens = tgsi_dup_tokens(state->tokens);
2628 if (!sel->tokens) {
2629 FREE(sel);
2630 return NULL;
2631 }
2632
2633 tgsi_scan_shader(state->tokens, &sel->info);
2634 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2635
2636 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2637 if (sel->info.uses_persp_opcode_interp_centroid)
2638 sel->info.uses_persp_centroid = true;
2639
2640 if (sel->info.uses_linear_opcode_interp_centroid)
2641 sel->info.uses_linear_centroid = true;
2642
2643 if (sel->info.uses_persp_opcode_interp_offset ||
2644 sel->info.uses_persp_opcode_interp_sample)
2645 sel->info.uses_persp_center = true;
2646
2647 if (sel->info.uses_linear_opcode_interp_offset ||
2648 sel->info.uses_linear_opcode_interp_sample)
2649 sel->info.uses_linear_center = true;
2650 } else {
2651 if (state->type == PIPE_SHADER_IR_TGSI) {
2652 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2653 } else {
2654 assert(state->type == PIPE_SHADER_IR_NIR);
2655 sel->nir = state->ir.nir;
2656 }
2657
2658 si_nir_lower_ps_inputs(sel->nir);
2659 si_nir_opts(sel->nir);
2660 si_nir_scan_shader(sel->nir, &sel->info);
2661 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2662 }
2663
2664 sel->type = sel->info.processor;
2665 p_atomic_inc(&sscreen->num_shaders_created);
2666 si_get_active_slot_masks(&sel->info,
2667 &sel->active_const_and_shader_buffers,
2668 &sel->active_samplers_and_images);
2669
2670 /* Record which streamout buffers are enabled. */
2671 for (i = 0; i < sel->so.num_outputs; i++) {
2672 sel->enabled_streamout_buffer_mask |=
2673 (1 << sel->so.output[i].output_buffer) <<
2674 (sel->so.output[i].stream * 4);
2675 }
2676
2677 /* The prolog is a no-op if there are no inputs. */
2678 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2679 sel->info.num_inputs &&
2680 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2681
2682 sel->force_correct_derivs_after_kill =
2683 sel->type == PIPE_SHADER_FRAGMENT &&
2684 sel->info.uses_derivatives &&
2685 sel->info.uses_kill &&
2686 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2687
2688 sel->prim_discard_cs_allowed =
2689 sel->type == PIPE_SHADER_VERTEX &&
2690 !sel->info.uses_bindless_images &&
2691 !sel->info.uses_bindless_samplers &&
2692 !sel->info.writes_memory &&
2693 !sel->info.writes_viewport_index &&
2694 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2695 !sel->so.num_outputs;
2696
2697 if (sel->type == PIPE_SHADER_VERTEX &&
2698 sel->info.writes_edgeflag) {
2699 if (sscreen->info.chip_class >= GFX10)
2700 sel->ngg_writes_edgeflag = true;
2701 else
2702 sel->pos_writes_edgeflag = true;
2703 }
2704
2705 switch (sel->type) {
2706 case PIPE_SHADER_GEOMETRY:
2707 sel->gs_output_prim =
2708 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2709
2710 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2711 sel->rast_prim = sel->gs_output_prim;
2712 if (util_rast_prim_is_triangles(sel->rast_prim))
2713 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2714
2715 sel->gs_max_out_vertices =
2716 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2717 sel->gs_num_invocations =
2718 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2719 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2720 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2721 sel->gs_max_out_vertices;
2722
2723 sel->max_gs_stream = 0;
2724 for (i = 0; i < sel->so.num_outputs; i++)
2725 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2726 sel->so.output[i].stream);
2727
2728 sel->gs_input_verts_per_prim =
2729 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2730
2731 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2732 sel->tess_turns_off_ngg =
2733 (sscreen->info.family == CHIP_NAVI10 ||
2734 sscreen->info.family == CHIP_NAVI12 ||
2735 sscreen->info.family == CHIP_NAVI14) &&
2736 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2737 break;
2738
2739 case PIPE_SHADER_TESS_CTRL:
2740 /* Always reserve space for these. */
2741 sel->patch_outputs_written |=
2742 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2743 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2744 /* fall through */
2745 case PIPE_SHADER_VERTEX:
2746 case PIPE_SHADER_TESS_EVAL:
2747 for (i = 0; i < sel->info.num_outputs; i++) {
2748 unsigned name = sel->info.output_semantic_name[i];
2749 unsigned index = sel->info.output_semantic_index[i];
2750
2751 switch (name) {
2752 case TGSI_SEMANTIC_TESSINNER:
2753 case TGSI_SEMANTIC_TESSOUTER:
2754 case TGSI_SEMANTIC_PATCH:
2755 sel->patch_outputs_written |=
2756 1ull << si_shader_io_get_unique_index_patch(name, index);
2757 break;
2758
2759 case TGSI_SEMANTIC_GENERIC:
2760 /* don't process indices the function can't handle */
2761 if (index >= SI_MAX_IO_GENERIC)
2762 break;
2763 /* fall through */
2764 default:
2765 sel->outputs_written |=
2766 1ull << si_shader_io_get_unique_index(name, index, false);
2767 sel->outputs_written_before_ps |=
2768 1ull << si_shader_io_get_unique_index(name, index, true);
2769 break;
2770 case TGSI_SEMANTIC_EDGEFLAG:
2771 break;
2772 }
2773 }
2774 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2775 sel->lshs_vertex_stride = sel->esgs_itemsize;
2776
2777 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2778 * will start on a different bank. (except for the maximum 32*16).
2779 */
2780 if (sel->lshs_vertex_stride < 32*16)
2781 sel->lshs_vertex_stride += 4;
2782
2783 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2784 * conflicts, i.e. each vertex will start at a different bank.
2785 */
2786 if (sctx->chip_class >= GFX9)
2787 sel->esgs_itemsize += 4;
2788
2789 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2790
2791 /* Only for TES: */
2792 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2793 sel->rast_prim = PIPE_PRIM_POINTS;
2794 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2795 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2796 else
2797 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2798 break;
2799
2800 case PIPE_SHADER_FRAGMENT:
2801 for (i = 0; i < sel->info.num_inputs; i++) {
2802 unsigned name = sel->info.input_semantic_name[i];
2803 unsigned index = sel->info.input_semantic_index[i];
2804
2805 switch (name) {
2806 case TGSI_SEMANTIC_GENERIC:
2807 /* don't process indices the function can't handle */
2808 if (index >= SI_MAX_IO_GENERIC)
2809 break;
2810 /* fall through */
2811 default:
2812 sel->inputs_read |=
2813 1ull << si_shader_io_get_unique_index(name, index, true);
2814 break;
2815 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2816 break;
2817 }
2818 }
2819
2820 for (i = 0; i < 8; i++)
2821 if (sel->info.colors_written & (1 << i))
2822 sel->colors_written_4bit |= 0xf << (4 * i);
2823
2824 for (i = 0; i < sel->info.num_inputs; i++) {
2825 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2826 int index = sel->info.input_semantic_index[i];
2827 sel->color_attr_index[index] = i;
2828 }
2829 }
2830 break;
2831 default:;
2832 }
2833
2834 /* PA_CL_VS_OUT_CNTL */
2835 bool misc_vec_ena =
2836 sel->info.writes_psize || sel->pos_writes_edgeflag ||
2837 sel->info.writes_layer || sel->info.writes_viewport_index;
2838 sel->pa_cl_vs_out_cntl =
2839 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2840 S_02881C_USE_VTX_EDGE_FLAG(sel->pos_writes_edgeflag) |
2841 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2842 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2843 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2844 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2845 sel->clipdist_mask = sel->info.writes_clipvertex ?
2846 SIX_BITS : sel->info.clipdist_writemask;
2847 sel->culldist_mask = sel->info.culldist_writemask <<
2848 sel->info.num_written_clipdistance;
2849
2850 /* DB_SHADER_CONTROL */
2851 sel->db_shader_control =
2852 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2853 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2854 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2855 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2856
2857 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2858 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2859 sel->db_shader_control |=
2860 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2861 break;
2862 case TGSI_FS_DEPTH_LAYOUT_LESS:
2863 sel->db_shader_control |=
2864 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2865 break;
2866 }
2867
2868 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2869 *
2870 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2871 * --|-----------|------------|------------|--------------------|-------------------|-------------
2872 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2873 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2874 * 2 | false | true | n/a | LateZ | 1 | 0
2875 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2876 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2877 *
2878 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2879 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2880 *
2881 * Don't use ReZ without profiling !!!
2882 *
2883 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2884 * shaders.
2885 */
2886 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2887 /* Cases 3, 4. */
2888 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2889 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2890 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2891 } else if (sel->info.writes_memory) {
2892 /* Case 2. */
2893 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2894 S_02880C_EXEC_ON_HIER_FAIL(1);
2895 } else {
2896 /* Case 1. */
2897 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2898 }
2899
2900 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2901 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2902
2903 (void) mtx_init(&sel->mutex, mtx_plain);
2904
2905 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2906 &sel->compiler_ctx_state, sel,
2907 si_init_shader_selector_async);
2908 return sel;
2909 }
2910
2911 static void si_update_streamout_state(struct si_context *sctx)
2912 {
2913 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2914
2915 if (!shader_with_so)
2916 return;
2917
2918 sctx->streamout.enabled_stream_buffers_mask =
2919 shader_with_so->enabled_streamout_buffer_mask;
2920 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2921 }
2922
2923 static void si_update_clip_regs(struct si_context *sctx,
2924 struct si_shader_selector *old_hw_vs,
2925 struct si_shader *old_hw_vs_variant,
2926 struct si_shader_selector *next_hw_vs,
2927 struct si_shader *next_hw_vs_variant)
2928 {
2929 if (next_hw_vs &&
2930 (!old_hw_vs ||
2931 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2932 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2933 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2934 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2935 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2936 !old_hw_vs_variant ||
2937 !next_hw_vs_variant ||
2938 old_hw_vs_variant->key.opt.clip_disable !=
2939 next_hw_vs_variant->key.opt.clip_disable))
2940 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2941 }
2942
2943 static void si_update_common_shader_state(struct si_context *sctx)
2944 {
2945 sctx->uses_bindless_samplers =
2946 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2947 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2948 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2949 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2950 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2951 sctx->uses_bindless_images =
2952 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2953 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2954 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2955 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2956 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2957 sctx->do_update_shaders = true;
2958 }
2959
2960 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2961 {
2962 struct si_context *sctx = (struct si_context *)ctx;
2963 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2964 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2965 struct si_shader_selector *sel = state;
2966
2967 if (sctx->vs_shader.cso == sel)
2968 return;
2969
2970 sctx->vs_shader.cso = sel;
2971 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2972 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2973
2974 si_update_common_shader_state(sctx);
2975 si_update_vs_viewport_state(sctx);
2976 si_set_active_descriptors_for_shader(sctx, sel);
2977 si_update_streamout_state(sctx);
2978 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2979 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2980 }
2981
2982 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2983 {
2984 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2985 (sctx->tes_shader.cso &&
2986 sctx->tes_shader.cso->info.uses_primid) ||
2987 (sctx->tcs_shader.cso &&
2988 sctx->tcs_shader.cso->info.uses_primid) ||
2989 (sctx->gs_shader.cso &&
2990 sctx->gs_shader.cso->info.uses_primid) ||
2991 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2992 sctx->ps_shader.cso->info.uses_primid);
2993 }
2994
2995 static bool si_update_ngg(struct si_context *sctx)
2996 {
2997 if (sctx->chip_class <= GFX9)
2998 return false;
2999
3000 bool new_ngg = true;
3001
3002 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3003 sctx->gs_shader.cso->tess_turns_off_ngg)
3004 new_ngg = false;
3005
3006 if (new_ngg != sctx->ngg) {
3007 sctx->ngg = new_ngg;
3008 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3009 return true;
3010 }
3011 return false;
3012 }
3013
3014 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3015 {
3016 struct si_context *sctx = (struct si_context *)ctx;
3017 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3018 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3019 struct si_shader_selector *sel = state;
3020 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3021 bool ngg_changed;
3022
3023 if (sctx->gs_shader.cso == sel)
3024 return;
3025
3026 sctx->gs_shader.cso = sel;
3027 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3028 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3029
3030 si_update_common_shader_state(sctx);
3031 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3032
3033 ngg_changed = si_update_ngg(sctx);
3034 if (ngg_changed || enable_changed)
3035 si_shader_change_notify(sctx);
3036 if (enable_changed) {
3037 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3038 si_update_tess_uses_prim_id(sctx);
3039 }
3040 si_update_vs_viewport_state(sctx);
3041 si_set_active_descriptors_for_shader(sctx, sel);
3042 si_update_streamout_state(sctx);
3043 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3044 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3045 }
3046
3047 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3048 {
3049 struct si_context *sctx = (struct si_context *)ctx;
3050 struct si_shader_selector *sel = state;
3051 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3052
3053 if (sctx->tcs_shader.cso == sel)
3054 return;
3055
3056 sctx->tcs_shader.cso = sel;
3057 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3058 si_update_tess_uses_prim_id(sctx);
3059
3060 si_update_common_shader_state(sctx);
3061
3062 if (enable_changed)
3063 sctx->last_tcs = NULL; /* invalidate derived tess state */
3064
3065 si_set_active_descriptors_for_shader(sctx, sel);
3066 }
3067
3068 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3069 {
3070 struct si_context *sctx = (struct si_context *)ctx;
3071 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3072 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3073 struct si_shader_selector *sel = state;
3074 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3075
3076 if (sctx->tes_shader.cso == sel)
3077 return;
3078
3079 sctx->tes_shader.cso = sel;
3080 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3081 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3082 si_update_tess_uses_prim_id(sctx);
3083
3084 si_update_common_shader_state(sctx);
3085 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3086
3087 if (enable_changed) {
3088 si_update_ngg(sctx);
3089 si_shader_change_notify(sctx);
3090 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3091 }
3092 si_update_vs_viewport_state(sctx);
3093 si_set_active_descriptors_for_shader(sctx, sel);
3094 si_update_streamout_state(sctx);
3095 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3096 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3097 }
3098
3099 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3100 {
3101 struct si_context *sctx = (struct si_context *)ctx;
3102 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3103 struct si_shader_selector *sel = state;
3104
3105 /* skip if supplied shader is one already in use */
3106 if (old_sel == sel)
3107 return;
3108
3109 sctx->ps_shader.cso = sel;
3110 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3111
3112 si_update_common_shader_state(sctx);
3113 if (sel) {
3114 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3115 si_update_tess_uses_prim_id(sctx);
3116
3117 if (!old_sel ||
3118 old_sel->info.colors_written != sel->info.colors_written)
3119 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3120
3121 if (sctx->screen->has_out_of_order_rast &&
3122 (!old_sel ||
3123 old_sel->info.writes_memory != sel->info.writes_memory ||
3124 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3125 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3126 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3127 }
3128 si_set_active_descriptors_for_shader(sctx, sel);
3129 si_update_ps_colorbuf0_slot(sctx);
3130 }
3131
3132 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3133 {
3134 if (shader->is_optimized) {
3135 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3136 &shader->ready);
3137 }
3138
3139 util_queue_fence_destroy(&shader->ready);
3140
3141 if (shader->pm4) {
3142 /* If destroyed shaders were not unbound, the next compiled
3143 * shader variant could get the same pointer address and so
3144 * binding it to the same shader stage would be considered
3145 * a no-op, causing random behavior.
3146 */
3147 switch (shader->selector->type) {
3148 case PIPE_SHADER_VERTEX:
3149 if (shader->key.as_ls) {
3150 assert(sctx->chip_class <= GFX8);
3151 si_pm4_delete_state(sctx, ls, shader->pm4);
3152 } else if (shader->key.as_es) {
3153 assert(sctx->chip_class <= GFX8);
3154 si_pm4_delete_state(sctx, es, shader->pm4);
3155 } else if (shader->key.as_ngg) {
3156 si_pm4_delete_state(sctx, gs, shader->pm4);
3157 } else {
3158 si_pm4_delete_state(sctx, vs, shader->pm4);
3159 }
3160 break;
3161 case PIPE_SHADER_TESS_CTRL:
3162 si_pm4_delete_state(sctx, hs, shader->pm4);
3163 break;
3164 case PIPE_SHADER_TESS_EVAL:
3165 if (shader->key.as_es) {
3166 assert(sctx->chip_class <= GFX8);
3167 si_pm4_delete_state(sctx, es, shader->pm4);
3168 } else if (shader->key.as_ngg) {
3169 si_pm4_delete_state(sctx, gs, shader->pm4);
3170 } else {
3171 si_pm4_delete_state(sctx, vs, shader->pm4);
3172 }
3173 break;
3174 case PIPE_SHADER_GEOMETRY:
3175 if (shader->is_gs_copy_shader)
3176 si_pm4_delete_state(sctx, vs, shader->pm4);
3177 else
3178 si_pm4_delete_state(sctx, gs, shader->pm4);
3179 break;
3180 case PIPE_SHADER_FRAGMENT:
3181 si_pm4_delete_state(sctx, ps, shader->pm4);
3182 break;
3183 default:;
3184 }
3185 }
3186
3187 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3188 si_shader_destroy(shader);
3189 free(shader);
3190 }
3191
3192 void si_destroy_shader_selector(struct si_context *sctx,
3193 struct si_shader_selector *sel)
3194 {
3195 struct si_shader *p = sel->first_variant, *c;
3196 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3197 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3198 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3199 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3200 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3201 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3202 };
3203
3204 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3205
3206 if (current_shader[sel->type]->cso == sel) {
3207 current_shader[sel->type]->cso = NULL;
3208 current_shader[sel->type]->current = NULL;
3209 }
3210
3211 while (p) {
3212 c = p->next_variant;
3213 si_delete_shader(sctx, p);
3214 p = c;
3215 }
3216
3217 if (sel->main_shader_part)
3218 si_delete_shader(sctx, sel->main_shader_part);
3219 if (sel->main_shader_part_ls)
3220 si_delete_shader(sctx, sel->main_shader_part_ls);
3221 if (sel->main_shader_part_es)
3222 si_delete_shader(sctx, sel->main_shader_part_es);
3223 if (sel->main_shader_part_ngg)
3224 si_delete_shader(sctx, sel->main_shader_part_ngg);
3225 if (sel->gs_copy_shader)
3226 si_delete_shader(sctx, sel->gs_copy_shader);
3227
3228 util_queue_fence_destroy(&sel->ready);
3229 mtx_destroy(&sel->mutex);
3230 free(sel->tokens);
3231 ralloc_free(sel->nir);
3232 free(sel);
3233 }
3234
3235 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3236 {
3237 struct si_context *sctx = (struct si_context *)ctx;
3238 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3239
3240 si_shader_selector_reference(sctx, &sel, NULL);
3241 }
3242
3243 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3244 struct si_shader *vs, unsigned name,
3245 unsigned index, unsigned interpolate)
3246 {
3247 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3248 unsigned j, offset, ps_input_cntl = 0;
3249
3250 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3251 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3252 name == TGSI_SEMANTIC_PRIMID)
3253 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3254
3255 if (name == TGSI_SEMANTIC_PCOORD ||
3256 (name == TGSI_SEMANTIC_TEXCOORD &&
3257 sctx->sprite_coord_enable & (1 << index))) {
3258 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3259 }
3260
3261 for (j = 0; j < vsinfo->num_outputs; j++) {
3262 if (name == vsinfo->output_semantic_name[j] &&
3263 index == vsinfo->output_semantic_index[j]) {
3264 offset = vs->info.vs_output_param_offset[j];
3265
3266 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3267 /* The input is loaded from parameter memory. */
3268 ps_input_cntl |= S_028644_OFFSET(offset);
3269 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3270 if (offset == AC_EXP_PARAM_UNDEFINED) {
3271 /* This can happen with depth-only rendering. */
3272 offset = 0;
3273 } else {
3274 /* The input is a DEFAULT_VAL constant. */
3275 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3276 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3277 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3278 }
3279
3280 ps_input_cntl = S_028644_OFFSET(0x20) |
3281 S_028644_DEFAULT_VAL(offset);
3282 }
3283 break;
3284 }
3285 }
3286
3287 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3288 /* PrimID is written after the last output when HW VS is used. */
3289 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3290 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3291 /* No corresponding output found, load defaults into input.
3292 * Don't set any other bits.
3293 * (FLAT_SHADE=1 completely changes behavior) */
3294 ps_input_cntl = S_028644_OFFSET(0x20);
3295 /* D3D 9 behaviour. GL is undefined */
3296 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3297 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3298 }
3299 return ps_input_cntl;
3300 }
3301
3302 static void si_emit_spi_map(struct si_context *sctx)
3303 {
3304 struct si_shader *ps = sctx->ps_shader.current;
3305 struct si_shader *vs = si_get_vs_state(sctx);
3306 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3307 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3308 unsigned spi_ps_input_cntl[32];
3309
3310 if (!ps || !ps->selector->info.num_inputs)
3311 return;
3312
3313 num_interp = si_get_ps_num_interp(ps);
3314 assert(num_interp > 0);
3315
3316 for (i = 0; i < psinfo->num_inputs; i++) {
3317 unsigned name = psinfo->input_semantic_name[i];
3318 unsigned index = psinfo->input_semantic_index[i];
3319 unsigned interpolate = psinfo->input_interpolate[i];
3320
3321 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3322 index, interpolate);
3323
3324 if (name == TGSI_SEMANTIC_COLOR) {
3325 assert(index < ARRAY_SIZE(bcol_interp));
3326 bcol_interp[index] = interpolate;
3327 }
3328 }
3329
3330 if (ps->key.part.ps.prolog.color_two_side) {
3331 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3332
3333 for (i = 0; i < 2; i++) {
3334 if (!(psinfo->colors_read & (0xf << (i * 4))))
3335 continue;
3336
3337 spi_ps_input_cntl[num_written++] =
3338 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3339
3340 }
3341 }
3342 assert(num_interp == num_written);
3343
3344 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3345 /* Dota 2: Only ~16% of SPI map updates set different values. */
3346 /* Talos: Only ~9% of SPI map updates set different values. */
3347 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3348 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3349 spi_ps_input_cntl,
3350 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3351
3352 if (initial_cdw != sctx->gfx_cs->current.cdw)
3353 sctx->context_roll = true;
3354 }
3355
3356 /**
3357 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3358 */
3359 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3360 {
3361 if (sctx->init_config_has_vgt_flush)
3362 return;
3363
3364 /* Done by Vulkan before VGT_FLUSH. */
3365 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3366 si_pm4_cmd_add(sctx->init_config,
3367 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3368 si_pm4_cmd_end(sctx->init_config, false);
3369
3370 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3371 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3372 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3373 si_pm4_cmd_end(sctx->init_config, false);
3374 sctx->init_config_has_vgt_flush = true;
3375 }
3376
3377 /* Initialize state related to ESGS / GSVS ring buffers */
3378 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3379 {
3380 struct si_shader_selector *es =
3381 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3382 struct si_shader_selector *gs = sctx->gs_shader.cso;
3383 struct si_pm4_state *pm4;
3384
3385 /* Chip constants. */
3386 unsigned num_se = sctx->screen->info.max_se;
3387 unsigned wave_size = 64;
3388 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3389 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3390 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3391 */
3392 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3393 unsigned alignment = 256 * num_se;
3394 /* The maximum size is 63.999 MB per SE. */
3395 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3396
3397 /* Calculate the minimum size. */
3398 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3399 wave_size, alignment);
3400
3401 /* These are recommended sizes, not minimum sizes. */
3402 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3403 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3404 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3405 gs->max_gsvs_emit_size;
3406
3407 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3408 esgs_ring_size = align(esgs_ring_size, alignment);
3409 gsvs_ring_size = align(gsvs_ring_size, alignment);
3410
3411 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3412 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3413
3414 /* Some rings don't have to be allocated if shaders don't use them.
3415 * (e.g. no varyings between ES and GS or GS and VS)
3416 *
3417 * GFX9 doesn't have the ESGS ring.
3418 */
3419 bool update_esgs = sctx->chip_class <= GFX8 &&
3420 esgs_ring_size &&
3421 (!sctx->esgs_ring ||
3422 sctx->esgs_ring->width0 < esgs_ring_size);
3423 bool update_gsvs = gsvs_ring_size &&
3424 (!sctx->gsvs_ring ||
3425 sctx->gsvs_ring->width0 < gsvs_ring_size);
3426
3427 if (!update_esgs && !update_gsvs)
3428 return true;
3429
3430 if (update_esgs) {
3431 pipe_resource_reference(&sctx->esgs_ring, NULL);
3432 sctx->esgs_ring =
3433 pipe_aligned_buffer_create(sctx->b.screen,
3434 SI_RESOURCE_FLAG_UNMAPPABLE,
3435 PIPE_USAGE_DEFAULT,
3436 esgs_ring_size, alignment);
3437 if (!sctx->esgs_ring)
3438 return false;
3439 }
3440
3441 if (update_gsvs) {
3442 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3443 sctx->gsvs_ring =
3444 pipe_aligned_buffer_create(sctx->b.screen,
3445 SI_RESOURCE_FLAG_UNMAPPABLE,
3446 PIPE_USAGE_DEFAULT,
3447 gsvs_ring_size, alignment);
3448 if (!sctx->gsvs_ring)
3449 return false;
3450 }
3451
3452 /* Create the "init_config_gs_rings" state. */
3453 pm4 = CALLOC_STRUCT(si_pm4_state);
3454 if (!pm4)
3455 return false;
3456
3457 if (sctx->chip_class >= GFX7) {
3458 if (sctx->esgs_ring) {
3459 assert(sctx->chip_class <= GFX8);
3460 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3461 sctx->esgs_ring->width0 / 256);
3462 }
3463 if (sctx->gsvs_ring)
3464 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3465 sctx->gsvs_ring->width0 / 256);
3466 } else {
3467 if (sctx->esgs_ring)
3468 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3469 sctx->esgs_ring->width0 / 256);
3470 if (sctx->gsvs_ring)
3471 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3472 sctx->gsvs_ring->width0 / 256);
3473 }
3474
3475 /* Set the state. */
3476 if (sctx->init_config_gs_rings)
3477 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3478 sctx->init_config_gs_rings = pm4;
3479
3480 if (!sctx->init_config_has_vgt_flush) {
3481 si_init_config_add_vgt_flush(sctx);
3482 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3483 }
3484
3485 /* Flush the context to re-emit both init_config states. */
3486 sctx->initial_gfx_cs_size = 0; /* force flush */
3487 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3488
3489 /* Set ring bindings. */
3490 if (sctx->esgs_ring) {
3491 assert(sctx->chip_class <= GFX8);
3492 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3493 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3494 true, true, 4, 64, 0);
3495 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3496 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3497 false, false, 0, 0, 0);
3498 }
3499 if (sctx->gsvs_ring) {
3500 si_set_ring_buffer(sctx, SI_RING_GSVS,
3501 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3502 false, false, 0, 0, 0);
3503 }
3504
3505 return true;
3506 }
3507
3508 static void si_shader_lock(struct si_shader *shader)
3509 {
3510 mtx_lock(&shader->selector->mutex);
3511 if (shader->previous_stage_sel) {
3512 assert(shader->previous_stage_sel != shader->selector);
3513 mtx_lock(&shader->previous_stage_sel->mutex);
3514 }
3515 }
3516
3517 static void si_shader_unlock(struct si_shader *shader)
3518 {
3519 if (shader->previous_stage_sel)
3520 mtx_unlock(&shader->previous_stage_sel->mutex);
3521 mtx_unlock(&shader->selector->mutex);
3522 }
3523
3524 /**
3525 * @returns 1 if \p sel has been updated to use a new scratch buffer
3526 * 0 if not
3527 * < 0 if there was a failure
3528 */
3529 static int si_update_scratch_buffer(struct si_context *sctx,
3530 struct si_shader *shader)
3531 {
3532 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3533
3534 if (!shader)
3535 return 0;
3536
3537 /* This shader doesn't need a scratch buffer */
3538 if (shader->config.scratch_bytes_per_wave == 0)
3539 return 0;
3540
3541 /* Prevent race conditions when updating:
3542 * - si_shader::scratch_bo
3543 * - si_shader::binary::code
3544 * - si_shader::previous_stage::binary::code.
3545 */
3546 si_shader_lock(shader);
3547
3548 /* This shader is already configured to use the current
3549 * scratch buffer. */
3550 if (shader->scratch_bo == sctx->scratch_buffer) {
3551 si_shader_unlock(shader);
3552 return 0;
3553 }
3554
3555 assert(sctx->scratch_buffer);
3556
3557 /* Replace the shader bo with a new bo that has the relocs applied. */
3558 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3559 si_shader_unlock(shader);
3560 return -1;
3561 }
3562
3563 /* Update the shader state to use the new shader bo. */
3564 si_shader_init_pm4_state(sctx->screen, shader);
3565
3566 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3567
3568 si_shader_unlock(shader);
3569 return 1;
3570 }
3571
3572 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3573 {
3574 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3575 }
3576
3577 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3578 {
3579 return shader ? shader->config.scratch_bytes_per_wave : 0;
3580 }
3581
3582 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3583 {
3584 if (!sctx->tes_shader.cso)
3585 return NULL; /* tessellation disabled */
3586
3587 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3588 sctx->fixed_func_tcs_shader.current;
3589 }
3590
3591 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3592 {
3593 unsigned bytes = 0;
3594
3595 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3596 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3597 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3598 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3599
3600 if (sctx->tes_shader.cso) {
3601 struct si_shader *tcs = si_get_tcs_current(sctx);
3602
3603 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3604 }
3605 return bytes;
3606 }
3607
3608 static bool si_update_scratch_relocs(struct si_context *sctx)
3609 {
3610 struct si_shader *tcs = si_get_tcs_current(sctx);
3611 int r;
3612
3613 /* Update the shaders, so that they are using the latest scratch.
3614 * The scratch buffer may have been changed since these shaders were
3615 * last used, so we still need to try to update them, even if they
3616 * require scratch buffers smaller than the current size.
3617 */
3618 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3619 if (r < 0)
3620 return false;
3621 if (r == 1)
3622 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3623
3624 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3625 if (r < 0)
3626 return false;
3627 if (r == 1)
3628 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3629
3630 r = si_update_scratch_buffer(sctx, tcs);
3631 if (r < 0)
3632 return false;
3633 if (r == 1)
3634 si_pm4_bind_state(sctx, hs, tcs->pm4);
3635
3636 /* VS can be bound as LS, ES, or VS. */
3637 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3638 if (r < 0)
3639 return false;
3640 if (r == 1) {
3641 if (sctx->vs_shader.current->key.as_ls)
3642 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3643 else if (sctx->vs_shader.current->key.as_es)
3644 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3645 else if (sctx->vs_shader.current->key.as_ngg)
3646 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3647 else
3648 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3649 }
3650
3651 /* TES can be bound as ES or VS. */
3652 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3653 if (r < 0)
3654 return false;
3655 if (r == 1) {
3656 if (sctx->tes_shader.current->key.as_es)
3657 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3658 else if (sctx->tes_shader.current->key.as_ngg)
3659 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3660 else
3661 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3662 }
3663
3664 return true;
3665 }
3666
3667 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3668 {
3669 unsigned current_scratch_buffer_size =
3670 si_get_current_scratch_buffer_size(sctx);
3671 unsigned scratch_bytes_per_wave =
3672 si_get_max_scratch_bytes_per_wave(sctx);
3673 unsigned scratch_needed_size = scratch_bytes_per_wave *
3674 sctx->scratch_waves;
3675 unsigned spi_tmpring_size;
3676
3677 if (scratch_needed_size > 0) {
3678 if (scratch_needed_size > current_scratch_buffer_size) {
3679 /* Create a bigger scratch buffer */
3680 si_resource_reference(&sctx->scratch_buffer, NULL);
3681
3682 sctx->scratch_buffer =
3683 si_aligned_buffer_create(&sctx->screen->b,
3684 SI_RESOURCE_FLAG_UNMAPPABLE,
3685 PIPE_USAGE_DEFAULT,
3686 scratch_needed_size, 256);
3687 if (!sctx->scratch_buffer)
3688 return false;
3689
3690 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3691 si_context_add_resource_size(sctx,
3692 &sctx->scratch_buffer->b.b);
3693 }
3694
3695 if (!si_update_scratch_relocs(sctx))
3696 return false;
3697 }
3698
3699 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3700 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3701 "scratch size should already be aligned correctly.");
3702
3703 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3704 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3705 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3706 sctx->spi_tmpring_size = spi_tmpring_size;
3707 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3708 }
3709 return true;
3710 }
3711
3712 static void si_init_tess_factor_ring(struct si_context *sctx)
3713 {
3714 assert(!sctx->tess_rings);
3715
3716 /* The address must be aligned to 2^19, because the shader only
3717 * receives the high 13 bits.
3718 */
3719 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3720 SI_RESOURCE_FLAG_32BIT,
3721 PIPE_USAGE_DEFAULT,
3722 sctx->screen->tess_offchip_ring_size +
3723 sctx->screen->tess_factor_ring_size,
3724 1 << 19);
3725 if (!sctx->tess_rings)
3726 return;
3727
3728 si_init_config_add_vgt_flush(sctx);
3729
3730 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3731 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3732
3733 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3734 sctx->screen->tess_offchip_ring_size;
3735
3736 /* Append these registers to the init config state. */
3737 if (sctx->chip_class >= GFX7) {
3738 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3739 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3740 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3741 factor_va >> 8);
3742 if (sctx->chip_class >= GFX10)
3743 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3744 S_030984_BASE_HI(factor_va >> 40));
3745 else if (sctx->chip_class == GFX9)
3746 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3747 S_030944_BASE_HI(factor_va >> 40));
3748 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3749 sctx->screen->vgt_hs_offchip_param);
3750 } else {
3751 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3752 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3753 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3754 factor_va >> 8);
3755 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3756 sctx->screen->vgt_hs_offchip_param);
3757 }
3758
3759 /* Flush the context to re-emit the init_config state.
3760 * This is done only once in a lifetime of a context.
3761 */
3762 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3763 sctx->initial_gfx_cs_size = 0; /* force flush */
3764 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3765 }
3766
3767 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3768 union si_vgt_stages_key key)
3769 {
3770 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3771 uint32_t stages = 0;
3772
3773 if (key.u.tess) {
3774 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3775 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3776
3777 if (key.u.gs)
3778 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3779 S_028B54_GS_EN(1);
3780 else if (key.u.ngg)
3781 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3782 else
3783 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3784 } else if (key.u.gs) {
3785 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3786 S_028B54_GS_EN(1);
3787 } else if (key.u.ngg) {
3788 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3789 }
3790
3791 if (key.u.ngg) {
3792 stages |= S_028B54_PRIMGEN_EN(1);
3793 if (key.u.streamout)
3794 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3795 } else if (key.u.gs)
3796 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3797
3798 if (screen->info.chip_class >= GFX9)
3799 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3800
3801 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3802 stages |= S_028B54_HS_W32_EN(1) |
3803 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3804 S_028B54_VS_W32_EN(1);
3805 }
3806
3807 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3808 return pm4;
3809 }
3810
3811 static void si_update_vgt_shader_config(struct si_context *sctx,
3812 union si_vgt_stages_key key)
3813 {
3814 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3815
3816 if (unlikely(!*pm4))
3817 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3818 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3819 }
3820
3821 bool si_update_shaders(struct si_context *sctx)
3822 {
3823 struct pipe_context *ctx = (struct pipe_context*)sctx;
3824 struct si_compiler_ctx_state compiler_state;
3825 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3826 struct si_shader *old_vs = si_get_vs_state(sctx);
3827 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3828 struct si_shader *old_ps = sctx->ps_shader.current;
3829 union si_vgt_stages_key key;
3830 unsigned old_spi_shader_col_format =
3831 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3832 int r;
3833
3834 compiler_state.compiler = &sctx->compiler;
3835 compiler_state.debug = sctx->debug;
3836 compiler_state.is_debug_context = sctx->is_debug;
3837
3838 key.index = 0;
3839
3840 if (sctx->tes_shader.cso)
3841 key.u.tess = 1;
3842 if (sctx->gs_shader.cso)
3843 key.u.gs = 1;
3844
3845 if (sctx->ngg) {
3846 key.u.ngg = 1;
3847 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3848 }
3849
3850 /* Update TCS and TES. */
3851 if (sctx->tes_shader.cso) {
3852 if (!sctx->tess_rings) {
3853 si_init_tess_factor_ring(sctx);
3854 if (!sctx->tess_rings)
3855 return false;
3856 }
3857
3858 if (sctx->tcs_shader.cso) {
3859 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3860 &compiler_state);
3861 if (r)
3862 return false;
3863 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3864 } else {
3865 if (!sctx->fixed_func_tcs_shader.cso) {
3866 sctx->fixed_func_tcs_shader.cso =
3867 si_create_fixed_func_tcs(sctx);
3868 if (!sctx->fixed_func_tcs_shader.cso)
3869 return false;
3870 }
3871
3872 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3873 key, &compiler_state);
3874 if (r)
3875 return false;
3876 si_pm4_bind_state(sctx, hs,
3877 sctx->fixed_func_tcs_shader.current->pm4);
3878 }
3879
3880 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3881 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3882 if (r)
3883 return false;
3884
3885 if (sctx->gs_shader.cso) {
3886 /* TES as ES */
3887 assert(sctx->chip_class <= GFX8);
3888 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3889 } else if (key.u.ngg) {
3890 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3891 } else {
3892 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3893 }
3894 }
3895 } else {
3896 if (sctx->chip_class <= GFX8)
3897 si_pm4_bind_state(sctx, ls, NULL);
3898 si_pm4_bind_state(sctx, hs, NULL);
3899 }
3900
3901 /* Update GS. */
3902 if (sctx->gs_shader.cso) {
3903 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3904 if (r)
3905 return false;
3906 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3907 if (!key.u.ngg) {
3908 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3909
3910 if (!si_update_gs_ring_buffers(sctx))
3911 return false;
3912 } else {
3913 si_pm4_bind_state(sctx, vs, NULL);
3914 }
3915 } else {
3916 if (!key.u.ngg) {
3917 si_pm4_bind_state(sctx, gs, NULL);
3918 if (sctx->chip_class <= GFX8)
3919 si_pm4_bind_state(sctx, es, NULL);
3920 }
3921 }
3922
3923 /* Update VS. */
3924 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3925 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3926 if (r)
3927 return false;
3928
3929 if (!key.u.tess && !key.u.gs) {
3930 if (key.u.ngg) {
3931 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3932 si_pm4_bind_state(sctx, vs, NULL);
3933 } else {
3934 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3935 }
3936 } else if (sctx->tes_shader.cso) {
3937 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3938 } else {
3939 assert(sctx->gs_shader.cso);
3940 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3941 }
3942 }
3943
3944 si_update_vgt_shader_config(sctx, key);
3945
3946 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3947 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3948
3949 if (sctx->ps_shader.cso) {
3950 unsigned db_shader_control;
3951
3952 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3953 if (r)
3954 return false;
3955 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3956
3957 db_shader_control =
3958 sctx->ps_shader.cso->db_shader_control |
3959 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3960
3961 if (si_pm4_state_changed(sctx, ps) ||
3962 si_pm4_state_changed(sctx, vs) ||
3963 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3964 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3965 sctx->flatshade != rs->flatshade) {
3966 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3967 sctx->flatshade = rs->flatshade;
3968 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3969 }
3970
3971 if (sctx->screen->rbplus_allowed &&
3972 si_pm4_state_changed(sctx, ps) &&
3973 (!old_ps ||
3974 old_spi_shader_col_format !=
3975 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3976 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3977
3978 if (sctx->ps_db_shader_control != db_shader_control) {
3979 sctx->ps_db_shader_control = db_shader_control;
3980 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3981 if (sctx->screen->dpbb_allowed)
3982 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3983 }
3984
3985 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3986 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3987 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3988
3989 if (sctx->chip_class == GFX6)
3990 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3991
3992 if (sctx->framebuffer.nr_samples <= 1)
3993 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3994 }
3995 }
3996
3997 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
3998 si_pm4_state_enabled_and_changed(sctx, hs) ||
3999 si_pm4_state_enabled_and_changed(sctx, es) ||
4000 si_pm4_state_enabled_and_changed(sctx, gs) ||
4001 si_pm4_state_enabled_and_changed(sctx, vs) ||
4002 si_pm4_state_enabled_and_changed(sctx, ps)) {
4003 if (!si_update_spi_tmpring_size(sctx))
4004 return false;
4005 }
4006
4007 if (sctx->chip_class >= GFX7) {
4008 if (si_pm4_state_enabled_and_changed(sctx, ls))
4009 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4010 else if (!sctx->queued.named.ls)
4011 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4012
4013 if (si_pm4_state_enabled_and_changed(sctx, hs))
4014 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4015 else if (!sctx->queued.named.hs)
4016 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4017
4018 if (si_pm4_state_enabled_and_changed(sctx, es))
4019 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4020 else if (!sctx->queued.named.es)
4021 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4022
4023 if (si_pm4_state_enabled_and_changed(sctx, gs))
4024 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4025 else if (!sctx->queued.named.gs)
4026 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4027
4028 if (si_pm4_state_enabled_and_changed(sctx, vs))
4029 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4030 else if (!sctx->queued.named.vs)
4031 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4032
4033 if (si_pm4_state_enabled_and_changed(sctx, ps))
4034 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4035 else if (!sctx->queued.named.ps)
4036 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4037 }
4038
4039 sctx->do_update_shaders = false;
4040 return true;
4041 }
4042
4043 static void si_emit_scratch_state(struct si_context *sctx)
4044 {
4045 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4046
4047 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4048 sctx->spi_tmpring_size);
4049
4050 if (sctx->scratch_buffer) {
4051 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4052 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4053 RADEON_PRIO_SCRATCH_BUFFER);
4054 }
4055 }
4056
4057 void si_init_shader_functions(struct si_context *sctx)
4058 {
4059 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4060 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4061
4062 sctx->b.create_vs_state = si_create_shader_selector;
4063 sctx->b.create_tcs_state = si_create_shader_selector;
4064 sctx->b.create_tes_state = si_create_shader_selector;
4065 sctx->b.create_gs_state = si_create_shader_selector;
4066 sctx->b.create_fs_state = si_create_shader_selector;
4067
4068 sctx->b.bind_vs_state = si_bind_vs_shader;
4069 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4070 sctx->b.bind_tes_state = si_bind_tes_shader;
4071 sctx->b.bind_gs_state = si_bind_gs_shader;
4072 sctx->b.bind_fs_state = si_bind_ps_shader;
4073
4074 sctx->b.delete_vs_state = si_delete_shader_selector;
4075 sctx->b.delete_tcs_state = si_delete_shader_selector;
4076 sctx->b.delete_tes_state = si_delete_shader_selector;
4077 sctx->b.delete_gs_state = si_delete_shader_selector;
4078 sctx->b.delete_fs_state = si_delete_shader_selector;
4079 }