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radeonsi: add a bug workaround for NGG - LATE_ALLOC_GS
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR key for the shader cache.
45 */
46 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
47 unsigned char ir_sha1_cache_key[20])
48 {
49 struct blob blob = {};
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->nir_binary) {
54 ir_binary = sel->nir_binary;
55 ir_size = sel->nir_size;
56 } else {
57 assert(sel->nir);
58
59 blob_init(&blob);
60 nir_serialize(&blob, sel->nir, true);
61 ir_binary = blob.data;
62 ir_size = blob.size;
63 }
64
65 /* These settings affect the compilation, but they are not derived
66 * from the input shader IR.
67 */
68 unsigned shader_variant_flags = 0;
69
70 if (ngg)
71 shader_variant_flags |= 1 << 0;
72 if (sel->nir)
73 shader_variant_flags |= 1 << 1;
74 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
75 shader_variant_flags |= 1 << 2;
76 if (sel->type == PIPE_SHADER_FRAGMENT &&
77 sel->info.uses_derivatives &&
78 sel->info.uses_kill &&
79 sel->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
80 shader_variant_flags |= 1 << 3;
81
82 struct mesa_sha1 ctx;
83 _mesa_sha1_init(&ctx);
84 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
85 _mesa_sha1_update(&ctx, ir_binary, ir_size);
86 if (sel->type == PIPE_SHADER_VERTEX ||
87 sel->type == PIPE_SHADER_TESS_EVAL ||
88 sel->type == PIPE_SHADER_GEOMETRY)
89 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
90 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
91
92 if (ir_binary == blob.data)
93 blob_finish(&blob);
94 }
95
96 /** Copy "data" to "ptr" and return the next dword following copied data. */
97 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
98 {
99 /* data may be NULL if size == 0 */
100 if (size)
101 memcpy(ptr, data, size);
102 ptr += DIV_ROUND_UP(size, 4);
103 return ptr;
104 }
105
106 /** Read data from "ptr". Return the next dword following the data. */
107 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
108 {
109 memcpy(data, ptr, size);
110 ptr += DIV_ROUND_UP(size, 4);
111 return ptr;
112 }
113
114 /**
115 * Write the size as uint followed by the data. Return the next dword
116 * following the copied data.
117 */
118 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
119 {
120 *ptr++ = size;
121 return write_data(ptr, data, size);
122 }
123
124 /**
125 * Read the size as uint followed by the data. Return both via parameters.
126 * Return the next dword following the data.
127 */
128 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
129 {
130 *size = *ptr++;
131 assert(*data == NULL);
132 if (!*size)
133 return ptr;
134 *data = malloc(*size);
135 return read_data(ptr, *data, *size);
136 }
137
138 /**
139 * Return the shader binary in a buffer. The first 4 bytes contain its size
140 * as integer.
141 */
142 static void *si_get_shader_binary(struct si_shader *shader)
143 {
144 /* There is always a size of data followed by the data itself. */
145 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
146 strlen(shader->binary.llvm_ir_string) + 1 : 0;
147
148 /* Refuse to allocate overly large buffers and guard against integer
149 * overflow. */
150 if (shader->binary.elf_size > UINT_MAX / 4 ||
151 llvm_ir_size > UINT_MAX / 4)
152 return NULL;
153
154 unsigned size =
155 4 + /* total size */
156 4 + /* CRC32 of the data below */
157 align(sizeof(shader->config), 4) +
158 align(sizeof(shader->info), 4) +
159 4 + align(shader->binary.elf_size, 4) +
160 4 + align(llvm_ir_size, 4);
161 void *buffer = CALLOC(1, size);
162 uint32_t *ptr = (uint32_t*)buffer;
163
164 if (!buffer)
165 return NULL;
166
167 *ptr++ = size;
168 ptr++; /* CRC32 is calculated at the end. */
169
170 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
171 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
172 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
173 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
174 assert((char *)ptr - (char *)buffer == size);
175
176 /* Compute CRC32. */
177 ptr = (uint32_t*)buffer;
178 ptr++;
179 *ptr = util_hash_crc32(ptr + 1, size - 8);
180
181 return buffer;
182 }
183
184 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
185 {
186 uint32_t *ptr = (uint32_t*)binary;
187 uint32_t size = *ptr++;
188 uint32_t crc32 = *ptr++;
189 unsigned chunk_size;
190 unsigned elf_size;
191
192 if (util_hash_crc32(ptr, size - 8) != crc32) {
193 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
194 return false;
195 }
196
197 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
198 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
199 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
200 &elf_size);
201 shader->binary.elf_size = elf_size;
202 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
203
204 return true;
205 }
206
207 /**
208 * Insert a shader into the cache. It's assumed the shader is not in the cache.
209 * Use si_shader_cache_load_shader before calling this.
210 */
211 void si_shader_cache_insert_shader(struct si_screen *sscreen,
212 unsigned char ir_sha1_cache_key[20],
213 struct si_shader *shader,
214 bool insert_into_disk_cache)
215 {
216 void *hw_binary;
217 struct hash_entry *entry;
218 uint8_t key[CACHE_KEY_SIZE];
219
220 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
221 if (entry)
222 return; /* already added */
223
224 hw_binary = si_get_shader_binary(shader);
225 if (!hw_binary)
226 return;
227
228 if (_mesa_hash_table_insert(sscreen->shader_cache,
229 mem_dup(ir_sha1_cache_key, 20),
230 hw_binary) == NULL) {
231 FREE(hw_binary);
232 return;
233 }
234
235 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
236 disk_cache_compute_key(sscreen->disk_shader_cache,
237 ir_sha1_cache_key, 20, key);
238 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
239 *((uint32_t *) hw_binary), NULL);
240 }
241 }
242
243 bool si_shader_cache_load_shader(struct si_screen *sscreen,
244 unsigned char ir_sha1_cache_key[20],
245 struct si_shader *shader)
246 {
247 struct hash_entry *entry =
248 _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
249
250 if (entry) {
251 if (si_load_shader_binary(shader, entry->data)) {
252 p_atomic_inc(&sscreen->num_memory_shader_cache_hits);
253 return true;
254 }
255 }
256 p_atomic_inc(&sscreen->num_memory_shader_cache_misses);
257
258 if (!sscreen->disk_shader_cache)
259 return false;
260
261 unsigned char sha1[CACHE_KEY_SIZE];
262 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key,
263 20, sha1);
264
265 size_t binary_size;
266 uint8_t *buffer = disk_cache_get(sscreen->disk_shader_cache, sha1,
267 &binary_size);
268 if (buffer) {
269 if (binary_size >= sizeof(uint32_t) &&
270 *((uint32_t*)buffer) == binary_size) {
271 if (si_load_shader_binary(shader, buffer)) {
272 free(buffer);
273 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
274 shader, false);
275 p_atomic_inc(&sscreen->num_disk_shader_cache_hits);
276 return true;
277 }
278 } else {
279 /* Something has gone wrong discard the item from the cache and
280 * rebuild/link from source.
281 */
282 assert(!"Invalid radeonsi shader disk cache item!");
283 disk_cache_remove(sscreen->disk_shader_cache, sha1);
284 }
285 }
286
287 free(buffer);
288 p_atomic_inc(&sscreen->num_disk_shader_cache_misses);
289 return false;
290 }
291
292 static uint32_t si_shader_cache_key_hash(const void *key)
293 {
294 /* Take the first dword of SHA1. */
295 return *(uint32_t*)key;
296 }
297
298 static bool si_shader_cache_key_equals(const void *a, const void *b)
299 {
300 /* Compare SHA1s. */
301 return memcmp(a, b, 20) == 0;
302 }
303
304 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
305 {
306 FREE((void*)entry->key);
307 FREE(entry->data);
308 }
309
310 bool si_init_shader_cache(struct si_screen *sscreen)
311 {
312 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
313 sscreen->shader_cache =
314 _mesa_hash_table_create(NULL,
315 si_shader_cache_key_hash,
316 si_shader_cache_key_equals);
317
318 return sscreen->shader_cache != NULL;
319 }
320
321 void si_destroy_shader_cache(struct si_screen *sscreen)
322 {
323 if (sscreen->shader_cache)
324 _mesa_hash_table_destroy(sscreen->shader_cache,
325 si_destroy_shader_cache_entry);
326 simple_mtx_destroy(&sscreen->shader_cache_mutex);
327 }
328
329 /* SHADER STATES */
330
331 static void si_set_tesseval_regs(struct si_screen *sscreen,
332 const struct si_shader_selector *tes,
333 struct si_pm4_state *pm4)
334 {
335 const struct si_shader_info *info = &tes->info;
336 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
337 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
338 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
339 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
340 unsigned type, partitioning, topology, distribution_mode;
341
342 switch (tes_prim_mode) {
343 case PIPE_PRIM_LINES:
344 type = V_028B6C_TESS_ISOLINE;
345 break;
346 case PIPE_PRIM_TRIANGLES:
347 type = V_028B6C_TESS_TRIANGLE;
348 break;
349 case PIPE_PRIM_QUADS:
350 type = V_028B6C_TESS_QUAD;
351 break;
352 default:
353 assert(0);
354 return;
355 }
356
357 switch (tes_spacing) {
358 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
359 partitioning = V_028B6C_PART_FRAC_ODD;
360 break;
361 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
362 partitioning = V_028B6C_PART_FRAC_EVEN;
363 break;
364 case PIPE_TESS_SPACING_EQUAL:
365 partitioning = V_028B6C_PART_INTEGER;
366 break;
367 default:
368 assert(0);
369 return;
370 }
371
372 if (tes_point_mode)
373 topology = V_028B6C_OUTPUT_POINT;
374 else if (tes_prim_mode == PIPE_PRIM_LINES)
375 topology = V_028B6C_OUTPUT_LINE;
376 else if (tes_vertex_order_cw)
377 /* for some reason, this must be the other way around */
378 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
379 else
380 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
381
382 if (sscreen->info.has_distributed_tess) {
383 if (sscreen->info.family == CHIP_FIJI ||
384 sscreen->info.family >= CHIP_POLARIS10)
385 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
386 else
387 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
388 } else
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
390
391 assert(pm4->shader);
392 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
393 S_028B6C_PARTITIONING(partitioning) |
394 S_028B6C_TOPOLOGY(topology) |
395 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
396 }
397
398 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
399 * whether the "fractional odd" tessellation spacing is used.
400 *
401 * Possible VGT configurations and which state should set the register:
402 *
403 * Reg set in | VGT shader configuration | Value
404 * ------------------------------------------------------
405 * VS as VS | VS | 30
406 * VS as ES | ES -> GS -> VS | 30
407 * TES as VS | LS -> HS -> VS | 14 or 30
408 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
409 *
410 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
411 */
412 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
413 struct si_shader_selector *sel,
414 struct si_shader *shader,
415 struct si_pm4_state *pm4)
416 {
417 unsigned type = sel->type;
418
419 if (sscreen->info.family < CHIP_POLARIS10 ||
420 sscreen->info.chip_class >= GFX10)
421 return;
422
423 /* VS as VS, or VS as ES: */
424 if ((type == PIPE_SHADER_VERTEX &&
425 (!shader ||
426 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
427 /* TES as VS, or TES as ES: */
428 type == PIPE_SHADER_TESS_EVAL) {
429 unsigned vtx_reuse_depth = 30;
430
431 if (type == PIPE_SHADER_TESS_EVAL &&
432 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
433 PIPE_TESS_SPACING_FRACTIONAL_ODD)
434 vtx_reuse_depth = 14;
435
436 assert(pm4->shader);
437 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
438 }
439 }
440
441 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
442 {
443 if (shader->pm4)
444 si_pm4_clear_state(shader->pm4);
445 else
446 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
447
448 if (shader->pm4) {
449 shader->pm4->shader = shader;
450 return shader->pm4;
451 } else {
452 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
453 return NULL;
454 }
455 }
456
457 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
458 unsigned num_always_on_user_sgprs)
459 {
460 struct si_shader_selector *vs = shader->previous_stage_sel ?
461 shader->previous_stage_sel : shader->selector;
462 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
463
464 /* 1 SGPR is reserved for the vertex buffer pointer. */
465 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
466
467 if (num_vbos_in_user_sgprs)
468 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
469
470 /* Add the pointer to VBO descriptors. */
471 return num_always_on_user_sgprs + 1;
472 }
473
474 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
475 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
476 struct si_shader *shader, bool legacy_vs_prim_id)
477 {
478 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
479 (shader->previous_stage_sel &&
480 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
481
482 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
483 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
484 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
485 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
486 */
487 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
488
489 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
490 return 3;
491 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
492 return 2;
493 else if (is_ls || shader->info.uses_instanceid)
494 return 1;
495 else
496 return 0;
497 }
498
499 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
500 {
501 struct si_pm4_state *pm4;
502 uint64_t va;
503
504 assert(sscreen->info.chip_class <= GFX8);
505
506 pm4 = si_get_shader_pm4_state(shader);
507 if (!pm4)
508 return;
509
510 va = shader->bo->gpu_address;
511 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
512
513 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
514 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
515
516 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
517 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
518 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
519 S_00B528_DX10_CLAMP(1) |
520 S_00B528_FLOAT_MODE(shader->config.float_mode);
521 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
522 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
523 }
524
525 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
526 {
527 struct si_pm4_state *pm4;
528 uint64_t va;
529
530 pm4 = si_get_shader_pm4_state(shader);
531 if (!pm4)
532 return;
533
534 va = shader->bo->gpu_address;
535 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
536
537 if (sscreen->info.chip_class >= GFX9) {
538 if (sscreen->info.chip_class >= GFX10) {
539 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
540 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
541 } else {
542 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
543 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
544 }
545
546 unsigned num_user_sgprs =
547 si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
548
549 shader->config.rsrc2 =
550 S_00B42C_USER_SGPR(num_user_sgprs) |
551 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
552
553 if (sscreen->info.chip_class >= GFX10)
554 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
555 else
556 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
557 } else {
558 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
559 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
560
561 shader->config.rsrc2 =
562 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
563 S_00B42C_OC_LDS_EN(1) |
564 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
565 }
566
567 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
568 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
569 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
570 (sscreen->info.chip_class <= GFX9 ?
571 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
572 S_00B428_DX10_CLAMP(1) |
573 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
574 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
575 S_00B428_FLOAT_MODE(shader->config.float_mode) |
576 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
577 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
578
579 if (sscreen->info.chip_class <= GFX8) {
580 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
581 shader->config.rsrc2);
582 }
583 }
584
585 static void si_emit_shader_es(struct si_context *sctx)
586 {
587 struct si_shader *shader = sctx->queued.named.es->shader;
588 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
589
590 if (!shader)
591 return;
592
593 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
594 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
595 shader->selector->esgs_itemsize / 4);
596
597 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
598 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
599 SI_TRACKED_VGT_TF_PARAM,
600 shader->vgt_tf_param);
601
602 if (shader->vgt_vertex_reuse_block_cntl)
603 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
604 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
605 shader->vgt_vertex_reuse_block_cntl);
606
607 if (initial_cdw != sctx->gfx_cs->current.cdw)
608 sctx->context_roll = true;
609 }
610
611 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
612 {
613 struct si_pm4_state *pm4;
614 unsigned num_user_sgprs;
615 unsigned vgpr_comp_cnt;
616 uint64_t va;
617 unsigned oc_lds_en;
618
619 assert(sscreen->info.chip_class <= GFX8);
620
621 pm4 = si_get_shader_pm4_state(shader);
622 if (!pm4)
623 return;
624
625 pm4->atom.emit = si_emit_shader_es;
626 va = shader->bo->gpu_address;
627 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
628
629 if (shader->selector->type == PIPE_SHADER_VERTEX) {
630 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
631 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
632 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
633 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
634 num_user_sgprs = SI_TES_NUM_USER_SGPR;
635 } else
636 unreachable("invalid shader selector type");
637
638 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
639
640 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
641 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
642 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
643 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
644 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
645 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
646 S_00B328_DX10_CLAMP(1) |
647 S_00B328_FLOAT_MODE(shader->config.float_mode));
648 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
649 S_00B32C_USER_SGPR(num_user_sgprs) |
650 S_00B32C_OC_LDS_EN(oc_lds_en) |
651 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
652
653 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
654 si_set_tesseval_regs(sscreen, shader->selector, pm4);
655
656 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
657 }
658
659 void gfx9_get_gs_info(struct si_shader_selector *es,
660 struct si_shader_selector *gs,
661 struct gfx9_gs_info *out)
662 {
663 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
664 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
665 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
666 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
667
668 /* All these are in dwords: */
669 /* We can't allow using the whole LDS, because GS waves compete with
670 * other shader stages for LDS space. */
671 const unsigned max_lds_size = 8 * 1024;
672 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
673 unsigned esgs_lds_size;
674
675 /* All these are per subgroup: */
676 const unsigned max_out_prims = 32 * 1024;
677 const unsigned max_es_verts = 255;
678 const unsigned ideal_gs_prims = 64;
679 unsigned max_gs_prims, gs_prims;
680 unsigned min_es_verts, es_verts, worst_case_es_verts;
681
682 if (uses_adjacency || gs_num_invocations > 1)
683 max_gs_prims = 127 / gs_num_invocations;
684 else
685 max_gs_prims = 255;
686
687 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
688 * Make sure we don't go over the maximum value.
689 */
690 if (gs->gs_max_out_vertices > 0) {
691 max_gs_prims = MIN2(max_gs_prims,
692 max_out_prims /
693 (gs->gs_max_out_vertices * gs_num_invocations));
694 }
695 assert(max_gs_prims > 0);
696
697 /* If the primitive has adjacency, halve the number of vertices
698 * that will be reused in multiple primitives.
699 */
700 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
701
702 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
703 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
704
705 /* Compute ESGS LDS size based on the worst case number of ES vertices
706 * needed to create the target number of GS prims per subgroup.
707 */
708 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
709
710 /* If total LDS usage is too big, refactor partitions based on ratio
711 * of ESGS item sizes.
712 */
713 if (esgs_lds_size > max_lds_size) {
714 /* Our target GS Prims Per Subgroup was too large. Calculate
715 * the maximum number of GS Prims Per Subgroup that will fit
716 * into LDS, capped by the maximum that the hardware can support.
717 */
718 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
719 max_gs_prims);
720 assert(gs_prims > 0);
721 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
722 max_es_verts);
723
724 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
725 assert(esgs_lds_size <= max_lds_size);
726 }
727
728 /* Now calculate remaining ESGS information. */
729 if (esgs_lds_size)
730 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
731 else
732 es_verts = max_es_verts;
733
734 /* Vertices for adjacency primitives are not always reused, so restore
735 * it for ES_VERTS_PER_SUBGRP.
736 */
737 min_es_verts = gs->gs_input_verts_per_prim;
738
739 /* For normal primitives, the VGT only checks if they are past the ES
740 * verts per subgroup after allocating a full GS primitive and if they
741 * are, kick off a new subgroup. But if those additional ES verts are
742 * unique (e.g. not reused) we need to make sure there is enough LDS
743 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
744 */
745 es_verts -= min_es_verts - 1;
746
747 out->es_verts_per_subgroup = es_verts;
748 out->gs_prims_per_subgroup = gs_prims;
749 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
750 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
751 gs->gs_max_out_vertices;
752 out->esgs_ring_size = 4 * esgs_lds_size;
753
754 assert(out->max_prims_per_subgroup <= max_out_prims);
755 }
756
757 static void si_emit_shader_gs(struct si_context *sctx)
758 {
759 struct si_shader *shader = sctx->queued.named.gs->shader;
760 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
761
762 if (!shader)
763 return;
764
765 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
766 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
767 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
768 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
769 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
770 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
771 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
772
773 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
774 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
775 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
776 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
777
778 /* R_028B38_VGT_GS_MAX_VERT_OUT */
779 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
780 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
781 shader->ctx_reg.gs.vgt_gs_max_vert_out);
782
783 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
784 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
785 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
786 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
787 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
788 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
789 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
790 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
791
792 /* R_028B90_VGT_GS_INSTANCE_CNT */
793 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
794 SI_TRACKED_VGT_GS_INSTANCE_CNT,
795 shader->ctx_reg.gs.vgt_gs_instance_cnt);
796
797 if (sctx->chip_class >= GFX9) {
798 /* R_028A44_VGT_GS_ONCHIP_CNTL */
799 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
800 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
801 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
802 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
803 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
804 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
805 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
806 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
807 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
808 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
809 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
810
811 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
812 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
813 SI_TRACKED_VGT_TF_PARAM,
814 shader->vgt_tf_param);
815 if (shader->vgt_vertex_reuse_block_cntl)
816 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
817 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
818 shader->vgt_vertex_reuse_block_cntl);
819 }
820
821 if (initial_cdw != sctx->gfx_cs->current.cdw)
822 sctx->context_roll = true;
823 }
824
825 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
826 {
827 struct si_shader_selector *sel = shader->selector;
828 const ubyte *num_components = sel->info.num_stream_output_components;
829 unsigned gs_num_invocations = sel->gs_num_invocations;
830 struct si_pm4_state *pm4;
831 uint64_t va;
832 unsigned max_stream = sel->max_gs_stream;
833 unsigned offset;
834
835 pm4 = si_get_shader_pm4_state(shader);
836 if (!pm4)
837 return;
838
839 pm4->atom.emit = si_emit_shader_gs;
840
841 offset = num_components[0] * sel->gs_max_out_vertices;
842 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
843
844 if (max_stream >= 1)
845 offset += num_components[1] * sel->gs_max_out_vertices;
846 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
847
848 if (max_stream >= 2)
849 offset += num_components[2] * sel->gs_max_out_vertices;
850 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
851
852 if (max_stream >= 3)
853 offset += num_components[3] * sel->gs_max_out_vertices;
854 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
855
856 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
857 assert(offset < (1 << 15));
858
859 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
860
861 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
862 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
863 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
864 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
865
866 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
867 S_028B90_ENABLE(gs_num_invocations > 0);
868
869 va = shader->bo->gpu_address;
870 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
871
872 if (sscreen->info.chip_class >= GFX9) {
873 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
874 unsigned es_type = shader->key.part.gs.es->type;
875 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
876
877 if (es_type == PIPE_SHADER_VERTEX) {
878 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
879 } else if (es_type == PIPE_SHADER_TESS_EVAL)
880 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
881 else
882 unreachable("invalid shader selector type");
883
884 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
885 * VGPR[0:4] are always loaded.
886 */
887 if (sel->info.uses_invocationid)
888 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
889 else if (sel->info.uses_primid)
890 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
891 else if (input_prim >= PIPE_PRIM_TRIANGLES)
892 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
893 else
894 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
895
896 unsigned num_user_sgprs;
897 if (es_type == PIPE_SHADER_VERTEX)
898 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
899 else
900 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
901
902 if (sscreen->info.chip_class >= GFX10) {
903 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
904 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
905 } else {
906 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
907 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
908 }
909
910 uint32_t rsrc1 =
911 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
912 S_00B228_DX10_CLAMP(1) |
913 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
914 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
915 S_00B228_FLOAT_MODE(shader->config.float_mode) |
916 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
917 uint32_t rsrc2 =
918 S_00B22C_USER_SGPR(num_user_sgprs) |
919 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
920 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
921 S_00B22C_LDS_SIZE(shader->config.lds_size) |
922 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
923
924 if (sscreen->info.chip_class >= GFX10) {
925 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
926 } else {
927 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
928 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
929 }
930
931 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
932 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
933
934 if (sscreen->info.chip_class >= GFX10) {
935 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
936 S_00B204_CU_EN(0xffff) |
937 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
938 }
939
940 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
941 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
942 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
943 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
944 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
945 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
946 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
947 shader->key.part.gs.es->esgs_itemsize / 4;
948
949 if (es_type == PIPE_SHADER_TESS_EVAL)
950 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
951
952 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
953 NULL, pm4);
954 } else {
955 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
956 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
957
958 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
959 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
960 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
961 S_00B228_DX10_CLAMP(1) |
962 S_00B228_FLOAT_MODE(shader->config.float_mode));
963 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
964 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
965 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
966 }
967 }
968
969 static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
970 {
971 enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
972
973 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
974 sctx->tracked_regs.reg_value[reg] != value) {
975 struct radeon_cmdbuf *cs = sctx->gfx_cs;
976
977 if (sctx->family == CHIP_NAVI10 ||
978 sctx->family == CHIP_NAVI12 ||
979 sctx->family == CHIP_NAVI14) {
980 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
981 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
982 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
983 }
984
985 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
986
987 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
988 sctx->tracked_regs.reg_value[reg] = value;
989 }
990 }
991
992 /* Common tail code for NGG primitive shaders. */
993 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
994 struct si_shader *shader,
995 unsigned initial_cdw)
996 {
997 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
998 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
999 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
1000 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
1001 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
1002 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
1003 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1004 SI_TRACKED_VGT_PRIMITIVEID_EN,
1005 shader->ctx_reg.ngg.vgt_primitiveid_en);
1006 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1007 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1008 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
1009 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
1010 SI_TRACKED_VGT_GS_INSTANCE_CNT,
1011 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
1012 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
1013 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
1014 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
1015 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1016 SI_TRACKED_SPI_VS_OUT_CONFIG,
1017 shader->ctx_reg.ngg.spi_vs_out_config);
1018 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
1019 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
1020 shader->ctx_reg.ngg.spi_shader_idx_format,
1021 shader->ctx_reg.ngg.spi_shader_pos_format);
1022 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1023 SI_TRACKED_PA_CL_VTE_CNTL,
1024 shader->ctx_reg.ngg.pa_cl_vte_cntl);
1025 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1026 SI_TRACKED_PA_CL_NGG_CNTL,
1027 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1028
1029 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1030 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1031 shader->pa_cl_vs_out_cntl,
1032 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1033
1034 if (initial_cdw != sctx->gfx_cs->current.cdw)
1035 sctx->context_roll = true;
1036
1037 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1038 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
1039 }
1040
1041 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1042 {
1043 struct si_shader *shader = sctx->queued.named.gs->shader;
1044 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1045
1046 if (!shader)
1047 return;
1048
1049 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1050 }
1051
1052 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1053 {
1054 struct si_shader *shader = sctx->queued.named.gs->shader;
1055 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1056
1057 if (!shader)
1058 return;
1059
1060 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1061 SI_TRACKED_VGT_TF_PARAM,
1062 shader->vgt_tf_param);
1063
1064 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1065 }
1066
1067 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1068 {
1069 struct si_shader *shader = sctx->queued.named.gs->shader;
1070 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1071
1072 if (!shader)
1073 return;
1074
1075 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1076 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1077 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1078
1079 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1080 }
1081
1082 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1083 {
1084 struct si_shader *shader = sctx->queued.named.gs->shader;
1085 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1086
1087 if (!shader)
1088 return;
1089
1090 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1091 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1092 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1093 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1094 SI_TRACKED_VGT_TF_PARAM,
1095 shader->vgt_tf_param);
1096
1097 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1098 }
1099
1100 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1101 {
1102 if (gs->type == PIPE_SHADER_GEOMETRY)
1103 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1104
1105 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1106 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1107 return PIPE_PRIM_POINTS;
1108 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1109 return PIPE_PRIM_LINES;
1110 return PIPE_PRIM_TRIANGLES;
1111 }
1112
1113 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1114 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1115 }
1116
1117 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1118 {
1119 bool misc_vec_ena =
1120 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1121 sel->info.writes_layer || sel->info.writes_viewport_index;
1122 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1123 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1124 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1125 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1126 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1127 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1128 }
1129
1130 /**
1131 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1132 * in NGG mode.
1133 */
1134 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1135 {
1136 const struct si_shader_selector *gs_sel = shader->selector;
1137 const struct si_shader_info *gs_info = &gs_sel->info;
1138 enum pipe_shader_type gs_type = shader->selector->type;
1139 const struct si_shader_selector *es_sel =
1140 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1141 const struct si_shader_info *es_info = &es_sel->info;
1142 enum pipe_shader_type es_type = es_sel->type;
1143 unsigned num_user_sgprs;
1144 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1145 uint64_t va;
1146 unsigned window_space =
1147 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1148 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1149 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1150 unsigned input_prim = si_get_input_prim(gs_sel);
1151 bool break_wave_at_eoi = false;
1152 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1153 if (!pm4)
1154 return;
1155
1156 if (es_type == PIPE_SHADER_TESS_EVAL) {
1157 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1158 : gfx10_emit_shader_ngg_tess_nogs;
1159 } else {
1160 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1161 : gfx10_emit_shader_ngg_notess_nogs;
1162 }
1163
1164 va = shader->bo->gpu_address;
1165 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1166
1167 if (es_type == PIPE_SHADER_VERTEX) {
1168 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1169
1170 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1171 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1172 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1173 } else {
1174 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1175 }
1176 } else {
1177 assert(es_type == PIPE_SHADER_TESS_EVAL);
1178 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1179 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1180
1181 if (es_enable_prim_id || gs_info->uses_primid)
1182 break_wave_at_eoi = true;
1183 }
1184
1185 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1186 * VGPR[0:4] are always loaded.
1187 *
1188 * Vertex shaders always need to load VGPR3, because they need to
1189 * pass edge flags for decomposed primitives (such as quads) to the PA
1190 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1191 */
1192 if (gs_info->uses_invocationid ||
1193 (gs_type == PIPE_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1194 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1195 else if ((gs_type == PIPE_SHADER_GEOMETRY && gs_info->uses_primid) ||
1196 (gs_type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1197 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1198 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1199 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1200 else
1201 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1202
1203 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1204 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1205 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1206 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1207 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1208 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1209 S_00B228_DX10_CLAMP(1) |
1210 S_00B228_MEM_ORDERED(1) |
1211 S_00B228_WGP_MODE(1) |
1212 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1213 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1214 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1215 S_00B22C_USER_SGPR(num_user_sgprs) |
1216 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1217 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1218 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1219 S_00B22C_LDS_SIZE(shader->config.lds_size));
1220
1221 /* Determine LATE_ALLOC_GS. */
1222 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
1223 unsigned late_alloc_wave64; /* The limit is per SH. */
1224
1225 /* For Wave32, the hw will launch twice the number of late
1226 * alloc waves, so 1 == 2x wave32.
1227 *
1228 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1229 */
1230 if (sscreen->info.family == CHIP_NAVI14)
1231 late_alloc_wave64 = 0;
1232 else if (num_cu_per_sh <= 6)
1233 late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
1234 else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
1235 late_alloc_wave64 = (num_cu_per_sh - 2) * 6;
1236 else
1237 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
1238
1239 /* Limit LATE_ALLOC_GS for prevent a hang (hw bug). */
1240 if (sscreen->info.family == CHIP_NAVI10 ||
1241 sscreen->info.family == CHIP_NAVI12 ||
1242 sscreen->info.family == CHIP_NAVI14)
1243 late_alloc_wave64 = MIN2(late_alloc_wave64, 64);
1244
1245 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1246 S_00B204_CU_EN(0xffff) |
1247 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64));
1248
1249 nparams = MAX2(shader->info.nr_param_exports, 1);
1250 shader->ctx_reg.ngg.spi_vs_out_config =
1251 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1252 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1253
1254 shader->ctx_reg.ngg.spi_shader_idx_format =
1255 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1256 shader->ctx_reg.ngg.spi_shader_pos_format =
1257 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1258 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1259 V_02870C_SPI_SHADER_4COMP :
1260 V_02870C_SPI_SHADER_NONE) |
1261 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1262 V_02870C_SPI_SHADER_4COMP :
1263 V_02870C_SPI_SHADER_NONE) |
1264 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1265 V_02870C_SPI_SHADER_4COMP :
1266 V_02870C_SPI_SHADER_NONE);
1267
1268 shader->ctx_reg.ngg.vgt_primitiveid_en =
1269 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1270 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1271 gs_sel->info.writes_primid);
1272
1273 if (gs_type == PIPE_SHADER_GEOMETRY) {
1274 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1275 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1276 } else {
1277 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1278 }
1279
1280 if (es_type == PIPE_SHADER_TESS_EVAL)
1281 si_set_tesseval_regs(sscreen, es_sel, pm4);
1282
1283 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1284 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1285 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1286 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1287 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1288 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1289 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1290 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1291 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1292 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1293 S_028B90_CNT(gs_num_invocations) |
1294 S_028B90_ENABLE(gs_num_invocations > 1) |
1295 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1296 shader->ngg.max_vert_out_per_gs_instance);
1297
1298 /* Always output hw-generated edge flags and pass them via the prim
1299 * export to prevent drawing lines on internal edges of decomposed
1300 * primitives (such as quads) with polygon mode = lines. Only VS needs
1301 * this.
1302 */
1303 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1304 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1305 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1306
1307 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1308 float oversub_pc_factor = 0.25;
1309
1310 if (shader->key.opt.ngg_culling) {
1311 /* Be more aggressive with NGG culling. */
1312 if (shader->info.nr_param_exports > 4)
1313 oversub_pc_factor = 1;
1314 else if (shader->info.nr_param_exports > 2)
1315 oversub_pc_factor = 0.75;
1316 else
1317 oversub_pc_factor = 0.5;
1318 }
1319
1320 unsigned oversub_pc_lines = sscreen->info.pc_lines * oversub_pc_factor;
1321 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1322 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1323
1324 if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
1325 shader->ge_cntl =
1326 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1327 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims * 3);
1328 } else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP) {
1329 shader->ge_cntl =
1330 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1331 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims + 2);
1332 } else {
1333 shader->ge_cntl =
1334 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1335 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1336 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1337
1338 /* Bug workaround for a possible hang with non-tessellation cases.
1339 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1340 *
1341 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1342 */
1343 if ((sscreen->info.family == CHIP_NAVI10 ||
1344 sscreen->info.family == CHIP_NAVI12 ||
1345 sscreen->info.family == CHIP_NAVI14) &&
1346 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1347 shader->ngg.hw_max_esverts != 256) {
1348 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1349
1350 if (shader->ngg.hw_max_esverts > 5) {
1351 shader->ge_cntl |=
1352 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1353 }
1354 }
1355 }
1356
1357 if (window_space) {
1358 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1359 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1360 } else {
1361 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1362 S_028818_VTX_W0_FMT(1) |
1363 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1364 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1365 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1366 }
1367 }
1368
1369 static void si_emit_shader_vs(struct si_context *sctx)
1370 {
1371 struct si_shader *shader = sctx->queued.named.vs->shader;
1372 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1373
1374 if (!shader)
1375 return;
1376
1377 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1378 SI_TRACKED_VGT_GS_MODE,
1379 shader->ctx_reg.vs.vgt_gs_mode);
1380 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1381 SI_TRACKED_VGT_PRIMITIVEID_EN,
1382 shader->ctx_reg.vs.vgt_primitiveid_en);
1383
1384 if (sctx->chip_class <= GFX8) {
1385 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1386 SI_TRACKED_VGT_REUSE_OFF,
1387 shader->ctx_reg.vs.vgt_reuse_off);
1388 }
1389
1390 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1391 SI_TRACKED_SPI_VS_OUT_CONFIG,
1392 shader->ctx_reg.vs.spi_vs_out_config);
1393
1394 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1395 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1396 shader->ctx_reg.vs.spi_shader_pos_format);
1397
1398 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1399 SI_TRACKED_PA_CL_VTE_CNTL,
1400 shader->ctx_reg.vs.pa_cl_vte_cntl);
1401
1402 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1403 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1404 SI_TRACKED_VGT_TF_PARAM,
1405 shader->vgt_tf_param);
1406
1407 if (shader->vgt_vertex_reuse_block_cntl)
1408 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1409 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1410 shader->vgt_vertex_reuse_block_cntl);
1411
1412 /* Required programming for tessellation. (legacy pipeline only) */
1413 if (sctx->chip_class == GFX10 &&
1414 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1415 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1416 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1417 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1418 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1419 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1420 }
1421
1422 if (sctx->chip_class >= GFX10) {
1423 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1424 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1425 shader->pa_cl_vs_out_cntl,
1426 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1427 }
1428
1429 if (initial_cdw != sctx->gfx_cs->current.cdw)
1430 sctx->context_roll = true;
1431
1432 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1433 if (sctx->chip_class >= GFX10)
1434 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
1435 }
1436
1437 /**
1438 * Compute the state for \p shader, which will run as a vertex shader on the
1439 * hardware.
1440 *
1441 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1442 * is the copy shader.
1443 */
1444 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1445 struct si_shader_selector *gs)
1446 {
1447 const struct si_shader_info *info = &shader->selector->info;
1448 struct si_pm4_state *pm4;
1449 unsigned num_user_sgprs, vgpr_comp_cnt;
1450 uint64_t va;
1451 unsigned nparams, oc_lds_en;
1452 unsigned window_space =
1453 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1454 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1455
1456 pm4 = si_get_shader_pm4_state(shader);
1457 if (!pm4)
1458 return;
1459
1460 pm4->atom.emit = si_emit_shader_vs;
1461
1462 /* We always write VGT_GS_MODE in the VS state, because every switch
1463 * between different shader pipelines involving a different GS or no
1464 * GS at all involves a switch of the VS (different GS use different
1465 * copy shaders). On the other hand, when the API switches from a GS to
1466 * no GS and then back to the same GS used originally, the GS state is
1467 * not sent again.
1468 */
1469 if (!gs) {
1470 unsigned mode = V_028A40_GS_OFF;
1471
1472 /* PrimID needs GS scenario A. */
1473 if (enable_prim_id)
1474 mode = V_028A40_GS_SCENARIO_A;
1475
1476 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1477 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1478 } else {
1479 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1480 sscreen->info.chip_class);
1481 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1482 }
1483
1484 if (sscreen->info.chip_class <= GFX8) {
1485 /* Reuse needs to be set off if we write oViewport. */
1486 shader->ctx_reg.vs.vgt_reuse_off =
1487 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1488 }
1489
1490 va = shader->bo->gpu_address;
1491 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1492
1493 if (gs) {
1494 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1495 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1496 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1497 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1498
1499 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1500 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1501 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1502 } else {
1503 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1504 }
1505 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1506 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1507 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1508 } else
1509 unreachable("invalid shader selector type");
1510
1511 /* VS is required to export at least one param. */
1512 nparams = MAX2(shader->info.nr_param_exports, 1);
1513 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1514
1515 if (sscreen->info.chip_class >= GFX10) {
1516 shader->ctx_reg.vs.spi_vs_out_config |=
1517 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1518 }
1519
1520 shader->ctx_reg.vs.spi_shader_pos_format =
1521 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1522 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1523 V_02870C_SPI_SHADER_4COMP :
1524 V_02870C_SPI_SHADER_NONE) |
1525 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1526 V_02870C_SPI_SHADER_4COMP :
1527 V_02870C_SPI_SHADER_NONE) |
1528 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1529 V_02870C_SPI_SHADER_4COMP :
1530 V_02870C_SPI_SHADER_NONE);
1531 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1532 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1533 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1534
1535 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1536
1537 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1538 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1539
1540 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1541 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1542 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1543 S_00B128_DX10_CLAMP(1) |
1544 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1545 S_00B128_FLOAT_MODE(shader->config.float_mode);
1546 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1547 S_00B12C_OC_LDS_EN(oc_lds_en) |
1548 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1549
1550 if (sscreen->info.chip_class >= GFX10)
1551 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1552 else if (sscreen->info.chip_class == GFX9)
1553 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1554
1555 if (sscreen->info.chip_class <= GFX9)
1556 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1557
1558 if (!sscreen->use_ngg_streamout) {
1559 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1560 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1561 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1562 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1563 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1564 }
1565
1566 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1567 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1568
1569 if (window_space)
1570 shader->ctx_reg.vs.pa_cl_vte_cntl =
1571 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1572 else
1573 shader->ctx_reg.vs.pa_cl_vte_cntl =
1574 S_028818_VTX_W0_FMT(1) |
1575 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1576 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1577 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1578
1579 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1580 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1581
1582 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1583 }
1584
1585 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1586 {
1587 struct si_shader_info *info = &ps->selector->info;
1588 unsigned num_colors = !!(info->colors_read & 0x0f) +
1589 !!(info->colors_read & 0xf0);
1590 unsigned num_interp = ps->selector->info.num_inputs +
1591 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1592
1593 assert(num_interp <= 32);
1594 return MIN2(num_interp, 32);
1595 }
1596
1597 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1598 {
1599 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1600 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1601
1602 /* If the i-th target format is set, all previous target formats must
1603 * be non-zero to avoid hangs.
1604 */
1605 for (i = 0; i < num_targets; i++)
1606 if (!(value & (0xf << (i * 4))))
1607 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1608
1609 return value;
1610 }
1611
1612 static void si_emit_shader_ps(struct si_context *sctx)
1613 {
1614 struct si_shader *shader = sctx->queued.named.ps->shader;
1615 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1616
1617 if (!shader)
1618 return;
1619
1620 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1621 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1622 SI_TRACKED_SPI_PS_INPUT_ENA,
1623 shader->ctx_reg.ps.spi_ps_input_ena,
1624 shader->ctx_reg.ps.spi_ps_input_addr);
1625
1626 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1627 SI_TRACKED_SPI_BARYC_CNTL,
1628 shader->ctx_reg.ps.spi_baryc_cntl);
1629 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1630 SI_TRACKED_SPI_PS_IN_CONTROL,
1631 shader->ctx_reg.ps.spi_ps_in_control);
1632
1633 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1634 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1635 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1636 shader->ctx_reg.ps.spi_shader_z_format,
1637 shader->ctx_reg.ps.spi_shader_col_format);
1638
1639 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1640 SI_TRACKED_CB_SHADER_MASK,
1641 shader->ctx_reg.ps.cb_shader_mask);
1642
1643 if (initial_cdw != sctx->gfx_cs->current.cdw)
1644 sctx->context_roll = true;
1645 }
1646
1647 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1648 {
1649 struct si_shader_info *info = &shader->selector->info;
1650 struct si_pm4_state *pm4;
1651 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1652 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1653 uint64_t va;
1654 unsigned input_ena = shader->config.spi_ps_input_ena;
1655
1656 /* we need to enable at least one of them, otherwise we hang the GPU */
1657 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1658 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1659 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1660 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1661 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1662 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1663 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1664 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1665 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1666 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1667 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1668 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1669 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1670 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1671
1672 /* Validate interpolation optimization flags (read as implications). */
1673 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1674 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1675 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1676 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1677 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1678 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1679 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1680 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1681 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1682 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1683 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1684 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1685 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1686 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1687 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1688 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1689 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1690 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1691
1692 /* Validate cases when the optimizations are off (read as implications). */
1693 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1694 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1695 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1696 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1697 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1698 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1699
1700 pm4 = si_get_shader_pm4_state(shader);
1701 if (!pm4)
1702 return;
1703
1704 pm4->atom.emit = si_emit_shader_ps;
1705
1706 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1707 * Possible vaules:
1708 * 0 -> Position = pixel center
1709 * 1 -> Position = pixel centroid
1710 * 2 -> Position = at sample position
1711 *
1712 * From GLSL 4.5 specification, section 7.1:
1713 * "The variable gl_FragCoord is available as an input variable from
1714 * within fragment shaders and it holds the window relative coordinates
1715 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1716 * value can be for any location within the pixel, or one of the
1717 * fragment samples. The use of centroid does not further restrict
1718 * this value to be inside the current primitive."
1719 *
1720 * Meaning that centroid has no effect and we can return anything within
1721 * the pixel. Thus, return the value at sample position, because that's
1722 * the most accurate one shaders can get.
1723 */
1724 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1725
1726 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1727 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1728 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1729
1730 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1731 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1732
1733 /* Ensure that some export memory is always allocated, for two reasons:
1734 *
1735 * 1) Correctness: The hardware ignores the EXEC mask if no export
1736 * memory is allocated, so KILL and alpha test do not work correctly
1737 * without this.
1738 * 2) Performance: Every shader needs at least a NULL export, even when
1739 * it writes no color/depth output. The NULL export instruction
1740 * stalls without this setting.
1741 *
1742 * Don't add this to CB_SHADER_MASK.
1743 *
1744 * GFX10 supports pixel shaders without exports by setting both
1745 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1746 * instructions if any are present.
1747 */
1748 if ((sscreen->info.chip_class <= GFX9 ||
1749 info->uses_kill ||
1750 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1751 !spi_shader_col_format &&
1752 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1753 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1754
1755 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1756 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1757
1758 /* Set interpolation controls. */
1759 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1760 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1761
1762 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1763 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1764 shader->ctx_reg.ps.spi_shader_z_format =
1765 ac_get_spi_shader_z_format(info->writes_z,
1766 info->writes_stencil,
1767 info->writes_samplemask);
1768 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1769 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1770
1771 va = shader->bo->gpu_address;
1772 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1773 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1774 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1775
1776 uint32_t rsrc1 =
1777 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1778 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1779 S_00B028_DX10_CLAMP(1) |
1780 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1781 S_00B028_FLOAT_MODE(shader->config.float_mode);
1782
1783 if (sscreen->info.chip_class < GFX10) {
1784 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1785 }
1786
1787 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1788 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1789 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1790 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1791 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1792 }
1793
1794 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1795 struct si_shader *shader)
1796 {
1797 switch (shader->selector->type) {
1798 case PIPE_SHADER_VERTEX:
1799 if (shader->key.as_ls)
1800 si_shader_ls(sscreen, shader);
1801 else if (shader->key.as_es)
1802 si_shader_es(sscreen, shader);
1803 else if (shader->key.as_ngg)
1804 gfx10_shader_ngg(sscreen, shader);
1805 else
1806 si_shader_vs(sscreen, shader, NULL);
1807 break;
1808 case PIPE_SHADER_TESS_CTRL:
1809 si_shader_hs(sscreen, shader);
1810 break;
1811 case PIPE_SHADER_TESS_EVAL:
1812 if (shader->key.as_es)
1813 si_shader_es(sscreen, shader);
1814 else if (shader->key.as_ngg)
1815 gfx10_shader_ngg(sscreen, shader);
1816 else
1817 si_shader_vs(sscreen, shader, NULL);
1818 break;
1819 case PIPE_SHADER_GEOMETRY:
1820 if (shader->key.as_ngg)
1821 gfx10_shader_ngg(sscreen, shader);
1822 else
1823 si_shader_gs(sscreen, shader);
1824 break;
1825 case PIPE_SHADER_FRAGMENT:
1826 si_shader_ps(sscreen, shader);
1827 break;
1828 default:
1829 assert(0);
1830 }
1831 }
1832
1833 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1834 {
1835 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1836 return sctx->queued.named.dsa->alpha_func;
1837 }
1838
1839 void si_shader_selector_key_vs(struct si_context *sctx,
1840 struct si_shader_selector *vs,
1841 struct si_shader_key *key,
1842 struct si_vs_prolog_bits *prolog_key)
1843 {
1844 if (!sctx->vertex_elements ||
1845 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1846 return;
1847
1848 struct si_vertex_elements *elts = sctx->vertex_elements;
1849
1850 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1851 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1852 prolog_key->unpack_instance_id_from_vertex_id =
1853 sctx->prim_discard_cs_instancing;
1854
1855 /* Prefer a monolithic shader to allow scheduling divisions around
1856 * VBO loads. */
1857 if (prolog_key->instance_divisor_is_fetched)
1858 key->opt.prefer_mono = 1;
1859
1860 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1861 unsigned count_mask = (1 << count) - 1;
1862 unsigned fix = elts->fix_fetch_always & count_mask;
1863 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1864
1865 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1866 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1867 while (mask) {
1868 unsigned i = u_bit_scan(&mask);
1869 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1870 unsigned vbidx = elts->vertex_buffer_index[i];
1871 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1872 unsigned align_mask = (1 << log_hw_load_size) - 1;
1873 if (vb->buffer_offset & align_mask ||
1874 vb->stride & align_mask) {
1875 fix |= 1 << i;
1876 opencode |= 1 << i;
1877 }
1878 }
1879 }
1880
1881 while (fix) {
1882 unsigned i = u_bit_scan(&fix);
1883 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1884 }
1885 key->mono.vs_fetch_opencode = opencode;
1886 }
1887
1888 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1889 struct si_shader_selector *vs,
1890 struct si_shader_key *key)
1891 {
1892 struct si_shader_selector *ps = sctx->ps_shader.cso;
1893
1894 key->opt.clip_disable =
1895 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1896 (vs->info.clipdist_writemask ||
1897 vs->info.writes_clipvertex) &&
1898 !vs->info.culldist_writemask;
1899
1900 /* Find out if PS is disabled. */
1901 bool ps_disabled = true;
1902 if (ps) {
1903 bool ps_modifies_zs = ps->info.uses_kill ||
1904 ps->info.writes_z ||
1905 ps->info.writes_stencil ||
1906 ps->info.writes_samplemask ||
1907 sctx->queued.named.blend->alpha_to_coverage ||
1908 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1909 unsigned ps_colormask = si_get_total_colormask(sctx);
1910
1911 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1912 (!ps_colormask &&
1913 !ps_modifies_zs &&
1914 !ps->info.writes_memory);
1915 }
1916
1917 /* Find out which VS outputs aren't used by the PS. */
1918 uint64_t outputs_written = vs->outputs_written_before_ps;
1919 uint64_t inputs_read = 0;
1920
1921 /* Ignore outputs that are not passed from VS to PS. */
1922 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1923 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1924 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1925
1926 if (!ps_disabled) {
1927 inputs_read = ps->inputs_read;
1928 }
1929
1930 uint64_t linked = outputs_written & inputs_read;
1931
1932 key->opt.kill_outputs = ~linked & outputs_written;
1933 key->opt.ngg_culling = sctx->ngg_culling;
1934 }
1935
1936 /* Compute the key for the hw shader variant */
1937 static inline void si_shader_selector_key(struct pipe_context *ctx,
1938 struct si_shader_selector *sel,
1939 union si_vgt_stages_key stages_key,
1940 struct si_shader_key *key)
1941 {
1942 struct si_context *sctx = (struct si_context *)ctx;
1943
1944 memset(key, 0, sizeof(*key));
1945
1946 switch (sel->type) {
1947 case PIPE_SHADER_VERTEX:
1948 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1949
1950 if (sctx->tes_shader.cso)
1951 key->as_ls = 1;
1952 else if (sctx->gs_shader.cso) {
1953 key->as_es = 1;
1954 key->as_ngg = stages_key.u.ngg;
1955 } else {
1956 key->as_ngg = stages_key.u.ngg;
1957 si_shader_selector_key_hw_vs(sctx, sel, key);
1958
1959 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1960 key->mono.u.vs_export_prim_id = 1;
1961 }
1962 break;
1963 case PIPE_SHADER_TESS_CTRL:
1964 if (sctx->chip_class >= GFX9) {
1965 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1966 key, &key->part.tcs.ls_prolog);
1967 key->part.tcs.ls = sctx->vs_shader.cso;
1968
1969 /* When the LS VGPR fix is needed, monolithic shaders
1970 * can:
1971 * - avoid initializing EXEC in both the LS prolog
1972 * and the LS main part when !vs_needs_prolog
1973 * - remove the fixup for unused input VGPRs
1974 */
1975 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1976
1977 /* The LS output / HS input layout can be communicated
1978 * directly instead of via user SGPRs for merged LS-HS.
1979 * The LS VGPR fix prefers this too.
1980 */
1981 key->opt.prefer_mono = 1;
1982 }
1983
1984 key->part.tcs.epilog.prim_mode =
1985 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1986 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1987 sel->info.tessfactors_are_def_in_all_invocs;
1988 key->part.tcs.epilog.tes_reads_tess_factors =
1989 sctx->tes_shader.cso->info.reads_tess_factors;
1990
1991 if (sel == sctx->fixed_func_tcs_shader.cso)
1992 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1993 break;
1994 case PIPE_SHADER_TESS_EVAL:
1995 key->as_ngg = stages_key.u.ngg;
1996
1997 if (sctx->gs_shader.cso)
1998 key->as_es = 1;
1999 else {
2000 si_shader_selector_key_hw_vs(sctx, sel, key);
2001
2002 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
2003 key->mono.u.vs_export_prim_id = 1;
2004 }
2005 break;
2006 case PIPE_SHADER_GEOMETRY:
2007 if (sctx->chip_class >= GFX9) {
2008 if (sctx->tes_shader.cso) {
2009 key->part.gs.es = sctx->tes_shader.cso;
2010 } else {
2011 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
2012 key, &key->part.gs.vs_prolog);
2013 key->part.gs.es = sctx->vs_shader.cso;
2014 key->part.gs.prolog.gfx9_prev_is_vs = 1;
2015 }
2016
2017 key->as_ngg = stages_key.u.ngg;
2018
2019 /* Merged ES-GS can have unbalanced wave usage.
2020 *
2021 * ES threads are per-vertex, while GS threads are
2022 * per-primitive. So without any amplification, there
2023 * are fewer GS threads than ES threads, which can result
2024 * in empty (no-op) GS waves. With too much amplification,
2025 * there are more GS threads than ES threads, which
2026 * can result in empty (no-op) ES waves.
2027 *
2028 * Non-monolithic shaders are implemented by setting EXEC
2029 * at the beginning of shader parts, and don't jump to
2030 * the end if EXEC is 0.
2031 *
2032 * Monolithic shaders use conditional blocks, so they can
2033 * jump and skip empty waves of ES or GS. So set this to
2034 * always use optimized variants, which are monolithic.
2035 */
2036 key->opt.prefer_mono = 1;
2037 }
2038 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
2039 break;
2040 case PIPE_SHADER_FRAGMENT: {
2041 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2042 struct si_state_blend *blend = sctx->queued.named.blend;
2043
2044 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2045 sel->info.colors_written == 0x1)
2046 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
2047
2048 /* Select the shader color format based on whether
2049 * blending or alpha are needed.
2050 */
2051 key->part.ps.epilog.spi_shader_col_format =
2052 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
2053 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
2054 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
2055 sctx->framebuffer.spi_shader_col_format_blend) |
2056 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
2057 sctx->framebuffer.spi_shader_col_format_alpha) |
2058 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
2059 sctx->framebuffer.spi_shader_col_format);
2060 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
2061
2062 /* The output for dual source blending should have
2063 * the same format as the first output.
2064 */
2065 if (blend->dual_src_blend) {
2066 key->part.ps.epilog.spi_shader_col_format |=
2067 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
2068 }
2069
2070 /* If alpha-to-coverage is enabled, we have to export alpha
2071 * even if there is no color buffer.
2072 */
2073 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
2074 blend->alpha_to_coverage)
2075 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
2076
2077 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
2078 * to the range supported by the type if a channel has less
2079 * than 16 bits and the export format is 16_ABGR.
2080 */
2081 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
2082 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
2083 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
2084 }
2085
2086 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
2087 if (!key->part.ps.epilog.last_cbuf) {
2088 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
2089 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
2090 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
2091 }
2092
2093 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
2094 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
2095
2096 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
2097 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
2098
2099 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
2100 rs->multisample_enable;
2101
2102 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
2103 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
2104 (is_line && rs->line_smooth)) &&
2105 sctx->framebuffer.nr_samples <= 1;
2106 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2107
2108 if (sctx->ps_iter_samples > 1 &&
2109 sel->info.reads_samplemask) {
2110 key->part.ps.prolog.samplemask_log_ps_iter =
2111 util_logbase2(sctx->ps_iter_samples);
2112 }
2113
2114 if (rs->force_persample_interp &&
2115 rs->multisample_enable &&
2116 sctx->framebuffer.nr_samples > 1 &&
2117 sctx->ps_iter_samples > 1) {
2118 key->part.ps.prolog.force_persp_sample_interp =
2119 sel->info.uses_persp_center ||
2120 sel->info.uses_persp_centroid;
2121
2122 key->part.ps.prolog.force_linear_sample_interp =
2123 sel->info.uses_linear_center ||
2124 sel->info.uses_linear_centroid;
2125 } else if (rs->multisample_enable &&
2126 sctx->framebuffer.nr_samples > 1) {
2127 key->part.ps.prolog.bc_optimize_for_persp =
2128 sel->info.uses_persp_center &&
2129 sel->info.uses_persp_centroid;
2130 key->part.ps.prolog.bc_optimize_for_linear =
2131 sel->info.uses_linear_center &&
2132 sel->info.uses_linear_centroid;
2133 } else {
2134 /* Make sure SPI doesn't compute more than 1 pair
2135 * of (i,j), which is the optimization here. */
2136 key->part.ps.prolog.force_persp_center_interp =
2137 sel->info.uses_persp_center +
2138 sel->info.uses_persp_centroid +
2139 sel->info.uses_persp_sample > 1;
2140
2141 key->part.ps.prolog.force_linear_center_interp =
2142 sel->info.uses_linear_center +
2143 sel->info.uses_linear_centroid +
2144 sel->info.uses_linear_sample > 1;
2145
2146 if (sel->info.uses_persp_opcode_interp_sample ||
2147 sel->info.uses_linear_opcode_interp_sample)
2148 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2149 }
2150
2151 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2152
2153 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2154 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2155 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2156 struct pipe_resource *tex = cb0->texture;
2157
2158 /* 1D textures are allocated and used as 2D on GFX9. */
2159 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2160 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2161 (tex->target == PIPE_TEXTURE_1D ||
2162 tex->target == PIPE_TEXTURE_1D_ARRAY);
2163 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2164 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2165 tex->target == PIPE_TEXTURE_CUBE ||
2166 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2167 tex->target == PIPE_TEXTURE_3D;
2168 }
2169 break;
2170 }
2171 default:
2172 assert(0);
2173 }
2174
2175 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2176 memset(&key->opt, 0, sizeof(key->opt));
2177 }
2178
2179 static void si_build_shader_variant(struct si_shader *shader,
2180 int thread_index,
2181 bool low_priority)
2182 {
2183 struct si_shader_selector *sel = shader->selector;
2184 struct si_screen *sscreen = sel->screen;
2185 struct ac_llvm_compiler *compiler;
2186 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2187
2188 if (thread_index >= 0) {
2189 if (low_priority) {
2190 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2191 compiler = &sscreen->compiler_lowp[thread_index];
2192 } else {
2193 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2194 compiler = &sscreen->compiler[thread_index];
2195 }
2196 if (!debug->async)
2197 debug = NULL;
2198 } else {
2199 assert(!low_priority);
2200 compiler = shader->compiler_ctx_state.compiler;
2201 }
2202
2203 if (!compiler->passes)
2204 si_init_compiler(sscreen, compiler);
2205
2206 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2207 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2208 sel->type);
2209 shader->compilation_failed = true;
2210 return;
2211 }
2212
2213 if (shader->compiler_ctx_state.is_debug_context) {
2214 FILE *f = open_memstream(&shader->shader_log,
2215 &shader->shader_log_size);
2216 if (f) {
2217 si_shader_dump(sscreen, shader, NULL, f, false);
2218 fclose(f);
2219 }
2220 }
2221
2222 si_shader_init_pm4_state(sscreen, shader);
2223 }
2224
2225 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2226 {
2227 struct si_shader *shader = (struct si_shader *)job;
2228
2229 assert(thread_index >= 0);
2230
2231 si_build_shader_variant(shader, thread_index, true);
2232 }
2233
2234 static const struct si_shader_key zeroed;
2235
2236 static bool si_check_missing_main_part(struct si_screen *sscreen,
2237 struct si_shader_selector *sel,
2238 struct si_compiler_ctx_state *compiler_state,
2239 struct si_shader_key *key)
2240 {
2241 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2242
2243 if (!*mainp) {
2244 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2245
2246 if (!main_part)
2247 return false;
2248
2249 /* We can leave the fence as permanently signaled because the
2250 * main part becomes visible globally only after it has been
2251 * compiled. */
2252 util_queue_fence_init(&main_part->ready);
2253
2254 main_part->selector = sel;
2255 main_part->key.as_es = key->as_es;
2256 main_part->key.as_ls = key->as_ls;
2257 main_part->key.as_ngg = key->as_ngg;
2258 main_part->is_monolithic = false;
2259
2260 if (!si_compile_shader(sscreen, compiler_state->compiler,
2261 main_part, &compiler_state->debug)) {
2262 FREE(main_part);
2263 return false;
2264 }
2265 *mainp = main_part;
2266 }
2267 return true;
2268 }
2269
2270 /**
2271 * Select a shader variant according to the shader key.
2272 *
2273 * \param optimized_or_none If the key describes an optimized shader variant and
2274 * the compilation isn't finished, don't select any
2275 * shader and return an error.
2276 */
2277 int si_shader_select_with_key(struct si_screen *sscreen,
2278 struct si_shader_ctx_state *state,
2279 struct si_compiler_ctx_state *compiler_state,
2280 struct si_shader_key *key,
2281 int thread_index,
2282 bool optimized_or_none)
2283 {
2284 struct si_shader_selector *sel = state->cso;
2285 struct si_shader_selector *previous_stage_sel = NULL;
2286 struct si_shader *current = state->current;
2287 struct si_shader *iter, *shader = NULL;
2288
2289 again:
2290 /* Check if we don't need to change anything.
2291 * This path is also used for most shaders that don't need multiple
2292 * variants, it will cost just a computation of the key and this
2293 * test. */
2294 if (likely(current &&
2295 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2296 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2297 if (current->is_optimized) {
2298 if (optimized_or_none)
2299 return -1;
2300
2301 memset(&key->opt, 0, sizeof(key->opt));
2302 goto current_not_ready;
2303 }
2304
2305 util_queue_fence_wait(&current->ready);
2306 }
2307
2308 return current->compilation_failed ? -1 : 0;
2309 }
2310 current_not_ready:
2311
2312 /* This must be done before the mutex is locked, because async GS
2313 * compilation calls this function too, and therefore must enter
2314 * the mutex first.
2315 *
2316 * Only wait if we are in a draw call. Don't wait if we are
2317 * in a compiler thread.
2318 */
2319 if (thread_index < 0)
2320 util_queue_fence_wait(&sel->ready);
2321
2322 simple_mtx_lock(&sel->mutex);
2323
2324 /* Find the shader variant. */
2325 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2326 /* Don't check the "current" shader. We checked it above. */
2327 if (current != iter &&
2328 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2329 simple_mtx_unlock(&sel->mutex);
2330
2331 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2332 /* If it's an optimized shader and its compilation has
2333 * been started but isn't done, use the unoptimized
2334 * shader so as not to cause a stall due to compilation.
2335 */
2336 if (iter->is_optimized) {
2337 if (optimized_or_none)
2338 return -1;
2339 memset(&key->opt, 0, sizeof(key->opt));
2340 goto again;
2341 }
2342
2343 util_queue_fence_wait(&iter->ready);
2344 }
2345
2346 if (iter->compilation_failed) {
2347 return -1; /* skip the draw call */
2348 }
2349
2350 state->current = iter;
2351 return 0;
2352 }
2353 }
2354
2355 /* Build a new shader. */
2356 shader = CALLOC_STRUCT(si_shader);
2357 if (!shader) {
2358 simple_mtx_unlock(&sel->mutex);
2359 return -ENOMEM;
2360 }
2361
2362 util_queue_fence_init(&shader->ready);
2363
2364 shader->selector = sel;
2365 shader->key = *key;
2366 shader->compiler_ctx_state = *compiler_state;
2367
2368 /* If this is a merged shader, get the first shader's selector. */
2369 if (sscreen->info.chip_class >= GFX9) {
2370 if (sel->type == PIPE_SHADER_TESS_CTRL)
2371 previous_stage_sel = key->part.tcs.ls;
2372 else if (sel->type == PIPE_SHADER_GEOMETRY)
2373 previous_stage_sel = key->part.gs.es;
2374
2375 /* We need to wait for the previous shader. */
2376 if (previous_stage_sel && thread_index < 0)
2377 util_queue_fence_wait(&previous_stage_sel->ready);
2378 }
2379
2380 bool is_pure_monolithic =
2381 sscreen->use_monolithic_shaders ||
2382 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2383
2384 /* Compile the main shader part if it doesn't exist. This can happen
2385 * if the initial guess was wrong.
2386 *
2387 * The prim discard CS doesn't need the main shader part.
2388 */
2389 if (!is_pure_monolithic &&
2390 !key->opt.vs_as_prim_discard_cs) {
2391 bool ok = true;
2392
2393 /* Make sure the main shader part is present. This is needed
2394 * for shaders that can be compiled as VS, LS, or ES, and only
2395 * one of them is compiled at creation.
2396 *
2397 * It is also needed for GS, which can be compiled as non-NGG
2398 * and NGG.
2399 *
2400 * For merged shaders, check that the starting shader's main
2401 * part is present.
2402 */
2403 if (previous_stage_sel) {
2404 struct si_shader_key shader1_key = zeroed;
2405
2406 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2407 shader1_key.as_ls = 1;
2408 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2409 shader1_key.as_es = 1;
2410 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2411 } else {
2412 assert(0);
2413 }
2414
2415 simple_mtx_lock(&previous_stage_sel->mutex);
2416 ok = si_check_missing_main_part(sscreen,
2417 previous_stage_sel,
2418 compiler_state, &shader1_key);
2419 simple_mtx_unlock(&previous_stage_sel->mutex);
2420 }
2421
2422 if (ok) {
2423 ok = si_check_missing_main_part(sscreen, sel,
2424 compiler_state, key);
2425 }
2426
2427 if (!ok) {
2428 FREE(shader);
2429 simple_mtx_unlock(&sel->mutex);
2430 return -ENOMEM; /* skip the draw call */
2431 }
2432 }
2433
2434 /* Keep the reference to the 1st shader of merged shaders, so that
2435 * Gallium can't destroy it before we destroy the 2nd shader.
2436 *
2437 * Set sctx = NULL, because it's unused if we're not releasing
2438 * the shader, and we don't have any sctx here.
2439 */
2440 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2441 previous_stage_sel);
2442
2443 /* Monolithic-only shaders don't make a distinction between optimized
2444 * and unoptimized. */
2445 shader->is_monolithic =
2446 is_pure_monolithic ||
2447 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2448
2449 /* The prim discard CS is always optimized. */
2450 shader->is_optimized =
2451 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2452 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2453
2454 /* If it's an optimized shader, compile it asynchronously. */
2455 if (shader->is_optimized && thread_index < 0) {
2456 /* Compile it asynchronously. */
2457 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2458 shader, &shader->ready,
2459 si_build_shader_variant_low_priority, NULL,
2460 0);
2461
2462 /* Add only after the ready fence was reset, to guard against a
2463 * race with si_bind_XX_shader. */
2464 if (!sel->last_variant) {
2465 sel->first_variant = shader;
2466 sel->last_variant = shader;
2467 } else {
2468 sel->last_variant->next_variant = shader;
2469 sel->last_variant = shader;
2470 }
2471
2472 /* Use the default (unoptimized) shader for now. */
2473 memset(&key->opt, 0, sizeof(key->opt));
2474 simple_mtx_unlock(&sel->mutex);
2475
2476 if (sscreen->options.sync_compile)
2477 util_queue_fence_wait(&shader->ready);
2478
2479 if (optimized_or_none)
2480 return -1;
2481 goto again;
2482 }
2483
2484 /* Reset the fence before adding to the variant list. */
2485 util_queue_fence_reset(&shader->ready);
2486
2487 if (!sel->last_variant) {
2488 sel->first_variant = shader;
2489 sel->last_variant = shader;
2490 } else {
2491 sel->last_variant->next_variant = shader;
2492 sel->last_variant = shader;
2493 }
2494
2495 simple_mtx_unlock(&sel->mutex);
2496
2497 assert(!shader->is_optimized);
2498 si_build_shader_variant(shader, thread_index, false);
2499
2500 util_queue_fence_signal(&shader->ready);
2501
2502 if (!shader->compilation_failed)
2503 state->current = shader;
2504
2505 return shader->compilation_failed ? -1 : 0;
2506 }
2507
2508 static int si_shader_select(struct pipe_context *ctx,
2509 struct si_shader_ctx_state *state,
2510 union si_vgt_stages_key stages_key,
2511 struct si_compiler_ctx_state *compiler_state)
2512 {
2513 struct si_context *sctx = (struct si_context *)ctx;
2514 struct si_shader_key key;
2515
2516 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2517 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2518 &key, -1, false);
2519 }
2520
2521 static void si_parse_next_shader_property(const struct si_shader_info *info,
2522 bool streamout,
2523 struct si_shader_key *key)
2524 {
2525 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2526
2527 switch (info->processor) {
2528 case PIPE_SHADER_VERTEX:
2529 switch (next_shader) {
2530 case PIPE_SHADER_GEOMETRY:
2531 key->as_es = 1;
2532 break;
2533 case PIPE_SHADER_TESS_CTRL:
2534 case PIPE_SHADER_TESS_EVAL:
2535 key->as_ls = 1;
2536 break;
2537 default:
2538 /* If POSITION isn't written, it can only be a HW VS
2539 * if streamout is used. If streamout isn't used,
2540 * assume that it's a HW LS. (the next shader is TCS)
2541 * This heuristic is needed for separate shader objects.
2542 */
2543 if (!info->writes_position && !streamout)
2544 key->as_ls = 1;
2545 }
2546 break;
2547
2548 case PIPE_SHADER_TESS_EVAL:
2549 if (next_shader == PIPE_SHADER_GEOMETRY ||
2550 !info->writes_position)
2551 key->as_es = 1;
2552 break;
2553 }
2554 }
2555
2556 /**
2557 * Compile the main shader part or the monolithic shader as part of
2558 * si_shader_selector initialization. Since it can be done asynchronously,
2559 * there is no way to report compile failures to applications.
2560 */
2561 static void si_init_shader_selector_async(void *job, int thread_index)
2562 {
2563 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2564 struct si_screen *sscreen = sel->screen;
2565 struct ac_llvm_compiler *compiler;
2566 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2567
2568 assert(!debug->debug_message || debug->async);
2569 assert(thread_index >= 0);
2570 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2571 compiler = &sscreen->compiler[thread_index];
2572
2573 if (!compiler->passes)
2574 si_init_compiler(sscreen, compiler);
2575
2576 /* Serialize NIR to save memory. Monolithic shader variants
2577 * have to deserialize NIR before compilation.
2578 */
2579 if (sel->nir) {
2580 struct blob blob;
2581 size_t size;
2582
2583 blob_init(&blob);
2584 /* true = remove optional debugging data to increase
2585 * the likehood of getting more shader cache hits.
2586 * It also drops variable names, so we'll save more memory.
2587 */
2588 nir_serialize(&blob, sel->nir, true);
2589 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2590 sel->nir_size = size;
2591 }
2592
2593 /* Compile the main shader part for use with a prolog and/or epilog.
2594 * If this fails, the driver will try to compile a monolithic shader
2595 * on demand.
2596 */
2597 if (!sscreen->use_monolithic_shaders) {
2598 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2599 unsigned char ir_sha1_cache_key[20];
2600
2601 if (!shader) {
2602 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2603 return;
2604 }
2605
2606 /* We can leave the fence signaled because use of the default
2607 * main part is guarded by the selector's ready fence. */
2608 util_queue_fence_init(&shader->ready);
2609
2610 shader->selector = sel;
2611 shader->is_monolithic = false;
2612 si_parse_next_shader_property(&sel->info,
2613 sel->so.num_outputs != 0,
2614 &shader->key);
2615
2616 if (sscreen->use_ngg &&
2617 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2618 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2619 sel->type == PIPE_SHADER_TESS_EVAL ||
2620 sel->type == PIPE_SHADER_GEOMETRY))
2621 shader->key.as_ngg = 1;
2622
2623 if (sel->nir) {
2624 si_get_ir_cache_key(sel, shader->key.as_ngg,
2625 shader->key.as_es, ir_sha1_cache_key);
2626 }
2627
2628 /* Try to load the shader from the shader cache. */
2629 simple_mtx_lock(&sscreen->shader_cache_mutex);
2630
2631 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2632 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2633 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2634 } else {
2635 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2636
2637 /* Compile the shader if it hasn't been loaded from the cache. */
2638 if (!si_compile_shader(sscreen, compiler, shader, debug)) {
2639 FREE(shader);
2640 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2641 return;
2642 }
2643
2644 simple_mtx_lock(&sscreen->shader_cache_mutex);
2645 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
2646 shader, true);
2647 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2648 }
2649
2650 *si_get_main_shader_part(sel, &shader->key) = shader;
2651
2652 /* Unset "outputs_written" flags for outputs converted to
2653 * DEFAULT_VAL, so that later inter-shader optimizations don't
2654 * try to eliminate outputs that don't exist in the final
2655 * shader.
2656 *
2657 * This is only done if non-monolithic shaders are enabled.
2658 */
2659 if ((sel->type == PIPE_SHADER_VERTEX ||
2660 sel->type == PIPE_SHADER_TESS_EVAL) &&
2661 !shader->key.as_ls &&
2662 !shader->key.as_es) {
2663 unsigned i;
2664
2665 for (i = 0; i < sel->info.num_outputs; i++) {
2666 unsigned offset = shader->info.vs_output_param_offset[i];
2667
2668 if (offset <= AC_EXP_PARAM_OFFSET_31)
2669 continue;
2670
2671 unsigned name = sel->info.output_semantic_name[i];
2672 unsigned index = sel->info.output_semantic_index[i];
2673 unsigned id;
2674
2675 switch (name) {
2676 case TGSI_SEMANTIC_GENERIC:
2677 /* don't process indices the function can't handle */
2678 if (index >= SI_MAX_IO_GENERIC)
2679 break;
2680 /* fall through */
2681 default:
2682 id = si_shader_io_get_unique_index(name, index, true);
2683 sel->outputs_written_before_ps &= ~(1ull << id);
2684 break;
2685 case TGSI_SEMANTIC_POSITION: /* ignore these */
2686 case TGSI_SEMANTIC_PSIZE:
2687 case TGSI_SEMANTIC_CLIPVERTEX:
2688 case TGSI_SEMANTIC_EDGEFLAG:
2689 break;
2690 }
2691 }
2692 }
2693 }
2694
2695 /* The GS copy shader is always pre-compiled. */
2696 if (sel->type == PIPE_SHADER_GEOMETRY &&
2697 (!sscreen->use_ngg ||
2698 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2699 sel->tess_turns_off_ngg)) {
2700 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2701 if (!sel->gs_copy_shader) {
2702 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2703 return;
2704 }
2705
2706 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2707 }
2708
2709 /* Free NIR. We only keep serialized NIR after this point. */
2710 if (sel->nir) {
2711 ralloc_free(sel->nir);
2712 sel->nir = NULL;
2713 }
2714 }
2715
2716 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2717 struct util_queue_fence *ready_fence,
2718 struct si_compiler_ctx_state *compiler_ctx_state,
2719 void *job, util_queue_execute_func execute)
2720 {
2721 util_queue_fence_init(ready_fence);
2722
2723 struct util_async_debug_callback async_debug;
2724 bool debug =
2725 (sctx->debug.debug_message && !sctx->debug.async) ||
2726 sctx->is_debug ||
2727 si_can_dump_shader(sctx->screen, processor);
2728
2729 if (debug) {
2730 u_async_debug_init(&async_debug);
2731 compiler_ctx_state->debug = async_debug.base;
2732 }
2733
2734 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2735 ready_fence, execute, NULL, 0);
2736
2737 if (debug) {
2738 util_queue_fence_wait(ready_fence);
2739 u_async_debug_drain(&async_debug, &sctx->debug);
2740 u_async_debug_cleanup(&async_debug);
2741 }
2742
2743 if (sctx->screen->options.sync_compile)
2744 util_queue_fence_wait(ready_fence);
2745 }
2746
2747 /* Return descriptor slot usage masks from the given shader info. */
2748 void si_get_active_slot_masks(const struct si_shader_info *info,
2749 uint32_t *const_and_shader_buffers,
2750 uint64_t *samplers_and_images)
2751 {
2752 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2753
2754 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2755 num_constbufs = util_last_bit(info->const_buffers_declared);
2756 /* two 8-byte images share one 16-byte slot */
2757 num_images = align(util_last_bit(info->images_declared), 2);
2758 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2759 num_samplers = util_last_bit(info->samplers_declared);
2760
2761 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2762 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2763 *const_and_shader_buffers =
2764 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2765
2766 /* The layout is:
2767 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2768 * - image[last] ... image[0] go to [31-last .. 31]
2769 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2770 *
2771 * FMASKs for images are placed separately, because MSAA images are rare,
2772 * and so we can benefit from a better cache hit rate if we keep image
2773 * descriptors together.
2774 */
2775 if (num_msaa_images)
2776 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2777
2778 start = si_get_image_slot(num_images - 1) / 2;
2779 *samplers_and_images =
2780 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2781 }
2782
2783 static void *si_create_shader_selector(struct pipe_context *ctx,
2784 const struct pipe_shader_state *state)
2785 {
2786 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2787 struct si_context *sctx = (struct si_context*)ctx;
2788 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2789 int i;
2790
2791 if (!sel)
2792 return NULL;
2793
2794 sel->screen = sscreen;
2795 sel->compiler_ctx_state.debug = sctx->debug;
2796 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2797
2798 sel->so = state->stream_output;
2799
2800 if (state->type == PIPE_SHADER_IR_TGSI) {
2801 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2802 } else {
2803 assert(state->type == PIPE_SHADER_IR_NIR);
2804 sel->nir = state->ir.nir;
2805 }
2806
2807 si_nir_scan_shader(sel->nir, &sel->info);
2808 si_nir_adjust_driver_locations(sel->nir);
2809
2810 sel->type = sel->info.processor;
2811 p_atomic_inc(&sscreen->num_shaders_created);
2812 si_get_active_slot_masks(&sel->info,
2813 &sel->active_const_and_shader_buffers,
2814 &sel->active_samplers_and_images);
2815
2816 /* Record which streamout buffers are enabled. */
2817 for (i = 0; i < sel->so.num_outputs; i++) {
2818 sel->enabled_streamout_buffer_mask |=
2819 (1 << sel->so.output[i].output_buffer) <<
2820 (sel->so.output[i].stream * 4);
2821 }
2822
2823 sel->num_vs_inputs = sel->type == PIPE_SHADER_VERTEX &&
2824 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] ?
2825 sel->info.num_inputs : 0;
2826 sel->num_vbos_in_user_sgprs =
2827 MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2828
2829 /* The prolog is a no-op if there are no inputs. */
2830 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2831 sel->info.num_inputs &&
2832 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2833
2834 sel->prim_discard_cs_allowed =
2835 sel->type == PIPE_SHADER_VERTEX &&
2836 !sel->info.uses_bindless_images &&
2837 !sel->info.uses_bindless_samplers &&
2838 !sel->info.writes_memory &&
2839 !sel->info.writes_viewport_index &&
2840 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2841 !sel->so.num_outputs;
2842
2843 switch (sel->type) {
2844 case PIPE_SHADER_GEOMETRY:
2845 sel->gs_output_prim =
2846 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2847
2848 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2849 sel->rast_prim = sel->gs_output_prim;
2850 if (util_rast_prim_is_triangles(sel->rast_prim))
2851 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2852
2853 sel->gs_max_out_vertices =
2854 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2855 sel->gs_num_invocations =
2856 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2857 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2858 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2859 sel->gs_max_out_vertices;
2860
2861 sel->max_gs_stream = 0;
2862 for (i = 0; i < sel->so.num_outputs; i++)
2863 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2864 sel->so.output[i].stream);
2865
2866 sel->gs_input_verts_per_prim =
2867 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2868
2869 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2870 sel->tess_turns_off_ngg =
2871 sscreen->info.chip_class == GFX10 &&
2872 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2873 break;
2874
2875 case PIPE_SHADER_TESS_CTRL:
2876 /* Always reserve space for these. */
2877 sel->patch_outputs_written |=
2878 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2879 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2880 /* fall through */
2881 case PIPE_SHADER_VERTEX:
2882 case PIPE_SHADER_TESS_EVAL:
2883 for (i = 0; i < sel->info.num_outputs; i++) {
2884 unsigned name = sel->info.output_semantic_name[i];
2885 unsigned index = sel->info.output_semantic_index[i];
2886
2887 switch (name) {
2888 case TGSI_SEMANTIC_TESSINNER:
2889 case TGSI_SEMANTIC_TESSOUTER:
2890 case TGSI_SEMANTIC_PATCH:
2891 sel->patch_outputs_written |=
2892 1ull << si_shader_io_get_unique_index_patch(name, index);
2893 break;
2894
2895 case TGSI_SEMANTIC_GENERIC:
2896 /* don't process indices the function can't handle */
2897 if (index >= SI_MAX_IO_GENERIC)
2898 break;
2899 /* fall through */
2900 default:
2901 sel->outputs_written |=
2902 1ull << si_shader_io_get_unique_index(name, index, false);
2903 sel->outputs_written_before_ps |=
2904 1ull << si_shader_io_get_unique_index(name, index, true);
2905 break;
2906 case TGSI_SEMANTIC_EDGEFLAG:
2907 break;
2908 }
2909 }
2910 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2911 sel->lshs_vertex_stride = sel->esgs_itemsize;
2912
2913 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2914 * will start on a different bank. (except for the maximum 32*16).
2915 */
2916 if (sel->lshs_vertex_stride < 32*16)
2917 sel->lshs_vertex_stride += 4;
2918
2919 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2920 * conflicts, i.e. each vertex will start at a different bank.
2921 */
2922 if (sctx->chip_class >= GFX9)
2923 sel->esgs_itemsize += 4;
2924
2925 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2926
2927 /* Only for TES: */
2928 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2929 sel->rast_prim = PIPE_PRIM_POINTS;
2930 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2931 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2932 else
2933 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2934 break;
2935
2936 case PIPE_SHADER_FRAGMENT:
2937 for (i = 0; i < sel->info.num_inputs; i++) {
2938 unsigned name = sel->info.input_semantic_name[i];
2939 unsigned index = sel->info.input_semantic_index[i];
2940
2941 switch (name) {
2942 case TGSI_SEMANTIC_GENERIC:
2943 /* don't process indices the function can't handle */
2944 if (index >= SI_MAX_IO_GENERIC)
2945 break;
2946 /* fall through */
2947 default:
2948 sel->inputs_read |=
2949 1ull << si_shader_io_get_unique_index(name, index, true);
2950 break;
2951 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2952 break;
2953 }
2954 }
2955
2956 for (i = 0; i < 8; i++)
2957 if (sel->info.colors_written & (1 << i))
2958 sel->colors_written_4bit |= 0xf << (4 * i);
2959
2960 for (i = 0; i < sel->info.num_inputs; i++) {
2961 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2962 int index = sel->info.input_semantic_index[i];
2963 sel->color_attr_index[index] = i;
2964 }
2965 }
2966 break;
2967 default:;
2968 }
2969
2970 sel->ngg_culling_allowed =
2971 sscreen->info.chip_class == GFX10 &&
2972 sscreen->info.has_dedicated_vram &&
2973 sscreen->use_ngg_culling &&
2974 /* Disallow TES by default, because TessMark results are mixed. */
2975 (sel->type == PIPE_SHADER_VERTEX ||
2976 (sscreen->always_use_ngg_culling && sel->type == PIPE_SHADER_TESS_EVAL)) &&
2977 sel->info.writes_position &&
2978 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
2979 !sel->info.writes_memory &&
2980 !sel->so.num_outputs &&
2981 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] &&
2982 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2983
2984 /* PA_CL_VS_OUT_CNTL */
2985 if (sctx->chip_class <= GFX9)
2986 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2987
2988 sel->clipdist_mask = sel->info.writes_clipvertex ?
2989 SIX_BITS : sel->info.clipdist_writemask;
2990 sel->culldist_mask = sel->info.culldist_writemask <<
2991 sel->info.num_written_clipdistance;
2992
2993 /* DB_SHADER_CONTROL */
2994 sel->db_shader_control =
2995 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2996 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2997 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2998 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2999
3000 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
3001 case TGSI_FS_DEPTH_LAYOUT_GREATER:
3002 sel->db_shader_control |=
3003 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
3004 break;
3005 case TGSI_FS_DEPTH_LAYOUT_LESS:
3006 sel->db_shader_control |=
3007 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3008 break;
3009 }
3010
3011 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
3012 *
3013 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
3014 * --|-----------|------------|------------|--------------------|-------------------|-------------
3015 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
3016 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
3017 * 2 | false | true | n/a | LateZ | 1 | 0
3018 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
3019 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
3020 *
3021 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
3022 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
3023 *
3024 * Don't use ReZ without profiling !!!
3025 *
3026 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
3027 * shaders.
3028 */
3029 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3030 /* Cases 3, 4. */
3031 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3032 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
3033 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
3034 } else if (sel->info.writes_memory) {
3035 /* Case 2. */
3036 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
3037 S_02880C_EXEC_ON_HIER_FAIL(1);
3038 } else {
3039 /* Case 1. */
3040 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3041 }
3042
3043 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
3044 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
3045
3046 (void) simple_mtx_init(&sel->mutex, mtx_plain);
3047
3048 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
3049 &sel->compiler_ctx_state, sel,
3050 si_init_shader_selector_async);
3051 return sel;
3052 }
3053
3054 static void *si_create_shader(struct pipe_context *ctx,
3055 const struct pipe_shader_state *state)
3056 {
3057 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
3058
3059 return util_live_shader_cache_get(ctx, &sscreen->live_shader_cache, state);
3060 }
3061
3062 static void si_update_streamout_state(struct si_context *sctx)
3063 {
3064 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
3065
3066 if (!shader_with_so)
3067 return;
3068
3069 sctx->streamout.enabled_stream_buffers_mask =
3070 shader_with_so->enabled_streamout_buffer_mask;
3071 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
3072 }
3073
3074 static void si_update_clip_regs(struct si_context *sctx,
3075 struct si_shader_selector *old_hw_vs,
3076 struct si_shader *old_hw_vs_variant,
3077 struct si_shader_selector *next_hw_vs,
3078 struct si_shader *next_hw_vs_variant)
3079 {
3080 if (next_hw_vs &&
3081 (!old_hw_vs ||
3082 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
3083 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
3084 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
3085 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
3086 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
3087 !old_hw_vs_variant ||
3088 !next_hw_vs_variant ||
3089 old_hw_vs_variant->key.opt.clip_disable !=
3090 next_hw_vs_variant->key.opt.clip_disable))
3091 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3092 }
3093
3094 static void si_update_common_shader_state(struct si_context *sctx)
3095 {
3096 sctx->uses_bindless_samplers =
3097 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
3098 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
3099 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
3100 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
3101 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
3102 sctx->uses_bindless_images =
3103 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
3104 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
3105 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
3106 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3107 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3108 sctx->do_update_shaders = true;
3109 }
3110
3111 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3112 {
3113 struct si_context *sctx = (struct si_context *)ctx;
3114 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3115 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3116 struct si_shader_selector *sel = state;
3117
3118 if (sctx->vs_shader.cso == sel)
3119 return;
3120
3121 sctx->vs_shader.cso = sel;
3122 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3123 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3124
3125 if (si_update_ngg(sctx))
3126 si_shader_change_notify(sctx);
3127
3128 si_update_common_shader_state(sctx);
3129 si_update_vs_viewport_state(sctx);
3130 si_set_active_descriptors_for_shader(sctx, sel);
3131 si_update_streamout_state(sctx);
3132 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3133 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3134 }
3135
3136 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3137 {
3138 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3139 (sctx->tes_shader.cso &&
3140 sctx->tes_shader.cso->info.uses_primid) ||
3141 (sctx->tcs_shader.cso &&
3142 sctx->tcs_shader.cso->info.uses_primid) ||
3143 (sctx->gs_shader.cso &&
3144 sctx->gs_shader.cso->info.uses_primid) ||
3145 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3146 sctx->ps_shader.cso->info.uses_primid);
3147 }
3148
3149 bool si_update_ngg(struct si_context *sctx)
3150 {
3151 if (!sctx->screen->use_ngg) {
3152 assert(!sctx->ngg);
3153 return false;
3154 }
3155
3156 bool new_ngg = true;
3157
3158 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3159 sctx->gs_shader.cso->tess_turns_off_ngg) {
3160 new_ngg = false;
3161 } else if (!sctx->screen->use_ngg_streamout) {
3162 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3163
3164 if ((last && last->so.num_outputs) ||
3165 sctx->streamout.prims_gen_query_enabled)
3166 new_ngg = false;
3167 }
3168
3169 if (new_ngg != sctx->ngg) {
3170 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3171 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3172 * pointers are set.
3173 */
3174 if ((sctx->family == CHIP_NAVI10 ||
3175 sctx->family == CHIP_NAVI12 ||
3176 sctx->family == CHIP_NAVI14) &&
3177 !new_ngg)
3178 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3179
3180 sctx->ngg = new_ngg;
3181 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3182 return true;
3183 }
3184 return false;
3185 }
3186
3187 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3188 {
3189 struct si_context *sctx = (struct si_context *)ctx;
3190 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3191 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3192 struct si_shader_selector *sel = state;
3193 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3194 bool ngg_changed;
3195
3196 if (sctx->gs_shader.cso == sel)
3197 return;
3198
3199 sctx->gs_shader.cso = sel;
3200 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3201 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3202
3203 si_update_common_shader_state(sctx);
3204 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3205
3206 ngg_changed = si_update_ngg(sctx);
3207 if (ngg_changed || enable_changed)
3208 si_shader_change_notify(sctx);
3209 if (enable_changed) {
3210 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3211 si_update_tess_uses_prim_id(sctx);
3212 }
3213 si_update_vs_viewport_state(sctx);
3214 si_set_active_descriptors_for_shader(sctx, sel);
3215 si_update_streamout_state(sctx);
3216 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3217 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3218 }
3219
3220 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3221 {
3222 struct si_context *sctx = (struct si_context *)ctx;
3223 struct si_shader_selector *sel = state;
3224 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3225
3226 if (sctx->tcs_shader.cso == sel)
3227 return;
3228
3229 sctx->tcs_shader.cso = sel;
3230 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3231 si_update_tess_uses_prim_id(sctx);
3232
3233 si_update_common_shader_state(sctx);
3234
3235 if (enable_changed)
3236 sctx->last_tcs = NULL; /* invalidate derived tess state */
3237
3238 si_set_active_descriptors_for_shader(sctx, sel);
3239 }
3240
3241 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3242 {
3243 struct si_context *sctx = (struct si_context *)ctx;
3244 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3245 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3246 struct si_shader_selector *sel = state;
3247 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3248
3249 if (sctx->tes_shader.cso == sel)
3250 return;
3251
3252 sctx->tes_shader.cso = sel;
3253 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3254 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3255 si_update_tess_uses_prim_id(sctx);
3256
3257 si_update_common_shader_state(sctx);
3258 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3259
3260 bool ngg_changed = si_update_ngg(sctx);
3261 if (ngg_changed || enable_changed)
3262 si_shader_change_notify(sctx);
3263 if (enable_changed)
3264 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3265 si_update_vs_viewport_state(sctx);
3266 si_set_active_descriptors_for_shader(sctx, sel);
3267 si_update_streamout_state(sctx);
3268 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3269 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3270 }
3271
3272 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3273 {
3274 struct si_context *sctx = (struct si_context *)ctx;
3275 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3276 struct si_shader_selector *sel = state;
3277
3278 /* skip if supplied shader is one already in use */
3279 if (old_sel == sel)
3280 return;
3281
3282 sctx->ps_shader.cso = sel;
3283 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3284
3285 si_update_common_shader_state(sctx);
3286 if (sel) {
3287 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3288 si_update_tess_uses_prim_id(sctx);
3289
3290 if (!old_sel ||
3291 old_sel->info.colors_written != sel->info.colors_written)
3292 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3293
3294 if (sctx->screen->has_out_of_order_rast &&
3295 (!old_sel ||
3296 old_sel->info.writes_memory != sel->info.writes_memory ||
3297 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3298 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3299 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3300 }
3301 si_set_active_descriptors_for_shader(sctx, sel);
3302 si_update_ps_colorbuf0_slot(sctx);
3303 }
3304
3305 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3306 {
3307 if (shader->is_optimized) {
3308 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3309 &shader->ready);
3310 }
3311
3312 util_queue_fence_destroy(&shader->ready);
3313
3314 if (shader->pm4) {
3315 /* If destroyed shaders were not unbound, the next compiled
3316 * shader variant could get the same pointer address and so
3317 * binding it to the same shader stage would be considered
3318 * a no-op, causing random behavior.
3319 */
3320 switch (shader->selector->type) {
3321 case PIPE_SHADER_VERTEX:
3322 if (shader->key.as_ls) {
3323 assert(sctx->chip_class <= GFX8);
3324 si_pm4_delete_state(sctx, ls, shader->pm4);
3325 } else if (shader->key.as_es) {
3326 assert(sctx->chip_class <= GFX8);
3327 si_pm4_delete_state(sctx, es, shader->pm4);
3328 } else if (shader->key.as_ngg) {
3329 si_pm4_delete_state(sctx, gs, shader->pm4);
3330 } else {
3331 si_pm4_delete_state(sctx, vs, shader->pm4);
3332 }
3333 break;
3334 case PIPE_SHADER_TESS_CTRL:
3335 si_pm4_delete_state(sctx, hs, shader->pm4);
3336 break;
3337 case PIPE_SHADER_TESS_EVAL:
3338 if (shader->key.as_es) {
3339 assert(sctx->chip_class <= GFX8);
3340 si_pm4_delete_state(sctx, es, shader->pm4);
3341 } else if (shader->key.as_ngg) {
3342 si_pm4_delete_state(sctx, gs, shader->pm4);
3343 } else {
3344 si_pm4_delete_state(sctx, vs, shader->pm4);
3345 }
3346 break;
3347 case PIPE_SHADER_GEOMETRY:
3348 if (shader->is_gs_copy_shader)
3349 si_pm4_delete_state(sctx, vs, shader->pm4);
3350 else
3351 si_pm4_delete_state(sctx, gs, shader->pm4);
3352 break;
3353 case PIPE_SHADER_FRAGMENT:
3354 si_pm4_delete_state(sctx, ps, shader->pm4);
3355 break;
3356 default:;
3357 }
3358 }
3359
3360 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3361 si_shader_destroy(shader);
3362 free(shader);
3363 }
3364
3365 static void si_destroy_shader_selector(struct pipe_context *ctx, void *cso)
3366 {
3367 struct si_context *sctx = (struct si_context*)ctx;
3368 struct si_shader_selector *sel = (struct si_shader_selector *)cso;
3369 struct si_shader *p = sel->first_variant, *c;
3370 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3371 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3372 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3373 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3374 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3375 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3376 };
3377
3378 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3379
3380 if (current_shader[sel->type]->cso == sel) {
3381 current_shader[sel->type]->cso = NULL;
3382 current_shader[sel->type]->current = NULL;
3383 }
3384
3385 while (p) {
3386 c = p->next_variant;
3387 si_delete_shader(sctx, p);
3388 p = c;
3389 }
3390
3391 if (sel->main_shader_part)
3392 si_delete_shader(sctx, sel->main_shader_part);
3393 if (sel->main_shader_part_ls)
3394 si_delete_shader(sctx, sel->main_shader_part_ls);
3395 if (sel->main_shader_part_es)
3396 si_delete_shader(sctx, sel->main_shader_part_es);
3397 if (sel->main_shader_part_ngg)
3398 si_delete_shader(sctx, sel->main_shader_part_ngg);
3399 if (sel->gs_copy_shader)
3400 si_delete_shader(sctx, sel->gs_copy_shader);
3401
3402 util_queue_fence_destroy(&sel->ready);
3403 simple_mtx_destroy(&sel->mutex);
3404 ralloc_free(sel->nir);
3405 free(sel->nir_binary);
3406 free(sel);
3407 }
3408
3409 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3410 {
3411 struct si_context *sctx = (struct si_context *)ctx;
3412 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3413
3414 si_shader_selector_reference(sctx, &sel, NULL);
3415 }
3416
3417 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3418 struct si_shader *vs, unsigned name,
3419 unsigned index, unsigned interpolate)
3420 {
3421 struct si_shader_info *vsinfo = &vs->selector->info;
3422 unsigned j, offset, ps_input_cntl = 0;
3423
3424 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3425 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3426 name == TGSI_SEMANTIC_PRIMID)
3427 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3428
3429 if (name == TGSI_SEMANTIC_PCOORD ||
3430 (name == TGSI_SEMANTIC_TEXCOORD &&
3431 sctx->sprite_coord_enable & (1 << index))) {
3432 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3433 }
3434
3435 for (j = 0; j < vsinfo->num_outputs; j++) {
3436 if (name == vsinfo->output_semantic_name[j] &&
3437 index == vsinfo->output_semantic_index[j]) {
3438 offset = vs->info.vs_output_param_offset[j];
3439
3440 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3441 /* The input is loaded from parameter memory. */
3442 ps_input_cntl |= S_028644_OFFSET(offset);
3443 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3444 if (offset == AC_EXP_PARAM_UNDEFINED) {
3445 /* This can happen with depth-only rendering. */
3446 offset = 0;
3447 } else {
3448 /* The input is a DEFAULT_VAL constant. */
3449 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3450 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3451 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3452 }
3453
3454 ps_input_cntl = S_028644_OFFSET(0x20) |
3455 S_028644_DEFAULT_VAL(offset);
3456 }
3457 break;
3458 }
3459 }
3460
3461 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3462 /* PrimID is written after the last output when HW VS is used. */
3463 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3464 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3465 /* No corresponding output found, load defaults into input.
3466 * Don't set any other bits.
3467 * (FLAT_SHADE=1 completely changes behavior) */
3468 ps_input_cntl = S_028644_OFFSET(0x20);
3469 /* D3D 9 behaviour. GL is undefined */
3470 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3471 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3472 }
3473 return ps_input_cntl;
3474 }
3475
3476 static void si_emit_spi_map(struct si_context *sctx)
3477 {
3478 struct si_shader *ps = sctx->ps_shader.current;
3479 struct si_shader *vs = si_get_vs_state(sctx);
3480 struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3481 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3482 unsigned spi_ps_input_cntl[32];
3483
3484 if (!ps || !ps->selector->info.num_inputs)
3485 return;
3486
3487 num_interp = si_get_ps_num_interp(ps);
3488 assert(num_interp > 0);
3489
3490 for (i = 0; i < psinfo->num_inputs; i++) {
3491 unsigned name = psinfo->input_semantic_name[i];
3492 unsigned index = psinfo->input_semantic_index[i];
3493 unsigned interpolate = psinfo->input_interpolate[i];
3494
3495 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3496 index, interpolate);
3497
3498 if (name == TGSI_SEMANTIC_COLOR) {
3499 assert(index < ARRAY_SIZE(bcol_interp));
3500 bcol_interp[index] = interpolate;
3501 }
3502 }
3503
3504 if (ps->key.part.ps.prolog.color_two_side) {
3505 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3506
3507 for (i = 0; i < 2; i++) {
3508 if (!(psinfo->colors_read & (0xf << (i * 4))))
3509 continue;
3510
3511 spi_ps_input_cntl[num_written++] =
3512 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3513
3514 }
3515 }
3516 assert(num_interp == num_written);
3517
3518 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3519 /* Dota 2: Only ~16% of SPI map updates set different values. */
3520 /* Talos: Only ~9% of SPI map updates set different values. */
3521 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3522 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3523 spi_ps_input_cntl,
3524 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3525
3526 if (initial_cdw != sctx->gfx_cs->current.cdw)
3527 sctx->context_roll = true;
3528 }
3529
3530 /**
3531 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3532 */
3533 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3534 {
3535 if (sctx->init_config_has_vgt_flush)
3536 return;
3537
3538 /* Done by Vulkan before VGT_FLUSH. */
3539 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3540 si_pm4_cmd_add(sctx->init_config,
3541 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3542 si_pm4_cmd_end(sctx->init_config, false);
3543
3544 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3545 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3546 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3547 si_pm4_cmd_end(sctx->init_config, false);
3548 sctx->init_config_has_vgt_flush = true;
3549 }
3550
3551 /* Initialize state related to ESGS / GSVS ring buffers */
3552 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3553 {
3554 struct si_shader_selector *es =
3555 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3556 struct si_shader_selector *gs = sctx->gs_shader.cso;
3557 struct si_pm4_state *pm4;
3558
3559 /* Chip constants. */
3560 unsigned num_se = sctx->screen->info.max_se;
3561 unsigned wave_size = 64;
3562 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3563 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3564 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3565 */
3566 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3567 unsigned alignment = 256 * num_se;
3568 /* The maximum size is 63.999 MB per SE. */
3569 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3570
3571 /* Calculate the minimum size. */
3572 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3573 wave_size, alignment);
3574
3575 /* These are recommended sizes, not minimum sizes. */
3576 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3577 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3578 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3579 gs->max_gsvs_emit_size;
3580
3581 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3582 esgs_ring_size = align(esgs_ring_size, alignment);
3583 gsvs_ring_size = align(gsvs_ring_size, alignment);
3584
3585 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3586 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3587
3588 /* Some rings don't have to be allocated if shaders don't use them.
3589 * (e.g. no varyings between ES and GS or GS and VS)
3590 *
3591 * GFX9 doesn't have the ESGS ring.
3592 */
3593 bool update_esgs = sctx->chip_class <= GFX8 &&
3594 esgs_ring_size &&
3595 (!sctx->esgs_ring ||
3596 sctx->esgs_ring->width0 < esgs_ring_size);
3597 bool update_gsvs = gsvs_ring_size &&
3598 (!sctx->gsvs_ring ||
3599 sctx->gsvs_ring->width0 < gsvs_ring_size);
3600
3601 if (!update_esgs && !update_gsvs)
3602 return true;
3603
3604 if (update_esgs) {
3605 pipe_resource_reference(&sctx->esgs_ring, NULL);
3606 sctx->esgs_ring =
3607 pipe_aligned_buffer_create(sctx->b.screen,
3608 SI_RESOURCE_FLAG_UNMAPPABLE,
3609 PIPE_USAGE_DEFAULT,
3610 esgs_ring_size,
3611 sctx->screen->info.pte_fragment_size);
3612 if (!sctx->esgs_ring)
3613 return false;
3614 }
3615
3616 if (update_gsvs) {
3617 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3618 sctx->gsvs_ring =
3619 pipe_aligned_buffer_create(sctx->b.screen,
3620 SI_RESOURCE_FLAG_UNMAPPABLE,
3621 PIPE_USAGE_DEFAULT,
3622 gsvs_ring_size,
3623 sctx->screen->info.pte_fragment_size);
3624 if (!sctx->gsvs_ring)
3625 return false;
3626 }
3627
3628 /* Create the "init_config_gs_rings" state. */
3629 pm4 = CALLOC_STRUCT(si_pm4_state);
3630 if (!pm4)
3631 return false;
3632
3633 if (sctx->chip_class >= GFX7) {
3634 if (sctx->esgs_ring) {
3635 assert(sctx->chip_class <= GFX8);
3636 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3637 sctx->esgs_ring->width0 / 256);
3638 }
3639 if (sctx->gsvs_ring)
3640 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3641 sctx->gsvs_ring->width0 / 256);
3642 } else {
3643 if (sctx->esgs_ring)
3644 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3645 sctx->esgs_ring->width0 / 256);
3646 if (sctx->gsvs_ring)
3647 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3648 sctx->gsvs_ring->width0 / 256);
3649 }
3650
3651 /* Set the state. */
3652 if (sctx->init_config_gs_rings)
3653 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3654 sctx->init_config_gs_rings = pm4;
3655
3656 if (!sctx->init_config_has_vgt_flush) {
3657 si_init_config_add_vgt_flush(sctx);
3658 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3659 }
3660
3661 /* Flush the context to re-emit both init_config states. */
3662 sctx->initial_gfx_cs_size = 0; /* force flush */
3663 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3664
3665 /* Set ring bindings. */
3666 if (sctx->esgs_ring) {
3667 assert(sctx->chip_class <= GFX8);
3668 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3669 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3670 true, true, 4, 64, 0);
3671 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3672 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3673 false, false, 0, 0, 0);
3674 }
3675 if (sctx->gsvs_ring) {
3676 si_set_ring_buffer(sctx, SI_RING_GSVS,
3677 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3678 false, false, 0, 0, 0);
3679 }
3680
3681 return true;
3682 }
3683
3684 static void si_shader_lock(struct si_shader *shader)
3685 {
3686 simple_mtx_lock(&shader->selector->mutex);
3687 if (shader->previous_stage_sel) {
3688 assert(shader->previous_stage_sel != shader->selector);
3689 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3690 }
3691 }
3692
3693 static void si_shader_unlock(struct si_shader *shader)
3694 {
3695 if (shader->previous_stage_sel)
3696 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3697 simple_mtx_unlock(&shader->selector->mutex);
3698 }
3699
3700 /**
3701 * @returns 1 if \p sel has been updated to use a new scratch buffer
3702 * 0 if not
3703 * < 0 if there was a failure
3704 */
3705 static int si_update_scratch_buffer(struct si_context *sctx,
3706 struct si_shader *shader)
3707 {
3708 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3709
3710 if (!shader)
3711 return 0;
3712
3713 /* This shader doesn't need a scratch buffer */
3714 if (shader->config.scratch_bytes_per_wave == 0)
3715 return 0;
3716
3717 /* Prevent race conditions when updating:
3718 * - si_shader::scratch_bo
3719 * - si_shader::binary::code
3720 * - si_shader::previous_stage::binary::code.
3721 */
3722 si_shader_lock(shader);
3723
3724 /* This shader is already configured to use the current
3725 * scratch buffer. */
3726 if (shader->scratch_bo == sctx->scratch_buffer) {
3727 si_shader_unlock(shader);
3728 return 0;
3729 }
3730
3731 assert(sctx->scratch_buffer);
3732
3733 /* Replace the shader bo with a new bo that has the relocs applied. */
3734 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3735 si_shader_unlock(shader);
3736 return -1;
3737 }
3738
3739 /* Update the shader state to use the new shader bo. */
3740 si_shader_init_pm4_state(sctx->screen, shader);
3741
3742 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3743
3744 si_shader_unlock(shader);
3745 return 1;
3746 }
3747
3748 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3749 {
3750 return shader ? shader->config.scratch_bytes_per_wave : 0;
3751 }
3752
3753 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3754 {
3755 if (!sctx->tes_shader.cso)
3756 return NULL; /* tessellation disabled */
3757
3758 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3759 sctx->fixed_func_tcs_shader.current;
3760 }
3761
3762 static bool si_update_scratch_relocs(struct si_context *sctx)
3763 {
3764 struct si_shader *tcs = si_get_tcs_current(sctx);
3765 int r;
3766
3767 /* Update the shaders, so that they are using the latest scratch.
3768 * The scratch buffer may have been changed since these shaders were
3769 * last used, so we still need to try to update them, even if they
3770 * require scratch buffers smaller than the current size.
3771 */
3772 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3773 if (r < 0)
3774 return false;
3775 if (r == 1)
3776 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3777
3778 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3779 if (r < 0)
3780 return false;
3781 if (r == 1)
3782 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3783
3784 r = si_update_scratch_buffer(sctx, tcs);
3785 if (r < 0)
3786 return false;
3787 if (r == 1)
3788 si_pm4_bind_state(sctx, hs, tcs->pm4);
3789
3790 /* VS can be bound as LS, ES, or VS. */
3791 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3792 if (r < 0)
3793 return false;
3794 if (r == 1) {
3795 if (sctx->vs_shader.current->key.as_ls)
3796 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3797 else if (sctx->vs_shader.current->key.as_es)
3798 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3799 else if (sctx->vs_shader.current->key.as_ngg)
3800 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3801 else
3802 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3803 }
3804
3805 /* TES can be bound as ES or VS. */
3806 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3807 if (r < 0)
3808 return false;
3809 if (r == 1) {
3810 if (sctx->tes_shader.current->key.as_es)
3811 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3812 else if (sctx->tes_shader.current->key.as_ngg)
3813 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3814 else
3815 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3816 }
3817
3818 return true;
3819 }
3820
3821 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3822 {
3823 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3824 * There are 2 cases to handle:
3825 *
3826 * - If the current needed size is less than the maximum seen size,
3827 * use the maximum seen size, so that WAVESIZE remains the same.
3828 *
3829 * - If the current needed size is greater than the maximum seen size,
3830 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3831 *
3832 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3833 * Otherwise, the number of waves that can use scratch is
3834 * SPI_TMPRING_SIZE.WAVES.
3835 */
3836 unsigned bytes = 0;
3837
3838 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3839 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3840 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3841
3842 if (sctx->tes_shader.cso) {
3843 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3844 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3845 }
3846
3847 sctx->max_seen_scratch_bytes_per_wave =
3848 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3849
3850 unsigned scratch_needed_size =
3851 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3852 unsigned spi_tmpring_size;
3853
3854 if (scratch_needed_size > 0) {
3855 if (!sctx->scratch_buffer ||
3856 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3857 /* Create a bigger scratch buffer */
3858 si_resource_reference(&sctx->scratch_buffer, NULL);
3859
3860 sctx->scratch_buffer =
3861 si_aligned_buffer_create(&sctx->screen->b,
3862 SI_RESOURCE_FLAG_UNMAPPABLE,
3863 PIPE_USAGE_DEFAULT,
3864 scratch_needed_size,
3865 sctx->screen->info.pte_fragment_size);
3866 if (!sctx->scratch_buffer)
3867 return false;
3868
3869 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3870 si_context_add_resource_size(sctx,
3871 &sctx->scratch_buffer->b.b);
3872 }
3873
3874 if (!si_update_scratch_relocs(sctx))
3875 return false;
3876 }
3877
3878 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3879 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3880 "scratch size should already be aligned correctly.");
3881
3882 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3883 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3884 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3885 sctx->spi_tmpring_size = spi_tmpring_size;
3886 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3887 }
3888 return true;
3889 }
3890
3891 static void si_init_tess_factor_ring(struct si_context *sctx)
3892 {
3893 assert(!sctx->tess_rings);
3894 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3895
3896 /* The address must be aligned to 2^19, because the shader only
3897 * receives the high 13 bits.
3898 */
3899 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3900 SI_RESOURCE_FLAG_32BIT,
3901 PIPE_USAGE_DEFAULT,
3902 sctx->screen->tess_offchip_ring_size +
3903 sctx->screen->tess_factor_ring_size,
3904 1 << 19);
3905 if (!sctx->tess_rings)
3906 return;
3907
3908 si_init_config_add_vgt_flush(sctx);
3909
3910 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3911 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3912
3913 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3914 sctx->screen->tess_offchip_ring_size;
3915
3916 /* Append these registers to the init config state. */
3917 if (sctx->chip_class >= GFX7) {
3918 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3919 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3920 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3921 factor_va >> 8);
3922 if (sctx->chip_class >= GFX10)
3923 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3924 S_030984_BASE_HI(factor_va >> 40));
3925 else if (sctx->chip_class == GFX9)
3926 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3927 S_030944_BASE_HI(factor_va >> 40));
3928 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3929 sctx->screen->vgt_hs_offchip_param);
3930 } else {
3931 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3932 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3933 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3934 factor_va >> 8);
3935 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3936 sctx->screen->vgt_hs_offchip_param);
3937 }
3938
3939 /* Flush the context to re-emit the init_config state.
3940 * This is done only once in a lifetime of a context.
3941 */
3942 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3943 sctx->initial_gfx_cs_size = 0; /* force flush */
3944 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3945 }
3946
3947 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3948 union si_vgt_stages_key key)
3949 {
3950 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3951 uint32_t stages = 0;
3952
3953 if (key.u.tess) {
3954 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3955 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3956
3957 if (key.u.gs)
3958 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3959 S_028B54_GS_EN(1);
3960 else if (key.u.ngg)
3961 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3962 else
3963 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3964 } else if (key.u.gs) {
3965 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3966 S_028B54_GS_EN(1);
3967 } else if (key.u.ngg) {
3968 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3969 }
3970
3971 if (key.u.ngg) {
3972 stages |= S_028B54_PRIMGEN_EN(1) |
3973 S_028B54_GS_FAST_LAUNCH(key.u.ngg_gs_fast_launch) |
3974 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3975 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3976 } else if (key.u.gs)
3977 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3978
3979 if (screen->info.chip_class >= GFX9)
3980 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3981
3982 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3983 stages |= S_028B54_HS_W32_EN(1) |
3984 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3985 S_028B54_VS_W32_EN(1);
3986 }
3987
3988 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3989 return pm4;
3990 }
3991
3992 static void si_update_vgt_shader_config(struct si_context *sctx,
3993 union si_vgt_stages_key key)
3994 {
3995 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3996
3997 if (unlikely(!*pm4))
3998 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3999 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
4000 }
4001
4002 bool si_update_shaders(struct si_context *sctx)
4003 {
4004 struct pipe_context *ctx = (struct pipe_context*)sctx;
4005 struct si_compiler_ctx_state compiler_state;
4006 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
4007 struct si_shader *old_vs = si_get_vs_state(sctx);
4008 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
4009 struct si_shader *old_ps = sctx->ps_shader.current;
4010 union si_vgt_stages_key key;
4011 unsigned old_spi_shader_col_format =
4012 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
4013 int r;
4014
4015 if (!sctx->compiler.passes)
4016 si_init_compiler(sctx->screen, &sctx->compiler);
4017
4018 compiler_state.compiler = &sctx->compiler;
4019 compiler_state.debug = sctx->debug;
4020 compiler_state.is_debug_context = sctx->is_debug;
4021
4022 key.index = 0;
4023
4024 if (sctx->tes_shader.cso)
4025 key.u.tess = 1;
4026 if (sctx->gs_shader.cso)
4027 key.u.gs = 1;
4028
4029 if (sctx->ngg) {
4030 key.u.ngg = 1;
4031 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
4032 }
4033
4034 /* Update TCS and TES. */
4035 if (sctx->tes_shader.cso) {
4036 if (!sctx->tess_rings) {
4037 si_init_tess_factor_ring(sctx);
4038 if (!sctx->tess_rings)
4039 return false;
4040 }
4041
4042 if (sctx->tcs_shader.cso) {
4043 r = si_shader_select(ctx, &sctx->tcs_shader, key,
4044 &compiler_state);
4045 if (r)
4046 return false;
4047 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
4048 } else {
4049 if (!sctx->fixed_func_tcs_shader.cso) {
4050 sctx->fixed_func_tcs_shader.cso =
4051 si_create_fixed_func_tcs(sctx);
4052 if (!sctx->fixed_func_tcs_shader.cso)
4053 return false;
4054 }
4055
4056 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
4057 key, &compiler_state);
4058 if (r)
4059 return false;
4060 si_pm4_bind_state(sctx, hs,
4061 sctx->fixed_func_tcs_shader.current->pm4);
4062 }
4063
4064 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
4065 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
4066 if (r)
4067 return false;
4068
4069 if (sctx->gs_shader.cso) {
4070 /* TES as ES */
4071 assert(sctx->chip_class <= GFX8);
4072 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
4073 } else if (key.u.ngg) {
4074 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
4075 } else {
4076 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
4077 }
4078 }
4079 } else {
4080 if (sctx->chip_class <= GFX8)
4081 si_pm4_bind_state(sctx, ls, NULL);
4082 si_pm4_bind_state(sctx, hs, NULL);
4083 }
4084
4085 /* Update GS. */
4086 if (sctx->gs_shader.cso) {
4087 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
4088 if (r)
4089 return false;
4090 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
4091 if (!key.u.ngg) {
4092 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
4093
4094 if (!si_update_gs_ring_buffers(sctx))
4095 return false;
4096 } else {
4097 si_pm4_bind_state(sctx, vs, NULL);
4098 }
4099 } else {
4100 if (!key.u.ngg) {
4101 si_pm4_bind_state(sctx, gs, NULL);
4102 if (sctx->chip_class <= GFX8)
4103 si_pm4_bind_state(sctx, es, NULL);
4104 }
4105 }
4106
4107 /* Update VS. */
4108 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
4109 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
4110 if (r)
4111 return false;
4112
4113 if (!key.u.tess && !key.u.gs) {
4114 if (key.u.ngg) {
4115 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
4116 si_pm4_bind_state(sctx, vs, NULL);
4117 } else {
4118 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4119 }
4120 } else if (sctx->tes_shader.cso) {
4121 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4122 } else {
4123 assert(sctx->gs_shader.cso);
4124 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4125 }
4126 }
4127
4128 /* This must be done after the shader variant is selected. */
4129 if (sctx->ngg) {
4130 struct si_shader *vs = si_get_vs(sctx)->current;
4131
4132 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(vs);
4133 key.u.ngg_gs_fast_launch = !!(vs->key.opt.ngg_culling &
4134 SI_NGG_CULL_GS_FAST_LAUNCH_ALL);
4135 }
4136
4137 si_update_vgt_shader_config(sctx, key);
4138
4139 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4140 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4141
4142 if (sctx->ps_shader.cso) {
4143 unsigned db_shader_control;
4144
4145 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4146 if (r)
4147 return false;
4148 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4149
4150 db_shader_control =
4151 sctx->ps_shader.cso->db_shader_control |
4152 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4153
4154 if (si_pm4_state_changed(sctx, ps) ||
4155 si_pm4_state_changed(sctx, vs) ||
4156 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4157 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4158 sctx->flatshade != rs->flatshade) {
4159 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4160 sctx->flatshade = rs->flatshade;
4161 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4162 }
4163
4164 if (sctx->screen->info.rbplus_allowed &&
4165 si_pm4_state_changed(sctx, ps) &&
4166 (!old_ps ||
4167 old_spi_shader_col_format !=
4168 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4169 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4170
4171 if (sctx->ps_db_shader_control != db_shader_control) {
4172 sctx->ps_db_shader_control = db_shader_control;
4173 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4174 if (sctx->screen->dpbb_allowed)
4175 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4176 }
4177
4178 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4179 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4180 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4181
4182 if (sctx->chip_class == GFX6)
4183 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4184
4185 if (sctx->framebuffer.nr_samples <= 1)
4186 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4187 }
4188 }
4189
4190 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4191 si_pm4_state_enabled_and_changed(sctx, hs) ||
4192 si_pm4_state_enabled_and_changed(sctx, es) ||
4193 si_pm4_state_enabled_and_changed(sctx, gs) ||
4194 si_pm4_state_enabled_and_changed(sctx, vs) ||
4195 si_pm4_state_enabled_and_changed(sctx, ps)) {
4196 if (!si_update_spi_tmpring_size(sctx))
4197 return false;
4198 }
4199
4200 if (sctx->chip_class >= GFX7) {
4201 if (si_pm4_state_enabled_and_changed(sctx, ls))
4202 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4203 else if (!sctx->queued.named.ls)
4204 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4205
4206 if (si_pm4_state_enabled_and_changed(sctx, hs))
4207 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4208 else if (!sctx->queued.named.hs)
4209 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4210
4211 if (si_pm4_state_enabled_and_changed(sctx, es))
4212 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4213 else if (!sctx->queued.named.es)
4214 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4215
4216 if (si_pm4_state_enabled_and_changed(sctx, gs))
4217 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4218 else if (!sctx->queued.named.gs)
4219 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4220
4221 if (si_pm4_state_enabled_and_changed(sctx, vs))
4222 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4223 else if (!sctx->queued.named.vs)
4224 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4225
4226 if (si_pm4_state_enabled_and_changed(sctx, ps))
4227 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4228 else if (!sctx->queued.named.ps)
4229 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4230 }
4231
4232 sctx->do_update_shaders = false;
4233 return true;
4234 }
4235
4236 static void si_emit_scratch_state(struct si_context *sctx)
4237 {
4238 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4239
4240 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4241 sctx->spi_tmpring_size);
4242
4243 if (sctx->scratch_buffer) {
4244 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4245 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4246 RADEON_PRIO_SCRATCH_BUFFER);
4247 }
4248 }
4249
4250 void si_init_screen_live_shader_cache(struct si_screen *sscreen)
4251 {
4252 util_live_shader_cache_init(&sscreen->live_shader_cache,
4253 si_create_shader_selector,
4254 si_destroy_shader_selector);
4255 }
4256
4257 void si_init_shader_functions(struct si_context *sctx)
4258 {
4259 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4260 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4261
4262 sctx->b.create_vs_state = si_create_shader;
4263 sctx->b.create_tcs_state = si_create_shader;
4264 sctx->b.create_tes_state = si_create_shader;
4265 sctx->b.create_gs_state = si_create_shader;
4266 sctx->b.create_fs_state = si_create_shader;
4267
4268 sctx->b.bind_vs_state = si_bind_vs_shader;
4269 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4270 sctx->b.bind_tes_state = si_bind_tes_shader;
4271 sctx->b.bind_gs_state = si_bind_gs_shader;
4272 sctx->b.bind_fs_state = si_bind_ps_shader;
4273
4274 sctx->b.delete_vs_state = si_delete_shader_selector;
4275 sctx->b.delete_tcs_state = si_delete_shader_selector;
4276 sctx->b.delete_tes_state = si_delete_shader_selector;
4277 sctx->b.delete_gs_state = si_delete_shader_selector;
4278 sctx->b.delete_fs_state = si_delete_shader_selector;
4279 }