projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radeonsi/gfx10: fix the legacy pipeline by storing as_ngg in the shader cache
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 void *si_get_ir_binary(struct si_shader_selector *sel, bool as_ngg)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 unsigned size = 4 + 4 + ir_size + sizeof(sel->so);
68 char *result = (char*)MALLOC(size);
69 if (!result)
70 return NULL;
71
72 ((uint32_t*)result)[0] = size;
73 ((uint32_t*)result)[1] = as_ngg;
74 memcpy(result + 8, ir_binary, ir_size);
75 memcpy(result + 8 + ir_size, &sel->so, sizeof(sel->so));
76
77 if (sel->nir)
78 blob_finish(&blob);
79
80 return result;
81 }
82
83 /** Copy "data" to "ptr" and return the next dword following copied data. */
84 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
85 {
86 /* data may be NULL if size == 0 */
87 if (size)
88 memcpy(ptr, data, size);
89 ptr += DIV_ROUND_UP(size, 4);
90 return ptr;
91 }
92
93 /** Read data from "ptr". Return the next dword following the data. */
94 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
95 {
96 memcpy(data, ptr, size);
97 ptr += DIV_ROUND_UP(size, 4);
98 return ptr;
99 }
100
101 /**
102 * Write the size as uint followed by the data. Return the next dword
103 * following the copied data.
104 */
105 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
106 {
107 *ptr++ = size;
108 return write_data(ptr, data, size);
109 }
110
111 /**
112 * Read the size as uint followed by the data. Return both via parameters.
113 * Return the next dword following the data.
114 */
115 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
116 {
117 *size = *ptr++;
118 assert(*data == NULL);
119 if (!*size)
120 return ptr;
121 *data = malloc(*size);
122 return read_data(ptr, *data, *size);
123 }
124
125 /**
126 * Return the shader binary in a buffer. The first 4 bytes contain its size
127 * as integer.
128 */
129 static void *si_get_shader_binary(struct si_shader *shader)
130 {
131 /* There is always a size of data followed by the data itself. */
132 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
133 strlen(shader->binary.llvm_ir_string) + 1 : 0;
134
135 /* Refuse to allocate overly large buffers and guard against integer
136 * overflow. */
137 if (shader->binary.elf_size > UINT_MAX / 4 ||
138 llvm_ir_size > UINT_MAX / 4)
139 return NULL;
140
141 unsigned size =
142 4 + /* total size */
143 4 + /* CRC32 of the data below */
144 align(sizeof(shader->config), 4) +
145 align(sizeof(shader->info), 4) +
146 4 + align(shader->binary.elf_size, 4) +
147 4 + align(llvm_ir_size, 4);
148 void *buffer = CALLOC(1, size);
149 uint32_t *ptr = (uint32_t*)buffer;
150
151 if (!buffer)
152 return NULL;
153
154 *ptr++ = size;
155 ptr++; /* CRC32 is calculated at the end. */
156
157 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
158 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
159 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
160 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
161 assert((char *)ptr - (char *)buffer == size);
162
163 /* Compute CRC32. */
164 ptr = (uint32_t*)buffer;
165 ptr++;
166 *ptr = util_hash_crc32(ptr + 1, size - 8);
167
168 return buffer;
169 }
170
171 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
172 {
173 uint32_t *ptr = (uint32_t*)binary;
174 uint32_t size = *ptr++;
175 uint32_t crc32 = *ptr++;
176 unsigned chunk_size;
177 unsigned elf_size;
178
179 if (util_hash_crc32(ptr, size - 8) != crc32) {
180 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
181 return false;
182 }
183
184 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
185 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
186 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
187 &elf_size);
188 shader->binary.elf_size = elf_size;
189 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
190
191 return true;
192 }
193
194 /**
195 * Insert a shader into the cache. It's assumed the shader is not in the cache.
196 * Use si_shader_cache_load_shader before calling this.
197 *
198 * Returns false on failure, in which case the ir_binary should be freed.
199 */
200 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
201 struct si_shader *shader,
202 bool insert_into_disk_cache)
203 {
204 void *hw_binary;
205 struct hash_entry *entry;
206 uint8_t key[CACHE_KEY_SIZE];
207
208 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
209 if (entry)
210 return false; /* already added */
211
212 hw_binary = si_get_shader_binary(shader);
213 if (!hw_binary)
214 return false;
215
216 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
217 hw_binary) == NULL) {
218 FREE(hw_binary);
219 return false;
220 }
221
222 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
223 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
224 *((uint32_t *)ir_binary), key);
225 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
226 *((uint32_t *) hw_binary), NULL);
227 }
228
229 return true;
230 }
231
232 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
233 struct si_shader *shader)
234 {
235 struct hash_entry *entry =
236 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
237 if (!entry) {
238 if (sscreen->disk_shader_cache) {
239 unsigned char sha1[CACHE_KEY_SIZE];
240 size_t tg_size = *((uint32_t *) ir_binary);
241
242 disk_cache_compute_key(sscreen->disk_shader_cache,
243 ir_binary, tg_size, sha1);
244
245 size_t binary_size;
246 uint8_t *buffer =
247 disk_cache_get(sscreen->disk_shader_cache,
248 sha1, &binary_size);
249 if (!buffer)
250 return false;
251
252 if (binary_size < sizeof(uint32_t) ||
253 *((uint32_t*)buffer) != binary_size) {
254 /* Something has gone wrong discard the item
255 * from the cache and rebuild/link from
256 * source.
257 */
258 assert(!"Invalid radeonsi shader disk cache "
259 "item!");
260
261 disk_cache_remove(sscreen->disk_shader_cache,
262 sha1);
263 free(buffer);
264
265 return false;
266 }
267
268 if (!si_load_shader_binary(shader, buffer)) {
269 free(buffer);
270 return false;
271 }
272 free(buffer);
273
274 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
275 shader, false))
276 FREE(ir_binary);
277 } else {
278 return false;
279 }
280 } else {
281 if (si_load_shader_binary(shader, entry->data))
282 FREE(ir_binary);
283 else
284 return false;
285 }
286 p_atomic_inc(&sscreen->num_shader_cache_hits);
287 return true;
288 }
289
290 static uint32_t si_shader_cache_key_hash(const void *key)
291 {
292 /* The first dword is the key size. */
293 return util_hash_crc32(key, *(uint32_t*)key);
294 }
295
296 static bool si_shader_cache_key_equals(const void *a, const void *b)
297 {
298 uint32_t *keya = (uint32_t*)a;
299 uint32_t *keyb = (uint32_t*)b;
300
301 /* The first dword is the key size. */
302 if (*keya != *keyb)
303 return false;
304
305 return memcmp(keya, keyb, *keya) == 0;
306 }
307
308 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
309 {
310 FREE((void*)entry->key);
311 FREE(entry->data);
312 }
313
314 bool si_init_shader_cache(struct si_screen *sscreen)
315 {
316 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
317 sscreen->shader_cache =
318 _mesa_hash_table_create(NULL,
319 si_shader_cache_key_hash,
320 si_shader_cache_key_equals);
321
322 return sscreen->shader_cache != NULL;
323 }
324
325 void si_destroy_shader_cache(struct si_screen *sscreen)
326 {
327 if (sscreen->shader_cache)
328 _mesa_hash_table_destroy(sscreen->shader_cache,
329 si_destroy_shader_cache_entry);
330 mtx_destroy(&sscreen->shader_cache_mutex);
331 }
332
333 /* SHADER STATES */
334
335 static void si_set_tesseval_regs(struct si_screen *sscreen,
336 const struct si_shader_selector *tes,
337 struct si_pm4_state *pm4)
338 {
339 const struct tgsi_shader_info *info = &tes->info;
340 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
341 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
342 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
343 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
344 unsigned type, partitioning, topology, distribution_mode;
345
346 switch (tes_prim_mode) {
347 case PIPE_PRIM_LINES:
348 type = V_028B6C_TESS_ISOLINE;
349 break;
350 case PIPE_PRIM_TRIANGLES:
351 type = V_028B6C_TESS_TRIANGLE;
352 break;
353 case PIPE_PRIM_QUADS:
354 type = V_028B6C_TESS_QUAD;
355 break;
356 default:
357 assert(0);
358 return;
359 }
360
361 switch (tes_spacing) {
362 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
363 partitioning = V_028B6C_PART_FRAC_ODD;
364 break;
365 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
366 partitioning = V_028B6C_PART_FRAC_EVEN;
367 break;
368 case PIPE_TESS_SPACING_EQUAL:
369 partitioning = V_028B6C_PART_INTEGER;
370 break;
371 default:
372 assert(0);
373 return;
374 }
375
376 if (tes_point_mode)
377 topology = V_028B6C_OUTPUT_POINT;
378 else if (tes_prim_mode == PIPE_PRIM_LINES)
379 topology = V_028B6C_OUTPUT_LINE;
380 else if (tes_vertex_order_cw)
381 /* for some reason, this must be the other way around */
382 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
383 else
384 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
385
386 if (sscreen->info.has_distributed_tess) {
387 if (sscreen->info.family == CHIP_FIJI ||
388 sscreen->info.family >= CHIP_POLARIS10)
389 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
390 else
391 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
392 } else
393 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
394
395 assert(pm4->shader);
396 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
397 S_028B6C_PARTITIONING(partitioning) |
398 S_028B6C_TOPOLOGY(topology) |
399 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
400 }
401
402 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
403 * whether the "fractional odd" tessellation spacing is used.
404 *
405 * Possible VGT configurations and which state should set the register:
406 *
407 * Reg set in | VGT shader configuration | Value
408 * ------------------------------------------------------
409 * VS as VS | VS | 30
410 * VS as ES | ES -> GS -> VS | 30
411 * TES as VS | LS -> HS -> VS | 14 or 30
412 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
413 *
414 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
415 */
416 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
417 struct si_shader_selector *sel,
418 struct si_shader *shader,
419 struct si_pm4_state *pm4)
420 {
421 unsigned type = sel->type;
422
423 if (sscreen->info.family < CHIP_POLARIS10 ||
424 sscreen->info.chip_class >= GFX10)
425 return;
426
427 /* VS as VS, or VS as ES: */
428 if ((type == PIPE_SHADER_VERTEX &&
429 (!shader ||
430 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
431 /* TES as VS, or TES as ES: */
432 type == PIPE_SHADER_TESS_EVAL) {
433 unsigned vtx_reuse_depth = 30;
434
435 if (type == PIPE_SHADER_TESS_EVAL &&
436 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
437 PIPE_TESS_SPACING_FRACTIONAL_ODD)
438 vtx_reuse_depth = 14;
439
440 assert(pm4->shader);
441 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
442 }
443 }
444
445 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
446 {
447 if (shader->pm4)
448 si_pm4_clear_state(shader->pm4);
449 else
450 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
451
452 if (shader->pm4) {
453 shader->pm4->shader = shader;
454 return shader->pm4;
455 } else {
456 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
457 return NULL;
458 }
459 }
460
461 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
462 {
463 /* Add the pointer to VBO descriptors. */
464 return num_always_on_user_sgprs + 1;
465 }
466
467 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
468 {
469 struct si_pm4_state *pm4;
470 unsigned vgpr_comp_cnt;
471 uint64_t va;
472
473 assert(sscreen->info.chip_class <= GFX8);
474
475 pm4 = si_get_shader_pm4_state(shader);
476 if (!pm4)
477 return;
478
479 va = shader->bo->gpu_address;
480 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
481
482 /* We need at least 2 components for LS.
483 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
484 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
485 */
486 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
487
488 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
489 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
490
491 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
492 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
493 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
494 S_00B528_DX10_CLAMP(1) |
495 S_00B528_FLOAT_MODE(shader->config.float_mode);
496 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
497 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
498 }
499
500 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
501 {
502 struct si_pm4_state *pm4;
503 uint64_t va;
504 unsigned ls_vgpr_comp_cnt = 0;
505
506 pm4 = si_get_shader_pm4_state(shader);
507 if (!pm4)
508 return;
509
510 va = shader->bo->gpu_address;
511 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
512
513 if (sscreen->info.chip_class >= GFX9) {
514 if (sscreen->info.chip_class >= GFX10) {
515 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
516 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
517 } else {
518 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
519 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
520 }
521
522 /* We need at least 2 components for LS.
523 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
524 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
525 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
526 * be loaded.
527 */
528 ls_vgpr_comp_cnt = 1;
529 if (shader->info.uses_instanceid) {
530 if (sscreen->info.chip_class >= GFX10)
531 ls_vgpr_comp_cnt = 3;
532 else
533 ls_vgpr_comp_cnt = 2;
534 }
535
536 unsigned num_user_sgprs =
537 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
538
539 shader->config.rsrc2 =
540 S_00B42C_USER_SGPR(num_user_sgprs) |
541 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
542
543 if (sscreen->info.chip_class >= GFX10)
544 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
545 else
546 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
547 } else {
548 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
549 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
550
551 shader->config.rsrc2 =
552 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
553 S_00B42C_OC_LDS_EN(1) |
554 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
555 }
556
557 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
558 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
559 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
560 (sscreen->info.chip_class <= GFX9 ?
561 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
562 S_00B428_DX10_CLAMP(1) |
563 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
564 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
565 S_00B428_FLOAT_MODE(shader->config.float_mode) |
566 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
567
568 if (sscreen->info.chip_class <= GFX8) {
569 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
570 shader->config.rsrc2);
571 }
572 }
573
574 static void si_emit_shader_es(struct si_context *sctx)
575 {
576 struct si_shader *shader = sctx->queued.named.es->shader;
577 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
578
579 if (!shader)
580 return;
581
582 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
583 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
584 shader->selector->esgs_itemsize / 4);
585
586 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
587 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
588 SI_TRACKED_VGT_TF_PARAM,
589 shader->vgt_tf_param);
590
591 if (shader->vgt_vertex_reuse_block_cntl)
592 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
593 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
594 shader->vgt_vertex_reuse_block_cntl);
595
596 if (initial_cdw != sctx->gfx_cs->current.cdw)
597 sctx->context_roll = true;
598 }
599
600 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
601 {
602 struct si_pm4_state *pm4;
603 unsigned num_user_sgprs;
604 unsigned vgpr_comp_cnt;
605 uint64_t va;
606 unsigned oc_lds_en;
607
608 assert(sscreen->info.chip_class <= GFX8);
609
610 pm4 = si_get_shader_pm4_state(shader);
611 if (!pm4)
612 return;
613
614 pm4->atom.emit = si_emit_shader_es;
615 va = shader->bo->gpu_address;
616 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
617
618 if (shader->selector->type == PIPE_SHADER_VERTEX) {
619 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
620 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
621 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
622 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
623 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
624 num_user_sgprs = SI_TES_NUM_USER_SGPR;
625 } else
626 unreachable("invalid shader selector type");
627
628 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
629
630 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
631 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
632 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
633 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
634 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
635 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
636 S_00B328_DX10_CLAMP(1) |
637 S_00B328_FLOAT_MODE(shader->config.float_mode));
638 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
639 S_00B32C_USER_SGPR(num_user_sgprs) |
640 S_00B32C_OC_LDS_EN(oc_lds_en) |
641 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
642
643 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
644 si_set_tesseval_regs(sscreen, shader->selector, pm4);
645
646 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
647 }
648
649 void gfx9_get_gs_info(struct si_shader_selector *es,
650 struct si_shader_selector *gs,
651 struct gfx9_gs_info *out)
652 {
653 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
654 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
655 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
656 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
657
658 /* All these are in dwords: */
659 /* We can't allow using the whole LDS, because GS waves compete with
660 * other shader stages for LDS space. */
661 const unsigned max_lds_size = 8 * 1024;
662 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
663 unsigned esgs_lds_size;
664
665 /* All these are per subgroup: */
666 const unsigned max_out_prims = 32 * 1024;
667 const unsigned max_es_verts = 255;
668 const unsigned ideal_gs_prims = 64;
669 unsigned max_gs_prims, gs_prims;
670 unsigned min_es_verts, es_verts, worst_case_es_verts;
671
672 if (uses_adjacency || gs_num_invocations > 1)
673 max_gs_prims = 127 / gs_num_invocations;
674 else
675 max_gs_prims = 255;
676
677 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
678 * Make sure we don't go over the maximum value.
679 */
680 if (gs->gs_max_out_vertices > 0) {
681 max_gs_prims = MIN2(max_gs_prims,
682 max_out_prims /
683 (gs->gs_max_out_vertices * gs_num_invocations));
684 }
685 assert(max_gs_prims > 0);
686
687 /* If the primitive has adjacency, halve the number of vertices
688 * that will be reused in multiple primitives.
689 */
690 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
691
692 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
693 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
694
695 /* Compute ESGS LDS size based on the worst case number of ES vertices
696 * needed to create the target number of GS prims per subgroup.
697 */
698 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
699
700 /* If total LDS usage is too big, refactor partitions based on ratio
701 * of ESGS item sizes.
702 */
703 if (esgs_lds_size > max_lds_size) {
704 /* Our target GS Prims Per Subgroup was too large. Calculate
705 * the maximum number of GS Prims Per Subgroup that will fit
706 * into LDS, capped by the maximum that the hardware can support.
707 */
708 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
709 max_gs_prims);
710 assert(gs_prims > 0);
711 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
712 max_es_verts);
713
714 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
715 assert(esgs_lds_size <= max_lds_size);
716 }
717
718 /* Now calculate remaining ESGS information. */
719 if (esgs_lds_size)
720 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
721 else
722 es_verts = max_es_verts;
723
724 /* Vertices for adjacency primitives are not always reused, so restore
725 * it for ES_VERTS_PER_SUBGRP.
726 */
727 min_es_verts = gs->gs_input_verts_per_prim;
728
729 /* For normal primitives, the VGT only checks if they are past the ES
730 * verts per subgroup after allocating a full GS primitive and if they
731 * are, kick off a new subgroup. But if those additional ES verts are
732 * unique (e.g. not reused) we need to make sure there is enough LDS
733 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
734 */
735 es_verts -= min_es_verts - 1;
736
737 out->es_verts_per_subgroup = es_verts;
738 out->gs_prims_per_subgroup = gs_prims;
739 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
740 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
741 gs->gs_max_out_vertices;
742 out->esgs_ring_size = 4 * esgs_lds_size;
743
744 assert(out->max_prims_per_subgroup <= max_out_prims);
745 }
746
747 static void si_emit_shader_gs(struct si_context *sctx)
748 {
749 struct si_shader *shader = sctx->queued.named.gs->shader;
750 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
751
752 if (!shader)
753 return;
754
755 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
756 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
757 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
758 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
759 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
760 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
761 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
762
763 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
764 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
765 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
766 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
767
768 /* R_028B38_VGT_GS_MAX_VERT_OUT */
769 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
770 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
771 shader->ctx_reg.gs.vgt_gs_max_vert_out);
772
773 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
774 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
775 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
776 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
777 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
778 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
779 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
780 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
781
782 /* R_028B90_VGT_GS_INSTANCE_CNT */
783 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
784 SI_TRACKED_VGT_GS_INSTANCE_CNT,
785 shader->ctx_reg.gs.vgt_gs_instance_cnt);
786
787 if (sctx->chip_class >= GFX9) {
788 /* R_028A44_VGT_GS_ONCHIP_CNTL */
789 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
790 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
791 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
792 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
793 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
794 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
795 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
796 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
797 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
798 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
799 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
800
801 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
802 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
803 SI_TRACKED_VGT_TF_PARAM,
804 shader->vgt_tf_param);
805 if (shader->vgt_vertex_reuse_block_cntl)
806 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
807 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
808 shader->vgt_vertex_reuse_block_cntl);
809 }
810
811 if (initial_cdw != sctx->gfx_cs->current.cdw)
812 sctx->context_roll = true;
813 }
814
815 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
816 {
817 struct si_shader_selector *sel = shader->selector;
818 const ubyte *num_components = sel->info.num_stream_output_components;
819 unsigned gs_num_invocations = sel->gs_num_invocations;
820 struct si_pm4_state *pm4;
821 uint64_t va;
822 unsigned max_stream = sel->max_gs_stream;
823 unsigned offset;
824
825 pm4 = si_get_shader_pm4_state(shader);
826 if (!pm4)
827 return;
828
829 pm4->atom.emit = si_emit_shader_gs;
830
831 offset = num_components[0] * sel->gs_max_out_vertices;
832 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
833
834 if (max_stream >= 1)
835 offset += num_components[1] * sel->gs_max_out_vertices;
836 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
837
838 if (max_stream >= 2)
839 offset += num_components[2] * sel->gs_max_out_vertices;
840 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
841
842 if (max_stream >= 3)
843 offset += num_components[3] * sel->gs_max_out_vertices;
844 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
845
846 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
847 assert(offset < (1 << 15));
848
849 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
850
851 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
852 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
853 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
854 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
855
856 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
857 S_028B90_ENABLE(gs_num_invocations > 0);
858
859 va = shader->bo->gpu_address;
860 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
861
862 if (sscreen->info.chip_class >= GFX9) {
863 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
864 unsigned es_type = shader->key.part.gs.es->type;
865 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
866
867 if (es_type == PIPE_SHADER_VERTEX)
868 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
869 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
870 else if (es_type == PIPE_SHADER_TESS_EVAL)
871 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
872 else
873 unreachable("invalid shader selector type");
874
875 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
876 * VGPR[0:4] are always loaded.
877 */
878 if (sel->info.uses_invocationid)
879 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
880 else if (sel->info.uses_primid)
881 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
882 else if (input_prim >= PIPE_PRIM_TRIANGLES)
883 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
884 else
885 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
886
887 unsigned num_user_sgprs;
888 if (es_type == PIPE_SHADER_VERTEX)
889 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
890 else
891 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
892
893 if (sscreen->info.chip_class >= GFX10) {
894 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
895 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
896 } else {
897 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
898 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
899 }
900
901 uint32_t rsrc1 =
902 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
903 S_00B228_DX10_CLAMP(1) |
904 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
905 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
906 S_00B228_FLOAT_MODE(shader->config.float_mode) |
907 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
908 uint32_t rsrc2 =
909 S_00B22C_USER_SGPR(num_user_sgprs) |
910 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
911 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
912 S_00B22C_LDS_SIZE(shader->config.lds_size) |
913 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
914
915 if (sscreen->info.chip_class >= GFX10) {
916 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
917 } else {
918 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
919 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
920 }
921
922 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
923 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
924
925 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
926 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
927 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
928 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
929 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
930 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
931 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
932 shader->key.part.gs.es->esgs_itemsize / 4;
933
934 if (es_type == PIPE_SHADER_TESS_EVAL)
935 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
936
937 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
938 NULL, pm4);
939 } else {
940 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
941 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
942
943 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
944 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
945 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
946 S_00B228_DX10_CLAMP(1) |
947 S_00B228_FLOAT_MODE(shader->config.float_mode));
948 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
949 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
950 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
951 }
952 }
953
954 /* Common tail code for NGG primitive shaders. */
955 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
956 struct si_shader *shader,
957 unsigned initial_cdw)
958 {
959 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
960 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
961 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
962 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
963 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
964 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
965 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
966 SI_TRACKED_VGT_PRIMITIVEID_EN,
967 shader->ctx_reg.ngg.vgt_primitiveid_en);
968 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
969 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
970 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
971 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
972 SI_TRACKED_VGT_GS_INSTANCE_CNT,
973 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
974 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
975 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
976 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
977 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
978 SI_TRACKED_SPI_VS_OUT_CONFIG,
979 shader->ctx_reg.ngg.spi_vs_out_config);
980 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
981 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
982 shader->ctx_reg.ngg.spi_shader_idx_format,
983 shader->ctx_reg.ngg.spi_shader_pos_format);
984 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
985 SI_TRACKED_PA_CL_VTE_CNTL,
986 shader->ctx_reg.ngg.pa_cl_vte_cntl);
987 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
988 SI_TRACKED_PA_CL_NGG_CNTL,
989 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
990
991 if (initial_cdw != sctx->gfx_cs->current.cdw)
992 sctx->context_roll = true;
993 }
994
995 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
996 {
997 struct si_shader *shader = sctx->queued.named.gs->shader;
998 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
999
1000 if (!shader)
1001 return;
1002
1003 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1004 }
1005
1006 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1007 {
1008 struct si_shader *shader = sctx->queued.named.gs->shader;
1009 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1010
1011 if (!shader)
1012 return;
1013
1014 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1015 SI_TRACKED_VGT_TF_PARAM,
1016 shader->vgt_tf_param);
1017
1018 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1019 }
1020
1021 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1022 {
1023 struct si_shader *shader = sctx->queued.named.gs->shader;
1024 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1025
1026 if (!shader)
1027 return;
1028
1029 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1030 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1031 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1032
1033 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1034 }
1035
1036 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1037 {
1038 struct si_shader *shader = sctx->queued.named.gs->shader;
1039 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1040
1041 if (!shader)
1042 return;
1043
1044 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1045 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1046 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1047 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1048 SI_TRACKED_VGT_TF_PARAM,
1049 shader->vgt_tf_param);
1050
1051 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1052 }
1053
1054 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1055 {
1056 if (gs->type == PIPE_SHADER_GEOMETRY)
1057 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1058
1059 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1060 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1061 return PIPE_PRIM_POINTS;
1062 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1063 return PIPE_PRIM_LINES;
1064 return PIPE_PRIM_TRIANGLES;
1065 }
1066
1067 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1068 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1069 }
1070
1071 /**
1072 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1073 * in NGG mode.
1074 */
1075 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1076 {
1077 const struct si_shader_selector *gs_sel = shader->selector;
1078 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1079 enum pipe_shader_type gs_type = shader->selector->type;
1080 const struct si_shader_selector *es_sel =
1081 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1082 const struct tgsi_shader_info *es_info = &es_sel->info;
1083 enum pipe_shader_type es_type = es_sel->type;
1084 unsigned num_user_sgprs;
1085 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1086 uint64_t va;
1087 unsigned window_space =
1088 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1089 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1090 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1091 unsigned input_prim = si_get_input_prim(gs_sel);
1092 bool break_wave_at_eoi = false;
1093 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1094 if (!pm4)
1095 return;
1096
1097 if (es_type == PIPE_SHADER_TESS_EVAL) {
1098 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1099 : gfx10_emit_shader_ngg_tess_nogs;
1100 } else {
1101 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1102 : gfx10_emit_shader_ngg_notess_nogs;
1103 }
1104
1105 va = shader->bo->gpu_address;
1106 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1107
1108 if (es_type == PIPE_SHADER_VERTEX) {
1109 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1110 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1111
1112 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1113 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1114 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1115 } else {
1116 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1117 }
1118 } else {
1119 assert(es_type == PIPE_SHADER_TESS_EVAL);
1120 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1121 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1122
1123 if (es_enable_prim_id || gs_info->uses_primid)
1124 break_wave_at_eoi = true;
1125 }
1126
1127 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1128 * VGPR[0:4] are always loaded.
1129 *
1130 * Vertex shaders always need to load VGPR3, because they need to
1131 * pass edge flags for decomposed primitives (such as quads) to the PA
1132 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1133 */
1134 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1135 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1136 else if (gs_info->uses_primid)
1137 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1138 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1139 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1140 else
1141 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1142
1143 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1144 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1145 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1146 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1147 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1148 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1149 S_00B228_DX10_CLAMP(1) |
1150 S_00B228_MEM_ORDERED(1) |
1151 S_00B228_WGP_MODE(1) |
1152 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1153 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1154 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1155 S_00B22C_USER_SGPR(num_user_sgprs) |
1156 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1157 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1158 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1159 S_00B22C_LDS_SIZE(shader->config.lds_size));
1160
1161 nparams = MAX2(shader->info.nr_param_exports, 1);
1162 shader->ctx_reg.ngg.spi_vs_out_config =
1163 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1164 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1165
1166 shader->ctx_reg.ngg.spi_shader_idx_format =
1167 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1168 shader->ctx_reg.ngg.spi_shader_pos_format =
1169 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1170 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1171 V_02870C_SPI_SHADER_4COMP :
1172 V_02870C_SPI_SHADER_NONE) |
1173 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1174 V_02870C_SPI_SHADER_4COMP :
1175 V_02870C_SPI_SHADER_NONE) |
1176 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1177 V_02870C_SPI_SHADER_4COMP :
1178 V_02870C_SPI_SHADER_NONE);
1179
1180 shader->ctx_reg.ngg.vgt_primitiveid_en =
1181 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1182 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1183
1184 if (gs_type == PIPE_SHADER_GEOMETRY) {
1185 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1186 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1187 } else {
1188 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1189 }
1190
1191 if (es_type == PIPE_SHADER_TESS_EVAL)
1192 si_set_tesseval_regs(sscreen, es_sel, pm4);
1193
1194 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1195 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1196 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1197 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1198 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1199 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1200 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1201 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1202 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1203 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1204 S_028B90_CNT(gs_num_invocations) |
1205 S_028B90_ENABLE(gs_num_invocations > 1) |
1206 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1207 shader->ngg.max_vert_out_per_gs_instance);
1208
1209 /* Always output hw-generated edge flags and pass them via the prim
1210 * export to prevent drawing lines on internal edges of decomposed
1211 * primitives (such as quads) with polygon mode = lines. Only VS needs
1212 * this.
1213 */
1214 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1215 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1216
1217 shader->ge_cntl =
1218 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1219 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1220 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1221
1222 /* Bug workaround for a possible hang with non-tessellation cases.
1223 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1224 *
1225 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1226 */
1227 if ((sscreen->info.family == CHIP_NAVI10 ||
1228 sscreen->info.family == CHIP_NAVI12 ||
1229 sscreen->info.family == CHIP_NAVI14) &&
1230 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1231 shader->ngg.hw_max_esverts != 256) {
1232 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1233
1234 if (shader->ngg.hw_max_esverts > 5) {
1235 shader->ge_cntl |=
1236 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1237 }
1238 }
1239
1240 if (window_space) {
1241 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1242 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1243 } else {
1244 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1245 S_028818_VTX_W0_FMT(1) |
1246 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1247 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1248 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1249 }
1250 }
1251
1252 static void si_emit_shader_vs(struct si_context *sctx)
1253 {
1254 struct si_shader *shader = sctx->queued.named.vs->shader;
1255 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1256
1257 if (!shader)
1258 return;
1259
1260 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1261 SI_TRACKED_VGT_GS_MODE,
1262 shader->ctx_reg.vs.vgt_gs_mode);
1263 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1264 SI_TRACKED_VGT_PRIMITIVEID_EN,
1265 shader->ctx_reg.vs.vgt_primitiveid_en);
1266
1267 if (sctx->chip_class <= GFX8) {
1268 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1269 SI_TRACKED_VGT_REUSE_OFF,
1270 shader->ctx_reg.vs.vgt_reuse_off);
1271 }
1272
1273 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1274 SI_TRACKED_SPI_VS_OUT_CONFIG,
1275 shader->ctx_reg.vs.spi_vs_out_config);
1276
1277 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1278 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1279 shader->ctx_reg.vs.spi_shader_pos_format);
1280
1281 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1282 SI_TRACKED_PA_CL_VTE_CNTL,
1283 shader->ctx_reg.vs.pa_cl_vte_cntl);
1284
1285 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1286 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1287 SI_TRACKED_VGT_TF_PARAM,
1288 shader->vgt_tf_param);
1289
1290 if (shader->vgt_vertex_reuse_block_cntl)
1291 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1292 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1293 shader->vgt_vertex_reuse_block_cntl);
1294
1295 if (initial_cdw != sctx->gfx_cs->current.cdw)
1296 sctx->context_roll = true;
1297 }
1298
1299 /**
1300 * Compute the state for \p shader, which will run as a vertex shader on the
1301 * hardware.
1302 *
1303 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1304 * is the copy shader.
1305 */
1306 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1307 struct si_shader_selector *gs)
1308 {
1309 const struct tgsi_shader_info *info = &shader->selector->info;
1310 struct si_pm4_state *pm4;
1311 unsigned num_user_sgprs, vgpr_comp_cnt;
1312 uint64_t va;
1313 unsigned nparams, oc_lds_en;
1314 unsigned window_space =
1315 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1316 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1317
1318 pm4 = si_get_shader_pm4_state(shader);
1319 if (!pm4)
1320 return;
1321
1322 pm4->atom.emit = si_emit_shader_vs;
1323
1324 /* We always write VGT_GS_MODE in the VS state, because every switch
1325 * between different shader pipelines involving a different GS or no
1326 * GS at all involves a switch of the VS (different GS use different
1327 * copy shaders). On the other hand, when the API switches from a GS to
1328 * no GS and then back to the same GS used originally, the GS state is
1329 * not sent again.
1330 */
1331 if (!gs) {
1332 unsigned mode = V_028A40_GS_OFF;
1333
1334 /* PrimID needs GS scenario A. */
1335 if (enable_prim_id)
1336 mode = V_028A40_GS_SCENARIO_A;
1337
1338 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1339 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1340 } else {
1341 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1342 sscreen->info.chip_class);
1343 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1344 }
1345
1346 if (sscreen->info.chip_class <= GFX8) {
1347 /* Reuse needs to be set off if we write oViewport. */
1348 shader->ctx_reg.vs.vgt_reuse_off =
1349 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1350 }
1351
1352 va = shader->bo->gpu_address;
1353 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1354
1355 if (gs) {
1356 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1357 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1358 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1359 if (sscreen->info.chip_class >= GFX10) {
1360 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
1361 } else {
1362 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1363 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1364 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1365 */
1366 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1367 }
1368
1369 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1370 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1371 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1372 } else {
1373 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1374 }
1375 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1376 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1377 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1378 } else
1379 unreachable("invalid shader selector type");
1380
1381 /* VS is required to export at least one param. */
1382 nparams = MAX2(shader->info.nr_param_exports, 1);
1383 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1384
1385 if (sscreen->info.chip_class >= GFX10) {
1386 shader->ctx_reg.vs.spi_vs_out_config |=
1387 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1388 }
1389
1390 shader->ctx_reg.vs.spi_shader_pos_format =
1391 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1392 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1393 V_02870C_SPI_SHADER_4COMP :
1394 V_02870C_SPI_SHADER_NONE) |
1395 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1396 V_02870C_SPI_SHADER_4COMP :
1397 V_02870C_SPI_SHADER_NONE) |
1398 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1399 V_02870C_SPI_SHADER_4COMP :
1400 V_02870C_SPI_SHADER_NONE);
1401
1402 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1403
1404 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1405 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1406
1407 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1408 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1409 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1410 S_00B128_DX10_CLAMP(1) |
1411 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1412 S_00B128_FLOAT_MODE(shader->config.float_mode);
1413 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1414 S_00B12C_OC_LDS_EN(oc_lds_en) |
1415 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1416
1417 if (sscreen->info.chip_class <= GFX9)
1418 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1419
1420 if (!sscreen->use_ngg_streamout) {
1421 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1422 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1423 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1424 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1425 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1426 }
1427
1428 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1429 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1430
1431 if (window_space)
1432 shader->ctx_reg.vs.pa_cl_vte_cntl =
1433 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1434 else
1435 shader->ctx_reg.vs.pa_cl_vte_cntl =
1436 S_028818_VTX_W0_FMT(1) |
1437 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1438 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1439 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1440
1441 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1442 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1443
1444 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1445 }
1446
1447 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1448 {
1449 struct tgsi_shader_info *info = &ps->selector->info;
1450 unsigned num_colors = !!(info->colors_read & 0x0f) +
1451 !!(info->colors_read & 0xf0);
1452 unsigned num_interp = ps->selector->info.num_inputs +
1453 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1454
1455 assert(num_interp <= 32);
1456 return MIN2(num_interp, 32);
1457 }
1458
1459 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1460 {
1461 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1462 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1463
1464 /* If the i-th target format is set, all previous target formats must
1465 * be non-zero to avoid hangs.
1466 */
1467 for (i = 0; i < num_targets; i++)
1468 if (!(value & (0xf << (i * 4))))
1469 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1470
1471 return value;
1472 }
1473
1474 static void si_emit_shader_ps(struct si_context *sctx)
1475 {
1476 struct si_shader *shader = sctx->queued.named.ps->shader;
1477 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1478
1479 if (!shader)
1480 return;
1481
1482 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1483 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1484 SI_TRACKED_SPI_PS_INPUT_ENA,
1485 shader->ctx_reg.ps.spi_ps_input_ena,
1486 shader->ctx_reg.ps.spi_ps_input_addr);
1487
1488 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1489 SI_TRACKED_SPI_BARYC_CNTL,
1490 shader->ctx_reg.ps.spi_baryc_cntl);
1491 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1492 SI_TRACKED_SPI_PS_IN_CONTROL,
1493 shader->ctx_reg.ps.spi_ps_in_control);
1494
1495 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1496 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1497 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1498 shader->ctx_reg.ps.spi_shader_z_format,
1499 shader->ctx_reg.ps.spi_shader_col_format);
1500
1501 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1502 SI_TRACKED_CB_SHADER_MASK,
1503 shader->ctx_reg.ps.cb_shader_mask);
1504
1505 if (initial_cdw != sctx->gfx_cs->current.cdw)
1506 sctx->context_roll = true;
1507 }
1508
1509 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1510 {
1511 struct tgsi_shader_info *info = &shader->selector->info;
1512 struct si_pm4_state *pm4;
1513 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1514 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1515 uint64_t va;
1516 unsigned input_ena = shader->config.spi_ps_input_ena;
1517
1518 /* we need to enable at least one of them, otherwise we hang the GPU */
1519 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1520 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1521 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1522 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1523 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1524 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1525 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1526 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1527 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1528 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1529 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1530 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1531 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1532 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1533
1534 /* Validate interpolation optimization flags (read as implications). */
1535 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1536 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1537 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1538 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1539 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1540 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1541 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1542 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1543 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1544 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1545 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1546 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1547 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1548 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1549 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1550 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1551 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1552 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1553
1554 /* Validate cases when the optimizations are off (read as implications). */
1555 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1556 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1557 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1558 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1559 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1560 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1561
1562 pm4 = si_get_shader_pm4_state(shader);
1563 if (!pm4)
1564 return;
1565
1566 pm4->atom.emit = si_emit_shader_ps;
1567
1568 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1569 * Possible vaules:
1570 * 0 -> Position = pixel center
1571 * 1 -> Position = pixel centroid
1572 * 2 -> Position = at sample position
1573 *
1574 * From GLSL 4.5 specification, section 7.1:
1575 * "The variable gl_FragCoord is available as an input variable from
1576 * within fragment shaders and it holds the window relative coordinates
1577 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1578 * value can be for any location within the pixel, or one of the
1579 * fragment samples. The use of centroid does not further restrict
1580 * this value to be inside the current primitive."
1581 *
1582 * Meaning that centroid has no effect and we can return anything within
1583 * the pixel. Thus, return the value at sample position, because that's
1584 * the most accurate one shaders can get.
1585 */
1586 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1587
1588 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1589 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1590 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1591
1592 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1593 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1594
1595 /* Ensure that some export memory is always allocated, for two reasons:
1596 *
1597 * 1) Correctness: The hardware ignores the EXEC mask if no export
1598 * memory is allocated, so KILL and alpha test do not work correctly
1599 * without this.
1600 * 2) Performance: Every shader needs at least a NULL export, even when
1601 * it writes no color/depth output. The NULL export instruction
1602 * stalls without this setting.
1603 *
1604 * Don't add this to CB_SHADER_MASK.
1605 *
1606 * GFX10 supports pixel shaders without exports by setting both
1607 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1608 * instructions if any are present.
1609 */
1610 if ((sscreen->info.chip_class <= GFX9 ||
1611 info->uses_kill ||
1612 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1613 !spi_shader_col_format &&
1614 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1615 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1616
1617 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1618 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1619
1620 /* Set interpolation controls. */
1621 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1622 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1623
1624 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1625 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1626 shader->ctx_reg.ps.spi_shader_z_format =
1627 ac_get_spi_shader_z_format(info->writes_z,
1628 info->writes_stencil,
1629 info->writes_samplemask);
1630 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1631 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1632
1633 va = shader->bo->gpu_address;
1634 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1635 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1636 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1637
1638 uint32_t rsrc1 =
1639 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1640 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1641 S_00B028_DX10_CLAMP(1) |
1642 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1643 S_00B028_FLOAT_MODE(shader->config.float_mode);
1644
1645 if (sscreen->info.chip_class < GFX10) {
1646 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1647 }
1648
1649 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1650 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1651 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1652 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1653 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1654 }
1655
1656 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1657 struct si_shader *shader)
1658 {
1659 switch (shader->selector->type) {
1660 case PIPE_SHADER_VERTEX:
1661 if (shader->key.as_ls)
1662 si_shader_ls(sscreen, shader);
1663 else if (shader->key.as_es)
1664 si_shader_es(sscreen, shader);
1665 else if (shader->key.as_ngg)
1666 gfx10_shader_ngg(sscreen, shader);
1667 else
1668 si_shader_vs(sscreen, shader, NULL);
1669 break;
1670 case PIPE_SHADER_TESS_CTRL:
1671 si_shader_hs(sscreen, shader);
1672 break;
1673 case PIPE_SHADER_TESS_EVAL:
1674 if (shader->key.as_es)
1675 si_shader_es(sscreen, shader);
1676 else if (shader->key.as_ngg)
1677 gfx10_shader_ngg(sscreen, shader);
1678 else
1679 si_shader_vs(sscreen, shader, NULL);
1680 break;
1681 case PIPE_SHADER_GEOMETRY:
1682 if (shader->key.as_ngg)
1683 gfx10_shader_ngg(sscreen, shader);
1684 else
1685 si_shader_gs(sscreen, shader);
1686 break;
1687 case PIPE_SHADER_FRAGMENT:
1688 si_shader_ps(sscreen, shader);
1689 break;
1690 default:
1691 assert(0);
1692 }
1693 }
1694
1695 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1696 {
1697 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1698 return sctx->queued.named.dsa->alpha_func;
1699 }
1700
1701 void si_shader_selector_key_vs(struct si_context *sctx,
1702 struct si_shader_selector *vs,
1703 struct si_shader_key *key,
1704 struct si_vs_prolog_bits *prolog_key)
1705 {
1706 if (!sctx->vertex_elements ||
1707 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1708 return;
1709
1710 struct si_vertex_elements *elts = sctx->vertex_elements;
1711
1712 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1713 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1714 prolog_key->unpack_instance_id_from_vertex_id =
1715 sctx->prim_discard_cs_instancing;
1716
1717 /* Prefer a monolithic shader to allow scheduling divisions around
1718 * VBO loads. */
1719 if (prolog_key->instance_divisor_is_fetched)
1720 key->opt.prefer_mono = 1;
1721
1722 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1723 unsigned count_mask = (1 << count) - 1;
1724 unsigned fix = elts->fix_fetch_always & count_mask;
1725 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1726
1727 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1728 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1729 while (mask) {
1730 unsigned i = u_bit_scan(&mask);
1731 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1732 unsigned vbidx = elts->vertex_buffer_index[i];
1733 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1734 unsigned align_mask = (1 << log_hw_load_size) - 1;
1735 if (vb->buffer_offset & align_mask ||
1736 vb->stride & align_mask) {
1737 fix |= 1 << i;
1738 opencode |= 1 << i;
1739 }
1740 }
1741 }
1742
1743 while (fix) {
1744 unsigned i = u_bit_scan(&fix);
1745 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1746 }
1747 key->mono.vs_fetch_opencode = opencode;
1748 }
1749
1750 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1751 struct si_shader_selector *vs,
1752 struct si_shader_key *key)
1753 {
1754 struct si_shader_selector *ps = sctx->ps_shader.cso;
1755
1756 key->opt.clip_disable =
1757 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1758 (vs->info.clipdist_writemask ||
1759 vs->info.writes_clipvertex) &&
1760 !vs->info.culldist_writemask;
1761
1762 /* Find out if PS is disabled. */
1763 bool ps_disabled = true;
1764 if (ps) {
1765 bool ps_modifies_zs = ps->info.uses_kill ||
1766 ps->info.writes_z ||
1767 ps->info.writes_stencil ||
1768 ps->info.writes_samplemask ||
1769 sctx->queued.named.blend->alpha_to_coverage ||
1770 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1771 unsigned ps_colormask = si_get_total_colormask(sctx);
1772
1773 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1774 (!ps_colormask &&
1775 !ps_modifies_zs &&
1776 !ps->info.writes_memory);
1777 }
1778
1779 /* Find out which VS outputs aren't used by the PS. */
1780 uint64_t outputs_written = vs->outputs_written_before_ps;
1781 uint64_t inputs_read = 0;
1782
1783 /* Ignore outputs that are not passed from VS to PS. */
1784 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1785 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1786 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1787
1788 if (!ps_disabled) {
1789 inputs_read = ps->inputs_read;
1790 }
1791
1792 uint64_t linked = outputs_written & inputs_read;
1793
1794 key->opt.kill_outputs = ~linked & outputs_written;
1795 }
1796
1797 /* Compute the key for the hw shader variant */
1798 static inline void si_shader_selector_key(struct pipe_context *ctx,
1799 struct si_shader_selector *sel,
1800 union si_vgt_stages_key stages_key,
1801 struct si_shader_key *key)
1802 {
1803 struct si_context *sctx = (struct si_context *)ctx;
1804
1805 memset(key, 0, sizeof(*key));
1806
1807 switch (sel->type) {
1808 case PIPE_SHADER_VERTEX:
1809 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1810
1811 if (sctx->tes_shader.cso)
1812 key->as_ls = 1;
1813 else if (sctx->gs_shader.cso)
1814 key->as_es = 1;
1815 else {
1816 key->as_ngg = stages_key.u.ngg;
1817 si_shader_selector_key_hw_vs(sctx, sel, key);
1818
1819 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1820 key->mono.u.vs_export_prim_id = 1;
1821 }
1822 break;
1823 case PIPE_SHADER_TESS_CTRL:
1824 if (sctx->chip_class >= GFX9) {
1825 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1826 key, &key->part.tcs.ls_prolog);
1827 key->part.tcs.ls = sctx->vs_shader.cso;
1828
1829 /* When the LS VGPR fix is needed, monolithic shaders
1830 * can:
1831 * - avoid initializing EXEC in both the LS prolog
1832 * and the LS main part when !vs_needs_prolog
1833 * - remove the fixup for unused input VGPRs
1834 */
1835 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1836
1837 /* The LS output / HS input layout can be communicated
1838 * directly instead of via user SGPRs for merged LS-HS.
1839 * The LS VGPR fix prefers this too.
1840 */
1841 key->opt.prefer_mono = 1;
1842 }
1843
1844 key->part.tcs.epilog.prim_mode =
1845 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1846 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1847 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1848 key->part.tcs.epilog.tes_reads_tess_factors =
1849 sctx->tes_shader.cso->info.reads_tess_factors;
1850
1851 if (sel == sctx->fixed_func_tcs_shader.cso)
1852 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1853 break;
1854 case PIPE_SHADER_TESS_EVAL:
1855 key->as_ngg = stages_key.u.ngg;
1856
1857 if (sctx->gs_shader.cso)
1858 key->as_es = 1;
1859 else {
1860 si_shader_selector_key_hw_vs(sctx, sel, key);
1861
1862 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1863 key->mono.u.vs_export_prim_id = 1;
1864 }
1865 break;
1866 case PIPE_SHADER_GEOMETRY:
1867 if (sctx->chip_class >= GFX9) {
1868 if (sctx->tes_shader.cso) {
1869 key->part.gs.es = sctx->tes_shader.cso;
1870 } else {
1871 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1872 key, &key->part.gs.vs_prolog);
1873 key->part.gs.es = sctx->vs_shader.cso;
1874 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1875 }
1876
1877 key->as_ngg = stages_key.u.ngg;
1878
1879 /* Merged ES-GS can have unbalanced wave usage.
1880 *
1881 * ES threads are per-vertex, while GS threads are
1882 * per-primitive. So without any amplification, there
1883 * are fewer GS threads than ES threads, which can result
1884 * in empty (no-op) GS waves. With too much amplification,
1885 * there are more GS threads than ES threads, which
1886 * can result in empty (no-op) ES waves.
1887 *
1888 * Non-monolithic shaders are implemented by setting EXEC
1889 * at the beginning of shader parts, and don't jump to
1890 * the end if EXEC is 0.
1891 *
1892 * Monolithic shaders use conditional blocks, so they can
1893 * jump and skip empty waves of ES or GS. So set this to
1894 * always use optimized variants, which are monolithic.
1895 */
1896 key->opt.prefer_mono = 1;
1897 }
1898 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1899 break;
1900 case PIPE_SHADER_FRAGMENT: {
1901 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1902 struct si_state_blend *blend = sctx->queued.named.blend;
1903
1904 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1905 sel->info.colors_written == 0x1)
1906 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1907
1908 /* Select the shader color format based on whether
1909 * blending or alpha are needed.
1910 */
1911 key->part.ps.epilog.spi_shader_col_format =
1912 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1913 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1914 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1915 sctx->framebuffer.spi_shader_col_format_blend) |
1916 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1917 sctx->framebuffer.spi_shader_col_format_alpha) |
1918 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1919 sctx->framebuffer.spi_shader_col_format);
1920 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1921
1922 /* The output for dual source blending should have
1923 * the same format as the first output.
1924 */
1925 if (blend->dual_src_blend) {
1926 key->part.ps.epilog.spi_shader_col_format |=
1927 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1928 }
1929
1930 /* If alpha-to-coverage is enabled, we have to export alpha
1931 * even if there is no color buffer.
1932 */
1933 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1934 blend->alpha_to_coverage)
1935 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1936
1937 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1938 * to the range supported by the type if a channel has less
1939 * than 16 bits and the export format is 16_ABGR.
1940 */
1941 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1942 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1943 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1944 }
1945
1946 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1947 if (!key->part.ps.epilog.last_cbuf) {
1948 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1949 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1950 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1951 }
1952
1953 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1954 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1955
1956 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1957 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1958
1959 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
1960 rs->multisample_enable;
1961
1962 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1963 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1964 (is_line && rs->line_smooth)) &&
1965 sctx->framebuffer.nr_samples <= 1;
1966 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1967
1968 if (sctx->ps_iter_samples > 1 &&
1969 sel->info.reads_samplemask) {
1970 key->part.ps.prolog.samplemask_log_ps_iter =
1971 util_logbase2(sctx->ps_iter_samples);
1972 }
1973
1974 if (rs->force_persample_interp &&
1975 rs->multisample_enable &&
1976 sctx->framebuffer.nr_samples > 1 &&
1977 sctx->ps_iter_samples > 1) {
1978 key->part.ps.prolog.force_persp_sample_interp =
1979 sel->info.uses_persp_center ||
1980 sel->info.uses_persp_centroid;
1981
1982 key->part.ps.prolog.force_linear_sample_interp =
1983 sel->info.uses_linear_center ||
1984 sel->info.uses_linear_centroid;
1985 } else if (rs->multisample_enable &&
1986 sctx->framebuffer.nr_samples > 1) {
1987 key->part.ps.prolog.bc_optimize_for_persp =
1988 sel->info.uses_persp_center &&
1989 sel->info.uses_persp_centroid;
1990 key->part.ps.prolog.bc_optimize_for_linear =
1991 sel->info.uses_linear_center &&
1992 sel->info.uses_linear_centroid;
1993 } else {
1994 /* Make sure SPI doesn't compute more than 1 pair
1995 * of (i,j), which is the optimization here. */
1996 key->part.ps.prolog.force_persp_center_interp =
1997 sel->info.uses_persp_center +
1998 sel->info.uses_persp_centroid +
1999 sel->info.uses_persp_sample > 1;
2000
2001 key->part.ps.prolog.force_linear_center_interp =
2002 sel->info.uses_linear_center +
2003 sel->info.uses_linear_centroid +
2004 sel->info.uses_linear_sample > 1;
2005
2006 if (sel->info.uses_persp_opcode_interp_sample ||
2007 sel->info.uses_linear_opcode_interp_sample)
2008 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2009 }
2010
2011 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2012
2013 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2014 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2015 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2016 struct pipe_resource *tex = cb0->texture;
2017
2018 /* 1D textures are allocated and used as 2D on GFX9. */
2019 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2020 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2021 (tex->target == PIPE_TEXTURE_1D ||
2022 tex->target == PIPE_TEXTURE_1D_ARRAY);
2023 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2024 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2025 tex->target == PIPE_TEXTURE_CUBE ||
2026 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2027 tex->target == PIPE_TEXTURE_3D;
2028 }
2029 break;
2030 }
2031 default:
2032 assert(0);
2033 }
2034
2035 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2036 memset(&key->opt, 0, sizeof(key->opt));
2037 }
2038
2039 static void si_build_shader_variant(struct si_shader *shader,
2040 int thread_index,
2041 bool low_priority)
2042 {
2043 struct si_shader_selector *sel = shader->selector;
2044 struct si_screen *sscreen = sel->screen;
2045 struct ac_llvm_compiler *compiler;
2046 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2047
2048 if (thread_index >= 0) {
2049 if (low_priority) {
2050 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2051 compiler = &sscreen->compiler_lowp[thread_index];
2052 } else {
2053 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2054 compiler = &sscreen->compiler[thread_index];
2055 }
2056 if (!debug->async)
2057 debug = NULL;
2058 } else {
2059 assert(!low_priority);
2060 compiler = shader->compiler_ctx_state.compiler;
2061 }
2062
2063 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2064 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2065 sel->type);
2066 shader->compilation_failed = true;
2067 return;
2068 }
2069
2070 if (shader->compiler_ctx_state.is_debug_context) {
2071 FILE *f = open_memstream(&shader->shader_log,
2072 &shader->shader_log_size);
2073 if (f) {
2074 si_shader_dump(sscreen, shader, NULL, f, false);
2075 fclose(f);
2076 }
2077 }
2078
2079 si_shader_init_pm4_state(sscreen, shader);
2080 }
2081
2082 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2083 {
2084 struct si_shader *shader = (struct si_shader *)job;
2085
2086 assert(thread_index >= 0);
2087
2088 si_build_shader_variant(shader, thread_index, true);
2089 }
2090
2091 static const struct si_shader_key zeroed;
2092
2093 static bool si_check_missing_main_part(struct si_screen *sscreen,
2094 struct si_shader_selector *sel,
2095 struct si_compiler_ctx_state *compiler_state,
2096 struct si_shader_key *key)
2097 {
2098 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2099
2100 if (!*mainp) {
2101 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2102
2103 if (!main_part)
2104 return false;
2105
2106 /* We can leave the fence as permanently signaled because the
2107 * main part becomes visible globally only after it has been
2108 * compiled. */
2109 util_queue_fence_init(&main_part->ready);
2110
2111 main_part->selector = sel;
2112 main_part->key.as_es = key->as_es;
2113 main_part->key.as_ls = key->as_ls;
2114 main_part->key.as_ngg = key->as_ngg;
2115 main_part->is_monolithic = false;
2116
2117 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2118 main_part, &compiler_state->debug) != 0) {
2119 FREE(main_part);
2120 return false;
2121 }
2122 *mainp = main_part;
2123 }
2124 return true;
2125 }
2126
2127 /**
2128 * Select a shader variant according to the shader key.
2129 *
2130 * \param optimized_or_none If the key describes an optimized shader variant and
2131 * the compilation isn't finished, don't select any
2132 * shader and return an error.
2133 */
2134 int si_shader_select_with_key(struct si_screen *sscreen,
2135 struct si_shader_ctx_state *state,
2136 struct si_compiler_ctx_state *compiler_state,
2137 struct si_shader_key *key,
2138 int thread_index,
2139 bool optimized_or_none)
2140 {
2141 struct si_shader_selector *sel = state->cso;
2142 struct si_shader_selector *previous_stage_sel = NULL;
2143 struct si_shader *current = state->current;
2144 struct si_shader *iter, *shader = NULL;
2145
2146 again:
2147 /* Check if we don't need to change anything.
2148 * This path is also used for most shaders that don't need multiple
2149 * variants, it will cost just a computation of the key and this
2150 * test. */
2151 if (likely(current &&
2152 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2153 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2154 if (current->is_optimized) {
2155 if (optimized_or_none)
2156 return -1;
2157
2158 memset(&key->opt, 0, sizeof(key->opt));
2159 goto current_not_ready;
2160 }
2161
2162 util_queue_fence_wait(&current->ready);
2163 }
2164
2165 return current->compilation_failed ? -1 : 0;
2166 }
2167 current_not_ready:
2168
2169 /* This must be done before the mutex is locked, because async GS
2170 * compilation calls this function too, and therefore must enter
2171 * the mutex first.
2172 *
2173 * Only wait if we are in a draw call. Don't wait if we are
2174 * in a compiler thread.
2175 */
2176 if (thread_index < 0)
2177 util_queue_fence_wait(&sel->ready);
2178
2179 mtx_lock(&sel->mutex);
2180
2181 /* Find the shader variant. */
2182 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2183 /* Don't check the "current" shader. We checked it above. */
2184 if (current != iter &&
2185 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2186 mtx_unlock(&sel->mutex);
2187
2188 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2189 /* If it's an optimized shader and its compilation has
2190 * been started but isn't done, use the unoptimized
2191 * shader so as not to cause a stall due to compilation.
2192 */
2193 if (iter->is_optimized) {
2194 if (optimized_or_none)
2195 return -1;
2196 memset(&key->opt, 0, sizeof(key->opt));
2197 goto again;
2198 }
2199
2200 util_queue_fence_wait(&iter->ready);
2201 }
2202
2203 if (iter->compilation_failed) {
2204 return -1; /* skip the draw call */
2205 }
2206
2207 state->current = iter;
2208 return 0;
2209 }
2210 }
2211
2212 /* Build a new shader. */
2213 shader = CALLOC_STRUCT(si_shader);
2214 if (!shader) {
2215 mtx_unlock(&sel->mutex);
2216 return -ENOMEM;
2217 }
2218
2219 util_queue_fence_init(&shader->ready);
2220
2221 shader->selector = sel;
2222 shader->key = *key;
2223 shader->compiler_ctx_state = *compiler_state;
2224
2225 /* If this is a merged shader, get the first shader's selector. */
2226 if (sscreen->info.chip_class >= GFX9) {
2227 if (sel->type == PIPE_SHADER_TESS_CTRL)
2228 previous_stage_sel = key->part.tcs.ls;
2229 else if (sel->type == PIPE_SHADER_GEOMETRY)
2230 previous_stage_sel = key->part.gs.es;
2231
2232 /* We need to wait for the previous shader. */
2233 if (previous_stage_sel && thread_index < 0)
2234 util_queue_fence_wait(&previous_stage_sel->ready);
2235 }
2236
2237 bool is_pure_monolithic =
2238 sscreen->use_monolithic_shaders ||
2239 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2240
2241 /* Compile the main shader part if it doesn't exist. This can happen
2242 * if the initial guess was wrong.
2243 *
2244 * The prim discard CS doesn't need the main shader part.
2245 */
2246 if (!is_pure_monolithic &&
2247 !key->opt.vs_as_prim_discard_cs) {
2248 bool ok = true;
2249
2250 /* Make sure the main shader part is present. This is needed
2251 * for shaders that can be compiled as VS, LS, or ES, and only
2252 * one of them is compiled at creation.
2253 *
2254 * It is also needed for GS, which can be compiled as non-NGG
2255 * and NGG.
2256 *
2257 * For merged shaders, check that the starting shader's main
2258 * part is present.
2259 */
2260 if (previous_stage_sel) {
2261 struct si_shader_key shader1_key = zeroed;
2262
2263 if (sel->type == PIPE_SHADER_TESS_CTRL)
2264 shader1_key.as_ls = 1;
2265 else if (sel->type == PIPE_SHADER_GEOMETRY)
2266 shader1_key.as_es = 1;
2267 else
2268 assert(0);
2269
2270 if (sel->type == PIPE_SHADER_GEOMETRY &&
2271 previous_stage_sel->type == PIPE_SHADER_TESS_EVAL)
2272 shader1_key.as_ngg = key->as_ngg;
2273
2274 mtx_lock(&previous_stage_sel->mutex);
2275 ok = si_check_missing_main_part(sscreen,
2276 previous_stage_sel,
2277 compiler_state, &shader1_key);
2278 mtx_unlock(&previous_stage_sel->mutex);
2279 }
2280
2281 if (ok) {
2282 ok = si_check_missing_main_part(sscreen, sel,
2283 compiler_state, key);
2284 }
2285
2286 if (!ok) {
2287 FREE(shader);
2288 mtx_unlock(&sel->mutex);
2289 return -ENOMEM; /* skip the draw call */
2290 }
2291 }
2292
2293 /* Keep the reference to the 1st shader of merged shaders, so that
2294 * Gallium can't destroy it before we destroy the 2nd shader.
2295 *
2296 * Set sctx = NULL, because it's unused if we're not releasing
2297 * the shader, and we don't have any sctx here.
2298 */
2299 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2300 previous_stage_sel);
2301
2302 /* Monolithic-only shaders don't make a distinction between optimized
2303 * and unoptimized. */
2304 shader->is_monolithic =
2305 is_pure_monolithic ||
2306 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2307
2308 /* The prim discard CS is always optimized. */
2309 shader->is_optimized =
2310 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2311 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2312
2313 /* If it's an optimized shader, compile it asynchronously. */
2314 if (shader->is_optimized && thread_index < 0) {
2315 /* Compile it asynchronously. */
2316 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2317 shader, &shader->ready,
2318 si_build_shader_variant_low_priority, NULL);
2319
2320 /* Add only after the ready fence was reset, to guard against a
2321 * race with si_bind_XX_shader. */
2322 if (!sel->last_variant) {
2323 sel->first_variant = shader;
2324 sel->last_variant = shader;
2325 } else {
2326 sel->last_variant->next_variant = shader;
2327 sel->last_variant = shader;
2328 }
2329
2330 /* Use the default (unoptimized) shader for now. */
2331 memset(&key->opt, 0, sizeof(key->opt));
2332 mtx_unlock(&sel->mutex);
2333
2334 if (sscreen->options.sync_compile)
2335 util_queue_fence_wait(&shader->ready);
2336
2337 if (optimized_or_none)
2338 return -1;
2339 goto again;
2340 }
2341
2342 /* Reset the fence before adding to the variant list. */
2343 util_queue_fence_reset(&shader->ready);
2344
2345 if (!sel->last_variant) {
2346 sel->first_variant = shader;
2347 sel->last_variant = shader;
2348 } else {
2349 sel->last_variant->next_variant = shader;
2350 sel->last_variant = shader;
2351 }
2352
2353 mtx_unlock(&sel->mutex);
2354
2355 assert(!shader->is_optimized);
2356 si_build_shader_variant(shader, thread_index, false);
2357
2358 util_queue_fence_signal(&shader->ready);
2359
2360 if (!shader->compilation_failed)
2361 state->current = shader;
2362
2363 return shader->compilation_failed ? -1 : 0;
2364 }
2365
2366 static int si_shader_select(struct pipe_context *ctx,
2367 struct si_shader_ctx_state *state,
2368 union si_vgt_stages_key stages_key,
2369 struct si_compiler_ctx_state *compiler_state)
2370 {
2371 struct si_context *sctx = (struct si_context *)ctx;
2372 struct si_shader_key key;
2373
2374 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2375 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2376 &key, -1, false);
2377 }
2378
2379 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2380 bool streamout,
2381 struct si_shader_key *key)
2382 {
2383 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2384
2385 switch (info->processor) {
2386 case PIPE_SHADER_VERTEX:
2387 switch (next_shader) {
2388 case PIPE_SHADER_GEOMETRY:
2389 key->as_es = 1;
2390 break;
2391 case PIPE_SHADER_TESS_CTRL:
2392 case PIPE_SHADER_TESS_EVAL:
2393 key->as_ls = 1;
2394 break;
2395 default:
2396 /* If POSITION isn't written, it can only be a HW VS
2397 * if streamout is used. If streamout isn't used,
2398 * assume that it's a HW LS. (the next shader is TCS)
2399 * This heuristic is needed for separate shader objects.
2400 */
2401 if (!info->writes_position && !streamout)
2402 key->as_ls = 1;
2403 }
2404 break;
2405
2406 case PIPE_SHADER_TESS_EVAL:
2407 if (next_shader == PIPE_SHADER_GEOMETRY ||
2408 !info->writes_position)
2409 key->as_es = 1;
2410 break;
2411 }
2412 }
2413
2414 /**
2415 * Compile the main shader part or the monolithic shader as part of
2416 * si_shader_selector initialization. Since it can be done asynchronously,
2417 * there is no way to report compile failures to applications.
2418 */
2419 static void si_init_shader_selector_async(void *job, int thread_index)
2420 {
2421 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2422 struct si_screen *sscreen = sel->screen;
2423 struct ac_llvm_compiler *compiler;
2424 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2425
2426 assert(!debug->debug_message || debug->async);
2427 assert(thread_index >= 0);
2428 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2429 compiler = &sscreen->compiler[thread_index];
2430
2431 if (sel->nir)
2432 si_lower_nir(sel);
2433
2434 /* Compile the main shader part for use with a prolog and/or epilog.
2435 * If this fails, the driver will try to compile a monolithic shader
2436 * on demand.
2437 */
2438 if (!sscreen->use_monolithic_shaders) {
2439 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2440 void *ir_binary = NULL;
2441
2442 if (!shader) {
2443 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2444 return;
2445 }
2446
2447 /* We can leave the fence signaled because use of the default
2448 * main part is guarded by the selector's ready fence. */
2449 util_queue_fence_init(&shader->ready);
2450
2451 shader->selector = sel;
2452 shader->is_monolithic = false;
2453 si_parse_next_shader_property(&sel->info,
2454 sel->so.num_outputs != 0,
2455 &shader->key);
2456
2457 if (sscreen->use_ngg &&
2458 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2459 ((sel->type == PIPE_SHADER_VERTEX &&
2460 !shader->key.as_ls && !shader->key.as_es) ||
2461 sel->type == PIPE_SHADER_TESS_EVAL ||
2462 sel->type == PIPE_SHADER_GEOMETRY))
2463 shader->key.as_ngg = 1;
2464
2465 if (sel->tokens || sel->nir)
2466 ir_binary = si_get_ir_binary(sel, shader->key.as_ngg);
2467
2468 /* Try to load the shader from the shader cache. */
2469 mtx_lock(&sscreen->shader_cache_mutex);
2470
2471 if (ir_binary &&
2472 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2473 mtx_unlock(&sscreen->shader_cache_mutex);
2474 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2475 } else {
2476 mtx_unlock(&sscreen->shader_cache_mutex);
2477
2478 /* Compile the shader if it hasn't been loaded from the cache. */
2479 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2480 debug) != 0) {
2481 FREE(shader);
2482 FREE(ir_binary);
2483 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2484 return;
2485 }
2486
2487 if (ir_binary) {
2488 mtx_lock(&sscreen->shader_cache_mutex);
2489 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2490 FREE(ir_binary);
2491 mtx_unlock(&sscreen->shader_cache_mutex);
2492 }
2493 }
2494
2495 *si_get_main_shader_part(sel, &shader->key) = shader;
2496
2497 /* Unset "outputs_written" flags for outputs converted to
2498 * DEFAULT_VAL, so that later inter-shader optimizations don't
2499 * try to eliminate outputs that don't exist in the final
2500 * shader.
2501 *
2502 * This is only done if non-monolithic shaders are enabled.
2503 */
2504 if ((sel->type == PIPE_SHADER_VERTEX ||
2505 sel->type == PIPE_SHADER_TESS_EVAL) &&
2506 !shader->key.as_ls &&
2507 !shader->key.as_es) {
2508 unsigned i;
2509
2510 for (i = 0; i < sel->info.num_outputs; i++) {
2511 unsigned offset = shader->info.vs_output_param_offset[i];
2512
2513 if (offset <= AC_EXP_PARAM_OFFSET_31)
2514 continue;
2515
2516 unsigned name = sel->info.output_semantic_name[i];
2517 unsigned index = sel->info.output_semantic_index[i];
2518 unsigned id;
2519
2520 switch (name) {
2521 case TGSI_SEMANTIC_GENERIC:
2522 /* don't process indices the function can't handle */
2523 if (index >= SI_MAX_IO_GENERIC)
2524 break;
2525 /* fall through */
2526 default:
2527 id = si_shader_io_get_unique_index(name, index, true);
2528 sel->outputs_written_before_ps &= ~(1ull << id);
2529 break;
2530 case TGSI_SEMANTIC_POSITION: /* ignore these */
2531 case TGSI_SEMANTIC_PSIZE:
2532 case TGSI_SEMANTIC_CLIPVERTEX:
2533 case TGSI_SEMANTIC_EDGEFLAG:
2534 break;
2535 }
2536 }
2537 }
2538 }
2539
2540 /* The GS copy shader is always pre-compiled. */
2541 if (sel->type == PIPE_SHADER_GEOMETRY &&
2542 (!sscreen->use_ngg || sel->tess_turns_off_ngg)) {
2543 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2544 if (!sel->gs_copy_shader) {
2545 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2546 return;
2547 }
2548
2549 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2550 }
2551 }
2552
2553 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2554 struct util_queue_fence *ready_fence,
2555 struct si_compiler_ctx_state *compiler_ctx_state,
2556 void *job, util_queue_execute_func execute)
2557 {
2558 util_queue_fence_init(ready_fence);
2559
2560 struct util_async_debug_callback async_debug;
2561 bool debug =
2562 (sctx->debug.debug_message && !sctx->debug.async) ||
2563 sctx->is_debug ||
2564 si_can_dump_shader(sctx->screen, processor);
2565
2566 if (debug) {
2567 u_async_debug_init(&async_debug);
2568 compiler_ctx_state->debug = async_debug.base;
2569 }
2570
2571 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2572 ready_fence, execute, NULL);
2573
2574 if (debug) {
2575 util_queue_fence_wait(ready_fence);
2576 u_async_debug_drain(&async_debug, &sctx->debug);
2577 u_async_debug_cleanup(&async_debug);
2578 }
2579
2580 if (sctx->screen->options.sync_compile)
2581 util_queue_fence_wait(ready_fence);
2582 }
2583
2584 /* Return descriptor slot usage masks from the given shader info. */
2585 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2586 uint32_t *const_and_shader_buffers,
2587 uint64_t *samplers_and_images)
2588 {
2589 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2590
2591 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2592 num_constbufs = util_last_bit(info->const_buffers_declared);
2593 /* two 8-byte images share one 16-byte slot */
2594 num_images = align(util_last_bit(info->images_declared), 2);
2595 num_samplers = util_last_bit(info->samplers_declared);
2596
2597 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2598 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2599 *const_and_shader_buffers =
2600 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2601
2602 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2603 start = si_get_image_slot(num_images - 1) / 2;
2604 *samplers_and_images =
2605 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2606 }
2607
2608 static void *si_create_shader_selector(struct pipe_context *ctx,
2609 const struct pipe_shader_state *state)
2610 {
2611 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2612 struct si_context *sctx = (struct si_context*)ctx;
2613 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2614 int i;
2615
2616 if (!sel)
2617 return NULL;
2618
2619 pipe_reference_init(&sel->reference, 1);
2620 sel->screen = sscreen;
2621 sel->compiler_ctx_state.debug = sctx->debug;
2622 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2623
2624 sel->so = state->stream_output;
2625
2626 if (state->type == PIPE_SHADER_IR_TGSI &&
2627 !sscreen->options.enable_nir) {
2628 sel->tokens = tgsi_dup_tokens(state->tokens);
2629 if (!sel->tokens) {
2630 FREE(sel);
2631 return NULL;
2632 }
2633
2634 tgsi_scan_shader(state->tokens, &sel->info);
2635 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2636
2637 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2638 if (sel->info.uses_persp_opcode_interp_centroid)
2639 sel->info.uses_persp_centroid = true;
2640
2641 if (sel->info.uses_linear_opcode_interp_centroid)
2642 sel->info.uses_linear_centroid = true;
2643
2644 if (sel->info.uses_persp_opcode_interp_offset ||
2645 sel->info.uses_persp_opcode_interp_sample)
2646 sel->info.uses_persp_center = true;
2647
2648 if (sel->info.uses_linear_opcode_interp_offset ||
2649 sel->info.uses_linear_opcode_interp_sample)
2650 sel->info.uses_linear_center = true;
2651 } else {
2652 if (state->type == PIPE_SHADER_IR_TGSI) {
2653 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2654 } else {
2655 assert(state->type == PIPE_SHADER_IR_NIR);
2656 sel->nir = state->ir.nir;
2657 }
2658
2659 si_nir_lower_ps_inputs(sel->nir);
2660 si_nir_opts(sel->nir);
2661 si_nir_scan_shader(sel->nir, &sel->info);
2662 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2663 }
2664
2665 sel->type = sel->info.processor;
2666 p_atomic_inc(&sscreen->num_shaders_created);
2667 si_get_active_slot_masks(&sel->info,
2668 &sel->active_const_and_shader_buffers,
2669 &sel->active_samplers_and_images);
2670
2671 /* Record which streamout buffers are enabled. */
2672 for (i = 0; i < sel->so.num_outputs; i++) {
2673 sel->enabled_streamout_buffer_mask |=
2674 (1 << sel->so.output[i].output_buffer) <<
2675 (sel->so.output[i].stream * 4);
2676 }
2677
2678 /* The prolog is a no-op if there are no inputs. */
2679 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2680 sel->info.num_inputs &&
2681 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2682
2683 sel->force_correct_derivs_after_kill =
2684 sel->type == PIPE_SHADER_FRAGMENT &&
2685 sel->info.uses_derivatives &&
2686 sel->info.uses_kill &&
2687 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2688
2689 sel->prim_discard_cs_allowed =
2690 sel->type == PIPE_SHADER_VERTEX &&
2691 !sel->info.uses_bindless_images &&
2692 !sel->info.uses_bindless_samplers &&
2693 !sel->info.writes_memory &&
2694 !sel->info.writes_viewport_index &&
2695 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2696 !sel->so.num_outputs;
2697
2698 if (sel->type == PIPE_SHADER_VERTEX &&
2699 sel->info.writes_edgeflag) {
2700 if (sscreen->info.chip_class >= GFX10)
2701 sel->ngg_writes_edgeflag = true;
2702 else
2703 sel->pos_writes_edgeflag = true;
2704 }
2705
2706 switch (sel->type) {
2707 case PIPE_SHADER_GEOMETRY:
2708 sel->gs_output_prim =
2709 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2710
2711 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2712 sel->rast_prim = sel->gs_output_prim;
2713 if (util_rast_prim_is_triangles(sel->rast_prim))
2714 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2715
2716 sel->gs_max_out_vertices =
2717 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2718 sel->gs_num_invocations =
2719 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2720 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2721 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2722 sel->gs_max_out_vertices;
2723
2724 sel->max_gs_stream = 0;
2725 for (i = 0; i < sel->so.num_outputs; i++)
2726 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2727 sel->so.output[i].stream);
2728
2729 sel->gs_input_verts_per_prim =
2730 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2731
2732 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2733 sel->tess_turns_off_ngg =
2734 (sscreen->info.family == CHIP_NAVI10 ||
2735 sscreen->info.family == CHIP_NAVI12 ||
2736 sscreen->info.family == CHIP_NAVI14) &&
2737 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2738 break;
2739
2740 case PIPE_SHADER_TESS_CTRL:
2741 /* Always reserve space for these. */
2742 sel->patch_outputs_written |=
2743 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2744 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2745 /* fall through */
2746 case PIPE_SHADER_VERTEX:
2747 case PIPE_SHADER_TESS_EVAL:
2748 for (i = 0; i < sel->info.num_outputs; i++) {
2749 unsigned name = sel->info.output_semantic_name[i];
2750 unsigned index = sel->info.output_semantic_index[i];
2751
2752 switch (name) {
2753 case TGSI_SEMANTIC_TESSINNER:
2754 case TGSI_SEMANTIC_TESSOUTER:
2755 case TGSI_SEMANTIC_PATCH:
2756 sel->patch_outputs_written |=
2757 1ull << si_shader_io_get_unique_index_patch(name, index);
2758 break;
2759
2760 case TGSI_SEMANTIC_GENERIC:
2761 /* don't process indices the function can't handle */
2762 if (index >= SI_MAX_IO_GENERIC)
2763 break;
2764 /* fall through */
2765 default:
2766 sel->outputs_written |=
2767 1ull << si_shader_io_get_unique_index(name, index, false);
2768 sel->outputs_written_before_ps |=
2769 1ull << si_shader_io_get_unique_index(name, index, true);
2770 break;
2771 case TGSI_SEMANTIC_EDGEFLAG:
2772 break;
2773 }
2774 }
2775 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2776 sel->lshs_vertex_stride = sel->esgs_itemsize;
2777
2778 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2779 * will start on a different bank. (except for the maximum 32*16).
2780 */
2781 if (sel->lshs_vertex_stride < 32*16)
2782 sel->lshs_vertex_stride += 4;
2783
2784 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2785 * conflicts, i.e. each vertex will start at a different bank.
2786 */
2787 if (sctx->chip_class >= GFX9)
2788 sel->esgs_itemsize += 4;
2789
2790 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2791
2792 /* Only for TES: */
2793 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2794 sel->rast_prim = PIPE_PRIM_POINTS;
2795 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2796 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2797 else
2798 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2799 break;
2800
2801 case PIPE_SHADER_FRAGMENT:
2802 for (i = 0; i < sel->info.num_inputs; i++) {
2803 unsigned name = sel->info.input_semantic_name[i];
2804 unsigned index = sel->info.input_semantic_index[i];
2805
2806 switch (name) {
2807 case TGSI_SEMANTIC_GENERIC:
2808 /* don't process indices the function can't handle */
2809 if (index >= SI_MAX_IO_GENERIC)
2810 break;
2811 /* fall through */
2812 default:
2813 sel->inputs_read |=
2814 1ull << si_shader_io_get_unique_index(name, index, true);
2815 break;
2816 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2817 break;
2818 }
2819 }
2820
2821 for (i = 0; i < 8; i++)
2822 if (sel->info.colors_written & (1 << i))
2823 sel->colors_written_4bit |= 0xf << (4 * i);
2824
2825 for (i = 0; i < sel->info.num_inputs; i++) {
2826 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2827 int index = sel->info.input_semantic_index[i];
2828 sel->color_attr_index[index] = i;
2829 }
2830 }
2831 break;
2832 default:;
2833 }
2834
2835 /* PA_CL_VS_OUT_CNTL */
2836 bool misc_vec_ena =
2837 sel->info.writes_psize || sel->pos_writes_edgeflag ||
2838 sel->info.writes_layer || sel->info.writes_viewport_index;
2839 sel->pa_cl_vs_out_cntl =
2840 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2841 S_02881C_USE_VTX_EDGE_FLAG(sel->pos_writes_edgeflag) |
2842 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2843 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2844 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2845 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2846 sel->clipdist_mask = sel->info.writes_clipvertex ?
2847 SIX_BITS : sel->info.clipdist_writemask;
2848 sel->culldist_mask = sel->info.culldist_writemask <<
2849 sel->info.num_written_clipdistance;
2850
2851 /* DB_SHADER_CONTROL */
2852 sel->db_shader_control =
2853 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2854 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2855 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2856 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2857
2858 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2859 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2860 sel->db_shader_control |=
2861 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2862 break;
2863 case TGSI_FS_DEPTH_LAYOUT_LESS:
2864 sel->db_shader_control |=
2865 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2866 break;
2867 }
2868
2869 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2870 *
2871 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2872 * --|-----------|------------|------------|--------------------|-------------------|-------------
2873 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2874 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2875 * 2 | false | true | n/a | LateZ | 1 | 0
2876 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2877 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2878 *
2879 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2880 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2881 *
2882 * Don't use ReZ without profiling !!!
2883 *
2884 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2885 * shaders.
2886 */
2887 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2888 /* Cases 3, 4. */
2889 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2890 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2891 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2892 } else if (sel->info.writes_memory) {
2893 /* Case 2. */
2894 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2895 S_02880C_EXEC_ON_HIER_FAIL(1);
2896 } else {
2897 /* Case 1. */
2898 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2899 }
2900
2901 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2902 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2903
2904 (void) mtx_init(&sel->mutex, mtx_plain);
2905
2906 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2907 &sel->compiler_ctx_state, sel,
2908 si_init_shader_selector_async);
2909 return sel;
2910 }
2911
2912 static void si_update_streamout_state(struct si_context *sctx)
2913 {
2914 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2915
2916 if (!shader_with_so)
2917 return;
2918
2919 sctx->streamout.enabled_stream_buffers_mask =
2920 shader_with_so->enabled_streamout_buffer_mask;
2921 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2922 }
2923
2924 static void si_update_clip_regs(struct si_context *sctx,
2925 struct si_shader_selector *old_hw_vs,
2926 struct si_shader *old_hw_vs_variant,
2927 struct si_shader_selector *next_hw_vs,
2928 struct si_shader *next_hw_vs_variant)
2929 {
2930 if (next_hw_vs &&
2931 (!old_hw_vs ||
2932 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2933 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2934 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2935 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2936 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2937 !old_hw_vs_variant ||
2938 !next_hw_vs_variant ||
2939 old_hw_vs_variant->key.opt.clip_disable !=
2940 next_hw_vs_variant->key.opt.clip_disable))
2941 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2942 }
2943
2944 static void si_update_common_shader_state(struct si_context *sctx)
2945 {
2946 sctx->uses_bindless_samplers =
2947 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2948 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2949 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2950 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2951 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2952 sctx->uses_bindless_images =
2953 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2954 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2955 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2956 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2957 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2958 sctx->do_update_shaders = true;
2959 }
2960
2961 static bool si_update_ngg(struct si_context *sctx);
2962
2963 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2964 {
2965 struct si_context *sctx = (struct si_context *)ctx;
2966 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2967 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2968 struct si_shader_selector *sel = state;
2969
2970 if (sctx->vs_shader.cso == sel)
2971 return;
2972
2973 sctx->vs_shader.cso = sel;
2974 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2975 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
2976
2977 if (si_update_ngg(sctx))
2978 si_shader_change_notify(sctx);
2979
2980 si_update_common_shader_state(sctx);
2981 si_update_vs_viewport_state(sctx);
2982 si_set_active_descriptors_for_shader(sctx, sel);
2983 si_update_streamout_state(sctx);
2984 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2985 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2986 }
2987
2988 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2989 {
2990 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2991 (sctx->tes_shader.cso &&
2992 sctx->tes_shader.cso->info.uses_primid) ||
2993 (sctx->tcs_shader.cso &&
2994 sctx->tcs_shader.cso->info.uses_primid) ||
2995 (sctx->gs_shader.cso &&
2996 sctx->gs_shader.cso->info.uses_primid) ||
2997 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2998 sctx->ps_shader.cso->info.uses_primid);
2999 }
3000
3001 static bool si_update_ngg(struct si_context *sctx)
3002 {
3003 if (!sctx->screen->use_ngg) {
3004 assert(!sctx->ngg);
3005 return false;
3006 }
3007
3008 bool new_ngg = true;
3009
3010 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3011 sctx->gs_shader.cso->tess_turns_off_ngg) {
3012 new_ngg = false;
3013 } else if (!sctx->screen->use_ngg_streamout) {
3014 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3015
3016 if (last && last->so.num_outputs)
3017 new_ngg = false;
3018 }
3019
3020 if (new_ngg != sctx->ngg) {
3021 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3022 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3023 * pointers are set.
3024 */
3025 if ((sctx->family == CHIP_NAVI10 ||
3026 sctx->family == CHIP_NAVI12 ||
3027 sctx->family == CHIP_NAVI14) &&
3028 !new_ngg)
3029 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3030
3031 sctx->ngg = new_ngg;
3032 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3033 return true;
3034 }
3035 return false;
3036 }
3037
3038 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3039 {
3040 struct si_context *sctx = (struct si_context *)ctx;
3041 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3042 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3043 struct si_shader_selector *sel = state;
3044 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3045 bool ngg_changed;
3046
3047 if (sctx->gs_shader.cso == sel)
3048 return;
3049
3050 sctx->gs_shader.cso = sel;
3051 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3052 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3053
3054 si_update_common_shader_state(sctx);
3055 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3056
3057 ngg_changed = si_update_ngg(sctx);
3058 if (ngg_changed || enable_changed)
3059 si_shader_change_notify(sctx);
3060 if (enable_changed) {
3061 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3062 si_update_tess_uses_prim_id(sctx);
3063 }
3064 si_update_vs_viewport_state(sctx);
3065 si_set_active_descriptors_for_shader(sctx, sel);
3066 si_update_streamout_state(sctx);
3067 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3068 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3069 }
3070
3071 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3072 {
3073 struct si_context *sctx = (struct si_context *)ctx;
3074 struct si_shader_selector *sel = state;
3075 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3076
3077 if (sctx->tcs_shader.cso == sel)
3078 return;
3079
3080 sctx->tcs_shader.cso = sel;
3081 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3082 si_update_tess_uses_prim_id(sctx);
3083
3084 si_update_common_shader_state(sctx);
3085
3086 if (enable_changed)
3087 sctx->last_tcs = NULL; /* invalidate derived tess state */
3088
3089 si_set_active_descriptors_for_shader(sctx, sel);
3090 }
3091
3092 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3093 {
3094 struct si_context *sctx = (struct si_context *)ctx;
3095 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3096 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3097 struct si_shader_selector *sel = state;
3098 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3099
3100 if (sctx->tes_shader.cso == sel)
3101 return;
3102
3103 sctx->tes_shader.cso = sel;
3104 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3105 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3106 si_update_tess_uses_prim_id(sctx);
3107
3108 si_update_common_shader_state(sctx);
3109 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3110
3111 bool ngg_changed = si_update_ngg(sctx);
3112 if (ngg_changed || enable_changed)
3113 si_shader_change_notify(sctx);
3114 if (enable_changed)
3115 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3116 si_update_vs_viewport_state(sctx);
3117 si_set_active_descriptors_for_shader(sctx, sel);
3118 si_update_streamout_state(sctx);
3119 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3120 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3121 }
3122
3123 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3124 {
3125 struct si_context *sctx = (struct si_context *)ctx;
3126 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3127 struct si_shader_selector *sel = state;
3128
3129 /* skip if supplied shader is one already in use */
3130 if (old_sel == sel)
3131 return;
3132
3133 sctx->ps_shader.cso = sel;
3134 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3135
3136 si_update_common_shader_state(sctx);
3137 if (sel) {
3138 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3139 si_update_tess_uses_prim_id(sctx);
3140
3141 if (!old_sel ||
3142 old_sel->info.colors_written != sel->info.colors_written)
3143 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3144
3145 if (sctx->screen->has_out_of_order_rast &&
3146 (!old_sel ||
3147 old_sel->info.writes_memory != sel->info.writes_memory ||
3148 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3149 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3150 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3151 }
3152 si_set_active_descriptors_for_shader(sctx, sel);
3153 si_update_ps_colorbuf0_slot(sctx);
3154 }
3155
3156 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3157 {
3158 if (shader->is_optimized) {
3159 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3160 &shader->ready);
3161 }
3162
3163 util_queue_fence_destroy(&shader->ready);
3164
3165 if (shader->pm4) {
3166 /* If destroyed shaders were not unbound, the next compiled
3167 * shader variant could get the same pointer address and so
3168 * binding it to the same shader stage would be considered
3169 * a no-op, causing random behavior.
3170 */
3171 switch (shader->selector->type) {
3172 case PIPE_SHADER_VERTEX:
3173 if (shader->key.as_ls) {
3174 assert(sctx->chip_class <= GFX8);
3175 si_pm4_delete_state(sctx, ls, shader->pm4);
3176 } else if (shader->key.as_es) {
3177 assert(sctx->chip_class <= GFX8);
3178 si_pm4_delete_state(sctx, es, shader->pm4);
3179 } else if (shader->key.as_ngg) {
3180 si_pm4_delete_state(sctx, gs, shader->pm4);
3181 } else {
3182 si_pm4_delete_state(sctx, vs, shader->pm4);
3183 }
3184 break;
3185 case PIPE_SHADER_TESS_CTRL:
3186 si_pm4_delete_state(sctx, hs, shader->pm4);
3187 break;
3188 case PIPE_SHADER_TESS_EVAL:
3189 if (shader->key.as_es) {
3190 assert(sctx->chip_class <= GFX8);
3191 si_pm4_delete_state(sctx, es, shader->pm4);
3192 } else if (shader->key.as_ngg) {
3193 si_pm4_delete_state(sctx, gs, shader->pm4);
3194 } else {
3195 si_pm4_delete_state(sctx, vs, shader->pm4);
3196 }
3197 break;
3198 case PIPE_SHADER_GEOMETRY:
3199 if (shader->is_gs_copy_shader)
3200 si_pm4_delete_state(sctx, vs, shader->pm4);
3201 else
3202 si_pm4_delete_state(sctx, gs, shader->pm4);
3203 break;
3204 case PIPE_SHADER_FRAGMENT:
3205 si_pm4_delete_state(sctx, ps, shader->pm4);
3206 break;
3207 default:;
3208 }
3209 }
3210
3211 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3212 si_shader_destroy(shader);
3213 free(shader);
3214 }
3215
3216 void si_destroy_shader_selector(struct si_context *sctx,
3217 struct si_shader_selector *sel)
3218 {
3219 struct si_shader *p = sel->first_variant, *c;
3220 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3221 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3222 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3223 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3224 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3225 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3226 };
3227
3228 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3229
3230 if (current_shader[sel->type]->cso == sel) {
3231 current_shader[sel->type]->cso = NULL;
3232 current_shader[sel->type]->current = NULL;
3233 }
3234
3235 while (p) {
3236 c = p->next_variant;
3237 si_delete_shader(sctx, p);
3238 p = c;
3239 }
3240
3241 if (sel->main_shader_part)
3242 si_delete_shader(sctx, sel->main_shader_part);
3243 if (sel->main_shader_part_ls)
3244 si_delete_shader(sctx, sel->main_shader_part_ls);
3245 if (sel->main_shader_part_es)
3246 si_delete_shader(sctx, sel->main_shader_part_es);
3247 if (sel->main_shader_part_ngg)
3248 si_delete_shader(sctx, sel->main_shader_part_ngg);
3249 if (sel->gs_copy_shader)
3250 si_delete_shader(sctx, sel->gs_copy_shader);
3251
3252 util_queue_fence_destroy(&sel->ready);
3253 mtx_destroy(&sel->mutex);
3254 free(sel->tokens);
3255 ralloc_free(sel->nir);
3256 free(sel);
3257 }
3258
3259 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3260 {
3261 struct si_context *sctx = (struct si_context *)ctx;
3262 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3263
3264 si_shader_selector_reference(sctx, &sel, NULL);
3265 }
3266
3267 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3268 struct si_shader *vs, unsigned name,
3269 unsigned index, unsigned interpolate)
3270 {
3271 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3272 unsigned j, offset, ps_input_cntl = 0;
3273
3274 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3275 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3276 name == TGSI_SEMANTIC_PRIMID)
3277 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3278
3279 if (name == TGSI_SEMANTIC_PCOORD ||
3280 (name == TGSI_SEMANTIC_TEXCOORD &&
3281 sctx->sprite_coord_enable & (1 << index))) {
3282 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3283 }
3284
3285 for (j = 0; j < vsinfo->num_outputs; j++) {
3286 if (name == vsinfo->output_semantic_name[j] &&
3287 index == vsinfo->output_semantic_index[j]) {
3288 offset = vs->info.vs_output_param_offset[j];
3289
3290 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3291 /* The input is loaded from parameter memory. */
3292 ps_input_cntl |= S_028644_OFFSET(offset);
3293 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3294 if (offset == AC_EXP_PARAM_UNDEFINED) {
3295 /* This can happen with depth-only rendering. */
3296 offset = 0;
3297 } else {
3298 /* The input is a DEFAULT_VAL constant. */
3299 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3300 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3301 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3302 }
3303
3304 ps_input_cntl = S_028644_OFFSET(0x20) |
3305 S_028644_DEFAULT_VAL(offset);
3306 }
3307 break;
3308 }
3309 }
3310
3311 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3312 /* PrimID is written after the last output when HW VS is used. */
3313 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3314 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3315 /* No corresponding output found, load defaults into input.
3316 * Don't set any other bits.
3317 * (FLAT_SHADE=1 completely changes behavior) */
3318 ps_input_cntl = S_028644_OFFSET(0x20);
3319 /* D3D 9 behaviour. GL is undefined */
3320 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3321 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3322 }
3323 return ps_input_cntl;
3324 }
3325
3326 static void si_emit_spi_map(struct si_context *sctx)
3327 {
3328 struct si_shader *ps = sctx->ps_shader.current;
3329 struct si_shader *vs = si_get_vs_state(sctx);
3330 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3331 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3332 unsigned spi_ps_input_cntl[32];
3333
3334 if (!ps || !ps->selector->info.num_inputs)
3335 return;
3336
3337 num_interp = si_get_ps_num_interp(ps);
3338 assert(num_interp > 0);
3339
3340 for (i = 0; i < psinfo->num_inputs; i++) {
3341 unsigned name = psinfo->input_semantic_name[i];
3342 unsigned index = psinfo->input_semantic_index[i];
3343 unsigned interpolate = psinfo->input_interpolate[i];
3344
3345 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3346 index, interpolate);
3347
3348 if (name == TGSI_SEMANTIC_COLOR) {
3349 assert(index < ARRAY_SIZE(bcol_interp));
3350 bcol_interp[index] = interpolate;
3351 }
3352 }
3353
3354 if (ps->key.part.ps.prolog.color_two_side) {
3355 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3356
3357 for (i = 0; i < 2; i++) {
3358 if (!(psinfo->colors_read & (0xf << (i * 4))))
3359 continue;
3360
3361 spi_ps_input_cntl[num_written++] =
3362 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3363
3364 }
3365 }
3366 assert(num_interp == num_written);
3367
3368 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3369 /* Dota 2: Only ~16% of SPI map updates set different values. */
3370 /* Talos: Only ~9% of SPI map updates set different values. */
3371 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3372 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3373 spi_ps_input_cntl,
3374 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3375
3376 if (initial_cdw != sctx->gfx_cs->current.cdw)
3377 sctx->context_roll = true;
3378 }
3379
3380 /**
3381 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3382 */
3383 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3384 {
3385 if (sctx->init_config_has_vgt_flush)
3386 return;
3387
3388 /* Done by Vulkan before VGT_FLUSH. */
3389 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3390 si_pm4_cmd_add(sctx->init_config,
3391 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3392 si_pm4_cmd_end(sctx->init_config, false);
3393
3394 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3395 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3396 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3397 si_pm4_cmd_end(sctx->init_config, false);
3398 sctx->init_config_has_vgt_flush = true;
3399 }
3400
3401 /* Initialize state related to ESGS / GSVS ring buffers */
3402 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3403 {
3404 struct si_shader_selector *es =
3405 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3406 struct si_shader_selector *gs = sctx->gs_shader.cso;
3407 struct si_pm4_state *pm4;
3408
3409 /* Chip constants. */
3410 unsigned num_se = sctx->screen->info.max_se;
3411 unsigned wave_size = 64;
3412 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3413 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3414 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3415 */
3416 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3417 unsigned alignment = 256 * num_se;
3418 /* The maximum size is 63.999 MB per SE. */
3419 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3420
3421 /* Calculate the minimum size. */
3422 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3423 wave_size, alignment);
3424
3425 /* These are recommended sizes, not minimum sizes. */
3426 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3427 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3428 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3429 gs->max_gsvs_emit_size;
3430
3431 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3432 esgs_ring_size = align(esgs_ring_size, alignment);
3433 gsvs_ring_size = align(gsvs_ring_size, alignment);
3434
3435 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3436 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3437
3438 /* Some rings don't have to be allocated if shaders don't use them.
3439 * (e.g. no varyings between ES and GS or GS and VS)
3440 *
3441 * GFX9 doesn't have the ESGS ring.
3442 */
3443 bool update_esgs = sctx->chip_class <= GFX8 &&
3444 esgs_ring_size &&
3445 (!sctx->esgs_ring ||
3446 sctx->esgs_ring->width0 < esgs_ring_size);
3447 bool update_gsvs = gsvs_ring_size &&
3448 (!sctx->gsvs_ring ||
3449 sctx->gsvs_ring->width0 < gsvs_ring_size);
3450
3451 if (!update_esgs && !update_gsvs)
3452 return true;
3453
3454 if (update_esgs) {
3455 pipe_resource_reference(&sctx->esgs_ring, NULL);
3456 sctx->esgs_ring =
3457 pipe_aligned_buffer_create(sctx->b.screen,
3458 SI_RESOURCE_FLAG_UNMAPPABLE,
3459 PIPE_USAGE_DEFAULT,
3460 esgs_ring_size, alignment);
3461 if (!sctx->esgs_ring)
3462 return false;
3463 }
3464
3465 if (update_gsvs) {
3466 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3467 sctx->gsvs_ring =
3468 pipe_aligned_buffer_create(sctx->b.screen,
3469 SI_RESOURCE_FLAG_UNMAPPABLE,
3470 PIPE_USAGE_DEFAULT,
3471 gsvs_ring_size, alignment);
3472 if (!sctx->gsvs_ring)
3473 return false;
3474 }
3475
3476 /* Create the "init_config_gs_rings" state. */
3477 pm4 = CALLOC_STRUCT(si_pm4_state);
3478 if (!pm4)
3479 return false;
3480
3481 if (sctx->chip_class >= GFX7) {
3482 if (sctx->esgs_ring) {
3483 assert(sctx->chip_class <= GFX8);
3484 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3485 sctx->esgs_ring->width0 / 256);
3486 }
3487 if (sctx->gsvs_ring)
3488 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3489 sctx->gsvs_ring->width0 / 256);
3490 } else {
3491 if (sctx->esgs_ring)
3492 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3493 sctx->esgs_ring->width0 / 256);
3494 if (sctx->gsvs_ring)
3495 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3496 sctx->gsvs_ring->width0 / 256);
3497 }
3498
3499 /* Set the state. */
3500 if (sctx->init_config_gs_rings)
3501 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3502 sctx->init_config_gs_rings = pm4;
3503
3504 if (!sctx->init_config_has_vgt_flush) {
3505 si_init_config_add_vgt_flush(sctx);
3506 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3507 }
3508
3509 /* Flush the context to re-emit both init_config states. */
3510 sctx->initial_gfx_cs_size = 0; /* force flush */
3511 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3512
3513 /* Set ring bindings. */
3514 if (sctx->esgs_ring) {
3515 assert(sctx->chip_class <= GFX8);
3516 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3517 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3518 true, true, 4, 64, 0);
3519 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3520 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3521 false, false, 0, 0, 0);
3522 }
3523 if (sctx->gsvs_ring) {
3524 si_set_ring_buffer(sctx, SI_RING_GSVS,
3525 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3526 false, false, 0, 0, 0);
3527 }
3528
3529 return true;
3530 }
3531
3532 static void si_shader_lock(struct si_shader *shader)
3533 {
3534 mtx_lock(&shader->selector->mutex);
3535 if (shader->previous_stage_sel) {
3536 assert(shader->previous_stage_sel != shader->selector);
3537 mtx_lock(&shader->previous_stage_sel->mutex);
3538 }
3539 }
3540
3541 static void si_shader_unlock(struct si_shader *shader)
3542 {
3543 if (shader->previous_stage_sel)
3544 mtx_unlock(&shader->previous_stage_sel->mutex);
3545 mtx_unlock(&shader->selector->mutex);
3546 }
3547
3548 /**
3549 * @returns 1 if \p sel has been updated to use a new scratch buffer
3550 * 0 if not
3551 * < 0 if there was a failure
3552 */
3553 static int si_update_scratch_buffer(struct si_context *sctx,
3554 struct si_shader *shader)
3555 {
3556 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3557
3558 if (!shader)
3559 return 0;
3560
3561 /* This shader doesn't need a scratch buffer */
3562 if (shader->config.scratch_bytes_per_wave == 0)
3563 return 0;
3564
3565 /* Prevent race conditions when updating:
3566 * - si_shader::scratch_bo
3567 * - si_shader::binary::code
3568 * - si_shader::previous_stage::binary::code.
3569 */
3570 si_shader_lock(shader);
3571
3572 /* This shader is already configured to use the current
3573 * scratch buffer. */
3574 if (shader->scratch_bo == sctx->scratch_buffer) {
3575 si_shader_unlock(shader);
3576 return 0;
3577 }
3578
3579 assert(sctx->scratch_buffer);
3580
3581 /* Replace the shader bo with a new bo that has the relocs applied. */
3582 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3583 si_shader_unlock(shader);
3584 return -1;
3585 }
3586
3587 /* Update the shader state to use the new shader bo. */
3588 si_shader_init_pm4_state(sctx->screen, shader);
3589
3590 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3591
3592 si_shader_unlock(shader);
3593 return 1;
3594 }
3595
3596 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3597 {
3598 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3599 }
3600
3601 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3602 {
3603 return shader ? shader->config.scratch_bytes_per_wave : 0;
3604 }
3605
3606 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3607 {
3608 if (!sctx->tes_shader.cso)
3609 return NULL; /* tessellation disabled */
3610
3611 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3612 sctx->fixed_func_tcs_shader.current;
3613 }
3614
3615 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3616 {
3617 unsigned bytes = 0;
3618
3619 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3620 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3621 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3622 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3623
3624 if (sctx->tes_shader.cso) {
3625 struct si_shader *tcs = si_get_tcs_current(sctx);
3626
3627 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3628 }
3629 return bytes;
3630 }
3631
3632 static bool si_update_scratch_relocs(struct si_context *sctx)
3633 {
3634 struct si_shader *tcs = si_get_tcs_current(sctx);
3635 int r;
3636
3637 /* Update the shaders, so that they are using the latest scratch.
3638 * The scratch buffer may have been changed since these shaders were
3639 * last used, so we still need to try to update them, even if they
3640 * require scratch buffers smaller than the current size.
3641 */
3642 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3643 if (r < 0)
3644 return false;
3645 if (r == 1)
3646 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3647
3648 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3649 if (r < 0)
3650 return false;
3651 if (r == 1)
3652 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3653
3654 r = si_update_scratch_buffer(sctx, tcs);
3655 if (r < 0)
3656 return false;
3657 if (r == 1)
3658 si_pm4_bind_state(sctx, hs, tcs->pm4);
3659
3660 /* VS can be bound as LS, ES, or VS. */
3661 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3662 if (r < 0)
3663 return false;
3664 if (r == 1) {
3665 if (sctx->vs_shader.current->key.as_ls)
3666 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3667 else if (sctx->vs_shader.current->key.as_es)
3668 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3669 else if (sctx->vs_shader.current->key.as_ngg)
3670 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3671 else
3672 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3673 }
3674
3675 /* TES can be bound as ES or VS. */
3676 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3677 if (r < 0)
3678 return false;
3679 if (r == 1) {
3680 if (sctx->tes_shader.current->key.as_es)
3681 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3682 else if (sctx->tes_shader.current->key.as_ngg)
3683 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3684 else
3685 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3686 }
3687
3688 return true;
3689 }
3690
3691 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3692 {
3693 unsigned current_scratch_buffer_size =
3694 si_get_current_scratch_buffer_size(sctx);
3695 unsigned scratch_bytes_per_wave =
3696 si_get_max_scratch_bytes_per_wave(sctx);
3697 unsigned scratch_needed_size = scratch_bytes_per_wave *
3698 sctx->scratch_waves;
3699 unsigned spi_tmpring_size;
3700
3701 if (scratch_needed_size > 0) {
3702 if (scratch_needed_size > current_scratch_buffer_size) {
3703 /* Create a bigger scratch buffer */
3704 si_resource_reference(&sctx->scratch_buffer, NULL);
3705
3706 sctx->scratch_buffer =
3707 si_aligned_buffer_create(&sctx->screen->b,
3708 SI_RESOURCE_FLAG_UNMAPPABLE,
3709 PIPE_USAGE_DEFAULT,
3710 scratch_needed_size, 256);
3711 if (!sctx->scratch_buffer)
3712 return false;
3713
3714 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3715 si_context_add_resource_size(sctx,
3716 &sctx->scratch_buffer->b.b);
3717 }
3718
3719 if (!si_update_scratch_relocs(sctx))
3720 return false;
3721 }
3722
3723 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3724 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3725 "scratch size should already be aligned correctly.");
3726
3727 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3728 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3729 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3730 sctx->spi_tmpring_size = spi_tmpring_size;
3731 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3732 }
3733 return true;
3734 }
3735
3736 static void si_init_tess_factor_ring(struct si_context *sctx)
3737 {
3738 assert(!sctx->tess_rings);
3739 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3740
3741 /* The address must be aligned to 2^19, because the shader only
3742 * receives the high 13 bits.
3743 */
3744 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3745 SI_RESOURCE_FLAG_32BIT,
3746 PIPE_USAGE_DEFAULT,
3747 sctx->screen->tess_offchip_ring_size +
3748 sctx->screen->tess_factor_ring_size,
3749 1 << 19);
3750 if (!sctx->tess_rings)
3751 return;
3752
3753 si_init_config_add_vgt_flush(sctx);
3754
3755 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3756 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3757
3758 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3759 sctx->screen->tess_offchip_ring_size;
3760
3761 /* Append these registers to the init config state. */
3762 if (sctx->chip_class >= GFX7) {
3763 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3764 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3765 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3766 factor_va >> 8);
3767 if (sctx->chip_class >= GFX10)
3768 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3769 S_030984_BASE_HI(factor_va >> 40));
3770 else if (sctx->chip_class == GFX9)
3771 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3772 S_030944_BASE_HI(factor_va >> 40));
3773 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3774 sctx->screen->vgt_hs_offchip_param);
3775 } else {
3776 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3777 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3778 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3779 factor_va >> 8);
3780 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3781 sctx->screen->vgt_hs_offchip_param);
3782 }
3783
3784 /* Flush the context to re-emit the init_config state.
3785 * This is done only once in a lifetime of a context.
3786 */
3787 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3788 sctx->initial_gfx_cs_size = 0; /* force flush */
3789 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3790 }
3791
3792 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3793 union si_vgt_stages_key key)
3794 {
3795 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3796 uint32_t stages = 0;
3797
3798 if (key.u.tess) {
3799 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3800 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3801
3802 if (key.u.gs)
3803 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3804 S_028B54_GS_EN(1);
3805 else if (key.u.ngg)
3806 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3807 else
3808 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3809 } else if (key.u.gs) {
3810 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3811 S_028B54_GS_EN(1);
3812 } else if (key.u.ngg) {
3813 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3814 }
3815
3816 if (key.u.ngg) {
3817 stages |= S_028B54_PRIMGEN_EN(1);
3818 if (key.u.streamout)
3819 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3820 } else if (key.u.gs)
3821 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3822
3823 if (screen->info.chip_class >= GFX9)
3824 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3825
3826 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3827 stages |= S_028B54_HS_W32_EN(1) |
3828 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3829 S_028B54_VS_W32_EN(1);
3830 }
3831
3832 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3833 return pm4;
3834 }
3835
3836 static void si_update_vgt_shader_config(struct si_context *sctx,
3837 union si_vgt_stages_key key)
3838 {
3839 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3840
3841 if (unlikely(!*pm4))
3842 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3843 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3844 }
3845
3846 bool si_update_shaders(struct si_context *sctx)
3847 {
3848 struct pipe_context *ctx = (struct pipe_context*)sctx;
3849 struct si_compiler_ctx_state compiler_state;
3850 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3851 struct si_shader *old_vs = si_get_vs_state(sctx);
3852 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3853 struct si_shader *old_ps = sctx->ps_shader.current;
3854 union si_vgt_stages_key key;
3855 unsigned old_spi_shader_col_format =
3856 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3857 int r;
3858
3859 compiler_state.compiler = &sctx->compiler;
3860 compiler_state.debug = sctx->debug;
3861 compiler_state.is_debug_context = sctx->is_debug;
3862
3863 key.index = 0;
3864
3865 if (sctx->tes_shader.cso)
3866 key.u.tess = 1;
3867 if (sctx->gs_shader.cso)
3868 key.u.gs = 1;
3869
3870 if (sctx->ngg) {
3871 key.u.ngg = 1;
3872 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3873 }
3874
3875 /* Update TCS and TES. */
3876 if (sctx->tes_shader.cso) {
3877 if (!sctx->tess_rings) {
3878 si_init_tess_factor_ring(sctx);
3879 if (!sctx->tess_rings)
3880 return false;
3881 }
3882
3883 if (sctx->tcs_shader.cso) {
3884 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3885 &compiler_state);
3886 if (r)
3887 return false;
3888 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3889 } else {
3890 if (!sctx->fixed_func_tcs_shader.cso) {
3891 sctx->fixed_func_tcs_shader.cso =
3892 si_create_fixed_func_tcs(sctx);
3893 if (!sctx->fixed_func_tcs_shader.cso)
3894 return false;
3895 }
3896
3897 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3898 key, &compiler_state);
3899 if (r)
3900 return false;
3901 si_pm4_bind_state(sctx, hs,
3902 sctx->fixed_func_tcs_shader.current->pm4);
3903 }
3904
3905 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3906 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3907 if (r)
3908 return false;
3909
3910 if (sctx->gs_shader.cso) {
3911 /* TES as ES */
3912 assert(sctx->chip_class <= GFX8);
3913 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3914 } else if (key.u.ngg) {
3915 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3916 } else {
3917 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3918 }
3919 }
3920 } else {
3921 if (sctx->chip_class <= GFX8)
3922 si_pm4_bind_state(sctx, ls, NULL);
3923 si_pm4_bind_state(sctx, hs, NULL);
3924 }
3925
3926 /* Update GS. */
3927 if (sctx->gs_shader.cso) {
3928 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3929 if (r)
3930 return false;
3931 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3932 if (!key.u.ngg) {
3933 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3934
3935 if (!si_update_gs_ring_buffers(sctx))
3936 return false;
3937 } else {
3938 si_pm4_bind_state(sctx, vs, NULL);
3939 }
3940 } else {
3941 if (!key.u.ngg) {
3942 si_pm4_bind_state(sctx, gs, NULL);
3943 if (sctx->chip_class <= GFX8)
3944 si_pm4_bind_state(sctx, es, NULL);
3945 }
3946 }
3947
3948 /* Update VS. */
3949 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3950 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3951 if (r)
3952 return false;
3953
3954 if (!key.u.tess && !key.u.gs) {
3955 if (key.u.ngg) {
3956 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3957 si_pm4_bind_state(sctx, vs, NULL);
3958 } else {
3959 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3960 }
3961 } else if (sctx->tes_shader.cso) {
3962 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3963 } else {
3964 assert(sctx->gs_shader.cso);
3965 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3966 }
3967 }
3968
3969 si_update_vgt_shader_config(sctx, key);
3970
3971 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3972 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3973
3974 if (sctx->ps_shader.cso) {
3975 unsigned db_shader_control;
3976
3977 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3978 if (r)
3979 return false;
3980 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3981
3982 db_shader_control =
3983 sctx->ps_shader.cso->db_shader_control |
3984 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3985
3986 if (si_pm4_state_changed(sctx, ps) ||
3987 si_pm4_state_changed(sctx, vs) ||
3988 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3989 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3990 sctx->flatshade != rs->flatshade) {
3991 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3992 sctx->flatshade = rs->flatshade;
3993 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3994 }
3995
3996 if (sctx->screen->info.rbplus_allowed &&
3997 si_pm4_state_changed(sctx, ps) &&
3998 (!old_ps ||
3999 old_spi_shader_col_format !=
4000 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4001 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4002
4003 if (sctx->ps_db_shader_control != db_shader_control) {
4004 sctx->ps_db_shader_control = db_shader_control;
4005 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4006 if (sctx->screen->dpbb_allowed)
4007 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4008 }
4009
4010 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4011 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4012 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4013
4014 if (sctx->chip_class == GFX6)
4015 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4016
4017 if (sctx->framebuffer.nr_samples <= 1)
4018 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4019 }
4020 }
4021
4022 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4023 si_pm4_state_enabled_and_changed(sctx, hs) ||
4024 si_pm4_state_enabled_and_changed(sctx, es) ||
4025 si_pm4_state_enabled_and_changed(sctx, gs) ||
4026 si_pm4_state_enabled_and_changed(sctx, vs) ||
4027 si_pm4_state_enabled_and_changed(sctx, ps)) {
4028 if (!si_update_spi_tmpring_size(sctx))
4029 return false;
4030 }
4031
4032 if (sctx->chip_class >= GFX7) {
4033 if (si_pm4_state_enabled_and_changed(sctx, ls))
4034 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4035 else if (!sctx->queued.named.ls)
4036 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4037
4038 if (si_pm4_state_enabled_and_changed(sctx, hs))
4039 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4040 else if (!sctx->queued.named.hs)
4041 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4042
4043 if (si_pm4_state_enabled_and_changed(sctx, es))
4044 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4045 else if (!sctx->queued.named.es)
4046 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4047
4048 if (si_pm4_state_enabled_and_changed(sctx, gs))
4049 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4050 else if (!sctx->queued.named.gs)
4051 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4052
4053 if (si_pm4_state_enabled_and_changed(sctx, vs))
4054 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4055 else if (!sctx->queued.named.vs)
4056 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4057
4058 if (si_pm4_state_enabled_and_changed(sctx, ps))
4059 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4060 else if (!sctx->queued.named.ps)
4061 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4062 }
4063
4064 sctx->do_update_shaders = false;
4065 return true;
4066 }
4067
4068 static void si_emit_scratch_state(struct si_context *sctx)
4069 {
4070 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4071
4072 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4073 sctx->spi_tmpring_size);
4074
4075 if (sctx->scratch_buffer) {
4076 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4077 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4078 RADEON_PRIO_SCRATCH_BUFFER);
4079 }
4080 }
4081
4082 void si_init_shader_functions(struct si_context *sctx)
4083 {
4084 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4085 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4086
4087 sctx->b.create_vs_state = si_create_shader_selector;
4088 sctx->b.create_tcs_state = si_create_shader_selector;
4089 sctx->b.create_tes_state = si_create_shader_selector;
4090 sctx->b.create_gs_state = si_create_shader_selector;
4091 sctx->b.create_fs_state = si_create_shader_selector;
4092
4093 sctx->b.bind_vs_state = si_bind_vs_shader;
4094 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4095 sctx->b.bind_tes_state = si_bind_tes_shader;
4096 sctx->b.bind_gs_state = si_bind_gs_shader;
4097 sctx->b.bind_fs_state = si_bind_ps_shader;
4098
4099 sctx->b.delete_vs_state = si_delete_shader_selector;
4100 sctx->b.delete_tcs_state = si_delete_shader_selector;
4101 sctx->b.delete_tes_state = si_delete_shader_selector;
4102 sctx->b.delete_gs_state = si_delete_shader_selector;
4103 sctx->b.delete_fs_state = si_delete_shader_selector;
4104 }