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radeonsi: lower IO intrinsics - complete rewrite of input/output scanning
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "ac_exp_param.h"
26 #include "ac_shader_util.h"
27 #include "compiler/nir/nir_serialize.h"
28 #include "nir/tgsi_to_nir.h"
29 #include "si_build_pm4.h"
30 #include "sid.h"
31 #include "util/crc32.h"
32 #include "util/disk_cache.h"
33 #include "util/hash_table.h"
34 #include "util/mesa-sha1.h"
35 #include "util/u_async_debug.h"
36 #include "util/u_memory.h"
37 #include "util/u_prim.h"
38
39 /* SHADER_CACHE */
40
41 /**
42 * Return the IR key for the shader cache.
43 */
44 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
45 unsigned char ir_sha1_cache_key[20])
46 {
47 struct blob blob = {};
48 unsigned ir_size;
49 void *ir_binary;
50
51 if (sel->nir_binary) {
52 ir_binary = sel->nir_binary;
53 ir_size = sel->nir_size;
54 } else {
55 assert(sel->nir);
56
57 blob_init(&blob);
58 nir_serialize(&blob, sel->nir, true);
59 ir_binary = blob.data;
60 ir_size = blob.size;
61 }
62
63 /* These settings affect the compilation, but they are not derived
64 * from the input shader IR.
65 */
66 unsigned shader_variant_flags = 0;
67
68 if (ngg)
69 shader_variant_flags |= 1 << 0;
70 if (sel->nir)
71 shader_variant_flags |= 1 << 1;
72 if (si_get_wave_size(sel->screen, sel->type, ngg, es, false, false) == 32)
73 shader_variant_flags |= 1 << 2;
74 if (sel->type == PIPE_SHADER_FRAGMENT && sel->info.uses_derivatives && sel->info.uses_kill &&
75 sel->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL))
76 shader_variant_flags |= 1 << 3;
77
78 /* This varies depending on whether compute-based culling is enabled. */
79 shader_variant_flags |= sel->screen->num_vbos_in_user_sgprs << 4;
80
81 struct mesa_sha1 ctx;
82 _mesa_sha1_init(&ctx);
83 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
84 _mesa_sha1_update(&ctx, ir_binary, ir_size);
85 if (sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_TESS_EVAL ||
86 sel->type == PIPE_SHADER_GEOMETRY)
87 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
88 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
89
90 if (ir_binary == blob.data)
91 blob_finish(&blob);
92 }
93
94 /** Copy "data" to "ptr" and return the next dword following copied data. */
95 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
96 {
97 /* data may be NULL if size == 0 */
98 if (size)
99 memcpy(ptr, data, size);
100 ptr += DIV_ROUND_UP(size, 4);
101 return ptr;
102 }
103
104 /** Read data from "ptr". Return the next dword following the data. */
105 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
106 {
107 memcpy(data, ptr, size);
108 ptr += DIV_ROUND_UP(size, 4);
109 return ptr;
110 }
111
112 /**
113 * Write the size as uint followed by the data. Return the next dword
114 * following the copied data.
115 */
116 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
117 {
118 *ptr++ = size;
119 return write_data(ptr, data, size);
120 }
121
122 /**
123 * Read the size as uint followed by the data. Return both via parameters.
124 * Return the next dword following the data.
125 */
126 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
127 {
128 *size = *ptr++;
129 assert(*data == NULL);
130 if (!*size)
131 return ptr;
132 *data = malloc(*size);
133 return read_data(ptr, *data, *size);
134 }
135
136 /**
137 * Return the shader binary in a buffer. The first 4 bytes contain its size
138 * as integer.
139 */
140 static void *si_get_shader_binary(struct si_shader *shader)
141 {
142 /* There is always a size of data followed by the data itself. */
143 unsigned llvm_ir_size =
144 shader->binary.llvm_ir_string ? strlen(shader->binary.llvm_ir_string) + 1 : 0;
145
146 /* Refuse to allocate overly large buffers and guard against integer
147 * overflow. */
148 if (shader->binary.elf_size > UINT_MAX / 4 || llvm_ir_size > UINT_MAX / 4)
149 return NULL;
150
151 unsigned size = 4 + /* total size */
152 4 + /* CRC32 of the data below */
153 align(sizeof(shader->config), 4) + align(sizeof(shader->info), 4) + 4 +
154 align(shader->binary.elf_size, 4) + 4 + align(llvm_ir_size, 4);
155 void *buffer = CALLOC(1, size);
156 uint32_t *ptr = (uint32_t *)buffer;
157
158 if (!buffer)
159 return NULL;
160
161 *ptr++ = size;
162 ptr++; /* CRC32 is calculated at the end. */
163
164 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
165 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
166 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
167 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
168 assert((char *)ptr - (char *)buffer == size);
169
170 /* Compute CRC32. */
171 ptr = (uint32_t *)buffer;
172 ptr++;
173 *ptr = util_hash_crc32(ptr + 1, size - 8);
174
175 return buffer;
176 }
177
178 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
179 {
180 uint32_t *ptr = (uint32_t *)binary;
181 uint32_t size = *ptr++;
182 uint32_t crc32 = *ptr++;
183 unsigned chunk_size;
184 unsigned elf_size;
185
186 if (util_hash_crc32(ptr, size - 8) != crc32) {
187 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
188 return false;
189 }
190
191 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
192 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
193 ptr = read_chunk(ptr, (void **)&shader->binary.elf_buffer, &elf_size);
194 shader->binary.elf_size = elf_size;
195 ptr = read_chunk(ptr, (void **)&shader->binary.llvm_ir_string, &chunk_size);
196
197 return true;
198 }
199
200 /**
201 * Insert a shader into the cache. It's assumed the shader is not in the cache.
202 * Use si_shader_cache_load_shader before calling this.
203 */
204 void si_shader_cache_insert_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
205 struct si_shader *shader, bool insert_into_disk_cache)
206 {
207 void *hw_binary;
208 struct hash_entry *entry;
209 uint8_t key[CACHE_KEY_SIZE];
210
211 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
212 if (entry)
213 return; /* already added */
214
215 hw_binary = si_get_shader_binary(shader);
216 if (!hw_binary)
217 return;
218
219 if (_mesa_hash_table_insert(sscreen->shader_cache, mem_dup(ir_sha1_cache_key, 20), hw_binary) ==
220 NULL) {
221 FREE(hw_binary);
222 return;
223 }
224
225 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
226 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, key);
227 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary, *((uint32_t *)hw_binary), NULL);
228 }
229 }
230
231 bool si_shader_cache_load_shader(struct si_screen *sscreen, unsigned char ir_sha1_cache_key[20],
232 struct si_shader *shader)
233 {
234 struct hash_entry *entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
235
236 if (entry) {
237 if (si_load_shader_binary(shader, entry->data)) {
238 p_atomic_inc(&sscreen->num_memory_shader_cache_hits);
239 return true;
240 }
241 }
242 p_atomic_inc(&sscreen->num_memory_shader_cache_misses);
243
244 if (!sscreen->disk_shader_cache)
245 return false;
246
247 unsigned char sha1[CACHE_KEY_SIZE];
248 disk_cache_compute_key(sscreen->disk_shader_cache, ir_sha1_cache_key, 20, sha1);
249
250 size_t binary_size;
251 uint8_t *buffer = disk_cache_get(sscreen->disk_shader_cache, sha1, &binary_size);
252 if (buffer) {
253 if (binary_size >= sizeof(uint32_t) && *((uint32_t *)buffer) == binary_size) {
254 if (si_load_shader_binary(shader, buffer)) {
255 free(buffer);
256 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, false);
257 p_atomic_inc(&sscreen->num_disk_shader_cache_hits);
258 return true;
259 }
260 } else {
261 /* Something has gone wrong discard the item from the cache and
262 * rebuild/link from source.
263 */
264 assert(!"Invalid radeonsi shader disk cache item!");
265 disk_cache_remove(sscreen->disk_shader_cache, sha1);
266 }
267 }
268
269 free(buffer);
270 p_atomic_inc(&sscreen->num_disk_shader_cache_misses);
271 return false;
272 }
273
274 static uint32_t si_shader_cache_key_hash(const void *key)
275 {
276 /* Take the first dword of SHA1. */
277 return *(uint32_t *)key;
278 }
279
280 static bool si_shader_cache_key_equals(const void *a, const void *b)
281 {
282 /* Compare SHA1s. */
283 return memcmp(a, b, 20) == 0;
284 }
285
286 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
287 {
288 FREE((void *)entry->key);
289 FREE(entry->data);
290 }
291
292 bool si_init_shader_cache(struct si_screen *sscreen)
293 {
294 (void)simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
295 sscreen->shader_cache =
296 _mesa_hash_table_create(NULL, si_shader_cache_key_hash, si_shader_cache_key_equals);
297
298 return sscreen->shader_cache != NULL;
299 }
300
301 void si_destroy_shader_cache(struct si_screen *sscreen)
302 {
303 if (sscreen->shader_cache)
304 _mesa_hash_table_destroy(sscreen->shader_cache, si_destroy_shader_cache_entry);
305 simple_mtx_destroy(&sscreen->shader_cache_mutex);
306 }
307
308 /* SHADER STATES */
309
310 static void si_set_tesseval_regs(struct si_screen *sscreen, const struct si_shader_selector *tes,
311 struct si_pm4_state *pm4)
312 {
313 const struct si_shader_info *info = &tes->info;
314 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
315 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
316 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
317 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
318 unsigned type, partitioning, topology, distribution_mode;
319
320 switch (tes_prim_mode) {
321 case PIPE_PRIM_LINES:
322 type = V_028B6C_TESS_ISOLINE;
323 break;
324 case PIPE_PRIM_TRIANGLES:
325 type = V_028B6C_TESS_TRIANGLE;
326 break;
327 case PIPE_PRIM_QUADS:
328 type = V_028B6C_TESS_QUAD;
329 break;
330 default:
331 assert(0);
332 return;
333 }
334
335 switch (tes_spacing) {
336 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
337 partitioning = V_028B6C_PART_FRAC_ODD;
338 break;
339 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
340 partitioning = V_028B6C_PART_FRAC_EVEN;
341 break;
342 case PIPE_TESS_SPACING_EQUAL:
343 partitioning = V_028B6C_PART_INTEGER;
344 break;
345 default:
346 assert(0);
347 return;
348 }
349
350 if (tes_point_mode)
351 topology = V_028B6C_OUTPUT_POINT;
352 else if (tes_prim_mode == PIPE_PRIM_LINES)
353 topology = V_028B6C_OUTPUT_LINE;
354 else if (tes_vertex_order_cw)
355 /* for some reason, this must be the other way around */
356 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
357 else
358 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
359
360 if (sscreen->info.has_distributed_tess) {
361 if (sscreen->info.family == CHIP_FIJI || sscreen->info.family >= CHIP_POLARIS10)
362 distribution_mode = V_028B6C_TRAPEZOIDS;
363 else
364 distribution_mode = V_028B6C_DONUTS;
365 } else
366 distribution_mode = V_028B6C_NO_DIST;
367
368 assert(pm4->shader);
369 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) | S_028B6C_PARTITIONING(partitioning) |
370 S_028B6C_TOPOLOGY(topology) |
371 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
372 }
373
374 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
375 * whether the "fractional odd" tessellation spacing is used.
376 *
377 * Possible VGT configurations and which state should set the register:
378 *
379 * Reg set in | VGT shader configuration | Value
380 * ------------------------------------------------------
381 * VS as VS | VS | 30
382 * VS as ES | ES -> GS -> VS | 30
383 * TES as VS | LS -> HS -> VS | 14 or 30
384 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
385 *
386 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
387 */
388 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen, struct si_shader_selector *sel,
389 struct si_shader *shader, struct si_pm4_state *pm4)
390 {
391 unsigned type = sel->type;
392
393 if (sscreen->info.family < CHIP_POLARIS10 || sscreen->info.chip_class >= GFX10)
394 return;
395
396 /* VS as VS, or VS as ES: */
397 if ((type == PIPE_SHADER_VERTEX &&
398 (!shader || (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
399 /* TES as VS, or TES as ES: */
400 type == PIPE_SHADER_TESS_EVAL) {
401 unsigned vtx_reuse_depth = 30;
402
403 if (type == PIPE_SHADER_TESS_EVAL &&
404 sel->info.properties[TGSI_PROPERTY_TES_SPACING] == PIPE_TESS_SPACING_FRACTIONAL_ODD)
405 vtx_reuse_depth = 14;
406
407 assert(pm4->shader);
408 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
409 }
410 }
411
412 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
413 {
414 if (shader->pm4)
415 si_pm4_clear_state(shader->pm4);
416 else
417 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
418
419 if (shader->pm4) {
420 shader->pm4->shader = shader;
421 return shader->pm4;
422 } else {
423 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
424 return NULL;
425 }
426 }
427
428 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
429 unsigned num_always_on_user_sgprs)
430 {
431 struct si_shader_selector *vs =
432 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
433 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
434
435 /* 1 SGPR is reserved for the vertex buffer pointer. */
436 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
437
438 if (num_vbos_in_user_sgprs)
439 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
440
441 /* Add the pointer to VBO descriptors. */
442 return num_always_on_user_sgprs + 1;
443 }
444
445 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
446 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen, struct si_shader *shader,
447 bool legacy_vs_prim_id)
448 {
449 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
450 (shader->previous_stage_sel && shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
451
452 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
453 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
454 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
455 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or
456 * InstanceID)
457 */
458 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
459
460 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
461 return 3;
462 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
463 return 2;
464 else if (is_ls || shader->info.uses_instanceid)
465 return 1;
466 else
467 return 0;
468 }
469
470 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
471 {
472 struct si_pm4_state *pm4;
473 uint64_t va;
474
475 assert(sscreen->info.chip_class <= GFX8);
476
477 pm4 = si_get_shader_pm4_state(shader);
478 if (!pm4)
479 return;
480
481 va = shader->bo->gpu_address;
482 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
483 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
484
485 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
486 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
487 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
488 S_00B528_DX10_CLAMP(1) | S_00B528_FLOAT_MODE(shader->config.float_mode);
489 shader->config.rsrc2 =
490 S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
491 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
492 }
493
494 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
495 {
496 struct si_pm4_state *pm4;
497 uint64_t va;
498
499 pm4 = si_get_shader_pm4_state(shader);
500 if (!pm4)
501 return;
502
503 va = shader->bo->gpu_address;
504
505 if (sscreen->info.chip_class >= GFX9) {
506 if (sscreen->info.chip_class >= GFX10) {
507 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
508 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
509 } else {
510 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
511 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
512 }
513
514 unsigned num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
515
516 shader->config.rsrc2 = S_00B42C_USER_SGPR(num_user_sgprs) |
517 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
518
519 if (sscreen->info.chip_class >= GFX10)
520 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
521 else
522 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
523 } else {
524 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
525 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
526
527 shader->config.rsrc2 = S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) | S_00B42C_OC_LDS_EN(1) |
528 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
529 }
530
531 si_pm4_set_reg(
532 pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
533 S_00B428_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
534 (sscreen->info.chip_class <= GFX9 ? S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8)
535 : 0) |
536 S_00B428_DX10_CLAMP(1) | S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
537 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
538 S_00B428_FLOAT_MODE(shader->config.float_mode) |
539 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9
540 ? si_get_vs_vgpr_comp_cnt(sscreen, shader, false)
541 : 0));
542
543 if (sscreen->info.chip_class <= GFX8) {
544 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS, shader->config.rsrc2);
545 }
546 }
547
548 static void si_emit_shader_es(struct si_context *sctx)
549 {
550 struct si_shader *shader = sctx->queued.named.es->shader;
551 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
552
553 if (!shader)
554 return;
555
556 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
557 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
558 shader->selector->esgs_itemsize / 4);
559
560 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
561 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
562 shader->vgt_tf_param);
563
564 if (shader->vgt_vertex_reuse_block_cntl)
565 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
566 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
567 shader->vgt_vertex_reuse_block_cntl);
568
569 if (initial_cdw != sctx->gfx_cs->current.cdw)
570 sctx->context_roll = true;
571 }
572
573 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
574 {
575 struct si_pm4_state *pm4;
576 unsigned num_user_sgprs;
577 unsigned vgpr_comp_cnt;
578 uint64_t va;
579 unsigned oc_lds_en;
580
581 assert(sscreen->info.chip_class <= GFX8);
582
583 pm4 = si_get_shader_pm4_state(shader);
584 if (!pm4)
585 return;
586
587 pm4->atom.emit = si_emit_shader_es;
588 va = shader->bo->gpu_address;
589
590 if (shader->selector->type == PIPE_SHADER_VERTEX) {
591 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
592 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
593 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
594 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
595 num_user_sgprs = SI_TES_NUM_USER_SGPR;
596 } else
597 unreachable("invalid shader selector type");
598
599 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
600
601 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
602 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
603 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
604 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
605 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
606 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B328_DX10_CLAMP(1) |
607 S_00B328_FLOAT_MODE(shader->config.float_mode));
608 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
609 S_00B32C_USER_SGPR(num_user_sgprs) | S_00B32C_OC_LDS_EN(oc_lds_en) |
610 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
611
612 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
613 si_set_tesseval_regs(sscreen, shader->selector, pm4);
614
615 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
616 }
617
618 void gfx9_get_gs_info(struct si_shader_selector *es, struct si_shader_selector *gs,
619 struct gfx9_gs_info *out)
620 {
621 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
622 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
623 bool uses_adjacency =
624 input_prim >= PIPE_PRIM_LINES_ADJACENCY && input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
625
626 /* All these are in dwords: */
627 /* We can't allow using the whole LDS, because GS waves compete with
628 * other shader stages for LDS space. */
629 const unsigned max_lds_size = 8 * 1024;
630 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
631 unsigned esgs_lds_size;
632
633 /* All these are per subgroup: */
634 const unsigned max_out_prims = 32 * 1024;
635 const unsigned max_es_verts = 255;
636 const unsigned ideal_gs_prims = 64;
637 unsigned max_gs_prims, gs_prims;
638 unsigned min_es_verts, es_verts, worst_case_es_verts;
639
640 if (uses_adjacency || gs_num_invocations > 1)
641 max_gs_prims = 127 / gs_num_invocations;
642 else
643 max_gs_prims = 255;
644
645 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
646 * Make sure we don't go over the maximum value.
647 */
648 if (gs->gs_max_out_vertices > 0) {
649 max_gs_prims =
650 MIN2(max_gs_prims, max_out_prims / (gs->gs_max_out_vertices * gs_num_invocations));
651 }
652 assert(max_gs_prims > 0);
653
654 /* If the primitive has adjacency, halve the number of vertices
655 * that will be reused in multiple primitives.
656 */
657 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
658
659 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
660 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
661
662 /* Compute ESGS LDS size based on the worst case number of ES vertices
663 * needed to create the target number of GS prims per subgroup.
664 */
665 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
666
667 /* If total LDS usage is too big, refactor partitions based on ratio
668 * of ESGS item sizes.
669 */
670 if (esgs_lds_size > max_lds_size) {
671 /* Our target GS Prims Per Subgroup was too large. Calculate
672 * the maximum number of GS Prims Per Subgroup that will fit
673 * into LDS, capped by the maximum that the hardware can support.
674 */
675 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)), max_gs_prims);
676 assert(gs_prims > 0);
677 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
678
679 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
680 assert(esgs_lds_size <= max_lds_size);
681 }
682
683 /* Now calculate remaining ESGS information. */
684 if (esgs_lds_size)
685 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
686 else
687 es_verts = max_es_verts;
688
689 /* Vertices for adjacency primitives are not always reused, so restore
690 * it for ES_VERTS_PER_SUBGRP.
691 */
692 min_es_verts = gs->gs_input_verts_per_prim;
693
694 /* For normal primitives, the VGT only checks if they are past the ES
695 * verts per subgroup after allocating a full GS primitive and if they
696 * are, kick off a new subgroup. But if those additional ES verts are
697 * unique (e.g. not reused) we need to make sure there is enough LDS
698 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
699 */
700 es_verts -= min_es_verts - 1;
701
702 out->es_verts_per_subgroup = es_verts;
703 out->gs_prims_per_subgroup = gs_prims;
704 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
705 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup * gs->gs_max_out_vertices;
706 out->esgs_ring_size = esgs_lds_size;
707
708 assert(out->max_prims_per_subgroup <= max_out_prims);
709 }
710
711 static void si_emit_shader_gs(struct si_context *sctx)
712 {
713 struct si_shader *shader = sctx->queued.named.gs->shader;
714 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
715
716 if (!shader)
717 return;
718
719 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
720 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
721 radeon_opt_set_context_reg3(
722 sctx, R_028A60_VGT_GSVS_RING_OFFSET_1, SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
723 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1, shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
724 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
725
726 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
727 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
728 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
729 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
730
731 /* R_028B38_VGT_GS_MAX_VERT_OUT */
732 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
733 shader->ctx_reg.gs.vgt_gs_max_vert_out);
734
735 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
736 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
737 radeon_opt_set_context_reg4(
738 sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE, SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
739 shader->ctx_reg.gs.vgt_gs_vert_itemsize, shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
740 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2, shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
741
742 /* R_028B90_VGT_GS_INSTANCE_CNT */
743 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
744 shader->ctx_reg.gs.vgt_gs_instance_cnt);
745
746 if (sctx->chip_class >= GFX9) {
747 /* R_028A44_VGT_GS_ONCHIP_CNTL */
748 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
749 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
750 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
751 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
752 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
753 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
754 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
755 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
756 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
757 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
758
759 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
760 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
761 shader->vgt_tf_param);
762 if (shader->vgt_vertex_reuse_block_cntl)
763 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
764 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
765 shader->vgt_vertex_reuse_block_cntl);
766 }
767
768 if (initial_cdw != sctx->gfx_cs->current.cdw)
769 sctx->context_roll = true;
770 }
771
772 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
773 {
774 struct si_shader_selector *sel = shader->selector;
775 const ubyte *num_components = sel->info.num_stream_output_components;
776 unsigned gs_num_invocations = sel->gs_num_invocations;
777 struct si_pm4_state *pm4;
778 uint64_t va;
779 unsigned max_stream = sel->max_gs_stream;
780 unsigned offset;
781
782 pm4 = si_get_shader_pm4_state(shader);
783 if (!pm4)
784 return;
785
786 pm4->atom.emit = si_emit_shader_gs;
787
788 offset = num_components[0] * sel->gs_max_out_vertices;
789 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
790
791 if (max_stream >= 1)
792 offset += num_components[1] * sel->gs_max_out_vertices;
793 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
794
795 if (max_stream >= 2)
796 offset += num_components[2] * sel->gs_max_out_vertices;
797 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
798
799 if (max_stream >= 3)
800 offset += num_components[3] * sel->gs_max_out_vertices;
801 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
802
803 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
804 assert(offset < (1 << 15));
805
806 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
807
808 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
809 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
810 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
811 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
812
813 shader->ctx_reg.gs.vgt_gs_instance_cnt =
814 S_028B90_CNT(MIN2(gs_num_invocations, 127)) | S_028B90_ENABLE(gs_num_invocations > 0);
815
816 va = shader->bo->gpu_address;
817
818 if (sscreen->info.chip_class >= GFX9) {
819 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
820 unsigned es_type = shader->key.part.gs.es->type;
821 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
822
823 if (es_type == PIPE_SHADER_VERTEX) {
824 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
825 } else if (es_type == PIPE_SHADER_TESS_EVAL)
826 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
827 else
828 unreachable("invalid shader selector type");
829
830 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
831 * VGPR[0:4] are always loaded.
832 */
833 if (sel->info.uses_invocationid)
834 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
835 else if (sel->info.uses_primid)
836 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
837 else if (input_prim >= PIPE_PRIM_TRIANGLES)
838 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
839 else
840 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
841
842 unsigned num_user_sgprs;
843 if (es_type == PIPE_SHADER_VERTEX)
844 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
845 else
846 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
847
848 if (sscreen->info.chip_class >= GFX10) {
849 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
850 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
851 } else {
852 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
853 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
854 }
855
856 uint32_t rsrc1 = S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) | S_00B228_DX10_CLAMP(1) |
857 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
858 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
859 S_00B228_FLOAT_MODE(shader->config.float_mode) |
860 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
861 uint32_t rsrc2 = S_00B22C_USER_SGPR(num_user_sgprs) |
862 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
863 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
864 S_00B22C_LDS_SIZE(shader->config.lds_size) |
865 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
866
867 if (sscreen->info.chip_class >= GFX10) {
868 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
869 } else {
870 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
871 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
872 }
873
874 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
875 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
876
877 if (sscreen->info.chip_class >= GFX10) {
878 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
879 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
880 }
881
882 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
883 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
884 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
885 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
886 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
887 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
888 shader->ctx_reg.gs.vgt_esgs_ring_itemsize = shader->key.part.gs.es->esgs_itemsize / 4;
889
890 if (es_type == PIPE_SHADER_TESS_EVAL)
891 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
892
893 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es, NULL, pm4);
894 } else {
895 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
896 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
897
898 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
899 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
900 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
901 S_00B228_DX10_CLAMP(1) | S_00B228_FLOAT_MODE(shader->config.float_mode));
902 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
903 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
904 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
905 }
906 }
907
908 static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
909 {
910 enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
911
912 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
913 sctx->tracked_regs.reg_value[reg] != value) {
914 struct radeon_cmdbuf *cs = sctx->gfx_cs;
915
916 if (sctx->chip_class == GFX10) {
917 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
918 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
919 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
920 }
921
922 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
923
924 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
925 sctx->tracked_regs.reg_value[reg] = value;
926 }
927 }
928
929 /* Common tail code for NGG primitive shaders. */
930 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx, struct si_shader *shader,
931 unsigned initial_cdw)
932 {
933 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
934 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
935 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
936 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL, SI_TRACKED_GE_NGG_SUBGRP_CNTL,
937 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
938 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
939 shader->ctx_reg.ngg.vgt_primitiveid_en);
940 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL, SI_TRACKED_VGT_GS_ONCHIP_CNTL,
941 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
942 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT, SI_TRACKED_VGT_GS_INSTANCE_CNT,
943 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
944 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
945 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
946 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
947 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
948 shader->ctx_reg.ngg.spi_vs_out_config);
949 radeon_opt_set_context_reg2(
950 sctx, R_028708_SPI_SHADER_IDX_FORMAT, SI_TRACKED_SPI_SHADER_IDX_FORMAT,
951 shader->ctx_reg.ngg.spi_shader_idx_format, shader->ctx_reg.ngg.spi_shader_pos_format);
952 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
953 shader->ctx_reg.ngg.pa_cl_vte_cntl);
954 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL, SI_TRACKED_PA_CL_NGG_CNTL,
955 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
956
957 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
958 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, shader->pa_cl_vs_out_cntl,
959 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
960
961 if (initial_cdw != sctx->gfx_cs->current.cdw)
962 sctx->context_roll = true;
963
964 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
965 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
966 }
967
968 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
969 {
970 struct si_shader *shader = sctx->queued.named.gs->shader;
971 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
972
973 if (!shader)
974 return;
975
976 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
977 }
978
979 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
980 {
981 struct si_shader *shader = sctx->queued.named.gs->shader;
982 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
983
984 if (!shader)
985 return;
986
987 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
988 shader->vgt_tf_param);
989
990 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
991 }
992
993 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
994 {
995 struct si_shader *shader = sctx->queued.named.gs->shader;
996 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
997
998 if (!shader)
999 return;
1000
1001 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1002 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1003
1004 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1005 }
1006
1007 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1008 {
1009 struct si_shader *shader = sctx->queued.named.gs->shader;
1010 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1011
1012 if (!shader)
1013 return;
1014
1015 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT, SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1016 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1017 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1018 shader->vgt_tf_param);
1019
1020 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1021 }
1022
1023 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1024 {
1025 if (gs->type == PIPE_SHADER_GEOMETRY)
1026 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1027
1028 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1029 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1030 return PIPE_PRIM_POINTS;
1031 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1032 return PIPE_PRIM_LINES;
1033 return PIPE_PRIM_TRIANGLES;
1034 }
1035
1036 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1037 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1038 }
1039
1040 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1041 {
1042 bool misc_vec_ena = sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1043 sel->info.writes_layer || sel->info.writes_viewport_index;
1044 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1045 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1046 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1047 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1048 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1049 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1050 }
1051
1052 /**
1053 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1054 * in NGG mode.
1055 */
1056 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1057 {
1058 const struct si_shader_selector *gs_sel = shader->selector;
1059 const struct si_shader_info *gs_info = &gs_sel->info;
1060 enum pipe_shader_type gs_type = shader->selector->type;
1061 const struct si_shader_selector *es_sel =
1062 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1063 const struct si_shader_info *es_info = &es_sel->info;
1064 enum pipe_shader_type es_type = es_sel->type;
1065 unsigned num_user_sgprs;
1066 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1067 uint64_t va;
1068 unsigned window_space = gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1069 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1070 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1071 unsigned input_prim = si_get_input_prim(gs_sel);
1072 bool break_wave_at_eoi = false;
1073 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1074 if (!pm4)
1075 return;
1076
1077 if (es_type == PIPE_SHADER_TESS_EVAL) {
1078 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1079 : gfx10_emit_shader_ngg_tess_nogs;
1080 } else {
1081 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1082 : gfx10_emit_shader_ngg_notess_nogs;
1083 }
1084
1085 va = shader->bo->gpu_address;
1086
1087 if (es_type == PIPE_SHADER_VERTEX) {
1088 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1089
1090 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1091 num_user_sgprs =
1092 SI_SGPR_VS_BLIT_DATA + es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1093 } else {
1094 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1095 }
1096 } else {
1097 assert(es_type == PIPE_SHADER_TESS_EVAL);
1098 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1099 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1100
1101 if (es_enable_prim_id || gs_info->uses_primid)
1102 break_wave_at_eoi = true;
1103 }
1104
1105 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1106 * VGPR[0:4] are always loaded.
1107 *
1108 * Vertex shaders always need to load VGPR3, because they need to
1109 * pass edge flags for decomposed primitives (such as quads) to the PA
1110 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1111 */
1112 if (gs_info->uses_invocationid ||
1113 (gs_type == PIPE_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1114 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1115 else if ((gs_type == PIPE_SHADER_GEOMETRY && gs_info->uses_primid) ||
1116 (gs_type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1117 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1118 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1119 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1120 else
1121 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1122
1123 unsigned wave_size = si_get_shader_wave_size(shader);
1124
1125 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1126 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1127 si_pm4_set_reg(
1128 pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1129 S_00B228_VGPRS((shader->config.num_vgprs - 1) / (wave_size == 32 ? 8 : 4)) |
1130 S_00B228_FLOAT_MODE(shader->config.float_mode) | S_00B228_DX10_CLAMP(1) |
1131 S_00B228_MEM_ORDERED(1) | S_00B228_WGP_MODE(1) |
1132 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1133 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1134 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1135 S_00B22C_USER_SGPR(num_user_sgprs) |
1136 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1137 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1138 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1139 S_00B22C_LDS_SIZE(shader->config.lds_size));
1140
1141 /* Determine LATE_ALLOC_GS. */
1142 unsigned num_cu_per_sh = sscreen->info.min_good_cu_per_sa;
1143 unsigned late_alloc_wave64; /* The limit is per SA. */
1144
1145 /* For Wave32, the hw will launch twice the number of late
1146 * alloc waves, so 1 == 2x wave32.
1147 *
1148 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1149 */
1150 if (sscreen->info.family == CHIP_NAVI14 || !sscreen->info.use_late_alloc)
1151 late_alloc_wave64 = 0;
1152 else if (num_cu_per_sh <= 6)
1153 late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
1154 else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL)
1155 late_alloc_wave64 = (num_cu_per_sh - 2) * 6;
1156 else
1157 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
1158
1159 /* Limit LATE_ALLOC_GS for prevent a hang (hw bug). */
1160 if (sscreen->info.chip_class == GFX10)
1161 late_alloc_wave64 = MIN2(late_alloc_wave64, 64);
1162
1163 si_pm4_set_reg(
1164 pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1165 S_00B204_CU_EN(0xffff) | S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64));
1166
1167 nparams = MAX2(shader->info.nr_param_exports, 1);
1168 shader->ctx_reg.ngg.spi_vs_out_config =
1169 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1170 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1171
1172 shader->ctx_reg.ngg.spi_shader_idx_format =
1173 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1174 shader->ctx_reg.ngg.spi_shader_pos_format =
1175 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1176 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1177 : V_02870C_SPI_SHADER_NONE) |
1178 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1179 : V_02870C_SPI_SHADER_NONE) |
1180 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1181 : V_02870C_SPI_SHADER_NONE);
1182
1183 shader->ctx_reg.ngg.vgt_primitiveid_en =
1184 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1185 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1186 gs_sel->info.writes_primid);
1187
1188 if (gs_type == PIPE_SHADER_GEOMETRY) {
1189 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1190 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1191 } else {
1192 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1193 }
1194
1195 if (es_type == PIPE_SHADER_TESS_EVAL)
1196 si_set_tesseval_regs(sscreen, es_sel, pm4);
1197
1198 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1199 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1200 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1201 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1202 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1203 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1204 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl = S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1205 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1206 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1207 S_028B90_CNT(gs_num_invocations) | S_028B90_ENABLE(gs_num_invocations > 1) |
1208 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(shader->ngg.max_vert_out_per_gs_instance);
1209
1210 /* Always output hw-generated edge flags and pass them via the prim
1211 * export to prevent drawing lines on internal edges of decomposed
1212 * primitives (such as quads) with polygon mode = lines. Only VS needs
1213 * this.
1214 */
1215 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1216 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX) |
1217 /* Reuse for NGG. */
1218 S_028838_VERTEX_REUSE_DEPTH(sscreen->info.chip_class >= GFX10_3 ? 30 : 0);
1219 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1220
1221 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1222 float oversub_pc_factor = 0.25;
1223
1224 if (shader->key.opt.ngg_culling) {
1225 /* Be more aggressive with NGG culling. */
1226 if (shader->info.nr_param_exports > 4)
1227 oversub_pc_factor = 1;
1228 else if (shader->info.nr_param_exports > 2)
1229 oversub_pc_factor = 0.75;
1230 else
1231 oversub_pc_factor = 0.5;
1232 }
1233
1234 unsigned oversub_pc_lines = sscreen->info.pc_lines * oversub_pc_factor;
1235 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
1236 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1237
1238 if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_LIST) {
1239 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1240 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims * 3);
1241 } else if (shader->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_TRI_STRIP) {
1242 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1243 S_03096C_VERT_GRP_SIZE(shader->ngg.max_gsprims + 2);
1244 } else {
1245 shader->ge_cntl = S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1246 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1247 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1248
1249 /* Bug workaround for a possible hang with non-tessellation cases.
1250 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1251 *
1252 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1253 */
1254 if ((sscreen->info.chip_class == GFX10) &&
1255 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1256 shader->ngg.hw_max_esverts != 256) {
1257 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1258
1259 if (shader->ngg.hw_max_esverts > 5) {
1260 shader->ge_cntl |= S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1261 }
1262 }
1263 }
1264
1265 if (window_space) {
1266 shader->ctx_reg.ngg.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1267 } else {
1268 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1269 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1270 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1271 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1272 }
1273 }
1274
1275 static void si_emit_shader_vs(struct si_context *sctx)
1276 {
1277 struct si_shader *shader = sctx->queued.named.vs->shader;
1278 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1279
1280 if (!shader)
1281 return;
1282
1283 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE, SI_TRACKED_VGT_GS_MODE,
1284 shader->ctx_reg.vs.vgt_gs_mode);
1285 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN, SI_TRACKED_VGT_PRIMITIVEID_EN,
1286 shader->ctx_reg.vs.vgt_primitiveid_en);
1287
1288 if (sctx->chip_class <= GFX8) {
1289 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF, SI_TRACKED_VGT_REUSE_OFF,
1290 shader->ctx_reg.vs.vgt_reuse_off);
1291 }
1292
1293 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG, SI_TRACKED_SPI_VS_OUT_CONFIG,
1294 shader->ctx_reg.vs.spi_vs_out_config);
1295
1296 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1297 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1298 shader->ctx_reg.vs.spi_shader_pos_format);
1299
1300 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL, SI_TRACKED_PA_CL_VTE_CNTL,
1301 shader->ctx_reg.vs.pa_cl_vte_cntl);
1302
1303 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1304 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM, SI_TRACKED_VGT_TF_PARAM,
1305 shader->vgt_tf_param);
1306
1307 if (shader->vgt_vertex_reuse_block_cntl)
1308 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1309 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1310 shader->vgt_vertex_reuse_block_cntl);
1311
1312 /* Required programming for tessellation. (legacy pipeline only) */
1313 if (sctx->chip_class >= GFX10 && shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1314 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1315 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1316 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1317 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1318 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1319 }
1320
1321 if (sctx->chip_class >= GFX10) {
1322 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1323 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS, shader->pa_cl_vs_out_cntl,
1324 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1325 }
1326
1327 if (initial_cdw != sctx->gfx_cs->current.cdw)
1328 sctx->context_roll = true;
1329
1330 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1331 if (sctx->chip_class >= GFX10)
1332 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
1333 }
1334
1335 /**
1336 * Compute the state for \p shader, which will run as a vertex shader on the
1337 * hardware.
1338 *
1339 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1340 * is the copy shader.
1341 */
1342 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1343 struct si_shader_selector *gs)
1344 {
1345 const struct si_shader_info *info = &shader->selector->info;
1346 struct si_pm4_state *pm4;
1347 unsigned num_user_sgprs, vgpr_comp_cnt;
1348 uint64_t va;
1349 unsigned nparams, oc_lds_en;
1350 unsigned window_space = info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1351 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1352
1353 pm4 = si_get_shader_pm4_state(shader);
1354 if (!pm4)
1355 return;
1356
1357 pm4->atom.emit = si_emit_shader_vs;
1358
1359 /* We always write VGT_GS_MODE in the VS state, because every switch
1360 * between different shader pipelines involving a different GS or no
1361 * GS at all involves a switch of the VS (different GS use different
1362 * copy shaders). On the other hand, when the API switches from a GS to
1363 * no GS and then back to the same GS used originally, the GS state is
1364 * not sent again.
1365 */
1366 if (!gs) {
1367 unsigned mode = V_028A40_GS_OFF;
1368
1369 /* PrimID needs GS scenario A. */
1370 if (enable_prim_id)
1371 mode = V_028A40_GS_SCENARIO_A;
1372
1373 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1374 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1375 } else {
1376 shader->ctx_reg.vs.vgt_gs_mode =
1377 ac_vgt_gs_mode(gs->gs_max_out_vertices, sscreen->info.chip_class);
1378 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1379 }
1380
1381 if (sscreen->info.chip_class <= GFX8) {
1382 /* Reuse needs to be set off if we write oViewport. */
1383 shader->ctx_reg.vs.vgt_reuse_off = S_028AB4_REUSE_OFF(info->writes_viewport_index);
1384 }
1385
1386 va = shader->bo->gpu_address;
1387
1388 if (gs) {
1389 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1390 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1391 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1392 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1393
1394 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1395 num_user_sgprs = SI_SGPR_VS_BLIT_DATA + info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1396 } else {
1397 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1398 }
1399 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1400 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1401 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1402 } else
1403 unreachable("invalid shader selector type");
1404
1405 /* VS is required to export at least one param. */
1406 nparams = MAX2(shader->info.nr_param_exports, 1);
1407 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1408
1409 if (sscreen->info.chip_class >= GFX10) {
1410 shader->ctx_reg.vs.spi_vs_out_config |=
1411 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1412 }
1413
1414 shader->ctx_reg.vs.spi_shader_pos_format =
1415 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1416 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ? V_02870C_SPI_SHADER_4COMP
1417 : V_02870C_SPI_SHADER_NONE) |
1418 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ? V_02870C_SPI_SHADER_4COMP
1419 : V_02870C_SPI_SHADER_NONE) |
1420 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ? V_02870C_SPI_SHADER_4COMP
1421 : V_02870C_SPI_SHADER_NONE);
1422 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(sscreen->info.use_late_alloc) |
1423 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1424 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1425
1426 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1427
1428 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1429 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1430
1431 uint32_t rsrc1 =
1432 S_00B128_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1433 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) | S_00B128_DX10_CLAMP(1) |
1434 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1435 S_00B128_FLOAT_MODE(shader->config.float_mode);
1436 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) | S_00B12C_OC_LDS_EN(oc_lds_en) |
1437 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1438
1439 if (sscreen->info.chip_class >= GFX10)
1440 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1441 else if (sscreen->info.chip_class == GFX9)
1442 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1443
1444 if (sscreen->info.chip_class <= GFX9)
1445 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1446
1447 if (!sscreen->use_ngg_streamout) {
1448 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1449 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1450 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1451 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1452 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1453 }
1454
1455 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1456 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1457
1458 if (window_space)
1459 shader->ctx_reg.vs.pa_cl_vte_cntl = S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1460 else
1461 shader->ctx_reg.vs.pa_cl_vte_cntl =
1462 S_028818_VTX_W0_FMT(1) | S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1463 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1464 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1465
1466 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1467 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1468
1469 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1470 }
1471
1472 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1473 {
1474 struct si_shader_info *info = &ps->selector->info;
1475 unsigned num_colors = !!(info->colors_read & 0x0f) + !!(info->colors_read & 0xf0);
1476 unsigned num_interp =
1477 ps->selector->info.num_inputs + (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1478
1479 assert(num_interp <= 32);
1480 return MIN2(num_interp, 32);
1481 }
1482
1483 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1484 {
1485 unsigned spi_shader_col_format = shader->key.part.ps.epilog.spi_shader_col_format;
1486 unsigned value = 0, num_mrts = 0;
1487 unsigned i, num_targets = (util_last_bit(spi_shader_col_format) + 3) / 4;
1488
1489 /* Remove holes in spi_shader_col_format. */
1490 for (i = 0; i < num_targets; i++) {
1491 unsigned spi_format = (spi_shader_col_format >> (i * 4)) & 0xf;
1492
1493 if (spi_format) {
1494 value |= spi_format << (num_mrts * 4);
1495 num_mrts++;
1496 }
1497 }
1498
1499 return value;
1500 }
1501
1502 static void si_emit_shader_ps(struct si_context *sctx)
1503 {
1504 struct si_shader *shader = sctx->queued.named.ps->shader;
1505 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1506
1507 if (!shader)
1508 return;
1509
1510 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1511 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA, SI_TRACKED_SPI_PS_INPUT_ENA,
1512 shader->ctx_reg.ps.spi_ps_input_ena,
1513 shader->ctx_reg.ps.spi_ps_input_addr);
1514
1515 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL, SI_TRACKED_SPI_BARYC_CNTL,
1516 shader->ctx_reg.ps.spi_baryc_cntl);
1517 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL, SI_TRACKED_SPI_PS_IN_CONTROL,
1518 shader->ctx_reg.ps.spi_ps_in_control);
1519
1520 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1521 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT, SI_TRACKED_SPI_SHADER_Z_FORMAT,
1522 shader->ctx_reg.ps.spi_shader_z_format,
1523 shader->ctx_reg.ps.spi_shader_col_format);
1524
1525 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK, SI_TRACKED_CB_SHADER_MASK,
1526 shader->ctx_reg.ps.cb_shader_mask);
1527
1528 if (initial_cdw != sctx->gfx_cs->current.cdw)
1529 sctx->context_roll = true;
1530 }
1531
1532 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1533 {
1534 struct si_shader_info *info = &shader->selector->info;
1535 struct si_pm4_state *pm4;
1536 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1537 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1538 uint64_t va;
1539 unsigned input_ena = shader->config.spi_ps_input_ena;
1540
1541 /* we need to enable at least one of them, otherwise we hang the GPU */
1542 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) || G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1543 G_0286CC_PERSP_CENTROID_ENA(input_ena) || G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1544 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) || G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1545 G_0286CC_LINEAR_CENTROID_ENA(input_ena) || G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1546 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1547 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) || G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1548 G_0286CC_PERSP_CENTER_ENA(input_ena) || G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1549 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1550
1551 /* Validate interpolation optimization flags (read as implications). */
1552 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1553 (G_0286CC_PERSP_CENTER_ENA(input_ena) && G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1554 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1555 (G_0286CC_LINEAR_CENTER_ENA(input_ena) && G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1556 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1557 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1558 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1559 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1560 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1561 (!G_0286CC_PERSP_CENTER_ENA(input_ena) && !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1562 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1563 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) && !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1564
1565 /* Validate cases when the optimizations are off (read as implications). */
1566 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1567 !G_0286CC_PERSP_CENTER_ENA(input_ena) || !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1568 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1569 !G_0286CC_LINEAR_CENTER_ENA(input_ena) || !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1570
1571 pm4 = si_get_shader_pm4_state(shader);
1572 if (!pm4)
1573 return;
1574
1575 pm4->atom.emit = si_emit_shader_ps;
1576
1577 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1578 * Possible vaules:
1579 * 0 -> Position = pixel center
1580 * 1 -> Position = pixel centroid
1581 * 2 -> Position = at sample position
1582 *
1583 * From GLSL 4.5 specification, section 7.1:
1584 * "The variable gl_FragCoord is available as an input variable from
1585 * within fragment shaders and it holds the window relative coordinates
1586 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1587 * value can be for any location within the pixel, or one of the
1588 * fragment samples. The use of centroid does not further restrict
1589 * this value to be inside the current primitive."
1590 *
1591 * Meaning that centroid has no effect and we can return anything within
1592 * the pixel. Thus, return the value at sample position, because that's
1593 * the most accurate one shaders can get.
1594 */
1595 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1596
1597 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] == TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1598 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1599
1600 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1601 cb_shader_mask = ac_get_cb_shader_mask(shader->key.part.ps.epilog.spi_shader_col_format);
1602
1603 /* Ensure that some export memory is always allocated, for two reasons:
1604 *
1605 * 1) Correctness: The hardware ignores the EXEC mask if no export
1606 * memory is allocated, so KILL and alpha test do not work correctly
1607 * without this.
1608 * 2) Performance: Every shader needs at least a NULL export, even when
1609 * it writes no color/depth output. The NULL export instruction
1610 * stalls without this setting.
1611 *
1612 * Don't add this to CB_SHADER_MASK.
1613 *
1614 * GFX10 supports pixel shaders without exports by setting both
1615 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1616 * instructions if any are present.
1617 */
1618 if ((sscreen->info.chip_class <= GFX9 || info->uses_kill ||
1619 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1620 !spi_shader_col_format && !info->writes_z && !info->writes_stencil &&
1621 !info->writes_samplemask)
1622 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1623
1624 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1625 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1626
1627 /* Set interpolation controls. */
1628 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1629 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1630
1631 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1632 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1633 shader->ctx_reg.ps.spi_shader_z_format =
1634 ac_get_spi_shader_z_format(info->writes_z, info->writes_stencil, info->writes_samplemask);
1635 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1636 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1637
1638 va = shader->bo->gpu_address;
1639 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1640 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1641
1642 uint32_t rsrc1 =
1643 S_00B028_VGPRS((shader->config.num_vgprs - 1) / (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1644 S_00B028_DX10_CLAMP(1) | S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1645 S_00B028_FLOAT_MODE(shader->config.float_mode);
1646
1647 if (sscreen->info.chip_class < GFX10) {
1648 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1649 }
1650
1651 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1652 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1653 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1654 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1655 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1656 }
1657
1658 static void si_shader_init_pm4_state(struct si_screen *sscreen, struct si_shader *shader)
1659 {
1660 switch (shader->selector->type) {
1661 case PIPE_SHADER_VERTEX:
1662 if (shader->key.as_ls)
1663 si_shader_ls(sscreen, shader);
1664 else if (shader->key.as_es)
1665 si_shader_es(sscreen, shader);
1666 else if (shader->key.as_ngg)
1667 gfx10_shader_ngg(sscreen, shader);
1668 else
1669 si_shader_vs(sscreen, shader, NULL);
1670 break;
1671 case PIPE_SHADER_TESS_CTRL:
1672 si_shader_hs(sscreen, shader);
1673 break;
1674 case PIPE_SHADER_TESS_EVAL:
1675 if (shader->key.as_es)
1676 si_shader_es(sscreen, shader);
1677 else if (shader->key.as_ngg)
1678 gfx10_shader_ngg(sscreen, shader);
1679 else
1680 si_shader_vs(sscreen, shader, NULL);
1681 break;
1682 case PIPE_SHADER_GEOMETRY:
1683 if (shader->key.as_ngg)
1684 gfx10_shader_ngg(sscreen, shader);
1685 else
1686 si_shader_gs(sscreen, shader);
1687 break;
1688 case PIPE_SHADER_FRAGMENT:
1689 si_shader_ps(sscreen, shader);
1690 break;
1691 default:
1692 assert(0);
1693 }
1694 }
1695
1696 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1697 {
1698 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1699 return sctx->queued.named.dsa->alpha_func;
1700 }
1701
1702 void si_shader_selector_key_vs(struct si_context *sctx, struct si_shader_selector *vs,
1703 struct si_shader_key *key, struct si_vs_prolog_bits *prolog_key)
1704 {
1705 if (!sctx->vertex_elements || vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1706 return;
1707
1708 struct si_vertex_elements *elts = sctx->vertex_elements;
1709
1710 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1711 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1712 prolog_key->unpack_instance_id_from_vertex_id = sctx->prim_discard_cs_instancing;
1713
1714 /* Prefer a monolithic shader to allow scheduling divisions around
1715 * VBO loads. */
1716 if (prolog_key->instance_divisor_is_fetched)
1717 key->opt.prefer_mono = 1;
1718
1719 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1720 unsigned count_mask = (1 << count) - 1;
1721 unsigned fix = elts->fix_fetch_always & count_mask;
1722 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1723
1724 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1725 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1726 while (mask) {
1727 unsigned i = u_bit_scan(&mask);
1728 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1729 unsigned vbidx = elts->vertex_buffer_index[i];
1730 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1731 unsigned align_mask = (1 << log_hw_load_size) - 1;
1732 if (vb->buffer_offset & align_mask || vb->stride & align_mask) {
1733 fix |= 1 << i;
1734 opencode |= 1 << i;
1735 }
1736 }
1737 }
1738
1739 while (fix) {
1740 unsigned i = u_bit_scan(&fix);
1741 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1742 }
1743 key->mono.vs_fetch_opencode = opencode;
1744 }
1745
1746 static void si_shader_selector_key_hw_vs(struct si_context *sctx, struct si_shader_selector *vs,
1747 struct si_shader_key *key)
1748 {
1749 struct si_shader_selector *ps = sctx->ps_shader.cso;
1750
1751 key->opt.clip_disable = sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1752 (vs->info.clipdist_writemask || vs->info.writes_clipvertex) &&
1753 !vs->info.culldist_writemask;
1754
1755 /* Find out if PS is disabled. */
1756 bool ps_disabled = true;
1757 if (ps) {
1758 bool ps_modifies_zs = ps->info.uses_kill || ps->info.writes_z || ps->info.writes_stencil ||
1759 ps->info.writes_samplemask ||
1760 sctx->queued.named.blend->alpha_to_coverage ||
1761 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1762 unsigned ps_colormask = si_get_total_colormask(sctx);
1763
1764 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1765 (!ps_colormask && !ps_modifies_zs && !ps->info.writes_memory);
1766 }
1767
1768 /* Find out which VS outputs aren't used by the PS. */
1769 uint64_t outputs_written = vs->outputs_written_before_ps;
1770 uint64_t inputs_read = 0;
1771
1772 /* Ignore outputs that are not passed from VS to PS. */
1773 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1774 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1775 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1776
1777 if (!ps_disabled) {
1778 inputs_read = ps->inputs_read;
1779 }
1780
1781 uint64_t linked = outputs_written & inputs_read;
1782
1783 key->opt.kill_outputs = ~linked & outputs_written;
1784 key->opt.ngg_culling = sctx->ngg_culling;
1785 }
1786
1787 /* Compute the key for the hw shader variant */
1788 static inline void si_shader_selector_key(struct pipe_context *ctx, struct si_shader_selector *sel,
1789 union si_vgt_stages_key stages_key,
1790 struct si_shader_key *key)
1791 {
1792 struct si_context *sctx = (struct si_context *)ctx;
1793
1794 memset(key, 0, sizeof(*key));
1795
1796 switch (sel->type) {
1797 case PIPE_SHADER_VERTEX:
1798 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1799
1800 if (sctx->tes_shader.cso)
1801 key->as_ls = 1;
1802 else if (sctx->gs_shader.cso) {
1803 key->as_es = 1;
1804 key->as_ngg = stages_key.u.ngg;
1805 } else {
1806 key->as_ngg = stages_key.u.ngg;
1807 si_shader_selector_key_hw_vs(sctx, sel, key);
1808
1809 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1810 key->mono.u.vs_export_prim_id = 1;
1811 }
1812 break;
1813 case PIPE_SHADER_TESS_CTRL:
1814 if (sctx->chip_class >= GFX9) {
1815 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.tcs.ls_prolog);
1816 key->part.tcs.ls = sctx->vs_shader.cso;
1817
1818 /* When the LS VGPR fix is needed, monolithic shaders
1819 * can:
1820 * - avoid initializing EXEC in both the LS prolog
1821 * and the LS main part when !vs_needs_prolog
1822 * - remove the fixup for unused input VGPRs
1823 */
1824 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1825
1826 /* The LS output / HS input layout can be communicated
1827 * directly instead of via user SGPRs for merged LS-HS.
1828 * The LS VGPR fix prefers this too.
1829 */
1830 key->opt.prefer_mono = 1;
1831 }
1832
1833 key->part.tcs.epilog.prim_mode =
1834 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1835 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1836 sel->info.tessfactors_are_def_in_all_invocs;
1837 key->part.tcs.epilog.tes_reads_tess_factors = sctx->tes_shader.cso->info.reads_tess_factors;
1838
1839 if (sel == sctx->fixed_func_tcs_shader.cso)
1840 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1841 break;
1842 case PIPE_SHADER_TESS_EVAL:
1843 key->as_ngg = stages_key.u.ngg;
1844
1845 if (sctx->gs_shader.cso)
1846 key->as_es = 1;
1847 else {
1848 si_shader_selector_key_hw_vs(sctx, sel, key);
1849
1850 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1851 key->mono.u.vs_export_prim_id = 1;
1852 }
1853 break;
1854 case PIPE_SHADER_GEOMETRY:
1855 if (sctx->chip_class >= GFX9) {
1856 if (sctx->tes_shader.cso) {
1857 key->part.gs.es = sctx->tes_shader.cso;
1858 } else {
1859 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso, key, &key->part.gs.vs_prolog);
1860 key->part.gs.es = sctx->vs_shader.cso;
1861 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1862 }
1863
1864 key->as_ngg = stages_key.u.ngg;
1865
1866 /* Merged ES-GS can have unbalanced wave usage.
1867 *
1868 * ES threads are per-vertex, while GS threads are
1869 * per-primitive. So without any amplification, there
1870 * are fewer GS threads than ES threads, which can result
1871 * in empty (no-op) GS waves. With too much amplification,
1872 * there are more GS threads than ES threads, which
1873 * can result in empty (no-op) ES waves.
1874 *
1875 * Non-monolithic shaders are implemented by setting EXEC
1876 * at the beginning of shader parts, and don't jump to
1877 * the end if EXEC is 0.
1878 *
1879 * Monolithic shaders use conditional blocks, so they can
1880 * jump and skip empty waves of ES or GS. So set this to
1881 * always use optimized variants, which are monolithic.
1882 */
1883 key->opt.prefer_mono = 1;
1884 }
1885 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1886 break;
1887 case PIPE_SHADER_FRAGMENT: {
1888 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1889 struct si_state_blend *blend = sctx->queued.named.blend;
1890
1891 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1892 sel->info.colors_written == 0x1)
1893 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1894
1895 /* Select the shader color format based on whether
1896 * blending or alpha are needed.
1897 */
1898 key->part.ps.epilog.spi_shader_col_format =
1899 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1900 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1901 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1902 sctx->framebuffer.spi_shader_col_format_blend) |
1903 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1904 sctx->framebuffer.spi_shader_col_format_alpha) |
1905 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1906 sctx->framebuffer.spi_shader_col_format);
1907 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1908
1909 /* The output for dual source blending should have
1910 * the same format as the first output.
1911 */
1912 if (blend->dual_src_blend) {
1913 key->part.ps.epilog.spi_shader_col_format |=
1914 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1915 }
1916
1917 /* If alpha-to-coverage is enabled, we have to export alpha
1918 * even if there is no color buffer.
1919 */
1920 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) && blend->alpha_to_coverage)
1921 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1922
1923 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1924 * to the range supported by the type if a channel has less
1925 * than 16 bits and the export format is 16_ABGR.
1926 */
1927 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1928 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1929 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1930 }
1931
1932 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1933 if (!key->part.ps.epilog.last_cbuf) {
1934 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1935 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1936 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1937 }
1938
1939 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1940 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1941
1942 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1943 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1944
1945 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one && rs->multisample_enable;
1946
1947 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1948 key->part.ps.epilog.poly_line_smoothing =
1949 ((is_poly && rs->poly_smooth) || (is_line && rs->line_smooth)) &&
1950 sctx->framebuffer.nr_samples <= 1;
1951 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1952
1953 if (sctx->ps_iter_samples > 1 && sel->info.reads_samplemask) {
1954 key->part.ps.prolog.samplemask_log_ps_iter = util_logbase2(sctx->ps_iter_samples);
1955 }
1956
1957 if (rs->force_persample_interp && rs->multisample_enable &&
1958 sctx->framebuffer.nr_samples > 1 && sctx->ps_iter_samples > 1) {
1959 key->part.ps.prolog.force_persp_sample_interp =
1960 sel->info.uses_persp_center || sel->info.uses_persp_centroid;
1961
1962 key->part.ps.prolog.force_linear_sample_interp =
1963 sel->info.uses_linear_center || sel->info.uses_linear_centroid;
1964 } else if (rs->multisample_enable && sctx->framebuffer.nr_samples > 1) {
1965 key->part.ps.prolog.bc_optimize_for_persp =
1966 sel->info.uses_persp_center && sel->info.uses_persp_centroid;
1967 key->part.ps.prolog.bc_optimize_for_linear =
1968 sel->info.uses_linear_center && sel->info.uses_linear_centroid;
1969 } else {
1970 /* Make sure SPI doesn't compute more than 1 pair
1971 * of (i,j), which is the optimization here. */
1972 key->part.ps.prolog.force_persp_center_interp = sel->info.uses_persp_center +
1973 sel->info.uses_persp_centroid +
1974 sel->info.uses_persp_sample >
1975 1;
1976
1977 key->part.ps.prolog.force_linear_center_interp = sel->info.uses_linear_center +
1978 sel->info.uses_linear_centroid +
1979 sel->info.uses_linear_sample >
1980 1;
1981
1982 if (sel->info.uses_persp_opcode_interp_sample ||
1983 sel->info.uses_linear_opcode_interp_sample)
1984 key->mono.u.ps.interpolate_at_sample_force_center = 1;
1985 }
1986
1987 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
1988
1989 /* ps_uses_fbfetch is true only if the color buffer is bound. */
1990 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
1991 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
1992 struct pipe_resource *tex = cb0->texture;
1993
1994 /* 1D textures are allocated and used as 2D on GFX9. */
1995 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
1996 key->mono.u.ps.fbfetch_is_1D =
1997 sctx->chip_class != GFX9 &&
1998 (tex->target == PIPE_TEXTURE_1D || tex->target == PIPE_TEXTURE_1D_ARRAY);
1999 key->mono.u.ps.fbfetch_layered =
2000 tex->target == PIPE_TEXTURE_1D_ARRAY || tex->target == PIPE_TEXTURE_2D_ARRAY ||
2001 tex->target == PIPE_TEXTURE_CUBE || tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2002 tex->target == PIPE_TEXTURE_3D;
2003 }
2004 break;
2005 }
2006 default:
2007 assert(0);
2008 }
2009
2010 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2011 memset(&key->opt, 0, sizeof(key->opt));
2012 }
2013
2014 static void si_build_shader_variant(struct si_shader *shader, int thread_index, bool low_priority)
2015 {
2016 struct si_shader_selector *sel = shader->selector;
2017 struct si_screen *sscreen = sel->screen;
2018 struct ac_llvm_compiler *compiler;
2019 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2020
2021 if (thread_index >= 0) {
2022 if (low_priority) {
2023 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2024 compiler = &sscreen->compiler_lowp[thread_index];
2025 } else {
2026 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2027 compiler = &sscreen->compiler[thread_index];
2028 }
2029 if (!debug->async)
2030 debug = NULL;
2031 } else {
2032 assert(!low_priority);
2033 compiler = shader->compiler_ctx_state.compiler;
2034 }
2035
2036 if (!compiler->passes)
2037 si_init_compiler(sscreen, compiler);
2038
2039 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2040 PRINT_ERR("Failed to build shader variant (type=%u)\n", sel->type);
2041 shader->compilation_failed = true;
2042 return;
2043 }
2044
2045 if (shader->compiler_ctx_state.is_debug_context) {
2046 FILE *f = open_memstream(&shader->shader_log, &shader->shader_log_size);
2047 if (f) {
2048 si_shader_dump(sscreen, shader, NULL, f, false);
2049 fclose(f);
2050 }
2051 }
2052
2053 si_shader_init_pm4_state(sscreen, shader);
2054 }
2055
2056 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2057 {
2058 struct si_shader *shader = (struct si_shader *)job;
2059
2060 assert(thread_index >= 0);
2061
2062 si_build_shader_variant(shader, thread_index, true);
2063 }
2064
2065 static const struct si_shader_key zeroed;
2066
2067 static bool si_check_missing_main_part(struct si_screen *sscreen, struct si_shader_selector *sel,
2068 struct si_compiler_ctx_state *compiler_state,
2069 struct si_shader_key *key)
2070 {
2071 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2072
2073 if (!*mainp) {
2074 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2075
2076 if (!main_part)
2077 return false;
2078
2079 /* We can leave the fence as permanently signaled because the
2080 * main part becomes visible globally only after it has been
2081 * compiled. */
2082 util_queue_fence_init(&main_part->ready);
2083
2084 main_part->selector = sel;
2085 main_part->key.as_es = key->as_es;
2086 main_part->key.as_ls = key->as_ls;
2087 main_part->key.as_ngg = key->as_ngg;
2088 main_part->is_monolithic = false;
2089
2090 if (!si_compile_shader(sscreen, compiler_state->compiler, main_part,
2091 &compiler_state->debug)) {
2092 FREE(main_part);
2093 return false;
2094 }
2095 *mainp = main_part;
2096 }
2097 return true;
2098 }
2099
2100 /**
2101 * Select a shader variant according to the shader key.
2102 *
2103 * \param optimized_or_none If the key describes an optimized shader variant and
2104 * the compilation isn't finished, don't select any
2105 * shader and return an error.
2106 */
2107 int si_shader_select_with_key(struct si_screen *sscreen, struct si_shader_ctx_state *state,
2108 struct si_compiler_ctx_state *compiler_state,
2109 struct si_shader_key *key, int thread_index, bool optimized_or_none)
2110 {
2111 struct si_shader_selector *sel = state->cso;
2112 struct si_shader_selector *previous_stage_sel = NULL;
2113 struct si_shader *current = state->current;
2114 struct si_shader *iter, *shader = NULL;
2115
2116 again:
2117 /* Check if we don't need to change anything.
2118 * This path is also used for most shaders that don't need multiple
2119 * variants, it will cost just a computation of the key and this
2120 * test. */
2121 if (likely(current && memcmp(&current->key, key, sizeof(*key)) == 0)) {
2122 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2123 if (current->is_optimized) {
2124 if (optimized_or_none)
2125 return -1;
2126
2127 memset(&key->opt, 0, sizeof(key->opt));
2128 goto current_not_ready;
2129 }
2130
2131 util_queue_fence_wait(&current->ready);
2132 }
2133
2134 return current->compilation_failed ? -1 : 0;
2135 }
2136 current_not_ready:
2137
2138 /* This must be done before the mutex is locked, because async GS
2139 * compilation calls this function too, and therefore must enter
2140 * the mutex first.
2141 *
2142 * Only wait if we are in a draw call. Don't wait if we are
2143 * in a compiler thread.
2144 */
2145 if (thread_index < 0)
2146 util_queue_fence_wait(&sel->ready);
2147
2148 simple_mtx_lock(&sel->mutex);
2149
2150 /* Find the shader variant. */
2151 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2152 /* Don't check the "current" shader. We checked it above. */
2153 if (current != iter && memcmp(&iter->key, key, sizeof(*key)) == 0) {
2154 simple_mtx_unlock(&sel->mutex);
2155
2156 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2157 /* If it's an optimized shader and its compilation has
2158 * been started but isn't done, use the unoptimized
2159 * shader so as not to cause a stall due to compilation.
2160 */
2161 if (iter->is_optimized) {
2162 if (optimized_or_none)
2163 return -1;
2164 memset(&key->opt, 0, sizeof(key->opt));
2165 goto again;
2166 }
2167
2168 util_queue_fence_wait(&iter->ready);
2169 }
2170
2171 if (iter->compilation_failed) {
2172 return -1; /* skip the draw call */
2173 }
2174
2175 state->current = iter;
2176 return 0;
2177 }
2178 }
2179
2180 /* Build a new shader. */
2181 shader = CALLOC_STRUCT(si_shader);
2182 if (!shader) {
2183 simple_mtx_unlock(&sel->mutex);
2184 return -ENOMEM;
2185 }
2186
2187 util_queue_fence_init(&shader->ready);
2188
2189 shader->selector = sel;
2190 shader->key = *key;
2191 shader->compiler_ctx_state = *compiler_state;
2192
2193 /* If this is a merged shader, get the first shader's selector. */
2194 if (sscreen->info.chip_class >= GFX9) {
2195 if (sel->type == PIPE_SHADER_TESS_CTRL)
2196 previous_stage_sel = key->part.tcs.ls;
2197 else if (sel->type == PIPE_SHADER_GEOMETRY)
2198 previous_stage_sel = key->part.gs.es;
2199
2200 /* We need to wait for the previous shader. */
2201 if (previous_stage_sel && thread_index < 0)
2202 util_queue_fence_wait(&previous_stage_sel->ready);
2203 }
2204
2205 bool is_pure_monolithic =
2206 sscreen->use_monolithic_shaders || memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2207
2208 /* Compile the main shader part if it doesn't exist. This can happen
2209 * if the initial guess was wrong.
2210 *
2211 * The prim discard CS doesn't need the main shader part.
2212 */
2213 if (!is_pure_monolithic && !key->opt.vs_as_prim_discard_cs) {
2214 bool ok = true;
2215
2216 /* Make sure the main shader part is present. This is needed
2217 * for shaders that can be compiled as VS, LS, or ES, and only
2218 * one of them is compiled at creation.
2219 *
2220 * It is also needed for GS, which can be compiled as non-NGG
2221 * and NGG.
2222 *
2223 * For merged shaders, check that the starting shader's main
2224 * part is present.
2225 */
2226 if (previous_stage_sel) {
2227 struct si_shader_key shader1_key = zeroed;
2228
2229 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2230 shader1_key.as_ls = 1;
2231 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2232 shader1_key.as_es = 1;
2233 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2234 } else {
2235 assert(0);
2236 }
2237
2238 simple_mtx_lock(&previous_stage_sel->mutex);
2239 ok = si_check_missing_main_part(sscreen, previous_stage_sel, compiler_state, &shader1_key);
2240 simple_mtx_unlock(&previous_stage_sel->mutex);
2241 }
2242
2243 if (ok) {
2244 ok = si_check_missing_main_part(sscreen, sel, compiler_state, key);
2245 }
2246
2247 if (!ok) {
2248 FREE(shader);
2249 simple_mtx_unlock(&sel->mutex);
2250 return -ENOMEM; /* skip the draw call */
2251 }
2252 }
2253
2254 /* Keep the reference to the 1st shader of merged shaders, so that
2255 * Gallium can't destroy it before we destroy the 2nd shader.
2256 *
2257 * Set sctx = NULL, because it's unused if we're not releasing
2258 * the shader, and we don't have any sctx here.
2259 */
2260 si_shader_selector_reference(NULL, &shader->previous_stage_sel, previous_stage_sel);
2261
2262 /* Monolithic-only shaders don't make a distinction between optimized
2263 * and unoptimized. */
2264 shader->is_monolithic =
2265 is_pure_monolithic || memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2266
2267 /* The prim discard CS is always optimized. */
2268 shader->is_optimized = (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2269 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2270
2271 /* If it's an optimized shader, compile it asynchronously. */
2272 if (shader->is_optimized && thread_index < 0) {
2273 /* Compile it asynchronously. */
2274 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority, shader, &shader->ready,
2275 si_build_shader_variant_low_priority, NULL, 0);
2276
2277 /* Add only after the ready fence was reset, to guard against a
2278 * race with si_bind_XX_shader. */
2279 if (!sel->last_variant) {
2280 sel->first_variant = shader;
2281 sel->last_variant = shader;
2282 } else {
2283 sel->last_variant->next_variant = shader;
2284 sel->last_variant = shader;
2285 }
2286
2287 /* Use the default (unoptimized) shader for now. */
2288 memset(&key->opt, 0, sizeof(key->opt));
2289 simple_mtx_unlock(&sel->mutex);
2290
2291 if (sscreen->options.sync_compile)
2292 util_queue_fence_wait(&shader->ready);
2293
2294 if (optimized_or_none)
2295 return -1;
2296 goto again;
2297 }
2298
2299 /* Reset the fence before adding to the variant list. */
2300 util_queue_fence_reset(&shader->ready);
2301
2302 if (!sel->last_variant) {
2303 sel->first_variant = shader;
2304 sel->last_variant = shader;
2305 } else {
2306 sel->last_variant->next_variant = shader;
2307 sel->last_variant = shader;
2308 }
2309
2310 simple_mtx_unlock(&sel->mutex);
2311
2312 assert(!shader->is_optimized);
2313 si_build_shader_variant(shader, thread_index, false);
2314
2315 util_queue_fence_signal(&shader->ready);
2316
2317 if (!shader->compilation_failed)
2318 state->current = shader;
2319
2320 return shader->compilation_failed ? -1 : 0;
2321 }
2322
2323 static int si_shader_select(struct pipe_context *ctx, struct si_shader_ctx_state *state,
2324 union si_vgt_stages_key stages_key,
2325 struct si_compiler_ctx_state *compiler_state)
2326 {
2327 struct si_context *sctx = (struct si_context *)ctx;
2328 struct si_shader_key key;
2329
2330 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2331 return si_shader_select_with_key(sctx->screen, state, compiler_state, &key, -1, false);
2332 }
2333
2334 static void si_parse_next_shader_property(const struct si_shader_info *info, bool streamout,
2335 struct si_shader_key *key)
2336 {
2337 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2338
2339 switch (info->processor) {
2340 case PIPE_SHADER_VERTEX:
2341 switch (next_shader) {
2342 case PIPE_SHADER_GEOMETRY:
2343 key->as_es = 1;
2344 break;
2345 case PIPE_SHADER_TESS_CTRL:
2346 case PIPE_SHADER_TESS_EVAL:
2347 key->as_ls = 1;
2348 break;
2349 default:
2350 /* If POSITION isn't written, it can only be a HW VS
2351 * if streamout is used. If streamout isn't used,
2352 * assume that it's a HW LS. (the next shader is TCS)
2353 * This heuristic is needed for separate shader objects.
2354 */
2355 if (!info->writes_position && !streamout)
2356 key->as_ls = 1;
2357 }
2358 break;
2359
2360 case PIPE_SHADER_TESS_EVAL:
2361 if (next_shader == PIPE_SHADER_GEOMETRY || !info->writes_position)
2362 key->as_es = 1;
2363 break;
2364 }
2365 }
2366
2367 /**
2368 * Compile the main shader part or the monolithic shader as part of
2369 * si_shader_selector initialization. Since it can be done asynchronously,
2370 * there is no way to report compile failures to applications.
2371 */
2372 static void si_init_shader_selector_async(void *job, int thread_index)
2373 {
2374 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2375 struct si_screen *sscreen = sel->screen;
2376 struct ac_llvm_compiler *compiler;
2377 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2378
2379 assert(!debug->debug_message || debug->async);
2380 assert(thread_index >= 0);
2381 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2382 compiler = &sscreen->compiler[thread_index];
2383
2384 if (!compiler->passes)
2385 si_init_compiler(sscreen, compiler);
2386
2387 /* Serialize NIR to save memory. Monolithic shader variants
2388 * have to deserialize NIR before compilation.
2389 */
2390 if (sel->nir) {
2391 struct blob blob;
2392 size_t size;
2393
2394 blob_init(&blob);
2395 /* true = remove optional debugging data to increase
2396 * the likehood of getting more shader cache hits.
2397 * It also drops variable names, so we'll save more memory.
2398 */
2399 nir_serialize(&blob, sel->nir, true);
2400 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2401 sel->nir_size = size;
2402 }
2403
2404 /* Compile the main shader part for use with a prolog and/or epilog.
2405 * If this fails, the driver will try to compile a monolithic shader
2406 * on demand.
2407 */
2408 if (!sscreen->use_monolithic_shaders) {
2409 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2410 unsigned char ir_sha1_cache_key[20];
2411
2412 if (!shader) {
2413 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2414 return;
2415 }
2416
2417 /* We can leave the fence signaled because use of the default
2418 * main part is guarded by the selector's ready fence. */
2419 util_queue_fence_init(&shader->ready);
2420
2421 shader->selector = sel;
2422 shader->is_monolithic = false;
2423 si_parse_next_shader_property(&sel->info, sel->so.num_outputs != 0, &shader->key);
2424
2425 if (sscreen->use_ngg && (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2426 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2427 sel->type == PIPE_SHADER_TESS_EVAL || sel->type == PIPE_SHADER_GEOMETRY))
2428 shader->key.as_ngg = 1;
2429
2430 if (sel->nir) {
2431 si_get_ir_cache_key(sel, shader->key.as_ngg, shader->key.as_es, ir_sha1_cache_key);
2432 }
2433
2434 /* Try to load the shader from the shader cache. */
2435 simple_mtx_lock(&sscreen->shader_cache_mutex);
2436
2437 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2438 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2439 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2440 } else {
2441 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2442
2443 /* Compile the shader if it hasn't been loaded from the cache. */
2444 if (!si_compile_shader(sscreen, compiler, shader, debug)) {
2445 FREE(shader);
2446 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2447 return;
2448 }
2449
2450 simple_mtx_lock(&sscreen->shader_cache_mutex);
2451 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key, shader, true);
2452 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2453 }
2454
2455 *si_get_main_shader_part(sel, &shader->key) = shader;
2456
2457 /* Unset "outputs_written" flags for outputs converted to
2458 * DEFAULT_VAL, so that later inter-shader optimizations don't
2459 * try to eliminate outputs that don't exist in the final
2460 * shader.
2461 *
2462 * This is only done if non-monolithic shaders are enabled.
2463 */
2464 if ((sel->type == PIPE_SHADER_VERTEX || sel->type == PIPE_SHADER_TESS_EVAL) &&
2465 !shader->key.as_ls && !shader->key.as_es) {
2466 unsigned i;
2467
2468 for (i = 0; i < sel->info.num_outputs; i++) {
2469 unsigned offset = shader->info.vs_output_param_offset[i];
2470
2471 if (offset <= AC_EXP_PARAM_OFFSET_31)
2472 continue;
2473
2474 unsigned name = sel->info.output_semantic_name[i];
2475 unsigned index = sel->info.output_semantic_index[i];
2476 unsigned id;
2477
2478 switch (name) {
2479 case TGSI_SEMANTIC_GENERIC:
2480 /* don't process indices the function can't handle */
2481 if (index >= SI_MAX_IO_GENERIC)
2482 break;
2483 /* fall through */
2484 default:
2485 id = si_shader_io_get_unique_index(name, index, true);
2486 sel->outputs_written_before_ps &= ~(1ull << id);
2487 break;
2488 case TGSI_SEMANTIC_POSITION: /* ignore these */
2489 case TGSI_SEMANTIC_PSIZE:
2490 case TGSI_SEMANTIC_CLIPVERTEX:
2491 case TGSI_SEMANTIC_EDGEFLAG:
2492 break;
2493 }
2494 }
2495 }
2496 }
2497
2498 /* The GS copy shader is always pre-compiled. */
2499 if (sel->type == PIPE_SHADER_GEOMETRY &&
2500 (!sscreen->use_ngg || !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2501 sel->tess_turns_off_ngg)) {
2502 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2503 if (!sel->gs_copy_shader) {
2504 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2505 return;
2506 }
2507
2508 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2509 }
2510
2511 /* Free NIR. We only keep serialized NIR after this point. */
2512 if (sel->nir) {
2513 ralloc_free(sel->nir);
2514 sel->nir = NULL;
2515 }
2516 }
2517
2518 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2519 struct util_queue_fence *ready_fence,
2520 struct si_compiler_ctx_state *compiler_ctx_state, void *job,
2521 util_queue_execute_func execute)
2522 {
2523 util_queue_fence_init(ready_fence);
2524
2525 struct util_async_debug_callback async_debug;
2526 bool debug = (sctx->debug.debug_message && !sctx->debug.async) || sctx->is_debug ||
2527 si_can_dump_shader(sctx->screen, processor);
2528
2529 if (debug) {
2530 u_async_debug_init(&async_debug);
2531 compiler_ctx_state->debug = async_debug.base;
2532 }
2533
2534 util_queue_add_job(&sctx->screen->shader_compiler_queue, job, ready_fence, execute, NULL, 0);
2535
2536 if (debug) {
2537 util_queue_fence_wait(ready_fence);
2538 u_async_debug_drain(&async_debug, &sctx->debug);
2539 u_async_debug_cleanup(&async_debug);
2540 }
2541
2542 if (sctx->screen->options.sync_compile)
2543 util_queue_fence_wait(ready_fence);
2544 }
2545
2546 /* Return descriptor slot usage masks from the given shader info. */
2547 void si_get_active_slot_masks(const struct si_shader_info *info, uint64_t *const_and_shader_buffers,
2548 uint64_t *samplers_and_images)
2549 {
2550 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2551
2552 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2553 num_constbufs = util_last_bit(info->const_buffers_declared);
2554 /* two 8-byte images share one 16-byte slot */
2555 num_images = align(util_last_bit(info->images_declared), 2);
2556 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2557 num_samplers = util_last_bit(info->samplers_declared);
2558
2559 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2560 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2561 *const_and_shader_buffers = u_bit_consecutive64(start, num_shaderbufs + num_constbufs);
2562
2563 /* The layout is:
2564 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2565 * - image[last] ... image[0] go to [31-last .. 31]
2566 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2567 *
2568 * FMASKs for images are placed separately, because MSAA images are rare,
2569 * and so we can benefit from a better cache hit rate if we keep image
2570 * descriptors together.
2571 */
2572 if (num_msaa_images)
2573 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2574
2575 start = si_get_image_slot(num_images - 1) / 2;
2576 *samplers_and_images = u_bit_consecutive64(start, num_images / 2 + num_samplers);
2577 }
2578
2579 static void *si_create_shader_selector(struct pipe_context *ctx,
2580 const struct pipe_shader_state *state)
2581 {
2582 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2583 struct si_context *sctx = (struct si_context *)ctx;
2584 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2585 int i;
2586
2587 if (!sel)
2588 return NULL;
2589
2590 sel->screen = sscreen;
2591 sel->compiler_ctx_state.debug = sctx->debug;
2592 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2593
2594 sel->so = state->stream_output;
2595
2596 if (state->type == PIPE_SHADER_IR_TGSI) {
2597 sel->nir = tgsi_to_nir(state->tokens, ctx->screen, true);
2598 } else {
2599 assert(state->type == PIPE_SHADER_IR_NIR);
2600 sel->nir = state->ir.nir;
2601 }
2602
2603 si_nir_scan_shader(sel->nir, &sel->info);
2604
2605 sel->type = sel->info.processor;
2606 p_atomic_inc(&sscreen->num_shaders_created);
2607 si_get_active_slot_masks(&sel->info, &sel->active_const_and_shader_buffers,
2608 &sel->active_samplers_and_images);
2609
2610 /* Record which streamout buffers are enabled. */
2611 for (i = 0; i < sel->so.num_outputs; i++) {
2612 sel->enabled_streamout_buffer_mask |= (1 << sel->so.output[i].output_buffer)
2613 << (sel->so.output[i].stream * 4);
2614 }
2615
2616 sel->num_vs_inputs =
2617 sel->type == PIPE_SHADER_VERTEX && !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]
2618 ? sel->info.num_inputs
2619 : 0;
2620 sel->num_vbos_in_user_sgprs = MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2621
2622 /* The prolog is a no-op if there are no inputs. */
2623 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX && sel->info.num_inputs &&
2624 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2625
2626 sel->prim_discard_cs_allowed =
2627 sel->type == PIPE_SHADER_VERTEX && !sel->info.uses_bindless_images &&
2628 !sel->info.uses_bindless_samplers && !sel->info.writes_memory &&
2629 !sel->info.writes_viewport_index &&
2630 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] && !sel->so.num_outputs;
2631
2632 switch (sel->type) {
2633 case PIPE_SHADER_GEOMETRY:
2634 sel->gs_output_prim = sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2635
2636 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2637 sel->rast_prim = sel->gs_output_prim;
2638 if (util_rast_prim_is_triangles(sel->rast_prim))
2639 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2640
2641 sel->gs_max_out_vertices = sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2642 sel->gs_num_invocations = sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2643 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2644 sel->max_gsvs_emit_size = sel->gsvs_vertex_size * sel->gs_max_out_vertices;
2645
2646 sel->max_gs_stream = 0;
2647 for (i = 0; i < sel->so.num_outputs; i++)
2648 sel->max_gs_stream = MAX2(sel->max_gs_stream, sel->so.output[i].stream);
2649
2650 sel->gs_input_verts_per_prim =
2651 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2652
2653 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation so
2654 * we can't split workgroups. Disable ngg if any of the following conditions is true:
2655 * - num_invocations * gs_max_out_vertices > 256
2656 * - LDS usage is too high
2657 */
2658 sel->tess_turns_off_ngg = sscreen->info.chip_class >= GFX10 &&
2659 (sel->gs_num_invocations * sel->gs_max_out_vertices > 256 ||
2660 sel->gs_num_invocations * sel->gs_max_out_vertices *
2661 (sel->info.num_outputs * 4 + 1) > 6500 /* max dw per GS primitive */);
2662 break;
2663
2664 case PIPE_SHADER_TESS_CTRL:
2665 /* Always reserve space for these. */
2666 sel->patch_outputs_written |=
2667 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2668 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2669 /* fall through */
2670 case PIPE_SHADER_VERTEX:
2671 case PIPE_SHADER_TESS_EVAL:
2672 for (i = 0; i < sel->info.num_outputs; i++) {
2673 unsigned name = sel->info.output_semantic_name[i];
2674 unsigned index = sel->info.output_semantic_index[i];
2675
2676 switch (name) {
2677 case TGSI_SEMANTIC_TESSINNER:
2678 case TGSI_SEMANTIC_TESSOUTER:
2679 case TGSI_SEMANTIC_PATCH:
2680 sel->patch_outputs_written |= 1ull << si_shader_io_get_unique_index_patch(name, index);
2681 break;
2682
2683 case TGSI_SEMANTIC_GENERIC:
2684 /* don't process indices the function can't handle */
2685 if (index >= SI_MAX_IO_GENERIC)
2686 break;
2687 /* fall through */
2688 default:
2689 sel->outputs_written |= 1ull << si_shader_io_get_unique_index(name, index, false);
2690 sel->outputs_written_before_ps |= 1ull
2691 << si_shader_io_get_unique_index(name, index, true);
2692 break;
2693 case TGSI_SEMANTIC_EDGEFLAG:
2694 break;
2695 }
2696 }
2697 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2698 sel->lshs_vertex_stride = sel->esgs_itemsize;
2699
2700 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2701 * will start on a different bank. (except for the maximum 32*16).
2702 */
2703 if (sel->lshs_vertex_stride < 32 * 16)
2704 sel->lshs_vertex_stride += 4;
2705
2706 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2707 * conflicts, i.e. each vertex will start at a different bank.
2708 */
2709 if (sctx->chip_class >= GFX9)
2710 sel->esgs_itemsize += 4;
2711
2712 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2713
2714 /* Only for TES: */
2715 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2716 sel->rast_prim = PIPE_PRIM_POINTS;
2717 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2718 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2719 else
2720 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2721 break;
2722
2723 case PIPE_SHADER_FRAGMENT:
2724 for (i = 0; i < sel->info.num_inputs; i++) {
2725 unsigned name = sel->info.input_semantic_name[i];
2726 unsigned index = sel->info.input_semantic_index[i];
2727
2728 switch (name) {
2729 case TGSI_SEMANTIC_GENERIC:
2730 /* don't process indices the function can't handle */
2731 if (index >= SI_MAX_IO_GENERIC)
2732 break;
2733 /* fall through */
2734 default:
2735 sel->inputs_read |= 1ull << si_shader_io_get_unique_index(name, index, true);
2736 break;
2737 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2738 break;
2739 }
2740 }
2741
2742 for (i = 0; i < 8; i++)
2743 if (sel->info.colors_written & (1 << i))
2744 sel->colors_written_4bit |= 0xf << (4 * i);
2745
2746 for (i = 0; i < sel->info.num_inputs; i++) {
2747 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2748 int index = sel->info.input_semantic_index[i];
2749 sel->color_attr_index[index] = i;
2750 }
2751 }
2752 break;
2753 default:;
2754 }
2755
2756 sel->ngg_culling_allowed =
2757 sscreen->info.chip_class >= GFX10 &&
2758 sscreen->info.has_dedicated_vram &&
2759 sscreen->use_ngg_culling &&
2760 (sel->type == PIPE_SHADER_VERTEX ||
2761 (sel->type == PIPE_SHADER_TESS_EVAL &&
2762 (sscreen->always_use_ngg_culling_all ||
2763 sscreen->always_use_ngg_culling_tess))) &&
2764 sel->info.writes_position &&
2765 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
2766 !sel->info.writes_memory && !sel->so.num_outputs &&
2767 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] &&
2768 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2769
2770 /* PA_CL_VS_OUT_CNTL */
2771 if (sctx->chip_class <= GFX9)
2772 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2773
2774 sel->clipdist_mask = sel->info.writes_clipvertex ? SIX_BITS : sel->info.clipdist_writemask;
2775 sel->culldist_mask = sel->info.culldist_writemask << sel->info.num_written_clipdistance;
2776
2777 /* DB_SHADER_CONTROL */
2778 sel->db_shader_control = S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2779 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2780 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2781 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2782
2783 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2784 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2785 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2786 break;
2787 case TGSI_FS_DEPTH_LAYOUT_LESS:
2788 sel->db_shader_control |= S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2789 break;
2790 }
2791
2792 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2793 *
2794 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2795 * --|-----------|------------|------------|--------------------|-------------------|-------------
2796 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2797 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2798 * 2 | false | true | n/a | LateZ | 1 | 0
2799 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2800 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2801 *
2802 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2803 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2804 *
2805 * Don't use ReZ without profiling !!!
2806 *
2807 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2808 * shaders.
2809 */
2810 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2811 /* Cases 3, 4. */
2812 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2813 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2814 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2815 } else if (sel->info.writes_memory) {
2816 /* Case 2. */
2817 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) | S_02880C_EXEC_ON_HIER_FAIL(1);
2818 } else {
2819 /* Case 1. */
2820 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2821 }
2822
2823 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2824 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2825
2826 (void)simple_mtx_init(&sel->mutex, mtx_plain);
2827
2828 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready, &sel->compiler_ctx_state,
2829 sel, si_init_shader_selector_async);
2830 return sel;
2831 }
2832
2833 static void *si_create_shader(struct pipe_context *ctx, const struct pipe_shader_state *state)
2834 {
2835 struct si_context *sctx = (struct si_context *)ctx;
2836 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2837 bool cache_hit;
2838 struct si_shader_selector *sel = (struct si_shader_selector *)util_live_shader_cache_get(
2839 ctx, &sscreen->live_shader_cache, state, &cache_hit);
2840
2841 if (sel && cache_hit && sctx->debug.debug_message) {
2842 if (sel->main_shader_part)
2843 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part, &sctx->debug);
2844 if (sel->main_shader_part_ls)
2845 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ls, &sctx->debug);
2846 if (sel->main_shader_part_es)
2847 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_es, &sctx->debug);
2848 if (sel->main_shader_part_ngg)
2849 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg, &sctx->debug);
2850 if (sel->main_shader_part_ngg_es)
2851 si_shader_dump_stats_for_shader_db(sscreen, sel->main_shader_part_ngg_es, &sctx->debug);
2852 }
2853 return sel;
2854 }
2855
2856 static void si_update_streamout_state(struct si_context *sctx)
2857 {
2858 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2859
2860 if (!shader_with_so)
2861 return;
2862
2863 sctx->streamout.enabled_stream_buffers_mask = shader_with_so->enabled_streamout_buffer_mask;
2864 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2865 }
2866
2867 static void si_update_clip_regs(struct si_context *sctx, struct si_shader_selector *old_hw_vs,
2868 struct si_shader *old_hw_vs_variant,
2869 struct si_shader_selector *next_hw_vs,
2870 struct si_shader *next_hw_vs_variant)
2871 {
2872 if (next_hw_vs &&
2873 (!old_hw_vs ||
2874 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2875 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2876 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2877 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2878 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask || !old_hw_vs_variant ||
2879 !next_hw_vs_variant ||
2880 old_hw_vs_variant->key.opt.clip_disable != next_hw_vs_variant->key.opt.clip_disable))
2881 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2882 }
2883
2884 static void si_update_common_shader_state(struct si_context *sctx)
2885 {
2886 sctx->uses_bindless_samplers = si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2887 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2888 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2889 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2890 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2891 sctx->uses_bindless_images = si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2892 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2893 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2894 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2895 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2896 sctx->do_update_shaders = true;
2897 }
2898
2899 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2900 {
2901 struct si_context *sctx = (struct si_context *)ctx;
2902 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2903 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2904 struct si_shader_selector *sel = state;
2905
2906 if (sctx->vs_shader.cso == sel)
2907 return;
2908
2909 sctx->vs_shader.cso = sel;
2910 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2911 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
2912
2913 if (si_update_ngg(sctx))
2914 si_shader_change_notify(sctx);
2915
2916 si_update_common_shader_state(sctx);
2917 si_update_vs_viewport_state(sctx);
2918 si_set_active_descriptors_for_shader(sctx, sel);
2919 si_update_streamout_state(sctx);
2920 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso,
2921 si_get_vs_state(sctx));
2922 }
2923
2924 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2925 {
2926 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2927 (sctx->tes_shader.cso && sctx->tes_shader.cso->info.uses_primid) ||
2928 (sctx->tcs_shader.cso && sctx->tcs_shader.cso->info.uses_primid) ||
2929 (sctx->gs_shader.cso && sctx->gs_shader.cso->info.uses_primid) ||
2930 (sctx->ps_shader.cso && !sctx->gs_shader.cso && sctx->ps_shader.cso->info.uses_primid);
2931 }
2932
2933 bool si_update_ngg(struct si_context *sctx)
2934 {
2935 if (!sctx->screen->use_ngg) {
2936 assert(!sctx->ngg);
2937 return false;
2938 }
2939
2940 bool new_ngg = true;
2941
2942 if (sctx->gs_shader.cso && sctx->tes_shader.cso && sctx->gs_shader.cso->tess_turns_off_ngg) {
2943 new_ngg = false;
2944 } else if (!sctx->screen->use_ngg_streamout) {
2945 struct si_shader_selector *last = si_get_vs(sctx)->cso;
2946
2947 if ((last && last->so.num_outputs) || sctx->streamout.prims_gen_query_enabled)
2948 new_ngg = false;
2949 }
2950
2951 if (new_ngg != sctx->ngg) {
2952 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
2953 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
2954 * pointers are set.
2955 */
2956 if (sctx->chip_class == GFX10 && !new_ngg)
2957 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
2958
2959 sctx->ngg = new_ngg;
2960 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
2961 return true;
2962 }
2963 return false;
2964 }
2965
2966 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
2967 {
2968 struct si_context *sctx = (struct si_context *)ctx;
2969 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2970 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2971 struct si_shader_selector *sel = state;
2972 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
2973 bool ngg_changed;
2974
2975 if (sctx->gs_shader.cso == sel)
2976 return;
2977
2978 sctx->gs_shader.cso = sel;
2979 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
2980 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
2981
2982 si_update_common_shader_state(sctx);
2983 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
2984
2985 ngg_changed = si_update_ngg(sctx);
2986 if (ngg_changed || enable_changed)
2987 si_shader_change_notify(sctx);
2988 if (enable_changed) {
2989 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
2990 si_update_tess_uses_prim_id(sctx);
2991 }
2992 si_update_vs_viewport_state(sctx);
2993 si_set_active_descriptors_for_shader(sctx, sel);
2994 si_update_streamout_state(sctx);
2995 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso,
2996 si_get_vs_state(sctx));
2997 }
2998
2999 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3000 {
3001 struct si_context *sctx = (struct si_context *)ctx;
3002 struct si_shader_selector *sel = state;
3003 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3004
3005 if (sctx->tcs_shader.cso == sel)
3006 return;
3007
3008 sctx->tcs_shader.cso = sel;
3009 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3010 si_update_tess_uses_prim_id(sctx);
3011
3012 si_update_common_shader_state(sctx);
3013
3014 if (enable_changed)
3015 sctx->last_tcs = NULL; /* invalidate derived tess state */
3016
3017 si_set_active_descriptors_for_shader(sctx, sel);
3018 }
3019
3020 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3021 {
3022 struct si_context *sctx = (struct si_context *)ctx;
3023 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3024 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3025 struct si_shader_selector *sel = state;
3026 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3027
3028 if (sctx->tes_shader.cso == sel)
3029 return;
3030
3031 sctx->tes_shader.cso = sel;
3032 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3033 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3034 si_update_tess_uses_prim_id(sctx);
3035
3036 si_update_common_shader_state(sctx);
3037 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3038
3039 bool ngg_changed = si_update_ngg(sctx);
3040 if (ngg_changed || enable_changed)
3041 si_shader_change_notify(sctx);
3042 if (enable_changed)
3043 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3044 si_update_vs_viewport_state(sctx);
3045 si_set_active_descriptors_for_shader(sctx, sel);
3046 si_update_streamout_state(sctx);
3047 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant, si_get_vs(sctx)->cso,
3048 si_get_vs_state(sctx));
3049 }
3050
3051 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3052 {
3053 struct si_context *sctx = (struct si_context *)ctx;
3054 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3055 struct si_shader_selector *sel = state;
3056
3057 /* skip if supplied shader is one already in use */
3058 if (old_sel == sel)
3059 return;
3060
3061 sctx->ps_shader.cso = sel;
3062 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3063
3064 si_update_common_shader_state(sctx);
3065 if (sel) {
3066 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3067 si_update_tess_uses_prim_id(sctx);
3068
3069 if (!old_sel || old_sel->info.colors_written != sel->info.colors_written)
3070 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3071
3072 if (sctx->screen->has_out_of_order_rast &&
3073 (!old_sel || old_sel->info.writes_memory != sel->info.writes_memory ||
3074 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3075 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3076 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3077 }
3078 si_set_active_descriptors_for_shader(sctx, sel);
3079 si_update_ps_colorbuf0_slot(sctx);
3080 }
3081
3082 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3083 {
3084 if (shader->is_optimized) {
3085 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority, &shader->ready);
3086 }
3087
3088 util_queue_fence_destroy(&shader->ready);
3089
3090 if (shader->pm4) {
3091 /* If destroyed shaders were not unbound, the next compiled
3092 * shader variant could get the same pointer address and so
3093 * binding it to the same shader stage would be considered
3094 * a no-op, causing random behavior.
3095 */
3096 switch (shader->selector->type) {
3097 case PIPE_SHADER_VERTEX:
3098 if (shader->key.as_ls) {
3099 assert(sctx->chip_class <= GFX8);
3100 si_pm4_delete_state(sctx, ls, shader->pm4);
3101 } else if (shader->key.as_es) {
3102 assert(sctx->chip_class <= GFX8);
3103 si_pm4_delete_state(sctx, es, shader->pm4);
3104 } else if (shader->key.as_ngg) {
3105 si_pm4_delete_state(sctx, gs, shader->pm4);
3106 } else {
3107 si_pm4_delete_state(sctx, vs, shader->pm4);
3108 }
3109 break;
3110 case PIPE_SHADER_TESS_CTRL:
3111 si_pm4_delete_state(sctx, hs, shader->pm4);
3112 break;
3113 case PIPE_SHADER_TESS_EVAL:
3114 if (shader->key.as_es) {
3115 assert(sctx->chip_class <= GFX8);
3116 si_pm4_delete_state(sctx, es, shader->pm4);
3117 } else if (shader->key.as_ngg) {
3118 si_pm4_delete_state(sctx, gs, shader->pm4);
3119 } else {
3120 si_pm4_delete_state(sctx, vs, shader->pm4);
3121 }
3122 break;
3123 case PIPE_SHADER_GEOMETRY:
3124 if (shader->is_gs_copy_shader)
3125 si_pm4_delete_state(sctx, vs, shader->pm4);
3126 else
3127 si_pm4_delete_state(sctx, gs, shader->pm4);
3128 break;
3129 case PIPE_SHADER_FRAGMENT:
3130 si_pm4_delete_state(sctx, ps, shader->pm4);
3131 break;
3132 default:;
3133 }
3134 }
3135
3136 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3137 si_shader_destroy(shader);
3138 free(shader);
3139 }
3140
3141 static void si_destroy_shader_selector(struct pipe_context *ctx, void *cso)
3142 {
3143 struct si_context *sctx = (struct si_context *)ctx;
3144 struct si_shader_selector *sel = (struct si_shader_selector *)cso;
3145 struct si_shader *p = sel->first_variant, *c;
3146 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3147 [PIPE_SHADER_VERTEX] = &sctx->vs_shader, [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3148 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader, [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3149 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3150 };
3151
3152 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3153
3154 if (current_shader[sel->type]->cso == sel) {
3155 current_shader[sel->type]->cso = NULL;
3156 current_shader[sel->type]->current = NULL;
3157 }
3158
3159 while (p) {
3160 c = p->next_variant;
3161 si_delete_shader(sctx, p);
3162 p = c;
3163 }
3164
3165 if (sel->main_shader_part)
3166 si_delete_shader(sctx, sel->main_shader_part);
3167 if (sel->main_shader_part_ls)
3168 si_delete_shader(sctx, sel->main_shader_part_ls);
3169 if (sel->main_shader_part_es)
3170 si_delete_shader(sctx, sel->main_shader_part_es);
3171 if (sel->main_shader_part_ngg)
3172 si_delete_shader(sctx, sel->main_shader_part_ngg);
3173 if (sel->gs_copy_shader)
3174 si_delete_shader(sctx, sel->gs_copy_shader);
3175
3176 util_queue_fence_destroy(&sel->ready);
3177 simple_mtx_destroy(&sel->mutex);
3178 ralloc_free(sel->nir);
3179 free(sel->nir_binary);
3180 free(sel);
3181 }
3182
3183 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3184 {
3185 struct si_context *sctx = (struct si_context *)ctx;
3186 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3187
3188 si_shader_selector_reference(sctx, &sel, NULL);
3189 }
3190
3191 static unsigned si_get_ps_input_cntl(struct si_context *sctx, struct si_shader *vs, unsigned name,
3192 unsigned index, unsigned interpolate)
3193 {
3194 struct si_shader_info *vsinfo = &vs->selector->info;
3195 unsigned j, offset, ps_input_cntl = 0;
3196
3197 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3198 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) || name == TGSI_SEMANTIC_PRIMID)
3199 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3200
3201 if (name == TGSI_SEMANTIC_PCOORD ||
3202 (name == TGSI_SEMANTIC_TEXCOORD && sctx->sprite_coord_enable & (1 << index))) {
3203 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3204 }
3205
3206 for (j = 0; j < vsinfo->num_outputs; j++) {
3207 if (name == vsinfo->output_semantic_name[j] && index == vsinfo->output_semantic_index[j]) {
3208 offset = vs->info.vs_output_param_offset[j];
3209
3210 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3211 /* The input is loaded from parameter memory. */
3212 ps_input_cntl |= S_028644_OFFSET(offset);
3213 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3214 if (offset == AC_EXP_PARAM_UNDEFINED) {
3215 /* This can happen with depth-only rendering. */
3216 offset = 0;
3217 } else {
3218 /* The input is a DEFAULT_VAL constant. */
3219 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3220 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3221 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3222 }
3223
3224 ps_input_cntl = S_028644_OFFSET(0x20) | S_028644_DEFAULT_VAL(offset);
3225 }
3226 break;
3227 }
3228 }
3229
3230 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3231 /* PrimID is written after the last output when HW VS is used. */
3232 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3233 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3234 /* No corresponding output found, load defaults into input.
3235 * Don't set any other bits.
3236 * (FLAT_SHADE=1 completely changes behavior) */
3237 ps_input_cntl = S_028644_OFFSET(0x20);
3238 /* D3D 9 behaviour. GL is undefined */
3239 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3240 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3241 }
3242 return ps_input_cntl;
3243 }
3244
3245 static void si_emit_spi_map(struct si_context *sctx)
3246 {
3247 struct si_shader *ps = sctx->ps_shader.current;
3248 struct si_shader *vs = si_get_vs_state(sctx);
3249 struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3250 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3251 unsigned spi_ps_input_cntl[32];
3252
3253 if (!ps || !ps->selector->info.num_inputs)
3254 return;
3255
3256 num_interp = si_get_ps_num_interp(ps);
3257 assert(num_interp > 0);
3258
3259 for (i = 0; i < psinfo->num_inputs; i++) {
3260 unsigned name = psinfo->input_semantic_name[i];
3261 unsigned index = psinfo->input_semantic_index[i];
3262 unsigned interpolate = psinfo->input_interpolate[i];
3263
3264 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name, index, interpolate);
3265
3266 if (name == TGSI_SEMANTIC_COLOR) {
3267 assert(index < ARRAY_SIZE(bcol_interp));
3268 bcol_interp[index] = interpolate;
3269 }
3270 }
3271
3272 if (ps->key.part.ps.prolog.color_two_side) {
3273 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3274
3275 for (i = 0; i < 2; i++) {
3276 if (!(psinfo->colors_read & (0xf << (i * 4))))
3277 continue;
3278
3279 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3280 }
3281 }
3282 assert(num_interp == num_written);
3283
3284 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3285 /* Dota 2: Only ~16% of SPI map updates set different values. */
3286 /* Talos: Only ~9% of SPI map updates set different values. */
3287 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3288 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0, spi_ps_input_cntl,
3289 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3290
3291 if (initial_cdw != sctx->gfx_cs->current.cdw)
3292 sctx->context_roll = true;
3293 }
3294
3295 /**
3296 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3297 */
3298 static void si_cs_preamble_add_vgt_flush(struct si_context *sctx)
3299 {
3300 /* We shouldn't get here if registers are shadowed. */
3301 assert(!sctx->shadowed_regs);
3302
3303 if (sctx->cs_preamble_has_vgt_flush)
3304 return;
3305
3306 /* Done by Vulkan before VGT_FLUSH. */
3307 si_pm4_cmd_add(sctx->cs_preamble_state, PKT3(PKT3_EVENT_WRITE, 0, 0));
3308 si_pm4_cmd_add(sctx->cs_preamble_state, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3309
3310 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3311 si_pm4_cmd_add(sctx->cs_preamble_state, PKT3(PKT3_EVENT_WRITE, 0, 0));
3312 si_pm4_cmd_add(sctx->cs_preamble_state, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3313 sctx->cs_preamble_has_vgt_flush = true;
3314 }
3315
3316 /**
3317 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3318 */
3319 static void si_emit_vgt_flush(struct radeon_cmdbuf *cs)
3320 {
3321 /* This is required before VGT_FLUSH. */
3322 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3323 radeon_emit(cs, EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3324
3325 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3326 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3327 radeon_emit(cs, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3328 }
3329
3330 /* Initialize state related to ESGS / GSVS ring buffers */
3331 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3332 {
3333 struct si_shader_selector *es =
3334 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3335 struct si_shader_selector *gs = sctx->gs_shader.cso;
3336 struct si_pm4_state *pm4;
3337
3338 /* Chip constants. */
3339 unsigned num_se = sctx->screen->info.max_se;
3340 unsigned wave_size = 64;
3341 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3342 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3343 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3344 */
3345 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3346 unsigned alignment = 256 * num_se;
3347 /* The maximum size is 63.999 MB per SE. */
3348 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3349
3350 /* Calculate the minimum size. */
3351 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse * wave_size, alignment);
3352
3353 /* These are recommended sizes, not minimum sizes. */
3354 unsigned esgs_ring_size =
3355 max_gs_waves * 2 * wave_size * es->esgs_itemsize * gs->gs_input_verts_per_prim;
3356 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size * gs->max_gsvs_emit_size;
3357
3358 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3359 esgs_ring_size = align(esgs_ring_size, alignment);
3360 gsvs_ring_size = align(gsvs_ring_size, alignment);
3361
3362 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3363 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3364
3365 /* Some rings don't have to be allocated if shaders don't use them.
3366 * (e.g. no varyings between ES and GS or GS and VS)
3367 *
3368 * GFX9 doesn't have the ESGS ring.
3369 */
3370 bool update_esgs = sctx->chip_class <= GFX8 && esgs_ring_size &&
3371 (!sctx->esgs_ring || sctx->esgs_ring->width0 < esgs_ring_size);
3372 bool update_gsvs =
3373 gsvs_ring_size && (!sctx->gsvs_ring || sctx->gsvs_ring->width0 < gsvs_ring_size);
3374
3375 if (!update_esgs && !update_gsvs)
3376 return true;
3377
3378 if (update_esgs) {
3379 pipe_resource_reference(&sctx->esgs_ring, NULL);
3380 sctx->esgs_ring =
3381 pipe_aligned_buffer_create(sctx->b.screen, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
3382 esgs_ring_size, sctx->screen->info.pte_fragment_size);
3383 if (!sctx->esgs_ring)
3384 return false;
3385 }
3386
3387 if (update_gsvs) {
3388 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3389 sctx->gsvs_ring =
3390 pipe_aligned_buffer_create(sctx->b.screen, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT,
3391 gsvs_ring_size, sctx->screen->info.pte_fragment_size);
3392 if (!sctx->gsvs_ring)
3393 return false;
3394 }
3395
3396 /* Set ring bindings. */
3397 if (sctx->esgs_ring) {
3398 assert(sctx->chip_class <= GFX8);
3399 si_set_ring_buffer(sctx, SI_ES_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, true,
3400 true, 4, 64, 0);
3401 si_set_ring_buffer(sctx, SI_GS_RING_ESGS, sctx->esgs_ring, 0, sctx->esgs_ring->width0, false,
3402 false, 0, 0, 0);
3403 }
3404 if (sctx->gsvs_ring) {
3405 si_set_ring_buffer(sctx, SI_RING_GSVS, sctx->gsvs_ring, 0, sctx->gsvs_ring->width0, false,
3406 false, 0, 0, 0);
3407 }
3408
3409 if (sctx->shadowed_regs) {
3410 /* These registers will be shadowed, so set them only once. */
3411 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3412
3413 assert(sctx->chip_class >= GFX7);
3414
3415 si_emit_vgt_flush(cs);
3416
3417 /* Set the GS registers. */
3418 if (sctx->esgs_ring) {
3419 assert(sctx->chip_class <= GFX8);
3420 radeon_set_uconfig_reg(cs, R_030900_VGT_ESGS_RING_SIZE,
3421 sctx->esgs_ring->width0 / 256);
3422 }
3423 if (sctx->gsvs_ring) {
3424 radeon_set_uconfig_reg(cs, R_030904_VGT_GSVS_RING_SIZE,
3425 sctx->gsvs_ring->width0 / 256);
3426 }
3427 return true;
3428 }
3429
3430 /* The codepath without register shadowing. */
3431 /* Create the "cs_preamble_gs_rings" state. */
3432 pm4 = CALLOC_STRUCT(si_pm4_state);
3433 if (!pm4)
3434 return false;
3435
3436 if (sctx->chip_class >= GFX7) {
3437 if (sctx->esgs_ring) {
3438 assert(sctx->chip_class <= GFX8);
3439 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE, sctx->esgs_ring->width0 / 256);
3440 }
3441 if (sctx->gsvs_ring)
3442 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE, sctx->gsvs_ring->width0 / 256);
3443 } else {
3444 if (sctx->esgs_ring)
3445 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE, sctx->esgs_ring->width0 / 256);
3446 if (sctx->gsvs_ring)
3447 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE, sctx->gsvs_ring->width0 / 256);
3448 }
3449
3450 /* Set the state. */
3451 if (sctx->cs_preamble_gs_rings)
3452 si_pm4_free_state(sctx, sctx->cs_preamble_gs_rings, ~0);
3453 sctx->cs_preamble_gs_rings = pm4;
3454
3455 si_cs_preamble_add_vgt_flush(sctx);
3456
3457 /* Flush the context to re-emit both cs_preamble states. */
3458 sctx->initial_gfx_cs_size = 0; /* force flush */
3459 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3460
3461 return true;
3462 }
3463
3464 static void si_shader_lock(struct si_shader *shader)
3465 {
3466 simple_mtx_lock(&shader->selector->mutex);
3467 if (shader->previous_stage_sel) {
3468 assert(shader->previous_stage_sel != shader->selector);
3469 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3470 }
3471 }
3472
3473 static void si_shader_unlock(struct si_shader *shader)
3474 {
3475 if (shader->previous_stage_sel)
3476 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3477 simple_mtx_unlock(&shader->selector->mutex);
3478 }
3479
3480 /**
3481 * @returns 1 if \p sel has been updated to use a new scratch buffer
3482 * 0 if not
3483 * < 0 if there was a failure
3484 */
3485 static int si_update_scratch_buffer(struct si_context *sctx, struct si_shader *shader)
3486 {
3487 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3488
3489 if (!shader)
3490 return 0;
3491
3492 /* This shader doesn't need a scratch buffer */
3493 if (shader->config.scratch_bytes_per_wave == 0)
3494 return 0;
3495
3496 /* Prevent race conditions when updating:
3497 * - si_shader::scratch_bo
3498 * - si_shader::binary::code
3499 * - si_shader::previous_stage::binary::code.
3500 */
3501 si_shader_lock(shader);
3502
3503 /* This shader is already configured to use the current
3504 * scratch buffer. */
3505 if (shader->scratch_bo == sctx->scratch_buffer) {
3506 si_shader_unlock(shader);
3507 return 0;
3508 }
3509
3510 assert(sctx->scratch_buffer);
3511
3512 /* Replace the shader bo with a new bo that has the relocs applied. */
3513 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3514 si_shader_unlock(shader);
3515 return -1;
3516 }
3517
3518 /* Update the shader state to use the new shader bo. */
3519 si_shader_init_pm4_state(sctx->screen, shader);
3520
3521 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3522
3523 si_shader_unlock(shader);
3524 return 1;
3525 }
3526
3527 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3528 {
3529 return shader ? shader->config.scratch_bytes_per_wave : 0;
3530 }
3531
3532 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3533 {
3534 if (!sctx->tes_shader.cso)
3535 return NULL; /* tessellation disabled */
3536
3537 return sctx->tcs_shader.cso ? sctx->tcs_shader.current : sctx->fixed_func_tcs_shader.current;
3538 }
3539
3540 static bool si_update_scratch_relocs(struct si_context *sctx)
3541 {
3542 struct si_shader *tcs = si_get_tcs_current(sctx);
3543 int r;
3544
3545 /* Update the shaders, so that they are using the latest scratch.
3546 * The scratch buffer may have been changed since these shaders were
3547 * last used, so we still need to try to update them, even if they
3548 * require scratch buffers smaller than the current size.
3549 */
3550 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3551 if (r < 0)
3552 return false;
3553 if (r == 1)
3554 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3555
3556 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3557 if (r < 0)
3558 return false;
3559 if (r == 1)
3560 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3561
3562 r = si_update_scratch_buffer(sctx, tcs);
3563 if (r < 0)
3564 return false;
3565 if (r == 1)
3566 si_pm4_bind_state(sctx, hs, tcs->pm4);
3567
3568 /* VS can be bound as LS, ES, or VS. */
3569 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3570 if (r < 0)
3571 return false;
3572 if (r == 1) {
3573 if (sctx->vs_shader.current->key.as_ls)
3574 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3575 else if (sctx->vs_shader.current->key.as_es)
3576 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3577 else if (sctx->vs_shader.current->key.as_ngg)
3578 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3579 else
3580 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3581 }
3582
3583 /* TES can be bound as ES or VS. */
3584 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3585 if (r < 0)
3586 return false;
3587 if (r == 1) {
3588 if (sctx->tes_shader.current->key.as_es)
3589 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3590 else if (sctx->tes_shader.current->key.as_ngg)
3591 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3592 else
3593 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3594 }
3595
3596 return true;
3597 }
3598
3599 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3600 {
3601 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3602 * There are 2 cases to handle:
3603 *
3604 * - If the current needed size is less than the maximum seen size,
3605 * use the maximum seen size, so that WAVESIZE remains the same.
3606 *
3607 * - If the current needed size is greater than the maximum seen size,
3608 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3609 *
3610 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3611 * Otherwise, the number of waves that can use scratch is
3612 * SPI_TMPRING_SIZE.WAVES.
3613 */
3614 unsigned bytes = 0;
3615
3616 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3617 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3618 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3619
3620 if (sctx->tes_shader.cso) {
3621 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3622 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3623 }
3624
3625 sctx->max_seen_scratch_bytes_per_wave = MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3626
3627 unsigned scratch_needed_size = sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3628 unsigned spi_tmpring_size;
3629
3630 if (scratch_needed_size > 0) {
3631 if (!sctx->scratch_buffer || scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3632 /* Create a bigger scratch buffer */
3633 si_resource_reference(&sctx->scratch_buffer, NULL);
3634
3635 sctx->scratch_buffer = si_aligned_buffer_create(
3636 &sctx->screen->b, SI_RESOURCE_FLAG_UNMAPPABLE, PIPE_USAGE_DEFAULT, scratch_needed_size,
3637 sctx->screen->info.pte_fragment_size);
3638 if (!sctx->scratch_buffer)
3639 return false;
3640
3641 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3642 si_context_add_resource_size(sctx, &sctx->scratch_buffer->b.b);
3643 }
3644
3645 if (!si_update_scratch_relocs(sctx))
3646 return false;
3647 }
3648
3649 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3650 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3651 "scratch size should already be aligned correctly.");
3652
3653 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3654 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3655 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3656 sctx->spi_tmpring_size = spi_tmpring_size;
3657 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3658 }
3659 return true;
3660 }
3661
3662 static void si_init_tess_factor_ring(struct si_context *sctx)
3663 {
3664 assert(!sctx->tess_rings);
3665 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3666
3667 /* The address must be aligned to 2^19, because the shader only
3668 * receives the high 13 bits.
3669 */
3670 sctx->tess_rings = pipe_aligned_buffer_create(
3671 sctx->b.screen, SI_RESOURCE_FLAG_32BIT, PIPE_USAGE_DEFAULT,
3672 sctx->screen->tess_offchip_ring_size + sctx->screen->tess_factor_ring_size, 1 << 19);
3673 if (!sctx->tess_rings)
3674 return;
3675
3676 uint64_t factor_va =
3677 si_resource(sctx->tess_rings)->gpu_address + sctx->screen->tess_offchip_ring_size;
3678
3679 if (sctx->shadowed_regs) {
3680 /* These registers will be shadowed, so set them only once. */
3681 struct radeon_cmdbuf *cs = sctx->gfx_cs;
3682
3683 assert(sctx->chip_class >= GFX7);
3684
3685 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, si_resource(sctx->tess_rings),
3686 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3687 si_emit_vgt_flush(cs);
3688
3689 /* Set tessellation registers. */
3690 radeon_set_uconfig_reg(cs, R_030938_VGT_TF_RING_SIZE,
3691 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3692 radeon_set_uconfig_reg(cs, R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8);
3693 if (sctx->chip_class >= GFX10) {
3694 radeon_set_uconfig_reg(cs, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3695 S_030984_BASE_HI(factor_va >> 40));
3696 } else if (sctx->chip_class == GFX9) {
3697 radeon_set_uconfig_reg(cs, R_030944_VGT_TF_MEMORY_BASE_HI,
3698 S_030944_BASE_HI(factor_va >> 40));
3699 }
3700 radeon_set_uconfig_reg(cs, R_03093C_VGT_HS_OFFCHIP_PARAM,
3701 sctx->screen->vgt_hs_offchip_param);
3702 return;
3703 }
3704
3705 /* The codepath without register shadowing. */
3706 si_cs_preamble_add_vgt_flush(sctx);
3707
3708 /* Append these registers to the init config state. */
3709 if (sctx->chip_class >= GFX7) {
3710 si_pm4_set_reg(sctx->cs_preamble_state, R_030938_VGT_TF_RING_SIZE,
3711 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3712 si_pm4_set_reg(sctx->cs_preamble_state, R_030940_VGT_TF_MEMORY_BASE, factor_va >> 8);
3713 if (sctx->chip_class >= GFX10)
3714 si_pm4_set_reg(sctx->cs_preamble_state, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3715 S_030984_BASE_HI(factor_va >> 40));
3716 else if (sctx->chip_class == GFX9)
3717 si_pm4_set_reg(sctx->cs_preamble_state, R_030944_VGT_TF_MEMORY_BASE_HI,
3718 S_030944_BASE_HI(factor_va >> 40));
3719 si_pm4_set_reg(sctx->cs_preamble_state, R_03093C_VGT_HS_OFFCHIP_PARAM,
3720 sctx->screen->vgt_hs_offchip_param);
3721 } else {
3722 si_pm4_set_reg(sctx->cs_preamble_state, R_008988_VGT_TF_RING_SIZE,
3723 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3724 si_pm4_set_reg(sctx->cs_preamble_state, R_0089B8_VGT_TF_MEMORY_BASE, factor_va >> 8);
3725 si_pm4_set_reg(sctx->cs_preamble_state, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3726 sctx->screen->vgt_hs_offchip_param);
3727 }
3728
3729 /* Flush the context to re-emit the cs_preamble state.
3730 * This is done only once in a lifetime of a context.
3731 */
3732 sctx->initial_gfx_cs_size = 0; /* force flush */
3733 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3734 }
3735
3736 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3737 union si_vgt_stages_key key)
3738 {
3739 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3740 uint32_t stages = 0;
3741
3742 if (key.u.tess) {
3743 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) | S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3744
3745 if (key.u.gs)
3746 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) | S_028B54_GS_EN(1);
3747 else if (key.u.ngg)
3748 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3749 else
3750 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3751 } else if (key.u.gs) {
3752 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) | S_028B54_GS_EN(1);
3753 } else if (key.u.ngg) {
3754 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3755 }
3756
3757 if (key.u.ngg) {
3758 stages |= S_028B54_PRIMGEN_EN(1) | S_028B54_GS_FAST_LAUNCH(key.u.ngg_gs_fast_launch) |
3759 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3760 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3761 } else if (key.u.gs)
3762 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3763
3764 if (screen->info.chip_class >= GFX9)
3765 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3766
3767 if (screen->info.chip_class >= GFX10 &&
3768 /* GS fast launch hangs with Wave64, so always use Wave32. */
3769 (screen->ge_wave_size == 32 || (key.u.ngg && key.u.ngg_gs_fast_launch))) {
3770 stages |= S_028B54_HS_W32_EN(1) |
3771 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3772 S_028B54_VS_W32_EN(1);
3773 }
3774
3775 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3776 return pm4;
3777 }
3778
3779 static void si_update_vgt_shader_config(struct si_context *sctx, union si_vgt_stages_key key)
3780 {
3781 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3782
3783 if (unlikely(!*pm4))
3784 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3785 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3786 }
3787
3788 bool si_update_shaders(struct si_context *sctx)
3789 {
3790 struct pipe_context *ctx = (struct pipe_context *)sctx;
3791 struct si_compiler_ctx_state compiler_state;
3792 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3793 struct si_shader *old_vs = si_get_vs_state(sctx);
3794 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3795 struct si_shader *old_ps = sctx->ps_shader.current;
3796 union si_vgt_stages_key key;
3797 unsigned old_spi_shader_col_format =
3798 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3799 int r;
3800
3801 if (!sctx->compiler.passes)
3802 si_init_compiler(sctx->screen, &sctx->compiler);
3803
3804 compiler_state.compiler = &sctx->compiler;
3805 compiler_state.debug = sctx->debug;
3806 compiler_state.is_debug_context = sctx->is_debug;
3807
3808 key.index = 0;
3809
3810 if (sctx->tes_shader.cso)
3811 key.u.tess = 1;
3812 if (sctx->gs_shader.cso)
3813 key.u.gs = 1;
3814
3815 if (sctx->ngg) {
3816 key.u.ngg = 1;
3817 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3818 }
3819
3820 /* Update TCS and TES. */
3821 if (sctx->tes_shader.cso) {
3822 if (!sctx->tess_rings) {
3823 si_init_tess_factor_ring(sctx);
3824 if (!sctx->tess_rings)
3825 return false;
3826 }
3827
3828 if (sctx->tcs_shader.cso) {
3829 r = si_shader_select(ctx, &sctx->tcs_shader, key, &compiler_state);
3830 if (r)
3831 return false;
3832 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3833 } else {
3834 if (!sctx->fixed_func_tcs_shader.cso) {
3835 sctx->fixed_func_tcs_shader.cso = si_create_fixed_func_tcs(sctx);
3836 if (!sctx->fixed_func_tcs_shader.cso)
3837 return false;
3838 }
3839
3840 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader, key, &compiler_state);
3841 if (r)
3842 return false;
3843 si_pm4_bind_state(sctx, hs, sctx->fixed_func_tcs_shader.current->pm4);
3844 }
3845
3846 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3847 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3848 if (r)
3849 return false;
3850
3851 if (sctx->gs_shader.cso) {
3852 /* TES as ES */
3853 assert(sctx->chip_class <= GFX8);
3854 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3855 } else if (key.u.ngg) {
3856 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3857 } else {
3858 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3859 }
3860 }
3861 } else {
3862 if (sctx->chip_class <= GFX8)
3863 si_pm4_bind_state(sctx, ls, NULL);
3864 si_pm4_bind_state(sctx, hs, NULL);
3865 }
3866
3867 /* Update GS. */
3868 if (sctx->gs_shader.cso) {
3869 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3870 if (r)
3871 return false;
3872 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3873 if (!key.u.ngg) {
3874 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3875
3876 if (!si_update_gs_ring_buffers(sctx))
3877 return false;
3878 } else {
3879 si_pm4_bind_state(sctx, vs, NULL);
3880 }
3881 } else {
3882 if (!key.u.ngg) {
3883 si_pm4_bind_state(sctx, gs, NULL);
3884 if (sctx->chip_class <= GFX8)
3885 si_pm4_bind_state(sctx, es, NULL);
3886 }
3887 }
3888
3889 /* Update VS. */
3890 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3891 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3892 if (r)
3893 return false;
3894
3895 if (!key.u.tess && !key.u.gs) {
3896 if (key.u.ngg) {
3897 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3898 si_pm4_bind_state(sctx, vs, NULL);
3899 } else {
3900 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3901 }
3902 } else if (sctx->tes_shader.cso) {
3903 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3904 } else {
3905 assert(sctx->gs_shader.cso);
3906 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3907 }
3908 }
3909
3910 /* This must be done after the shader variant is selected. */
3911 if (sctx->ngg) {
3912 struct si_shader *vs = si_get_vs(sctx)->current;
3913
3914 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(vs);
3915 key.u.ngg_gs_fast_launch = !!(vs->key.opt.ngg_culling & SI_NGG_CULL_GS_FAST_LAUNCH_ALL);
3916 }
3917
3918 si_update_vgt_shader_config(sctx, key);
3919
3920 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3921 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3922
3923 if (sctx->ps_shader.cso) {
3924 unsigned db_shader_control;
3925
3926 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3927 if (r)
3928 return false;
3929 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3930
3931 db_shader_control = sctx->ps_shader.cso->db_shader_control |
3932 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3933
3934 if (si_pm4_state_changed(sctx, ps) || si_pm4_state_changed(sctx, vs) ||
3935 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3936 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3937 sctx->flatshade != rs->flatshade) {
3938 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3939 sctx->flatshade = rs->flatshade;
3940 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3941 }
3942
3943 if (sctx->screen->info.rbplus_allowed && si_pm4_state_changed(sctx, ps) &&
3944 (!old_ps || old_spi_shader_col_format !=
3945 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3946 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3947
3948 if (sctx->ps_db_shader_control != db_shader_control) {
3949 sctx->ps_db_shader_control = db_shader_control;
3950 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3951 if (sctx->screen->dpbb_allowed)
3952 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3953 }
3954
3955 if (sctx->smoothing_enabled !=
3956 sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3957 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3958 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3959
3960 if (sctx->chip_class == GFX6)
3961 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3962
3963 if (sctx->framebuffer.nr_samples <= 1)
3964 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3965 }
3966 }
3967
3968 if (si_pm4_state_enabled_and_changed(sctx, ls) || si_pm4_state_enabled_and_changed(sctx, hs) ||
3969 si_pm4_state_enabled_and_changed(sctx, es) || si_pm4_state_enabled_and_changed(sctx, gs) ||
3970 si_pm4_state_enabled_and_changed(sctx, vs) || si_pm4_state_enabled_and_changed(sctx, ps)) {
3971 if (!si_update_spi_tmpring_size(sctx))
3972 return false;
3973 }
3974
3975 if (sctx->chip_class >= GFX7) {
3976 if (si_pm4_state_enabled_and_changed(sctx, ls))
3977 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
3978 else if (!sctx->queued.named.ls)
3979 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
3980
3981 if (si_pm4_state_enabled_and_changed(sctx, hs))
3982 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
3983 else if (!sctx->queued.named.hs)
3984 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
3985
3986 if (si_pm4_state_enabled_and_changed(sctx, es))
3987 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
3988 else if (!sctx->queued.named.es)
3989 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
3990
3991 if (si_pm4_state_enabled_and_changed(sctx, gs))
3992 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
3993 else if (!sctx->queued.named.gs)
3994 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
3995
3996 if (si_pm4_state_enabled_and_changed(sctx, vs))
3997 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
3998 else if (!sctx->queued.named.vs)
3999 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4000
4001 if (si_pm4_state_enabled_and_changed(sctx, ps))
4002 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4003 else if (!sctx->queued.named.ps)
4004 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4005 }
4006
4007 sctx->do_update_shaders = false;
4008 return true;
4009 }
4010
4011 static void si_emit_scratch_state(struct si_context *sctx)
4012 {
4013 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4014
4015 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE, sctx->spi_tmpring_size);
4016
4017 if (sctx->scratch_buffer) {
4018 radeon_add_to_buffer_list(sctx, sctx->gfx_cs, sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4019 RADEON_PRIO_SCRATCH_BUFFER);
4020 }
4021 }
4022
4023 void si_init_screen_live_shader_cache(struct si_screen *sscreen)
4024 {
4025 util_live_shader_cache_init(&sscreen->live_shader_cache, si_create_shader_selector,
4026 si_destroy_shader_selector);
4027 }
4028
4029 void si_init_shader_functions(struct si_context *sctx)
4030 {
4031 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4032 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4033
4034 sctx->b.create_vs_state = si_create_shader;
4035 sctx->b.create_tcs_state = si_create_shader;
4036 sctx->b.create_tes_state = si_create_shader;
4037 sctx->b.create_gs_state = si_create_shader;
4038 sctx->b.create_fs_state = si_create_shader;
4039
4040 sctx->b.bind_vs_state = si_bind_vs_shader;
4041 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4042 sctx->b.bind_tes_state = si_bind_tes_shader;
4043 sctx->b.bind_gs_state = si_bind_gs_shader;
4044 sctx->b.bind_fs_state = si_bind_ps_shader;
4045
4046 sctx->b.delete_vs_state = si_delete_shader_selector;
4047 sctx->b.delete_tcs_state = si_delete_shader_selector;
4048 sctx->b.delete_tes_state = si_delete_shader_selector;
4049 sctx->b.delete_gs_state = si_delete_shader_selector;
4050 sctx->b.delete_fs_state = si_delete_shader_selector;
4051 }