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radeonsi: make sure that DSA state != NULL and remove all NULL checking
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 void *si_get_ir_binary(struct si_shader_selector *sel)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 unsigned size = 4 + ir_size + sizeof(sel->so);
68 char *result = (char*)MALLOC(size);
69 if (!result)
70 return NULL;
71
72 *((uint32_t*)result) = size;
73 memcpy(result + 4, ir_binary, ir_size);
74 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
75
76 if (sel->nir)
77 blob_finish(&blob);
78
79 return result;
80 }
81
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
84 {
85 /* data may be NULL if size == 0 */
86 if (size)
87 memcpy(ptr, data, size);
88 ptr += DIV_ROUND_UP(size, 4);
89 return ptr;
90 }
91
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
94 {
95 memcpy(data, ptr, size);
96 ptr += DIV_ROUND_UP(size, 4);
97 return ptr;
98 }
99
100 /**
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
103 */
104 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
105 {
106 *ptr++ = size;
107 return write_data(ptr, data, size);
108 }
109
110 /**
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
113 */
114 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
115 {
116 *size = *ptr++;
117 assert(*data == NULL);
118 if (!*size)
119 return ptr;
120 *data = malloc(*size);
121 return read_data(ptr, *data, *size);
122 }
123
124 /**
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
126 * as integer.
127 */
128 static void *si_get_shader_binary(struct si_shader *shader)
129 {
130 /* There is always a size of data followed by the data itself. */
131 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
132 strlen(shader->binary.llvm_ir_string) + 1 : 0;
133
134 /* Refuse to allocate overly large buffers and guard against integer
135 * overflow. */
136 if (shader->binary.elf_size > UINT_MAX / 4 ||
137 llvm_ir_size > UINT_MAX / 4)
138 return NULL;
139
140 unsigned size =
141 4 + /* total size */
142 4 + /* CRC32 of the data below */
143 align(sizeof(shader->config), 4) +
144 align(sizeof(shader->info), 4) +
145 4 + align(shader->binary.elf_size, 4) +
146 4 + align(llvm_ir_size, 4);
147 void *buffer = CALLOC(1, size);
148 uint32_t *ptr = (uint32_t*)buffer;
149
150 if (!buffer)
151 return NULL;
152
153 *ptr++ = size;
154 ptr++; /* CRC32 is calculated at the end. */
155
156 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
157 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
158 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
159 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
160 assert((char *)ptr - (char *)buffer == size);
161
162 /* Compute CRC32. */
163 ptr = (uint32_t*)buffer;
164 ptr++;
165 *ptr = util_hash_crc32(ptr + 1, size - 8);
166
167 return buffer;
168 }
169
170 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
171 {
172 uint32_t *ptr = (uint32_t*)binary;
173 uint32_t size = *ptr++;
174 uint32_t crc32 = *ptr++;
175 unsigned chunk_size;
176 unsigned elf_size;
177
178 if (util_hash_crc32(ptr, size - 8) != crc32) {
179 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
180 return false;
181 }
182
183 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
184 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
185 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
186 &elf_size);
187 shader->binary.elf_size = elf_size;
188 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
189
190 return true;
191 }
192
193 /**
194 * Insert a shader into the cache. It's assumed the shader is not in the cache.
195 * Use si_shader_cache_load_shader before calling this.
196 *
197 * Returns false on failure, in which case the ir_binary should be freed.
198 */
199 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
200 struct si_shader *shader,
201 bool insert_into_disk_cache)
202 {
203 void *hw_binary;
204 struct hash_entry *entry;
205 uint8_t key[CACHE_KEY_SIZE];
206
207 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
208 if (entry)
209 return false; /* already added */
210
211 hw_binary = si_get_shader_binary(shader);
212 if (!hw_binary)
213 return false;
214
215 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
216 hw_binary) == NULL) {
217 FREE(hw_binary);
218 return false;
219 }
220
221 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
222 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
223 *((uint32_t *)ir_binary), key);
224 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
225 *((uint32_t *) hw_binary), NULL);
226 }
227
228 return true;
229 }
230
231 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
232 struct si_shader *shader)
233 {
234 struct hash_entry *entry =
235 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
236 if (!entry) {
237 if (sscreen->disk_shader_cache) {
238 unsigned char sha1[CACHE_KEY_SIZE];
239 size_t tg_size = *((uint32_t *) ir_binary);
240
241 disk_cache_compute_key(sscreen->disk_shader_cache,
242 ir_binary, tg_size, sha1);
243
244 size_t binary_size;
245 uint8_t *buffer =
246 disk_cache_get(sscreen->disk_shader_cache,
247 sha1, &binary_size);
248 if (!buffer)
249 return false;
250
251 if (binary_size < sizeof(uint32_t) ||
252 *((uint32_t*)buffer) != binary_size) {
253 /* Something has gone wrong discard the item
254 * from the cache and rebuild/link from
255 * source.
256 */
257 assert(!"Invalid radeonsi shader disk cache "
258 "item!");
259
260 disk_cache_remove(sscreen->disk_shader_cache,
261 sha1);
262 free(buffer);
263
264 return false;
265 }
266
267 if (!si_load_shader_binary(shader, buffer)) {
268 free(buffer);
269 return false;
270 }
271 free(buffer);
272
273 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
274 shader, false))
275 FREE(ir_binary);
276 } else {
277 return false;
278 }
279 } else {
280 if (si_load_shader_binary(shader, entry->data))
281 FREE(ir_binary);
282 else
283 return false;
284 }
285 p_atomic_inc(&sscreen->num_shader_cache_hits);
286 return true;
287 }
288
289 static uint32_t si_shader_cache_key_hash(const void *key)
290 {
291 /* The first dword is the key size. */
292 return util_hash_crc32(key, *(uint32_t*)key);
293 }
294
295 static bool si_shader_cache_key_equals(const void *a, const void *b)
296 {
297 uint32_t *keya = (uint32_t*)a;
298 uint32_t *keyb = (uint32_t*)b;
299
300 /* The first dword is the key size. */
301 if (*keya != *keyb)
302 return false;
303
304 return memcmp(keya, keyb, *keya) == 0;
305 }
306
307 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
308 {
309 FREE((void*)entry->key);
310 FREE(entry->data);
311 }
312
313 bool si_init_shader_cache(struct si_screen *sscreen)
314 {
315 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
316 sscreen->shader_cache =
317 _mesa_hash_table_create(NULL,
318 si_shader_cache_key_hash,
319 si_shader_cache_key_equals);
320
321 return sscreen->shader_cache != NULL;
322 }
323
324 void si_destroy_shader_cache(struct si_screen *sscreen)
325 {
326 if (sscreen->shader_cache)
327 _mesa_hash_table_destroy(sscreen->shader_cache,
328 si_destroy_shader_cache_entry);
329 mtx_destroy(&sscreen->shader_cache_mutex);
330 }
331
332 /* SHADER STATES */
333
334 static void si_set_tesseval_regs(struct si_screen *sscreen,
335 const struct si_shader_selector *tes,
336 struct si_pm4_state *pm4)
337 {
338 const struct tgsi_shader_info *info = &tes->info;
339 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
340 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
341 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
342 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
343 unsigned type, partitioning, topology, distribution_mode;
344
345 switch (tes_prim_mode) {
346 case PIPE_PRIM_LINES:
347 type = V_028B6C_TESS_ISOLINE;
348 break;
349 case PIPE_PRIM_TRIANGLES:
350 type = V_028B6C_TESS_TRIANGLE;
351 break;
352 case PIPE_PRIM_QUADS:
353 type = V_028B6C_TESS_QUAD;
354 break;
355 default:
356 assert(0);
357 return;
358 }
359
360 switch (tes_spacing) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
362 partitioning = V_028B6C_PART_FRAC_ODD;
363 break;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
365 partitioning = V_028B6C_PART_FRAC_EVEN;
366 break;
367 case PIPE_TESS_SPACING_EQUAL:
368 partitioning = V_028B6C_PART_INTEGER;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 if (tes_point_mode)
376 topology = V_028B6C_OUTPUT_POINT;
377 else if (tes_prim_mode == PIPE_PRIM_LINES)
378 topology = V_028B6C_OUTPUT_LINE;
379 else if (tes_vertex_order_cw)
380 /* for some reason, this must be the other way around */
381 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
382 else
383 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
384
385 if (sscreen->has_distributed_tess) {
386 if (sscreen->info.family == CHIP_FIJI ||
387 sscreen->info.family >= CHIP_POLARIS10)
388 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
389 else
390 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
391 } else
392 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
393
394 assert(pm4->shader);
395 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
396 S_028B6C_PARTITIONING(partitioning) |
397 S_028B6C_TOPOLOGY(topology) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
399 }
400
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
403 *
404 * Possible VGT configurations and which state should set the register:
405 *
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
408 * VS as VS | VS | 30
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 *
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 */
415 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
416 struct si_shader_selector *sel,
417 struct si_shader *shader,
418 struct si_pm4_state *pm4)
419 {
420 unsigned type = sel->type;
421
422 if (sscreen->info.family < CHIP_POLARIS10 ||
423 sscreen->info.chip_class >= GFX10)
424 return;
425
426 /* VS as VS, or VS as ES: */
427 if ((type == PIPE_SHADER_VERTEX &&
428 (!shader ||
429 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
430 /* TES as VS, or TES as ES: */
431 type == PIPE_SHADER_TESS_EVAL) {
432 unsigned vtx_reuse_depth = 30;
433
434 if (type == PIPE_SHADER_TESS_EVAL &&
435 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD)
437 vtx_reuse_depth = 14;
438
439 assert(pm4->shader);
440 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
441 }
442 }
443
444 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
445 {
446 if (shader->pm4)
447 si_pm4_clear_state(shader->pm4);
448 else
449 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
450
451 if (shader->pm4) {
452 shader->pm4->shader = shader;
453 return shader->pm4;
454 } else {
455 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
456 return NULL;
457 }
458 }
459
460 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
461 {
462 /* Add the pointer to VBO descriptors. */
463 return num_always_on_user_sgprs + 1;
464 }
465
466 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
467 {
468 struct si_pm4_state *pm4;
469 unsigned vgpr_comp_cnt;
470 uint64_t va;
471
472 assert(sscreen->info.chip_class <= GFX8);
473
474 pm4 = si_get_shader_pm4_state(shader);
475 if (!pm4)
476 return;
477
478 va = shader->bo->gpu_address;
479 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
480
481 /* We need at least 2 components for LS.
482 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
483 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
484 */
485 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
486
487 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
488 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
489
490 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
491 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
492 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
493 S_00B528_DX10_CLAMP(1) |
494 S_00B528_FLOAT_MODE(shader->config.float_mode);
495 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
496 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
497 }
498
499 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
500 {
501 struct si_pm4_state *pm4;
502 uint64_t va;
503 unsigned ls_vgpr_comp_cnt = 0;
504
505 pm4 = si_get_shader_pm4_state(shader);
506 if (!pm4)
507 return;
508
509 va = shader->bo->gpu_address;
510 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
511
512 if (sscreen->info.chip_class >= GFX9) {
513 if (sscreen->info.chip_class >= GFX10) {
514 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
515 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
516 } else {
517 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
518 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
519 }
520
521 /* We need at least 2 components for LS.
522 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
523 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
524 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
525 * be loaded.
526 */
527 ls_vgpr_comp_cnt = 1;
528 if (shader->info.uses_instanceid) {
529 if (sscreen->info.chip_class >= GFX10)
530 ls_vgpr_comp_cnt = 3;
531 else
532 ls_vgpr_comp_cnt = 2;
533 }
534
535 unsigned num_user_sgprs =
536 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
537
538 shader->config.rsrc2 =
539 S_00B42C_USER_SGPR(num_user_sgprs) |
540 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
541
542 if (sscreen->info.chip_class >= GFX10)
543 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
544 else
545 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
546 } else {
547 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
548 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
549
550 shader->config.rsrc2 =
551 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
552 S_00B42C_OC_LDS_EN(1) |
553 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
554 }
555
556 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
557 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
558 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
559 (sscreen->info.chip_class <= GFX9 ?
560 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
561 S_00B428_DX10_CLAMP(1) |
562 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
563 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
564 S_00B428_FLOAT_MODE(shader->config.float_mode) |
565 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
566
567 if (sscreen->info.chip_class <= GFX8) {
568 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
569 shader->config.rsrc2);
570 }
571 }
572
573 static void si_emit_shader_es(struct si_context *sctx)
574 {
575 struct si_shader *shader = sctx->queued.named.es->shader;
576 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
577
578 if (!shader)
579 return;
580
581 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
582 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
583 shader->selector->esgs_itemsize / 4);
584
585 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
586 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
587 SI_TRACKED_VGT_TF_PARAM,
588 shader->vgt_tf_param);
589
590 if (shader->vgt_vertex_reuse_block_cntl)
591 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
592 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
593 shader->vgt_vertex_reuse_block_cntl);
594
595 if (initial_cdw != sctx->gfx_cs->current.cdw)
596 sctx->context_roll = true;
597 }
598
599 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
600 {
601 struct si_pm4_state *pm4;
602 unsigned num_user_sgprs;
603 unsigned vgpr_comp_cnt;
604 uint64_t va;
605 unsigned oc_lds_en;
606
607 assert(sscreen->info.chip_class <= GFX8);
608
609 pm4 = si_get_shader_pm4_state(shader);
610 if (!pm4)
611 return;
612
613 pm4->atom.emit = si_emit_shader_es;
614 va = shader->bo->gpu_address;
615 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
616
617 if (shader->selector->type == PIPE_SHADER_VERTEX) {
618 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
619 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
620 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
621 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
622 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
623 num_user_sgprs = SI_TES_NUM_USER_SGPR;
624 } else
625 unreachable("invalid shader selector type");
626
627 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
628
629 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
630 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
631 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
632 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
633 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
634 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
635 S_00B328_DX10_CLAMP(1) |
636 S_00B328_FLOAT_MODE(shader->config.float_mode));
637 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
638 S_00B32C_USER_SGPR(num_user_sgprs) |
639 S_00B32C_OC_LDS_EN(oc_lds_en) |
640 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
641
642 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
643 si_set_tesseval_regs(sscreen, shader->selector, pm4);
644
645 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
646 }
647
648 void gfx9_get_gs_info(struct si_shader_selector *es,
649 struct si_shader_selector *gs,
650 struct gfx9_gs_info *out)
651 {
652 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
653 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
654 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
655 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
656
657 /* All these are in dwords: */
658 /* We can't allow using the whole LDS, because GS waves compete with
659 * other shader stages for LDS space. */
660 const unsigned max_lds_size = 8 * 1024;
661 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
662 unsigned esgs_lds_size;
663
664 /* All these are per subgroup: */
665 const unsigned max_out_prims = 32 * 1024;
666 const unsigned max_es_verts = 255;
667 const unsigned ideal_gs_prims = 64;
668 unsigned max_gs_prims, gs_prims;
669 unsigned min_es_verts, es_verts, worst_case_es_verts;
670
671 if (uses_adjacency || gs_num_invocations > 1)
672 max_gs_prims = 127 / gs_num_invocations;
673 else
674 max_gs_prims = 255;
675
676 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
677 * Make sure we don't go over the maximum value.
678 */
679 if (gs->gs_max_out_vertices > 0) {
680 max_gs_prims = MIN2(max_gs_prims,
681 max_out_prims /
682 (gs->gs_max_out_vertices * gs_num_invocations));
683 }
684 assert(max_gs_prims > 0);
685
686 /* If the primitive has adjacency, halve the number of vertices
687 * that will be reused in multiple primitives.
688 */
689 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
690
691 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
692 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
693
694 /* Compute ESGS LDS size based on the worst case number of ES vertices
695 * needed to create the target number of GS prims per subgroup.
696 */
697 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
698
699 /* If total LDS usage is too big, refactor partitions based on ratio
700 * of ESGS item sizes.
701 */
702 if (esgs_lds_size > max_lds_size) {
703 /* Our target GS Prims Per Subgroup was too large. Calculate
704 * the maximum number of GS Prims Per Subgroup that will fit
705 * into LDS, capped by the maximum that the hardware can support.
706 */
707 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
708 max_gs_prims);
709 assert(gs_prims > 0);
710 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
711 max_es_verts);
712
713 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
714 assert(esgs_lds_size <= max_lds_size);
715 }
716
717 /* Now calculate remaining ESGS information. */
718 if (esgs_lds_size)
719 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
720 else
721 es_verts = max_es_verts;
722
723 /* Vertices for adjacency primitives are not always reused, so restore
724 * it for ES_VERTS_PER_SUBGRP.
725 */
726 min_es_verts = gs->gs_input_verts_per_prim;
727
728 /* For normal primitives, the VGT only checks if they are past the ES
729 * verts per subgroup after allocating a full GS primitive and if they
730 * are, kick off a new subgroup. But if those additional ES verts are
731 * unique (e.g. not reused) we need to make sure there is enough LDS
732 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
733 */
734 es_verts -= min_es_verts - 1;
735
736 out->es_verts_per_subgroup = es_verts;
737 out->gs_prims_per_subgroup = gs_prims;
738 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
739 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
740 gs->gs_max_out_vertices;
741 out->esgs_ring_size = 4 * esgs_lds_size;
742
743 assert(out->max_prims_per_subgroup <= max_out_prims);
744 }
745
746 static void si_emit_shader_gs(struct si_context *sctx)
747 {
748 struct si_shader *shader = sctx->queued.named.gs->shader;
749 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
750
751 if (!shader)
752 return;
753
754 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
755 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
756 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
757 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
758 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
759 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
760 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
761
762 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
763 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
764 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
765 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
766
767 /* R_028B38_VGT_GS_MAX_VERT_OUT */
768 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
769 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
770 shader->ctx_reg.gs.vgt_gs_max_vert_out);
771
772 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
773 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
774 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
775 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
776 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
777 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
778 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
779 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
780
781 /* R_028B90_VGT_GS_INSTANCE_CNT */
782 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
783 SI_TRACKED_VGT_GS_INSTANCE_CNT,
784 shader->ctx_reg.gs.vgt_gs_instance_cnt);
785
786 if (sctx->chip_class >= GFX9) {
787 /* R_028A44_VGT_GS_ONCHIP_CNTL */
788 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
789 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
790 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
791 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
792 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
793 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
794 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
795 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
796 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
797 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
798 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
799
800 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
801 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
802 SI_TRACKED_VGT_TF_PARAM,
803 shader->vgt_tf_param);
804 if (shader->vgt_vertex_reuse_block_cntl)
805 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
806 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
807 shader->vgt_vertex_reuse_block_cntl);
808 }
809
810 if (initial_cdw != sctx->gfx_cs->current.cdw)
811 sctx->context_roll = true;
812 }
813
814 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
815 {
816 struct si_shader_selector *sel = shader->selector;
817 const ubyte *num_components = sel->info.num_stream_output_components;
818 unsigned gs_num_invocations = sel->gs_num_invocations;
819 struct si_pm4_state *pm4;
820 uint64_t va;
821 unsigned max_stream = sel->max_gs_stream;
822 unsigned offset;
823
824 pm4 = si_get_shader_pm4_state(shader);
825 if (!pm4)
826 return;
827
828 pm4->atom.emit = si_emit_shader_gs;
829
830 offset = num_components[0] * sel->gs_max_out_vertices;
831 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
832
833 if (max_stream >= 1)
834 offset += num_components[1] * sel->gs_max_out_vertices;
835 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
836
837 if (max_stream >= 2)
838 offset += num_components[2] * sel->gs_max_out_vertices;
839 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
840
841 if (max_stream >= 3)
842 offset += num_components[3] * sel->gs_max_out_vertices;
843 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
844
845 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
846 assert(offset < (1 << 15));
847
848 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
849
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
851 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
852 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
853 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
854
855 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
856 S_028B90_ENABLE(gs_num_invocations > 0);
857
858 va = shader->bo->gpu_address;
859 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
860
861 if (sscreen->info.chip_class >= GFX9) {
862 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
863 unsigned es_type = shader->key.part.gs.es->type;
864 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
865
866 if (es_type == PIPE_SHADER_VERTEX)
867 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
868 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
869 else if (es_type == PIPE_SHADER_TESS_EVAL)
870 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
871 else
872 unreachable("invalid shader selector type");
873
874 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
875 * VGPR[0:4] are always loaded.
876 */
877 if (sel->info.uses_invocationid)
878 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
879 else if (sel->info.uses_primid)
880 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
881 else if (input_prim >= PIPE_PRIM_TRIANGLES)
882 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
883 else
884 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
885
886 unsigned num_user_sgprs;
887 if (es_type == PIPE_SHADER_VERTEX)
888 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
889 else
890 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
891
892 if (sscreen->info.chip_class >= GFX10) {
893 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
894 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
895 } else {
896 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
897 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
898 }
899
900 uint32_t rsrc1 =
901 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
902 S_00B228_DX10_CLAMP(1) |
903 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
904 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
905 S_00B228_FLOAT_MODE(shader->config.float_mode) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
907 uint32_t rsrc2 =
908 S_00B22C_USER_SGPR(num_user_sgprs) |
909 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
910 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
911 S_00B22C_LDS_SIZE(shader->config.lds_size) |
912 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
913
914 if (sscreen->info.chip_class >= GFX10) {
915 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
916 } else {
917 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
918 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
919 }
920
921 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
922 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
923
924 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
925 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
926 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
927 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
928 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
929 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
930 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
931 shader->key.part.gs.es->esgs_itemsize / 4;
932
933 if (es_type == PIPE_SHADER_TESS_EVAL)
934 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
935
936 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
937 NULL, pm4);
938 } else {
939 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
940 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
941
942 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
943 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
944 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
945 S_00B228_DX10_CLAMP(1) |
946 S_00B228_FLOAT_MODE(shader->config.float_mode));
947 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
948 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
949 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
950 }
951 }
952
953 /* Common tail code for NGG primitive shaders. */
954 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
955 struct si_shader *shader,
956 unsigned initial_cdw)
957 {
958 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
959 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
960 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
961 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
962 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
963 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
964 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
965 SI_TRACKED_VGT_PRIMITIVEID_EN,
966 shader->ctx_reg.ngg.vgt_primitiveid_en);
967 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
968 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
969 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
970 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
971 SI_TRACKED_VGT_GS_INSTANCE_CNT,
972 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
973 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
974 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
975 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
976 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
977 SI_TRACKED_VGT_REUSE_OFF,
978 shader->ctx_reg.ngg.vgt_reuse_off);
979 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
980 SI_TRACKED_SPI_VS_OUT_CONFIG,
981 shader->ctx_reg.ngg.spi_vs_out_config);
982 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
983 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
984 shader->ctx_reg.ngg.spi_shader_idx_format,
985 shader->ctx_reg.ngg.spi_shader_pos_format);
986 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
987 SI_TRACKED_PA_CL_VTE_CNTL,
988 shader->ctx_reg.ngg.pa_cl_vte_cntl);
989 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
990 SI_TRACKED_PA_CL_NGG_CNTL,
991 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
992
993 if (initial_cdw != sctx->gfx_cs->current.cdw)
994 sctx->context_roll = true;
995 }
996
997 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
998 {
999 struct si_shader *shader = sctx->queued.named.gs->shader;
1000 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1001
1002 if (!shader)
1003 return;
1004
1005 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1006 }
1007
1008 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1009 {
1010 struct si_shader *shader = sctx->queued.named.gs->shader;
1011 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1012
1013 if (!shader)
1014 return;
1015
1016 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1017 SI_TRACKED_VGT_TF_PARAM,
1018 shader->vgt_tf_param);
1019
1020 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1021 }
1022
1023 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1024 {
1025 struct si_shader *shader = sctx->queued.named.gs->shader;
1026 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1027
1028 if (!shader)
1029 return;
1030
1031 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1032 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1033 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1034
1035 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1036 }
1037
1038 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1039 {
1040 struct si_shader *shader = sctx->queued.named.gs->shader;
1041 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1042
1043 if (!shader)
1044 return;
1045
1046 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1047 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1048 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1049 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1050 SI_TRACKED_VGT_TF_PARAM,
1051 shader->vgt_tf_param);
1052
1053 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1054 }
1055
1056 static void si_set_ge_pc_alloc(struct si_screen *sscreen,
1057 struct si_pm4_state *pm4, bool culling)
1058 {
1059 si_pm4_set_reg(pm4, R_030980_GE_PC_ALLOC,
1060 S_030980_OVERSUB_EN(1) |
1061 S_030980_NUM_PC_LINES((culling ? 256 : 128) * sscreen->info.max_se - 1));
1062 }
1063
1064 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1065 {
1066 if (gs->type == PIPE_SHADER_GEOMETRY)
1067 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1068
1069 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1070 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1071 return PIPE_PRIM_POINTS;
1072 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1073 return PIPE_PRIM_LINES;
1074 return PIPE_PRIM_TRIANGLES;
1075 }
1076
1077 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1078 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1079 }
1080
1081 /**
1082 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1083 * in NGG mode.
1084 */
1085 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1086 {
1087 const struct si_shader_selector *gs_sel = shader->selector;
1088 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1089 enum pipe_shader_type gs_type = shader->selector->type;
1090 const struct si_shader_selector *es_sel =
1091 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1092 const struct tgsi_shader_info *es_info = &es_sel->info;
1093 enum pipe_shader_type es_type = es_sel->type;
1094 unsigned num_user_sgprs;
1095 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1096 uint64_t va;
1097 unsigned window_space =
1098 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1099 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1100 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1101 unsigned input_prim = si_get_input_prim(gs_sel);
1102 bool break_wave_at_eoi = false;
1103 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1104 if (!pm4)
1105 return;
1106
1107 if (es_type == PIPE_SHADER_TESS_EVAL) {
1108 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1109 : gfx10_emit_shader_ngg_tess_nogs;
1110 } else {
1111 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1112 : gfx10_emit_shader_ngg_notess_nogs;
1113 }
1114
1115 va = shader->bo->gpu_address;
1116 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1117
1118 if (es_type == PIPE_SHADER_VERTEX) {
1119 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1120 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1121
1122 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1123 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1124 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1125 } else {
1126 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1127 }
1128 } else {
1129 assert(es_type == PIPE_SHADER_TESS_EVAL);
1130 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1131 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1132
1133 if (es_enable_prim_id || gs_info->uses_primid)
1134 break_wave_at_eoi = true;
1135 }
1136
1137 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1138 * VGPR[0:4] are always loaded.
1139 *
1140 * Vertex shaders always need to load VGPR3, because they need to
1141 * pass edge flags for decomposed primitives (such as quads) to the PA
1142 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1143 */
1144 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1145 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1146 else if (gs_info->uses_primid)
1147 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1148 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1149 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1150 else
1151 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1152
1153 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1154 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1155 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1156 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1157 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1158 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1159 S_00B228_DX10_CLAMP(1) |
1160 S_00B228_MEM_ORDERED(1) |
1161 S_00B228_WGP_MODE(1) |
1162 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1163 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1164 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1165 S_00B22C_USER_SGPR(num_user_sgprs) |
1166 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1167 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1168 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1169 S_00B22C_LDS_SIZE(shader->config.lds_size));
1170 si_set_ge_pc_alloc(sscreen, pm4, false);
1171
1172 nparams = MAX2(shader->info.nr_param_exports, 1);
1173 shader->ctx_reg.ngg.spi_vs_out_config =
1174 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1175 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1176
1177 shader->ctx_reg.ngg.spi_shader_idx_format =
1178 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1179 shader->ctx_reg.ngg.spi_shader_pos_format =
1180 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1181 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1182 V_02870C_SPI_SHADER_4COMP :
1183 V_02870C_SPI_SHADER_NONE) |
1184 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1185 V_02870C_SPI_SHADER_4COMP :
1186 V_02870C_SPI_SHADER_NONE) |
1187 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1188 V_02870C_SPI_SHADER_4COMP :
1189 V_02870C_SPI_SHADER_NONE);
1190
1191 shader->ctx_reg.ngg.vgt_primitiveid_en =
1192 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1193 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1194
1195 if (gs_type == PIPE_SHADER_GEOMETRY) {
1196 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1197 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1198 } else {
1199 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1200 }
1201
1202 if (es_type == PIPE_SHADER_TESS_EVAL)
1203 si_set_tesseval_regs(sscreen, es_sel, pm4);
1204
1205 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1206 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1207 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1208 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1209 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1210 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1211 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1212 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1213 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1214 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1215 S_028B90_CNT(gs_num_invocations) |
1216 S_028B90_ENABLE(gs_num_invocations > 1) |
1217 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1218 shader->ngg.max_vert_out_per_gs_instance);
1219
1220 /* Always output hw-generated edge flags and pass them via the prim
1221 * export to prevent drawing lines on internal edges of decomposed
1222 * primitives (such as quads) with polygon mode = lines. Only VS needs
1223 * this.
1224 */
1225 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1226 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1227
1228 shader->ge_cntl =
1229 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1230 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1231 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1232
1233 if (window_space) {
1234 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1235 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1236 } else {
1237 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1238 S_028818_VTX_W0_FMT(1) |
1239 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1240 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1241 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1242 }
1243
1244 shader->ctx_reg.ngg.vgt_reuse_off =
1245 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1246 sscreen->info.chip_external_rev == 0x1 &&
1247 es_type == PIPE_SHADER_TESS_EVAL);
1248 }
1249
1250 static void si_emit_shader_vs(struct si_context *sctx)
1251 {
1252 struct si_shader *shader = sctx->queued.named.vs->shader;
1253 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1254
1255 if (!shader)
1256 return;
1257
1258 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1259 SI_TRACKED_VGT_GS_MODE,
1260 shader->ctx_reg.vs.vgt_gs_mode);
1261 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1262 SI_TRACKED_VGT_PRIMITIVEID_EN,
1263 shader->ctx_reg.vs.vgt_primitiveid_en);
1264
1265 if (sctx->chip_class <= GFX8) {
1266 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1267 SI_TRACKED_VGT_REUSE_OFF,
1268 shader->ctx_reg.vs.vgt_reuse_off);
1269 }
1270
1271 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1272 SI_TRACKED_SPI_VS_OUT_CONFIG,
1273 shader->ctx_reg.vs.spi_vs_out_config);
1274
1275 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1276 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1277 shader->ctx_reg.vs.spi_shader_pos_format);
1278
1279 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1280 SI_TRACKED_PA_CL_VTE_CNTL,
1281 shader->ctx_reg.vs.pa_cl_vte_cntl);
1282
1283 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1284 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1285 SI_TRACKED_VGT_TF_PARAM,
1286 shader->vgt_tf_param);
1287
1288 if (shader->vgt_vertex_reuse_block_cntl)
1289 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1290 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1291 shader->vgt_vertex_reuse_block_cntl);
1292
1293 if (initial_cdw != sctx->gfx_cs->current.cdw)
1294 sctx->context_roll = true;
1295 }
1296
1297 /**
1298 * Compute the state for \p shader, which will run as a vertex shader on the
1299 * hardware.
1300 *
1301 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1302 * is the copy shader.
1303 */
1304 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1305 struct si_shader_selector *gs)
1306 {
1307 const struct tgsi_shader_info *info = &shader->selector->info;
1308 struct si_pm4_state *pm4;
1309 unsigned num_user_sgprs, vgpr_comp_cnt;
1310 uint64_t va;
1311 unsigned nparams, oc_lds_en;
1312 unsigned window_space =
1313 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1314 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1315
1316 pm4 = si_get_shader_pm4_state(shader);
1317 if (!pm4)
1318 return;
1319
1320 pm4->atom.emit = si_emit_shader_vs;
1321
1322 /* We always write VGT_GS_MODE in the VS state, because every switch
1323 * between different shader pipelines involving a different GS or no
1324 * GS at all involves a switch of the VS (different GS use different
1325 * copy shaders). On the other hand, when the API switches from a GS to
1326 * no GS and then back to the same GS used originally, the GS state is
1327 * not sent again.
1328 */
1329 if (!gs) {
1330 unsigned mode = V_028A40_GS_OFF;
1331
1332 /* PrimID needs GS scenario A. */
1333 if (enable_prim_id)
1334 mode = V_028A40_GS_SCENARIO_A;
1335
1336 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1337 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1338 } else {
1339 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1340 sscreen->info.chip_class);
1341 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1342 }
1343
1344 if (sscreen->info.chip_class <= GFX8) {
1345 /* Reuse needs to be set off if we write oViewport. */
1346 shader->ctx_reg.vs.vgt_reuse_off =
1347 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1348 }
1349
1350 va = shader->bo->gpu_address;
1351 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1352
1353 if (gs) {
1354 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1355 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1356 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1357 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1358 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1359 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1360 */
1361 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1362
1363 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1364 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1365 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1366 } else {
1367 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1368 }
1369 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1370 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1371 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1372 } else
1373 unreachable("invalid shader selector type");
1374
1375 /* VS is required to export at least one param. */
1376 nparams = MAX2(shader->info.nr_param_exports, 1);
1377 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1378
1379 if (sscreen->info.chip_class >= GFX10) {
1380 shader->ctx_reg.vs.spi_vs_out_config |=
1381 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1382 }
1383
1384 shader->ctx_reg.vs.spi_shader_pos_format =
1385 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1386 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1387 V_02870C_SPI_SHADER_4COMP :
1388 V_02870C_SPI_SHADER_NONE) |
1389 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1390 V_02870C_SPI_SHADER_4COMP :
1391 V_02870C_SPI_SHADER_NONE) |
1392 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1393 V_02870C_SPI_SHADER_4COMP :
1394 V_02870C_SPI_SHADER_NONE);
1395
1396 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1397
1398 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1399 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1400 if (sscreen->info.chip_class >= GFX10)
1401 si_set_ge_pc_alloc(sscreen, pm4, false);
1402
1403 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1404 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1405 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1406 S_00B128_DX10_CLAMP(1) |
1407 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1408 S_00B128_FLOAT_MODE(shader->config.float_mode);
1409 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1410 S_00B12C_OC_LDS_EN(oc_lds_en) |
1411 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1412
1413 if (sscreen->info.chip_class <= GFX9) {
1414 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1415 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1416 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1417 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1418 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1419 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1420 }
1421
1422 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1423 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1424
1425 if (window_space)
1426 shader->ctx_reg.vs.pa_cl_vte_cntl =
1427 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1428 else
1429 shader->ctx_reg.vs.pa_cl_vte_cntl =
1430 S_028818_VTX_W0_FMT(1) |
1431 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1432 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1433 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1434
1435 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1436 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1437
1438 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1439 }
1440
1441 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1442 {
1443 struct tgsi_shader_info *info = &ps->selector->info;
1444 unsigned num_colors = !!(info->colors_read & 0x0f) +
1445 !!(info->colors_read & 0xf0);
1446 unsigned num_interp = ps->selector->info.num_inputs +
1447 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1448
1449 assert(num_interp <= 32);
1450 return MIN2(num_interp, 32);
1451 }
1452
1453 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1454 {
1455 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1456 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1457
1458 /* If the i-th target format is set, all previous target formats must
1459 * be non-zero to avoid hangs.
1460 */
1461 for (i = 0; i < num_targets; i++)
1462 if (!(value & (0xf << (i * 4))))
1463 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1464
1465 return value;
1466 }
1467
1468 static void si_emit_shader_ps(struct si_context *sctx)
1469 {
1470 struct si_shader *shader = sctx->queued.named.ps->shader;
1471 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1472
1473 if (!shader)
1474 return;
1475
1476 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1477 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1478 SI_TRACKED_SPI_PS_INPUT_ENA,
1479 shader->ctx_reg.ps.spi_ps_input_ena,
1480 shader->ctx_reg.ps.spi_ps_input_addr);
1481
1482 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1483 SI_TRACKED_SPI_BARYC_CNTL,
1484 shader->ctx_reg.ps.spi_baryc_cntl);
1485 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1486 SI_TRACKED_SPI_PS_IN_CONTROL,
1487 shader->ctx_reg.ps.spi_ps_in_control);
1488
1489 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1490 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1491 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1492 shader->ctx_reg.ps.spi_shader_z_format,
1493 shader->ctx_reg.ps.spi_shader_col_format);
1494
1495 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1496 SI_TRACKED_CB_SHADER_MASK,
1497 shader->ctx_reg.ps.cb_shader_mask);
1498
1499 if (initial_cdw != sctx->gfx_cs->current.cdw)
1500 sctx->context_roll = true;
1501 }
1502
1503 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1504 {
1505 struct tgsi_shader_info *info = &shader->selector->info;
1506 struct si_pm4_state *pm4;
1507 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1508 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1509 uint64_t va;
1510 unsigned input_ena = shader->config.spi_ps_input_ena;
1511
1512 /* we need to enable at least one of them, otherwise we hang the GPU */
1513 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1514 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1515 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1516 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1517 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1518 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1519 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1520 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1521 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1522 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1523 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1524 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1525 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1526 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1527
1528 /* Validate interpolation optimization flags (read as implications). */
1529 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1530 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1531 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1532 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1533 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1534 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1535 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1536 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1537 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1538 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1539 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1540 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1541 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1542 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1543 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1544 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1545 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1546 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1547
1548 /* Validate cases when the optimizations are off (read as implications). */
1549 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1550 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1551 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1552 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1553 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1554 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1555
1556 pm4 = si_get_shader_pm4_state(shader);
1557 if (!pm4)
1558 return;
1559
1560 pm4->atom.emit = si_emit_shader_ps;
1561
1562 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1563 * Possible vaules:
1564 * 0 -> Position = pixel center
1565 * 1 -> Position = pixel centroid
1566 * 2 -> Position = at sample position
1567 *
1568 * From GLSL 4.5 specification, section 7.1:
1569 * "The variable gl_FragCoord is available as an input variable from
1570 * within fragment shaders and it holds the window relative coordinates
1571 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1572 * value can be for any location within the pixel, or one of the
1573 * fragment samples. The use of centroid does not further restrict
1574 * this value to be inside the current primitive."
1575 *
1576 * Meaning that centroid has no effect and we can return anything within
1577 * the pixel. Thus, return the value at sample position, because that's
1578 * the most accurate one shaders can get.
1579 */
1580 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1581
1582 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1583 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1584 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1585
1586 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1587 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1588
1589 /* Ensure that some export memory is always allocated, for two reasons:
1590 *
1591 * 1) Correctness: The hardware ignores the EXEC mask if no export
1592 * memory is allocated, so KILL and alpha test do not work correctly
1593 * without this.
1594 * 2) Performance: Every shader needs at least a NULL export, even when
1595 * it writes no color/depth output. The NULL export instruction
1596 * stalls without this setting.
1597 *
1598 * Don't add this to CB_SHADER_MASK.
1599 *
1600 * GFX10 supports pixel shaders without exports by setting both
1601 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1602 * instructions if any are present.
1603 */
1604 if ((sscreen->info.chip_class <= GFX9 ||
1605 info->uses_kill ||
1606 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1607 !spi_shader_col_format &&
1608 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1609 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1610
1611 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1612 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1613
1614 /* Set interpolation controls. */
1615 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1616 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1617
1618 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1619 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1620 shader->ctx_reg.ps.spi_shader_z_format =
1621 ac_get_spi_shader_z_format(info->writes_z,
1622 info->writes_stencil,
1623 info->writes_samplemask);
1624 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1625 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1626
1627 va = shader->bo->gpu_address;
1628 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1629 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1630 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1631
1632 uint32_t rsrc1 =
1633 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1634 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1635 S_00B028_DX10_CLAMP(1) |
1636 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1637 S_00B028_FLOAT_MODE(shader->config.float_mode);
1638
1639 if (sscreen->info.chip_class < GFX10) {
1640 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1641 }
1642
1643 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1644 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1645 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1646 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1647 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1648 }
1649
1650 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1651 struct si_shader *shader)
1652 {
1653 switch (shader->selector->type) {
1654 case PIPE_SHADER_VERTEX:
1655 if (shader->key.as_ls)
1656 si_shader_ls(sscreen, shader);
1657 else if (shader->key.as_es)
1658 si_shader_es(sscreen, shader);
1659 else if (shader->key.as_ngg)
1660 gfx10_shader_ngg(sscreen, shader);
1661 else
1662 si_shader_vs(sscreen, shader, NULL);
1663 break;
1664 case PIPE_SHADER_TESS_CTRL:
1665 si_shader_hs(sscreen, shader);
1666 break;
1667 case PIPE_SHADER_TESS_EVAL:
1668 if (shader->key.as_es)
1669 si_shader_es(sscreen, shader);
1670 else if (shader->key.as_ngg)
1671 gfx10_shader_ngg(sscreen, shader);
1672 else
1673 si_shader_vs(sscreen, shader, NULL);
1674 break;
1675 case PIPE_SHADER_GEOMETRY:
1676 if (shader->key.as_ngg)
1677 gfx10_shader_ngg(sscreen, shader);
1678 else
1679 si_shader_gs(sscreen, shader);
1680 break;
1681 case PIPE_SHADER_FRAGMENT:
1682 si_shader_ps(sscreen, shader);
1683 break;
1684 default:
1685 assert(0);
1686 }
1687 }
1688
1689 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1690 {
1691 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1692 return sctx->queued.named.dsa->alpha_func;
1693 }
1694
1695 void si_shader_selector_key_vs(struct si_context *sctx,
1696 struct si_shader_selector *vs,
1697 struct si_shader_key *key,
1698 struct si_vs_prolog_bits *prolog_key)
1699 {
1700 if (!sctx->vertex_elements ||
1701 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1702 return;
1703
1704 struct si_vertex_elements *elts = sctx->vertex_elements;
1705
1706 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1707 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1708 prolog_key->unpack_instance_id_from_vertex_id =
1709 sctx->prim_discard_cs_instancing;
1710
1711 /* Prefer a monolithic shader to allow scheduling divisions around
1712 * VBO loads. */
1713 if (prolog_key->instance_divisor_is_fetched)
1714 key->opt.prefer_mono = 1;
1715
1716 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1717 unsigned count_mask = (1 << count) - 1;
1718 unsigned fix = elts->fix_fetch_always & count_mask;
1719 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1720
1721 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1722 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1723 while (mask) {
1724 unsigned i = u_bit_scan(&mask);
1725 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1726 unsigned vbidx = elts->vertex_buffer_index[i];
1727 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1728 unsigned align_mask = (1 << log_hw_load_size) - 1;
1729 if (vb->buffer_offset & align_mask ||
1730 vb->stride & align_mask) {
1731 fix |= 1 << i;
1732 opencode |= 1 << i;
1733 }
1734 }
1735 }
1736
1737 while (fix) {
1738 unsigned i = u_bit_scan(&fix);
1739 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1740 }
1741 key->mono.vs_fetch_opencode = opencode;
1742 }
1743
1744 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1745 struct si_shader_selector *vs,
1746 struct si_shader_key *key)
1747 {
1748 struct si_shader_selector *ps = sctx->ps_shader.cso;
1749
1750 key->opt.clip_disable =
1751 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1752 (vs->info.clipdist_writemask ||
1753 vs->info.writes_clipvertex) &&
1754 !vs->info.culldist_writemask;
1755
1756 /* Find out if PS is disabled. */
1757 bool ps_disabled = true;
1758 if (ps) {
1759 bool ps_modifies_zs = ps->info.uses_kill ||
1760 ps->info.writes_z ||
1761 ps->info.writes_stencil ||
1762 ps->info.writes_samplemask ||
1763 sctx->queued.named.blend->alpha_to_coverage ||
1764 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1765 unsigned ps_colormask = si_get_total_colormask(sctx);
1766
1767 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1768 (!ps_colormask &&
1769 !ps_modifies_zs &&
1770 !ps->info.writes_memory);
1771 }
1772
1773 /* Find out which VS outputs aren't used by the PS. */
1774 uint64_t outputs_written = vs->outputs_written_before_ps;
1775 uint64_t inputs_read = 0;
1776
1777 /* Ignore outputs that are not passed from VS to PS. */
1778 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1779 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1780 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1781
1782 if (!ps_disabled) {
1783 inputs_read = ps->inputs_read;
1784 }
1785
1786 uint64_t linked = outputs_written & inputs_read;
1787
1788 key->opt.kill_outputs = ~linked & outputs_written;
1789 }
1790
1791 /* Compute the key for the hw shader variant */
1792 static inline void si_shader_selector_key(struct pipe_context *ctx,
1793 struct si_shader_selector *sel,
1794 union si_vgt_stages_key stages_key,
1795 struct si_shader_key *key)
1796 {
1797 struct si_context *sctx = (struct si_context *)ctx;
1798
1799 memset(key, 0, sizeof(*key));
1800
1801 switch (sel->type) {
1802 case PIPE_SHADER_VERTEX:
1803 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1804
1805 if (sctx->tes_shader.cso)
1806 key->as_ls = 1;
1807 else if (sctx->gs_shader.cso)
1808 key->as_es = 1;
1809 else {
1810 key->as_ngg = stages_key.u.ngg;
1811 si_shader_selector_key_hw_vs(sctx, sel, key);
1812
1813 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1814 key->mono.u.vs_export_prim_id = 1;
1815 }
1816 break;
1817 case PIPE_SHADER_TESS_CTRL:
1818 if (sctx->chip_class >= GFX9) {
1819 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1820 key, &key->part.tcs.ls_prolog);
1821 key->part.tcs.ls = sctx->vs_shader.cso;
1822
1823 /* When the LS VGPR fix is needed, monolithic shaders
1824 * can:
1825 * - avoid initializing EXEC in both the LS prolog
1826 * and the LS main part when !vs_needs_prolog
1827 * - remove the fixup for unused input VGPRs
1828 */
1829 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1830
1831 /* The LS output / HS input layout can be communicated
1832 * directly instead of via user SGPRs for merged LS-HS.
1833 * The LS VGPR fix prefers this too.
1834 */
1835 key->opt.prefer_mono = 1;
1836 }
1837
1838 key->part.tcs.epilog.prim_mode =
1839 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1840 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1841 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1842 key->part.tcs.epilog.tes_reads_tess_factors =
1843 sctx->tes_shader.cso->info.reads_tess_factors;
1844
1845 if (sel == sctx->fixed_func_tcs_shader.cso)
1846 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1847 break;
1848 case PIPE_SHADER_TESS_EVAL:
1849 key->as_ngg = stages_key.u.ngg;
1850
1851 if (sctx->gs_shader.cso)
1852 key->as_es = 1;
1853 else {
1854 si_shader_selector_key_hw_vs(sctx, sel, key);
1855
1856 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1857 key->mono.u.vs_export_prim_id = 1;
1858 }
1859 break;
1860 case PIPE_SHADER_GEOMETRY:
1861 if (sctx->chip_class >= GFX9) {
1862 if (sctx->tes_shader.cso) {
1863 key->part.gs.es = sctx->tes_shader.cso;
1864 } else {
1865 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1866 key, &key->part.gs.vs_prolog);
1867 key->part.gs.es = sctx->vs_shader.cso;
1868 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1869 }
1870
1871 key->as_ngg = stages_key.u.ngg;
1872
1873 /* Merged ES-GS can have unbalanced wave usage.
1874 *
1875 * ES threads are per-vertex, while GS threads are
1876 * per-primitive. So without any amplification, there
1877 * are fewer GS threads than ES threads, which can result
1878 * in empty (no-op) GS waves. With too much amplification,
1879 * there are more GS threads than ES threads, which
1880 * can result in empty (no-op) ES waves.
1881 *
1882 * Non-monolithic shaders are implemented by setting EXEC
1883 * at the beginning of shader parts, and don't jump to
1884 * the end if EXEC is 0.
1885 *
1886 * Monolithic shaders use conditional blocks, so they can
1887 * jump and skip empty waves of ES or GS. So set this to
1888 * always use optimized variants, which are monolithic.
1889 */
1890 key->opt.prefer_mono = 1;
1891 }
1892 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1893 break;
1894 case PIPE_SHADER_FRAGMENT: {
1895 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1896 struct si_state_blend *blend = sctx->queued.named.blend;
1897
1898 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1899 sel->info.colors_written == 0x1)
1900 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1901
1902 /* Select the shader color format based on whether
1903 * blending or alpha are needed.
1904 */
1905 key->part.ps.epilog.spi_shader_col_format =
1906 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1907 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1908 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1909 sctx->framebuffer.spi_shader_col_format_blend) |
1910 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1911 sctx->framebuffer.spi_shader_col_format_alpha) |
1912 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1913 sctx->framebuffer.spi_shader_col_format);
1914 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1915
1916 /* The output for dual source blending should have
1917 * the same format as the first output.
1918 */
1919 if (blend->dual_src_blend) {
1920 key->part.ps.epilog.spi_shader_col_format |=
1921 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1922 }
1923
1924 /* If alpha-to-coverage is enabled, we have to export alpha
1925 * even if there is no color buffer.
1926 */
1927 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1928 blend->alpha_to_coverage)
1929 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1930
1931 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1932 * to the range supported by the type if a channel has less
1933 * than 16 bits and the export format is 16_ABGR.
1934 */
1935 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1936 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1937 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1938 }
1939
1940 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1941 if (!key->part.ps.epilog.last_cbuf) {
1942 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1943 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1944 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1945 }
1946
1947 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1948 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1949
1950 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1951 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1952
1953 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
1954 rs->multisample_enable;
1955
1956 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1957 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1958 (is_line && rs->line_smooth)) &&
1959 sctx->framebuffer.nr_samples <= 1;
1960 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1961
1962 if (sctx->ps_iter_samples > 1 &&
1963 sel->info.reads_samplemask) {
1964 key->part.ps.prolog.samplemask_log_ps_iter =
1965 util_logbase2(sctx->ps_iter_samples);
1966 }
1967
1968 if (rs->force_persample_interp &&
1969 rs->multisample_enable &&
1970 sctx->framebuffer.nr_samples > 1 &&
1971 sctx->ps_iter_samples > 1) {
1972 key->part.ps.prolog.force_persp_sample_interp =
1973 sel->info.uses_persp_center ||
1974 sel->info.uses_persp_centroid;
1975
1976 key->part.ps.prolog.force_linear_sample_interp =
1977 sel->info.uses_linear_center ||
1978 sel->info.uses_linear_centroid;
1979 } else if (rs->multisample_enable &&
1980 sctx->framebuffer.nr_samples > 1) {
1981 key->part.ps.prolog.bc_optimize_for_persp =
1982 sel->info.uses_persp_center &&
1983 sel->info.uses_persp_centroid;
1984 key->part.ps.prolog.bc_optimize_for_linear =
1985 sel->info.uses_linear_center &&
1986 sel->info.uses_linear_centroid;
1987 } else {
1988 /* Make sure SPI doesn't compute more than 1 pair
1989 * of (i,j), which is the optimization here. */
1990 key->part.ps.prolog.force_persp_center_interp =
1991 sel->info.uses_persp_center +
1992 sel->info.uses_persp_centroid +
1993 sel->info.uses_persp_sample > 1;
1994
1995 key->part.ps.prolog.force_linear_center_interp =
1996 sel->info.uses_linear_center +
1997 sel->info.uses_linear_centroid +
1998 sel->info.uses_linear_sample > 1;
1999
2000 if (sel->info.uses_persp_opcode_interp_sample ||
2001 sel->info.uses_linear_opcode_interp_sample)
2002 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2003 }
2004
2005 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2006
2007 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2008 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2009 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2010 struct pipe_resource *tex = cb0->texture;
2011
2012 /* 1D textures are allocated and used as 2D on GFX9. */
2013 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2014 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2015 (tex->target == PIPE_TEXTURE_1D ||
2016 tex->target == PIPE_TEXTURE_1D_ARRAY);
2017 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2018 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2019 tex->target == PIPE_TEXTURE_CUBE ||
2020 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2021 tex->target == PIPE_TEXTURE_3D;
2022 }
2023 break;
2024 }
2025 default:
2026 assert(0);
2027 }
2028
2029 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2030 memset(&key->opt, 0, sizeof(key->opt));
2031 }
2032
2033 static void si_build_shader_variant(struct si_shader *shader,
2034 int thread_index,
2035 bool low_priority)
2036 {
2037 struct si_shader_selector *sel = shader->selector;
2038 struct si_screen *sscreen = sel->screen;
2039 struct ac_llvm_compiler *compiler;
2040 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2041
2042 if (thread_index >= 0) {
2043 if (low_priority) {
2044 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2045 compiler = &sscreen->compiler_lowp[thread_index];
2046 } else {
2047 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2048 compiler = &sscreen->compiler[thread_index];
2049 }
2050 if (!debug->async)
2051 debug = NULL;
2052 } else {
2053 assert(!low_priority);
2054 compiler = shader->compiler_ctx_state.compiler;
2055 }
2056
2057 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2058 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2059 sel->type);
2060 shader->compilation_failed = true;
2061 return;
2062 }
2063
2064 if (shader->compiler_ctx_state.is_debug_context) {
2065 FILE *f = open_memstream(&shader->shader_log,
2066 &shader->shader_log_size);
2067 if (f) {
2068 si_shader_dump(sscreen, shader, NULL, f, false);
2069 fclose(f);
2070 }
2071 }
2072
2073 si_shader_init_pm4_state(sscreen, shader);
2074 }
2075
2076 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2077 {
2078 struct si_shader *shader = (struct si_shader *)job;
2079
2080 assert(thread_index >= 0);
2081
2082 si_build_shader_variant(shader, thread_index, true);
2083 }
2084
2085 static const struct si_shader_key zeroed;
2086
2087 static bool si_check_missing_main_part(struct si_screen *sscreen,
2088 struct si_shader_selector *sel,
2089 struct si_compiler_ctx_state *compiler_state,
2090 struct si_shader_key *key)
2091 {
2092 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2093
2094 if (!*mainp) {
2095 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2096
2097 if (!main_part)
2098 return false;
2099
2100 /* We can leave the fence as permanently signaled because the
2101 * main part becomes visible globally only after it has been
2102 * compiled. */
2103 util_queue_fence_init(&main_part->ready);
2104
2105 main_part->selector = sel;
2106 main_part->key.as_es = key->as_es;
2107 main_part->key.as_ls = key->as_ls;
2108 main_part->key.as_ngg = key->as_ngg;
2109 main_part->is_monolithic = false;
2110
2111 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2112 main_part, &compiler_state->debug) != 0) {
2113 FREE(main_part);
2114 return false;
2115 }
2116 *mainp = main_part;
2117 }
2118 return true;
2119 }
2120
2121 /**
2122 * Select a shader variant according to the shader key.
2123 *
2124 * \param optimized_or_none If the key describes an optimized shader variant and
2125 * the compilation isn't finished, don't select any
2126 * shader and return an error.
2127 */
2128 int si_shader_select_with_key(struct si_screen *sscreen,
2129 struct si_shader_ctx_state *state,
2130 struct si_compiler_ctx_state *compiler_state,
2131 struct si_shader_key *key,
2132 int thread_index,
2133 bool optimized_or_none)
2134 {
2135 struct si_shader_selector *sel = state->cso;
2136 struct si_shader_selector *previous_stage_sel = NULL;
2137 struct si_shader *current = state->current;
2138 struct si_shader *iter, *shader = NULL;
2139
2140 again:
2141 /* Check if we don't need to change anything.
2142 * This path is also used for most shaders that don't need multiple
2143 * variants, it will cost just a computation of the key and this
2144 * test. */
2145 if (likely(current &&
2146 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2147 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2148 if (current->is_optimized) {
2149 if (optimized_or_none)
2150 return -1;
2151
2152 memset(&key->opt, 0, sizeof(key->opt));
2153 goto current_not_ready;
2154 }
2155
2156 util_queue_fence_wait(&current->ready);
2157 }
2158
2159 return current->compilation_failed ? -1 : 0;
2160 }
2161 current_not_ready:
2162
2163 /* This must be done before the mutex is locked, because async GS
2164 * compilation calls this function too, and therefore must enter
2165 * the mutex first.
2166 *
2167 * Only wait if we are in a draw call. Don't wait if we are
2168 * in a compiler thread.
2169 */
2170 if (thread_index < 0)
2171 util_queue_fence_wait(&sel->ready);
2172
2173 mtx_lock(&sel->mutex);
2174
2175 /* Find the shader variant. */
2176 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2177 /* Don't check the "current" shader. We checked it above. */
2178 if (current != iter &&
2179 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2180 mtx_unlock(&sel->mutex);
2181
2182 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2183 /* If it's an optimized shader and its compilation has
2184 * been started but isn't done, use the unoptimized
2185 * shader so as not to cause a stall due to compilation.
2186 */
2187 if (iter->is_optimized) {
2188 if (optimized_or_none)
2189 return -1;
2190 memset(&key->opt, 0, sizeof(key->opt));
2191 goto again;
2192 }
2193
2194 util_queue_fence_wait(&iter->ready);
2195 }
2196
2197 if (iter->compilation_failed) {
2198 return -1; /* skip the draw call */
2199 }
2200
2201 state->current = iter;
2202 return 0;
2203 }
2204 }
2205
2206 /* Build a new shader. */
2207 shader = CALLOC_STRUCT(si_shader);
2208 if (!shader) {
2209 mtx_unlock(&sel->mutex);
2210 return -ENOMEM;
2211 }
2212
2213 util_queue_fence_init(&shader->ready);
2214
2215 shader->selector = sel;
2216 shader->key = *key;
2217 shader->compiler_ctx_state = *compiler_state;
2218
2219 /* If this is a merged shader, get the first shader's selector. */
2220 if (sscreen->info.chip_class >= GFX9) {
2221 if (sel->type == PIPE_SHADER_TESS_CTRL)
2222 previous_stage_sel = key->part.tcs.ls;
2223 else if (sel->type == PIPE_SHADER_GEOMETRY)
2224 previous_stage_sel = key->part.gs.es;
2225
2226 /* We need to wait for the previous shader. */
2227 if (previous_stage_sel && thread_index < 0)
2228 util_queue_fence_wait(&previous_stage_sel->ready);
2229 }
2230
2231 bool is_pure_monolithic =
2232 sscreen->use_monolithic_shaders ||
2233 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2234
2235 /* Compile the main shader part if it doesn't exist. This can happen
2236 * if the initial guess was wrong.
2237 *
2238 * The prim discard CS doesn't need the main shader part.
2239 */
2240 if (!is_pure_monolithic &&
2241 !key->opt.vs_as_prim_discard_cs) {
2242 bool ok = true;
2243
2244 /* Make sure the main shader part is present. This is needed
2245 * for shaders that can be compiled as VS, LS, or ES, and only
2246 * one of them is compiled at creation.
2247 *
2248 * It is also needed for GS, which can be compiled as non-NGG
2249 * and NGG.
2250 *
2251 * For merged shaders, check that the starting shader's main
2252 * part is present.
2253 */
2254 if (previous_stage_sel) {
2255 struct si_shader_key shader1_key = zeroed;
2256
2257 if (sel->type == PIPE_SHADER_TESS_CTRL)
2258 shader1_key.as_ls = 1;
2259 else if (sel->type == PIPE_SHADER_GEOMETRY)
2260 shader1_key.as_es = 1;
2261 else
2262 assert(0);
2263
2264 if (sel->type == PIPE_SHADER_GEOMETRY &&
2265 previous_stage_sel->type == PIPE_SHADER_TESS_EVAL)
2266 shader1_key.as_ngg = key->as_ngg;
2267
2268 mtx_lock(&previous_stage_sel->mutex);
2269 ok = si_check_missing_main_part(sscreen,
2270 previous_stage_sel,
2271 compiler_state, &shader1_key);
2272 mtx_unlock(&previous_stage_sel->mutex);
2273 }
2274
2275 if (ok) {
2276 ok = si_check_missing_main_part(sscreen, sel,
2277 compiler_state, key);
2278 }
2279
2280 if (!ok) {
2281 FREE(shader);
2282 mtx_unlock(&sel->mutex);
2283 return -ENOMEM; /* skip the draw call */
2284 }
2285 }
2286
2287 /* Keep the reference to the 1st shader of merged shaders, so that
2288 * Gallium can't destroy it before we destroy the 2nd shader.
2289 *
2290 * Set sctx = NULL, because it's unused if we're not releasing
2291 * the shader, and we don't have any sctx here.
2292 */
2293 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2294 previous_stage_sel);
2295
2296 /* Monolithic-only shaders don't make a distinction between optimized
2297 * and unoptimized. */
2298 shader->is_monolithic =
2299 is_pure_monolithic ||
2300 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2301
2302 /* The prim discard CS is always optimized. */
2303 shader->is_optimized =
2304 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2305 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2306
2307 /* If it's an optimized shader, compile it asynchronously. */
2308 if (shader->is_optimized && thread_index < 0) {
2309 /* Compile it asynchronously. */
2310 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2311 shader, &shader->ready,
2312 si_build_shader_variant_low_priority, NULL);
2313
2314 /* Add only after the ready fence was reset, to guard against a
2315 * race with si_bind_XX_shader. */
2316 if (!sel->last_variant) {
2317 sel->first_variant = shader;
2318 sel->last_variant = shader;
2319 } else {
2320 sel->last_variant->next_variant = shader;
2321 sel->last_variant = shader;
2322 }
2323
2324 /* Use the default (unoptimized) shader for now. */
2325 memset(&key->opt, 0, sizeof(key->opt));
2326 mtx_unlock(&sel->mutex);
2327
2328 if (sscreen->options.sync_compile)
2329 util_queue_fence_wait(&shader->ready);
2330
2331 if (optimized_or_none)
2332 return -1;
2333 goto again;
2334 }
2335
2336 /* Reset the fence before adding to the variant list. */
2337 util_queue_fence_reset(&shader->ready);
2338
2339 if (!sel->last_variant) {
2340 sel->first_variant = shader;
2341 sel->last_variant = shader;
2342 } else {
2343 sel->last_variant->next_variant = shader;
2344 sel->last_variant = shader;
2345 }
2346
2347 mtx_unlock(&sel->mutex);
2348
2349 assert(!shader->is_optimized);
2350 si_build_shader_variant(shader, thread_index, false);
2351
2352 util_queue_fence_signal(&shader->ready);
2353
2354 if (!shader->compilation_failed)
2355 state->current = shader;
2356
2357 return shader->compilation_failed ? -1 : 0;
2358 }
2359
2360 static int si_shader_select(struct pipe_context *ctx,
2361 struct si_shader_ctx_state *state,
2362 union si_vgt_stages_key stages_key,
2363 struct si_compiler_ctx_state *compiler_state)
2364 {
2365 struct si_context *sctx = (struct si_context *)ctx;
2366 struct si_shader_key key;
2367
2368 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2369 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2370 &key, -1, false);
2371 }
2372
2373 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2374 bool streamout,
2375 struct si_shader_key *key)
2376 {
2377 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2378
2379 switch (info->processor) {
2380 case PIPE_SHADER_VERTEX:
2381 switch (next_shader) {
2382 case PIPE_SHADER_GEOMETRY:
2383 key->as_es = 1;
2384 break;
2385 case PIPE_SHADER_TESS_CTRL:
2386 case PIPE_SHADER_TESS_EVAL:
2387 key->as_ls = 1;
2388 break;
2389 default:
2390 /* If POSITION isn't written, it can only be a HW VS
2391 * if streamout is used. If streamout isn't used,
2392 * assume that it's a HW LS. (the next shader is TCS)
2393 * This heuristic is needed for separate shader objects.
2394 */
2395 if (!info->writes_position && !streamout)
2396 key->as_ls = 1;
2397 }
2398 break;
2399
2400 case PIPE_SHADER_TESS_EVAL:
2401 if (next_shader == PIPE_SHADER_GEOMETRY ||
2402 !info->writes_position)
2403 key->as_es = 1;
2404 break;
2405 }
2406 }
2407
2408 /**
2409 * Compile the main shader part or the monolithic shader as part of
2410 * si_shader_selector initialization. Since it can be done asynchronously,
2411 * there is no way to report compile failures to applications.
2412 */
2413 static void si_init_shader_selector_async(void *job, int thread_index)
2414 {
2415 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2416 struct si_screen *sscreen = sel->screen;
2417 struct ac_llvm_compiler *compiler;
2418 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2419
2420 assert(!debug->debug_message || debug->async);
2421 assert(thread_index >= 0);
2422 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2423 compiler = &sscreen->compiler[thread_index];
2424
2425 if (sel->nir) {
2426 /* TODO: GS always sets wave size = default. Legacy GS will have
2427 * incorrect subgroup_size and ballot_bit_size. */
2428 si_lower_nir(sel, si_get_wave_size(sscreen, sel->type, true, false));
2429 }
2430
2431 /* Compile the main shader part for use with a prolog and/or epilog.
2432 * If this fails, the driver will try to compile a monolithic shader
2433 * on demand.
2434 */
2435 if (!sscreen->use_monolithic_shaders) {
2436 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2437 void *ir_binary = NULL;
2438
2439 if (!shader) {
2440 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2441 return;
2442 }
2443
2444 /* We can leave the fence signaled because use of the default
2445 * main part is guarded by the selector's ready fence. */
2446 util_queue_fence_init(&shader->ready);
2447
2448 shader->selector = sel;
2449 shader->is_monolithic = false;
2450 si_parse_next_shader_property(&sel->info,
2451 sel->so.num_outputs != 0,
2452 &shader->key);
2453 if (sscreen->info.chip_class >= GFX10 &&
2454 ((sel->type == PIPE_SHADER_VERTEX &&
2455 !shader->key.as_ls && !shader->key.as_es) ||
2456 sel->type == PIPE_SHADER_TESS_EVAL ||
2457 sel->type == PIPE_SHADER_GEOMETRY))
2458 shader->key.as_ngg = 1;
2459
2460 if (sel->tokens || sel->nir)
2461 ir_binary = si_get_ir_binary(sel);
2462
2463 /* Try to load the shader from the shader cache. */
2464 mtx_lock(&sscreen->shader_cache_mutex);
2465
2466 if (ir_binary &&
2467 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2468 mtx_unlock(&sscreen->shader_cache_mutex);
2469 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2470 } else {
2471 mtx_unlock(&sscreen->shader_cache_mutex);
2472
2473 /* Compile the shader if it hasn't been loaded from the cache. */
2474 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2475 debug) != 0) {
2476 FREE(shader);
2477 FREE(ir_binary);
2478 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2479 return;
2480 }
2481
2482 if (ir_binary) {
2483 mtx_lock(&sscreen->shader_cache_mutex);
2484 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2485 FREE(ir_binary);
2486 mtx_unlock(&sscreen->shader_cache_mutex);
2487 }
2488 }
2489
2490 *si_get_main_shader_part(sel, &shader->key) = shader;
2491
2492 /* Unset "outputs_written" flags for outputs converted to
2493 * DEFAULT_VAL, so that later inter-shader optimizations don't
2494 * try to eliminate outputs that don't exist in the final
2495 * shader.
2496 *
2497 * This is only done if non-monolithic shaders are enabled.
2498 */
2499 if ((sel->type == PIPE_SHADER_VERTEX ||
2500 sel->type == PIPE_SHADER_TESS_EVAL) &&
2501 !shader->key.as_ls &&
2502 !shader->key.as_es) {
2503 unsigned i;
2504
2505 for (i = 0; i < sel->info.num_outputs; i++) {
2506 unsigned offset = shader->info.vs_output_param_offset[i];
2507
2508 if (offset <= AC_EXP_PARAM_OFFSET_31)
2509 continue;
2510
2511 unsigned name = sel->info.output_semantic_name[i];
2512 unsigned index = sel->info.output_semantic_index[i];
2513 unsigned id;
2514
2515 switch (name) {
2516 case TGSI_SEMANTIC_GENERIC:
2517 /* don't process indices the function can't handle */
2518 if (index >= SI_MAX_IO_GENERIC)
2519 break;
2520 /* fall through */
2521 default:
2522 id = si_shader_io_get_unique_index(name, index, true);
2523 sel->outputs_written_before_ps &= ~(1ull << id);
2524 break;
2525 case TGSI_SEMANTIC_POSITION: /* ignore these */
2526 case TGSI_SEMANTIC_PSIZE:
2527 case TGSI_SEMANTIC_CLIPVERTEX:
2528 case TGSI_SEMANTIC_EDGEFLAG:
2529 break;
2530 }
2531 }
2532 }
2533 }
2534
2535 /* The GS copy shader is always pre-compiled. */
2536 if (sel->type == PIPE_SHADER_GEOMETRY &&
2537 (sscreen->info.chip_class <= GFX9 || sel->tess_turns_off_ngg)) {
2538 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2539 if (!sel->gs_copy_shader) {
2540 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2541 return;
2542 }
2543
2544 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2545 }
2546 }
2547
2548 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2549 struct util_queue_fence *ready_fence,
2550 struct si_compiler_ctx_state *compiler_ctx_state,
2551 void *job, util_queue_execute_func execute)
2552 {
2553 util_queue_fence_init(ready_fence);
2554
2555 struct util_async_debug_callback async_debug;
2556 bool debug =
2557 (sctx->debug.debug_message && !sctx->debug.async) ||
2558 sctx->is_debug ||
2559 si_can_dump_shader(sctx->screen, processor);
2560
2561 if (debug) {
2562 u_async_debug_init(&async_debug);
2563 compiler_ctx_state->debug = async_debug.base;
2564 }
2565
2566 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2567 ready_fence, execute, NULL);
2568
2569 if (debug) {
2570 util_queue_fence_wait(ready_fence);
2571 u_async_debug_drain(&async_debug, &sctx->debug);
2572 u_async_debug_cleanup(&async_debug);
2573 }
2574
2575 if (sctx->screen->options.sync_compile)
2576 util_queue_fence_wait(ready_fence);
2577 }
2578
2579 /* Return descriptor slot usage masks from the given shader info. */
2580 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2581 uint32_t *const_and_shader_buffers,
2582 uint64_t *samplers_and_images)
2583 {
2584 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2585
2586 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2587 num_constbufs = util_last_bit(info->const_buffers_declared);
2588 /* two 8-byte images share one 16-byte slot */
2589 num_images = align(util_last_bit(info->images_declared), 2);
2590 num_samplers = util_last_bit(info->samplers_declared);
2591
2592 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2593 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2594 *const_and_shader_buffers =
2595 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2596
2597 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2598 start = si_get_image_slot(num_images - 1) / 2;
2599 *samplers_and_images =
2600 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2601 }
2602
2603 static void *si_create_shader_selector(struct pipe_context *ctx,
2604 const struct pipe_shader_state *state)
2605 {
2606 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2607 struct si_context *sctx = (struct si_context*)ctx;
2608 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2609 int i;
2610
2611 if (!sel)
2612 return NULL;
2613
2614 pipe_reference_init(&sel->reference, 1);
2615 sel->screen = sscreen;
2616 sel->compiler_ctx_state.debug = sctx->debug;
2617 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2618
2619 sel->so = state->stream_output;
2620
2621 if (state->type == PIPE_SHADER_IR_TGSI &&
2622 !sscreen->options.always_nir) {
2623 sel->tokens = tgsi_dup_tokens(state->tokens);
2624 if (!sel->tokens) {
2625 FREE(sel);
2626 return NULL;
2627 }
2628
2629 tgsi_scan_shader(state->tokens, &sel->info);
2630 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2631
2632 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2633 if (sel->info.uses_persp_opcode_interp_centroid)
2634 sel->info.uses_persp_centroid = true;
2635
2636 if (sel->info.uses_linear_opcode_interp_centroid)
2637 sel->info.uses_linear_centroid = true;
2638
2639 if (sel->info.uses_persp_opcode_interp_offset ||
2640 sel->info.uses_persp_opcode_interp_sample)
2641 sel->info.uses_persp_center = true;
2642
2643 if (sel->info.uses_linear_opcode_interp_offset ||
2644 sel->info.uses_linear_opcode_interp_sample)
2645 sel->info.uses_linear_center = true;
2646 } else {
2647 if (state->type == PIPE_SHADER_IR_TGSI) {
2648 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2649 } else {
2650 assert(state->type == PIPE_SHADER_IR_NIR);
2651 sel->nir = state->ir.nir;
2652 }
2653
2654 si_nir_lower_ps_inputs(sel->nir);
2655 si_nir_opts(sel->nir);
2656 si_nir_scan_shader(sel->nir, &sel->info);
2657 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2658 }
2659
2660 sel->type = sel->info.processor;
2661 p_atomic_inc(&sscreen->num_shaders_created);
2662 si_get_active_slot_masks(&sel->info,
2663 &sel->active_const_and_shader_buffers,
2664 &sel->active_samplers_and_images);
2665
2666 /* Record which streamout buffers are enabled. */
2667 for (i = 0; i < sel->so.num_outputs; i++) {
2668 sel->enabled_streamout_buffer_mask |=
2669 (1 << sel->so.output[i].output_buffer) <<
2670 (sel->so.output[i].stream * 4);
2671 }
2672
2673 /* The prolog is a no-op if there are no inputs. */
2674 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2675 sel->info.num_inputs &&
2676 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2677
2678 sel->force_correct_derivs_after_kill =
2679 sel->type == PIPE_SHADER_FRAGMENT &&
2680 sel->info.uses_derivatives &&
2681 sel->info.uses_kill &&
2682 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2683
2684 sel->prim_discard_cs_allowed =
2685 sel->type == PIPE_SHADER_VERTEX &&
2686 !sel->info.uses_bindless_images &&
2687 !sel->info.uses_bindless_samplers &&
2688 !sel->info.writes_memory &&
2689 !sel->info.writes_viewport_index &&
2690 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2691 !sel->so.num_outputs;
2692
2693 if (sel->type == PIPE_SHADER_VERTEX &&
2694 sel->info.writes_edgeflag) {
2695 if (sscreen->info.chip_class >= GFX10)
2696 sel->ngg_writes_edgeflag = true;
2697 else
2698 sel->pos_writes_edgeflag = true;
2699 }
2700
2701 switch (sel->type) {
2702 case PIPE_SHADER_GEOMETRY:
2703 sel->gs_output_prim =
2704 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2705
2706 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2707 sel->rast_prim = sel->gs_output_prim;
2708 if (util_rast_prim_is_triangles(sel->rast_prim))
2709 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2710
2711 sel->gs_max_out_vertices =
2712 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2713 sel->gs_num_invocations =
2714 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2715 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2716 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2717 sel->gs_max_out_vertices;
2718
2719 sel->max_gs_stream = 0;
2720 for (i = 0; i < sel->so.num_outputs; i++)
2721 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2722 sel->so.output[i].stream);
2723
2724 sel->gs_input_verts_per_prim =
2725 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2726
2727 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2728 sel->tess_turns_off_ngg =
2729 (sscreen->info.family == CHIP_NAVI10 ||
2730 sscreen->info.family == CHIP_NAVI12 ||
2731 sscreen->info.family == CHIP_NAVI14) &&
2732 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2733 break;
2734
2735 case PIPE_SHADER_TESS_CTRL:
2736 /* Always reserve space for these. */
2737 sel->patch_outputs_written |=
2738 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2739 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2740 /* fall through */
2741 case PIPE_SHADER_VERTEX:
2742 case PIPE_SHADER_TESS_EVAL:
2743 for (i = 0; i < sel->info.num_outputs; i++) {
2744 unsigned name = sel->info.output_semantic_name[i];
2745 unsigned index = sel->info.output_semantic_index[i];
2746
2747 switch (name) {
2748 case TGSI_SEMANTIC_TESSINNER:
2749 case TGSI_SEMANTIC_TESSOUTER:
2750 case TGSI_SEMANTIC_PATCH:
2751 sel->patch_outputs_written |=
2752 1ull << si_shader_io_get_unique_index_patch(name, index);
2753 break;
2754
2755 case TGSI_SEMANTIC_GENERIC:
2756 /* don't process indices the function can't handle */
2757 if (index >= SI_MAX_IO_GENERIC)
2758 break;
2759 /* fall through */
2760 default:
2761 sel->outputs_written |=
2762 1ull << si_shader_io_get_unique_index(name, index, false);
2763 sel->outputs_written_before_ps |=
2764 1ull << si_shader_io_get_unique_index(name, index, true);
2765 break;
2766 case TGSI_SEMANTIC_EDGEFLAG:
2767 break;
2768 }
2769 }
2770 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2771 sel->lshs_vertex_stride = sel->esgs_itemsize;
2772
2773 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2774 * will start on a different bank. (except for the maximum 32*16).
2775 */
2776 if (sel->lshs_vertex_stride < 32*16)
2777 sel->lshs_vertex_stride += 4;
2778
2779 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2780 * conflicts, i.e. each vertex will start at a different bank.
2781 */
2782 if (sctx->chip_class >= GFX9)
2783 sel->esgs_itemsize += 4;
2784
2785 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2786
2787 /* Only for TES: */
2788 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2789 sel->rast_prim = PIPE_PRIM_POINTS;
2790 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2791 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2792 else
2793 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2794 break;
2795
2796 case PIPE_SHADER_FRAGMENT:
2797 for (i = 0; i < sel->info.num_inputs; i++) {
2798 unsigned name = sel->info.input_semantic_name[i];
2799 unsigned index = sel->info.input_semantic_index[i];
2800
2801 switch (name) {
2802 case TGSI_SEMANTIC_GENERIC:
2803 /* don't process indices the function can't handle */
2804 if (index >= SI_MAX_IO_GENERIC)
2805 break;
2806 /* fall through */
2807 default:
2808 sel->inputs_read |=
2809 1ull << si_shader_io_get_unique_index(name, index, true);
2810 break;
2811 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2812 break;
2813 }
2814 }
2815
2816 for (i = 0; i < 8; i++)
2817 if (sel->info.colors_written & (1 << i))
2818 sel->colors_written_4bit |= 0xf << (4 * i);
2819
2820 for (i = 0; i < sel->info.num_inputs; i++) {
2821 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2822 int index = sel->info.input_semantic_index[i];
2823 sel->color_attr_index[index] = i;
2824 }
2825 }
2826 break;
2827 default:;
2828 }
2829
2830 /* PA_CL_VS_OUT_CNTL */
2831 bool misc_vec_ena =
2832 sel->info.writes_psize || sel->pos_writes_edgeflag ||
2833 sel->info.writes_layer || sel->info.writes_viewport_index;
2834 sel->pa_cl_vs_out_cntl =
2835 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2836 S_02881C_USE_VTX_EDGE_FLAG(sel->pos_writes_edgeflag) |
2837 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2838 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2839 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2840 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2841 sel->clipdist_mask = sel->info.writes_clipvertex ?
2842 SIX_BITS : sel->info.clipdist_writemask;
2843 sel->culldist_mask = sel->info.culldist_writemask <<
2844 sel->info.num_written_clipdistance;
2845
2846 /* DB_SHADER_CONTROL */
2847 sel->db_shader_control =
2848 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2849 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2850 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2851 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2852
2853 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2854 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2855 sel->db_shader_control |=
2856 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2857 break;
2858 case TGSI_FS_DEPTH_LAYOUT_LESS:
2859 sel->db_shader_control |=
2860 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2861 break;
2862 }
2863
2864 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2865 *
2866 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2867 * --|-----------|------------|------------|--------------------|-------------------|-------------
2868 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2869 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2870 * 2 | false | true | n/a | LateZ | 1 | 0
2871 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2872 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2873 *
2874 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2875 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2876 *
2877 * Don't use ReZ without profiling !!!
2878 *
2879 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2880 * shaders.
2881 */
2882 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2883 /* Cases 3, 4. */
2884 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2885 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2886 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2887 } else if (sel->info.writes_memory) {
2888 /* Case 2. */
2889 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2890 S_02880C_EXEC_ON_HIER_FAIL(1);
2891 } else {
2892 /* Case 1. */
2893 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2894 }
2895
2896 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2897 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2898
2899 (void) mtx_init(&sel->mutex, mtx_plain);
2900
2901 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2902 &sel->compiler_ctx_state, sel,
2903 si_init_shader_selector_async);
2904 return sel;
2905 }
2906
2907 static void si_update_streamout_state(struct si_context *sctx)
2908 {
2909 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2910
2911 if (!shader_with_so)
2912 return;
2913
2914 sctx->streamout.enabled_stream_buffers_mask =
2915 shader_with_so->enabled_streamout_buffer_mask;
2916 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2917 }
2918
2919 static void si_update_clip_regs(struct si_context *sctx,
2920 struct si_shader_selector *old_hw_vs,
2921 struct si_shader *old_hw_vs_variant,
2922 struct si_shader_selector *next_hw_vs,
2923 struct si_shader *next_hw_vs_variant)
2924 {
2925 if (next_hw_vs &&
2926 (!old_hw_vs ||
2927 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2928 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2929 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2930 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2931 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2932 !old_hw_vs_variant ||
2933 !next_hw_vs_variant ||
2934 old_hw_vs_variant->key.opt.clip_disable !=
2935 next_hw_vs_variant->key.opt.clip_disable))
2936 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2937 }
2938
2939 static void si_update_common_shader_state(struct si_context *sctx)
2940 {
2941 sctx->uses_bindless_samplers =
2942 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2943 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2944 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2945 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2946 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2947 sctx->uses_bindless_images =
2948 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2949 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2950 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2951 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2952 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2953 sctx->do_update_shaders = true;
2954 }
2955
2956 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2957 {
2958 struct si_context *sctx = (struct si_context *)ctx;
2959 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2960 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2961 struct si_shader_selector *sel = state;
2962
2963 if (sctx->vs_shader.cso == sel)
2964 return;
2965
2966 sctx->vs_shader.cso = sel;
2967 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2968 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2969
2970 si_update_common_shader_state(sctx);
2971 si_update_vs_viewport_state(sctx);
2972 si_set_active_descriptors_for_shader(sctx, sel);
2973 si_update_streamout_state(sctx);
2974 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2975 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2976 }
2977
2978 static void si_update_tess_uses_prim_id(struct si_context *sctx)
2979 {
2980 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
2981 (sctx->tes_shader.cso &&
2982 sctx->tes_shader.cso->info.uses_primid) ||
2983 (sctx->tcs_shader.cso &&
2984 sctx->tcs_shader.cso->info.uses_primid) ||
2985 (sctx->gs_shader.cso &&
2986 sctx->gs_shader.cso->info.uses_primid) ||
2987 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
2988 sctx->ps_shader.cso->info.uses_primid);
2989 }
2990
2991 static bool si_update_ngg(struct si_context *sctx)
2992 {
2993 if (sctx->chip_class <= GFX9)
2994 return false;
2995
2996 bool new_ngg = true;
2997
2998 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
2999 sctx->gs_shader.cso->tess_turns_off_ngg)
3000 new_ngg = false;
3001
3002 if (new_ngg != sctx->ngg) {
3003 sctx->ngg = new_ngg;
3004 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3005 return true;
3006 }
3007 return false;
3008 }
3009
3010 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3011 {
3012 struct si_context *sctx = (struct si_context *)ctx;
3013 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3014 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3015 struct si_shader_selector *sel = state;
3016 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3017 bool ngg_changed;
3018
3019 if (sctx->gs_shader.cso == sel)
3020 return;
3021
3022 sctx->gs_shader.cso = sel;
3023 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3024 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3025
3026 si_update_common_shader_state(sctx);
3027 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3028
3029 ngg_changed = si_update_ngg(sctx);
3030 if (ngg_changed || enable_changed)
3031 si_shader_change_notify(sctx);
3032 if (enable_changed) {
3033 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3034 si_update_tess_uses_prim_id(sctx);
3035 }
3036 si_update_vs_viewport_state(sctx);
3037 si_set_active_descriptors_for_shader(sctx, sel);
3038 si_update_streamout_state(sctx);
3039 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3040 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3041 }
3042
3043 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3044 {
3045 struct si_context *sctx = (struct si_context *)ctx;
3046 struct si_shader_selector *sel = state;
3047 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3048
3049 if (sctx->tcs_shader.cso == sel)
3050 return;
3051
3052 sctx->tcs_shader.cso = sel;
3053 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3054 si_update_tess_uses_prim_id(sctx);
3055
3056 si_update_common_shader_state(sctx);
3057
3058 if (enable_changed)
3059 sctx->last_tcs = NULL; /* invalidate derived tess state */
3060
3061 si_set_active_descriptors_for_shader(sctx, sel);
3062 }
3063
3064 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3065 {
3066 struct si_context *sctx = (struct si_context *)ctx;
3067 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3068 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3069 struct si_shader_selector *sel = state;
3070 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3071
3072 if (sctx->tes_shader.cso == sel)
3073 return;
3074
3075 sctx->tes_shader.cso = sel;
3076 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3077 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3078 si_update_tess_uses_prim_id(sctx);
3079
3080 si_update_common_shader_state(sctx);
3081 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3082
3083 if (enable_changed) {
3084 si_update_ngg(sctx);
3085 si_shader_change_notify(sctx);
3086 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3087 }
3088 si_update_vs_viewport_state(sctx);
3089 si_set_active_descriptors_for_shader(sctx, sel);
3090 si_update_streamout_state(sctx);
3091 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3092 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3093 }
3094
3095 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3096 {
3097 struct si_context *sctx = (struct si_context *)ctx;
3098 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3099 struct si_shader_selector *sel = state;
3100
3101 /* skip if supplied shader is one already in use */
3102 if (old_sel == sel)
3103 return;
3104
3105 sctx->ps_shader.cso = sel;
3106 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3107
3108 si_update_common_shader_state(sctx);
3109 if (sel) {
3110 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3111 si_update_tess_uses_prim_id(sctx);
3112
3113 if (!old_sel ||
3114 old_sel->info.colors_written != sel->info.colors_written)
3115 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3116
3117 if (sctx->screen->has_out_of_order_rast &&
3118 (!old_sel ||
3119 old_sel->info.writes_memory != sel->info.writes_memory ||
3120 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3121 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3122 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3123 }
3124 si_set_active_descriptors_for_shader(sctx, sel);
3125 si_update_ps_colorbuf0_slot(sctx);
3126 }
3127
3128 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3129 {
3130 if (shader->is_optimized) {
3131 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3132 &shader->ready);
3133 }
3134
3135 util_queue_fence_destroy(&shader->ready);
3136
3137 if (shader->pm4) {
3138 /* If destroyed shaders were not unbound, the next compiled
3139 * shader variant could get the same pointer address and so
3140 * binding it to the same shader stage would be considered
3141 * a no-op, causing random behavior.
3142 */
3143 switch (shader->selector->type) {
3144 case PIPE_SHADER_VERTEX:
3145 if (shader->key.as_ls) {
3146 assert(sctx->chip_class <= GFX8);
3147 si_pm4_delete_state(sctx, ls, shader->pm4);
3148 } else if (shader->key.as_es) {
3149 assert(sctx->chip_class <= GFX8);
3150 si_pm4_delete_state(sctx, es, shader->pm4);
3151 } else if (shader->key.as_ngg) {
3152 si_pm4_delete_state(sctx, gs, shader->pm4);
3153 } else {
3154 si_pm4_delete_state(sctx, vs, shader->pm4);
3155 }
3156 break;
3157 case PIPE_SHADER_TESS_CTRL:
3158 si_pm4_delete_state(sctx, hs, shader->pm4);
3159 break;
3160 case PIPE_SHADER_TESS_EVAL:
3161 if (shader->key.as_es) {
3162 assert(sctx->chip_class <= GFX8);
3163 si_pm4_delete_state(sctx, es, shader->pm4);
3164 } else if (shader->key.as_ngg) {
3165 si_pm4_delete_state(sctx, gs, shader->pm4);
3166 } else {
3167 si_pm4_delete_state(sctx, vs, shader->pm4);
3168 }
3169 break;
3170 case PIPE_SHADER_GEOMETRY:
3171 if (shader->is_gs_copy_shader)
3172 si_pm4_delete_state(sctx, vs, shader->pm4);
3173 else
3174 si_pm4_delete_state(sctx, gs, shader->pm4);
3175 break;
3176 case PIPE_SHADER_FRAGMENT:
3177 si_pm4_delete_state(sctx, ps, shader->pm4);
3178 break;
3179 default:;
3180 }
3181 }
3182
3183 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3184 si_shader_destroy(shader);
3185 free(shader);
3186 }
3187
3188 void si_destroy_shader_selector(struct si_context *sctx,
3189 struct si_shader_selector *sel)
3190 {
3191 struct si_shader *p = sel->first_variant, *c;
3192 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3193 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3194 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3195 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3196 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3197 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3198 };
3199
3200 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3201
3202 if (current_shader[sel->type]->cso == sel) {
3203 current_shader[sel->type]->cso = NULL;
3204 current_shader[sel->type]->current = NULL;
3205 }
3206
3207 while (p) {
3208 c = p->next_variant;
3209 si_delete_shader(sctx, p);
3210 p = c;
3211 }
3212
3213 if (sel->main_shader_part)
3214 si_delete_shader(sctx, sel->main_shader_part);
3215 if (sel->main_shader_part_ls)
3216 si_delete_shader(sctx, sel->main_shader_part_ls);
3217 if (sel->main_shader_part_es)
3218 si_delete_shader(sctx, sel->main_shader_part_es);
3219 if (sel->main_shader_part_ngg)
3220 si_delete_shader(sctx, sel->main_shader_part_ngg);
3221 if (sel->gs_copy_shader)
3222 si_delete_shader(sctx, sel->gs_copy_shader);
3223
3224 util_queue_fence_destroy(&sel->ready);
3225 mtx_destroy(&sel->mutex);
3226 free(sel->tokens);
3227 ralloc_free(sel->nir);
3228 free(sel);
3229 }
3230
3231 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3232 {
3233 struct si_context *sctx = (struct si_context *)ctx;
3234 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3235
3236 si_shader_selector_reference(sctx, &sel, NULL);
3237 }
3238
3239 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3240 struct si_shader *vs, unsigned name,
3241 unsigned index, unsigned interpolate)
3242 {
3243 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3244 unsigned j, offset, ps_input_cntl = 0;
3245
3246 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3247 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3248 name == TGSI_SEMANTIC_PRIMID)
3249 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3250
3251 if (name == TGSI_SEMANTIC_PCOORD ||
3252 (name == TGSI_SEMANTIC_TEXCOORD &&
3253 sctx->sprite_coord_enable & (1 << index))) {
3254 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3255 }
3256
3257 for (j = 0; j < vsinfo->num_outputs; j++) {
3258 if (name == vsinfo->output_semantic_name[j] &&
3259 index == vsinfo->output_semantic_index[j]) {
3260 offset = vs->info.vs_output_param_offset[j];
3261
3262 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3263 /* The input is loaded from parameter memory. */
3264 ps_input_cntl |= S_028644_OFFSET(offset);
3265 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3266 if (offset == AC_EXP_PARAM_UNDEFINED) {
3267 /* This can happen with depth-only rendering. */
3268 offset = 0;
3269 } else {
3270 /* The input is a DEFAULT_VAL constant. */
3271 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3272 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3273 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3274 }
3275
3276 ps_input_cntl = S_028644_OFFSET(0x20) |
3277 S_028644_DEFAULT_VAL(offset);
3278 }
3279 break;
3280 }
3281 }
3282
3283 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3284 /* PrimID is written after the last output when HW VS is used. */
3285 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3286 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3287 /* No corresponding output found, load defaults into input.
3288 * Don't set any other bits.
3289 * (FLAT_SHADE=1 completely changes behavior) */
3290 ps_input_cntl = S_028644_OFFSET(0x20);
3291 /* D3D 9 behaviour. GL is undefined */
3292 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3293 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3294 }
3295 return ps_input_cntl;
3296 }
3297
3298 static void si_emit_spi_map(struct si_context *sctx)
3299 {
3300 struct si_shader *ps = sctx->ps_shader.current;
3301 struct si_shader *vs = si_get_vs_state(sctx);
3302 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3303 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3304 unsigned spi_ps_input_cntl[32];
3305
3306 if (!ps || !ps->selector->info.num_inputs)
3307 return;
3308
3309 num_interp = si_get_ps_num_interp(ps);
3310 assert(num_interp > 0);
3311
3312 for (i = 0; i < psinfo->num_inputs; i++) {
3313 unsigned name = psinfo->input_semantic_name[i];
3314 unsigned index = psinfo->input_semantic_index[i];
3315 unsigned interpolate = psinfo->input_interpolate[i];
3316
3317 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3318 index, interpolate);
3319
3320 if (name == TGSI_SEMANTIC_COLOR) {
3321 assert(index < ARRAY_SIZE(bcol_interp));
3322 bcol_interp[index] = interpolate;
3323 }
3324 }
3325
3326 if (ps->key.part.ps.prolog.color_two_side) {
3327 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3328
3329 for (i = 0; i < 2; i++) {
3330 if (!(psinfo->colors_read & (0xf << (i * 4))))
3331 continue;
3332
3333 spi_ps_input_cntl[num_written++] =
3334 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3335
3336 }
3337 }
3338 assert(num_interp == num_written);
3339
3340 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3341 /* Dota 2: Only ~16% of SPI map updates set different values. */
3342 /* Talos: Only ~9% of SPI map updates set different values. */
3343 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3344 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3345 spi_ps_input_cntl,
3346 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3347
3348 if (initial_cdw != sctx->gfx_cs->current.cdw)
3349 sctx->context_roll = true;
3350 }
3351
3352 /**
3353 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3354 */
3355 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3356 {
3357 if (sctx->init_config_has_vgt_flush)
3358 return;
3359
3360 /* Done by Vulkan before VGT_FLUSH. */
3361 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3362 si_pm4_cmd_add(sctx->init_config,
3363 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3364 si_pm4_cmd_end(sctx->init_config, false);
3365
3366 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3367 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3368 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3369 si_pm4_cmd_end(sctx->init_config, false);
3370 sctx->init_config_has_vgt_flush = true;
3371 }
3372
3373 /* Initialize state related to ESGS / GSVS ring buffers */
3374 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3375 {
3376 struct si_shader_selector *es =
3377 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3378 struct si_shader_selector *gs = sctx->gs_shader.cso;
3379 struct si_pm4_state *pm4;
3380
3381 /* Chip constants. */
3382 unsigned num_se = sctx->screen->info.max_se;
3383 unsigned wave_size = 64;
3384 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3385 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3386 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3387 */
3388 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3389 unsigned alignment = 256 * num_se;
3390 /* The maximum size is 63.999 MB per SE. */
3391 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3392
3393 /* Calculate the minimum size. */
3394 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3395 wave_size, alignment);
3396
3397 /* These are recommended sizes, not minimum sizes. */
3398 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3399 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3400 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3401 gs->max_gsvs_emit_size;
3402
3403 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3404 esgs_ring_size = align(esgs_ring_size, alignment);
3405 gsvs_ring_size = align(gsvs_ring_size, alignment);
3406
3407 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3408 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3409
3410 /* Some rings don't have to be allocated if shaders don't use them.
3411 * (e.g. no varyings between ES and GS or GS and VS)
3412 *
3413 * GFX9 doesn't have the ESGS ring.
3414 */
3415 bool update_esgs = sctx->chip_class <= GFX8 &&
3416 esgs_ring_size &&
3417 (!sctx->esgs_ring ||
3418 sctx->esgs_ring->width0 < esgs_ring_size);
3419 bool update_gsvs = gsvs_ring_size &&
3420 (!sctx->gsvs_ring ||
3421 sctx->gsvs_ring->width0 < gsvs_ring_size);
3422
3423 if (!update_esgs && !update_gsvs)
3424 return true;
3425
3426 if (update_esgs) {
3427 pipe_resource_reference(&sctx->esgs_ring, NULL);
3428 sctx->esgs_ring =
3429 pipe_aligned_buffer_create(sctx->b.screen,
3430 SI_RESOURCE_FLAG_UNMAPPABLE,
3431 PIPE_USAGE_DEFAULT,
3432 esgs_ring_size, alignment);
3433 if (!sctx->esgs_ring)
3434 return false;
3435 }
3436
3437 if (update_gsvs) {
3438 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3439 sctx->gsvs_ring =
3440 pipe_aligned_buffer_create(sctx->b.screen,
3441 SI_RESOURCE_FLAG_UNMAPPABLE,
3442 PIPE_USAGE_DEFAULT,
3443 gsvs_ring_size, alignment);
3444 if (!sctx->gsvs_ring)
3445 return false;
3446 }
3447
3448 /* Create the "init_config_gs_rings" state. */
3449 pm4 = CALLOC_STRUCT(si_pm4_state);
3450 if (!pm4)
3451 return false;
3452
3453 if (sctx->chip_class >= GFX7) {
3454 if (sctx->esgs_ring) {
3455 assert(sctx->chip_class <= GFX8);
3456 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3457 sctx->esgs_ring->width0 / 256);
3458 }
3459 if (sctx->gsvs_ring)
3460 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3461 sctx->gsvs_ring->width0 / 256);
3462 } else {
3463 if (sctx->esgs_ring)
3464 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3465 sctx->esgs_ring->width0 / 256);
3466 if (sctx->gsvs_ring)
3467 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3468 sctx->gsvs_ring->width0 / 256);
3469 }
3470
3471 /* Set the state. */
3472 if (sctx->init_config_gs_rings)
3473 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3474 sctx->init_config_gs_rings = pm4;
3475
3476 if (!sctx->init_config_has_vgt_flush) {
3477 si_init_config_add_vgt_flush(sctx);
3478 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3479 }
3480
3481 /* Flush the context to re-emit both init_config states. */
3482 sctx->initial_gfx_cs_size = 0; /* force flush */
3483 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3484
3485 /* Set ring bindings. */
3486 if (sctx->esgs_ring) {
3487 assert(sctx->chip_class <= GFX8);
3488 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3489 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3490 true, true, 4, 64, 0);
3491 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3492 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3493 false, false, 0, 0, 0);
3494 }
3495 if (sctx->gsvs_ring) {
3496 si_set_ring_buffer(sctx, SI_RING_GSVS,
3497 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3498 false, false, 0, 0, 0);
3499 }
3500
3501 return true;
3502 }
3503
3504 static void si_shader_lock(struct si_shader *shader)
3505 {
3506 mtx_lock(&shader->selector->mutex);
3507 if (shader->previous_stage_sel) {
3508 assert(shader->previous_stage_sel != shader->selector);
3509 mtx_lock(&shader->previous_stage_sel->mutex);
3510 }
3511 }
3512
3513 static void si_shader_unlock(struct si_shader *shader)
3514 {
3515 if (shader->previous_stage_sel)
3516 mtx_unlock(&shader->previous_stage_sel->mutex);
3517 mtx_unlock(&shader->selector->mutex);
3518 }
3519
3520 /**
3521 * @returns 1 if \p sel has been updated to use a new scratch buffer
3522 * 0 if not
3523 * < 0 if there was a failure
3524 */
3525 static int si_update_scratch_buffer(struct si_context *sctx,
3526 struct si_shader *shader)
3527 {
3528 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3529
3530 if (!shader)
3531 return 0;
3532
3533 /* This shader doesn't need a scratch buffer */
3534 if (shader->config.scratch_bytes_per_wave == 0)
3535 return 0;
3536
3537 /* Prevent race conditions when updating:
3538 * - si_shader::scratch_bo
3539 * - si_shader::binary::code
3540 * - si_shader::previous_stage::binary::code.
3541 */
3542 si_shader_lock(shader);
3543
3544 /* This shader is already configured to use the current
3545 * scratch buffer. */
3546 if (shader->scratch_bo == sctx->scratch_buffer) {
3547 si_shader_unlock(shader);
3548 return 0;
3549 }
3550
3551 assert(sctx->scratch_buffer);
3552
3553 /* Replace the shader bo with a new bo that has the relocs applied. */
3554 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3555 si_shader_unlock(shader);
3556 return -1;
3557 }
3558
3559 /* Update the shader state to use the new shader bo. */
3560 si_shader_init_pm4_state(sctx->screen, shader);
3561
3562 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3563
3564 si_shader_unlock(shader);
3565 return 1;
3566 }
3567
3568 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3569 {
3570 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3571 }
3572
3573 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3574 {
3575 return shader ? shader->config.scratch_bytes_per_wave : 0;
3576 }
3577
3578 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3579 {
3580 if (!sctx->tes_shader.cso)
3581 return NULL; /* tessellation disabled */
3582
3583 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3584 sctx->fixed_func_tcs_shader.current;
3585 }
3586
3587 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3588 {
3589 unsigned bytes = 0;
3590
3591 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3592 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3593 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3594 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3595
3596 if (sctx->tes_shader.cso) {
3597 struct si_shader *tcs = si_get_tcs_current(sctx);
3598
3599 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3600 }
3601 return bytes;
3602 }
3603
3604 static bool si_update_scratch_relocs(struct si_context *sctx)
3605 {
3606 struct si_shader *tcs = si_get_tcs_current(sctx);
3607 int r;
3608
3609 /* Update the shaders, so that they are using the latest scratch.
3610 * The scratch buffer may have been changed since these shaders were
3611 * last used, so we still need to try to update them, even if they
3612 * require scratch buffers smaller than the current size.
3613 */
3614 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3615 if (r < 0)
3616 return false;
3617 if (r == 1)
3618 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3619
3620 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3621 if (r < 0)
3622 return false;
3623 if (r == 1)
3624 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3625
3626 r = si_update_scratch_buffer(sctx, tcs);
3627 if (r < 0)
3628 return false;
3629 if (r == 1)
3630 si_pm4_bind_state(sctx, hs, tcs->pm4);
3631
3632 /* VS can be bound as LS, ES, or VS. */
3633 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3634 if (r < 0)
3635 return false;
3636 if (r == 1) {
3637 if (sctx->vs_shader.current->key.as_ls)
3638 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3639 else if (sctx->vs_shader.current->key.as_es)
3640 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3641 else if (sctx->vs_shader.current->key.as_ngg)
3642 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3643 else
3644 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3645 }
3646
3647 /* TES can be bound as ES or VS. */
3648 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3649 if (r < 0)
3650 return false;
3651 if (r == 1) {
3652 if (sctx->tes_shader.current->key.as_es)
3653 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3654 else if (sctx->tes_shader.current->key.as_ngg)
3655 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3656 else
3657 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3658 }
3659
3660 return true;
3661 }
3662
3663 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3664 {
3665 unsigned current_scratch_buffer_size =
3666 si_get_current_scratch_buffer_size(sctx);
3667 unsigned scratch_bytes_per_wave =
3668 si_get_max_scratch_bytes_per_wave(sctx);
3669 unsigned scratch_needed_size = scratch_bytes_per_wave *
3670 sctx->scratch_waves;
3671 unsigned spi_tmpring_size;
3672
3673 if (scratch_needed_size > 0) {
3674 if (scratch_needed_size > current_scratch_buffer_size) {
3675 /* Create a bigger scratch buffer */
3676 si_resource_reference(&sctx->scratch_buffer, NULL);
3677
3678 sctx->scratch_buffer =
3679 si_aligned_buffer_create(&sctx->screen->b,
3680 SI_RESOURCE_FLAG_UNMAPPABLE,
3681 PIPE_USAGE_DEFAULT,
3682 scratch_needed_size, 256);
3683 if (!sctx->scratch_buffer)
3684 return false;
3685
3686 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3687 si_context_add_resource_size(sctx,
3688 &sctx->scratch_buffer->b.b);
3689 }
3690
3691 if (!si_update_scratch_relocs(sctx))
3692 return false;
3693 }
3694
3695 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3696 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3697 "scratch size should already be aligned correctly.");
3698
3699 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3700 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3701 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3702 sctx->spi_tmpring_size = spi_tmpring_size;
3703 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3704 }
3705 return true;
3706 }
3707
3708 static void si_init_tess_factor_ring(struct si_context *sctx)
3709 {
3710 assert(!sctx->tess_rings);
3711
3712 /* The address must be aligned to 2^19, because the shader only
3713 * receives the high 13 bits.
3714 */
3715 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3716 SI_RESOURCE_FLAG_32BIT,
3717 PIPE_USAGE_DEFAULT,
3718 sctx->screen->tess_offchip_ring_size +
3719 sctx->screen->tess_factor_ring_size,
3720 1 << 19);
3721 if (!sctx->tess_rings)
3722 return;
3723
3724 si_init_config_add_vgt_flush(sctx);
3725
3726 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3727 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3728
3729 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3730 sctx->screen->tess_offchip_ring_size;
3731
3732 /* Append these registers to the init config state. */
3733 if (sctx->chip_class >= GFX7) {
3734 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3735 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3736 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3737 factor_va >> 8);
3738 if (sctx->chip_class >= GFX10)
3739 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3740 S_030984_BASE_HI(factor_va >> 40));
3741 else if (sctx->chip_class == GFX9)
3742 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3743 S_030944_BASE_HI(factor_va >> 40));
3744 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3745 sctx->screen->vgt_hs_offchip_param);
3746 } else {
3747 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3748 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3749 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3750 factor_va >> 8);
3751 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3752 sctx->screen->vgt_hs_offchip_param);
3753 }
3754
3755 /* Flush the context to re-emit the init_config state.
3756 * This is done only once in a lifetime of a context.
3757 */
3758 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3759 sctx->initial_gfx_cs_size = 0; /* force flush */
3760 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3761 }
3762
3763 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3764 union si_vgt_stages_key key)
3765 {
3766 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3767 uint32_t stages = 0;
3768
3769 if (key.u.tess) {
3770 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3771 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3772
3773 if (key.u.gs)
3774 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3775 S_028B54_GS_EN(1);
3776 else if (key.u.ngg)
3777 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3778 else
3779 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3780 } else if (key.u.gs) {
3781 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3782 S_028B54_GS_EN(1);
3783 } else if (key.u.ngg) {
3784 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3785 }
3786
3787 if (key.u.ngg) {
3788 stages |= S_028B54_PRIMGEN_EN(1);
3789 if (key.u.streamout)
3790 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3791 } else if (key.u.gs)
3792 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3793
3794 if (screen->info.chip_class >= GFX9)
3795 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3796
3797 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3798 stages |= S_028B54_HS_W32_EN(1) |
3799 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3800 S_028B54_VS_W32_EN(1);
3801 }
3802
3803 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3804 return pm4;
3805 }
3806
3807 static void si_update_vgt_shader_config(struct si_context *sctx,
3808 union si_vgt_stages_key key)
3809 {
3810 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3811
3812 if (unlikely(!*pm4))
3813 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3814 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3815 }
3816
3817 bool si_update_shaders(struct si_context *sctx)
3818 {
3819 struct pipe_context *ctx = (struct pipe_context*)sctx;
3820 struct si_compiler_ctx_state compiler_state;
3821 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3822 struct si_shader *old_vs = si_get_vs_state(sctx);
3823 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3824 struct si_shader *old_ps = sctx->ps_shader.current;
3825 union si_vgt_stages_key key;
3826 unsigned old_spi_shader_col_format =
3827 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3828 int r;
3829
3830 compiler_state.compiler = &sctx->compiler;
3831 compiler_state.debug = sctx->debug;
3832 compiler_state.is_debug_context = sctx->is_debug;
3833
3834 key.index = 0;
3835
3836 if (sctx->tes_shader.cso)
3837 key.u.tess = 1;
3838 if (sctx->gs_shader.cso)
3839 key.u.gs = 1;
3840
3841 if (sctx->chip_class >= GFX10) {
3842 key.u.ngg = sctx->ngg;
3843
3844 if (sctx->gs_shader.cso)
3845 key.u.streamout = !!sctx->gs_shader.cso->so.num_outputs;
3846 else if (sctx->tes_shader.cso)
3847 key.u.streamout = !!sctx->tes_shader.cso->so.num_outputs;
3848 else
3849 key.u.streamout = !!sctx->vs_shader.cso->so.num_outputs;
3850 }
3851
3852 /* Update TCS and TES. */
3853 if (sctx->tes_shader.cso) {
3854 if (!sctx->tess_rings) {
3855 si_init_tess_factor_ring(sctx);
3856 if (!sctx->tess_rings)
3857 return false;
3858 }
3859
3860 if (sctx->tcs_shader.cso) {
3861 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3862 &compiler_state);
3863 if (r)
3864 return false;
3865 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3866 } else {
3867 if (!sctx->fixed_func_tcs_shader.cso) {
3868 sctx->fixed_func_tcs_shader.cso =
3869 si_create_fixed_func_tcs(sctx);
3870 if (!sctx->fixed_func_tcs_shader.cso)
3871 return false;
3872 }
3873
3874 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3875 key, &compiler_state);
3876 if (r)
3877 return false;
3878 si_pm4_bind_state(sctx, hs,
3879 sctx->fixed_func_tcs_shader.current->pm4);
3880 }
3881
3882 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3883 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3884 if (r)
3885 return false;
3886
3887 if (sctx->gs_shader.cso) {
3888 /* TES as ES */
3889 assert(sctx->chip_class <= GFX8);
3890 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3891 } else if (key.u.ngg) {
3892 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3893 } else {
3894 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3895 }
3896 }
3897 } else {
3898 if (sctx->chip_class <= GFX8)
3899 si_pm4_bind_state(sctx, ls, NULL);
3900 si_pm4_bind_state(sctx, hs, NULL);
3901 }
3902
3903 /* Update GS. */
3904 if (sctx->gs_shader.cso) {
3905 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3906 if (r)
3907 return false;
3908 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3909 if (!key.u.ngg) {
3910 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3911
3912 if (!si_update_gs_ring_buffers(sctx))
3913 return false;
3914 } else {
3915 si_pm4_bind_state(sctx, vs, NULL);
3916 }
3917 } else {
3918 if (!key.u.ngg) {
3919 si_pm4_bind_state(sctx, gs, NULL);
3920 if (sctx->chip_class <= GFX8)
3921 si_pm4_bind_state(sctx, es, NULL);
3922 }
3923 }
3924
3925 /* Update VS. */
3926 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3927 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3928 if (r)
3929 return false;
3930
3931 if (!key.u.tess && !key.u.gs) {
3932 if (key.u.ngg) {
3933 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3934 si_pm4_bind_state(sctx, vs, NULL);
3935 } else {
3936 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3937 }
3938 } else if (sctx->tes_shader.cso) {
3939 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3940 } else {
3941 assert(sctx->gs_shader.cso);
3942 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3943 }
3944 }
3945
3946 si_update_vgt_shader_config(sctx, key);
3947
3948 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3949 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3950
3951 if (sctx->ps_shader.cso) {
3952 unsigned db_shader_control;
3953
3954 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3955 if (r)
3956 return false;
3957 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3958
3959 db_shader_control =
3960 sctx->ps_shader.cso->db_shader_control |
3961 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3962
3963 if (si_pm4_state_changed(sctx, ps) ||
3964 si_pm4_state_changed(sctx, vs) ||
3965 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3966 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3967 sctx->flatshade != rs->flatshade) {
3968 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3969 sctx->flatshade = rs->flatshade;
3970 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3971 }
3972
3973 if (sctx->screen->rbplus_allowed &&
3974 si_pm4_state_changed(sctx, ps) &&
3975 (!old_ps ||
3976 old_spi_shader_col_format !=
3977 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3978 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3979
3980 if (sctx->ps_db_shader_control != db_shader_control) {
3981 sctx->ps_db_shader_control = db_shader_control;
3982 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3983 if (sctx->screen->dpbb_allowed)
3984 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
3985 }
3986
3987 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
3988 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
3989 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3990
3991 if (sctx->chip_class == GFX6)
3992 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3993
3994 if (sctx->framebuffer.nr_samples <= 1)
3995 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
3996 }
3997 }
3998
3999 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4000 si_pm4_state_enabled_and_changed(sctx, hs) ||
4001 si_pm4_state_enabled_and_changed(sctx, es) ||
4002 si_pm4_state_enabled_and_changed(sctx, gs) ||
4003 si_pm4_state_enabled_and_changed(sctx, vs) ||
4004 si_pm4_state_enabled_and_changed(sctx, ps)) {
4005 if (!si_update_spi_tmpring_size(sctx))
4006 return false;
4007 }
4008
4009 if (sctx->chip_class >= GFX7) {
4010 if (si_pm4_state_enabled_and_changed(sctx, ls))
4011 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4012 else if (!sctx->queued.named.ls)
4013 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4014
4015 if (si_pm4_state_enabled_and_changed(sctx, hs))
4016 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4017 else if (!sctx->queued.named.hs)
4018 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4019
4020 if (si_pm4_state_enabled_and_changed(sctx, es))
4021 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4022 else if (!sctx->queued.named.es)
4023 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4024
4025 if (si_pm4_state_enabled_and_changed(sctx, gs))
4026 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4027 else if (!sctx->queued.named.gs)
4028 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4029
4030 if (si_pm4_state_enabled_and_changed(sctx, vs))
4031 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4032 else if (!sctx->queued.named.vs)
4033 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4034
4035 if (si_pm4_state_enabled_and_changed(sctx, ps))
4036 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4037 else if (!sctx->queued.named.ps)
4038 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4039 }
4040
4041 sctx->do_update_shaders = false;
4042 return true;
4043 }
4044
4045 static void si_emit_scratch_state(struct si_context *sctx)
4046 {
4047 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4048
4049 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4050 sctx->spi_tmpring_size);
4051
4052 if (sctx->scratch_buffer) {
4053 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4054 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4055 RADEON_PRIO_SCRATCH_BUFFER);
4056 }
4057 }
4058
4059 void si_init_shader_functions(struct si_context *sctx)
4060 {
4061 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4062 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4063
4064 sctx->b.create_vs_state = si_create_shader_selector;
4065 sctx->b.create_tcs_state = si_create_shader_selector;
4066 sctx->b.create_tes_state = si_create_shader_selector;
4067 sctx->b.create_gs_state = si_create_shader_selector;
4068 sctx->b.create_fs_state = si_create_shader_selector;
4069
4070 sctx->b.bind_vs_state = si_bind_vs_shader;
4071 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4072 sctx->b.bind_tes_state = si_bind_tes_shader;
4073 sctx->b.bind_gs_state = si_bind_gs_shader;
4074 sctx->b.bind_fs_state = si_bind_ps_shader;
4075
4076 sctx->b.delete_vs_state = si_delete_shader_selector;
4077 sctx->b.delete_tcs_state = si_delete_shader_selector;
4078 sctx->b.delete_tes_state = si_delete_shader_selector;
4079 sctx->b.delete_gs_state = si_delete_shader_selector;
4080 sctx->b.delete_fs_state = si_delete_shader_selector;
4081 }