2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
48 void *si_get_ir_binary(struct si_shader_selector
*sel
)
55 ir_binary
= sel
->tokens
;
56 ir_size
= tgsi_num_tokens(sel
->tokens
) *
57 sizeof(struct tgsi_token
);
62 nir_serialize(&blob
, sel
->nir
);
63 ir_binary
= blob
.data
;
67 unsigned size
= 4 + ir_size
+ sizeof(sel
->so
);
68 char *result
= (char*)MALLOC(size
);
72 *((uint32_t*)result
) = size
;
73 memcpy(result
+ 4, ir_binary
, ir_size
);
74 memcpy(result
+ 4 + ir_size
, &sel
->so
, sizeof(sel
->so
));
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr
, const void *data
, unsigned size
)
85 /* data may be NULL if size == 0 */
87 memcpy(ptr
, data
, size
);
88 ptr
+= DIV_ROUND_UP(size
, 4);
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr
, void *data
, unsigned size
)
95 memcpy(data
, ptr
, size
);
96 ptr
+= DIV_ROUND_UP(size
, 4);
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
104 static uint32_t *write_chunk(uint32_t *ptr
, const void *data
, unsigned size
)
107 return write_data(ptr
, data
, size
);
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
114 static uint32_t *read_chunk(uint32_t *ptr
, void **data
, unsigned *size
)
117 assert(*data
== NULL
);
120 *data
= malloc(*size
);
121 return read_data(ptr
, *data
, *size
);
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
128 static void *si_get_shader_binary(struct si_shader
*shader
)
130 /* There is always a size of data followed by the data itself. */
131 unsigned llvm_ir_size
= shader
->binary
.llvm_ir_string
?
132 strlen(shader
->binary
.llvm_ir_string
) + 1 : 0;
134 /* Refuse to allocate overly large buffers and guard against integer
136 if (shader
->binary
.elf_size
> UINT_MAX
/ 4 ||
137 llvm_ir_size
> UINT_MAX
/ 4)
142 4 + /* CRC32 of the data below */
143 align(sizeof(shader
->config
), 4) +
144 align(sizeof(shader
->info
), 4) +
145 4 + align(shader
->binary
.elf_size
, 4) +
146 4 + align(llvm_ir_size
, 4);
147 void *buffer
= CALLOC(1, size
);
148 uint32_t *ptr
= (uint32_t*)buffer
;
154 ptr
++; /* CRC32 is calculated at the end. */
156 ptr
= write_data(ptr
, &shader
->config
, sizeof(shader
->config
));
157 ptr
= write_data(ptr
, &shader
->info
, sizeof(shader
->info
));
158 ptr
= write_chunk(ptr
, shader
->binary
.elf_buffer
, shader
->binary
.elf_size
);
159 ptr
= write_chunk(ptr
, shader
->binary
.llvm_ir_string
, llvm_ir_size
);
160 assert((char *)ptr
- (char *)buffer
== size
);
163 ptr
= (uint32_t*)buffer
;
165 *ptr
= util_hash_crc32(ptr
+ 1, size
- 8);
170 static bool si_load_shader_binary(struct si_shader
*shader
, void *binary
)
172 uint32_t *ptr
= (uint32_t*)binary
;
173 uint32_t size
= *ptr
++;
174 uint32_t crc32
= *ptr
++;
178 if (util_hash_crc32(ptr
, size
- 8) != crc32
) {
179 fprintf(stderr
, "radeonsi: binary shader has invalid CRC32\n");
183 ptr
= read_data(ptr
, &shader
->config
, sizeof(shader
->config
));
184 ptr
= read_data(ptr
, &shader
->info
, sizeof(shader
->info
));
185 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.elf_buffer
,
187 shader
->binary
.elf_size
= elf_size
;
188 ptr
= read_chunk(ptr
, (void**)&shader
->binary
.llvm_ir_string
, &chunk_size
);
194 * Insert a shader into the cache. It's assumed the shader is not in the cache.
195 * Use si_shader_cache_load_shader before calling this.
197 * Returns false on failure, in which case the ir_binary should be freed.
199 bool si_shader_cache_insert_shader(struct si_screen
*sscreen
, void *ir_binary
,
200 struct si_shader
*shader
,
201 bool insert_into_disk_cache
)
204 struct hash_entry
*entry
;
205 uint8_t key
[CACHE_KEY_SIZE
];
207 entry
= _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
209 return false; /* already added */
211 hw_binary
= si_get_shader_binary(shader
);
215 if (_mesa_hash_table_insert(sscreen
->shader_cache
, ir_binary
,
216 hw_binary
) == NULL
) {
221 if (sscreen
->disk_shader_cache
&& insert_into_disk_cache
) {
222 disk_cache_compute_key(sscreen
->disk_shader_cache
, ir_binary
,
223 *((uint32_t *)ir_binary
), key
);
224 disk_cache_put(sscreen
->disk_shader_cache
, key
, hw_binary
,
225 *((uint32_t *) hw_binary
), NULL
);
231 bool si_shader_cache_load_shader(struct si_screen
*sscreen
, void *ir_binary
,
232 struct si_shader
*shader
)
234 struct hash_entry
*entry
=
235 _mesa_hash_table_search(sscreen
->shader_cache
, ir_binary
);
237 if (sscreen
->disk_shader_cache
) {
238 unsigned char sha1
[CACHE_KEY_SIZE
];
239 size_t tg_size
= *((uint32_t *) ir_binary
);
241 disk_cache_compute_key(sscreen
->disk_shader_cache
,
242 ir_binary
, tg_size
, sha1
);
246 disk_cache_get(sscreen
->disk_shader_cache
,
251 if (binary_size
< sizeof(uint32_t) ||
252 *((uint32_t*)buffer
) != binary_size
) {
253 /* Something has gone wrong discard the item
254 * from the cache and rebuild/link from
257 assert(!"Invalid radeonsi shader disk cache "
260 disk_cache_remove(sscreen
->disk_shader_cache
,
267 if (!si_load_shader_binary(shader
, buffer
)) {
273 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
,
280 if (si_load_shader_binary(shader
, entry
->data
))
285 p_atomic_inc(&sscreen
->num_shader_cache_hits
);
289 static uint32_t si_shader_cache_key_hash(const void *key
)
291 /* The first dword is the key size. */
292 return util_hash_crc32(key
, *(uint32_t*)key
);
295 static bool si_shader_cache_key_equals(const void *a
, const void *b
)
297 uint32_t *keya
= (uint32_t*)a
;
298 uint32_t *keyb
= (uint32_t*)b
;
300 /* The first dword is the key size. */
304 return memcmp(keya
, keyb
, *keya
) == 0;
307 static void si_destroy_shader_cache_entry(struct hash_entry
*entry
)
309 FREE((void*)entry
->key
);
313 bool si_init_shader_cache(struct si_screen
*sscreen
)
315 (void) mtx_init(&sscreen
->shader_cache_mutex
, mtx_plain
);
316 sscreen
->shader_cache
=
317 _mesa_hash_table_create(NULL
,
318 si_shader_cache_key_hash
,
319 si_shader_cache_key_equals
);
321 return sscreen
->shader_cache
!= NULL
;
324 void si_destroy_shader_cache(struct si_screen
*sscreen
)
326 if (sscreen
->shader_cache
)
327 _mesa_hash_table_destroy(sscreen
->shader_cache
,
328 si_destroy_shader_cache_entry
);
329 mtx_destroy(&sscreen
->shader_cache_mutex
);
334 static void si_set_tesseval_regs(struct si_screen
*sscreen
,
335 const struct si_shader_selector
*tes
,
336 struct si_pm4_state
*pm4
)
338 const struct tgsi_shader_info
*info
= &tes
->info
;
339 unsigned tes_prim_mode
= info
->properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
340 unsigned tes_spacing
= info
->properties
[TGSI_PROPERTY_TES_SPACING
];
341 bool tes_vertex_order_cw
= info
->properties
[TGSI_PROPERTY_TES_VERTEX_ORDER_CW
];
342 bool tes_point_mode
= info
->properties
[TGSI_PROPERTY_TES_POINT_MODE
];
343 unsigned type
, partitioning
, topology
, distribution_mode
;
345 switch (tes_prim_mode
) {
346 case PIPE_PRIM_LINES
:
347 type
= V_028B6C_TESS_ISOLINE
;
349 case PIPE_PRIM_TRIANGLES
:
350 type
= V_028B6C_TESS_TRIANGLE
;
352 case PIPE_PRIM_QUADS
:
353 type
= V_028B6C_TESS_QUAD
;
360 switch (tes_spacing
) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD
:
362 partitioning
= V_028B6C_PART_FRAC_ODD
;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN
:
365 partitioning
= V_028B6C_PART_FRAC_EVEN
;
367 case PIPE_TESS_SPACING_EQUAL
:
368 partitioning
= V_028B6C_PART_INTEGER
;
376 topology
= V_028B6C_OUTPUT_POINT
;
377 else if (tes_prim_mode
== PIPE_PRIM_LINES
)
378 topology
= V_028B6C_OUTPUT_LINE
;
379 else if (tes_vertex_order_cw
)
380 /* for some reason, this must be the other way around */
381 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
383 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
385 if (sscreen
->has_distributed_tess
) {
386 if (sscreen
->info
.family
== CHIP_FIJI
||
387 sscreen
->info
.family
>= CHIP_POLARIS10
)
388 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
390 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
392 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
395 pm4
->shader
->vgt_tf_param
= S_028B6C_TYPE(type
) |
396 S_028B6C_PARTITIONING(partitioning
) |
397 S_028B6C_TOPOLOGY(topology
) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
404 * Possible VGT configurations and which state should set the register:
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
415 static void polaris_set_vgt_vertex_reuse(struct si_screen
*sscreen
,
416 struct si_shader_selector
*sel
,
417 struct si_shader
*shader
,
418 struct si_pm4_state
*pm4
)
420 unsigned type
= sel
->type
;
422 if (sscreen
->info
.family
< CHIP_POLARIS10
||
423 sscreen
->info
.chip_class
>= GFX10
)
426 /* VS as VS, or VS as ES: */
427 if ((type
== PIPE_SHADER_VERTEX
&&
429 (!shader
->key
.as_ls
&& !shader
->is_gs_copy_shader
))) ||
430 /* TES as VS, or TES as ES: */
431 type
== PIPE_SHADER_TESS_EVAL
) {
432 unsigned vtx_reuse_depth
= 30;
434 if (type
== PIPE_SHADER_TESS_EVAL
&&
435 sel
->info
.properties
[TGSI_PROPERTY_TES_SPACING
] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD
)
437 vtx_reuse_depth
= 14;
440 pm4
->shader
->vgt_vertex_reuse_block_cntl
= vtx_reuse_depth
;
444 static struct si_pm4_state
*si_get_shader_pm4_state(struct si_shader
*shader
)
447 si_pm4_clear_state(shader
->pm4
);
449 shader
->pm4
= CALLOC_STRUCT(si_pm4_state
);
452 shader
->pm4
->shader
= shader
;
455 fprintf(stderr
, "radeonsi: Failed to create pm4 state.\n");
460 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs
)
462 /* Add the pointer to VBO descriptors. */
463 return num_always_on_user_sgprs
+ 1;
466 static void si_shader_ls(struct si_screen
*sscreen
, struct si_shader
*shader
)
468 struct si_pm4_state
*pm4
;
469 unsigned vgpr_comp_cnt
;
472 assert(sscreen
->info
.chip_class
<= GFX8
);
474 pm4
= si_get_shader_pm4_state(shader
);
478 va
= shader
->bo
->gpu_address
;
479 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
481 /* We need at least 2 components for LS.
482 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
483 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
485 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 2 : 1;
487 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
488 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
490 shader
->config
.rsrc1
= S_00B528_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
491 S_00B528_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
492 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt
) |
493 S_00B528_DX10_CLAMP(1) |
494 S_00B528_FLOAT_MODE(shader
->config
.float_mode
);
495 shader
->config
.rsrc2
= S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
)) |
496 S_00B52C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
499 static void si_shader_hs(struct si_screen
*sscreen
, struct si_shader
*shader
)
501 struct si_pm4_state
*pm4
;
503 unsigned ls_vgpr_comp_cnt
= 0;
505 pm4
= si_get_shader_pm4_state(shader
);
509 va
= shader
->bo
->gpu_address
;
510 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
512 if (sscreen
->info
.chip_class
>= GFX9
) {
513 if (sscreen
->info
.chip_class
>= GFX10
) {
514 si_pm4_set_reg(pm4
, R_00B520_SPI_SHADER_PGM_LO_LS
, va
>> 8);
515 si_pm4_set_reg(pm4
, R_00B524_SPI_SHADER_PGM_HI_LS
, S_00B524_MEM_BASE(va
>> 40));
517 si_pm4_set_reg(pm4
, R_00B410_SPI_SHADER_PGM_LO_LS
, va
>> 8);
518 si_pm4_set_reg(pm4
, R_00B414_SPI_SHADER_PGM_HI_LS
, S_00B414_MEM_BASE(va
>> 40));
521 /* We need at least 2 components for LS.
522 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
523 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
524 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
527 ls_vgpr_comp_cnt
= 1;
528 if (shader
->info
.uses_instanceid
) {
529 if (sscreen
->info
.chip_class
>= GFX10
)
530 ls_vgpr_comp_cnt
= 3;
532 ls_vgpr_comp_cnt
= 2;
535 unsigned num_user_sgprs
=
536 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR
);
538 shader
->config
.rsrc2
=
539 S_00B42C_USER_SGPR(num_user_sgprs
) |
540 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
542 if (sscreen
->info
.chip_class
>= GFX10
)
543 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
545 shader
->config
.rsrc2
|= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
547 si_pm4_set_reg(pm4
, R_00B420_SPI_SHADER_PGM_LO_HS
, va
>> 8);
548 si_pm4_set_reg(pm4
, R_00B424_SPI_SHADER_PGM_HI_HS
, S_00B424_MEM_BASE(va
>> 40));
550 shader
->config
.rsrc2
=
551 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR
) |
552 S_00B42C_OC_LDS_EN(1) |
553 S_00B42C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
556 si_pm4_set_reg(pm4
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
,
557 S_00B428_VGPRS((shader
->config
.num_vgprs
- 1) /
558 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
559 (sscreen
->info
.chip_class
<= GFX9
?
560 S_00B428_SGPRS((shader
->config
.num_sgprs
- 1) / 8) : 0) |
561 S_00B428_DX10_CLAMP(1) |
562 S_00B428_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
563 S_00B428_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
564 S_00B428_FLOAT_MODE(shader
->config
.float_mode
) |
565 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt
));
567 if (sscreen
->info
.chip_class
<= GFX8
) {
568 si_pm4_set_reg(pm4
, R_00B42C_SPI_SHADER_PGM_RSRC2_HS
,
569 shader
->config
.rsrc2
);
573 static void si_emit_shader_es(struct si_context
*sctx
)
575 struct si_shader
*shader
= sctx
->queued
.named
.es
->shader
;
576 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
581 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
582 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
583 shader
->selector
->esgs_itemsize
/ 4);
585 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
586 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
587 SI_TRACKED_VGT_TF_PARAM
,
588 shader
->vgt_tf_param
);
590 if (shader
->vgt_vertex_reuse_block_cntl
)
591 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
592 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
593 shader
->vgt_vertex_reuse_block_cntl
);
595 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
596 sctx
->context_roll
= true;
599 static void si_shader_es(struct si_screen
*sscreen
, struct si_shader
*shader
)
601 struct si_pm4_state
*pm4
;
602 unsigned num_user_sgprs
;
603 unsigned vgpr_comp_cnt
;
607 assert(sscreen
->info
.chip_class
<= GFX8
);
609 pm4
= si_get_shader_pm4_state(shader
);
613 pm4
->atom
.emit
= si_emit_shader_es
;
614 va
= shader
->bo
->gpu_address
;
615 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
617 if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
618 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
619 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
620 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
621 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
622 vgpr_comp_cnt
= shader
->selector
->info
.uses_primid
? 3 : 2;
623 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
625 unreachable("invalid shader selector type");
627 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
629 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
630 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
631 si_pm4_set_reg(pm4
, R_00B328_SPI_SHADER_PGM_RSRC1_ES
,
632 S_00B328_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
633 S_00B328_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
634 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt
) |
635 S_00B328_DX10_CLAMP(1) |
636 S_00B328_FLOAT_MODE(shader
->config
.float_mode
));
637 si_pm4_set_reg(pm4
, R_00B32C_SPI_SHADER_PGM_RSRC2_ES
,
638 S_00B32C_USER_SGPR(num_user_sgprs
) |
639 S_00B32C_OC_LDS_EN(oc_lds_en
) |
640 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
642 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
643 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
645 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
648 void gfx9_get_gs_info(struct si_shader_selector
*es
,
649 struct si_shader_selector
*gs
,
650 struct gfx9_gs_info
*out
)
652 unsigned gs_num_invocations
= MAX2(gs
->gs_num_invocations
, 1);
653 unsigned input_prim
= gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
654 bool uses_adjacency
= input_prim
>= PIPE_PRIM_LINES_ADJACENCY
&&
655 input_prim
<= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY
;
657 /* All these are in dwords: */
658 /* We can't allow using the whole LDS, because GS waves compete with
659 * other shader stages for LDS space. */
660 const unsigned max_lds_size
= 8 * 1024;
661 const unsigned esgs_itemsize
= es
->esgs_itemsize
/ 4;
662 unsigned esgs_lds_size
;
664 /* All these are per subgroup: */
665 const unsigned max_out_prims
= 32 * 1024;
666 const unsigned max_es_verts
= 255;
667 const unsigned ideal_gs_prims
= 64;
668 unsigned max_gs_prims
, gs_prims
;
669 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
671 if (uses_adjacency
|| gs_num_invocations
> 1)
672 max_gs_prims
= 127 / gs_num_invocations
;
676 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
677 * Make sure we don't go over the maximum value.
679 if (gs
->gs_max_out_vertices
> 0) {
680 max_gs_prims
= MIN2(max_gs_prims
,
682 (gs
->gs_max_out_vertices
* gs_num_invocations
));
684 assert(max_gs_prims
> 0);
686 /* If the primitive has adjacency, halve the number of vertices
687 * that will be reused in multiple primitives.
689 min_es_verts
= gs
->gs_input_verts_per_prim
/ (uses_adjacency
? 2 : 1);
691 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
692 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
694 /* Compute ESGS LDS size based on the worst case number of ES vertices
695 * needed to create the target number of GS prims per subgroup.
697 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
699 /* If total LDS usage is too big, refactor partitions based on ratio
700 * of ESGS item sizes.
702 if (esgs_lds_size
> max_lds_size
) {
703 /* Our target GS Prims Per Subgroup was too large. Calculate
704 * the maximum number of GS Prims Per Subgroup that will fit
705 * into LDS, capped by the maximum that the hardware can support.
707 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
709 assert(gs_prims
> 0);
710 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
713 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
714 assert(esgs_lds_size
<= max_lds_size
);
717 /* Now calculate remaining ESGS information. */
719 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
721 es_verts
= max_es_verts
;
723 /* Vertices for adjacency primitives are not always reused, so restore
724 * it for ES_VERTS_PER_SUBGRP.
726 min_es_verts
= gs
->gs_input_verts_per_prim
;
728 /* For normal primitives, the VGT only checks if they are past the ES
729 * verts per subgroup after allocating a full GS primitive and if they
730 * are, kick off a new subgroup. But if those additional ES verts are
731 * unique (e.g. not reused) we need to make sure there is enough LDS
732 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
734 es_verts
-= min_es_verts
- 1;
736 out
->es_verts_per_subgroup
= es_verts
;
737 out
->gs_prims_per_subgroup
= gs_prims
;
738 out
->gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
739 out
->max_prims_per_subgroup
= out
->gs_inst_prims_in_subgroup
*
740 gs
->gs_max_out_vertices
;
741 out
->esgs_ring_size
= 4 * esgs_lds_size
;
743 assert(out
->max_prims_per_subgroup
<= max_out_prims
);
746 static void si_emit_shader_gs(struct si_context
*sctx
)
748 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
749 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
754 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
755 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
756 radeon_opt_set_context_reg3(sctx
, R_028A60_VGT_GSVS_RING_OFFSET_1
,
757 SI_TRACKED_VGT_GSVS_RING_OFFSET_1
,
758 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
,
759 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
,
760 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
);
762 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
763 radeon_opt_set_context_reg(sctx
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
,
764 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE
,
765 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
);
767 /* R_028B38_VGT_GS_MAX_VERT_OUT */
768 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
769 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
770 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
);
772 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
773 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
774 radeon_opt_set_context_reg4(sctx
, R_028B5C_VGT_GS_VERT_ITEMSIZE
,
775 SI_TRACKED_VGT_GS_VERT_ITEMSIZE
,
776 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
,
777 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
,
778 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
,
779 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
);
781 /* R_028B90_VGT_GS_INSTANCE_CNT */
782 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
783 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
784 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
);
786 if (sctx
->chip_class
>= GFX9
) {
787 /* R_028A44_VGT_GS_ONCHIP_CNTL */
788 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
789 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
790 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
);
791 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
792 radeon_opt_set_context_reg(sctx
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
793 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP
,
794 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
);
795 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
796 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
797 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
798 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
);
800 if (shader
->key
.part
.gs
.es
->type
== PIPE_SHADER_TESS_EVAL
)
801 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
802 SI_TRACKED_VGT_TF_PARAM
,
803 shader
->vgt_tf_param
);
804 if (shader
->vgt_vertex_reuse_block_cntl
)
805 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
806 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
807 shader
->vgt_vertex_reuse_block_cntl
);
810 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
811 sctx
->context_roll
= true;
814 static void si_shader_gs(struct si_screen
*sscreen
, struct si_shader
*shader
)
816 struct si_shader_selector
*sel
= shader
->selector
;
817 const ubyte
*num_components
= sel
->info
.num_stream_output_components
;
818 unsigned gs_num_invocations
= sel
->gs_num_invocations
;
819 struct si_pm4_state
*pm4
;
821 unsigned max_stream
= sel
->max_gs_stream
;
824 pm4
= si_get_shader_pm4_state(shader
);
828 pm4
->atom
.emit
= si_emit_shader_gs
;
830 offset
= num_components
[0] * sel
->gs_max_out_vertices
;
831 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_1
= offset
;
834 offset
+= num_components
[1] * sel
->gs_max_out_vertices
;
835 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_2
= offset
;
838 offset
+= num_components
[2] * sel
->gs_max_out_vertices
;
839 shader
->ctx_reg
.gs
.vgt_gsvs_ring_offset_3
= offset
;
842 offset
+= num_components
[3] * sel
->gs_max_out_vertices
;
843 shader
->ctx_reg
.gs
.vgt_gsvs_ring_itemsize
= offset
;
845 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
846 assert(offset
< (1 << 15));
848 shader
->ctx_reg
.gs
.vgt_gs_max_vert_out
= sel
->gs_max_out_vertices
;
850 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize
= num_components
[0];
851 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_1
= (max_stream
>= 1) ? num_components
[1] : 0;
852 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_2
= (max_stream
>= 2) ? num_components
[2] : 0;
853 shader
->ctx_reg
.gs
.vgt_gs_vert_itemsize_3
= (max_stream
>= 3) ? num_components
[3] : 0;
855 shader
->ctx_reg
.gs
.vgt_gs_instance_cnt
= S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
856 S_028B90_ENABLE(gs_num_invocations
> 0);
858 va
= shader
->bo
->gpu_address
;
859 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
861 if (sscreen
->info
.chip_class
>= GFX9
) {
862 unsigned input_prim
= sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
863 unsigned es_type
= shader
->key
.part
.gs
.es
->type
;
864 unsigned es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
866 if (es_type
== PIPE_SHADER_VERTEX
)
867 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
868 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 1 : 0;
869 else if (es_type
== PIPE_SHADER_TESS_EVAL
)
870 es_vgpr_comp_cnt
= shader
->key
.part
.gs
.es
->info
.uses_primid
? 3 : 2;
872 unreachable("invalid shader selector type");
874 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
875 * VGPR[0:4] are always loaded.
877 if (sel
->info
.uses_invocationid
)
878 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID. */
879 else if (sel
->info
.uses_primid
)
880 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
881 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
882 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
884 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
886 unsigned num_user_sgprs
;
887 if (es_type
== PIPE_SHADER_VERTEX
)
888 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
890 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
892 if (sscreen
->info
.chip_class
>= GFX10
) {
893 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
894 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, S_00B324_MEM_BASE(va
>> 40));
896 si_pm4_set_reg(pm4
, R_00B210_SPI_SHADER_PGM_LO_ES
, va
>> 8);
897 si_pm4_set_reg(pm4
, R_00B214_SPI_SHADER_PGM_HI_ES
, S_00B214_MEM_BASE(va
>> 40));
901 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
902 S_00B228_DX10_CLAMP(1) |
903 S_00B228_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
904 S_00B228_WGP_MODE(sscreen
->info
.chip_class
>= GFX10
) |
905 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
);
908 S_00B22C_USER_SGPR(num_user_sgprs
) |
909 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
910 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
911 S_00B22C_LDS_SIZE(shader
->config
.lds_size
) |
912 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
914 if (sscreen
->info
.chip_class
>= GFX10
) {
915 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5);
917 rsrc1
|= S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
918 rsrc2
|= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs
>> 5);
921 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, rsrc1
);
922 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
, rsrc2
);
924 shader
->ctx_reg
.gs
.vgt_gs_onchip_cntl
=
925 S_028A44_ES_VERTS_PER_SUBGRP(shader
->gs_info
.es_verts_per_subgroup
) |
926 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->gs_info
.gs_prims_per_subgroup
) |
927 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->gs_info
.gs_inst_prims_in_subgroup
);
928 shader
->ctx_reg
.gs
.vgt_gs_max_prims_per_subgroup
=
929 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader
->gs_info
.max_prims_per_subgroup
);
930 shader
->ctx_reg
.gs
.vgt_esgs_ring_itemsize
=
931 shader
->key
.part
.gs
.es
->esgs_itemsize
/ 4;
933 if (es_type
== PIPE_SHADER_TESS_EVAL
)
934 si_set_tesseval_regs(sscreen
, shader
->key
.part
.gs
.es
, pm4
);
936 polaris_set_vgt_vertex_reuse(sscreen
, shader
->key
.part
.gs
.es
,
939 si_pm4_set_reg(pm4
, R_00B220_SPI_SHADER_PGM_LO_GS
, va
>> 8);
940 si_pm4_set_reg(pm4
, R_00B224_SPI_SHADER_PGM_HI_GS
, S_00B224_MEM_BASE(va
>> 40));
942 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
943 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) / 4) |
944 S_00B228_SGPRS((shader
->config
.num_sgprs
- 1) / 8) |
945 S_00B228_DX10_CLAMP(1) |
946 S_00B228_FLOAT_MODE(shader
->config
.float_mode
));
947 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
948 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR
) |
949 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
953 /* Common tail code for NGG primitive shaders. */
954 static void gfx10_emit_shader_ngg_tail(struct si_context
*sctx
,
955 struct si_shader
*shader
,
956 unsigned initial_cdw
)
958 radeon_opt_set_context_reg(sctx
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
959 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP
,
960 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
);
961 radeon_opt_set_context_reg(sctx
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
962 SI_TRACKED_GE_NGG_SUBGRP_CNTL
,
963 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
);
964 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
965 SI_TRACKED_VGT_PRIMITIVEID_EN
,
966 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
);
967 radeon_opt_set_context_reg(sctx
, R_028A44_VGT_GS_ONCHIP_CNTL
,
968 SI_TRACKED_VGT_GS_ONCHIP_CNTL
,
969 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
);
970 radeon_opt_set_context_reg(sctx
, R_028B90_VGT_GS_INSTANCE_CNT
,
971 SI_TRACKED_VGT_GS_INSTANCE_CNT
,
972 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
);
973 radeon_opt_set_context_reg(sctx
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
974 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE
,
975 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
);
976 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
977 SI_TRACKED_VGT_REUSE_OFF
,
978 shader
->ctx_reg
.ngg
.vgt_reuse_off
);
979 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
980 SI_TRACKED_SPI_VS_OUT_CONFIG
,
981 shader
->ctx_reg
.ngg
.spi_vs_out_config
);
982 radeon_opt_set_context_reg2(sctx
, R_028708_SPI_SHADER_IDX_FORMAT
,
983 SI_TRACKED_SPI_SHADER_IDX_FORMAT
,
984 shader
->ctx_reg
.ngg
.spi_shader_idx_format
,
985 shader
->ctx_reg
.ngg
.spi_shader_pos_format
);
986 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
987 SI_TRACKED_PA_CL_VTE_CNTL
,
988 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
);
989 radeon_opt_set_context_reg(sctx
, R_028838_PA_CL_NGG_CNTL
,
990 SI_TRACKED_PA_CL_NGG_CNTL
,
991 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
);
993 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
994 sctx
->context_roll
= true;
997 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context
*sctx
)
999 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1000 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1005 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1008 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context
*sctx
)
1010 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1011 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1016 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1017 SI_TRACKED_VGT_TF_PARAM
,
1018 shader
->vgt_tf_param
);
1020 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1023 static void gfx10_emit_shader_ngg_notess_gs(struct si_context
*sctx
)
1025 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1026 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1031 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1032 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1033 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1035 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1038 static void gfx10_emit_shader_ngg_tess_gs(struct si_context
*sctx
)
1040 struct si_shader
*shader
= sctx
->queued
.named
.gs
->shader
;
1041 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1046 radeon_opt_set_context_reg(sctx
, R_028B38_VGT_GS_MAX_VERT_OUT
,
1047 SI_TRACKED_VGT_GS_MAX_VERT_OUT
,
1048 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
);
1049 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1050 SI_TRACKED_VGT_TF_PARAM
,
1051 shader
->vgt_tf_param
);
1053 gfx10_emit_shader_ngg_tail(sctx
, shader
, initial_cdw
);
1056 static void si_set_ge_pc_alloc(struct si_screen
*sscreen
,
1057 struct si_pm4_state
*pm4
, bool culling
)
1059 si_pm4_set_reg(pm4
, R_030980_GE_PC_ALLOC
,
1060 S_030980_OVERSUB_EN(1) |
1061 S_030980_NUM_PC_LINES((culling
? 256 : 128) * sscreen
->info
.max_se
- 1));
1064 unsigned si_get_input_prim(const struct si_shader_selector
*gs
)
1066 if (gs
->type
== PIPE_SHADER_GEOMETRY
)
1067 return gs
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
];
1069 if (gs
->type
== PIPE_SHADER_TESS_EVAL
) {
1070 if (gs
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
1071 return PIPE_PRIM_POINTS
;
1072 if (gs
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
1073 return PIPE_PRIM_LINES
;
1074 return PIPE_PRIM_TRIANGLES
;
1077 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1078 return PIPE_PRIM_TRIANGLES
; /* worst case for all callers */
1082 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1085 static void gfx10_shader_ngg(struct si_screen
*sscreen
, struct si_shader
*shader
)
1087 const struct si_shader_selector
*gs_sel
= shader
->selector
;
1088 const struct tgsi_shader_info
*gs_info
= &gs_sel
->info
;
1089 enum pipe_shader_type gs_type
= shader
->selector
->type
;
1090 const struct si_shader_selector
*es_sel
=
1091 shader
->previous_stage_sel
? shader
->previous_stage_sel
: shader
->selector
;
1092 const struct tgsi_shader_info
*es_info
= &es_sel
->info
;
1093 enum pipe_shader_type es_type
= es_sel
->type
;
1094 unsigned num_user_sgprs
;
1095 unsigned nparams
, es_vgpr_comp_cnt
, gs_vgpr_comp_cnt
;
1097 unsigned window_space
=
1098 gs_info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1099 bool es_enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| es_info
->uses_primid
;
1100 unsigned gs_num_invocations
= MAX2(gs_sel
->gs_num_invocations
, 1);
1101 unsigned input_prim
= si_get_input_prim(gs_sel
);
1102 bool break_wave_at_eoi
= false;
1103 struct si_pm4_state
*pm4
= si_get_shader_pm4_state(shader
);
1107 if (es_type
== PIPE_SHADER_TESS_EVAL
) {
1108 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_tess_gs
1109 : gfx10_emit_shader_ngg_tess_nogs
;
1111 pm4
->atom
.emit
= gs_type
== PIPE_SHADER_GEOMETRY
? gfx10_emit_shader_ngg_notess_gs
1112 : gfx10_emit_shader_ngg_notess_nogs
;
1115 va
= shader
->bo
->gpu_address
;
1116 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1118 if (es_type
== PIPE_SHADER_VERTEX
) {
1119 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1120 es_vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : 0;
1122 if (es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1123 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1124 es_info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1126 num_user_sgprs
= si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR
);
1129 assert(es_type
== PIPE_SHADER_TESS_EVAL
);
1130 es_vgpr_comp_cnt
= es_enable_prim_id
? 3 : 2;
1131 num_user_sgprs
= GFX9_TESGS_NUM_USER_SGPR
;
1133 if (es_enable_prim_id
|| gs_info
->uses_primid
)
1134 break_wave_at_eoi
= true;
1137 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1138 * VGPR[0:4] are always loaded.
1140 * Vertex shaders always need to load VGPR3, because they need to
1141 * pass edge flags for decomposed primitives (such as quads) to the PA
1142 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1144 if (gs_info
->uses_invocationid
|| gs_type
== PIPE_SHADER_VERTEX
)
1145 gs_vgpr_comp_cnt
= 3; /* VGPR3 contains InvocationID, edge flags. */
1146 else if (gs_info
->uses_primid
)
1147 gs_vgpr_comp_cnt
= 2; /* VGPR2 contains PrimitiveID. */
1148 else if (input_prim
>= PIPE_PRIM_TRIANGLES
)
1149 gs_vgpr_comp_cnt
= 1; /* VGPR1 contains offsets 2, 3 */
1151 gs_vgpr_comp_cnt
= 0; /* VGPR0 contains offsets 0, 1 */
1153 si_pm4_set_reg(pm4
, R_00B320_SPI_SHADER_PGM_LO_ES
, va
>> 8);
1154 si_pm4_set_reg(pm4
, R_00B324_SPI_SHADER_PGM_HI_ES
, va
>> 40);
1155 si_pm4_set_reg(pm4
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
,
1156 S_00B228_VGPRS((shader
->config
.num_vgprs
- 1) /
1157 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1158 S_00B228_FLOAT_MODE(shader
->config
.float_mode
) |
1159 S_00B228_DX10_CLAMP(1) |
1160 S_00B228_MEM_ORDERED(1) |
1161 S_00B228_WGP_MODE(1) |
1162 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt
));
1163 si_pm4_set_reg(pm4
, R_00B22C_SPI_SHADER_PGM_RSRC2_GS
,
1164 S_00B22C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0) |
1165 S_00B22C_USER_SGPR(num_user_sgprs
) |
1166 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt
) |
1167 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs
>> 5) |
1168 S_00B22C_OC_LDS_EN(es_type
== PIPE_SHADER_TESS_EVAL
) |
1169 S_00B22C_LDS_SIZE(shader
->config
.lds_size
));
1170 si_set_ge_pc_alloc(sscreen
, pm4
, false);
1172 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1173 shader
->ctx_reg
.ngg
.spi_vs_out_config
=
1174 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
1175 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1177 shader
->ctx_reg
.ngg
.spi_shader_idx_format
=
1178 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
);
1179 shader
->ctx_reg
.ngg
.spi_shader_pos_format
=
1180 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1181 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1182 V_02870C_SPI_SHADER_4COMP
:
1183 V_02870C_SPI_SHADER_NONE
) |
1184 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1185 V_02870C_SPI_SHADER_4COMP
:
1186 V_02870C_SPI_SHADER_NONE
) |
1187 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1188 V_02870C_SPI_SHADER_4COMP
:
1189 V_02870C_SPI_SHADER_NONE
);
1191 shader
->ctx_reg
.ngg
.vgt_primitiveid_en
=
1192 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
1193 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
);
1195 if (gs_type
== PIPE_SHADER_GEOMETRY
) {
1196 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= es_sel
->esgs_itemsize
/ 4;
1197 shader
->ctx_reg
.ngg
.vgt_gs_max_vert_out
= gs_sel
->gs_max_out_vertices
;
1199 shader
->ctx_reg
.ngg
.vgt_esgs_ring_itemsize
= 1;
1202 if (es_type
== PIPE_SHADER_TESS_EVAL
)
1203 si_set_tesseval_regs(sscreen
, es_sel
, pm4
);
1205 shader
->ctx_reg
.ngg
.vgt_gs_onchip_cntl
=
1206 S_028A44_ES_VERTS_PER_SUBGRP(shader
->ngg
.hw_max_esverts
) |
1207 S_028A44_GS_PRIMS_PER_SUBGRP(shader
->ngg
.max_gsprims
) |
1208 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader
->ngg
.max_gsprims
* gs_num_invocations
);
1209 shader
->ctx_reg
.ngg
.ge_max_output_per_subgroup
=
1210 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader
->ngg
.max_out_verts
);
1211 shader
->ctx_reg
.ngg
.ge_ngg_subgrp_cntl
=
1212 S_028B4C_PRIM_AMP_FACTOR(shader
->ngg
.prim_amp_factor
) |
1213 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1214 shader
->ctx_reg
.ngg
.vgt_gs_instance_cnt
=
1215 S_028B90_CNT(gs_num_invocations
) |
1216 S_028B90_ENABLE(gs_num_invocations
> 1) |
1217 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1218 shader
->ngg
.max_vert_out_per_gs_instance
);
1220 /* Always output hw-generated edge flags and pass them via the prim
1221 * export to prevent drawing lines on internal edges of decomposed
1222 * primitives (such as quads) with polygon mode = lines. Only VS needs
1225 shader
->ctx_reg
.ngg
.pa_cl_ngg_cntl
=
1226 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type
== PIPE_SHADER_VERTEX
);
1229 S_03096C_PRIM_GRP_SIZE(shader
->ngg
.max_gsprims
) |
1230 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
) |
1231 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
1233 /* Bug workaround for a possible hang with non-tessellation cases.
1234 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1236 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1238 if ((sscreen
->info
.family
== CHIP_NAVI10
||
1239 sscreen
->info
.family
== CHIP_NAVI12
||
1240 sscreen
->info
.family
== CHIP_NAVI14
) &&
1241 (es_type
== PIPE_SHADER_VERTEX
|| gs_type
== PIPE_SHADER_VERTEX
) && /* = no tess */
1242 shader
->ngg
.hw_max_esverts
!= 256) {
1243 shader
->ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
1245 if (shader
->ngg
.hw_max_esverts
> 5) {
1247 S_03096C_VERT_GRP_SIZE(shader
->ngg
.hw_max_esverts
- 5);
1252 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1253 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1255 shader
->ctx_reg
.ngg
.pa_cl_vte_cntl
=
1256 S_028818_VTX_W0_FMT(1) |
1257 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1258 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1259 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1262 shader
->ctx_reg
.ngg
.vgt_reuse_off
=
1263 S_028AB4_REUSE_OFF(sscreen
->info
.family
== CHIP_NAVI10
&&
1264 sscreen
->info
.chip_external_rev
== 0x1 &&
1265 es_type
== PIPE_SHADER_TESS_EVAL
);
1268 static void si_emit_shader_vs(struct si_context
*sctx
)
1270 struct si_shader
*shader
= sctx
->queued
.named
.vs
->shader
;
1271 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1276 radeon_opt_set_context_reg(sctx
, R_028A40_VGT_GS_MODE
,
1277 SI_TRACKED_VGT_GS_MODE
,
1278 shader
->ctx_reg
.vs
.vgt_gs_mode
);
1279 radeon_opt_set_context_reg(sctx
, R_028A84_VGT_PRIMITIVEID_EN
,
1280 SI_TRACKED_VGT_PRIMITIVEID_EN
,
1281 shader
->ctx_reg
.vs
.vgt_primitiveid_en
);
1283 if (sctx
->chip_class
<= GFX8
) {
1284 radeon_opt_set_context_reg(sctx
, R_028AB4_VGT_REUSE_OFF
,
1285 SI_TRACKED_VGT_REUSE_OFF
,
1286 shader
->ctx_reg
.vs
.vgt_reuse_off
);
1289 radeon_opt_set_context_reg(sctx
, R_0286C4_SPI_VS_OUT_CONFIG
,
1290 SI_TRACKED_SPI_VS_OUT_CONFIG
,
1291 shader
->ctx_reg
.vs
.spi_vs_out_config
);
1293 radeon_opt_set_context_reg(sctx
, R_02870C_SPI_SHADER_POS_FORMAT
,
1294 SI_TRACKED_SPI_SHADER_POS_FORMAT
,
1295 shader
->ctx_reg
.vs
.spi_shader_pos_format
);
1297 radeon_opt_set_context_reg(sctx
, R_028818_PA_CL_VTE_CNTL
,
1298 SI_TRACKED_PA_CL_VTE_CNTL
,
1299 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
);
1301 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1302 radeon_opt_set_context_reg(sctx
, R_028B6C_VGT_TF_PARAM
,
1303 SI_TRACKED_VGT_TF_PARAM
,
1304 shader
->vgt_tf_param
);
1306 if (shader
->vgt_vertex_reuse_block_cntl
)
1307 radeon_opt_set_context_reg(sctx
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1308 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL
,
1309 shader
->vgt_vertex_reuse_block_cntl
);
1311 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1312 sctx
->context_roll
= true;
1316 * Compute the state for \p shader, which will run as a vertex shader on the
1319 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1320 * is the copy shader.
1322 static void si_shader_vs(struct si_screen
*sscreen
, struct si_shader
*shader
,
1323 struct si_shader_selector
*gs
)
1325 const struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1326 struct si_pm4_state
*pm4
;
1327 unsigned num_user_sgprs
, vgpr_comp_cnt
;
1329 unsigned nparams
, oc_lds_en
;
1330 unsigned window_space
=
1331 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
1332 bool enable_prim_id
= shader
->key
.mono
.u
.vs_export_prim_id
|| info
->uses_primid
;
1334 pm4
= si_get_shader_pm4_state(shader
);
1338 pm4
->atom
.emit
= si_emit_shader_vs
;
1340 /* We always write VGT_GS_MODE in the VS state, because every switch
1341 * between different shader pipelines involving a different GS or no
1342 * GS at all involves a switch of the VS (different GS use different
1343 * copy shaders). On the other hand, when the API switches from a GS to
1344 * no GS and then back to the same GS used originally, the GS state is
1348 unsigned mode
= V_028A40_GS_OFF
;
1350 /* PrimID needs GS scenario A. */
1352 mode
= V_028A40_GS_SCENARIO_A
;
1354 shader
->ctx_reg
.vs
.vgt_gs_mode
= S_028A40_MODE(mode
);
1355 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= enable_prim_id
;
1357 shader
->ctx_reg
.vs
.vgt_gs_mode
= ac_vgt_gs_mode(gs
->gs_max_out_vertices
,
1358 sscreen
->info
.chip_class
);
1359 shader
->ctx_reg
.vs
.vgt_primitiveid_en
= 0;
1362 if (sscreen
->info
.chip_class
<= GFX8
) {
1363 /* Reuse needs to be set off if we write oViewport. */
1364 shader
->ctx_reg
.vs
.vgt_reuse_off
=
1365 S_028AB4_REUSE_OFF(info
->writes_viewport_index
);
1368 va
= shader
->bo
->gpu_address
;
1369 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1372 vgpr_comp_cnt
= 0; /* only VertexID is needed for GS-COPY. */
1373 num_user_sgprs
= SI_GSCOPY_NUM_USER_SGPR
;
1374 } else if (shader
->selector
->type
== PIPE_SHADER_VERTEX
) {
1375 if (sscreen
->info
.chip_class
>= GFX10
) {
1376 vgpr_comp_cnt
= shader
->info
.uses_instanceid
? 3 : (enable_prim_id
? 2 : 0);
1378 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1379 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1380 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1382 vgpr_comp_cnt
= enable_prim_id
? 2 : (shader
->info
.uses_instanceid
? 1 : 0);
1385 if (info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
]) {
1386 num_user_sgprs
= SI_SGPR_VS_BLIT_DATA
+
1387 info
->properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
1389 num_user_sgprs
= si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR
);
1391 } else if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
) {
1392 vgpr_comp_cnt
= enable_prim_id
? 3 : 2;
1393 num_user_sgprs
= SI_TES_NUM_USER_SGPR
;
1395 unreachable("invalid shader selector type");
1397 /* VS is required to export at least one param. */
1398 nparams
= MAX2(shader
->info
.nr_param_exports
, 1);
1399 shader
->ctx_reg
.vs
.spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
1401 if (sscreen
->info
.chip_class
>= GFX10
) {
1402 shader
->ctx_reg
.vs
.spi_vs_out_config
|=
1403 S_0286C4_NO_PC_EXPORT(shader
->info
.nr_param_exports
== 0);
1406 shader
->ctx_reg
.vs
.spi_shader_pos_format
=
1407 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
1408 S_02870C_POS1_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 1 ?
1409 V_02870C_SPI_SHADER_4COMP
:
1410 V_02870C_SPI_SHADER_NONE
) |
1411 S_02870C_POS2_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 2 ?
1412 V_02870C_SPI_SHADER_4COMP
:
1413 V_02870C_SPI_SHADER_NONE
) |
1414 S_02870C_POS3_EXPORT_FORMAT(shader
->info
.nr_pos_exports
> 3 ?
1415 V_02870C_SPI_SHADER_4COMP
:
1416 V_02870C_SPI_SHADER_NONE
);
1418 oc_lds_en
= shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
? 1 : 0;
1420 si_pm4_set_reg(pm4
, R_00B120_SPI_SHADER_PGM_LO_VS
, va
>> 8);
1421 si_pm4_set_reg(pm4
, R_00B124_SPI_SHADER_PGM_HI_VS
, S_00B124_MEM_BASE(va
>> 40));
1422 if (sscreen
->info
.chip_class
>= GFX10
)
1423 si_set_ge_pc_alloc(sscreen
, pm4
, false);
1425 uint32_t rsrc1
= S_00B128_VGPRS((shader
->config
.num_vgprs
- 1) /
1426 (sscreen
->ge_wave_size
== 32 ? 8 : 4)) |
1427 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt
) |
1428 S_00B128_DX10_CLAMP(1) |
1429 S_00B128_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1430 S_00B128_FLOAT_MODE(shader
->config
.float_mode
);
1431 uint32_t rsrc2
= S_00B12C_USER_SGPR(num_user_sgprs
) |
1432 S_00B12C_OC_LDS_EN(oc_lds_en
) |
1433 S_00B12C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0);
1435 if (sscreen
->info
.chip_class
<= GFX9
) {
1436 rsrc1
|= S_00B128_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1437 rsrc2
|= S_00B12C_SO_BASE0_EN(!!shader
->selector
->so
.stride
[0]) |
1438 S_00B12C_SO_BASE1_EN(!!shader
->selector
->so
.stride
[1]) |
1439 S_00B12C_SO_BASE2_EN(!!shader
->selector
->so
.stride
[2]) |
1440 S_00B12C_SO_BASE3_EN(!!shader
->selector
->so
.stride
[3]) |
1441 S_00B12C_SO_EN(!!shader
->selector
->so
.num_outputs
);
1444 si_pm4_set_reg(pm4
, R_00B128_SPI_SHADER_PGM_RSRC1_VS
, rsrc1
);
1445 si_pm4_set_reg(pm4
, R_00B12C_SPI_SHADER_PGM_RSRC2_VS
, rsrc2
);
1448 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1449 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1451 shader
->ctx_reg
.vs
.pa_cl_vte_cntl
=
1452 S_028818_VTX_W0_FMT(1) |
1453 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1454 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1455 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1457 if (shader
->selector
->type
== PIPE_SHADER_TESS_EVAL
)
1458 si_set_tesseval_regs(sscreen
, shader
->selector
, pm4
);
1460 polaris_set_vgt_vertex_reuse(sscreen
, shader
->selector
, shader
, pm4
);
1463 static unsigned si_get_ps_num_interp(struct si_shader
*ps
)
1465 struct tgsi_shader_info
*info
= &ps
->selector
->info
;
1466 unsigned num_colors
= !!(info
->colors_read
& 0x0f) +
1467 !!(info
->colors_read
& 0xf0);
1468 unsigned num_interp
= ps
->selector
->info
.num_inputs
+
1469 (ps
->key
.part
.ps
.prolog
.color_two_side
? num_colors
: 0);
1471 assert(num_interp
<= 32);
1472 return MIN2(num_interp
, 32);
1475 static unsigned si_get_spi_shader_col_format(struct si_shader
*shader
)
1477 unsigned value
= shader
->key
.part
.ps
.epilog
.spi_shader_col_format
;
1478 unsigned i
, num_targets
= (util_last_bit(value
) + 3) / 4;
1480 /* If the i-th target format is set, all previous target formats must
1481 * be non-zero to avoid hangs.
1483 for (i
= 0; i
< num_targets
; i
++)
1484 if (!(value
& (0xf << (i
* 4))))
1485 value
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
1490 static void si_emit_shader_ps(struct si_context
*sctx
)
1492 struct si_shader
*shader
= sctx
->queued
.named
.ps
->shader
;
1493 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
1498 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1499 radeon_opt_set_context_reg2(sctx
, R_0286CC_SPI_PS_INPUT_ENA
,
1500 SI_TRACKED_SPI_PS_INPUT_ENA
,
1501 shader
->ctx_reg
.ps
.spi_ps_input_ena
,
1502 shader
->ctx_reg
.ps
.spi_ps_input_addr
);
1504 radeon_opt_set_context_reg(sctx
, R_0286E0_SPI_BARYC_CNTL
,
1505 SI_TRACKED_SPI_BARYC_CNTL
,
1506 shader
->ctx_reg
.ps
.spi_baryc_cntl
);
1507 radeon_opt_set_context_reg(sctx
, R_0286D8_SPI_PS_IN_CONTROL
,
1508 SI_TRACKED_SPI_PS_IN_CONTROL
,
1509 shader
->ctx_reg
.ps
.spi_ps_in_control
);
1511 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1512 radeon_opt_set_context_reg2(sctx
, R_028710_SPI_SHADER_Z_FORMAT
,
1513 SI_TRACKED_SPI_SHADER_Z_FORMAT
,
1514 shader
->ctx_reg
.ps
.spi_shader_z_format
,
1515 shader
->ctx_reg
.ps
.spi_shader_col_format
);
1517 radeon_opt_set_context_reg(sctx
, R_02823C_CB_SHADER_MASK
,
1518 SI_TRACKED_CB_SHADER_MASK
,
1519 shader
->ctx_reg
.ps
.cb_shader_mask
);
1521 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
1522 sctx
->context_roll
= true;
1525 static void si_shader_ps(struct si_screen
*sscreen
, struct si_shader
*shader
)
1527 struct tgsi_shader_info
*info
= &shader
->selector
->info
;
1528 struct si_pm4_state
*pm4
;
1529 unsigned spi_ps_in_control
, spi_shader_col_format
, cb_shader_mask
;
1530 unsigned spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
1532 unsigned input_ena
= shader
->config
.spi_ps_input_ena
;
1534 /* we need to enable at least one of them, otherwise we hang the GPU */
1535 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1536 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1537 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1538 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
) ||
1539 G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) ||
1540 G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1541 G_0286CC_LINEAR_CENTROID_ENA(input_ena
) ||
1542 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena
));
1543 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1544 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena
) ||
1545 G_0286CC_PERSP_SAMPLE_ENA(input_ena
) ||
1546 G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1547 G_0286CC_PERSP_CENTROID_ENA(input_ena
) ||
1548 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena
));
1550 /* Validate interpolation optimization flags (read as implications). */
1551 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1552 (G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1553 G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1554 assert(!shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1555 (G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1556 G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1557 assert(!shader
->key
.part
.ps
.prolog
.force_persp_center_interp
||
1558 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena
) &&
1559 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1560 assert(!shader
->key
.part
.ps
.prolog
.force_linear_center_interp
||
1561 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena
) &&
1562 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1563 assert(!shader
->key
.part
.ps
.prolog
.force_persp_sample_interp
||
1564 (!G_0286CC_PERSP_CENTER_ENA(input_ena
) &&
1565 !G_0286CC_PERSP_CENTROID_ENA(input_ena
)));
1566 assert(!shader
->key
.part
.ps
.prolog
.force_linear_sample_interp
||
1567 (!G_0286CC_LINEAR_CENTER_ENA(input_ena
) &&
1568 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
)));
1570 /* Validate cases when the optimizations are off (read as implications). */
1571 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_persp
||
1572 !G_0286CC_PERSP_CENTER_ENA(input_ena
) ||
1573 !G_0286CC_PERSP_CENTROID_ENA(input_ena
));
1574 assert(shader
->key
.part
.ps
.prolog
.bc_optimize_for_linear
||
1575 !G_0286CC_LINEAR_CENTER_ENA(input_ena
) ||
1576 !G_0286CC_LINEAR_CENTROID_ENA(input_ena
));
1578 pm4
= si_get_shader_pm4_state(shader
);
1582 pm4
->atom
.emit
= si_emit_shader_ps
;
1584 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1586 * 0 -> Position = pixel center
1587 * 1 -> Position = pixel centroid
1588 * 2 -> Position = at sample position
1590 * From GLSL 4.5 specification, section 7.1:
1591 * "The variable gl_FragCoord is available as an input variable from
1592 * within fragment shaders and it holds the window relative coordinates
1593 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1594 * value can be for any location within the pixel, or one of the
1595 * fragment samples. The use of centroid does not further restrict
1596 * this value to be inside the current primitive."
1598 * Meaning that centroid has no effect and we can return anything within
1599 * the pixel. Thus, return the value at sample position, because that's
1600 * the most accurate one shaders can get.
1602 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1604 if (info
->properties
[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER
] ==
1605 TGSI_FS_COORD_PIXEL_CENTER_INTEGER
)
1606 spi_baryc_cntl
|= S_0286E0_POS_FLOAT_ULC(1);
1608 spi_shader_col_format
= si_get_spi_shader_col_format(shader
);
1609 cb_shader_mask
= ac_get_cb_shader_mask(spi_shader_col_format
);
1611 /* Ensure that some export memory is always allocated, for two reasons:
1613 * 1) Correctness: The hardware ignores the EXEC mask if no export
1614 * memory is allocated, so KILL and alpha test do not work correctly
1616 * 2) Performance: Every shader needs at least a NULL export, even when
1617 * it writes no color/depth output. The NULL export instruction
1618 * stalls without this setting.
1620 * Don't add this to CB_SHADER_MASK.
1622 * GFX10 supports pixel shaders without exports by setting both
1623 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1624 * instructions if any are present.
1626 if ((sscreen
->info
.chip_class
<= GFX9
||
1628 shader
->key
.part
.ps
.epilog
.alpha_func
!= PIPE_FUNC_ALWAYS
) &&
1629 !spi_shader_col_format
&&
1630 !info
->writes_z
&& !info
->writes_stencil
&& !info
->writes_samplemask
)
1631 spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
1633 shader
->ctx_reg
.ps
.spi_ps_input_ena
= input_ena
;
1634 shader
->ctx_reg
.ps
.spi_ps_input_addr
= shader
->config
.spi_ps_input_addr
;
1636 /* Set interpolation controls. */
1637 spi_ps_in_control
= S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader
)) |
1638 S_0286D8_PS_W32_EN(sscreen
->ps_wave_size
== 32);
1640 shader
->ctx_reg
.ps
.spi_baryc_cntl
= spi_baryc_cntl
;
1641 shader
->ctx_reg
.ps
.spi_ps_in_control
= spi_ps_in_control
;
1642 shader
->ctx_reg
.ps
.spi_shader_z_format
=
1643 ac_get_spi_shader_z_format(info
->writes_z
,
1644 info
->writes_stencil
,
1645 info
->writes_samplemask
);
1646 shader
->ctx_reg
.ps
.spi_shader_col_format
= spi_shader_col_format
;
1647 shader
->ctx_reg
.ps
.cb_shader_mask
= cb_shader_mask
;
1649 va
= shader
->bo
->gpu_address
;
1650 si_pm4_add_bo(pm4
, shader
->bo
, RADEON_USAGE_READ
, RADEON_PRIO_SHADER_BINARY
);
1651 si_pm4_set_reg(pm4
, R_00B020_SPI_SHADER_PGM_LO_PS
, va
>> 8);
1652 si_pm4_set_reg(pm4
, R_00B024_SPI_SHADER_PGM_HI_PS
, S_00B024_MEM_BASE(va
>> 40));
1655 S_00B028_VGPRS((shader
->config
.num_vgprs
- 1) /
1656 (sscreen
->ps_wave_size
== 32 ? 8 : 4)) |
1657 S_00B028_DX10_CLAMP(1) |
1658 S_00B028_MEM_ORDERED(sscreen
->info
.chip_class
>= GFX10
) |
1659 S_00B028_FLOAT_MODE(shader
->config
.float_mode
);
1661 if (sscreen
->info
.chip_class
< GFX10
) {
1662 rsrc1
|= S_00B028_SGPRS((shader
->config
.num_sgprs
- 1) / 8);
1665 si_pm4_set_reg(pm4
, R_00B028_SPI_SHADER_PGM_RSRC1_PS
, rsrc1
);
1666 si_pm4_set_reg(pm4
, R_00B02C_SPI_SHADER_PGM_RSRC2_PS
,
1667 S_00B02C_EXTRA_LDS_SIZE(shader
->config
.lds_size
) |
1668 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR
) |
1669 S_00B32C_SCRATCH_EN(shader
->config
.scratch_bytes_per_wave
> 0));
1672 static void si_shader_init_pm4_state(struct si_screen
*sscreen
,
1673 struct si_shader
*shader
)
1675 switch (shader
->selector
->type
) {
1676 case PIPE_SHADER_VERTEX
:
1677 if (shader
->key
.as_ls
)
1678 si_shader_ls(sscreen
, shader
);
1679 else if (shader
->key
.as_es
)
1680 si_shader_es(sscreen
, shader
);
1681 else if (shader
->key
.as_ngg
)
1682 gfx10_shader_ngg(sscreen
, shader
);
1684 si_shader_vs(sscreen
, shader
, NULL
);
1686 case PIPE_SHADER_TESS_CTRL
:
1687 si_shader_hs(sscreen
, shader
);
1689 case PIPE_SHADER_TESS_EVAL
:
1690 if (shader
->key
.as_es
)
1691 si_shader_es(sscreen
, shader
);
1692 else if (shader
->key
.as_ngg
)
1693 gfx10_shader_ngg(sscreen
, shader
);
1695 si_shader_vs(sscreen
, shader
, NULL
);
1697 case PIPE_SHADER_GEOMETRY
:
1698 if (shader
->key
.as_ngg
)
1699 gfx10_shader_ngg(sscreen
, shader
);
1701 si_shader_gs(sscreen
, shader
);
1703 case PIPE_SHADER_FRAGMENT
:
1704 si_shader_ps(sscreen
, shader
);
1711 static unsigned si_get_alpha_test_func(struct si_context
*sctx
)
1713 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1714 return sctx
->queued
.named
.dsa
->alpha_func
;
1717 void si_shader_selector_key_vs(struct si_context
*sctx
,
1718 struct si_shader_selector
*vs
,
1719 struct si_shader_key
*key
,
1720 struct si_vs_prolog_bits
*prolog_key
)
1722 if (!sctx
->vertex_elements
||
1723 vs
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
])
1726 struct si_vertex_elements
*elts
= sctx
->vertex_elements
;
1728 prolog_key
->instance_divisor_is_one
= elts
->instance_divisor_is_one
;
1729 prolog_key
->instance_divisor_is_fetched
= elts
->instance_divisor_is_fetched
;
1730 prolog_key
->unpack_instance_id_from_vertex_id
=
1731 sctx
->prim_discard_cs_instancing
;
1733 /* Prefer a monolithic shader to allow scheduling divisions around
1735 if (prolog_key
->instance_divisor_is_fetched
)
1736 key
->opt
.prefer_mono
= 1;
1738 unsigned count
= MIN2(vs
->info
.num_inputs
, elts
->count
);
1739 unsigned count_mask
= (1 << count
) - 1;
1740 unsigned fix
= elts
->fix_fetch_always
& count_mask
;
1741 unsigned opencode
= elts
->fix_fetch_opencode
& count_mask
;
1743 if (sctx
->vertex_buffer_unaligned
& elts
->vb_alignment_check_mask
) {
1744 uint32_t mask
= elts
->fix_fetch_unaligned
& count_mask
;
1746 unsigned i
= u_bit_scan(&mask
);
1747 unsigned log_hw_load_size
= 1 + ((elts
->hw_load_is_dword
>> i
) & 1);
1748 unsigned vbidx
= elts
->vertex_buffer_index
[i
];
1749 struct pipe_vertex_buffer
*vb
= &sctx
->vertex_buffer
[vbidx
];
1750 unsigned align_mask
= (1 << log_hw_load_size
) - 1;
1751 if (vb
->buffer_offset
& align_mask
||
1752 vb
->stride
& align_mask
) {
1760 unsigned i
= u_bit_scan(&fix
);
1761 key
->mono
.vs_fix_fetch
[i
].bits
= elts
->fix_fetch
[i
];
1763 key
->mono
.vs_fetch_opencode
= opencode
;
1766 static void si_shader_selector_key_hw_vs(struct si_context
*sctx
,
1767 struct si_shader_selector
*vs
,
1768 struct si_shader_key
*key
)
1770 struct si_shader_selector
*ps
= sctx
->ps_shader
.cso
;
1772 key
->opt
.clip_disable
=
1773 sctx
->queued
.named
.rasterizer
->clip_plane_enable
== 0 &&
1774 (vs
->info
.clipdist_writemask
||
1775 vs
->info
.writes_clipvertex
) &&
1776 !vs
->info
.culldist_writemask
;
1778 /* Find out if PS is disabled. */
1779 bool ps_disabled
= true;
1781 bool ps_modifies_zs
= ps
->info
.uses_kill
||
1782 ps
->info
.writes_z
||
1783 ps
->info
.writes_stencil
||
1784 ps
->info
.writes_samplemask
||
1785 sctx
->queued
.named
.blend
->alpha_to_coverage
||
1786 si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
;
1787 unsigned ps_colormask
= si_get_total_colormask(sctx
);
1789 ps_disabled
= sctx
->queued
.named
.rasterizer
->rasterizer_discard
||
1792 !ps
->info
.writes_memory
);
1795 /* Find out which VS outputs aren't used by the PS. */
1796 uint64_t outputs_written
= vs
->outputs_written_before_ps
;
1797 uint64_t inputs_read
= 0;
1799 /* Ignore outputs that are not passed from VS to PS. */
1800 outputs_written
&= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION
, 0, true)) |
1801 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE
, 0, true)) |
1802 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX
, 0, true)));
1805 inputs_read
= ps
->inputs_read
;
1808 uint64_t linked
= outputs_written
& inputs_read
;
1810 key
->opt
.kill_outputs
= ~linked
& outputs_written
;
1813 /* Compute the key for the hw shader variant */
1814 static inline void si_shader_selector_key(struct pipe_context
*ctx
,
1815 struct si_shader_selector
*sel
,
1816 union si_vgt_stages_key stages_key
,
1817 struct si_shader_key
*key
)
1819 struct si_context
*sctx
= (struct si_context
*)ctx
;
1821 memset(key
, 0, sizeof(*key
));
1823 switch (sel
->type
) {
1824 case PIPE_SHADER_VERTEX
:
1825 si_shader_selector_key_vs(sctx
, sel
, key
, &key
->part
.vs
.prolog
);
1827 if (sctx
->tes_shader
.cso
)
1829 else if (sctx
->gs_shader
.cso
)
1832 key
->as_ngg
= stages_key
.u
.ngg
;
1833 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1835 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1836 key
->mono
.u
.vs_export_prim_id
= 1;
1839 case PIPE_SHADER_TESS_CTRL
:
1840 if (sctx
->chip_class
>= GFX9
) {
1841 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1842 key
, &key
->part
.tcs
.ls_prolog
);
1843 key
->part
.tcs
.ls
= sctx
->vs_shader
.cso
;
1845 /* When the LS VGPR fix is needed, monolithic shaders
1847 * - avoid initializing EXEC in both the LS prolog
1848 * and the LS main part when !vs_needs_prolog
1849 * - remove the fixup for unused input VGPRs
1851 key
->part
.tcs
.ls_prolog
.ls_vgpr_fix
= sctx
->ls_vgpr_fix
;
1853 /* The LS output / HS input layout can be communicated
1854 * directly instead of via user SGPRs for merged LS-HS.
1855 * The LS VGPR fix prefers this too.
1857 key
->opt
.prefer_mono
= 1;
1860 key
->part
.tcs
.epilog
.prim_mode
=
1861 sctx
->tes_shader
.cso
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
];
1862 key
->part
.tcs
.epilog
.invoc0_tess_factors_are_def
=
1863 sel
->tcs_info
.tessfactors_are_def_in_all_invocs
;
1864 key
->part
.tcs
.epilog
.tes_reads_tess_factors
=
1865 sctx
->tes_shader
.cso
->info
.reads_tess_factors
;
1867 if (sel
== sctx
->fixed_func_tcs_shader
.cso
)
1868 key
->mono
.u
.ff_tcs_inputs_to_copy
= sctx
->vs_shader
.cso
->outputs_written
;
1870 case PIPE_SHADER_TESS_EVAL
:
1871 key
->as_ngg
= stages_key
.u
.ngg
;
1873 if (sctx
->gs_shader
.cso
)
1876 si_shader_selector_key_hw_vs(sctx
, sel
, key
);
1878 if (sctx
->ps_shader
.cso
&& sctx
->ps_shader
.cso
->info
.uses_primid
)
1879 key
->mono
.u
.vs_export_prim_id
= 1;
1882 case PIPE_SHADER_GEOMETRY
:
1883 if (sctx
->chip_class
>= GFX9
) {
1884 if (sctx
->tes_shader
.cso
) {
1885 key
->part
.gs
.es
= sctx
->tes_shader
.cso
;
1887 si_shader_selector_key_vs(sctx
, sctx
->vs_shader
.cso
,
1888 key
, &key
->part
.gs
.vs_prolog
);
1889 key
->part
.gs
.es
= sctx
->vs_shader
.cso
;
1890 key
->part
.gs
.prolog
.gfx9_prev_is_vs
= 1;
1893 key
->as_ngg
= stages_key
.u
.ngg
;
1895 /* Merged ES-GS can have unbalanced wave usage.
1897 * ES threads are per-vertex, while GS threads are
1898 * per-primitive. So without any amplification, there
1899 * are fewer GS threads than ES threads, which can result
1900 * in empty (no-op) GS waves. With too much amplification,
1901 * there are more GS threads than ES threads, which
1902 * can result in empty (no-op) ES waves.
1904 * Non-monolithic shaders are implemented by setting EXEC
1905 * at the beginning of shader parts, and don't jump to
1906 * the end if EXEC is 0.
1908 * Monolithic shaders use conditional blocks, so they can
1909 * jump and skip empty waves of ES or GS. So set this to
1910 * always use optimized variants, which are monolithic.
1912 key
->opt
.prefer_mono
= 1;
1914 key
->part
.gs
.prolog
.tri_strip_adj_fix
= sctx
->gs_tri_strip_adj_fix
;
1916 case PIPE_SHADER_FRAGMENT
: {
1917 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
1918 struct si_state_blend
*blend
= sctx
->queued
.named
.blend
;
1920 if (sel
->info
.properties
[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS
] &&
1921 sel
->info
.colors_written
== 0x1)
1922 key
->part
.ps
.epilog
.last_cbuf
= MAX2(sctx
->framebuffer
.state
.nr_cbufs
, 1) - 1;
1924 /* Select the shader color format based on whether
1925 * blending or alpha are needed.
1927 key
->part
.ps
.epilog
.spi_shader_col_format
=
1928 (blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1929 sctx
->framebuffer
.spi_shader_col_format_blend_alpha
) |
1930 (blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1931 sctx
->framebuffer
.spi_shader_col_format_blend
) |
1932 (~blend
->blend_enable_4bit
& blend
->need_src_alpha_4bit
&
1933 sctx
->framebuffer
.spi_shader_col_format_alpha
) |
1934 (~blend
->blend_enable_4bit
& ~blend
->need_src_alpha_4bit
&
1935 sctx
->framebuffer
.spi_shader_col_format
);
1936 key
->part
.ps
.epilog
.spi_shader_col_format
&= blend
->cb_target_enabled_4bit
;
1938 /* The output for dual source blending should have
1939 * the same format as the first output.
1941 if (blend
->dual_src_blend
) {
1942 key
->part
.ps
.epilog
.spi_shader_col_format
|=
1943 (key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) << 4;
1946 /* If alpha-to-coverage is enabled, we have to export alpha
1947 * even if there is no color buffer.
1949 if (!(key
->part
.ps
.epilog
.spi_shader_col_format
& 0xf) &&
1950 blend
->alpha_to_coverage
)
1951 key
->part
.ps
.epilog
.spi_shader_col_format
|= V_028710_SPI_SHADER_32_AR
;
1953 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1954 * to the range supported by the type if a channel has less
1955 * than 16 bits and the export format is 16_ABGR.
1957 if (sctx
->chip_class
<= GFX7
&& sctx
->family
!= CHIP_HAWAII
) {
1958 key
->part
.ps
.epilog
.color_is_int8
= sctx
->framebuffer
.color_is_int8
;
1959 key
->part
.ps
.epilog
.color_is_int10
= sctx
->framebuffer
.color_is_int10
;
1962 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1963 if (!key
->part
.ps
.epilog
.last_cbuf
) {
1964 key
->part
.ps
.epilog
.spi_shader_col_format
&= sel
->colors_written_4bit
;
1965 key
->part
.ps
.epilog
.color_is_int8
&= sel
->info
.colors_written
;
1966 key
->part
.ps
.epilog
.color_is_int10
&= sel
->info
.colors_written
;
1969 bool is_poly
= !util_prim_is_points_or_lines(sctx
->current_rast_prim
);
1970 bool is_line
= util_prim_is_lines(sctx
->current_rast_prim
);
1972 key
->part
.ps
.prolog
.color_two_side
= rs
->two_side
&& sel
->info
.colors_read
;
1973 key
->part
.ps
.prolog
.flatshade_colors
= rs
->flatshade
&& sel
->info
.colors_read
;
1975 key
->part
.ps
.epilog
.alpha_to_one
= blend
->alpha_to_one
&&
1976 rs
->multisample_enable
;
1978 key
->part
.ps
.prolog
.poly_stipple
= rs
->poly_stipple_enable
&& is_poly
;
1979 key
->part
.ps
.epilog
.poly_line_smoothing
= ((is_poly
&& rs
->poly_smooth
) ||
1980 (is_line
&& rs
->line_smooth
)) &&
1981 sctx
->framebuffer
.nr_samples
<= 1;
1982 key
->part
.ps
.epilog
.clamp_color
= rs
->clamp_fragment_color
;
1984 if (sctx
->ps_iter_samples
> 1 &&
1985 sel
->info
.reads_samplemask
) {
1986 key
->part
.ps
.prolog
.samplemask_log_ps_iter
=
1987 util_logbase2(sctx
->ps_iter_samples
);
1990 if (rs
->force_persample_interp
&&
1991 rs
->multisample_enable
&&
1992 sctx
->framebuffer
.nr_samples
> 1 &&
1993 sctx
->ps_iter_samples
> 1) {
1994 key
->part
.ps
.prolog
.force_persp_sample_interp
=
1995 sel
->info
.uses_persp_center
||
1996 sel
->info
.uses_persp_centroid
;
1998 key
->part
.ps
.prolog
.force_linear_sample_interp
=
1999 sel
->info
.uses_linear_center
||
2000 sel
->info
.uses_linear_centroid
;
2001 } else if (rs
->multisample_enable
&&
2002 sctx
->framebuffer
.nr_samples
> 1) {
2003 key
->part
.ps
.prolog
.bc_optimize_for_persp
=
2004 sel
->info
.uses_persp_center
&&
2005 sel
->info
.uses_persp_centroid
;
2006 key
->part
.ps
.prolog
.bc_optimize_for_linear
=
2007 sel
->info
.uses_linear_center
&&
2008 sel
->info
.uses_linear_centroid
;
2010 /* Make sure SPI doesn't compute more than 1 pair
2011 * of (i,j), which is the optimization here. */
2012 key
->part
.ps
.prolog
.force_persp_center_interp
=
2013 sel
->info
.uses_persp_center
+
2014 sel
->info
.uses_persp_centroid
+
2015 sel
->info
.uses_persp_sample
> 1;
2017 key
->part
.ps
.prolog
.force_linear_center_interp
=
2018 sel
->info
.uses_linear_center
+
2019 sel
->info
.uses_linear_centroid
+
2020 sel
->info
.uses_linear_sample
> 1;
2022 if (sel
->info
.uses_persp_opcode_interp_sample
||
2023 sel
->info
.uses_linear_opcode_interp_sample
)
2024 key
->mono
.u
.ps
.interpolate_at_sample_force_center
= 1;
2027 key
->part
.ps
.epilog
.alpha_func
= si_get_alpha_test_func(sctx
);
2029 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2030 if (sctx
->ps_uses_fbfetch
&& !sctx
->blitter
->running
) {
2031 struct pipe_surface
*cb0
= sctx
->framebuffer
.state
.cbufs
[0];
2032 struct pipe_resource
*tex
= cb0
->texture
;
2034 /* 1D textures are allocated and used as 2D on GFX9. */
2035 key
->mono
.u
.ps
.fbfetch_msaa
= sctx
->framebuffer
.nr_samples
> 1;
2036 key
->mono
.u
.ps
.fbfetch_is_1D
= sctx
->chip_class
!= GFX9
&&
2037 (tex
->target
== PIPE_TEXTURE_1D
||
2038 tex
->target
== PIPE_TEXTURE_1D_ARRAY
);
2039 key
->mono
.u
.ps
.fbfetch_layered
= tex
->target
== PIPE_TEXTURE_1D_ARRAY
||
2040 tex
->target
== PIPE_TEXTURE_2D_ARRAY
||
2041 tex
->target
== PIPE_TEXTURE_CUBE
||
2042 tex
->target
== PIPE_TEXTURE_CUBE_ARRAY
||
2043 tex
->target
== PIPE_TEXTURE_3D
;
2051 if (unlikely(sctx
->screen
->debug_flags
& DBG(NO_OPT_VARIANT
)))
2052 memset(&key
->opt
, 0, sizeof(key
->opt
));
2055 static void si_build_shader_variant(struct si_shader
*shader
,
2059 struct si_shader_selector
*sel
= shader
->selector
;
2060 struct si_screen
*sscreen
= sel
->screen
;
2061 struct ac_llvm_compiler
*compiler
;
2062 struct pipe_debug_callback
*debug
= &shader
->compiler_ctx_state
.debug
;
2064 if (thread_index
>= 0) {
2066 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler_lowp
));
2067 compiler
= &sscreen
->compiler_lowp
[thread_index
];
2069 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2070 compiler
= &sscreen
->compiler
[thread_index
];
2075 assert(!low_priority
);
2076 compiler
= shader
->compiler_ctx_state
.compiler
;
2079 if (unlikely(!si_shader_create(sscreen
, compiler
, shader
, debug
))) {
2080 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2082 shader
->compilation_failed
= true;
2086 if (shader
->compiler_ctx_state
.is_debug_context
) {
2087 FILE *f
= open_memstream(&shader
->shader_log
,
2088 &shader
->shader_log_size
);
2090 si_shader_dump(sscreen
, shader
, NULL
, f
, false);
2095 si_shader_init_pm4_state(sscreen
, shader
);
2098 static void si_build_shader_variant_low_priority(void *job
, int thread_index
)
2100 struct si_shader
*shader
= (struct si_shader
*)job
;
2102 assert(thread_index
>= 0);
2104 si_build_shader_variant(shader
, thread_index
, true);
2107 static const struct si_shader_key zeroed
;
2109 static bool si_check_missing_main_part(struct si_screen
*sscreen
,
2110 struct si_shader_selector
*sel
,
2111 struct si_compiler_ctx_state
*compiler_state
,
2112 struct si_shader_key
*key
)
2114 struct si_shader
**mainp
= si_get_main_shader_part(sel
, key
);
2117 struct si_shader
*main_part
= CALLOC_STRUCT(si_shader
);
2122 /* We can leave the fence as permanently signaled because the
2123 * main part becomes visible globally only after it has been
2125 util_queue_fence_init(&main_part
->ready
);
2127 main_part
->selector
= sel
;
2128 main_part
->key
.as_es
= key
->as_es
;
2129 main_part
->key
.as_ls
= key
->as_ls
;
2130 main_part
->key
.as_ngg
= key
->as_ngg
;
2131 main_part
->is_monolithic
= false;
2133 if (si_compile_tgsi_shader(sscreen
, compiler_state
->compiler
,
2134 main_part
, &compiler_state
->debug
) != 0) {
2144 * Select a shader variant according to the shader key.
2146 * \param optimized_or_none If the key describes an optimized shader variant and
2147 * the compilation isn't finished, don't select any
2148 * shader and return an error.
2150 int si_shader_select_with_key(struct si_screen
*sscreen
,
2151 struct si_shader_ctx_state
*state
,
2152 struct si_compiler_ctx_state
*compiler_state
,
2153 struct si_shader_key
*key
,
2155 bool optimized_or_none
)
2157 struct si_shader_selector
*sel
= state
->cso
;
2158 struct si_shader_selector
*previous_stage_sel
= NULL
;
2159 struct si_shader
*current
= state
->current
;
2160 struct si_shader
*iter
, *shader
= NULL
;
2163 /* Check if we don't need to change anything.
2164 * This path is also used for most shaders that don't need multiple
2165 * variants, it will cost just a computation of the key and this
2167 if (likely(current
&&
2168 memcmp(¤t
->key
, key
, sizeof(*key
)) == 0)) {
2169 if (unlikely(!util_queue_fence_is_signalled(¤t
->ready
))) {
2170 if (current
->is_optimized
) {
2171 if (optimized_or_none
)
2174 memset(&key
->opt
, 0, sizeof(key
->opt
));
2175 goto current_not_ready
;
2178 util_queue_fence_wait(¤t
->ready
);
2181 return current
->compilation_failed
? -1 : 0;
2185 /* This must be done before the mutex is locked, because async GS
2186 * compilation calls this function too, and therefore must enter
2189 * Only wait if we are in a draw call. Don't wait if we are
2190 * in a compiler thread.
2192 if (thread_index
< 0)
2193 util_queue_fence_wait(&sel
->ready
);
2195 mtx_lock(&sel
->mutex
);
2197 /* Find the shader variant. */
2198 for (iter
= sel
->first_variant
; iter
; iter
= iter
->next_variant
) {
2199 /* Don't check the "current" shader. We checked it above. */
2200 if (current
!= iter
&&
2201 memcmp(&iter
->key
, key
, sizeof(*key
)) == 0) {
2202 mtx_unlock(&sel
->mutex
);
2204 if (unlikely(!util_queue_fence_is_signalled(&iter
->ready
))) {
2205 /* If it's an optimized shader and its compilation has
2206 * been started but isn't done, use the unoptimized
2207 * shader so as not to cause a stall due to compilation.
2209 if (iter
->is_optimized
) {
2210 if (optimized_or_none
)
2212 memset(&key
->opt
, 0, sizeof(key
->opt
));
2216 util_queue_fence_wait(&iter
->ready
);
2219 if (iter
->compilation_failed
) {
2220 return -1; /* skip the draw call */
2223 state
->current
= iter
;
2228 /* Build a new shader. */
2229 shader
= CALLOC_STRUCT(si_shader
);
2231 mtx_unlock(&sel
->mutex
);
2235 util_queue_fence_init(&shader
->ready
);
2237 shader
->selector
= sel
;
2239 shader
->compiler_ctx_state
= *compiler_state
;
2241 /* If this is a merged shader, get the first shader's selector. */
2242 if (sscreen
->info
.chip_class
>= GFX9
) {
2243 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2244 previous_stage_sel
= key
->part
.tcs
.ls
;
2245 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2246 previous_stage_sel
= key
->part
.gs
.es
;
2248 /* We need to wait for the previous shader. */
2249 if (previous_stage_sel
&& thread_index
< 0)
2250 util_queue_fence_wait(&previous_stage_sel
->ready
);
2253 bool is_pure_monolithic
=
2254 sscreen
->use_monolithic_shaders
||
2255 memcmp(&key
->mono
, &zeroed
.mono
, sizeof(key
->mono
)) != 0;
2257 /* Compile the main shader part if it doesn't exist. This can happen
2258 * if the initial guess was wrong.
2260 * The prim discard CS doesn't need the main shader part.
2262 if (!is_pure_monolithic
&&
2263 !key
->opt
.vs_as_prim_discard_cs
) {
2266 /* Make sure the main shader part is present. This is needed
2267 * for shaders that can be compiled as VS, LS, or ES, and only
2268 * one of them is compiled at creation.
2270 * It is also needed for GS, which can be compiled as non-NGG
2273 * For merged shaders, check that the starting shader's main
2276 if (previous_stage_sel
) {
2277 struct si_shader_key shader1_key
= zeroed
;
2279 if (sel
->type
== PIPE_SHADER_TESS_CTRL
)
2280 shader1_key
.as_ls
= 1;
2281 else if (sel
->type
== PIPE_SHADER_GEOMETRY
)
2282 shader1_key
.as_es
= 1;
2286 if (sel
->type
== PIPE_SHADER_GEOMETRY
&&
2287 previous_stage_sel
->type
== PIPE_SHADER_TESS_EVAL
)
2288 shader1_key
.as_ngg
= key
->as_ngg
;
2290 mtx_lock(&previous_stage_sel
->mutex
);
2291 ok
= si_check_missing_main_part(sscreen
,
2293 compiler_state
, &shader1_key
);
2294 mtx_unlock(&previous_stage_sel
->mutex
);
2298 ok
= si_check_missing_main_part(sscreen
, sel
,
2299 compiler_state
, key
);
2304 mtx_unlock(&sel
->mutex
);
2305 return -ENOMEM
; /* skip the draw call */
2309 /* Keep the reference to the 1st shader of merged shaders, so that
2310 * Gallium can't destroy it before we destroy the 2nd shader.
2312 * Set sctx = NULL, because it's unused if we're not releasing
2313 * the shader, and we don't have any sctx here.
2315 si_shader_selector_reference(NULL
, &shader
->previous_stage_sel
,
2316 previous_stage_sel
);
2318 /* Monolithic-only shaders don't make a distinction between optimized
2319 * and unoptimized. */
2320 shader
->is_monolithic
=
2321 is_pure_monolithic
||
2322 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2324 /* The prim discard CS is always optimized. */
2325 shader
->is_optimized
=
2326 (!is_pure_monolithic
|| key
->opt
.vs_as_prim_discard_cs
) &&
2327 memcmp(&key
->opt
, &zeroed
.opt
, sizeof(key
->opt
)) != 0;
2329 /* If it's an optimized shader, compile it asynchronously. */
2330 if (shader
->is_optimized
&& thread_index
< 0) {
2331 /* Compile it asynchronously. */
2332 util_queue_add_job(&sscreen
->shader_compiler_queue_low_priority
,
2333 shader
, &shader
->ready
,
2334 si_build_shader_variant_low_priority
, NULL
);
2336 /* Add only after the ready fence was reset, to guard against a
2337 * race with si_bind_XX_shader. */
2338 if (!sel
->last_variant
) {
2339 sel
->first_variant
= shader
;
2340 sel
->last_variant
= shader
;
2342 sel
->last_variant
->next_variant
= shader
;
2343 sel
->last_variant
= shader
;
2346 /* Use the default (unoptimized) shader for now. */
2347 memset(&key
->opt
, 0, sizeof(key
->opt
));
2348 mtx_unlock(&sel
->mutex
);
2350 if (sscreen
->options
.sync_compile
)
2351 util_queue_fence_wait(&shader
->ready
);
2353 if (optimized_or_none
)
2358 /* Reset the fence before adding to the variant list. */
2359 util_queue_fence_reset(&shader
->ready
);
2361 if (!sel
->last_variant
) {
2362 sel
->first_variant
= shader
;
2363 sel
->last_variant
= shader
;
2365 sel
->last_variant
->next_variant
= shader
;
2366 sel
->last_variant
= shader
;
2369 mtx_unlock(&sel
->mutex
);
2371 assert(!shader
->is_optimized
);
2372 si_build_shader_variant(shader
, thread_index
, false);
2374 util_queue_fence_signal(&shader
->ready
);
2376 if (!shader
->compilation_failed
)
2377 state
->current
= shader
;
2379 return shader
->compilation_failed
? -1 : 0;
2382 static int si_shader_select(struct pipe_context
*ctx
,
2383 struct si_shader_ctx_state
*state
,
2384 union si_vgt_stages_key stages_key
,
2385 struct si_compiler_ctx_state
*compiler_state
)
2387 struct si_context
*sctx
= (struct si_context
*)ctx
;
2388 struct si_shader_key key
;
2390 si_shader_selector_key(ctx
, state
->cso
, stages_key
, &key
);
2391 return si_shader_select_with_key(sctx
->screen
, state
, compiler_state
,
2395 static void si_parse_next_shader_property(const struct tgsi_shader_info
*info
,
2397 struct si_shader_key
*key
)
2399 unsigned next_shader
= info
->properties
[TGSI_PROPERTY_NEXT_SHADER
];
2401 switch (info
->processor
) {
2402 case PIPE_SHADER_VERTEX
:
2403 switch (next_shader
) {
2404 case PIPE_SHADER_GEOMETRY
:
2407 case PIPE_SHADER_TESS_CTRL
:
2408 case PIPE_SHADER_TESS_EVAL
:
2412 /* If POSITION isn't written, it can only be a HW VS
2413 * if streamout is used. If streamout isn't used,
2414 * assume that it's a HW LS. (the next shader is TCS)
2415 * This heuristic is needed for separate shader objects.
2417 if (!info
->writes_position
&& !streamout
)
2422 case PIPE_SHADER_TESS_EVAL
:
2423 if (next_shader
== PIPE_SHADER_GEOMETRY
||
2424 !info
->writes_position
)
2431 * Compile the main shader part or the monolithic shader as part of
2432 * si_shader_selector initialization. Since it can be done asynchronously,
2433 * there is no way to report compile failures to applications.
2435 static void si_init_shader_selector_async(void *job
, int thread_index
)
2437 struct si_shader_selector
*sel
= (struct si_shader_selector
*)job
;
2438 struct si_screen
*sscreen
= sel
->screen
;
2439 struct ac_llvm_compiler
*compiler
;
2440 struct pipe_debug_callback
*debug
= &sel
->compiler_ctx_state
.debug
;
2442 assert(!debug
->debug_message
|| debug
->async
);
2443 assert(thread_index
>= 0);
2444 assert(thread_index
< ARRAY_SIZE(sscreen
->compiler
));
2445 compiler
= &sscreen
->compiler
[thread_index
];
2448 /* TODO: GS always sets wave size = default. Legacy GS will have
2449 * incorrect subgroup_size and ballot_bit_size. */
2450 si_lower_nir(sel
, si_get_wave_size(sscreen
, sel
->type
, true, false));
2453 /* Compile the main shader part for use with a prolog and/or epilog.
2454 * If this fails, the driver will try to compile a monolithic shader
2457 if (!sscreen
->use_monolithic_shaders
) {
2458 struct si_shader
*shader
= CALLOC_STRUCT(si_shader
);
2459 void *ir_binary
= NULL
;
2462 fprintf(stderr
, "radeonsi: can't allocate a main shader part\n");
2466 /* We can leave the fence signaled because use of the default
2467 * main part is guarded by the selector's ready fence. */
2468 util_queue_fence_init(&shader
->ready
);
2470 shader
->selector
= sel
;
2471 shader
->is_monolithic
= false;
2472 si_parse_next_shader_property(&sel
->info
,
2473 sel
->so
.num_outputs
!= 0,
2475 if (sscreen
->info
.chip_class
>= GFX10
&&
2476 ((sel
->type
== PIPE_SHADER_VERTEX
&&
2477 !shader
->key
.as_ls
&& !shader
->key
.as_es
) ||
2478 sel
->type
== PIPE_SHADER_TESS_EVAL
||
2479 sel
->type
== PIPE_SHADER_GEOMETRY
))
2480 shader
->key
.as_ngg
= 1;
2482 if (sel
->tokens
|| sel
->nir
)
2483 ir_binary
= si_get_ir_binary(sel
);
2485 /* Try to load the shader from the shader cache. */
2486 mtx_lock(&sscreen
->shader_cache_mutex
);
2489 si_shader_cache_load_shader(sscreen
, ir_binary
, shader
)) {
2490 mtx_unlock(&sscreen
->shader_cache_mutex
);
2491 si_shader_dump_stats_for_shader_db(sscreen
, shader
, debug
);
2493 mtx_unlock(&sscreen
->shader_cache_mutex
);
2495 /* Compile the shader if it hasn't been loaded from the cache. */
2496 if (si_compile_tgsi_shader(sscreen
, compiler
, shader
,
2500 fprintf(stderr
, "radeonsi: can't compile a main shader part\n");
2505 mtx_lock(&sscreen
->shader_cache_mutex
);
2506 if (!si_shader_cache_insert_shader(sscreen
, ir_binary
, shader
, true))
2508 mtx_unlock(&sscreen
->shader_cache_mutex
);
2512 *si_get_main_shader_part(sel
, &shader
->key
) = shader
;
2514 /* Unset "outputs_written" flags for outputs converted to
2515 * DEFAULT_VAL, so that later inter-shader optimizations don't
2516 * try to eliminate outputs that don't exist in the final
2519 * This is only done if non-monolithic shaders are enabled.
2521 if ((sel
->type
== PIPE_SHADER_VERTEX
||
2522 sel
->type
== PIPE_SHADER_TESS_EVAL
) &&
2523 !shader
->key
.as_ls
&&
2524 !shader
->key
.as_es
) {
2527 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2528 unsigned offset
= shader
->info
.vs_output_param_offset
[i
];
2530 if (offset
<= AC_EXP_PARAM_OFFSET_31
)
2533 unsigned name
= sel
->info
.output_semantic_name
[i
];
2534 unsigned index
= sel
->info
.output_semantic_index
[i
];
2538 case TGSI_SEMANTIC_GENERIC
:
2539 /* don't process indices the function can't handle */
2540 if (index
>= SI_MAX_IO_GENERIC
)
2544 id
= si_shader_io_get_unique_index(name
, index
, true);
2545 sel
->outputs_written_before_ps
&= ~(1ull << id
);
2547 case TGSI_SEMANTIC_POSITION
: /* ignore these */
2548 case TGSI_SEMANTIC_PSIZE
:
2549 case TGSI_SEMANTIC_CLIPVERTEX
:
2550 case TGSI_SEMANTIC_EDGEFLAG
:
2557 /* The GS copy shader is always pre-compiled. */
2558 if (sel
->type
== PIPE_SHADER_GEOMETRY
&&
2559 (sscreen
->info
.chip_class
<= GFX9
|| sel
->tess_turns_off_ngg
)) {
2560 sel
->gs_copy_shader
= si_generate_gs_copy_shader(sscreen
, compiler
, sel
, debug
);
2561 if (!sel
->gs_copy_shader
) {
2562 fprintf(stderr
, "radeonsi: can't create GS copy shader\n");
2566 si_shader_vs(sscreen
, sel
->gs_copy_shader
, sel
);
2570 void si_schedule_initial_compile(struct si_context
*sctx
, unsigned processor
,
2571 struct util_queue_fence
*ready_fence
,
2572 struct si_compiler_ctx_state
*compiler_ctx_state
,
2573 void *job
, util_queue_execute_func execute
)
2575 util_queue_fence_init(ready_fence
);
2577 struct util_async_debug_callback async_debug
;
2579 (sctx
->debug
.debug_message
&& !sctx
->debug
.async
) ||
2581 si_can_dump_shader(sctx
->screen
, processor
);
2584 u_async_debug_init(&async_debug
);
2585 compiler_ctx_state
->debug
= async_debug
.base
;
2588 util_queue_add_job(&sctx
->screen
->shader_compiler_queue
, job
,
2589 ready_fence
, execute
, NULL
);
2592 util_queue_fence_wait(ready_fence
);
2593 u_async_debug_drain(&async_debug
, &sctx
->debug
);
2594 u_async_debug_cleanup(&async_debug
);
2597 if (sctx
->screen
->options
.sync_compile
)
2598 util_queue_fence_wait(ready_fence
);
2601 /* Return descriptor slot usage masks from the given shader info. */
2602 void si_get_active_slot_masks(const struct tgsi_shader_info
*info
,
2603 uint32_t *const_and_shader_buffers
,
2604 uint64_t *samplers_and_images
)
2606 unsigned start
, num_shaderbufs
, num_constbufs
, num_images
, num_samplers
;
2608 num_shaderbufs
= util_last_bit(info
->shader_buffers_declared
);
2609 num_constbufs
= util_last_bit(info
->const_buffers_declared
);
2610 /* two 8-byte images share one 16-byte slot */
2611 num_images
= align(util_last_bit(info
->images_declared
), 2);
2612 num_samplers
= util_last_bit(info
->samplers_declared
);
2614 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2615 start
= si_get_shaderbuf_slot(num_shaderbufs
- 1);
2616 *const_and_shader_buffers
=
2617 u_bit_consecutive(start
, num_shaderbufs
+ num_constbufs
);
2619 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2620 start
= si_get_image_slot(num_images
- 1) / 2;
2621 *samplers_and_images
=
2622 u_bit_consecutive64(start
, num_images
/ 2 + num_samplers
);
2625 static void *si_create_shader_selector(struct pipe_context
*ctx
,
2626 const struct pipe_shader_state
*state
)
2628 struct si_screen
*sscreen
= (struct si_screen
*)ctx
->screen
;
2629 struct si_context
*sctx
= (struct si_context
*)ctx
;
2630 struct si_shader_selector
*sel
= CALLOC_STRUCT(si_shader_selector
);
2636 pipe_reference_init(&sel
->reference
, 1);
2637 sel
->screen
= sscreen
;
2638 sel
->compiler_ctx_state
.debug
= sctx
->debug
;
2639 sel
->compiler_ctx_state
.is_debug_context
= sctx
->is_debug
;
2641 sel
->so
= state
->stream_output
;
2643 if (state
->type
== PIPE_SHADER_IR_TGSI
&&
2644 !sscreen
->options
.always_nir
) {
2645 sel
->tokens
= tgsi_dup_tokens(state
->tokens
);
2651 tgsi_scan_shader(state
->tokens
, &sel
->info
);
2652 tgsi_scan_tess_ctrl(state
->tokens
, &sel
->info
, &sel
->tcs_info
);
2654 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2655 if (sel
->info
.uses_persp_opcode_interp_centroid
)
2656 sel
->info
.uses_persp_centroid
= true;
2658 if (sel
->info
.uses_linear_opcode_interp_centroid
)
2659 sel
->info
.uses_linear_centroid
= true;
2661 if (sel
->info
.uses_persp_opcode_interp_offset
||
2662 sel
->info
.uses_persp_opcode_interp_sample
)
2663 sel
->info
.uses_persp_center
= true;
2665 if (sel
->info
.uses_linear_opcode_interp_offset
||
2666 sel
->info
.uses_linear_opcode_interp_sample
)
2667 sel
->info
.uses_linear_center
= true;
2669 if (state
->type
== PIPE_SHADER_IR_TGSI
) {
2670 sel
->nir
= tgsi_to_nir(state
->tokens
, ctx
->screen
);
2672 assert(state
->type
== PIPE_SHADER_IR_NIR
);
2673 sel
->nir
= state
->ir
.nir
;
2676 si_nir_lower_ps_inputs(sel
->nir
);
2677 si_nir_opts(sel
->nir
);
2678 si_nir_scan_shader(sel
->nir
, &sel
->info
);
2679 si_nir_scan_tess_ctrl(sel
->nir
, &sel
->tcs_info
);
2682 sel
->type
= sel
->info
.processor
;
2683 p_atomic_inc(&sscreen
->num_shaders_created
);
2684 si_get_active_slot_masks(&sel
->info
,
2685 &sel
->active_const_and_shader_buffers
,
2686 &sel
->active_samplers_and_images
);
2688 /* Record which streamout buffers are enabled. */
2689 for (i
= 0; i
< sel
->so
.num_outputs
; i
++) {
2690 sel
->enabled_streamout_buffer_mask
|=
2691 (1 << sel
->so
.output
[i
].output_buffer
) <<
2692 (sel
->so
.output
[i
].stream
* 4);
2695 /* The prolog is a no-op if there are no inputs. */
2696 sel
->vs_needs_prolog
= sel
->type
== PIPE_SHADER_VERTEX
&&
2697 sel
->info
.num_inputs
&&
2698 !sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
];
2700 sel
->force_correct_derivs_after_kill
=
2701 sel
->type
== PIPE_SHADER_FRAGMENT
&&
2702 sel
->info
.uses_derivatives
&&
2703 sel
->info
.uses_kill
&&
2704 sctx
->screen
->debug_flags
& DBG(FS_CORRECT_DERIVS_AFTER_KILL
);
2706 sel
->prim_discard_cs_allowed
=
2707 sel
->type
== PIPE_SHADER_VERTEX
&&
2708 !sel
->info
.uses_bindless_images
&&
2709 !sel
->info
.uses_bindless_samplers
&&
2710 !sel
->info
.writes_memory
&&
2711 !sel
->info
.writes_viewport_index
&&
2712 !sel
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] &&
2713 !sel
->so
.num_outputs
;
2715 if (sel
->type
== PIPE_SHADER_VERTEX
&&
2716 sel
->info
.writes_edgeflag
) {
2717 if (sscreen
->info
.chip_class
>= GFX10
)
2718 sel
->ngg_writes_edgeflag
= true;
2720 sel
->pos_writes_edgeflag
= true;
2723 switch (sel
->type
) {
2724 case PIPE_SHADER_GEOMETRY
:
2725 sel
->gs_output_prim
=
2726 sel
->info
.properties
[TGSI_PROPERTY_GS_OUTPUT_PRIM
];
2728 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2729 sel
->rast_prim
= sel
->gs_output_prim
;
2730 if (util_rast_prim_is_triangles(sel
->rast_prim
))
2731 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2733 sel
->gs_max_out_vertices
=
2734 sel
->info
.properties
[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES
];
2735 sel
->gs_num_invocations
=
2736 sel
->info
.properties
[TGSI_PROPERTY_GS_INVOCATIONS
];
2737 sel
->gsvs_vertex_size
= sel
->info
.num_outputs
* 16;
2738 sel
->max_gsvs_emit_size
= sel
->gsvs_vertex_size
*
2739 sel
->gs_max_out_vertices
;
2741 sel
->max_gs_stream
= 0;
2742 for (i
= 0; i
< sel
->so
.num_outputs
; i
++)
2743 sel
->max_gs_stream
= MAX2(sel
->max_gs_stream
,
2744 sel
->so
.output
[i
].stream
);
2746 sel
->gs_input_verts_per_prim
=
2747 u_vertices_per_prim(sel
->info
.properties
[TGSI_PROPERTY_GS_INPUT_PRIM
]);
2749 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2750 sel
->tess_turns_off_ngg
=
2751 (sscreen
->info
.family
== CHIP_NAVI10
||
2752 sscreen
->info
.family
== CHIP_NAVI12
||
2753 sscreen
->info
.family
== CHIP_NAVI14
) &&
2754 sel
->gs_num_invocations
* sel
->gs_max_out_vertices
> 256;
2757 case PIPE_SHADER_TESS_CTRL
:
2758 /* Always reserve space for these. */
2759 sel
->patch_outputs_written
|=
2760 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER
, 0)) |
2761 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER
, 0));
2763 case PIPE_SHADER_VERTEX
:
2764 case PIPE_SHADER_TESS_EVAL
:
2765 for (i
= 0; i
< sel
->info
.num_outputs
; i
++) {
2766 unsigned name
= sel
->info
.output_semantic_name
[i
];
2767 unsigned index
= sel
->info
.output_semantic_index
[i
];
2770 case TGSI_SEMANTIC_TESSINNER
:
2771 case TGSI_SEMANTIC_TESSOUTER
:
2772 case TGSI_SEMANTIC_PATCH
:
2773 sel
->patch_outputs_written
|=
2774 1ull << si_shader_io_get_unique_index_patch(name
, index
);
2777 case TGSI_SEMANTIC_GENERIC
:
2778 /* don't process indices the function can't handle */
2779 if (index
>= SI_MAX_IO_GENERIC
)
2783 sel
->outputs_written
|=
2784 1ull << si_shader_io_get_unique_index(name
, index
, false);
2785 sel
->outputs_written_before_ps
|=
2786 1ull << si_shader_io_get_unique_index(name
, index
, true);
2788 case TGSI_SEMANTIC_EDGEFLAG
:
2792 sel
->esgs_itemsize
= util_last_bit64(sel
->outputs_written
) * 16;
2793 sel
->lshs_vertex_stride
= sel
->esgs_itemsize
;
2795 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2796 * will start on a different bank. (except for the maximum 32*16).
2798 if (sel
->lshs_vertex_stride
< 32*16)
2799 sel
->lshs_vertex_stride
+= 4;
2801 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2802 * conflicts, i.e. each vertex will start at a different bank.
2804 if (sctx
->chip_class
>= GFX9
)
2805 sel
->esgs_itemsize
+= 4;
2807 assert(((sel
->esgs_itemsize
/ 4) & C_028AAC_ITEMSIZE
) == 0);
2810 if (sel
->info
.properties
[TGSI_PROPERTY_TES_POINT_MODE
])
2811 sel
->rast_prim
= PIPE_PRIM_POINTS
;
2812 else if (sel
->info
.properties
[TGSI_PROPERTY_TES_PRIM_MODE
] == PIPE_PRIM_LINES
)
2813 sel
->rast_prim
= PIPE_PRIM_LINE_STRIP
;
2815 sel
->rast_prim
= PIPE_PRIM_TRIANGLES
;
2818 case PIPE_SHADER_FRAGMENT
:
2819 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2820 unsigned name
= sel
->info
.input_semantic_name
[i
];
2821 unsigned index
= sel
->info
.input_semantic_index
[i
];
2824 case TGSI_SEMANTIC_GENERIC
:
2825 /* don't process indices the function can't handle */
2826 if (index
>= SI_MAX_IO_GENERIC
)
2831 1ull << si_shader_io_get_unique_index(name
, index
, true);
2833 case TGSI_SEMANTIC_PCOORD
: /* ignore this */
2838 for (i
= 0; i
< 8; i
++)
2839 if (sel
->info
.colors_written
& (1 << i
))
2840 sel
->colors_written_4bit
|= 0xf << (4 * i
);
2842 for (i
= 0; i
< sel
->info
.num_inputs
; i
++) {
2843 if (sel
->info
.input_semantic_name
[i
] == TGSI_SEMANTIC_COLOR
) {
2844 int index
= sel
->info
.input_semantic_index
[i
];
2845 sel
->color_attr_index
[index
] = i
;
2852 /* PA_CL_VS_OUT_CNTL */
2854 sel
->info
.writes_psize
|| sel
->pos_writes_edgeflag
||
2855 sel
->info
.writes_layer
|| sel
->info
.writes_viewport_index
;
2856 sel
->pa_cl_vs_out_cntl
=
2857 S_02881C_USE_VTX_POINT_SIZE(sel
->info
.writes_psize
) |
2858 S_02881C_USE_VTX_EDGE_FLAG(sel
->pos_writes_edgeflag
) |
2859 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel
->info
.writes_layer
) |
2860 S_02881C_USE_VTX_VIEWPORT_INDX(sel
->info
.writes_viewport_index
) |
2861 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
2862 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
);
2863 sel
->clipdist_mask
= sel
->info
.writes_clipvertex
?
2864 SIX_BITS
: sel
->info
.clipdist_writemask
;
2865 sel
->culldist_mask
= sel
->info
.culldist_writemask
<<
2866 sel
->info
.num_written_clipdistance
;
2868 /* DB_SHADER_CONTROL */
2869 sel
->db_shader_control
=
2870 S_02880C_Z_EXPORT_ENABLE(sel
->info
.writes_z
) |
2871 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel
->info
.writes_stencil
) |
2872 S_02880C_MASK_EXPORT_ENABLE(sel
->info
.writes_samplemask
) |
2873 S_02880C_KILL_ENABLE(sel
->info
.uses_kill
);
2875 switch (sel
->info
.properties
[TGSI_PROPERTY_FS_DEPTH_LAYOUT
]) {
2876 case TGSI_FS_DEPTH_LAYOUT_GREATER
:
2877 sel
->db_shader_control
|=
2878 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z
);
2880 case TGSI_FS_DEPTH_LAYOUT_LESS
:
2881 sel
->db_shader_control
|=
2882 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z
);
2886 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2888 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2889 * --|-----------|------------|------------|--------------------|-------------------|-------------
2890 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2891 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2892 * 2 | false | true | n/a | LateZ | 1 | 0
2893 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2894 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2896 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2897 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2899 * Don't use ReZ without profiling !!!
2901 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2904 if (sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]) {
2906 sel
->db_shader_control
|= S_02880C_DEPTH_BEFORE_SHADER(1) |
2907 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
) |
2908 S_02880C_EXEC_ON_NOOP(sel
->info
.writes_memory
);
2909 } else if (sel
->info
.writes_memory
) {
2911 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_LATE_Z
) |
2912 S_02880C_EXEC_ON_HIER_FAIL(1);
2915 sel
->db_shader_control
|= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z
);
2918 if (sel
->info
.properties
[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE
])
2919 sel
->db_shader_control
|= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2921 (void) mtx_init(&sel
->mutex
, mtx_plain
);
2923 si_schedule_initial_compile(sctx
, sel
->info
.processor
, &sel
->ready
,
2924 &sel
->compiler_ctx_state
, sel
,
2925 si_init_shader_selector_async
);
2929 static void si_update_streamout_state(struct si_context
*sctx
)
2931 struct si_shader_selector
*shader_with_so
= si_get_vs(sctx
)->cso
;
2933 if (!shader_with_so
)
2936 sctx
->streamout
.enabled_stream_buffers_mask
=
2937 shader_with_so
->enabled_streamout_buffer_mask
;
2938 sctx
->streamout
.stride_in_dw
= shader_with_so
->so
.stride
;
2941 static void si_update_clip_regs(struct si_context
*sctx
,
2942 struct si_shader_selector
*old_hw_vs
,
2943 struct si_shader
*old_hw_vs_variant
,
2944 struct si_shader_selector
*next_hw_vs
,
2945 struct si_shader
*next_hw_vs_variant
)
2949 old_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] !=
2950 next_hw_vs
->info
.properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
] ||
2951 old_hw_vs
->pa_cl_vs_out_cntl
!= next_hw_vs
->pa_cl_vs_out_cntl
||
2952 old_hw_vs
->clipdist_mask
!= next_hw_vs
->clipdist_mask
||
2953 old_hw_vs
->culldist_mask
!= next_hw_vs
->culldist_mask
||
2954 !old_hw_vs_variant
||
2955 !next_hw_vs_variant
||
2956 old_hw_vs_variant
->key
.opt
.clip_disable
!=
2957 next_hw_vs_variant
->key
.opt
.clip_disable
))
2958 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
2961 static void si_update_common_shader_state(struct si_context
*sctx
)
2963 sctx
->uses_bindless_samplers
=
2964 si_shader_uses_bindless_samplers(sctx
->vs_shader
.cso
) ||
2965 si_shader_uses_bindless_samplers(sctx
->gs_shader
.cso
) ||
2966 si_shader_uses_bindless_samplers(sctx
->ps_shader
.cso
) ||
2967 si_shader_uses_bindless_samplers(sctx
->tcs_shader
.cso
) ||
2968 si_shader_uses_bindless_samplers(sctx
->tes_shader
.cso
);
2969 sctx
->uses_bindless_images
=
2970 si_shader_uses_bindless_images(sctx
->vs_shader
.cso
) ||
2971 si_shader_uses_bindless_images(sctx
->gs_shader
.cso
) ||
2972 si_shader_uses_bindless_images(sctx
->ps_shader
.cso
) ||
2973 si_shader_uses_bindless_images(sctx
->tcs_shader
.cso
) ||
2974 si_shader_uses_bindless_images(sctx
->tes_shader
.cso
);
2975 sctx
->do_update_shaders
= true;
2978 static void si_bind_vs_shader(struct pipe_context
*ctx
, void *state
)
2980 struct si_context
*sctx
= (struct si_context
*)ctx
;
2981 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
2982 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
2983 struct si_shader_selector
*sel
= state
;
2985 if (sctx
->vs_shader
.cso
== sel
)
2988 sctx
->vs_shader
.cso
= sel
;
2989 sctx
->vs_shader
.current
= sel
? sel
->first_variant
: NULL
;
2990 sctx
->num_vs_blit_sgprs
= sel
? sel
->info
.properties
[TGSI_PROPERTY_VS_BLIT_SGPRS
] : 0;
2992 si_update_common_shader_state(sctx
);
2993 si_update_vs_viewport_state(sctx
);
2994 si_set_active_descriptors_for_shader(sctx
, sel
);
2995 si_update_streamout_state(sctx
);
2996 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
2997 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3000 static void si_update_tess_uses_prim_id(struct si_context
*sctx
)
3002 sctx
->ia_multi_vgt_param_key
.u
.tess_uses_prim_id
=
3003 (sctx
->tes_shader
.cso
&&
3004 sctx
->tes_shader
.cso
->info
.uses_primid
) ||
3005 (sctx
->tcs_shader
.cso
&&
3006 sctx
->tcs_shader
.cso
->info
.uses_primid
) ||
3007 (sctx
->gs_shader
.cso
&&
3008 sctx
->gs_shader
.cso
->info
.uses_primid
) ||
3009 (sctx
->ps_shader
.cso
&& !sctx
->gs_shader
.cso
&&
3010 sctx
->ps_shader
.cso
->info
.uses_primid
);
3013 static bool si_update_ngg(struct si_context
*sctx
)
3015 if (sctx
->chip_class
<= GFX9
)
3018 bool new_ngg
= true;
3020 if (sctx
->gs_shader
.cso
&& sctx
->tes_shader
.cso
&&
3021 sctx
->gs_shader
.cso
->tess_turns_off_ngg
)
3024 if (new_ngg
!= sctx
->ngg
) {
3025 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3026 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3029 if ((sctx
->family
== CHIP_NAVI10
||
3030 sctx
->family
== CHIP_NAVI12
||
3031 sctx
->family
== CHIP_NAVI14
) &&
3033 sctx
->flags
|= SI_CONTEXT_VGT_FLUSH
;
3035 sctx
->ngg
= new_ngg
;
3036 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3042 static void si_bind_gs_shader(struct pipe_context
*ctx
, void *state
)
3044 struct si_context
*sctx
= (struct si_context
*)ctx
;
3045 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3046 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3047 struct si_shader_selector
*sel
= state
;
3048 bool enable_changed
= !!sctx
->gs_shader
.cso
!= !!sel
;
3051 if (sctx
->gs_shader
.cso
== sel
)
3054 sctx
->gs_shader
.cso
= sel
;
3055 sctx
->gs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3056 sctx
->ia_multi_vgt_param_key
.u
.uses_gs
= sel
!= NULL
;
3058 si_update_common_shader_state(sctx
);
3059 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3061 ngg_changed
= si_update_ngg(sctx
);
3062 if (ngg_changed
|| enable_changed
)
3063 si_shader_change_notify(sctx
);
3064 if (enable_changed
) {
3065 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3066 si_update_tess_uses_prim_id(sctx
);
3068 si_update_vs_viewport_state(sctx
);
3069 si_set_active_descriptors_for_shader(sctx
, sel
);
3070 si_update_streamout_state(sctx
);
3071 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3072 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3075 static void si_bind_tcs_shader(struct pipe_context
*ctx
, void *state
)
3077 struct si_context
*sctx
= (struct si_context
*)ctx
;
3078 struct si_shader_selector
*sel
= state
;
3079 bool enable_changed
= !!sctx
->tcs_shader
.cso
!= !!sel
;
3081 if (sctx
->tcs_shader
.cso
== sel
)
3084 sctx
->tcs_shader
.cso
= sel
;
3085 sctx
->tcs_shader
.current
= sel
? sel
->first_variant
: NULL
;
3086 si_update_tess_uses_prim_id(sctx
);
3088 si_update_common_shader_state(sctx
);
3091 sctx
->last_tcs
= NULL
; /* invalidate derived tess state */
3093 si_set_active_descriptors_for_shader(sctx
, sel
);
3096 static void si_bind_tes_shader(struct pipe_context
*ctx
, void *state
)
3098 struct si_context
*sctx
= (struct si_context
*)ctx
;
3099 struct si_shader_selector
*old_hw_vs
= si_get_vs(sctx
)->cso
;
3100 struct si_shader
*old_hw_vs_variant
= si_get_vs_state(sctx
);
3101 struct si_shader_selector
*sel
= state
;
3102 bool enable_changed
= !!sctx
->tes_shader
.cso
!= !!sel
;
3104 if (sctx
->tes_shader
.cso
== sel
)
3107 sctx
->tes_shader
.cso
= sel
;
3108 sctx
->tes_shader
.current
= sel
? sel
->first_variant
: NULL
;
3109 sctx
->ia_multi_vgt_param_key
.u
.uses_tess
= sel
!= NULL
;
3110 si_update_tess_uses_prim_id(sctx
);
3112 si_update_common_shader_state(sctx
);
3113 sctx
->last_rast_prim
= -1; /* reset this so that it gets updated */
3115 if (enable_changed
) {
3116 si_update_ngg(sctx
);
3117 si_shader_change_notify(sctx
);
3118 sctx
->last_tes_sh_base
= -1; /* invalidate derived tess state */
3120 si_update_vs_viewport_state(sctx
);
3121 si_set_active_descriptors_for_shader(sctx
, sel
);
3122 si_update_streamout_state(sctx
);
3123 si_update_clip_regs(sctx
, old_hw_vs
, old_hw_vs_variant
,
3124 si_get_vs(sctx
)->cso
, si_get_vs_state(sctx
));
3127 static void si_bind_ps_shader(struct pipe_context
*ctx
, void *state
)
3129 struct si_context
*sctx
= (struct si_context
*)ctx
;
3130 struct si_shader_selector
*old_sel
= sctx
->ps_shader
.cso
;
3131 struct si_shader_selector
*sel
= state
;
3133 /* skip if supplied shader is one already in use */
3137 sctx
->ps_shader
.cso
= sel
;
3138 sctx
->ps_shader
.current
= sel
? sel
->first_variant
: NULL
;
3140 si_update_common_shader_state(sctx
);
3142 if (sctx
->ia_multi_vgt_param_key
.u
.uses_tess
)
3143 si_update_tess_uses_prim_id(sctx
);
3146 old_sel
->info
.colors_written
!= sel
->info
.colors_written
)
3147 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
3149 if (sctx
->screen
->has_out_of_order_rast
&&
3151 old_sel
->info
.writes_memory
!= sel
->info
.writes_memory
||
3152 old_sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
] !=
3153 sel
->info
.properties
[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL
]))
3154 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
3156 si_set_active_descriptors_for_shader(sctx
, sel
);
3157 si_update_ps_colorbuf0_slot(sctx
);
3160 static void si_delete_shader(struct si_context
*sctx
, struct si_shader
*shader
)
3162 if (shader
->is_optimized
) {
3163 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue_low_priority
,
3167 util_queue_fence_destroy(&shader
->ready
);
3170 /* If destroyed shaders were not unbound, the next compiled
3171 * shader variant could get the same pointer address and so
3172 * binding it to the same shader stage would be considered
3173 * a no-op, causing random behavior.
3175 switch (shader
->selector
->type
) {
3176 case PIPE_SHADER_VERTEX
:
3177 if (shader
->key
.as_ls
) {
3178 assert(sctx
->chip_class
<= GFX8
);
3179 si_pm4_delete_state(sctx
, ls
, shader
->pm4
);
3180 } else if (shader
->key
.as_es
) {
3181 assert(sctx
->chip_class
<= GFX8
);
3182 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3183 } else if (shader
->key
.as_ngg
) {
3184 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3186 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3189 case PIPE_SHADER_TESS_CTRL
:
3190 si_pm4_delete_state(sctx
, hs
, shader
->pm4
);
3192 case PIPE_SHADER_TESS_EVAL
:
3193 if (shader
->key
.as_es
) {
3194 assert(sctx
->chip_class
<= GFX8
);
3195 si_pm4_delete_state(sctx
, es
, shader
->pm4
);
3196 } else if (shader
->key
.as_ngg
) {
3197 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3199 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3202 case PIPE_SHADER_GEOMETRY
:
3203 if (shader
->is_gs_copy_shader
)
3204 si_pm4_delete_state(sctx
, vs
, shader
->pm4
);
3206 si_pm4_delete_state(sctx
, gs
, shader
->pm4
);
3208 case PIPE_SHADER_FRAGMENT
:
3209 si_pm4_delete_state(sctx
, ps
, shader
->pm4
);
3215 si_shader_selector_reference(sctx
, &shader
->previous_stage_sel
, NULL
);
3216 si_shader_destroy(shader
);
3220 void si_destroy_shader_selector(struct si_context
*sctx
,
3221 struct si_shader_selector
*sel
)
3223 struct si_shader
*p
= sel
->first_variant
, *c
;
3224 struct si_shader_ctx_state
*current_shader
[SI_NUM_SHADERS
] = {
3225 [PIPE_SHADER_VERTEX
] = &sctx
->vs_shader
,
3226 [PIPE_SHADER_TESS_CTRL
] = &sctx
->tcs_shader
,
3227 [PIPE_SHADER_TESS_EVAL
] = &sctx
->tes_shader
,
3228 [PIPE_SHADER_GEOMETRY
] = &sctx
->gs_shader
,
3229 [PIPE_SHADER_FRAGMENT
] = &sctx
->ps_shader
,
3232 util_queue_drop_job(&sctx
->screen
->shader_compiler_queue
, &sel
->ready
);
3234 if (current_shader
[sel
->type
]->cso
== sel
) {
3235 current_shader
[sel
->type
]->cso
= NULL
;
3236 current_shader
[sel
->type
]->current
= NULL
;
3240 c
= p
->next_variant
;
3241 si_delete_shader(sctx
, p
);
3245 if (sel
->main_shader_part
)
3246 si_delete_shader(sctx
, sel
->main_shader_part
);
3247 if (sel
->main_shader_part_ls
)
3248 si_delete_shader(sctx
, sel
->main_shader_part_ls
);
3249 if (sel
->main_shader_part_es
)
3250 si_delete_shader(sctx
, sel
->main_shader_part_es
);
3251 if (sel
->main_shader_part_ngg
)
3252 si_delete_shader(sctx
, sel
->main_shader_part_ngg
);
3253 if (sel
->gs_copy_shader
)
3254 si_delete_shader(sctx
, sel
->gs_copy_shader
);
3256 util_queue_fence_destroy(&sel
->ready
);
3257 mtx_destroy(&sel
->mutex
);
3259 ralloc_free(sel
->nir
);
3263 static void si_delete_shader_selector(struct pipe_context
*ctx
, void *state
)
3265 struct si_context
*sctx
= (struct si_context
*)ctx
;
3266 struct si_shader_selector
*sel
= (struct si_shader_selector
*)state
;
3268 si_shader_selector_reference(sctx
, &sel
, NULL
);
3271 static unsigned si_get_ps_input_cntl(struct si_context
*sctx
,
3272 struct si_shader
*vs
, unsigned name
,
3273 unsigned index
, unsigned interpolate
)
3275 struct tgsi_shader_info
*vsinfo
= &vs
->selector
->info
;
3276 unsigned j
, offset
, ps_input_cntl
= 0;
3278 if (interpolate
== TGSI_INTERPOLATE_CONSTANT
||
3279 (interpolate
== TGSI_INTERPOLATE_COLOR
&& sctx
->flatshade
) ||
3280 name
== TGSI_SEMANTIC_PRIMID
)
3281 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
3283 if (name
== TGSI_SEMANTIC_PCOORD
||
3284 (name
== TGSI_SEMANTIC_TEXCOORD
&&
3285 sctx
->sprite_coord_enable
& (1 << index
))) {
3286 ps_input_cntl
|= S_028644_PT_SPRITE_TEX(1);
3289 for (j
= 0; j
< vsinfo
->num_outputs
; j
++) {
3290 if (name
== vsinfo
->output_semantic_name
[j
] &&
3291 index
== vsinfo
->output_semantic_index
[j
]) {
3292 offset
= vs
->info
.vs_output_param_offset
[j
];
3294 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
3295 /* The input is loaded from parameter memory. */
3296 ps_input_cntl
|= S_028644_OFFSET(offset
);
3297 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3298 if (offset
== AC_EXP_PARAM_UNDEFINED
) {
3299 /* This can happen with depth-only rendering. */
3302 /* The input is a DEFAULT_VAL constant. */
3303 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
3304 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
3305 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
3308 ps_input_cntl
= S_028644_OFFSET(0x20) |
3309 S_028644_DEFAULT_VAL(offset
);
3315 if (j
== vsinfo
->num_outputs
&& name
== TGSI_SEMANTIC_PRIMID
)
3316 /* PrimID is written after the last output when HW VS is used. */
3317 ps_input_cntl
|= S_028644_OFFSET(vs
->info
.vs_output_param_offset
[vsinfo
->num_outputs
]);
3318 else if (j
== vsinfo
->num_outputs
&& !G_028644_PT_SPRITE_TEX(ps_input_cntl
)) {
3319 /* No corresponding output found, load defaults into input.
3320 * Don't set any other bits.
3321 * (FLAT_SHADE=1 completely changes behavior) */
3322 ps_input_cntl
= S_028644_OFFSET(0x20);
3323 /* D3D 9 behaviour. GL is undefined */
3324 if (name
== TGSI_SEMANTIC_COLOR
&& index
== 0)
3325 ps_input_cntl
|= S_028644_DEFAULT_VAL(3);
3327 return ps_input_cntl
;
3330 static void si_emit_spi_map(struct si_context
*sctx
)
3332 struct si_shader
*ps
= sctx
->ps_shader
.current
;
3333 struct si_shader
*vs
= si_get_vs_state(sctx
);
3334 struct tgsi_shader_info
*psinfo
= ps
? &ps
->selector
->info
: NULL
;
3335 unsigned i
, num_interp
, num_written
= 0, bcol_interp
[2];
3336 unsigned spi_ps_input_cntl
[32];
3338 if (!ps
|| !ps
->selector
->info
.num_inputs
)
3341 num_interp
= si_get_ps_num_interp(ps
);
3342 assert(num_interp
> 0);
3344 for (i
= 0; i
< psinfo
->num_inputs
; i
++) {
3345 unsigned name
= psinfo
->input_semantic_name
[i
];
3346 unsigned index
= psinfo
->input_semantic_index
[i
];
3347 unsigned interpolate
= psinfo
->input_interpolate
[i
];
3349 spi_ps_input_cntl
[num_written
++] = si_get_ps_input_cntl(sctx
, vs
, name
,
3350 index
, interpolate
);
3352 if (name
== TGSI_SEMANTIC_COLOR
) {
3353 assert(index
< ARRAY_SIZE(bcol_interp
));
3354 bcol_interp
[index
] = interpolate
;
3358 if (ps
->key
.part
.ps
.prolog
.color_two_side
) {
3359 unsigned bcol
= TGSI_SEMANTIC_BCOLOR
;
3361 for (i
= 0; i
< 2; i
++) {
3362 if (!(psinfo
->colors_read
& (0xf << (i
* 4))))
3365 spi_ps_input_cntl
[num_written
++] =
3366 si_get_ps_input_cntl(sctx
, vs
, bcol
, i
, bcol_interp
[i
]);
3370 assert(num_interp
== num_written
);
3372 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3373 /* Dota 2: Only ~16% of SPI map updates set different values. */
3374 /* Talos: Only ~9% of SPI map updates set different values. */
3375 unsigned initial_cdw
= sctx
->gfx_cs
->current
.cdw
;
3376 radeon_opt_set_context_regn(sctx
, R_028644_SPI_PS_INPUT_CNTL_0
,
3378 sctx
->tracked_regs
.spi_ps_input_cntl
, num_interp
);
3380 if (initial_cdw
!= sctx
->gfx_cs
->current
.cdw
)
3381 sctx
->context_roll
= true;
3385 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3387 static void si_init_config_add_vgt_flush(struct si_context
*sctx
)
3389 if (sctx
->init_config_has_vgt_flush
)
3392 /* Done by Vulkan before VGT_FLUSH. */
3393 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3394 si_pm4_cmd_add(sctx
->init_config
,
3395 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH
) | EVENT_INDEX(4));
3396 si_pm4_cmd_end(sctx
->init_config
, false);
3398 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3399 si_pm4_cmd_begin(sctx
->init_config
, PKT3_EVENT_WRITE
);
3400 si_pm4_cmd_add(sctx
->init_config
, EVENT_TYPE(V_028A90_VGT_FLUSH
) | EVENT_INDEX(0));
3401 si_pm4_cmd_end(sctx
->init_config
, false);
3402 sctx
->init_config_has_vgt_flush
= true;
3405 /* Initialize state related to ESGS / GSVS ring buffers */
3406 static bool si_update_gs_ring_buffers(struct si_context
*sctx
)
3408 struct si_shader_selector
*es
=
3409 sctx
->tes_shader
.cso
? sctx
->tes_shader
.cso
: sctx
->vs_shader
.cso
;
3410 struct si_shader_selector
*gs
= sctx
->gs_shader
.cso
;
3411 struct si_pm4_state
*pm4
;
3413 /* Chip constants. */
3414 unsigned num_se
= sctx
->screen
->info
.max_se
;
3415 unsigned wave_size
= 64;
3416 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
3417 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3418 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3420 unsigned gs_vertex_reuse
= (sctx
->chip_class
>= GFX8
? 32 : 16) * num_se
;
3421 unsigned alignment
= 256 * num_se
;
3422 /* The maximum size is 63.999 MB per SE. */
3423 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
3425 /* Calculate the minimum size. */
3426 unsigned min_esgs_ring_size
= align(es
->esgs_itemsize
* gs_vertex_reuse
*
3427 wave_size
, alignment
);
3429 /* These are recommended sizes, not minimum sizes. */
3430 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
3431 es
->esgs_itemsize
* gs
->gs_input_verts_per_prim
;
3432 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
3433 gs
->max_gsvs_emit_size
;
3435 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
3436 esgs_ring_size
= align(esgs_ring_size
, alignment
);
3437 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
3439 esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
3440 gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
3442 /* Some rings don't have to be allocated if shaders don't use them.
3443 * (e.g. no varyings between ES and GS or GS and VS)
3445 * GFX9 doesn't have the ESGS ring.
3447 bool update_esgs
= sctx
->chip_class
<= GFX8
&&
3449 (!sctx
->esgs_ring
||
3450 sctx
->esgs_ring
->width0
< esgs_ring_size
);
3451 bool update_gsvs
= gsvs_ring_size
&&
3452 (!sctx
->gsvs_ring
||
3453 sctx
->gsvs_ring
->width0
< gsvs_ring_size
);
3455 if (!update_esgs
&& !update_gsvs
)
3459 pipe_resource_reference(&sctx
->esgs_ring
, NULL
);
3461 pipe_aligned_buffer_create(sctx
->b
.screen
,
3462 SI_RESOURCE_FLAG_UNMAPPABLE
,
3464 esgs_ring_size
, alignment
);
3465 if (!sctx
->esgs_ring
)
3470 pipe_resource_reference(&sctx
->gsvs_ring
, NULL
);
3472 pipe_aligned_buffer_create(sctx
->b
.screen
,
3473 SI_RESOURCE_FLAG_UNMAPPABLE
,
3475 gsvs_ring_size
, alignment
);
3476 if (!sctx
->gsvs_ring
)
3480 /* Create the "init_config_gs_rings" state. */
3481 pm4
= CALLOC_STRUCT(si_pm4_state
);
3485 if (sctx
->chip_class
>= GFX7
) {
3486 if (sctx
->esgs_ring
) {
3487 assert(sctx
->chip_class
<= GFX8
);
3488 si_pm4_set_reg(pm4
, R_030900_VGT_ESGS_RING_SIZE
,
3489 sctx
->esgs_ring
->width0
/ 256);
3491 if (sctx
->gsvs_ring
)
3492 si_pm4_set_reg(pm4
, R_030904_VGT_GSVS_RING_SIZE
,
3493 sctx
->gsvs_ring
->width0
/ 256);
3495 if (sctx
->esgs_ring
)
3496 si_pm4_set_reg(pm4
, R_0088C8_VGT_ESGS_RING_SIZE
,
3497 sctx
->esgs_ring
->width0
/ 256);
3498 if (sctx
->gsvs_ring
)
3499 si_pm4_set_reg(pm4
, R_0088CC_VGT_GSVS_RING_SIZE
,
3500 sctx
->gsvs_ring
->width0
/ 256);
3503 /* Set the state. */
3504 if (sctx
->init_config_gs_rings
)
3505 si_pm4_free_state(sctx
, sctx
->init_config_gs_rings
, ~0);
3506 sctx
->init_config_gs_rings
= pm4
;
3508 if (!sctx
->init_config_has_vgt_flush
) {
3509 si_init_config_add_vgt_flush(sctx
);
3510 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3513 /* Flush the context to re-emit both init_config states. */
3514 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3515 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3517 /* Set ring bindings. */
3518 if (sctx
->esgs_ring
) {
3519 assert(sctx
->chip_class
<= GFX8
);
3520 si_set_ring_buffer(sctx
, SI_ES_RING_ESGS
,
3521 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3522 true, true, 4, 64, 0);
3523 si_set_ring_buffer(sctx
, SI_GS_RING_ESGS
,
3524 sctx
->esgs_ring
, 0, sctx
->esgs_ring
->width0
,
3525 false, false, 0, 0, 0);
3527 if (sctx
->gsvs_ring
) {
3528 si_set_ring_buffer(sctx
, SI_RING_GSVS
,
3529 sctx
->gsvs_ring
, 0, sctx
->gsvs_ring
->width0
,
3530 false, false, 0, 0, 0);
3536 static void si_shader_lock(struct si_shader
*shader
)
3538 mtx_lock(&shader
->selector
->mutex
);
3539 if (shader
->previous_stage_sel
) {
3540 assert(shader
->previous_stage_sel
!= shader
->selector
);
3541 mtx_lock(&shader
->previous_stage_sel
->mutex
);
3545 static void si_shader_unlock(struct si_shader
*shader
)
3547 if (shader
->previous_stage_sel
)
3548 mtx_unlock(&shader
->previous_stage_sel
->mutex
);
3549 mtx_unlock(&shader
->selector
->mutex
);
3553 * @returns 1 if \p sel has been updated to use a new scratch buffer
3555 * < 0 if there was a failure
3557 static int si_update_scratch_buffer(struct si_context
*sctx
,
3558 struct si_shader
*shader
)
3560 uint64_t scratch_va
= sctx
->scratch_buffer
->gpu_address
;
3565 /* This shader doesn't need a scratch buffer */
3566 if (shader
->config
.scratch_bytes_per_wave
== 0)
3569 /* Prevent race conditions when updating:
3570 * - si_shader::scratch_bo
3571 * - si_shader::binary::code
3572 * - si_shader::previous_stage::binary::code.
3574 si_shader_lock(shader
);
3576 /* This shader is already configured to use the current
3577 * scratch buffer. */
3578 if (shader
->scratch_bo
== sctx
->scratch_buffer
) {
3579 si_shader_unlock(shader
);
3583 assert(sctx
->scratch_buffer
);
3585 /* Replace the shader bo with a new bo that has the relocs applied. */
3586 if (!si_shader_binary_upload(sctx
->screen
, shader
, scratch_va
)) {
3587 si_shader_unlock(shader
);
3591 /* Update the shader state to use the new shader bo. */
3592 si_shader_init_pm4_state(sctx
->screen
, shader
);
3594 si_resource_reference(&shader
->scratch_bo
, sctx
->scratch_buffer
);
3596 si_shader_unlock(shader
);
3600 static unsigned si_get_current_scratch_buffer_size(struct si_context
*sctx
)
3602 return sctx
->scratch_buffer
? sctx
->scratch_buffer
->b
.b
.width0
: 0;
3605 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader
*shader
)
3607 return shader
? shader
->config
.scratch_bytes_per_wave
: 0;
3610 static struct si_shader
*si_get_tcs_current(struct si_context
*sctx
)
3612 if (!sctx
->tes_shader
.cso
)
3613 return NULL
; /* tessellation disabled */
3615 return sctx
->tcs_shader
.cso
? sctx
->tcs_shader
.current
:
3616 sctx
->fixed_func_tcs_shader
.current
;
3619 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context
*sctx
)
3623 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->ps_shader
.current
));
3624 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->gs_shader
.current
));
3625 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->vs_shader
.current
));
3626 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(sctx
->tes_shader
.current
));
3628 if (sctx
->tes_shader
.cso
) {
3629 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3631 bytes
= MAX2(bytes
, si_get_scratch_buffer_bytes_per_wave(tcs
));
3636 static bool si_update_scratch_relocs(struct si_context
*sctx
)
3638 struct si_shader
*tcs
= si_get_tcs_current(sctx
);
3641 /* Update the shaders, so that they are using the latest scratch.
3642 * The scratch buffer may have been changed since these shaders were
3643 * last used, so we still need to try to update them, even if they
3644 * require scratch buffers smaller than the current size.
3646 r
= si_update_scratch_buffer(sctx
, sctx
->ps_shader
.current
);
3650 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3652 r
= si_update_scratch_buffer(sctx
, sctx
->gs_shader
.current
);
3656 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3658 r
= si_update_scratch_buffer(sctx
, tcs
);
3662 si_pm4_bind_state(sctx
, hs
, tcs
->pm4
);
3664 /* VS can be bound as LS, ES, or VS. */
3665 r
= si_update_scratch_buffer(sctx
, sctx
->vs_shader
.current
);
3669 if (sctx
->vs_shader
.current
->key
.as_ls
)
3670 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3671 else if (sctx
->vs_shader
.current
->key
.as_es
)
3672 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3673 else if (sctx
->vs_shader
.current
->key
.as_ngg
)
3674 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3676 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3679 /* TES can be bound as ES or VS. */
3680 r
= si_update_scratch_buffer(sctx
, sctx
->tes_shader
.current
);
3684 if (sctx
->tes_shader
.current
->key
.as_es
)
3685 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3686 else if (sctx
->tes_shader
.current
->key
.as_ngg
)
3687 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3689 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3695 static bool si_update_spi_tmpring_size(struct si_context
*sctx
)
3697 unsigned current_scratch_buffer_size
=
3698 si_get_current_scratch_buffer_size(sctx
);
3699 unsigned scratch_bytes_per_wave
=
3700 si_get_max_scratch_bytes_per_wave(sctx
);
3701 unsigned scratch_needed_size
= scratch_bytes_per_wave
*
3702 sctx
->scratch_waves
;
3703 unsigned spi_tmpring_size
;
3705 if (scratch_needed_size
> 0) {
3706 if (scratch_needed_size
> current_scratch_buffer_size
) {
3707 /* Create a bigger scratch buffer */
3708 si_resource_reference(&sctx
->scratch_buffer
, NULL
);
3710 sctx
->scratch_buffer
=
3711 si_aligned_buffer_create(&sctx
->screen
->b
,
3712 SI_RESOURCE_FLAG_UNMAPPABLE
,
3714 scratch_needed_size
, 256);
3715 if (!sctx
->scratch_buffer
)
3718 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3719 si_context_add_resource_size(sctx
,
3720 &sctx
->scratch_buffer
->b
.b
);
3723 if (!si_update_scratch_relocs(sctx
))
3727 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3728 assert((scratch_needed_size
& ~0x3FF) == scratch_needed_size
&&
3729 "scratch size should already be aligned correctly.");
3731 spi_tmpring_size
= S_0286E8_WAVES(sctx
->scratch_waves
) |
3732 S_0286E8_WAVESIZE(scratch_bytes_per_wave
>> 10);
3733 if (spi_tmpring_size
!= sctx
->spi_tmpring_size
) {
3734 sctx
->spi_tmpring_size
= spi_tmpring_size
;
3735 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.scratch_state
);
3740 static void si_init_tess_factor_ring(struct si_context
*sctx
)
3742 assert(!sctx
->tess_rings
);
3744 /* The address must be aligned to 2^19, because the shader only
3745 * receives the high 13 bits.
3747 sctx
->tess_rings
= pipe_aligned_buffer_create(sctx
->b
.screen
,
3748 SI_RESOURCE_FLAG_32BIT
,
3750 sctx
->screen
->tess_offchip_ring_size
+
3751 sctx
->screen
->tess_factor_ring_size
,
3753 if (!sctx
->tess_rings
)
3756 si_init_config_add_vgt_flush(sctx
);
3758 si_pm4_add_bo(sctx
->init_config
, si_resource(sctx
->tess_rings
),
3759 RADEON_USAGE_READWRITE
, RADEON_PRIO_SHADER_RINGS
);
3761 uint64_t factor_va
= si_resource(sctx
->tess_rings
)->gpu_address
+
3762 sctx
->screen
->tess_offchip_ring_size
;
3764 /* Append these registers to the init config state. */
3765 if (sctx
->chip_class
>= GFX7
) {
3766 si_pm4_set_reg(sctx
->init_config
, R_030938_VGT_TF_RING_SIZE
,
3767 S_030938_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3768 si_pm4_set_reg(sctx
->init_config
, R_030940_VGT_TF_MEMORY_BASE
,
3770 if (sctx
->chip_class
>= GFX10
)
3771 si_pm4_set_reg(sctx
->init_config
, R_030984_VGT_TF_MEMORY_BASE_HI_UMD
,
3772 S_030984_BASE_HI(factor_va
>> 40));
3773 else if (sctx
->chip_class
== GFX9
)
3774 si_pm4_set_reg(sctx
->init_config
, R_030944_VGT_TF_MEMORY_BASE_HI
,
3775 S_030944_BASE_HI(factor_va
>> 40));
3776 si_pm4_set_reg(sctx
->init_config
, R_03093C_VGT_HS_OFFCHIP_PARAM
,
3777 sctx
->screen
->vgt_hs_offchip_param
);
3779 si_pm4_set_reg(sctx
->init_config
, R_008988_VGT_TF_RING_SIZE
,
3780 S_008988_SIZE(sctx
->screen
->tess_factor_ring_size
/ 4));
3781 si_pm4_set_reg(sctx
->init_config
, R_0089B8_VGT_TF_MEMORY_BASE
,
3783 si_pm4_set_reg(sctx
->init_config
, R_0089B0_VGT_HS_OFFCHIP_PARAM
,
3784 sctx
->screen
->vgt_hs_offchip_param
);
3787 /* Flush the context to re-emit the init_config state.
3788 * This is done only once in a lifetime of a context.
3790 si_pm4_upload_indirect_buffer(sctx
, sctx
->init_config
);
3791 sctx
->initial_gfx_cs_size
= 0; /* force flush */
3792 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
3795 static struct si_pm4_state
*si_build_vgt_shader_config(struct si_screen
*screen
,
3796 union si_vgt_stages_key key
)
3798 struct si_pm4_state
*pm4
= CALLOC_STRUCT(si_pm4_state
);
3799 uint32_t stages
= 0;
3802 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
3803 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3806 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
3809 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
3811 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
3812 } else if (key
.u
.gs
) {
3813 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
3815 } else if (key
.u
.ngg
) {
3816 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
3820 stages
|= S_028B54_PRIMGEN_EN(1);
3821 if (key
.u
.streamout
)
3822 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
3823 } else if (key
.u
.gs
)
3824 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
3826 if (screen
->info
.chip_class
>= GFX9
)
3827 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3829 if (screen
->info
.chip_class
>= GFX10
&& screen
->ge_wave_size
== 32) {
3830 stages
|= S_028B54_HS_W32_EN(1) |
3831 S_028B54_GS_W32_EN(key
.u
.ngg
) | /* legacy GS only supports Wave64 */
3832 S_028B54_VS_W32_EN(1);
3835 si_pm4_set_reg(pm4
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
3839 static void si_update_vgt_shader_config(struct si_context
*sctx
,
3840 union si_vgt_stages_key key
)
3842 struct si_pm4_state
**pm4
= &sctx
->vgt_shader_config
[key
.index
];
3844 if (unlikely(!*pm4
))
3845 *pm4
= si_build_vgt_shader_config(sctx
->screen
, key
);
3846 si_pm4_bind_state(sctx
, vgt_shader_config
, *pm4
);
3849 bool si_update_shaders(struct si_context
*sctx
)
3851 struct pipe_context
*ctx
= (struct pipe_context
*)sctx
;
3852 struct si_compiler_ctx_state compiler_state
;
3853 struct si_state_rasterizer
*rs
= sctx
->queued
.named
.rasterizer
;
3854 struct si_shader
*old_vs
= si_get_vs_state(sctx
);
3855 bool old_clip_disable
= old_vs
? old_vs
->key
.opt
.clip_disable
: false;
3856 struct si_shader
*old_ps
= sctx
->ps_shader
.current
;
3857 union si_vgt_stages_key key
;
3858 unsigned old_spi_shader_col_format
=
3859 old_ps
? old_ps
->key
.part
.ps
.epilog
.spi_shader_col_format
: 0;
3862 compiler_state
.compiler
= &sctx
->compiler
;
3863 compiler_state
.debug
= sctx
->debug
;
3864 compiler_state
.is_debug_context
= sctx
->is_debug
;
3868 if (sctx
->tes_shader
.cso
)
3870 if (sctx
->gs_shader
.cso
)
3875 key
.u
.streamout
= !!si_get_vs(sctx
)->cso
->so
.num_outputs
;
3878 /* Update TCS and TES. */
3879 if (sctx
->tes_shader
.cso
) {
3880 if (!sctx
->tess_rings
) {
3881 si_init_tess_factor_ring(sctx
);
3882 if (!sctx
->tess_rings
)
3886 if (sctx
->tcs_shader
.cso
) {
3887 r
= si_shader_select(ctx
, &sctx
->tcs_shader
, key
,
3891 si_pm4_bind_state(sctx
, hs
, sctx
->tcs_shader
.current
->pm4
);
3893 if (!sctx
->fixed_func_tcs_shader
.cso
) {
3894 sctx
->fixed_func_tcs_shader
.cso
=
3895 si_create_fixed_func_tcs(sctx
);
3896 if (!sctx
->fixed_func_tcs_shader
.cso
)
3900 r
= si_shader_select(ctx
, &sctx
->fixed_func_tcs_shader
,
3901 key
, &compiler_state
);
3904 si_pm4_bind_state(sctx
, hs
,
3905 sctx
->fixed_func_tcs_shader
.current
->pm4
);
3908 if (!sctx
->gs_shader
.cso
|| sctx
->chip_class
<= GFX8
) {
3909 r
= si_shader_select(ctx
, &sctx
->tes_shader
, key
, &compiler_state
);
3913 if (sctx
->gs_shader
.cso
) {
3915 assert(sctx
->chip_class
<= GFX8
);
3916 si_pm4_bind_state(sctx
, es
, sctx
->tes_shader
.current
->pm4
);
3917 } else if (key
.u
.ngg
) {
3918 si_pm4_bind_state(sctx
, gs
, sctx
->tes_shader
.current
->pm4
);
3920 si_pm4_bind_state(sctx
, vs
, sctx
->tes_shader
.current
->pm4
);
3924 if (sctx
->chip_class
<= GFX8
)
3925 si_pm4_bind_state(sctx
, ls
, NULL
);
3926 si_pm4_bind_state(sctx
, hs
, NULL
);
3930 if (sctx
->gs_shader
.cso
) {
3931 r
= si_shader_select(ctx
, &sctx
->gs_shader
, key
, &compiler_state
);
3934 si_pm4_bind_state(sctx
, gs
, sctx
->gs_shader
.current
->pm4
);
3936 si_pm4_bind_state(sctx
, vs
, sctx
->gs_shader
.cso
->gs_copy_shader
->pm4
);
3938 if (!si_update_gs_ring_buffers(sctx
))
3941 si_pm4_bind_state(sctx
, vs
, NULL
);
3945 si_pm4_bind_state(sctx
, gs
, NULL
);
3946 if (sctx
->chip_class
<= GFX8
)
3947 si_pm4_bind_state(sctx
, es
, NULL
);
3952 if ((!key
.u
.tess
&& !key
.u
.gs
) || sctx
->chip_class
<= GFX8
) {
3953 r
= si_shader_select(ctx
, &sctx
->vs_shader
, key
, &compiler_state
);
3957 if (!key
.u
.tess
&& !key
.u
.gs
) {
3959 si_pm4_bind_state(sctx
, gs
, sctx
->vs_shader
.current
->pm4
);
3960 si_pm4_bind_state(sctx
, vs
, NULL
);
3962 si_pm4_bind_state(sctx
, vs
, sctx
->vs_shader
.current
->pm4
);
3964 } else if (sctx
->tes_shader
.cso
) {
3965 si_pm4_bind_state(sctx
, ls
, sctx
->vs_shader
.current
->pm4
);
3967 assert(sctx
->gs_shader
.cso
);
3968 si_pm4_bind_state(sctx
, es
, sctx
->vs_shader
.current
->pm4
);
3972 si_update_vgt_shader_config(sctx
, key
);
3974 if (old_clip_disable
!= si_get_vs_state(sctx
)->key
.opt
.clip_disable
)
3975 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.clip_regs
);
3977 if (sctx
->ps_shader
.cso
) {
3978 unsigned db_shader_control
;
3980 r
= si_shader_select(ctx
, &sctx
->ps_shader
, key
, &compiler_state
);
3983 si_pm4_bind_state(sctx
, ps
, sctx
->ps_shader
.current
->pm4
);
3986 sctx
->ps_shader
.cso
->db_shader_control
|
3987 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx
) != PIPE_FUNC_ALWAYS
);
3989 if (si_pm4_state_changed(sctx
, ps
) ||
3990 si_pm4_state_changed(sctx
, vs
) ||
3991 (key
.u
.ngg
&& si_pm4_state_changed(sctx
, gs
)) ||
3992 sctx
->sprite_coord_enable
!= rs
->sprite_coord_enable
||
3993 sctx
->flatshade
!= rs
->flatshade
) {
3994 sctx
->sprite_coord_enable
= rs
->sprite_coord_enable
;
3995 sctx
->flatshade
= rs
->flatshade
;
3996 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.spi_map
);
3999 if (sctx
->screen
->rbplus_allowed
&&
4000 si_pm4_state_changed(sctx
, ps
) &&
4002 old_spi_shader_col_format
!=
4003 sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.spi_shader_col_format
))
4004 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.cb_render_state
);
4006 if (sctx
->ps_db_shader_control
!= db_shader_control
) {
4007 sctx
->ps_db_shader_control
= db_shader_control
;
4008 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4009 if (sctx
->screen
->dpbb_allowed
)
4010 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.dpbb_state
);
4013 if (sctx
->smoothing_enabled
!= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
) {
4014 sctx
->smoothing_enabled
= sctx
->ps_shader
.current
->key
.part
.ps
.epilog
.poly_line_smoothing
;
4015 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_config
);
4017 if (sctx
->chip_class
== GFX6
)
4018 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.db_render_state
);
4020 if (sctx
->framebuffer
.nr_samples
<= 1)
4021 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.msaa_sample_locs
);
4025 if (si_pm4_state_enabled_and_changed(sctx
, ls
) ||
4026 si_pm4_state_enabled_and_changed(sctx
, hs
) ||
4027 si_pm4_state_enabled_and_changed(sctx
, es
) ||
4028 si_pm4_state_enabled_and_changed(sctx
, gs
) ||
4029 si_pm4_state_enabled_and_changed(sctx
, vs
) ||
4030 si_pm4_state_enabled_and_changed(sctx
, ps
)) {
4031 if (!si_update_spi_tmpring_size(sctx
))
4035 if (sctx
->chip_class
>= GFX7
) {
4036 if (si_pm4_state_enabled_and_changed(sctx
, ls
))
4037 sctx
->prefetch_L2_mask
|= SI_PREFETCH_LS
;
4038 else if (!sctx
->queued
.named
.ls
)
4039 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_LS
;
4041 if (si_pm4_state_enabled_and_changed(sctx
, hs
))
4042 sctx
->prefetch_L2_mask
|= SI_PREFETCH_HS
;
4043 else if (!sctx
->queued
.named
.hs
)
4044 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_HS
;
4046 if (si_pm4_state_enabled_and_changed(sctx
, es
))
4047 sctx
->prefetch_L2_mask
|= SI_PREFETCH_ES
;
4048 else if (!sctx
->queued
.named
.es
)
4049 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_ES
;
4051 if (si_pm4_state_enabled_and_changed(sctx
, gs
))
4052 sctx
->prefetch_L2_mask
|= SI_PREFETCH_GS
;
4053 else if (!sctx
->queued
.named
.gs
)
4054 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_GS
;
4056 if (si_pm4_state_enabled_and_changed(sctx
, vs
))
4057 sctx
->prefetch_L2_mask
|= SI_PREFETCH_VS
;
4058 else if (!sctx
->queued
.named
.vs
)
4059 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_VS
;
4061 if (si_pm4_state_enabled_and_changed(sctx
, ps
))
4062 sctx
->prefetch_L2_mask
|= SI_PREFETCH_PS
;
4063 else if (!sctx
->queued
.named
.ps
)
4064 sctx
->prefetch_L2_mask
&= ~SI_PREFETCH_PS
;
4067 sctx
->do_update_shaders
= false;
4071 static void si_emit_scratch_state(struct si_context
*sctx
)
4073 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
4075 radeon_set_context_reg(cs
, R_0286E8_SPI_TMPRING_SIZE
,
4076 sctx
->spi_tmpring_size
);
4078 if (sctx
->scratch_buffer
) {
4079 radeon_add_to_buffer_list(sctx
, sctx
->gfx_cs
,
4080 sctx
->scratch_buffer
, RADEON_USAGE_READWRITE
,
4081 RADEON_PRIO_SCRATCH_BUFFER
);
4085 void si_init_shader_functions(struct si_context
*sctx
)
4087 sctx
->atoms
.s
.spi_map
.emit
= si_emit_spi_map
;
4088 sctx
->atoms
.s
.scratch_state
.emit
= si_emit_scratch_state
;
4090 sctx
->b
.create_vs_state
= si_create_shader_selector
;
4091 sctx
->b
.create_tcs_state
= si_create_shader_selector
;
4092 sctx
->b
.create_tes_state
= si_create_shader_selector
;
4093 sctx
->b
.create_gs_state
= si_create_shader_selector
;
4094 sctx
->b
.create_fs_state
= si_create_shader_selector
;
4096 sctx
->b
.bind_vs_state
= si_bind_vs_shader
;
4097 sctx
->b
.bind_tcs_state
= si_bind_tcs_shader
;
4098 sctx
->b
.bind_tes_state
= si_bind_tes_shader
;
4099 sctx
->b
.bind_gs_state
= si_bind_gs_shader
;
4100 sctx
->b
.bind_fs_state
= si_bind_ps_shader
;
4102 sctx
->b
.delete_vs_state
= si_delete_shader_selector
;
4103 sctx
->b
.delete_tcs_state
= si_delete_shader_selector
;
4104 sctx
->b
.delete_tes_state
= si_delete_shader_selector
;
4105 sctx
->b
.delete_gs_state
= si_delete_shader_selector
;
4106 sctx
->b
.delete_fs_state
= si_delete_shader_selector
;