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radeonsi/gfx10: enable NGG passthrough for eligible shaders
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR key for the shader cache.
46 */
47 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
48 unsigned char ir_sha1_cache_key[20])
49 {
50 struct blob blob = {};
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else if (sel->nir_binary) {
59 ir_binary = sel->nir_binary;
60 ir_size = sel->nir_size;
61 } else {
62 assert(sel->nir);
63
64 blob_init(&blob);
65 nir_serialize(&blob, sel->nir, true);
66 ir_binary = blob.data;
67 ir_size = blob.size;
68 }
69
70 /* These settings affect the compilation, but they are not derived
71 * from the input shader IR.
72 */
73 unsigned shader_variant_flags = 0;
74
75 if (ngg)
76 shader_variant_flags |= 1 << 0;
77 if (sel->nir)
78 shader_variant_flags |= 1 << 1;
79 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
80 shader_variant_flags |= 1 << 2;
81 if (sel->force_correct_derivs_after_kill)
82 shader_variant_flags |= 1 << 3;
83
84 struct mesa_sha1 ctx;
85 _mesa_sha1_init(&ctx);
86 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
87 _mesa_sha1_update(&ctx, ir_binary, ir_size);
88 if (sel->type == PIPE_SHADER_VERTEX ||
89 sel->type == PIPE_SHADER_TESS_EVAL ||
90 sel->type == PIPE_SHADER_GEOMETRY)
91 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
92 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
93
94 if (ir_binary == blob.data)
95 blob_finish(&blob);
96 }
97
98 /** Copy "data" to "ptr" and return the next dword following copied data. */
99 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
100 {
101 /* data may be NULL if size == 0 */
102 if (size)
103 memcpy(ptr, data, size);
104 ptr += DIV_ROUND_UP(size, 4);
105 return ptr;
106 }
107
108 /** Read data from "ptr". Return the next dword following the data. */
109 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
110 {
111 memcpy(data, ptr, size);
112 ptr += DIV_ROUND_UP(size, 4);
113 return ptr;
114 }
115
116 /**
117 * Write the size as uint followed by the data. Return the next dword
118 * following the copied data.
119 */
120 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
121 {
122 *ptr++ = size;
123 return write_data(ptr, data, size);
124 }
125
126 /**
127 * Read the size as uint followed by the data. Return both via parameters.
128 * Return the next dword following the data.
129 */
130 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
131 {
132 *size = *ptr++;
133 assert(*data == NULL);
134 if (!*size)
135 return ptr;
136 *data = malloc(*size);
137 return read_data(ptr, *data, *size);
138 }
139
140 /**
141 * Return the shader binary in a buffer. The first 4 bytes contain its size
142 * as integer.
143 */
144 static void *si_get_shader_binary(struct si_shader *shader)
145 {
146 /* There is always a size of data followed by the data itself. */
147 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
148 strlen(shader->binary.llvm_ir_string) + 1 : 0;
149
150 /* Refuse to allocate overly large buffers and guard against integer
151 * overflow. */
152 if (shader->binary.elf_size > UINT_MAX / 4 ||
153 llvm_ir_size > UINT_MAX / 4)
154 return NULL;
155
156 unsigned size =
157 4 + /* total size */
158 4 + /* CRC32 of the data below */
159 align(sizeof(shader->config), 4) +
160 align(sizeof(shader->info), 4) +
161 4 + align(shader->binary.elf_size, 4) +
162 4 + align(llvm_ir_size, 4);
163 void *buffer = CALLOC(1, size);
164 uint32_t *ptr = (uint32_t*)buffer;
165
166 if (!buffer)
167 return NULL;
168
169 *ptr++ = size;
170 ptr++; /* CRC32 is calculated at the end. */
171
172 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
173 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
174 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
175 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
176 assert((char *)ptr - (char *)buffer == size);
177
178 /* Compute CRC32. */
179 ptr = (uint32_t*)buffer;
180 ptr++;
181 *ptr = util_hash_crc32(ptr + 1, size - 8);
182
183 return buffer;
184 }
185
186 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
187 {
188 uint32_t *ptr = (uint32_t*)binary;
189 uint32_t size = *ptr++;
190 uint32_t crc32 = *ptr++;
191 unsigned chunk_size;
192 unsigned elf_size;
193
194 if (util_hash_crc32(ptr, size - 8) != crc32) {
195 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
196 return false;
197 }
198
199 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
200 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
201 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
202 &elf_size);
203 shader->binary.elf_size = elf_size;
204 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
205
206 return true;
207 }
208
209 /**
210 * Insert a shader into the cache. It's assumed the shader is not in the cache.
211 * Use si_shader_cache_load_shader before calling this.
212 */
213 void si_shader_cache_insert_shader(struct si_screen *sscreen,
214 unsigned char ir_sha1_cache_key[20],
215 struct si_shader *shader,
216 bool insert_into_disk_cache)
217 {
218 void *hw_binary;
219 struct hash_entry *entry;
220 uint8_t key[CACHE_KEY_SIZE];
221
222 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
223 if (entry)
224 return; /* already added */
225
226 hw_binary = si_get_shader_binary(shader);
227 if (!hw_binary)
228 return;
229
230 if (_mesa_hash_table_insert(sscreen->shader_cache,
231 mem_dup(ir_sha1_cache_key, 20),
232 hw_binary) == NULL) {
233 FREE(hw_binary);
234 return;
235 }
236
237 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
238 disk_cache_compute_key(sscreen->disk_shader_cache,
239 ir_sha1_cache_key, 20, key);
240 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
241 *((uint32_t *) hw_binary), NULL);
242 }
243 }
244
245 bool si_shader_cache_load_shader(struct si_screen *sscreen,
246 unsigned char ir_sha1_cache_key[20],
247 struct si_shader *shader)
248 {
249 struct hash_entry *entry =
250 _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
251 if (!entry) {
252 if (sscreen->disk_shader_cache) {
253 unsigned char sha1[CACHE_KEY_SIZE];
254
255 disk_cache_compute_key(sscreen->disk_shader_cache,
256 ir_sha1_cache_key, 20, sha1);
257
258 size_t binary_size;
259 uint8_t *buffer =
260 disk_cache_get(sscreen->disk_shader_cache,
261 sha1, &binary_size);
262 if (!buffer)
263 return false;
264
265 if (binary_size < sizeof(uint32_t) ||
266 *((uint32_t*)buffer) != binary_size) {
267 /* Something has gone wrong discard the item
268 * from the cache and rebuild/link from
269 * source.
270 */
271 assert(!"Invalid radeonsi shader disk cache "
272 "item!");
273
274 disk_cache_remove(sscreen->disk_shader_cache,
275 sha1);
276 free(buffer);
277
278 return false;
279 }
280
281 if (!si_load_shader_binary(shader, buffer)) {
282 free(buffer);
283 return false;
284 }
285 free(buffer);
286
287 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
288 shader, false);
289 } else {
290 return false;
291 }
292 } else {
293 if (!si_load_shader_binary(shader, entry->data))
294 return false;
295 }
296 p_atomic_inc(&sscreen->num_shader_cache_hits);
297 return true;
298 }
299
300 static uint32_t si_shader_cache_key_hash(const void *key)
301 {
302 /* Take the first dword of SHA1. */
303 return *(uint32_t*)key;
304 }
305
306 static bool si_shader_cache_key_equals(const void *a, const void *b)
307 {
308 /* Compare SHA1s. */
309 return memcmp(a, b, 20) == 0;
310 }
311
312 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
313 {
314 FREE((void*)entry->key);
315 FREE(entry->data);
316 }
317
318 bool si_init_shader_cache(struct si_screen *sscreen)
319 {
320 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
321 sscreen->shader_cache =
322 _mesa_hash_table_create(NULL,
323 si_shader_cache_key_hash,
324 si_shader_cache_key_equals);
325
326 return sscreen->shader_cache != NULL;
327 }
328
329 void si_destroy_shader_cache(struct si_screen *sscreen)
330 {
331 if (sscreen->shader_cache)
332 _mesa_hash_table_destroy(sscreen->shader_cache,
333 si_destroy_shader_cache_entry);
334 simple_mtx_destroy(&sscreen->shader_cache_mutex);
335 }
336
337 /* SHADER STATES */
338
339 static void si_set_tesseval_regs(struct si_screen *sscreen,
340 const struct si_shader_selector *tes,
341 struct si_pm4_state *pm4)
342 {
343 const struct tgsi_shader_info *info = &tes->info;
344 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
345 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
346 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
347 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
348 unsigned type, partitioning, topology, distribution_mode;
349
350 switch (tes_prim_mode) {
351 case PIPE_PRIM_LINES:
352 type = V_028B6C_TESS_ISOLINE;
353 break;
354 case PIPE_PRIM_TRIANGLES:
355 type = V_028B6C_TESS_TRIANGLE;
356 break;
357 case PIPE_PRIM_QUADS:
358 type = V_028B6C_TESS_QUAD;
359 break;
360 default:
361 assert(0);
362 return;
363 }
364
365 switch (tes_spacing) {
366 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
367 partitioning = V_028B6C_PART_FRAC_ODD;
368 break;
369 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
370 partitioning = V_028B6C_PART_FRAC_EVEN;
371 break;
372 case PIPE_TESS_SPACING_EQUAL:
373 partitioning = V_028B6C_PART_INTEGER;
374 break;
375 default:
376 assert(0);
377 return;
378 }
379
380 if (tes_point_mode)
381 topology = V_028B6C_OUTPUT_POINT;
382 else if (tes_prim_mode == PIPE_PRIM_LINES)
383 topology = V_028B6C_OUTPUT_LINE;
384 else if (tes_vertex_order_cw)
385 /* for some reason, this must be the other way around */
386 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
387 else
388 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
389
390 if (sscreen->info.has_distributed_tess) {
391 if (sscreen->info.family == CHIP_FIJI ||
392 sscreen->info.family >= CHIP_POLARIS10)
393 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
394 else
395 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
396 } else
397 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
398
399 assert(pm4->shader);
400 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
401 S_028B6C_PARTITIONING(partitioning) |
402 S_028B6C_TOPOLOGY(topology) |
403 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
404 }
405
406 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
407 * whether the "fractional odd" tessellation spacing is used.
408 *
409 * Possible VGT configurations and which state should set the register:
410 *
411 * Reg set in | VGT shader configuration | Value
412 * ------------------------------------------------------
413 * VS as VS | VS | 30
414 * VS as ES | ES -> GS -> VS | 30
415 * TES as VS | LS -> HS -> VS | 14 or 30
416 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
417 *
418 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
419 */
420 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
421 struct si_shader_selector *sel,
422 struct si_shader *shader,
423 struct si_pm4_state *pm4)
424 {
425 unsigned type = sel->type;
426
427 if (sscreen->info.family < CHIP_POLARIS10 ||
428 sscreen->info.chip_class >= GFX10)
429 return;
430
431 /* VS as VS, or VS as ES: */
432 if ((type == PIPE_SHADER_VERTEX &&
433 (!shader ||
434 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
435 /* TES as VS, or TES as ES: */
436 type == PIPE_SHADER_TESS_EVAL) {
437 unsigned vtx_reuse_depth = 30;
438
439 if (type == PIPE_SHADER_TESS_EVAL &&
440 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
441 PIPE_TESS_SPACING_FRACTIONAL_ODD)
442 vtx_reuse_depth = 14;
443
444 assert(pm4->shader);
445 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
446 }
447 }
448
449 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
450 {
451 if (shader->pm4)
452 si_pm4_clear_state(shader->pm4);
453 else
454 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
455
456 if (shader->pm4) {
457 shader->pm4->shader = shader;
458 return shader->pm4;
459 } else {
460 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
461 return NULL;
462 }
463 }
464
465 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
466 {
467 /* Add the pointer to VBO descriptors. */
468 return num_always_on_user_sgprs + 1;
469 }
470
471 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
472 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
473 struct si_shader *shader, bool legacy_vs_prim_id)
474 {
475 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
476 (shader->previous_stage_sel &&
477 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
478
479 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
480 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
481 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
482 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
483 */
484 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
485
486 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
487 return 3;
488 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
489 return 2;
490 else if (is_ls || shader->info.uses_instanceid)
491 return 1;
492 else
493 return 0;
494 }
495
496 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
497 {
498 struct si_pm4_state *pm4;
499 uint64_t va;
500
501 assert(sscreen->info.chip_class <= GFX8);
502
503 pm4 = si_get_shader_pm4_state(shader);
504 if (!pm4)
505 return;
506
507 va = shader->bo->gpu_address;
508 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
509
510 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
511 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
512
513 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
514 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
515 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
516 S_00B528_DX10_CLAMP(1) |
517 S_00B528_FLOAT_MODE(shader->config.float_mode);
518 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
519 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
520 }
521
522 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
523 {
524 struct si_pm4_state *pm4;
525 uint64_t va;
526
527 pm4 = si_get_shader_pm4_state(shader);
528 if (!pm4)
529 return;
530
531 va = shader->bo->gpu_address;
532 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
533
534 if (sscreen->info.chip_class >= GFX9) {
535 if (sscreen->info.chip_class >= GFX10) {
536 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
537 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
538 } else {
539 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
540 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
541 }
542
543 unsigned num_user_sgprs =
544 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
545
546 shader->config.rsrc2 =
547 S_00B42C_USER_SGPR(num_user_sgprs) |
548 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
549
550 if (sscreen->info.chip_class >= GFX10)
551 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
552 else
553 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
554 } else {
555 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
556 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
557
558 shader->config.rsrc2 =
559 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
560 S_00B42C_OC_LDS_EN(1) |
561 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
562 }
563
564 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
565 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
566 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
567 (sscreen->info.chip_class <= GFX9 ?
568 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
569 S_00B428_DX10_CLAMP(1) |
570 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
571 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
572 S_00B428_FLOAT_MODE(shader->config.float_mode) |
573 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
574 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
575
576 if (sscreen->info.chip_class <= GFX8) {
577 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
578 shader->config.rsrc2);
579 }
580 }
581
582 static void si_emit_shader_es(struct si_context *sctx)
583 {
584 struct si_shader *shader = sctx->queued.named.es->shader;
585 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
586
587 if (!shader)
588 return;
589
590 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
591 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
592 shader->selector->esgs_itemsize / 4);
593
594 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
595 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
596 SI_TRACKED_VGT_TF_PARAM,
597 shader->vgt_tf_param);
598
599 if (shader->vgt_vertex_reuse_block_cntl)
600 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
601 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
602 shader->vgt_vertex_reuse_block_cntl);
603
604 if (initial_cdw != sctx->gfx_cs->current.cdw)
605 sctx->context_roll = true;
606 }
607
608 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
609 {
610 struct si_pm4_state *pm4;
611 unsigned num_user_sgprs;
612 unsigned vgpr_comp_cnt;
613 uint64_t va;
614 unsigned oc_lds_en;
615
616 assert(sscreen->info.chip_class <= GFX8);
617
618 pm4 = si_get_shader_pm4_state(shader);
619 if (!pm4)
620 return;
621
622 pm4->atom.emit = si_emit_shader_es;
623 va = shader->bo->gpu_address;
624 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
625
626 if (shader->selector->type == PIPE_SHADER_VERTEX) {
627 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
628 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
629 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
630 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
631 num_user_sgprs = SI_TES_NUM_USER_SGPR;
632 } else
633 unreachable("invalid shader selector type");
634
635 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
636
637 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
638 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
639 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
640 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
641 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
642 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
643 S_00B328_DX10_CLAMP(1) |
644 S_00B328_FLOAT_MODE(shader->config.float_mode));
645 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
646 S_00B32C_USER_SGPR(num_user_sgprs) |
647 S_00B32C_OC_LDS_EN(oc_lds_en) |
648 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
649
650 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
651 si_set_tesseval_regs(sscreen, shader->selector, pm4);
652
653 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
654 }
655
656 void gfx9_get_gs_info(struct si_shader_selector *es,
657 struct si_shader_selector *gs,
658 struct gfx9_gs_info *out)
659 {
660 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
661 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
662 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
663 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
664
665 /* All these are in dwords: */
666 /* We can't allow using the whole LDS, because GS waves compete with
667 * other shader stages for LDS space. */
668 const unsigned max_lds_size = 8 * 1024;
669 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
670 unsigned esgs_lds_size;
671
672 /* All these are per subgroup: */
673 const unsigned max_out_prims = 32 * 1024;
674 const unsigned max_es_verts = 255;
675 const unsigned ideal_gs_prims = 64;
676 unsigned max_gs_prims, gs_prims;
677 unsigned min_es_verts, es_verts, worst_case_es_verts;
678
679 if (uses_adjacency || gs_num_invocations > 1)
680 max_gs_prims = 127 / gs_num_invocations;
681 else
682 max_gs_prims = 255;
683
684 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
685 * Make sure we don't go over the maximum value.
686 */
687 if (gs->gs_max_out_vertices > 0) {
688 max_gs_prims = MIN2(max_gs_prims,
689 max_out_prims /
690 (gs->gs_max_out_vertices * gs_num_invocations));
691 }
692 assert(max_gs_prims > 0);
693
694 /* If the primitive has adjacency, halve the number of vertices
695 * that will be reused in multiple primitives.
696 */
697 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
698
699 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
700 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
701
702 /* Compute ESGS LDS size based on the worst case number of ES vertices
703 * needed to create the target number of GS prims per subgroup.
704 */
705 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
706
707 /* If total LDS usage is too big, refactor partitions based on ratio
708 * of ESGS item sizes.
709 */
710 if (esgs_lds_size > max_lds_size) {
711 /* Our target GS Prims Per Subgroup was too large. Calculate
712 * the maximum number of GS Prims Per Subgroup that will fit
713 * into LDS, capped by the maximum that the hardware can support.
714 */
715 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
716 max_gs_prims);
717 assert(gs_prims > 0);
718 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
719 max_es_verts);
720
721 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
722 assert(esgs_lds_size <= max_lds_size);
723 }
724
725 /* Now calculate remaining ESGS information. */
726 if (esgs_lds_size)
727 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
728 else
729 es_verts = max_es_verts;
730
731 /* Vertices for adjacency primitives are not always reused, so restore
732 * it for ES_VERTS_PER_SUBGRP.
733 */
734 min_es_verts = gs->gs_input_verts_per_prim;
735
736 /* For normal primitives, the VGT only checks if they are past the ES
737 * verts per subgroup after allocating a full GS primitive and if they
738 * are, kick off a new subgroup. But if those additional ES verts are
739 * unique (e.g. not reused) we need to make sure there is enough LDS
740 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
741 */
742 es_verts -= min_es_verts - 1;
743
744 out->es_verts_per_subgroup = es_verts;
745 out->gs_prims_per_subgroup = gs_prims;
746 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
747 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
748 gs->gs_max_out_vertices;
749 out->esgs_ring_size = 4 * esgs_lds_size;
750
751 assert(out->max_prims_per_subgroup <= max_out_prims);
752 }
753
754 static void si_emit_shader_gs(struct si_context *sctx)
755 {
756 struct si_shader *shader = sctx->queued.named.gs->shader;
757 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
758
759 if (!shader)
760 return;
761
762 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
763 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
764 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
765 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
766 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
767 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
768 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
769
770 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
771 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
772 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
773 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
774
775 /* R_028B38_VGT_GS_MAX_VERT_OUT */
776 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
777 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
778 shader->ctx_reg.gs.vgt_gs_max_vert_out);
779
780 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
781 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
782 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
783 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
784 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
785 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
786 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
787 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
788
789 /* R_028B90_VGT_GS_INSTANCE_CNT */
790 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
791 SI_TRACKED_VGT_GS_INSTANCE_CNT,
792 shader->ctx_reg.gs.vgt_gs_instance_cnt);
793
794 if (sctx->chip_class >= GFX9) {
795 /* R_028A44_VGT_GS_ONCHIP_CNTL */
796 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
797 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
798 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
799 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
800 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
801 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
802 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
803 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
804 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
805 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
806 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
807
808 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
809 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
810 SI_TRACKED_VGT_TF_PARAM,
811 shader->vgt_tf_param);
812 if (shader->vgt_vertex_reuse_block_cntl)
813 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
814 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
815 shader->vgt_vertex_reuse_block_cntl);
816 }
817
818 if (initial_cdw != sctx->gfx_cs->current.cdw)
819 sctx->context_roll = true;
820 }
821
822 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
823 {
824 struct si_shader_selector *sel = shader->selector;
825 const ubyte *num_components = sel->info.num_stream_output_components;
826 unsigned gs_num_invocations = sel->gs_num_invocations;
827 struct si_pm4_state *pm4;
828 uint64_t va;
829 unsigned max_stream = sel->max_gs_stream;
830 unsigned offset;
831
832 pm4 = si_get_shader_pm4_state(shader);
833 if (!pm4)
834 return;
835
836 pm4->atom.emit = si_emit_shader_gs;
837
838 offset = num_components[0] * sel->gs_max_out_vertices;
839 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
840
841 if (max_stream >= 1)
842 offset += num_components[1] * sel->gs_max_out_vertices;
843 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
844
845 if (max_stream >= 2)
846 offset += num_components[2] * sel->gs_max_out_vertices;
847 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
848
849 if (max_stream >= 3)
850 offset += num_components[3] * sel->gs_max_out_vertices;
851 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
852
853 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
854 assert(offset < (1 << 15));
855
856 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
857
858 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
859 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
860 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
861 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
862
863 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
864 S_028B90_ENABLE(gs_num_invocations > 0);
865
866 va = shader->bo->gpu_address;
867 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
868
869 if (sscreen->info.chip_class >= GFX9) {
870 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
871 unsigned es_type = shader->key.part.gs.es->type;
872 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
873
874 if (es_type == PIPE_SHADER_VERTEX) {
875 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
876 } else if (es_type == PIPE_SHADER_TESS_EVAL)
877 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
878 else
879 unreachable("invalid shader selector type");
880
881 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
882 * VGPR[0:4] are always loaded.
883 */
884 if (sel->info.uses_invocationid)
885 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
886 else if (sel->info.uses_primid)
887 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
888 else if (input_prim >= PIPE_PRIM_TRIANGLES)
889 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
890 else
891 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
892
893 unsigned num_user_sgprs;
894 if (es_type == PIPE_SHADER_VERTEX)
895 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
896 else
897 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
898
899 if (sscreen->info.chip_class >= GFX10) {
900 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
901 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
902 } else {
903 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
904 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
905 }
906
907 uint32_t rsrc1 =
908 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
909 S_00B228_DX10_CLAMP(1) |
910 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
911 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
912 S_00B228_FLOAT_MODE(shader->config.float_mode) |
913 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
914 uint32_t rsrc2 =
915 S_00B22C_USER_SGPR(num_user_sgprs) |
916 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
917 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
918 S_00B22C_LDS_SIZE(shader->config.lds_size) |
919 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
920
921 if (sscreen->info.chip_class >= GFX10) {
922 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
923 } else {
924 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
925 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
926 }
927
928 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
929 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
930
931 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
932 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
933 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
934 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
935 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
936 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
937 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
938 shader->key.part.gs.es->esgs_itemsize / 4;
939
940 if (es_type == PIPE_SHADER_TESS_EVAL)
941 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
942
943 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
944 NULL, pm4);
945 } else {
946 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
947 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
948
949 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
950 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
951 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
952 S_00B228_DX10_CLAMP(1) |
953 S_00B228_FLOAT_MODE(shader->config.float_mode));
954 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
955 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
956 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
957 }
958 }
959
960 /* Common tail code for NGG primitive shaders. */
961 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
962 struct si_shader *shader,
963 unsigned initial_cdw)
964 {
965 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
966 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
967 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
968 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
969 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
970 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
971 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
972 SI_TRACKED_VGT_PRIMITIVEID_EN,
973 shader->ctx_reg.ngg.vgt_primitiveid_en);
974 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
975 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
976 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
977 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
978 SI_TRACKED_VGT_GS_INSTANCE_CNT,
979 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
980 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
981 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
982 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
983 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
984 SI_TRACKED_SPI_VS_OUT_CONFIG,
985 shader->ctx_reg.ngg.spi_vs_out_config);
986 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
987 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
988 shader->ctx_reg.ngg.spi_shader_idx_format,
989 shader->ctx_reg.ngg.spi_shader_pos_format);
990 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
991 SI_TRACKED_PA_CL_VTE_CNTL,
992 shader->ctx_reg.ngg.pa_cl_vte_cntl);
993 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
994 SI_TRACKED_PA_CL_NGG_CNTL,
995 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
996
997 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
998 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
999 shader->pa_cl_vs_out_cntl,
1000 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1001
1002 if (initial_cdw != sctx->gfx_cs->current.cdw)
1003 sctx->context_roll = true;
1004 }
1005
1006 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1007 {
1008 struct si_shader *shader = sctx->queued.named.gs->shader;
1009 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1010
1011 if (!shader)
1012 return;
1013
1014 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1015 }
1016
1017 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1018 {
1019 struct si_shader *shader = sctx->queued.named.gs->shader;
1020 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1021
1022 if (!shader)
1023 return;
1024
1025 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1026 SI_TRACKED_VGT_TF_PARAM,
1027 shader->vgt_tf_param);
1028
1029 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1030 }
1031
1032 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1033 {
1034 struct si_shader *shader = sctx->queued.named.gs->shader;
1035 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1036
1037 if (!shader)
1038 return;
1039
1040 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1041 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1042 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1043
1044 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1045 }
1046
1047 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1048 {
1049 struct si_shader *shader = sctx->queued.named.gs->shader;
1050 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1051
1052 if (!shader)
1053 return;
1054
1055 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1056 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1057 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1058 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1059 SI_TRACKED_VGT_TF_PARAM,
1060 shader->vgt_tf_param);
1061
1062 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1063 }
1064
1065 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1066 {
1067 if (gs->type == PIPE_SHADER_GEOMETRY)
1068 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1069
1070 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1071 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1072 return PIPE_PRIM_POINTS;
1073 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1074 return PIPE_PRIM_LINES;
1075 return PIPE_PRIM_TRIANGLES;
1076 }
1077
1078 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1079 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1080 }
1081
1082 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1083 {
1084 bool misc_vec_ena =
1085 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1086 sel->info.writes_layer || sel->info.writes_viewport_index;
1087 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1088 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1089 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1090 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1091 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1092 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1093 }
1094
1095 /**
1096 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1097 * in NGG mode.
1098 */
1099 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1100 {
1101 const struct si_shader_selector *gs_sel = shader->selector;
1102 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1103 enum pipe_shader_type gs_type = shader->selector->type;
1104 const struct si_shader_selector *es_sel =
1105 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1106 const struct tgsi_shader_info *es_info = &es_sel->info;
1107 enum pipe_shader_type es_type = es_sel->type;
1108 unsigned num_user_sgprs;
1109 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1110 uint64_t va;
1111 unsigned window_space =
1112 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1113 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1114 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1115 unsigned input_prim = si_get_input_prim(gs_sel);
1116 bool break_wave_at_eoi = false;
1117 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1118 if (!pm4)
1119 return;
1120
1121 if (es_type == PIPE_SHADER_TESS_EVAL) {
1122 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1123 : gfx10_emit_shader_ngg_tess_nogs;
1124 } else {
1125 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1126 : gfx10_emit_shader_ngg_notess_nogs;
1127 }
1128
1129 va = shader->bo->gpu_address;
1130 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1131
1132 if (es_type == PIPE_SHADER_VERTEX) {
1133 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1134
1135 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1136 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1137 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1138 } else {
1139 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1140 }
1141 } else {
1142 assert(es_type == PIPE_SHADER_TESS_EVAL);
1143 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1144 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1145
1146 if (es_enable_prim_id || gs_info->uses_primid)
1147 break_wave_at_eoi = true;
1148 }
1149
1150 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1151 * VGPR[0:4] are always loaded.
1152 *
1153 * Vertex shaders always need to load VGPR3, because they need to
1154 * pass edge flags for decomposed primitives (such as quads) to the PA
1155 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1156 */
1157 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1158 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1159 else if (gs_info->uses_primid)
1160 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1161 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1162 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1163 else
1164 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1165
1166 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1167 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1168 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1169 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1170 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1171 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1172 S_00B228_DX10_CLAMP(1) |
1173 S_00B228_MEM_ORDERED(1) |
1174 S_00B228_WGP_MODE(1) |
1175 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1176 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1177 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1178 S_00B22C_USER_SGPR(num_user_sgprs) |
1179 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1180 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1181 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1182 S_00B22C_LDS_SIZE(shader->config.lds_size));
1183
1184 nparams = MAX2(shader->info.nr_param_exports, 1);
1185 shader->ctx_reg.ngg.spi_vs_out_config =
1186 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1187 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1188
1189 shader->ctx_reg.ngg.spi_shader_idx_format =
1190 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1191 shader->ctx_reg.ngg.spi_shader_pos_format =
1192 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1193 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1194 V_02870C_SPI_SHADER_4COMP :
1195 V_02870C_SPI_SHADER_NONE) |
1196 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1197 V_02870C_SPI_SHADER_4COMP :
1198 V_02870C_SPI_SHADER_NONE) |
1199 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1200 V_02870C_SPI_SHADER_4COMP :
1201 V_02870C_SPI_SHADER_NONE);
1202
1203 shader->ctx_reg.ngg.vgt_primitiveid_en =
1204 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1205 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1206
1207 if (gs_type == PIPE_SHADER_GEOMETRY) {
1208 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1209 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1210 } else {
1211 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1212 }
1213
1214 if (es_type == PIPE_SHADER_TESS_EVAL)
1215 si_set_tesseval_regs(sscreen, es_sel, pm4);
1216
1217 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1218 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1219 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1220 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1221 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1222 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1223 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1224 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1225 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1226 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1227 S_028B90_CNT(gs_num_invocations) |
1228 S_028B90_ENABLE(gs_num_invocations > 1) |
1229 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1230 shader->ngg.max_vert_out_per_gs_instance);
1231
1232 /* Always output hw-generated edge flags and pass them via the prim
1233 * export to prevent drawing lines on internal edges of decomposed
1234 * primitives (such as quads) with polygon mode = lines. Only VS needs
1235 * this.
1236 */
1237 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1238 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1239 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1240
1241 shader->ge_cntl =
1242 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1243 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1244 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1245
1246 /* Bug workaround for a possible hang with non-tessellation cases.
1247 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1248 *
1249 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1250 */
1251 if ((sscreen->info.family == CHIP_NAVI10 ||
1252 sscreen->info.family == CHIP_NAVI12 ||
1253 sscreen->info.family == CHIP_NAVI14) &&
1254 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1255 shader->ngg.hw_max_esverts != 256) {
1256 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1257
1258 if (shader->ngg.hw_max_esverts > 5) {
1259 shader->ge_cntl |=
1260 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1261 }
1262 }
1263
1264 if (window_space) {
1265 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1266 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1267 } else {
1268 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1269 S_028818_VTX_W0_FMT(1) |
1270 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1271 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1272 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1273 }
1274 }
1275
1276 static void si_emit_shader_vs(struct si_context *sctx)
1277 {
1278 struct si_shader *shader = sctx->queued.named.vs->shader;
1279 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1280
1281 if (!shader)
1282 return;
1283
1284 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1285 SI_TRACKED_VGT_GS_MODE,
1286 shader->ctx_reg.vs.vgt_gs_mode);
1287 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1288 SI_TRACKED_VGT_PRIMITIVEID_EN,
1289 shader->ctx_reg.vs.vgt_primitiveid_en);
1290
1291 if (sctx->chip_class <= GFX8) {
1292 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1293 SI_TRACKED_VGT_REUSE_OFF,
1294 shader->ctx_reg.vs.vgt_reuse_off);
1295 }
1296
1297 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1298 SI_TRACKED_SPI_VS_OUT_CONFIG,
1299 shader->ctx_reg.vs.spi_vs_out_config);
1300
1301 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1302 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1303 shader->ctx_reg.vs.spi_shader_pos_format);
1304
1305 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1306 SI_TRACKED_PA_CL_VTE_CNTL,
1307 shader->ctx_reg.vs.pa_cl_vte_cntl);
1308
1309 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1310 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1311 SI_TRACKED_VGT_TF_PARAM,
1312 shader->vgt_tf_param);
1313
1314 if (shader->vgt_vertex_reuse_block_cntl)
1315 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1316 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1317 shader->vgt_vertex_reuse_block_cntl);
1318
1319 if (initial_cdw != sctx->gfx_cs->current.cdw)
1320 sctx->context_roll = true;
1321
1322 /* Required programming for tessellation. (legacy pipeline only) */
1323 if (sctx->chip_class == GFX10 &&
1324 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1325 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1326 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1327 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1328 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1329 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1330 }
1331
1332 if (sctx->chip_class >= GFX10) {
1333 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1334 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1335 shader->pa_cl_vs_out_cntl,
1336 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1337 }
1338 }
1339
1340 /**
1341 * Compute the state for \p shader, which will run as a vertex shader on the
1342 * hardware.
1343 *
1344 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1345 * is the copy shader.
1346 */
1347 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1348 struct si_shader_selector *gs)
1349 {
1350 const struct tgsi_shader_info *info = &shader->selector->info;
1351 struct si_pm4_state *pm4;
1352 unsigned num_user_sgprs, vgpr_comp_cnt;
1353 uint64_t va;
1354 unsigned nparams, oc_lds_en;
1355 unsigned window_space =
1356 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1357 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1358
1359 pm4 = si_get_shader_pm4_state(shader);
1360 if (!pm4)
1361 return;
1362
1363 pm4->atom.emit = si_emit_shader_vs;
1364
1365 /* We always write VGT_GS_MODE in the VS state, because every switch
1366 * between different shader pipelines involving a different GS or no
1367 * GS at all involves a switch of the VS (different GS use different
1368 * copy shaders). On the other hand, when the API switches from a GS to
1369 * no GS and then back to the same GS used originally, the GS state is
1370 * not sent again.
1371 */
1372 if (!gs) {
1373 unsigned mode = V_028A40_GS_OFF;
1374
1375 /* PrimID needs GS scenario A. */
1376 if (enable_prim_id)
1377 mode = V_028A40_GS_SCENARIO_A;
1378
1379 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1380 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1381 } else {
1382 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1383 sscreen->info.chip_class);
1384 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1385 }
1386
1387 if (sscreen->info.chip_class <= GFX8) {
1388 /* Reuse needs to be set off if we write oViewport. */
1389 shader->ctx_reg.vs.vgt_reuse_off =
1390 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1391 }
1392
1393 va = shader->bo->gpu_address;
1394 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1395
1396 if (gs) {
1397 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1398 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1399 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1400 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1401
1402 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1403 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1404 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1405 } else {
1406 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1407 }
1408 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1409 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1410 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1411 } else
1412 unreachable("invalid shader selector type");
1413
1414 /* VS is required to export at least one param. */
1415 nparams = MAX2(shader->info.nr_param_exports, 1);
1416 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1417
1418 if (sscreen->info.chip_class >= GFX10) {
1419 shader->ctx_reg.vs.spi_vs_out_config |=
1420 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1421 }
1422
1423 shader->ctx_reg.vs.spi_shader_pos_format =
1424 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1425 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1426 V_02870C_SPI_SHADER_4COMP :
1427 V_02870C_SPI_SHADER_NONE) |
1428 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1429 V_02870C_SPI_SHADER_4COMP :
1430 V_02870C_SPI_SHADER_NONE) |
1431 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1432 V_02870C_SPI_SHADER_4COMP :
1433 V_02870C_SPI_SHADER_NONE);
1434 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1435
1436 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1437
1438 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1439 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1440
1441 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1442 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1443 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1444 S_00B128_DX10_CLAMP(1) |
1445 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1446 S_00B128_FLOAT_MODE(shader->config.float_mode);
1447 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1448 S_00B12C_OC_LDS_EN(oc_lds_en) |
1449 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1450
1451 if (sscreen->info.chip_class <= GFX9)
1452 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1453
1454 if (!sscreen->use_ngg_streamout) {
1455 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1456 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1457 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1458 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1459 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1460 }
1461
1462 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1463 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1464
1465 if (window_space)
1466 shader->ctx_reg.vs.pa_cl_vte_cntl =
1467 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1468 else
1469 shader->ctx_reg.vs.pa_cl_vte_cntl =
1470 S_028818_VTX_W0_FMT(1) |
1471 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1472 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1473 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1474
1475 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1476 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1477
1478 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1479 }
1480
1481 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1482 {
1483 struct tgsi_shader_info *info = &ps->selector->info;
1484 unsigned num_colors = !!(info->colors_read & 0x0f) +
1485 !!(info->colors_read & 0xf0);
1486 unsigned num_interp = ps->selector->info.num_inputs +
1487 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1488
1489 assert(num_interp <= 32);
1490 return MIN2(num_interp, 32);
1491 }
1492
1493 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1494 {
1495 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1496 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1497
1498 /* If the i-th target format is set, all previous target formats must
1499 * be non-zero to avoid hangs.
1500 */
1501 for (i = 0; i < num_targets; i++)
1502 if (!(value & (0xf << (i * 4))))
1503 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1504
1505 return value;
1506 }
1507
1508 static void si_emit_shader_ps(struct si_context *sctx)
1509 {
1510 struct si_shader *shader = sctx->queued.named.ps->shader;
1511 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1512
1513 if (!shader)
1514 return;
1515
1516 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1517 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1518 SI_TRACKED_SPI_PS_INPUT_ENA,
1519 shader->ctx_reg.ps.spi_ps_input_ena,
1520 shader->ctx_reg.ps.spi_ps_input_addr);
1521
1522 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1523 SI_TRACKED_SPI_BARYC_CNTL,
1524 shader->ctx_reg.ps.spi_baryc_cntl);
1525 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1526 SI_TRACKED_SPI_PS_IN_CONTROL,
1527 shader->ctx_reg.ps.spi_ps_in_control);
1528
1529 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1530 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1531 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1532 shader->ctx_reg.ps.spi_shader_z_format,
1533 shader->ctx_reg.ps.spi_shader_col_format);
1534
1535 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1536 SI_TRACKED_CB_SHADER_MASK,
1537 shader->ctx_reg.ps.cb_shader_mask);
1538
1539 if (initial_cdw != sctx->gfx_cs->current.cdw)
1540 sctx->context_roll = true;
1541 }
1542
1543 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1544 {
1545 struct tgsi_shader_info *info = &shader->selector->info;
1546 struct si_pm4_state *pm4;
1547 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1548 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1549 uint64_t va;
1550 unsigned input_ena = shader->config.spi_ps_input_ena;
1551
1552 /* we need to enable at least one of them, otherwise we hang the GPU */
1553 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1554 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1555 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1556 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1557 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1558 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1559 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1560 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1561 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1562 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1563 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1564 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1565 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1566 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1567
1568 /* Validate interpolation optimization flags (read as implications). */
1569 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1570 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1571 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1572 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1573 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1574 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1575 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1576 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1577 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1578 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1579 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1580 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1581 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1582 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1583 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1584 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1585 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1586 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1587
1588 /* Validate cases when the optimizations are off (read as implications). */
1589 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1590 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1591 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1592 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1593 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1594 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1595
1596 pm4 = si_get_shader_pm4_state(shader);
1597 if (!pm4)
1598 return;
1599
1600 pm4->atom.emit = si_emit_shader_ps;
1601
1602 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1603 * Possible vaules:
1604 * 0 -> Position = pixel center
1605 * 1 -> Position = pixel centroid
1606 * 2 -> Position = at sample position
1607 *
1608 * From GLSL 4.5 specification, section 7.1:
1609 * "The variable gl_FragCoord is available as an input variable from
1610 * within fragment shaders and it holds the window relative coordinates
1611 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1612 * value can be for any location within the pixel, or one of the
1613 * fragment samples. The use of centroid does not further restrict
1614 * this value to be inside the current primitive."
1615 *
1616 * Meaning that centroid has no effect and we can return anything within
1617 * the pixel. Thus, return the value at sample position, because that's
1618 * the most accurate one shaders can get.
1619 */
1620 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1621
1622 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1623 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1624 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1625
1626 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1627 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1628
1629 /* Ensure that some export memory is always allocated, for two reasons:
1630 *
1631 * 1) Correctness: The hardware ignores the EXEC mask if no export
1632 * memory is allocated, so KILL and alpha test do not work correctly
1633 * without this.
1634 * 2) Performance: Every shader needs at least a NULL export, even when
1635 * it writes no color/depth output. The NULL export instruction
1636 * stalls without this setting.
1637 *
1638 * Don't add this to CB_SHADER_MASK.
1639 *
1640 * GFX10 supports pixel shaders without exports by setting both
1641 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1642 * instructions if any are present.
1643 */
1644 if ((sscreen->info.chip_class <= GFX9 ||
1645 info->uses_kill ||
1646 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1647 !spi_shader_col_format &&
1648 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1649 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1650
1651 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1652 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1653
1654 /* Set interpolation controls. */
1655 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1656 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1657
1658 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1659 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1660 shader->ctx_reg.ps.spi_shader_z_format =
1661 ac_get_spi_shader_z_format(info->writes_z,
1662 info->writes_stencil,
1663 info->writes_samplemask);
1664 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1665 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1666
1667 va = shader->bo->gpu_address;
1668 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1669 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1670 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1671
1672 uint32_t rsrc1 =
1673 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1674 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1675 S_00B028_DX10_CLAMP(1) |
1676 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1677 S_00B028_FLOAT_MODE(shader->config.float_mode);
1678
1679 if (sscreen->info.chip_class < GFX10) {
1680 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1681 }
1682
1683 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1684 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1685 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1686 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1687 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1688 }
1689
1690 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1691 struct si_shader *shader)
1692 {
1693 switch (shader->selector->type) {
1694 case PIPE_SHADER_VERTEX:
1695 if (shader->key.as_ls)
1696 si_shader_ls(sscreen, shader);
1697 else if (shader->key.as_es)
1698 si_shader_es(sscreen, shader);
1699 else if (shader->key.as_ngg)
1700 gfx10_shader_ngg(sscreen, shader);
1701 else
1702 si_shader_vs(sscreen, shader, NULL);
1703 break;
1704 case PIPE_SHADER_TESS_CTRL:
1705 si_shader_hs(sscreen, shader);
1706 break;
1707 case PIPE_SHADER_TESS_EVAL:
1708 if (shader->key.as_es)
1709 si_shader_es(sscreen, shader);
1710 else if (shader->key.as_ngg)
1711 gfx10_shader_ngg(sscreen, shader);
1712 else
1713 si_shader_vs(sscreen, shader, NULL);
1714 break;
1715 case PIPE_SHADER_GEOMETRY:
1716 if (shader->key.as_ngg)
1717 gfx10_shader_ngg(sscreen, shader);
1718 else
1719 si_shader_gs(sscreen, shader);
1720 break;
1721 case PIPE_SHADER_FRAGMENT:
1722 si_shader_ps(sscreen, shader);
1723 break;
1724 default:
1725 assert(0);
1726 }
1727 }
1728
1729 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1730 {
1731 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1732 return sctx->queued.named.dsa->alpha_func;
1733 }
1734
1735 void si_shader_selector_key_vs(struct si_context *sctx,
1736 struct si_shader_selector *vs,
1737 struct si_shader_key *key,
1738 struct si_vs_prolog_bits *prolog_key)
1739 {
1740 if (!sctx->vertex_elements ||
1741 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1742 return;
1743
1744 struct si_vertex_elements *elts = sctx->vertex_elements;
1745
1746 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1747 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1748 prolog_key->unpack_instance_id_from_vertex_id =
1749 sctx->prim_discard_cs_instancing;
1750
1751 /* Prefer a monolithic shader to allow scheduling divisions around
1752 * VBO loads. */
1753 if (prolog_key->instance_divisor_is_fetched)
1754 key->opt.prefer_mono = 1;
1755
1756 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1757 unsigned count_mask = (1 << count) - 1;
1758 unsigned fix = elts->fix_fetch_always & count_mask;
1759 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1760
1761 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1762 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1763 while (mask) {
1764 unsigned i = u_bit_scan(&mask);
1765 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1766 unsigned vbidx = elts->vertex_buffer_index[i];
1767 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1768 unsigned align_mask = (1 << log_hw_load_size) - 1;
1769 if (vb->buffer_offset & align_mask ||
1770 vb->stride & align_mask) {
1771 fix |= 1 << i;
1772 opencode |= 1 << i;
1773 }
1774 }
1775 }
1776
1777 while (fix) {
1778 unsigned i = u_bit_scan(&fix);
1779 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1780 }
1781 key->mono.vs_fetch_opencode = opencode;
1782 }
1783
1784 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1785 struct si_shader_selector *vs,
1786 struct si_shader_key *key)
1787 {
1788 struct si_shader_selector *ps = sctx->ps_shader.cso;
1789
1790 key->opt.clip_disable =
1791 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1792 (vs->info.clipdist_writemask ||
1793 vs->info.writes_clipvertex) &&
1794 !vs->info.culldist_writemask;
1795
1796 /* Find out if PS is disabled. */
1797 bool ps_disabled = true;
1798 if (ps) {
1799 bool ps_modifies_zs = ps->info.uses_kill ||
1800 ps->info.writes_z ||
1801 ps->info.writes_stencil ||
1802 ps->info.writes_samplemask ||
1803 sctx->queued.named.blend->alpha_to_coverage ||
1804 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1805 unsigned ps_colormask = si_get_total_colormask(sctx);
1806
1807 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1808 (!ps_colormask &&
1809 !ps_modifies_zs &&
1810 !ps->info.writes_memory);
1811 }
1812
1813 /* Find out which VS outputs aren't used by the PS. */
1814 uint64_t outputs_written = vs->outputs_written_before_ps;
1815 uint64_t inputs_read = 0;
1816
1817 /* Ignore outputs that are not passed from VS to PS. */
1818 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1819 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1820 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1821
1822 if (!ps_disabled) {
1823 inputs_read = ps->inputs_read;
1824 }
1825
1826 uint64_t linked = outputs_written & inputs_read;
1827
1828 key->opt.kill_outputs = ~linked & outputs_written;
1829 }
1830
1831 /* Compute the key for the hw shader variant */
1832 static inline void si_shader_selector_key(struct pipe_context *ctx,
1833 struct si_shader_selector *sel,
1834 union si_vgt_stages_key stages_key,
1835 struct si_shader_key *key)
1836 {
1837 struct si_context *sctx = (struct si_context *)ctx;
1838
1839 memset(key, 0, sizeof(*key));
1840
1841 switch (sel->type) {
1842 case PIPE_SHADER_VERTEX:
1843 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1844
1845 if (sctx->tes_shader.cso)
1846 key->as_ls = 1;
1847 else if (sctx->gs_shader.cso) {
1848 key->as_es = 1;
1849 key->as_ngg = stages_key.u.ngg;
1850 } else {
1851 key->as_ngg = stages_key.u.ngg;
1852 si_shader_selector_key_hw_vs(sctx, sel, key);
1853
1854 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1855 key->mono.u.vs_export_prim_id = 1;
1856 }
1857 break;
1858 case PIPE_SHADER_TESS_CTRL:
1859 if (sctx->chip_class >= GFX9) {
1860 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1861 key, &key->part.tcs.ls_prolog);
1862 key->part.tcs.ls = sctx->vs_shader.cso;
1863
1864 /* When the LS VGPR fix is needed, monolithic shaders
1865 * can:
1866 * - avoid initializing EXEC in both the LS prolog
1867 * and the LS main part when !vs_needs_prolog
1868 * - remove the fixup for unused input VGPRs
1869 */
1870 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1871
1872 /* The LS output / HS input layout can be communicated
1873 * directly instead of via user SGPRs for merged LS-HS.
1874 * The LS VGPR fix prefers this too.
1875 */
1876 key->opt.prefer_mono = 1;
1877 }
1878
1879 key->part.tcs.epilog.prim_mode =
1880 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1881 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1882 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1883 key->part.tcs.epilog.tes_reads_tess_factors =
1884 sctx->tes_shader.cso->info.reads_tess_factors;
1885
1886 if (sel == sctx->fixed_func_tcs_shader.cso)
1887 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1888 break;
1889 case PIPE_SHADER_TESS_EVAL:
1890 key->as_ngg = stages_key.u.ngg;
1891
1892 if (sctx->gs_shader.cso)
1893 key->as_es = 1;
1894 else {
1895 si_shader_selector_key_hw_vs(sctx, sel, key);
1896
1897 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1898 key->mono.u.vs_export_prim_id = 1;
1899 }
1900 break;
1901 case PIPE_SHADER_GEOMETRY:
1902 if (sctx->chip_class >= GFX9) {
1903 if (sctx->tes_shader.cso) {
1904 key->part.gs.es = sctx->tes_shader.cso;
1905 } else {
1906 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1907 key, &key->part.gs.vs_prolog);
1908 key->part.gs.es = sctx->vs_shader.cso;
1909 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1910 }
1911
1912 key->as_ngg = stages_key.u.ngg;
1913
1914 /* Merged ES-GS can have unbalanced wave usage.
1915 *
1916 * ES threads are per-vertex, while GS threads are
1917 * per-primitive. So without any amplification, there
1918 * are fewer GS threads than ES threads, which can result
1919 * in empty (no-op) GS waves. With too much amplification,
1920 * there are more GS threads than ES threads, which
1921 * can result in empty (no-op) ES waves.
1922 *
1923 * Non-monolithic shaders are implemented by setting EXEC
1924 * at the beginning of shader parts, and don't jump to
1925 * the end if EXEC is 0.
1926 *
1927 * Monolithic shaders use conditional blocks, so they can
1928 * jump and skip empty waves of ES or GS. So set this to
1929 * always use optimized variants, which are monolithic.
1930 */
1931 key->opt.prefer_mono = 1;
1932 }
1933 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1934 break;
1935 case PIPE_SHADER_FRAGMENT: {
1936 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1937 struct si_state_blend *blend = sctx->queued.named.blend;
1938
1939 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1940 sel->info.colors_written == 0x1)
1941 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1942
1943 /* Select the shader color format based on whether
1944 * blending or alpha are needed.
1945 */
1946 key->part.ps.epilog.spi_shader_col_format =
1947 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1948 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1949 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1950 sctx->framebuffer.spi_shader_col_format_blend) |
1951 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1952 sctx->framebuffer.spi_shader_col_format_alpha) |
1953 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1954 sctx->framebuffer.spi_shader_col_format);
1955 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1956
1957 /* The output for dual source blending should have
1958 * the same format as the first output.
1959 */
1960 if (blend->dual_src_blend) {
1961 key->part.ps.epilog.spi_shader_col_format |=
1962 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1963 }
1964
1965 /* If alpha-to-coverage is enabled, we have to export alpha
1966 * even if there is no color buffer.
1967 */
1968 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1969 blend->alpha_to_coverage)
1970 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1971
1972 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1973 * to the range supported by the type if a channel has less
1974 * than 16 bits and the export format is 16_ABGR.
1975 */
1976 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1977 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1978 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1979 }
1980
1981 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1982 if (!key->part.ps.epilog.last_cbuf) {
1983 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1984 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1985 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1986 }
1987
1988 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1989 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1990
1991 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1992 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1993
1994 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
1995 rs->multisample_enable;
1996
1997 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1998 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1999 (is_line && rs->line_smooth)) &&
2000 sctx->framebuffer.nr_samples <= 1;
2001 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2002
2003 if (sctx->ps_iter_samples > 1 &&
2004 sel->info.reads_samplemask) {
2005 key->part.ps.prolog.samplemask_log_ps_iter =
2006 util_logbase2(sctx->ps_iter_samples);
2007 }
2008
2009 if (rs->force_persample_interp &&
2010 rs->multisample_enable &&
2011 sctx->framebuffer.nr_samples > 1 &&
2012 sctx->ps_iter_samples > 1) {
2013 key->part.ps.prolog.force_persp_sample_interp =
2014 sel->info.uses_persp_center ||
2015 sel->info.uses_persp_centroid;
2016
2017 key->part.ps.prolog.force_linear_sample_interp =
2018 sel->info.uses_linear_center ||
2019 sel->info.uses_linear_centroid;
2020 } else if (rs->multisample_enable &&
2021 sctx->framebuffer.nr_samples > 1) {
2022 key->part.ps.prolog.bc_optimize_for_persp =
2023 sel->info.uses_persp_center &&
2024 sel->info.uses_persp_centroid;
2025 key->part.ps.prolog.bc_optimize_for_linear =
2026 sel->info.uses_linear_center &&
2027 sel->info.uses_linear_centroid;
2028 } else {
2029 /* Make sure SPI doesn't compute more than 1 pair
2030 * of (i,j), which is the optimization here. */
2031 key->part.ps.prolog.force_persp_center_interp =
2032 sel->info.uses_persp_center +
2033 sel->info.uses_persp_centroid +
2034 sel->info.uses_persp_sample > 1;
2035
2036 key->part.ps.prolog.force_linear_center_interp =
2037 sel->info.uses_linear_center +
2038 sel->info.uses_linear_centroid +
2039 sel->info.uses_linear_sample > 1;
2040
2041 if (sel->info.uses_persp_opcode_interp_sample ||
2042 sel->info.uses_linear_opcode_interp_sample)
2043 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2044 }
2045
2046 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2047
2048 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2049 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2050 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2051 struct pipe_resource *tex = cb0->texture;
2052
2053 /* 1D textures are allocated and used as 2D on GFX9. */
2054 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2055 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2056 (tex->target == PIPE_TEXTURE_1D ||
2057 tex->target == PIPE_TEXTURE_1D_ARRAY);
2058 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2059 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2060 tex->target == PIPE_TEXTURE_CUBE ||
2061 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2062 tex->target == PIPE_TEXTURE_3D;
2063 }
2064 break;
2065 }
2066 default:
2067 assert(0);
2068 }
2069
2070 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2071 memset(&key->opt, 0, sizeof(key->opt));
2072 }
2073
2074 static void si_build_shader_variant(struct si_shader *shader,
2075 int thread_index,
2076 bool low_priority)
2077 {
2078 struct si_shader_selector *sel = shader->selector;
2079 struct si_screen *sscreen = sel->screen;
2080 struct ac_llvm_compiler *compiler;
2081 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2082
2083 if (thread_index >= 0) {
2084 if (low_priority) {
2085 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2086 compiler = &sscreen->compiler_lowp[thread_index];
2087 } else {
2088 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2089 compiler = &sscreen->compiler[thread_index];
2090 }
2091 if (!debug->async)
2092 debug = NULL;
2093 } else {
2094 assert(!low_priority);
2095 compiler = shader->compiler_ctx_state.compiler;
2096 }
2097
2098 if (!compiler->passes)
2099 si_init_compiler(sscreen, compiler);
2100
2101 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2102 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2103 sel->type);
2104 shader->compilation_failed = true;
2105 return;
2106 }
2107
2108 if (shader->compiler_ctx_state.is_debug_context) {
2109 FILE *f = open_memstream(&shader->shader_log,
2110 &shader->shader_log_size);
2111 if (f) {
2112 si_shader_dump(sscreen, shader, NULL, f, false);
2113 fclose(f);
2114 }
2115 }
2116
2117 si_shader_init_pm4_state(sscreen, shader);
2118 }
2119
2120 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2121 {
2122 struct si_shader *shader = (struct si_shader *)job;
2123
2124 assert(thread_index >= 0);
2125
2126 si_build_shader_variant(shader, thread_index, true);
2127 }
2128
2129 static const struct si_shader_key zeroed;
2130
2131 static bool si_check_missing_main_part(struct si_screen *sscreen,
2132 struct si_shader_selector *sel,
2133 struct si_compiler_ctx_state *compiler_state,
2134 struct si_shader_key *key)
2135 {
2136 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2137
2138 if (!*mainp) {
2139 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2140
2141 if (!main_part)
2142 return false;
2143
2144 /* We can leave the fence as permanently signaled because the
2145 * main part becomes visible globally only after it has been
2146 * compiled. */
2147 util_queue_fence_init(&main_part->ready);
2148
2149 main_part->selector = sel;
2150 main_part->key.as_es = key->as_es;
2151 main_part->key.as_ls = key->as_ls;
2152 main_part->key.as_ngg = key->as_ngg;
2153 main_part->is_monolithic = false;
2154
2155 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2156 main_part, &compiler_state->debug) != 0) {
2157 FREE(main_part);
2158 return false;
2159 }
2160 *mainp = main_part;
2161 }
2162 return true;
2163 }
2164
2165 /**
2166 * Select a shader variant according to the shader key.
2167 *
2168 * \param optimized_or_none If the key describes an optimized shader variant and
2169 * the compilation isn't finished, don't select any
2170 * shader and return an error.
2171 */
2172 int si_shader_select_with_key(struct si_screen *sscreen,
2173 struct si_shader_ctx_state *state,
2174 struct si_compiler_ctx_state *compiler_state,
2175 struct si_shader_key *key,
2176 int thread_index,
2177 bool optimized_or_none)
2178 {
2179 struct si_shader_selector *sel = state->cso;
2180 struct si_shader_selector *previous_stage_sel = NULL;
2181 struct si_shader *current = state->current;
2182 struct si_shader *iter, *shader = NULL;
2183
2184 again:
2185 /* Check if we don't need to change anything.
2186 * This path is also used for most shaders that don't need multiple
2187 * variants, it will cost just a computation of the key and this
2188 * test. */
2189 if (likely(current &&
2190 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2191 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2192 if (current->is_optimized) {
2193 if (optimized_or_none)
2194 return -1;
2195
2196 memset(&key->opt, 0, sizeof(key->opt));
2197 goto current_not_ready;
2198 }
2199
2200 util_queue_fence_wait(&current->ready);
2201 }
2202
2203 return current->compilation_failed ? -1 : 0;
2204 }
2205 current_not_ready:
2206
2207 /* This must be done before the mutex is locked, because async GS
2208 * compilation calls this function too, and therefore must enter
2209 * the mutex first.
2210 *
2211 * Only wait if we are in a draw call. Don't wait if we are
2212 * in a compiler thread.
2213 */
2214 if (thread_index < 0)
2215 util_queue_fence_wait(&sel->ready);
2216
2217 simple_mtx_lock(&sel->mutex);
2218
2219 /* Find the shader variant. */
2220 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2221 /* Don't check the "current" shader. We checked it above. */
2222 if (current != iter &&
2223 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2224 simple_mtx_unlock(&sel->mutex);
2225
2226 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2227 /* If it's an optimized shader and its compilation has
2228 * been started but isn't done, use the unoptimized
2229 * shader so as not to cause a stall due to compilation.
2230 */
2231 if (iter->is_optimized) {
2232 if (optimized_or_none)
2233 return -1;
2234 memset(&key->opt, 0, sizeof(key->opt));
2235 goto again;
2236 }
2237
2238 util_queue_fence_wait(&iter->ready);
2239 }
2240
2241 if (iter->compilation_failed) {
2242 return -1; /* skip the draw call */
2243 }
2244
2245 state->current = iter;
2246 return 0;
2247 }
2248 }
2249
2250 /* Build a new shader. */
2251 shader = CALLOC_STRUCT(si_shader);
2252 if (!shader) {
2253 simple_mtx_unlock(&sel->mutex);
2254 return -ENOMEM;
2255 }
2256
2257 util_queue_fence_init(&shader->ready);
2258
2259 shader->selector = sel;
2260 shader->key = *key;
2261 shader->compiler_ctx_state = *compiler_state;
2262
2263 /* If this is a merged shader, get the first shader's selector. */
2264 if (sscreen->info.chip_class >= GFX9) {
2265 if (sel->type == PIPE_SHADER_TESS_CTRL)
2266 previous_stage_sel = key->part.tcs.ls;
2267 else if (sel->type == PIPE_SHADER_GEOMETRY)
2268 previous_stage_sel = key->part.gs.es;
2269
2270 /* We need to wait for the previous shader. */
2271 if (previous_stage_sel && thread_index < 0)
2272 util_queue_fence_wait(&previous_stage_sel->ready);
2273 }
2274
2275 bool is_pure_monolithic =
2276 sscreen->use_monolithic_shaders ||
2277 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2278
2279 /* Compile the main shader part if it doesn't exist. This can happen
2280 * if the initial guess was wrong.
2281 *
2282 * The prim discard CS doesn't need the main shader part.
2283 */
2284 if (!is_pure_monolithic &&
2285 !key->opt.vs_as_prim_discard_cs) {
2286 bool ok = true;
2287
2288 /* Make sure the main shader part is present. This is needed
2289 * for shaders that can be compiled as VS, LS, or ES, and only
2290 * one of them is compiled at creation.
2291 *
2292 * It is also needed for GS, which can be compiled as non-NGG
2293 * and NGG.
2294 *
2295 * For merged shaders, check that the starting shader's main
2296 * part is present.
2297 */
2298 if (previous_stage_sel) {
2299 struct si_shader_key shader1_key = zeroed;
2300
2301 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2302 shader1_key.as_ls = 1;
2303 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2304 shader1_key.as_es = 1;
2305 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2306 } else {
2307 assert(0);
2308 }
2309
2310 simple_mtx_lock(&previous_stage_sel->mutex);
2311 ok = si_check_missing_main_part(sscreen,
2312 previous_stage_sel,
2313 compiler_state, &shader1_key);
2314 simple_mtx_unlock(&previous_stage_sel->mutex);
2315 }
2316
2317 if (ok) {
2318 ok = si_check_missing_main_part(sscreen, sel,
2319 compiler_state, key);
2320 }
2321
2322 if (!ok) {
2323 FREE(shader);
2324 simple_mtx_unlock(&sel->mutex);
2325 return -ENOMEM; /* skip the draw call */
2326 }
2327 }
2328
2329 /* Keep the reference to the 1st shader of merged shaders, so that
2330 * Gallium can't destroy it before we destroy the 2nd shader.
2331 *
2332 * Set sctx = NULL, because it's unused if we're not releasing
2333 * the shader, and we don't have any sctx here.
2334 */
2335 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2336 previous_stage_sel);
2337
2338 /* Monolithic-only shaders don't make a distinction between optimized
2339 * and unoptimized. */
2340 shader->is_monolithic =
2341 is_pure_monolithic ||
2342 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2343
2344 /* The prim discard CS is always optimized. */
2345 shader->is_optimized =
2346 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2347 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2348
2349 /* If it's an optimized shader, compile it asynchronously. */
2350 if (shader->is_optimized && thread_index < 0) {
2351 /* Compile it asynchronously. */
2352 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2353 shader, &shader->ready,
2354 si_build_shader_variant_low_priority, NULL,
2355 0);
2356
2357 /* Add only after the ready fence was reset, to guard against a
2358 * race with si_bind_XX_shader. */
2359 if (!sel->last_variant) {
2360 sel->first_variant = shader;
2361 sel->last_variant = shader;
2362 } else {
2363 sel->last_variant->next_variant = shader;
2364 sel->last_variant = shader;
2365 }
2366
2367 /* Use the default (unoptimized) shader for now. */
2368 memset(&key->opt, 0, sizeof(key->opt));
2369 simple_mtx_unlock(&sel->mutex);
2370
2371 if (sscreen->options.sync_compile)
2372 util_queue_fence_wait(&shader->ready);
2373
2374 if (optimized_or_none)
2375 return -1;
2376 goto again;
2377 }
2378
2379 /* Reset the fence before adding to the variant list. */
2380 util_queue_fence_reset(&shader->ready);
2381
2382 if (!sel->last_variant) {
2383 sel->first_variant = shader;
2384 sel->last_variant = shader;
2385 } else {
2386 sel->last_variant->next_variant = shader;
2387 sel->last_variant = shader;
2388 }
2389
2390 simple_mtx_unlock(&sel->mutex);
2391
2392 assert(!shader->is_optimized);
2393 si_build_shader_variant(shader, thread_index, false);
2394
2395 util_queue_fence_signal(&shader->ready);
2396
2397 if (!shader->compilation_failed)
2398 state->current = shader;
2399
2400 return shader->compilation_failed ? -1 : 0;
2401 }
2402
2403 static int si_shader_select(struct pipe_context *ctx,
2404 struct si_shader_ctx_state *state,
2405 union si_vgt_stages_key stages_key,
2406 struct si_compiler_ctx_state *compiler_state)
2407 {
2408 struct si_context *sctx = (struct si_context *)ctx;
2409 struct si_shader_key key;
2410
2411 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2412 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2413 &key, -1, false);
2414 }
2415
2416 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2417 bool streamout,
2418 struct si_shader_key *key)
2419 {
2420 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2421
2422 switch (info->processor) {
2423 case PIPE_SHADER_VERTEX:
2424 switch (next_shader) {
2425 case PIPE_SHADER_GEOMETRY:
2426 key->as_es = 1;
2427 break;
2428 case PIPE_SHADER_TESS_CTRL:
2429 case PIPE_SHADER_TESS_EVAL:
2430 key->as_ls = 1;
2431 break;
2432 default:
2433 /* If POSITION isn't written, it can only be a HW VS
2434 * if streamout is used. If streamout isn't used,
2435 * assume that it's a HW LS. (the next shader is TCS)
2436 * This heuristic is needed for separate shader objects.
2437 */
2438 if (!info->writes_position && !streamout)
2439 key->as_ls = 1;
2440 }
2441 break;
2442
2443 case PIPE_SHADER_TESS_EVAL:
2444 if (next_shader == PIPE_SHADER_GEOMETRY ||
2445 !info->writes_position)
2446 key->as_es = 1;
2447 break;
2448 }
2449 }
2450
2451 /**
2452 * Compile the main shader part or the monolithic shader as part of
2453 * si_shader_selector initialization. Since it can be done asynchronously,
2454 * there is no way to report compile failures to applications.
2455 */
2456 static void si_init_shader_selector_async(void *job, int thread_index)
2457 {
2458 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2459 struct si_screen *sscreen = sel->screen;
2460 struct ac_llvm_compiler *compiler;
2461 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2462
2463 assert(!debug->debug_message || debug->async);
2464 assert(thread_index >= 0);
2465 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2466 compiler = &sscreen->compiler[thread_index];
2467
2468 if (!compiler->passes)
2469 si_init_compiler(sscreen, compiler);
2470
2471 /* Serialize NIR to save memory. Monolithic shader variants
2472 * have to deserialize NIR before compilation.
2473 */
2474 if (sel->nir) {
2475 struct blob blob;
2476 size_t size;
2477
2478 blob_init(&blob);
2479 /* true = remove optional debugging data to increase
2480 * the likehood of getting more shader cache hits.
2481 * It also drops variable names, so we'll save more memory.
2482 */
2483 nir_serialize(&blob, sel->nir, true);
2484 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2485 sel->nir_size = size;
2486 }
2487
2488 /* Compile the main shader part for use with a prolog and/or epilog.
2489 * If this fails, the driver will try to compile a monolithic shader
2490 * on demand.
2491 */
2492 if (!sscreen->use_monolithic_shaders) {
2493 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2494 unsigned char ir_sha1_cache_key[20];
2495
2496 if (!shader) {
2497 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2498 return;
2499 }
2500
2501 /* We can leave the fence signaled because use of the default
2502 * main part is guarded by the selector's ready fence. */
2503 util_queue_fence_init(&shader->ready);
2504
2505 shader->selector = sel;
2506 shader->is_monolithic = false;
2507 si_parse_next_shader_property(&sel->info,
2508 sel->so.num_outputs != 0,
2509 &shader->key);
2510
2511 if (sscreen->use_ngg &&
2512 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2513 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2514 sel->type == PIPE_SHADER_TESS_EVAL ||
2515 sel->type == PIPE_SHADER_GEOMETRY))
2516 shader->key.as_ngg = 1;
2517
2518 if (sel->tokens || sel->nir) {
2519 si_get_ir_cache_key(sel, shader->key.as_ngg,
2520 shader->key.as_es, ir_sha1_cache_key);
2521 }
2522
2523 /* Try to load the shader from the shader cache. */
2524 simple_mtx_lock(&sscreen->shader_cache_mutex);
2525
2526 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2527 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2528 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2529 } else {
2530 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2531
2532 /* Compile the shader if it hasn't been loaded from the cache. */
2533 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2534 debug) != 0) {
2535 FREE(shader);
2536 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2537 return;
2538 }
2539
2540 simple_mtx_lock(&sscreen->shader_cache_mutex);
2541 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
2542 shader, true);
2543 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2544 }
2545
2546 *si_get_main_shader_part(sel, &shader->key) = shader;
2547
2548 /* Unset "outputs_written" flags for outputs converted to
2549 * DEFAULT_VAL, so that later inter-shader optimizations don't
2550 * try to eliminate outputs that don't exist in the final
2551 * shader.
2552 *
2553 * This is only done if non-monolithic shaders are enabled.
2554 */
2555 if ((sel->type == PIPE_SHADER_VERTEX ||
2556 sel->type == PIPE_SHADER_TESS_EVAL) &&
2557 !shader->key.as_ls &&
2558 !shader->key.as_es) {
2559 unsigned i;
2560
2561 for (i = 0; i < sel->info.num_outputs; i++) {
2562 unsigned offset = shader->info.vs_output_param_offset[i];
2563
2564 if (offset <= AC_EXP_PARAM_OFFSET_31)
2565 continue;
2566
2567 unsigned name = sel->info.output_semantic_name[i];
2568 unsigned index = sel->info.output_semantic_index[i];
2569 unsigned id;
2570
2571 switch (name) {
2572 case TGSI_SEMANTIC_GENERIC:
2573 /* don't process indices the function can't handle */
2574 if (index >= SI_MAX_IO_GENERIC)
2575 break;
2576 /* fall through */
2577 default:
2578 id = si_shader_io_get_unique_index(name, index, true);
2579 sel->outputs_written_before_ps &= ~(1ull << id);
2580 break;
2581 case TGSI_SEMANTIC_POSITION: /* ignore these */
2582 case TGSI_SEMANTIC_PSIZE:
2583 case TGSI_SEMANTIC_CLIPVERTEX:
2584 case TGSI_SEMANTIC_EDGEFLAG:
2585 break;
2586 }
2587 }
2588 }
2589 }
2590
2591 /* The GS copy shader is always pre-compiled. */
2592 if (sel->type == PIPE_SHADER_GEOMETRY &&
2593 (!sscreen->use_ngg ||
2594 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2595 sel->tess_turns_off_ngg)) {
2596 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2597 if (!sel->gs_copy_shader) {
2598 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2599 return;
2600 }
2601
2602 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2603 }
2604
2605 /* Free NIR. We only keep serialized NIR after this point. */
2606 if (sel->nir) {
2607 ralloc_free(sel->nir);
2608 sel->nir = NULL;
2609 }
2610 }
2611
2612 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2613 struct util_queue_fence *ready_fence,
2614 struct si_compiler_ctx_state *compiler_ctx_state,
2615 void *job, util_queue_execute_func execute)
2616 {
2617 util_queue_fence_init(ready_fence);
2618
2619 struct util_async_debug_callback async_debug;
2620 bool debug =
2621 (sctx->debug.debug_message && !sctx->debug.async) ||
2622 sctx->is_debug ||
2623 si_can_dump_shader(sctx->screen, processor);
2624
2625 if (debug) {
2626 u_async_debug_init(&async_debug);
2627 compiler_ctx_state->debug = async_debug.base;
2628 }
2629
2630 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2631 ready_fence, execute, NULL, 0);
2632
2633 if (debug) {
2634 util_queue_fence_wait(ready_fence);
2635 u_async_debug_drain(&async_debug, &sctx->debug);
2636 u_async_debug_cleanup(&async_debug);
2637 }
2638
2639 if (sctx->screen->options.sync_compile)
2640 util_queue_fence_wait(ready_fence);
2641 }
2642
2643 /* Return descriptor slot usage masks from the given shader info. */
2644 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2645 uint32_t *const_and_shader_buffers,
2646 uint64_t *samplers_and_images)
2647 {
2648 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2649
2650 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2651 num_constbufs = util_last_bit(info->const_buffers_declared);
2652 /* two 8-byte images share one 16-byte slot */
2653 num_images = align(util_last_bit(info->images_declared), 2);
2654 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2655 num_samplers = util_last_bit(info->samplers_declared);
2656
2657 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2658 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2659 *const_and_shader_buffers =
2660 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2661
2662 /* The layout is:
2663 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2664 * - image[last] ... image[0] go to [31-last .. 31]
2665 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2666 *
2667 * FMASKs for images are placed separately, because MSAA images are rare,
2668 * and so we can benefit from a better cache hit rate if we keep image
2669 * descriptors together.
2670 */
2671 if (num_msaa_images)
2672 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2673
2674 start = si_get_image_slot(num_images - 1) / 2;
2675 *samplers_and_images =
2676 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2677 }
2678
2679 static void *si_create_shader_selector(struct pipe_context *ctx,
2680 const struct pipe_shader_state *state)
2681 {
2682 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2683 struct si_context *sctx = (struct si_context*)ctx;
2684 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2685 int i;
2686
2687 if (!sel)
2688 return NULL;
2689
2690 pipe_reference_init(&sel->reference, 1);
2691 sel->screen = sscreen;
2692 sel->compiler_ctx_state.debug = sctx->debug;
2693 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2694
2695 sel->so = state->stream_output;
2696
2697 if (state->type == PIPE_SHADER_IR_TGSI &&
2698 !sscreen->options.enable_nir) {
2699 sel->tokens = tgsi_dup_tokens(state->tokens);
2700 if (!sel->tokens) {
2701 FREE(sel);
2702 return NULL;
2703 }
2704
2705 tgsi_scan_shader(state->tokens, &sel->info);
2706 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2707
2708 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2709 if (sel->info.uses_persp_opcode_interp_centroid)
2710 sel->info.uses_persp_centroid = true;
2711
2712 if (sel->info.uses_linear_opcode_interp_centroid)
2713 sel->info.uses_linear_centroid = true;
2714
2715 if (sel->info.uses_persp_opcode_interp_offset ||
2716 sel->info.uses_persp_opcode_interp_sample)
2717 sel->info.uses_persp_center = true;
2718
2719 if (sel->info.uses_linear_opcode_interp_offset ||
2720 sel->info.uses_linear_opcode_interp_sample)
2721 sel->info.uses_linear_center = true;
2722 } else {
2723 if (state->type == PIPE_SHADER_IR_TGSI) {
2724 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2725 } else {
2726 assert(state->type == PIPE_SHADER_IR_NIR);
2727 sel->nir = state->ir.nir;
2728 }
2729
2730 si_nir_scan_shader(sel->nir, &sel->info);
2731 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2732 si_nir_adjust_driver_locations(sel->nir);
2733 }
2734
2735 sel->type = sel->info.processor;
2736 p_atomic_inc(&sscreen->num_shaders_created);
2737 si_get_active_slot_masks(&sel->info,
2738 &sel->active_const_and_shader_buffers,
2739 &sel->active_samplers_and_images);
2740
2741 /* Record which streamout buffers are enabled. */
2742 for (i = 0; i < sel->so.num_outputs; i++) {
2743 sel->enabled_streamout_buffer_mask |=
2744 (1 << sel->so.output[i].output_buffer) <<
2745 (sel->so.output[i].stream * 4);
2746 }
2747
2748 /* The prolog is a no-op if there are no inputs. */
2749 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2750 sel->info.num_inputs &&
2751 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2752
2753 sel->force_correct_derivs_after_kill =
2754 sel->type == PIPE_SHADER_FRAGMENT &&
2755 sel->info.uses_derivatives &&
2756 sel->info.uses_kill &&
2757 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2758
2759 sel->prim_discard_cs_allowed =
2760 sel->type == PIPE_SHADER_VERTEX &&
2761 !sel->info.uses_bindless_images &&
2762 !sel->info.uses_bindless_samplers &&
2763 !sel->info.writes_memory &&
2764 !sel->info.writes_viewport_index &&
2765 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2766 !sel->so.num_outputs;
2767
2768 switch (sel->type) {
2769 case PIPE_SHADER_GEOMETRY:
2770 sel->gs_output_prim =
2771 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2772
2773 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2774 sel->rast_prim = sel->gs_output_prim;
2775 if (util_rast_prim_is_triangles(sel->rast_prim))
2776 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2777
2778 sel->gs_max_out_vertices =
2779 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2780 sel->gs_num_invocations =
2781 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2782 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2783 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2784 sel->gs_max_out_vertices;
2785
2786 sel->max_gs_stream = 0;
2787 for (i = 0; i < sel->so.num_outputs; i++)
2788 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2789 sel->so.output[i].stream);
2790
2791 sel->gs_input_verts_per_prim =
2792 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2793
2794 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2795 sel->tess_turns_off_ngg =
2796 sscreen->info.chip_class == GFX10 &&
2797 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2798 break;
2799
2800 case PIPE_SHADER_TESS_CTRL:
2801 /* Always reserve space for these. */
2802 sel->patch_outputs_written |=
2803 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2804 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2805 /* fall through */
2806 case PIPE_SHADER_VERTEX:
2807 case PIPE_SHADER_TESS_EVAL:
2808 for (i = 0; i < sel->info.num_outputs; i++) {
2809 unsigned name = sel->info.output_semantic_name[i];
2810 unsigned index = sel->info.output_semantic_index[i];
2811
2812 switch (name) {
2813 case TGSI_SEMANTIC_TESSINNER:
2814 case TGSI_SEMANTIC_TESSOUTER:
2815 case TGSI_SEMANTIC_PATCH:
2816 sel->patch_outputs_written |=
2817 1ull << si_shader_io_get_unique_index_patch(name, index);
2818 break;
2819
2820 case TGSI_SEMANTIC_GENERIC:
2821 /* don't process indices the function can't handle */
2822 if (index >= SI_MAX_IO_GENERIC)
2823 break;
2824 /* fall through */
2825 default:
2826 sel->outputs_written |=
2827 1ull << si_shader_io_get_unique_index(name, index, false);
2828 sel->outputs_written_before_ps |=
2829 1ull << si_shader_io_get_unique_index(name, index, true);
2830 break;
2831 case TGSI_SEMANTIC_EDGEFLAG:
2832 break;
2833 }
2834 }
2835 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2836 sel->lshs_vertex_stride = sel->esgs_itemsize;
2837
2838 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2839 * will start on a different bank. (except for the maximum 32*16).
2840 */
2841 if (sel->lshs_vertex_stride < 32*16)
2842 sel->lshs_vertex_stride += 4;
2843
2844 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2845 * conflicts, i.e. each vertex will start at a different bank.
2846 */
2847 if (sctx->chip_class >= GFX9)
2848 sel->esgs_itemsize += 4;
2849
2850 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2851
2852 /* Only for TES: */
2853 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2854 sel->rast_prim = PIPE_PRIM_POINTS;
2855 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2856 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2857 else
2858 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2859 break;
2860
2861 case PIPE_SHADER_FRAGMENT:
2862 for (i = 0; i < sel->info.num_inputs; i++) {
2863 unsigned name = sel->info.input_semantic_name[i];
2864 unsigned index = sel->info.input_semantic_index[i];
2865
2866 switch (name) {
2867 case TGSI_SEMANTIC_GENERIC:
2868 /* don't process indices the function can't handle */
2869 if (index >= SI_MAX_IO_GENERIC)
2870 break;
2871 /* fall through */
2872 default:
2873 sel->inputs_read |=
2874 1ull << si_shader_io_get_unique_index(name, index, true);
2875 break;
2876 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2877 break;
2878 }
2879 }
2880
2881 for (i = 0; i < 8; i++)
2882 if (sel->info.colors_written & (1 << i))
2883 sel->colors_written_4bit |= 0xf << (4 * i);
2884
2885 for (i = 0; i < sel->info.num_inputs; i++) {
2886 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2887 int index = sel->info.input_semantic_index[i];
2888 sel->color_attr_index[index] = i;
2889 }
2890 }
2891 break;
2892 default:;
2893 }
2894
2895 /* PA_CL_VS_OUT_CNTL */
2896 if (sctx->chip_class <= GFX9)
2897 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2898
2899 sel->clipdist_mask = sel->info.writes_clipvertex ?
2900 SIX_BITS : sel->info.clipdist_writemask;
2901 sel->culldist_mask = sel->info.culldist_writemask <<
2902 sel->info.num_written_clipdistance;
2903
2904 /* DB_SHADER_CONTROL */
2905 sel->db_shader_control =
2906 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2907 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2908 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2909 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2910
2911 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2912 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2913 sel->db_shader_control |=
2914 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2915 break;
2916 case TGSI_FS_DEPTH_LAYOUT_LESS:
2917 sel->db_shader_control |=
2918 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2919 break;
2920 }
2921
2922 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2923 *
2924 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2925 * --|-----------|------------|------------|--------------------|-------------------|-------------
2926 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2927 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2928 * 2 | false | true | n/a | LateZ | 1 | 0
2929 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2930 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2931 *
2932 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2933 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2934 *
2935 * Don't use ReZ without profiling !!!
2936 *
2937 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2938 * shaders.
2939 */
2940 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2941 /* Cases 3, 4. */
2942 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2943 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2944 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2945 } else if (sel->info.writes_memory) {
2946 /* Case 2. */
2947 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2948 S_02880C_EXEC_ON_HIER_FAIL(1);
2949 } else {
2950 /* Case 1. */
2951 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2952 }
2953
2954 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2955 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2956
2957 (void) simple_mtx_init(&sel->mutex, mtx_plain);
2958
2959 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2960 &sel->compiler_ctx_state, sel,
2961 si_init_shader_selector_async);
2962 return sel;
2963 }
2964
2965 static void si_update_streamout_state(struct si_context *sctx)
2966 {
2967 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2968
2969 if (!shader_with_so)
2970 return;
2971
2972 sctx->streamout.enabled_stream_buffers_mask =
2973 shader_with_so->enabled_streamout_buffer_mask;
2974 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2975 }
2976
2977 static void si_update_clip_regs(struct si_context *sctx,
2978 struct si_shader_selector *old_hw_vs,
2979 struct si_shader *old_hw_vs_variant,
2980 struct si_shader_selector *next_hw_vs,
2981 struct si_shader *next_hw_vs_variant)
2982 {
2983 if (next_hw_vs &&
2984 (!old_hw_vs ||
2985 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2986 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2987 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2988 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2989 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2990 !old_hw_vs_variant ||
2991 !next_hw_vs_variant ||
2992 old_hw_vs_variant->key.opt.clip_disable !=
2993 next_hw_vs_variant->key.opt.clip_disable))
2994 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2995 }
2996
2997 static void si_update_common_shader_state(struct si_context *sctx)
2998 {
2999 sctx->uses_bindless_samplers =
3000 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
3001 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
3002 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
3003 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
3004 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
3005 sctx->uses_bindless_images =
3006 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
3007 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
3008 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
3009 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3010 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3011 sctx->do_update_shaders = true;
3012 }
3013
3014 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3015 {
3016 struct si_context *sctx = (struct si_context *)ctx;
3017 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3018 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3019 struct si_shader_selector *sel = state;
3020
3021 if (sctx->vs_shader.cso == sel)
3022 return;
3023
3024 sctx->vs_shader.cso = sel;
3025 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3026 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3027
3028 if (si_update_ngg(sctx))
3029 si_shader_change_notify(sctx);
3030
3031 si_update_common_shader_state(sctx);
3032 si_update_vs_viewport_state(sctx);
3033 si_set_active_descriptors_for_shader(sctx, sel);
3034 si_update_streamout_state(sctx);
3035 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3036 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3037 }
3038
3039 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3040 {
3041 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3042 (sctx->tes_shader.cso &&
3043 sctx->tes_shader.cso->info.uses_primid) ||
3044 (sctx->tcs_shader.cso &&
3045 sctx->tcs_shader.cso->info.uses_primid) ||
3046 (sctx->gs_shader.cso &&
3047 sctx->gs_shader.cso->info.uses_primid) ||
3048 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3049 sctx->ps_shader.cso->info.uses_primid);
3050 }
3051
3052 bool si_update_ngg(struct si_context *sctx)
3053 {
3054 if (!sctx->screen->use_ngg) {
3055 assert(!sctx->ngg);
3056 return false;
3057 }
3058
3059 bool new_ngg = true;
3060
3061 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3062 sctx->gs_shader.cso->tess_turns_off_ngg) {
3063 new_ngg = false;
3064 } else if (!sctx->screen->use_ngg_streamout) {
3065 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3066
3067 if ((last && last->so.num_outputs) ||
3068 sctx->streamout.prims_gen_query_enabled)
3069 new_ngg = false;
3070 }
3071
3072 if (new_ngg != sctx->ngg) {
3073 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3074 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3075 * pointers are set.
3076 */
3077 if ((sctx->family == CHIP_NAVI10 ||
3078 sctx->family == CHIP_NAVI12 ||
3079 sctx->family == CHIP_NAVI14) &&
3080 !new_ngg)
3081 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3082
3083 sctx->ngg = new_ngg;
3084 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3085 return true;
3086 }
3087 return false;
3088 }
3089
3090 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3091 {
3092 struct si_context *sctx = (struct si_context *)ctx;
3093 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3094 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3095 struct si_shader_selector *sel = state;
3096 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3097 bool ngg_changed;
3098
3099 if (sctx->gs_shader.cso == sel)
3100 return;
3101
3102 sctx->gs_shader.cso = sel;
3103 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3104 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3105
3106 si_update_common_shader_state(sctx);
3107 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3108
3109 ngg_changed = si_update_ngg(sctx);
3110 if (ngg_changed || enable_changed)
3111 si_shader_change_notify(sctx);
3112 if (enable_changed) {
3113 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3114 si_update_tess_uses_prim_id(sctx);
3115 }
3116 si_update_vs_viewport_state(sctx);
3117 si_set_active_descriptors_for_shader(sctx, sel);
3118 si_update_streamout_state(sctx);
3119 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3120 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3121 }
3122
3123 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3124 {
3125 struct si_context *sctx = (struct si_context *)ctx;
3126 struct si_shader_selector *sel = state;
3127 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3128
3129 if (sctx->tcs_shader.cso == sel)
3130 return;
3131
3132 sctx->tcs_shader.cso = sel;
3133 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3134 si_update_tess_uses_prim_id(sctx);
3135
3136 si_update_common_shader_state(sctx);
3137
3138 if (enable_changed)
3139 sctx->last_tcs = NULL; /* invalidate derived tess state */
3140
3141 si_set_active_descriptors_for_shader(sctx, sel);
3142 }
3143
3144 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3145 {
3146 struct si_context *sctx = (struct si_context *)ctx;
3147 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3148 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3149 struct si_shader_selector *sel = state;
3150 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3151
3152 if (sctx->tes_shader.cso == sel)
3153 return;
3154
3155 sctx->tes_shader.cso = sel;
3156 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3157 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3158 si_update_tess_uses_prim_id(sctx);
3159
3160 si_update_common_shader_state(sctx);
3161 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3162
3163 bool ngg_changed = si_update_ngg(sctx);
3164 if (ngg_changed || enable_changed)
3165 si_shader_change_notify(sctx);
3166 if (enable_changed)
3167 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3168 si_update_vs_viewport_state(sctx);
3169 si_set_active_descriptors_for_shader(sctx, sel);
3170 si_update_streamout_state(sctx);
3171 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3172 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3173 }
3174
3175 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3176 {
3177 struct si_context *sctx = (struct si_context *)ctx;
3178 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3179 struct si_shader_selector *sel = state;
3180
3181 /* skip if supplied shader is one already in use */
3182 if (old_sel == sel)
3183 return;
3184
3185 sctx->ps_shader.cso = sel;
3186 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3187
3188 si_update_common_shader_state(sctx);
3189 if (sel) {
3190 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3191 si_update_tess_uses_prim_id(sctx);
3192
3193 if (!old_sel ||
3194 old_sel->info.colors_written != sel->info.colors_written)
3195 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3196
3197 if (sctx->screen->has_out_of_order_rast &&
3198 (!old_sel ||
3199 old_sel->info.writes_memory != sel->info.writes_memory ||
3200 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3201 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3202 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3203 }
3204 si_set_active_descriptors_for_shader(sctx, sel);
3205 si_update_ps_colorbuf0_slot(sctx);
3206 }
3207
3208 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3209 {
3210 if (shader->is_optimized) {
3211 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3212 &shader->ready);
3213 }
3214
3215 util_queue_fence_destroy(&shader->ready);
3216
3217 if (shader->pm4) {
3218 /* If destroyed shaders were not unbound, the next compiled
3219 * shader variant could get the same pointer address and so
3220 * binding it to the same shader stage would be considered
3221 * a no-op, causing random behavior.
3222 */
3223 switch (shader->selector->type) {
3224 case PIPE_SHADER_VERTEX:
3225 if (shader->key.as_ls) {
3226 assert(sctx->chip_class <= GFX8);
3227 si_pm4_delete_state(sctx, ls, shader->pm4);
3228 } else if (shader->key.as_es) {
3229 assert(sctx->chip_class <= GFX8);
3230 si_pm4_delete_state(sctx, es, shader->pm4);
3231 } else if (shader->key.as_ngg) {
3232 si_pm4_delete_state(sctx, gs, shader->pm4);
3233 } else {
3234 si_pm4_delete_state(sctx, vs, shader->pm4);
3235 }
3236 break;
3237 case PIPE_SHADER_TESS_CTRL:
3238 si_pm4_delete_state(sctx, hs, shader->pm4);
3239 break;
3240 case PIPE_SHADER_TESS_EVAL:
3241 if (shader->key.as_es) {
3242 assert(sctx->chip_class <= GFX8);
3243 si_pm4_delete_state(sctx, es, shader->pm4);
3244 } else if (shader->key.as_ngg) {
3245 si_pm4_delete_state(sctx, gs, shader->pm4);
3246 } else {
3247 si_pm4_delete_state(sctx, vs, shader->pm4);
3248 }
3249 break;
3250 case PIPE_SHADER_GEOMETRY:
3251 if (shader->is_gs_copy_shader)
3252 si_pm4_delete_state(sctx, vs, shader->pm4);
3253 else
3254 si_pm4_delete_state(sctx, gs, shader->pm4);
3255 break;
3256 case PIPE_SHADER_FRAGMENT:
3257 si_pm4_delete_state(sctx, ps, shader->pm4);
3258 break;
3259 default:;
3260 }
3261 }
3262
3263 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3264 si_shader_destroy(shader);
3265 free(shader);
3266 }
3267
3268 void si_destroy_shader_selector(struct si_context *sctx,
3269 struct si_shader_selector *sel)
3270 {
3271 struct si_shader *p = sel->first_variant, *c;
3272 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3273 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3274 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3275 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3276 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3277 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3278 };
3279
3280 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3281
3282 if (current_shader[sel->type]->cso == sel) {
3283 current_shader[sel->type]->cso = NULL;
3284 current_shader[sel->type]->current = NULL;
3285 }
3286
3287 while (p) {
3288 c = p->next_variant;
3289 si_delete_shader(sctx, p);
3290 p = c;
3291 }
3292
3293 if (sel->main_shader_part)
3294 si_delete_shader(sctx, sel->main_shader_part);
3295 if (sel->main_shader_part_ls)
3296 si_delete_shader(sctx, sel->main_shader_part_ls);
3297 if (sel->main_shader_part_es)
3298 si_delete_shader(sctx, sel->main_shader_part_es);
3299 if (sel->main_shader_part_ngg)
3300 si_delete_shader(sctx, sel->main_shader_part_ngg);
3301 if (sel->gs_copy_shader)
3302 si_delete_shader(sctx, sel->gs_copy_shader);
3303
3304 util_queue_fence_destroy(&sel->ready);
3305 simple_mtx_destroy(&sel->mutex);
3306 free(sel->tokens);
3307 ralloc_free(sel->nir);
3308 free(sel->nir_binary);
3309 free(sel);
3310 }
3311
3312 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3313 {
3314 struct si_context *sctx = (struct si_context *)ctx;
3315 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3316
3317 si_shader_selector_reference(sctx, &sel, NULL);
3318 }
3319
3320 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3321 struct si_shader *vs, unsigned name,
3322 unsigned index, unsigned interpolate)
3323 {
3324 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3325 unsigned j, offset, ps_input_cntl = 0;
3326
3327 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3328 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3329 name == TGSI_SEMANTIC_PRIMID)
3330 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3331
3332 if (name == TGSI_SEMANTIC_PCOORD ||
3333 (name == TGSI_SEMANTIC_TEXCOORD &&
3334 sctx->sprite_coord_enable & (1 << index))) {
3335 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3336 }
3337
3338 for (j = 0; j < vsinfo->num_outputs; j++) {
3339 if (name == vsinfo->output_semantic_name[j] &&
3340 index == vsinfo->output_semantic_index[j]) {
3341 offset = vs->info.vs_output_param_offset[j];
3342
3343 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3344 /* The input is loaded from parameter memory. */
3345 ps_input_cntl |= S_028644_OFFSET(offset);
3346 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3347 if (offset == AC_EXP_PARAM_UNDEFINED) {
3348 /* This can happen with depth-only rendering. */
3349 offset = 0;
3350 } else {
3351 /* The input is a DEFAULT_VAL constant. */
3352 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3353 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3354 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3355 }
3356
3357 ps_input_cntl = S_028644_OFFSET(0x20) |
3358 S_028644_DEFAULT_VAL(offset);
3359 }
3360 break;
3361 }
3362 }
3363
3364 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3365 /* PrimID is written after the last output when HW VS is used. */
3366 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3367 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3368 /* No corresponding output found, load defaults into input.
3369 * Don't set any other bits.
3370 * (FLAT_SHADE=1 completely changes behavior) */
3371 ps_input_cntl = S_028644_OFFSET(0x20);
3372 /* D3D 9 behaviour. GL is undefined */
3373 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3374 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3375 }
3376 return ps_input_cntl;
3377 }
3378
3379 static void si_emit_spi_map(struct si_context *sctx)
3380 {
3381 struct si_shader *ps = sctx->ps_shader.current;
3382 struct si_shader *vs = si_get_vs_state(sctx);
3383 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3384 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3385 unsigned spi_ps_input_cntl[32];
3386
3387 if (!ps || !ps->selector->info.num_inputs)
3388 return;
3389
3390 num_interp = si_get_ps_num_interp(ps);
3391 assert(num_interp > 0);
3392
3393 for (i = 0; i < psinfo->num_inputs; i++) {
3394 unsigned name = psinfo->input_semantic_name[i];
3395 unsigned index = psinfo->input_semantic_index[i];
3396 unsigned interpolate = psinfo->input_interpolate[i];
3397
3398 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3399 index, interpolate);
3400
3401 if (name == TGSI_SEMANTIC_COLOR) {
3402 assert(index < ARRAY_SIZE(bcol_interp));
3403 bcol_interp[index] = interpolate;
3404 }
3405 }
3406
3407 if (ps->key.part.ps.prolog.color_two_side) {
3408 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3409
3410 for (i = 0; i < 2; i++) {
3411 if (!(psinfo->colors_read & (0xf << (i * 4))))
3412 continue;
3413
3414 spi_ps_input_cntl[num_written++] =
3415 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3416
3417 }
3418 }
3419 assert(num_interp == num_written);
3420
3421 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3422 /* Dota 2: Only ~16% of SPI map updates set different values. */
3423 /* Talos: Only ~9% of SPI map updates set different values. */
3424 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3425 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3426 spi_ps_input_cntl,
3427 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3428
3429 if (initial_cdw != sctx->gfx_cs->current.cdw)
3430 sctx->context_roll = true;
3431 }
3432
3433 /**
3434 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3435 */
3436 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3437 {
3438 if (sctx->init_config_has_vgt_flush)
3439 return;
3440
3441 /* Done by Vulkan before VGT_FLUSH. */
3442 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3443 si_pm4_cmd_add(sctx->init_config,
3444 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3445 si_pm4_cmd_end(sctx->init_config, false);
3446
3447 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3448 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3449 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3450 si_pm4_cmd_end(sctx->init_config, false);
3451 sctx->init_config_has_vgt_flush = true;
3452 }
3453
3454 /* Initialize state related to ESGS / GSVS ring buffers */
3455 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3456 {
3457 struct si_shader_selector *es =
3458 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3459 struct si_shader_selector *gs = sctx->gs_shader.cso;
3460 struct si_pm4_state *pm4;
3461
3462 /* Chip constants. */
3463 unsigned num_se = sctx->screen->info.max_se;
3464 unsigned wave_size = 64;
3465 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3466 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3467 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3468 */
3469 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3470 unsigned alignment = 256 * num_se;
3471 /* The maximum size is 63.999 MB per SE. */
3472 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3473
3474 /* Calculate the minimum size. */
3475 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3476 wave_size, alignment);
3477
3478 /* These are recommended sizes, not minimum sizes. */
3479 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3480 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3481 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3482 gs->max_gsvs_emit_size;
3483
3484 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3485 esgs_ring_size = align(esgs_ring_size, alignment);
3486 gsvs_ring_size = align(gsvs_ring_size, alignment);
3487
3488 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3489 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3490
3491 /* Some rings don't have to be allocated if shaders don't use them.
3492 * (e.g. no varyings between ES and GS or GS and VS)
3493 *
3494 * GFX9 doesn't have the ESGS ring.
3495 */
3496 bool update_esgs = sctx->chip_class <= GFX8 &&
3497 esgs_ring_size &&
3498 (!sctx->esgs_ring ||
3499 sctx->esgs_ring->width0 < esgs_ring_size);
3500 bool update_gsvs = gsvs_ring_size &&
3501 (!sctx->gsvs_ring ||
3502 sctx->gsvs_ring->width0 < gsvs_ring_size);
3503
3504 if (!update_esgs && !update_gsvs)
3505 return true;
3506
3507 if (update_esgs) {
3508 pipe_resource_reference(&sctx->esgs_ring, NULL);
3509 sctx->esgs_ring =
3510 pipe_aligned_buffer_create(sctx->b.screen,
3511 SI_RESOURCE_FLAG_UNMAPPABLE,
3512 PIPE_USAGE_DEFAULT,
3513 esgs_ring_size,
3514 sctx->screen->info.pte_fragment_size);
3515 if (!sctx->esgs_ring)
3516 return false;
3517 }
3518
3519 if (update_gsvs) {
3520 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3521 sctx->gsvs_ring =
3522 pipe_aligned_buffer_create(sctx->b.screen,
3523 SI_RESOURCE_FLAG_UNMAPPABLE,
3524 PIPE_USAGE_DEFAULT,
3525 gsvs_ring_size,
3526 sctx->screen->info.pte_fragment_size);
3527 if (!sctx->gsvs_ring)
3528 return false;
3529 }
3530
3531 /* Create the "init_config_gs_rings" state. */
3532 pm4 = CALLOC_STRUCT(si_pm4_state);
3533 if (!pm4)
3534 return false;
3535
3536 if (sctx->chip_class >= GFX7) {
3537 if (sctx->esgs_ring) {
3538 assert(sctx->chip_class <= GFX8);
3539 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3540 sctx->esgs_ring->width0 / 256);
3541 }
3542 if (sctx->gsvs_ring)
3543 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3544 sctx->gsvs_ring->width0 / 256);
3545 } else {
3546 if (sctx->esgs_ring)
3547 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3548 sctx->esgs_ring->width0 / 256);
3549 if (sctx->gsvs_ring)
3550 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3551 sctx->gsvs_ring->width0 / 256);
3552 }
3553
3554 /* Set the state. */
3555 if (sctx->init_config_gs_rings)
3556 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3557 sctx->init_config_gs_rings = pm4;
3558
3559 if (!sctx->init_config_has_vgt_flush) {
3560 si_init_config_add_vgt_flush(sctx);
3561 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3562 }
3563
3564 /* Flush the context to re-emit both init_config states. */
3565 sctx->initial_gfx_cs_size = 0; /* force flush */
3566 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3567
3568 /* Set ring bindings. */
3569 if (sctx->esgs_ring) {
3570 assert(sctx->chip_class <= GFX8);
3571 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3572 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3573 true, true, 4, 64, 0);
3574 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3575 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3576 false, false, 0, 0, 0);
3577 }
3578 if (sctx->gsvs_ring) {
3579 si_set_ring_buffer(sctx, SI_RING_GSVS,
3580 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3581 false, false, 0, 0, 0);
3582 }
3583
3584 return true;
3585 }
3586
3587 static void si_shader_lock(struct si_shader *shader)
3588 {
3589 simple_mtx_lock(&shader->selector->mutex);
3590 if (shader->previous_stage_sel) {
3591 assert(shader->previous_stage_sel != shader->selector);
3592 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3593 }
3594 }
3595
3596 static void si_shader_unlock(struct si_shader *shader)
3597 {
3598 if (shader->previous_stage_sel)
3599 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3600 simple_mtx_unlock(&shader->selector->mutex);
3601 }
3602
3603 /**
3604 * @returns 1 if \p sel has been updated to use a new scratch buffer
3605 * 0 if not
3606 * < 0 if there was a failure
3607 */
3608 static int si_update_scratch_buffer(struct si_context *sctx,
3609 struct si_shader *shader)
3610 {
3611 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3612
3613 if (!shader)
3614 return 0;
3615
3616 /* This shader doesn't need a scratch buffer */
3617 if (shader->config.scratch_bytes_per_wave == 0)
3618 return 0;
3619
3620 /* Prevent race conditions when updating:
3621 * - si_shader::scratch_bo
3622 * - si_shader::binary::code
3623 * - si_shader::previous_stage::binary::code.
3624 */
3625 si_shader_lock(shader);
3626
3627 /* This shader is already configured to use the current
3628 * scratch buffer. */
3629 if (shader->scratch_bo == sctx->scratch_buffer) {
3630 si_shader_unlock(shader);
3631 return 0;
3632 }
3633
3634 assert(sctx->scratch_buffer);
3635
3636 /* Replace the shader bo with a new bo that has the relocs applied. */
3637 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3638 si_shader_unlock(shader);
3639 return -1;
3640 }
3641
3642 /* Update the shader state to use the new shader bo. */
3643 si_shader_init_pm4_state(sctx->screen, shader);
3644
3645 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3646
3647 si_shader_unlock(shader);
3648 return 1;
3649 }
3650
3651 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3652 {
3653 return shader ? shader->config.scratch_bytes_per_wave : 0;
3654 }
3655
3656 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3657 {
3658 if (!sctx->tes_shader.cso)
3659 return NULL; /* tessellation disabled */
3660
3661 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3662 sctx->fixed_func_tcs_shader.current;
3663 }
3664
3665 static bool si_update_scratch_relocs(struct si_context *sctx)
3666 {
3667 struct si_shader *tcs = si_get_tcs_current(sctx);
3668 int r;
3669
3670 /* Update the shaders, so that they are using the latest scratch.
3671 * The scratch buffer may have been changed since these shaders were
3672 * last used, so we still need to try to update them, even if they
3673 * require scratch buffers smaller than the current size.
3674 */
3675 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3676 if (r < 0)
3677 return false;
3678 if (r == 1)
3679 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3680
3681 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3682 if (r < 0)
3683 return false;
3684 if (r == 1)
3685 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3686
3687 r = si_update_scratch_buffer(sctx, tcs);
3688 if (r < 0)
3689 return false;
3690 if (r == 1)
3691 si_pm4_bind_state(sctx, hs, tcs->pm4);
3692
3693 /* VS can be bound as LS, ES, or VS. */
3694 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3695 if (r < 0)
3696 return false;
3697 if (r == 1) {
3698 if (sctx->vs_shader.current->key.as_ls)
3699 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3700 else if (sctx->vs_shader.current->key.as_es)
3701 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3702 else if (sctx->vs_shader.current->key.as_ngg)
3703 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3704 else
3705 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3706 }
3707
3708 /* TES can be bound as ES or VS. */
3709 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3710 if (r < 0)
3711 return false;
3712 if (r == 1) {
3713 if (sctx->tes_shader.current->key.as_es)
3714 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3715 else if (sctx->tes_shader.current->key.as_ngg)
3716 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3717 else
3718 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3719 }
3720
3721 return true;
3722 }
3723
3724 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3725 {
3726 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3727 * There are 2 cases to handle:
3728 *
3729 * - If the current needed size is less than the maximum seen size,
3730 * use the maximum seen size, so that WAVESIZE remains the same.
3731 *
3732 * - If the current needed size is greater than the maximum seen size,
3733 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3734 *
3735 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3736 * Otherwise, the number of waves that can use scratch is
3737 * SPI_TMPRING_SIZE.WAVES.
3738 */
3739 unsigned bytes = 0;
3740
3741 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3742 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3743 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3744
3745 if (sctx->tes_shader.cso) {
3746 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3747 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3748 }
3749
3750 sctx->max_seen_scratch_bytes_per_wave =
3751 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3752
3753 unsigned scratch_needed_size =
3754 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3755 unsigned spi_tmpring_size;
3756
3757 if (scratch_needed_size > 0) {
3758 if (!sctx->scratch_buffer ||
3759 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3760 /* Create a bigger scratch buffer */
3761 si_resource_reference(&sctx->scratch_buffer, NULL);
3762
3763 sctx->scratch_buffer =
3764 si_aligned_buffer_create(&sctx->screen->b,
3765 SI_RESOURCE_FLAG_UNMAPPABLE,
3766 PIPE_USAGE_DEFAULT,
3767 scratch_needed_size,
3768 sctx->screen->info.pte_fragment_size);
3769 if (!sctx->scratch_buffer)
3770 return false;
3771
3772 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3773 si_context_add_resource_size(sctx,
3774 &sctx->scratch_buffer->b.b);
3775 }
3776
3777 if (!si_update_scratch_relocs(sctx))
3778 return false;
3779 }
3780
3781 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3782 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3783 "scratch size should already be aligned correctly.");
3784
3785 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3786 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3787 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3788 sctx->spi_tmpring_size = spi_tmpring_size;
3789 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3790 }
3791 return true;
3792 }
3793
3794 static void si_init_tess_factor_ring(struct si_context *sctx)
3795 {
3796 assert(!sctx->tess_rings);
3797 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3798
3799 /* The address must be aligned to 2^19, because the shader only
3800 * receives the high 13 bits.
3801 */
3802 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3803 SI_RESOURCE_FLAG_32BIT,
3804 PIPE_USAGE_DEFAULT,
3805 sctx->screen->tess_offchip_ring_size +
3806 sctx->screen->tess_factor_ring_size,
3807 1 << 19);
3808 if (!sctx->tess_rings)
3809 return;
3810
3811 si_init_config_add_vgt_flush(sctx);
3812
3813 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3814 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3815
3816 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3817 sctx->screen->tess_offchip_ring_size;
3818
3819 /* Append these registers to the init config state. */
3820 if (sctx->chip_class >= GFX7) {
3821 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3822 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3823 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3824 factor_va >> 8);
3825 if (sctx->chip_class >= GFX10)
3826 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3827 S_030984_BASE_HI(factor_va >> 40));
3828 else if (sctx->chip_class == GFX9)
3829 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3830 S_030944_BASE_HI(factor_va >> 40));
3831 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3832 sctx->screen->vgt_hs_offchip_param);
3833 } else {
3834 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3835 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3836 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3837 factor_va >> 8);
3838 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3839 sctx->screen->vgt_hs_offchip_param);
3840 }
3841
3842 /* Flush the context to re-emit the init_config state.
3843 * This is done only once in a lifetime of a context.
3844 */
3845 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3846 sctx->initial_gfx_cs_size = 0; /* force flush */
3847 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3848 }
3849
3850 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3851 union si_vgt_stages_key key)
3852 {
3853 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3854 uint32_t stages = 0;
3855
3856 if (key.u.tess) {
3857 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3858 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3859
3860 if (key.u.gs)
3861 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3862 S_028B54_GS_EN(1);
3863 else if (key.u.ngg)
3864 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3865 else
3866 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3867 } else if (key.u.gs) {
3868 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3869 S_028B54_GS_EN(1);
3870 } else if (key.u.ngg) {
3871 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3872 }
3873
3874 if (key.u.ngg) {
3875 stages |= S_028B54_PRIMGEN_EN(1) |
3876 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3877 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3878 } else if (key.u.gs)
3879 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3880
3881 if (screen->info.chip_class >= GFX9)
3882 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3883
3884 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3885 stages |= S_028B54_HS_W32_EN(1) |
3886 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3887 S_028B54_VS_W32_EN(1);
3888 }
3889
3890 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3891 return pm4;
3892 }
3893
3894 static void si_update_vgt_shader_config(struct si_context *sctx,
3895 union si_vgt_stages_key key)
3896 {
3897 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3898
3899 if (unlikely(!*pm4))
3900 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3901 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3902 }
3903
3904 bool si_update_shaders(struct si_context *sctx)
3905 {
3906 struct pipe_context *ctx = (struct pipe_context*)sctx;
3907 struct si_compiler_ctx_state compiler_state;
3908 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3909 struct si_shader *old_vs = si_get_vs_state(sctx);
3910 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3911 struct si_shader *old_ps = sctx->ps_shader.current;
3912 union si_vgt_stages_key key;
3913 unsigned old_spi_shader_col_format =
3914 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3915 int r;
3916
3917 if (!sctx->compiler.passes)
3918 si_init_compiler(sctx->screen, &sctx->compiler);
3919
3920 compiler_state.compiler = &sctx->compiler;
3921 compiler_state.debug = sctx->debug;
3922 compiler_state.is_debug_context = sctx->is_debug;
3923
3924 key.index = 0;
3925
3926 if (sctx->tes_shader.cso)
3927 key.u.tess = 1;
3928 if (sctx->gs_shader.cso)
3929 key.u.gs = 1;
3930
3931 if (sctx->ngg) {
3932 key.u.ngg = 1;
3933 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3934 }
3935
3936 /* Update TCS and TES. */
3937 if (sctx->tes_shader.cso) {
3938 if (!sctx->tess_rings) {
3939 si_init_tess_factor_ring(sctx);
3940 if (!sctx->tess_rings)
3941 return false;
3942 }
3943
3944 if (sctx->tcs_shader.cso) {
3945 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3946 &compiler_state);
3947 if (r)
3948 return false;
3949 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3950 } else {
3951 if (!sctx->fixed_func_tcs_shader.cso) {
3952 sctx->fixed_func_tcs_shader.cso =
3953 si_create_fixed_func_tcs(sctx);
3954 if (!sctx->fixed_func_tcs_shader.cso)
3955 return false;
3956 }
3957
3958 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3959 key, &compiler_state);
3960 if (r)
3961 return false;
3962 si_pm4_bind_state(sctx, hs,
3963 sctx->fixed_func_tcs_shader.current->pm4);
3964 }
3965
3966 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3967 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3968 if (r)
3969 return false;
3970
3971 if (sctx->gs_shader.cso) {
3972 /* TES as ES */
3973 assert(sctx->chip_class <= GFX8);
3974 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3975 } else if (key.u.ngg) {
3976 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3977 } else {
3978 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3979 }
3980 }
3981 } else {
3982 if (sctx->chip_class <= GFX8)
3983 si_pm4_bind_state(sctx, ls, NULL);
3984 si_pm4_bind_state(sctx, hs, NULL);
3985 }
3986
3987 /* Update GS. */
3988 if (sctx->gs_shader.cso) {
3989 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3990 if (r)
3991 return false;
3992 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3993 if (!key.u.ngg) {
3994 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3995
3996 if (!si_update_gs_ring_buffers(sctx))
3997 return false;
3998 } else {
3999 si_pm4_bind_state(sctx, vs, NULL);
4000 }
4001 } else {
4002 if (!key.u.ngg) {
4003 si_pm4_bind_state(sctx, gs, NULL);
4004 if (sctx->chip_class <= GFX8)
4005 si_pm4_bind_state(sctx, es, NULL);
4006 }
4007 }
4008
4009 /* Update VS. */
4010 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
4011 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
4012 if (r)
4013 return false;
4014
4015 if (!key.u.tess && !key.u.gs) {
4016 if (key.u.ngg) {
4017 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
4018 si_pm4_bind_state(sctx, vs, NULL);
4019 } else {
4020 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4021 }
4022 } else if (sctx->tes_shader.cso) {
4023 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4024 } else {
4025 assert(sctx->gs_shader.cso);
4026 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4027 }
4028 }
4029
4030 /* This must be done after the shader variant is selected. */
4031 if (sctx->ngg)
4032 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(si_get_vs(sctx)->current);
4033
4034 si_update_vgt_shader_config(sctx, key);
4035
4036 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4037 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4038
4039 if (sctx->ps_shader.cso) {
4040 unsigned db_shader_control;
4041
4042 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4043 if (r)
4044 return false;
4045 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4046
4047 db_shader_control =
4048 sctx->ps_shader.cso->db_shader_control |
4049 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4050
4051 if (si_pm4_state_changed(sctx, ps) ||
4052 si_pm4_state_changed(sctx, vs) ||
4053 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4054 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4055 sctx->flatshade != rs->flatshade) {
4056 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4057 sctx->flatshade = rs->flatshade;
4058 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4059 }
4060
4061 if (sctx->screen->info.rbplus_allowed &&
4062 si_pm4_state_changed(sctx, ps) &&
4063 (!old_ps ||
4064 old_spi_shader_col_format !=
4065 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4066 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4067
4068 if (sctx->ps_db_shader_control != db_shader_control) {
4069 sctx->ps_db_shader_control = db_shader_control;
4070 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4071 if (sctx->screen->dpbb_allowed)
4072 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4073 }
4074
4075 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4076 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4077 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4078
4079 if (sctx->chip_class == GFX6)
4080 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4081
4082 if (sctx->framebuffer.nr_samples <= 1)
4083 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4084 }
4085 }
4086
4087 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4088 si_pm4_state_enabled_and_changed(sctx, hs) ||
4089 si_pm4_state_enabled_and_changed(sctx, es) ||
4090 si_pm4_state_enabled_and_changed(sctx, gs) ||
4091 si_pm4_state_enabled_and_changed(sctx, vs) ||
4092 si_pm4_state_enabled_and_changed(sctx, ps)) {
4093 if (!si_update_spi_tmpring_size(sctx))
4094 return false;
4095 }
4096
4097 if (sctx->chip_class >= GFX7) {
4098 if (si_pm4_state_enabled_and_changed(sctx, ls))
4099 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4100 else if (!sctx->queued.named.ls)
4101 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4102
4103 if (si_pm4_state_enabled_and_changed(sctx, hs))
4104 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4105 else if (!sctx->queued.named.hs)
4106 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4107
4108 if (si_pm4_state_enabled_and_changed(sctx, es))
4109 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4110 else if (!sctx->queued.named.es)
4111 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4112
4113 if (si_pm4_state_enabled_and_changed(sctx, gs))
4114 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4115 else if (!sctx->queued.named.gs)
4116 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4117
4118 if (si_pm4_state_enabled_and_changed(sctx, vs))
4119 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4120 else if (!sctx->queued.named.vs)
4121 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4122
4123 if (si_pm4_state_enabled_and_changed(sctx, ps))
4124 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4125 else if (!sctx->queued.named.ps)
4126 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4127 }
4128
4129 sctx->do_update_shaders = false;
4130 return true;
4131 }
4132
4133 static void si_emit_scratch_state(struct si_context *sctx)
4134 {
4135 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4136
4137 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4138 sctx->spi_tmpring_size);
4139
4140 if (sctx->scratch_buffer) {
4141 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4142 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4143 RADEON_PRIO_SCRATCH_BUFFER);
4144 }
4145 }
4146
4147 void si_init_shader_functions(struct si_context *sctx)
4148 {
4149 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4150 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4151
4152 sctx->b.create_vs_state = si_create_shader_selector;
4153 sctx->b.create_tcs_state = si_create_shader_selector;
4154 sctx->b.create_tes_state = si_create_shader_selector;
4155 sctx->b.create_gs_state = si_create_shader_selector;
4156 sctx->b.create_fs_state = si_create_shader_selector;
4157
4158 sctx->b.bind_vs_state = si_bind_vs_shader;
4159 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4160 sctx->b.bind_tes_state = si_bind_tes_shader;
4161 sctx->b.bind_gs_state = si_bind_gs_shader;
4162 sctx->b.bind_fs_state = si_bind_ps_shader;
4163
4164 sctx->b.delete_vs_state = si_delete_shader_selector;
4165 sctx->b.delete_tcs_state = si_delete_shader_selector;
4166 sctx->b.delete_tes_state = si_delete_shader_selector;
4167 sctx->b.delete_gs_state = si_delete_shader_selector;
4168 sctx->b.delete_fs_state = si_delete_shader_selector;
4169 }