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radeonsi/gfx10: rewrite late alloc computation
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "util/hash_table.h"
31 #include "util/crc32.h"
32 #include "util/u_async_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_prim.h"
35
36 #include "util/disk_cache.h"
37 #include "util/mesa-sha1.h"
38 #include "ac_exp_param.h"
39 #include "ac_shader_util.h"
40
41 /* SHADER_CACHE */
42
43 /**
44 * Return the IR key for the shader cache.
45 */
46 void si_get_ir_cache_key(struct si_shader_selector *sel, bool ngg, bool es,
47 unsigned char ir_sha1_cache_key[20])
48 {
49 struct blob blob = {};
50 unsigned ir_size;
51 void *ir_binary;
52
53 if (sel->nir_binary) {
54 ir_binary = sel->nir_binary;
55 ir_size = sel->nir_size;
56 } else {
57 assert(sel->nir);
58
59 blob_init(&blob);
60 nir_serialize(&blob, sel->nir, true);
61 ir_binary = blob.data;
62 ir_size = blob.size;
63 }
64
65 /* These settings affect the compilation, but they are not derived
66 * from the input shader IR.
67 */
68 unsigned shader_variant_flags = 0;
69
70 if (ngg)
71 shader_variant_flags |= 1 << 0;
72 if (sel->nir)
73 shader_variant_flags |= 1 << 1;
74 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
75 shader_variant_flags |= 1 << 2;
76 if (sel->force_correct_derivs_after_kill)
77 shader_variant_flags |= 1 << 3;
78
79 struct mesa_sha1 ctx;
80 _mesa_sha1_init(&ctx);
81 _mesa_sha1_update(&ctx, &shader_variant_flags, 4);
82 _mesa_sha1_update(&ctx, ir_binary, ir_size);
83 if (sel->type == PIPE_SHADER_VERTEX ||
84 sel->type == PIPE_SHADER_TESS_EVAL ||
85 sel->type == PIPE_SHADER_GEOMETRY)
86 _mesa_sha1_update(&ctx, &sel->so, sizeof(sel->so));
87 _mesa_sha1_final(&ctx, ir_sha1_cache_key);
88
89 if (ir_binary == blob.data)
90 blob_finish(&blob);
91 }
92
93 /** Copy "data" to "ptr" and return the next dword following copied data. */
94 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
95 {
96 /* data may be NULL if size == 0 */
97 if (size)
98 memcpy(ptr, data, size);
99 ptr += DIV_ROUND_UP(size, 4);
100 return ptr;
101 }
102
103 /** Read data from "ptr". Return the next dword following the data. */
104 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
105 {
106 memcpy(data, ptr, size);
107 ptr += DIV_ROUND_UP(size, 4);
108 return ptr;
109 }
110
111 /**
112 * Write the size as uint followed by the data. Return the next dword
113 * following the copied data.
114 */
115 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
116 {
117 *ptr++ = size;
118 return write_data(ptr, data, size);
119 }
120
121 /**
122 * Read the size as uint followed by the data. Return both via parameters.
123 * Return the next dword following the data.
124 */
125 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
126 {
127 *size = *ptr++;
128 assert(*data == NULL);
129 if (!*size)
130 return ptr;
131 *data = malloc(*size);
132 return read_data(ptr, *data, *size);
133 }
134
135 /**
136 * Return the shader binary in a buffer. The first 4 bytes contain its size
137 * as integer.
138 */
139 static void *si_get_shader_binary(struct si_shader *shader)
140 {
141 /* There is always a size of data followed by the data itself. */
142 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
143 strlen(shader->binary.llvm_ir_string) + 1 : 0;
144
145 /* Refuse to allocate overly large buffers and guard against integer
146 * overflow. */
147 if (shader->binary.elf_size > UINT_MAX / 4 ||
148 llvm_ir_size > UINT_MAX / 4)
149 return NULL;
150
151 unsigned size =
152 4 + /* total size */
153 4 + /* CRC32 of the data below */
154 align(sizeof(shader->config), 4) +
155 align(sizeof(shader->info), 4) +
156 4 + align(shader->binary.elf_size, 4) +
157 4 + align(llvm_ir_size, 4);
158 void *buffer = CALLOC(1, size);
159 uint32_t *ptr = (uint32_t*)buffer;
160
161 if (!buffer)
162 return NULL;
163
164 *ptr++ = size;
165 ptr++; /* CRC32 is calculated at the end. */
166
167 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
168 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
169 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
170 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
171 assert((char *)ptr - (char *)buffer == size);
172
173 /* Compute CRC32. */
174 ptr = (uint32_t*)buffer;
175 ptr++;
176 *ptr = util_hash_crc32(ptr + 1, size - 8);
177
178 return buffer;
179 }
180
181 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
182 {
183 uint32_t *ptr = (uint32_t*)binary;
184 uint32_t size = *ptr++;
185 uint32_t crc32 = *ptr++;
186 unsigned chunk_size;
187 unsigned elf_size;
188
189 if (util_hash_crc32(ptr, size - 8) != crc32) {
190 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
191 return false;
192 }
193
194 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
195 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
196 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
197 &elf_size);
198 shader->binary.elf_size = elf_size;
199 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
200
201 return true;
202 }
203
204 /**
205 * Insert a shader into the cache. It's assumed the shader is not in the cache.
206 * Use si_shader_cache_load_shader before calling this.
207 */
208 void si_shader_cache_insert_shader(struct si_screen *sscreen,
209 unsigned char ir_sha1_cache_key[20],
210 struct si_shader *shader,
211 bool insert_into_disk_cache)
212 {
213 void *hw_binary;
214 struct hash_entry *entry;
215 uint8_t key[CACHE_KEY_SIZE];
216
217 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
218 if (entry)
219 return; /* already added */
220
221 hw_binary = si_get_shader_binary(shader);
222 if (!hw_binary)
223 return;
224
225 if (_mesa_hash_table_insert(sscreen->shader_cache,
226 mem_dup(ir_sha1_cache_key, 20),
227 hw_binary) == NULL) {
228 FREE(hw_binary);
229 return;
230 }
231
232 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
233 disk_cache_compute_key(sscreen->disk_shader_cache,
234 ir_sha1_cache_key, 20, key);
235 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
236 *((uint32_t *) hw_binary), NULL);
237 }
238 }
239
240 bool si_shader_cache_load_shader(struct si_screen *sscreen,
241 unsigned char ir_sha1_cache_key[20],
242 struct si_shader *shader)
243 {
244 struct hash_entry *entry =
245 _mesa_hash_table_search(sscreen->shader_cache, ir_sha1_cache_key);
246 if (!entry) {
247 if (sscreen->disk_shader_cache) {
248 unsigned char sha1[CACHE_KEY_SIZE];
249
250 disk_cache_compute_key(sscreen->disk_shader_cache,
251 ir_sha1_cache_key, 20, sha1);
252
253 size_t binary_size;
254 uint8_t *buffer =
255 disk_cache_get(sscreen->disk_shader_cache,
256 sha1, &binary_size);
257 if (!buffer)
258 return false;
259
260 if (binary_size < sizeof(uint32_t) ||
261 *((uint32_t*)buffer) != binary_size) {
262 /* Something has gone wrong discard the item
263 * from the cache and rebuild/link from
264 * source.
265 */
266 assert(!"Invalid radeonsi shader disk cache "
267 "item!");
268
269 disk_cache_remove(sscreen->disk_shader_cache,
270 sha1);
271 free(buffer);
272
273 return false;
274 }
275
276 if (!si_load_shader_binary(shader, buffer)) {
277 free(buffer);
278 return false;
279 }
280 free(buffer);
281
282 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
283 shader, false);
284 } else {
285 return false;
286 }
287 } else {
288 if (!si_load_shader_binary(shader, entry->data))
289 return false;
290 }
291 p_atomic_inc(&sscreen->num_shader_cache_hits);
292 return true;
293 }
294
295 static uint32_t si_shader_cache_key_hash(const void *key)
296 {
297 /* Take the first dword of SHA1. */
298 return *(uint32_t*)key;
299 }
300
301 static bool si_shader_cache_key_equals(const void *a, const void *b)
302 {
303 /* Compare SHA1s. */
304 return memcmp(a, b, 20) == 0;
305 }
306
307 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
308 {
309 FREE((void*)entry->key);
310 FREE(entry->data);
311 }
312
313 bool si_init_shader_cache(struct si_screen *sscreen)
314 {
315 (void) simple_mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
316 sscreen->shader_cache =
317 _mesa_hash_table_create(NULL,
318 si_shader_cache_key_hash,
319 si_shader_cache_key_equals);
320
321 return sscreen->shader_cache != NULL;
322 }
323
324 void si_destroy_shader_cache(struct si_screen *sscreen)
325 {
326 if (sscreen->shader_cache)
327 _mesa_hash_table_destroy(sscreen->shader_cache,
328 si_destroy_shader_cache_entry);
329 simple_mtx_destroy(&sscreen->shader_cache_mutex);
330 }
331
332 /* SHADER STATES */
333
334 static void si_set_tesseval_regs(struct si_screen *sscreen,
335 const struct si_shader_selector *tes,
336 struct si_pm4_state *pm4)
337 {
338 const struct si_shader_info *info = &tes->info;
339 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
340 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
341 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
342 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
343 unsigned type, partitioning, topology, distribution_mode;
344
345 switch (tes_prim_mode) {
346 case PIPE_PRIM_LINES:
347 type = V_028B6C_TESS_ISOLINE;
348 break;
349 case PIPE_PRIM_TRIANGLES:
350 type = V_028B6C_TESS_TRIANGLE;
351 break;
352 case PIPE_PRIM_QUADS:
353 type = V_028B6C_TESS_QUAD;
354 break;
355 default:
356 assert(0);
357 return;
358 }
359
360 switch (tes_spacing) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
362 partitioning = V_028B6C_PART_FRAC_ODD;
363 break;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
365 partitioning = V_028B6C_PART_FRAC_EVEN;
366 break;
367 case PIPE_TESS_SPACING_EQUAL:
368 partitioning = V_028B6C_PART_INTEGER;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 if (tes_point_mode)
376 topology = V_028B6C_OUTPUT_POINT;
377 else if (tes_prim_mode == PIPE_PRIM_LINES)
378 topology = V_028B6C_OUTPUT_LINE;
379 else if (tes_vertex_order_cw)
380 /* for some reason, this must be the other way around */
381 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
382 else
383 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
384
385 if (sscreen->info.has_distributed_tess) {
386 if (sscreen->info.family == CHIP_FIJI ||
387 sscreen->info.family >= CHIP_POLARIS10)
388 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
389 else
390 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
391 } else
392 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
393
394 assert(pm4->shader);
395 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
396 S_028B6C_PARTITIONING(partitioning) |
397 S_028B6C_TOPOLOGY(topology) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
399 }
400
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
403 *
404 * Possible VGT configurations and which state should set the register:
405 *
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
408 * VS as VS | VS | 30
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 *
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 */
415 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
416 struct si_shader_selector *sel,
417 struct si_shader *shader,
418 struct si_pm4_state *pm4)
419 {
420 unsigned type = sel->type;
421
422 if (sscreen->info.family < CHIP_POLARIS10 ||
423 sscreen->info.chip_class >= GFX10)
424 return;
425
426 /* VS as VS, or VS as ES: */
427 if ((type == PIPE_SHADER_VERTEX &&
428 (!shader ||
429 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
430 /* TES as VS, or TES as ES: */
431 type == PIPE_SHADER_TESS_EVAL) {
432 unsigned vtx_reuse_depth = 30;
433
434 if (type == PIPE_SHADER_TESS_EVAL &&
435 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD)
437 vtx_reuse_depth = 14;
438
439 assert(pm4->shader);
440 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
441 }
442 }
443
444 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
445 {
446 if (shader->pm4)
447 si_pm4_clear_state(shader->pm4);
448 else
449 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
450
451 if (shader->pm4) {
452 shader->pm4->shader = shader;
453 return shader->pm4;
454 } else {
455 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
456 return NULL;
457 }
458 }
459
460 static unsigned si_get_num_vs_user_sgprs(struct si_shader *shader,
461 unsigned num_always_on_user_sgprs)
462 {
463 struct si_shader_selector *vs = shader->previous_stage_sel ?
464 shader->previous_stage_sel : shader->selector;
465 unsigned num_vbos_in_user_sgprs = vs->num_vbos_in_user_sgprs;
466
467 /* 1 SGPR is reserved for the vertex buffer pointer. */
468 assert(num_always_on_user_sgprs <= SI_SGPR_VS_VB_DESCRIPTOR_FIRST - 1);
469
470 if (num_vbos_in_user_sgprs)
471 return SI_SGPR_VS_VB_DESCRIPTOR_FIRST + num_vbos_in_user_sgprs * 4;
472
473 /* Add the pointer to VBO descriptors. */
474 return num_always_on_user_sgprs + 1;
475 }
476
477 /* Return VGPR_COMP_CNT for the API vertex shader. This can be hw LS, LSHS, ES, ESGS, VS. */
478 static unsigned si_get_vs_vgpr_comp_cnt(struct si_screen *sscreen,
479 struct si_shader *shader, bool legacy_vs_prim_id)
480 {
481 assert(shader->selector->type == PIPE_SHADER_VERTEX ||
482 (shader->previous_stage_sel &&
483 shader->previous_stage_sel->type == PIPE_SHADER_VERTEX));
484
485 /* GFX6-9 LS (VertexID, RelAutoindex, InstanceID / StepRate0(==1), ...).
486 * GFX6-9 ES,VS (VertexID, InstanceID / StepRate0(==1), VSPrimID, ...)
487 * GFX10 LS (VertexID, RelAutoindex, UserVGPR1, InstanceID).
488 * GFX10 ES,VS (VertexID, UserVGPR0, UserVGPR1 or VSPrimID, UserVGPR2 or InstanceID)
489 */
490 bool is_ls = shader->selector->type == PIPE_SHADER_TESS_CTRL || shader->key.as_ls;
491
492 if (sscreen->info.chip_class >= GFX10 && shader->info.uses_instanceid)
493 return 3;
494 else if ((is_ls && shader->info.uses_instanceid) || legacy_vs_prim_id)
495 return 2;
496 else if (is_ls || shader->info.uses_instanceid)
497 return 1;
498 else
499 return 0;
500 }
501
502 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
503 {
504 struct si_pm4_state *pm4;
505 uint64_t va;
506
507 assert(sscreen->info.chip_class <= GFX8);
508
509 pm4 = si_get_shader_pm4_state(shader);
510 if (!pm4)
511 return;
512
513 va = shader->bo->gpu_address;
514 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
515
516 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
517 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
518
519 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
520 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
521 S_00B528_VGPR_COMP_CNT(si_get_vs_vgpr_comp_cnt(sscreen, shader, false)) |
522 S_00B528_DX10_CLAMP(1) |
523 S_00B528_FLOAT_MODE(shader->config.float_mode);
524 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR)) |
525 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
526 }
527
528 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
529 {
530 struct si_pm4_state *pm4;
531 uint64_t va;
532
533 pm4 = si_get_shader_pm4_state(shader);
534 if (!pm4)
535 return;
536
537 va = shader->bo->gpu_address;
538 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
539
540 if (sscreen->info.chip_class >= GFX9) {
541 if (sscreen->info.chip_class >= GFX10) {
542 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
543 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
544 } else {
545 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
546 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
547 }
548
549 unsigned num_user_sgprs =
550 si_get_num_vs_user_sgprs(shader, GFX9_TCS_NUM_USER_SGPR);
551
552 shader->config.rsrc2 =
553 S_00B42C_USER_SGPR(num_user_sgprs) |
554 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
555
556 if (sscreen->info.chip_class >= GFX10)
557 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
558 else
559 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
560 } else {
561 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
562 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
563
564 shader->config.rsrc2 =
565 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
566 S_00B42C_OC_LDS_EN(1) |
567 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
568 }
569
570 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
571 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
572 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
573 (sscreen->info.chip_class <= GFX9 ?
574 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
575 S_00B428_DX10_CLAMP(1) |
576 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
577 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
578 S_00B428_FLOAT_MODE(shader->config.float_mode) |
579 S_00B428_LS_VGPR_COMP_CNT(sscreen->info.chip_class >= GFX9 ?
580 si_get_vs_vgpr_comp_cnt(sscreen, shader, false) : 0));
581
582 if (sscreen->info.chip_class <= GFX8) {
583 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
584 shader->config.rsrc2);
585 }
586 }
587
588 static void si_emit_shader_es(struct si_context *sctx)
589 {
590 struct si_shader *shader = sctx->queued.named.es->shader;
591 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
592
593 if (!shader)
594 return;
595
596 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
597 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
598 shader->selector->esgs_itemsize / 4);
599
600 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
601 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
602 SI_TRACKED_VGT_TF_PARAM,
603 shader->vgt_tf_param);
604
605 if (shader->vgt_vertex_reuse_block_cntl)
606 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
607 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
608 shader->vgt_vertex_reuse_block_cntl);
609
610 if (initial_cdw != sctx->gfx_cs->current.cdw)
611 sctx->context_roll = true;
612 }
613
614 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
615 {
616 struct si_pm4_state *pm4;
617 unsigned num_user_sgprs;
618 unsigned vgpr_comp_cnt;
619 uint64_t va;
620 unsigned oc_lds_en;
621
622 assert(sscreen->info.chip_class <= GFX8);
623
624 pm4 = si_get_shader_pm4_state(shader);
625 if (!pm4)
626 return;
627
628 pm4->atom.emit = si_emit_shader_es;
629 va = shader->bo->gpu_address;
630 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
631
632 if (shader->selector->type == PIPE_SHADER_VERTEX) {
633 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
634 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
635 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
636 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
637 num_user_sgprs = SI_TES_NUM_USER_SGPR;
638 } else
639 unreachable("invalid shader selector type");
640
641 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
642
643 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
644 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
645 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
646 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
647 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
648 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
649 S_00B328_DX10_CLAMP(1) |
650 S_00B328_FLOAT_MODE(shader->config.float_mode));
651 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
652 S_00B32C_USER_SGPR(num_user_sgprs) |
653 S_00B32C_OC_LDS_EN(oc_lds_en) |
654 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
655
656 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
657 si_set_tesseval_regs(sscreen, shader->selector, pm4);
658
659 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
660 }
661
662 void gfx9_get_gs_info(struct si_shader_selector *es,
663 struct si_shader_selector *gs,
664 struct gfx9_gs_info *out)
665 {
666 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
667 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
668 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
669 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
670
671 /* All these are in dwords: */
672 /* We can't allow using the whole LDS, because GS waves compete with
673 * other shader stages for LDS space. */
674 const unsigned max_lds_size = 8 * 1024;
675 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
676 unsigned esgs_lds_size;
677
678 /* All these are per subgroup: */
679 const unsigned max_out_prims = 32 * 1024;
680 const unsigned max_es_verts = 255;
681 const unsigned ideal_gs_prims = 64;
682 unsigned max_gs_prims, gs_prims;
683 unsigned min_es_verts, es_verts, worst_case_es_verts;
684
685 if (uses_adjacency || gs_num_invocations > 1)
686 max_gs_prims = 127 / gs_num_invocations;
687 else
688 max_gs_prims = 255;
689
690 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
691 * Make sure we don't go over the maximum value.
692 */
693 if (gs->gs_max_out_vertices > 0) {
694 max_gs_prims = MIN2(max_gs_prims,
695 max_out_prims /
696 (gs->gs_max_out_vertices * gs_num_invocations));
697 }
698 assert(max_gs_prims > 0);
699
700 /* If the primitive has adjacency, halve the number of vertices
701 * that will be reused in multiple primitives.
702 */
703 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
704
705 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
706 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
707
708 /* Compute ESGS LDS size based on the worst case number of ES vertices
709 * needed to create the target number of GS prims per subgroup.
710 */
711 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
712
713 /* If total LDS usage is too big, refactor partitions based on ratio
714 * of ESGS item sizes.
715 */
716 if (esgs_lds_size > max_lds_size) {
717 /* Our target GS Prims Per Subgroup was too large. Calculate
718 * the maximum number of GS Prims Per Subgroup that will fit
719 * into LDS, capped by the maximum that the hardware can support.
720 */
721 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
722 max_gs_prims);
723 assert(gs_prims > 0);
724 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
725 max_es_verts);
726
727 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
728 assert(esgs_lds_size <= max_lds_size);
729 }
730
731 /* Now calculate remaining ESGS information. */
732 if (esgs_lds_size)
733 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
734 else
735 es_verts = max_es_verts;
736
737 /* Vertices for adjacency primitives are not always reused, so restore
738 * it for ES_VERTS_PER_SUBGRP.
739 */
740 min_es_verts = gs->gs_input_verts_per_prim;
741
742 /* For normal primitives, the VGT only checks if they are past the ES
743 * verts per subgroup after allocating a full GS primitive and if they
744 * are, kick off a new subgroup. But if those additional ES verts are
745 * unique (e.g. not reused) we need to make sure there is enough LDS
746 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
747 */
748 es_verts -= min_es_verts - 1;
749
750 out->es_verts_per_subgroup = es_verts;
751 out->gs_prims_per_subgroup = gs_prims;
752 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
753 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
754 gs->gs_max_out_vertices;
755 out->esgs_ring_size = 4 * esgs_lds_size;
756
757 assert(out->max_prims_per_subgroup <= max_out_prims);
758 }
759
760 static void si_emit_shader_gs(struct si_context *sctx)
761 {
762 struct si_shader *shader = sctx->queued.named.gs->shader;
763 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
764
765 if (!shader)
766 return;
767
768 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
769 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
770 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
771 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
772 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
773 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
774 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
775
776 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
777 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
778 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
779 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
780
781 /* R_028B38_VGT_GS_MAX_VERT_OUT */
782 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
783 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
784 shader->ctx_reg.gs.vgt_gs_max_vert_out);
785
786 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
787 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
788 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
789 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
790 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
791 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
792 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
793 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
794
795 /* R_028B90_VGT_GS_INSTANCE_CNT */
796 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
797 SI_TRACKED_VGT_GS_INSTANCE_CNT,
798 shader->ctx_reg.gs.vgt_gs_instance_cnt);
799
800 if (sctx->chip_class >= GFX9) {
801 /* R_028A44_VGT_GS_ONCHIP_CNTL */
802 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
803 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
804 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
805 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
806 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
807 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
808 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
809 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
810 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
811 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
812 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
813
814 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
815 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
816 SI_TRACKED_VGT_TF_PARAM,
817 shader->vgt_tf_param);
818 if (shader->vgt_vertex_reuse_block_cntl)
819 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
820 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
821 shader->vgt_vertex_reuse_block_cntl);
822 }
823
824 if (initial_cdw != sctx->gfx_cs->current.cdw)
825 sctx->context_roll = true;
826 }
827
828 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
829 {
830 struct si_shader_selector *sel = shader->selector;
831 const ubyte *num_components = sel->info.num_stream_output_components;
832 unsigned gs_num_invocations = sel->gs_num_invocations;
833 struct si_pm4_state *pm4;
834 uint64_t va;
835 unsigned max_stream = sel->max_gs_stream;
836 unsigned offset;
837
838 pm4 = si_get_shader_pm4_state(shader);
839 if (!pm4)
840 return;
841
842 pm4->atom.emit = si_emit_shader_gs;
843
844 offset = num_components[0] * sel->gs_max_out_vertices;
845 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
846
847 if (max_stream >= 1)
848 offset += num_components[1] * sel->gs_max_out_vertices;
849 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
850
851 if (max_stream >= 2)
852 offset += num_components[2] * sel->gs_max_out_vertices;
853 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
854
855 if (max_stream >= 3)
856 offset += num_components[3] * sel->gs_max_out_vertices;
857 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
858
859 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
860 assert(offset < (1 << 15));
861
862 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
863
864 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
865 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
866 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
867 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
868
869 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
870 S_028B90_ENABLE(gs_num_invocations > 0);
871
872 va = shader->bo->gpu_address;
873 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
874
875 if (sscreen->info.chip_class >= GFX9) {
876 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
877 unsigned es_type = shader->key.part.gs.es->type;
878 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
879
880 if (es_type == PIPE_SHADER_VERTEX) {
881 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
882 } else if (es_type == PIPE_SHADER_TESS_EVAL)
883 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
884 else
885 unreachable("invalid shader selector type");
886
887 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
888 * VGPR[0:4] are always loaded.
889 */
890 if (sel->info.uses_invocationid)
891 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
892 else if (sel->info.uses_primid)
893 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
894 else if (input_prim >= PIPE_PRIM_TRIANGLES)
895 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
896 else
897 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
898
899 unsigned num_user_sgprs;
900 if (es_type == PIPE_SHADER_VERTEX)
901 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
902 else
903 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
904
905 if (sscreen->info.chip_class >= GFX10) {
906 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
907 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
908 } else {
909 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
910 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
911 }
912
913 uint32_t rsrc1 =
914 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
915 S_00B228_DX10_CLAMP(1) |
916 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
917 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
918 S_00B228_FLOAT_MODE(shader->config.float_mode) |
919 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
920 uint32_t rsrc2 =
921 S_00B22C_USER_SGPR(num_user_sgprs) |
922 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
923 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
924 S_00B22C_LDS_SIZE(shader->config.lds_size) |
925 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
926
927 if (sscreen->info.chip_class >= GFX10) {
928 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
929 } else {
930 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
931 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
932 }
933
934 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
935 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
936
937 if (sscreen->info.chip_class >= GFX10) {
938 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
939 S_00B204_CU_EN(0xffff) |
940 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(0));
941 }
942
943 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
944 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
945 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
946 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
947 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
948 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
949 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
950 shader->key.part.gs.es->esgs_itemsize / 4;
951
952 if (es_type == PIPE_SHADER_TESS_EVAL)
953 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
954
955 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
956 NULL, pm4);
957 } else {
958 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
959 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
960
961 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
962 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
963 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
964 S_00B228_DX10_CLAMP(1) |
965 S_00B228_FLOAT_MODE(shader->config.float_mode));
966 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
967 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
968 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
969 }
970 }
971
972 static void gfx10_emit_ge_pc_alloc(struct si_context *sctx, unsigned value)
973 {
974 enum si_tracked_reg reg = SI_TRACKED_GE_PC_ALLOC;
975
976 if (((sctx->tracked_regs.reg_saved >> reg) & 0x1) != 0x1 ||
977 sctx->tracked_regs.reg_value[reg] != value) {
978 struct radeon_cmdbuf *cs = sctx->gfx_cs;
979
980 if (sctx->family == CHIP_NAVI10 ||
981 sctx->family == CHIP_NAVI12 ||
982 sctx->family == CHIP_NAVI14) {
983 /* SQ_NON_EVENT must be emitted before GE_PC_ALLOC is written. */
984 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
985 radeon_emit(cs, EVENT_TYPE(V_028A90_SQ_NON_EVENT) | EVENT_INDEX(0));
986 }
987
988 radeon_set_uconfig_reg(cs, R_030980_GE_PC_ALLOC, value);
989
990 sctx->tracked_regs.reg_saved |= 0x1ull << reg;
991 sctx->tracked_regs.reg_value[reg] = value;
992 }
993 }
994
995 /* Common tail code for NGG primitive shaders. */
996 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
997 struct si_shader *shader,
998 unsigned initial_cdw)
999 {
1000 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
1001 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
1002 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
1003 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
1004 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
1005 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
1006 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1007 SI_TRACKED_VGT_PRIMITIVEID_EN,
1008 shader->ctx_reg.ngg.vgt_primitiveid_en);
1009 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1010 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1011 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
1012 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
1013 SI_TRACKED_VGT_GS_INSTANCE_CNT,
1014 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
1015 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
1016 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
1017 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
1018 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1019 SI_TRACKED_SPI_VS_OUT_CONFIG,
1020 shader->ctx_reg.ngg.spi_vs_out_config);
1021 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
1022 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
1023 shader->ctx_reg.ngg.spi_shader_idx_format,
1024 shader->ctx_reg.ngg.spi_shader_pos_format);
1025 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1026 SI_TRACKED_PA_CL_VTE_CNTL,
1027 shader->ctx_reg.ngg.pa_cl_vte_cntl);
1028 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1029 SI_TRACKED_PA_CL_NGG_CNTL,
1030 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1031
1032 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1033 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1034 shader->pa_cl_vs_out_cntl,
1035 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1036
1037 if (initial_cdw != sctx->gfx_cs->current.cdw)
1038 sctx->context_roll = true;
1039
1040 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1041 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.ngg.ge_pc_alloc);
1042 }
1043
1044 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1045 {
1046 struct si_shader *shader = sctx->queued.named.gs->shader;
1047 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1048
1049 if (!shader)
1050 return;
1051
1052 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1053 }
1054
1055 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1056 {
1057 struct si_shader *shader = sctx->queued.named.gs->shader;
1058 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1059
1060 if (!shader)
1061 return;
1062
1063 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1064 SI_TRACKED_VGT_TF_PARAM,
1065 shader->vgt_tf_param);
1066
1067 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1068 }
1069
1070 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1071 {
1072 struct si_shader *shader = sctx->queued.named.gs->shader;
1073 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1074
1075 if (!shader)
1076 return;
1077
1078 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1079 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1080 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1081
1082 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1083 }
1084
1085 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1086 {
1087 struct si_shader *shader = sctx->queued.named.gs->shader;
1088 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1089
1090 if (!shader)
1091 return;
1092
1093 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1094 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1095 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1096 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1097 SI_TRACKED_VGT_TF_PARAM,
1098 shader->vgt_tf_param);
1099
1100 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1101 }
1102
1103 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1104 {
1105 if (gs->type == PIPE_SHADER_GEOMETRY)
1106 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1107
1108 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1109 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1110 return PIPE_PRIM_POINTS;
1111 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1112 return PIPE_PRIM_LINES;
1113 return PIPE_PRIM_TRIANGLES;
1114 }
1115
1116 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1117 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1118 }
1119
1120 static unsigned si_get_vs_out_cntl(const struct si_shader_selector *sel, bool ngg)
1121 {
1122 bool misc_vec_ena =
1123 sel->info.writes_psize || (sel->info.writes_edgeflag && !ngg) ||
1124 sel->info.writes_layer || sel->info.writes_viewport_index;
1125 return S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
1126 S_02881C_USE_VTX_EDGE_FLAG(sel->info.writes_edgeflag && !ngg) |
1127 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
1128 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
1129 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
1130 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
1131 }
1132
1133 /**
1134 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1135 * in NGG mode.
1136 */
1137 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1138 {
1139 const struct si_shader_selector *gs_sel = shader->selector;
1140 const struct si_shader_info *gs_info = &gs_sel->info;
1141 enum pipe_shader_type gs_type = shader->selector->type;
1142 const struct si_shader_selector *es_sel =
1143 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1144 const struct si_shader_info *es_info = &es_sel->info;
1145 enum pipe_shader_type es_type = es_sel->type;
1146 unsigned num_user_sgprs;
1147 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1148 uint64_t va;
1149 unsigned window_space =
1150 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1151 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1152 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1153 unsigned input_prim = si_get_input_prim(gs_sel);
1154 bool break_wave_at_eoi = false;
1155 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1156 if (!pm4)
1157 return;
1158
1159 if (es_type == PIPE_SHADER_TESS_EVAL) {
1160 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1161 : gfx10_emit_shader_ngg_tess_nogs;
1162 } else {
1163 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1164 : gfx10_emit_shader_ngg_notess_nogs;
1165 }
1166
1167 va = shader->bo->gpu_address;
1168 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1169
1170 if (es_type == PIPE_SHADER_VERTEX) {
1171 es_vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, false);
1172
1173 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1174 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1175 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1176 } else {
1177 num_user_sgprs = si_get_num_vs_user_sgprs(shader, GFX9_VSGS_NUM_USER_SGPR);
1178 }
1179 } else {
1180 assert(es_type == PIPE_SHADER_TESS_EVAL);
1181 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1182 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1183
1184 if (es_enable_prim_id || gs_info->uses_primid)
1185 break_wave_at_eoi = true;
1186 }
1187
1188 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1189 * VGPR[0:4] are always loaded.
1190 *
1191 * Vertex shaders always need to load VGPR3, because they need to
1192 * pass edge flags for decomposed primitives (such as quads) to the PA
1193 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1194 */
1195 if (gs_info->uses_invocationid ||
1196 (gs_type == PIPE_SHADER_VERTEX && !gfx10_is_ngg_passthrough(shader)))
1197 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1198 else if ((gs_type == PIPE_SHADER_GEOMETRY && gs_info->uses_primid) ||
1199 (gs_type == PIPE_SHADER_VERTEX && shader->key.mono.u.vs_export_prim_id))
1200 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1201 else if (input_prim >= PIPE_PRIM_TRIANGLES && !gfx10_is_ngg_passthrough(shader))
1202 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1203 else
1204 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1205
1206 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1207 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1208 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1209 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1210 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1211 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1212 S_00B228_DX10_CLAMP(1) |
1213 S_00B228_MEM_ORDERED(1) |
1214 S_00B228_WGP_MODE(1) |
1215 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1216 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1217 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1218 S_00B22C_USER_SGPR(num_user_sgprs) |
1219 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1220 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1221 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1222 S_00B22C_LDS_SIZE(shader->config.lds_size));
1223
1224 /* Determine LATE_ALLOC_GS. */
1225 unsigned num_cu_per_sh = sscreen->info.num_good_cu_per_sh;
1226 unsigned late_alloc_wave64; /* The limit is per SH. */
1227
1228 /* For Wave32, the hw will launch twice the number of late
1229 * alloc waves, so 1 == 2x wave32.
1230 *
1231 * Don't use late alloc for NGG on Navi14 due to a hw bug.
1232 */
1233 if (sscreen->info.family == CHIP_NAVI14)
1234 late_alloc_wave64 = 0;
1235 else if (num_cu_per_sh <= 6)
1236 late_alloc_wave64 = num_cu_per_sh - 2; /* All CUs enabled */
1237 else
1238 late_alloc_wave64 = (num_cu_per_sh - 2) * 4;
1239
1240 si_pm4_set_reg(pm4, R_00B204_SPI_SHADER_PGM_RSRC4_GS,
1241 S_00B204_CU_EN(0xffff) |
1242 S_00B204_SPI_SHADER_LATE_ALLOC_GS_GFX10(late_alloc_wave64));
1243
1244 nparams = MAX2(shader->info.nr_param_exports, 1);
1245 shader->ctx_reg.ngg.spi_vs_out_config =
1246 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1247 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1248
1249 shader->ctx_reg.ngg.spi_shader_idx_format =
1250 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1251 shader->ctx_reg.ngg.spi_shader_pos_format =
1252 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1253 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1254 V_02870C_SPI_SHADER_4COMP :
1255 V_02870C_SPI_SHADER_NONE) |
1256 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1257 V_02870C_SPI_SHADER_4COMP :
1258 V_02870C_SPI_SHADER_NONE) |
1259 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1260 V_02870C_SPI_SHADER_4COMP :
1261 V_02870C_SPI_SHADER_NONE);
1262
1263 shader->ctx_reg.ngg.vgt_primitiveid_en =
1264 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1265 S_028A84_NGG_DISABLE_PROVOK_REUSE(shader->key.mono.u.vs_export_prim_id ||
1266 gs_sel->info.writes_primid);
1267
1268 if (gs_type == PIPE_SHADER_GEOMETRY) {
1269 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1270 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1271 } else {
1272 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1273 }
1274
1275 if (es_type == PIPE_SHADER_TESS_EVAL)
1276 si_set_tesseval_regs(sscreen, es_sel, pm4);
1277
1278 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1279 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1280 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1281 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1282 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1283 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1284 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1285 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1286 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1287 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1288 S_028B90_CNT(gs_num_invocations) |
1289 S_028B90_ENABLE(gs_num_invocations > 1) |
1290 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1291 shader->ngg.max_vert_out_per_gs_instance);
1292
1293 /* Always output hw-generated edge flags and pass them via the prim
1294 * export to prevent drawing lines on internal edges of decomposed
1295 * primitives (such as quads) with polygon mode = lines. Only VS needs
1296 * this.
1297 */
1298 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1299 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1300 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(gs_sel, true);
1301
1302 /* Oversubscribe PC. This improves performance when there are too many varyings. */
1303 float oversub_pc_factor = 0.25;
1304
1305 if (shader->key.opt.ngg_culling) {
1306 /* Be more aggressive with NGG culling. */
1307 if (shader->info.nr_param_exports > 4)
1308 oversub_pc_factor = 1;
1309 else if (shader->info.nr_param_exports > 2)
1310 oversub_pc_factor = 0.75;
1311 else
1312 oversub_pc_factor = 0.5;
1313 }
1314
1315 unsigned oversub_pc_lines = sscreen->info.pc_lines * oversub_pc_factor;
1316 shader->ctx_reg.ngg.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1317 S_030980_NUM_PC_LINES(oversub_pc_lines - 1);
1318
1319 shader->ge_cntl =
1320 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1321 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
1322 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1323
1324 /* Bug workaround for a possible hang with non-tessellation cases.
1325 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1326 *
1327 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1328 */
1329 if ((sscreen->info.family == CHIP_NAVI10 ||
1330 sscreen->info.family == CHIP_NAVI12 ||
1331 sscreen->info.family == CHIP_NAVI14) &&
1332 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1333 shader->ngg.hw_max_esverts != 256) {
1334 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1335
1336 if (shader->ngg.hw_max_esverts > 5) {
1337 shader->ge_cntl |=
1338 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1339 }
1340 }
1341
1342 if (window_space) {
1343 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1344 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1345 } else {
1346 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1347 S_028818_VTX_W0_FMT(1) |
1348 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1349 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1350 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1351 }
1352 }
1353
1354 static void si_emit_shader_vs(struct si_context *sctx)
1355 {
1356 struct si_shader *shader = sctx->queued.named.vs->shader;
1357 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1358
1359 if (!shader)
1360 return;
1361
1362 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1363 SI_TRACKED_VGT_GS_MODE,
1364 shader->ctx_reg.vs.vgt_gs_mode);
1365 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1366 SI_TRACKED_VGT_PRIMITIVEID_EN,
1367 shader->ctx_reg.vs.vgt_primitiveid_en);
1368
1369 if (sctx->chip_class <= GFX8) {
1370 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1371 SI_TRACKED_VGT_REUSE_OFF,
1372 shader->ctx_reg.vs.vgt_reuse_off);
1373 }
1374
1375 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1376 SI_TRACKED_SPI_VS_OUT_CONFIG,
1377 shader->ctx_reg.vs.spi_vs_out_config);
1378
1379 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1380 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1381 shader->ctx_reg.vs.spi_shader_pos_format);
1382
1383 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1384 SI_TRACKED_PA_CL_VTE_CNTL,
1385 shader->ctx_reg.vs.pa_cl_vte_cntl);
1386
1387 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1388 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1389 SI_TRACKED_VGT_TF_PARAM,
1390 shader->vgt_tf_param);
1391
1392 if (shader->vgt_vertex_reuse_block_cntl)
1393 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1394 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1395 shader->vgt_vertex_reuse_block_cntl);
1396
1397 /* Required programming for tessellation. (legacy pipeline only) */
1398 if (sctx->chip_class == GFX10 &&
1399 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1400 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1401 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1402 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1403 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1404 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1405 }
1406
1407 if (sctx->chip_class >= GFX10) {
1408 radeon_opt_set_context_reg_rmw(sctx, R_02881C_PA_CL_VS_OUT_CNTL,
1409 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS,
1410 shader->pa_cl_vs_out_cntl,
1411 SI_TRACKED_PA_CL_VS_OUT_CNTL__VS_MASK);
1412 }
1413
1414 if (initial_cdw != sctx->gfx_cs->current.cdw)
1415 sctx->context_roll = true;
1416
1417 /* GE_PC_ALLOC is not a context register, so it doesn't cause a context roll. */
1418 if (sctx->chip_class >= GFX10)
1419 gfx10_emit_ge_pc_alloc(sctx, shader->ctx_reg.vs.ge_pc_alloc);
1420 }
1421
1422 /**
1423 * Compute the state for \p shader, which will run as a vertex shader on the
1424 * hardware.
1425 *
1426 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1427 * is the copy shader.
1428 */
1429 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1430 struct si_shader_selector *gs)
1431 {
1432 const struct si_shader_info *info = &shader->selector->info;
1433 struct si_pm4_state *pm4;
1434 unsigned num_user_sgprs, vgpr_comp_cnt;
1435 uint64_t va;
1436 unsigned nparams, oc_lds_en;
1437 unsigned window_space =
1438 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1439 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1440
1441 pm4 = si_get_shader_pm4_state(shader);
1442 if (!pm4)
1443 return;
1444
1445 pm4->atom.emit = si_emit_shader_vs;
1446
1447 /* We always write VGT_GS_MODE in the VS state, because every switch
1448 * between different shader pipelines involving a different GS or no
1449 * GS at all involves a switch of the VS (different GS use different
1450 * copy shaders). On the other hand, when the API switches from a GS to
1451 * no GS and then back to the same GS used originally, the GS state is
1452 * not sent again.
1453 */
1454 if (!gs) {
1455 unsigned mode = V_028A40_GS_OFF;
1456
1457 /* PrimID needs GS scenario A. */
1458 if (enable_prim_id)
1459 mode = V_028A40_GS_SCENARIO_A;
1460
1461 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1462 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1463 } else {
1464 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1465 sscreen->info.chip_class);
1466 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1467 }
1468
1469 if (sscreen->info.chip_class <= GFX8) {
1470 /* Reuse needs to be set off if we write oViewport. */
1471 shader->ctx_reg.vs.vgt_reuse_off =
1472 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1473 }
1474
1475 va = shader->bo->gpu_address;
1476 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1477
1478 if (gs) {
1479 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1480 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1481 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1482 vgpr_comp_cnt = si_get_vs_vgpr_comp_cnt(sscreen, shader, enable_prim_id);
1483
1484 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1485 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1486 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1487 } else {
1488 num_user_sgprs = si_get_num_vs_user_sgprs(shader, SI_VS_NUM_USER_SGPR);
1489 }
1490 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1491 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1492 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1493 } else
1494 unreachable("invalid shader selector type");
1495
1496 /* VS is required to export at least one param. */
1497 nparams = MAX2(shader->info.nr_param_exports, 1);
1498 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1499
1500 if (sscreen->info.chip_class >= GFX10) {
1501 shader->ctx_reg.vs.spi_vs_out_config |=
1502 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1503 }
1504
1505 shader->ctx_reg.vs.spi_shader_pos_format =
1506 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1507 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1508 V_02870C_SPI_SHADER_4COMP :
1509 V_02870C_SPI_SHADER_NONE) |
1510 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1511 V_02870C_SPI_SHADER_4COMP :
1512 V_02870C_SPI_SHADER_NONE) |
1513 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1514 V_02870C_SPI_SHADER_4COMP :
1515 V_02870C_SPI_SHADER_NONE);
1516 shader->ctx_reg.vs.ge_pc_alloc = S_030980_OVERSUB_EN(1) |
1517 S_030980_NUM_PC_LINES(sscreen->info.pc_lines / 4 - 1);
1518 shader->pa_cl_vs_out_cntl = si_get_vs_out_cntl(shader->selector, false);
1519
1520 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1521
1522 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1523 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1524
1525 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1526 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1527 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1528 S_00B128_DX10_CLAMP(1) |
1529 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1530 S_00B128_FLOAT_MODE(shader->config.float_mode);
1531 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1532 S_00B12C_OC_LDS_EN(oc_lds_en) |
1533 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1534
1535 if (sscreen->info.chip_class >= GFX10)
1536 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
1537 else if (sscreen->info.chip_class == GFX9)
1538 rsrc2 |= S_00B12C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
1539
1540 if (sscreen->info.chip_class <= GFX9)
1541 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1542
1543 if (!sscreen->use_ngg_streamout) {
1544 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1545 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1546 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1547 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1548 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1549 }
1550
1551 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1552 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1553
1554 if (window_space)
1555 shader->ctx_reg.vs.pa_cl_vte_cntl =
1556 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1557 else
1558 shader->ctx_reg.vs.pa_cl_vte_cntl =
1559 S_028818_VTX_W0_FMT(1) |
1560 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1561 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1562 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1563
1564 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1565 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1566
1567 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1568 }
1569
1570 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1571 {
1572 struct si_shader_info *info = &ps->selector->info;
1573 unsigned num_colors = !!(info->colors_read & 0x0f) +
1574 !!(info->colors_read & 0xf0);
1575 unsigned num_interp = ps->selector->info.num_inputs +
1576 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1577
1578 assert(num_interp <= 32);
1579 return MIN2(num_interp, 32);
1580 }
1581
1582 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1583 {
1584 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1585 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1586
1587 /* If the i-th target format is set, all previous target formats must
1588 * be non-zero to avoid hangs.
1589 */
1590 for (i = 0; i < num_targets; i++)
1591 if (!(value & (0xf << (i * 4))))
1592 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1593
1594 return value;
1595 }
1596
1597 static void si_emit_shader_ps(struct si_context *sctx)
1598 {
1599 struct si_shader *shader = sctx->queued.named.ps->shader;
1600 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1601
1602 if (!shader)
1603 return;
1604
1605 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1606 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1607 SI_TRACKED_SPI_PS_INPUT_ENA,
1608 shader->ctx_reg.ps.spi_ps_input_ena,
1609 shader->ctx_reg.ps.spi_ps_input_addr);
1610
1611 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1612 SI_TRACKED_SPI_BARYC_CNTL,
1613 shader->ctx_reg.ps.spi_baryc_cntl);
1614 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1615 SI_TRACKED_SPI_PS_IN_CONTROL,
1616 shader->ctx_reg.ps.spi_ps_in_control);
1617
1618 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1619 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1620 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1621 shader->ctx_reg.ps.spi_shader_z_format,
1622 shader->ctx_reg.ps.spi_shader_col_format);
1623
1624 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1625 SI_TRACKED_CB_SHADER_MASK,
1626 shader->ctx_reg.ps.cb_shader_mask);
1627
1628 if (initial_cdw != sctx->gfx_cs->current.cdw)
1629 sctx->context_roll = true;
1630 }
1631
1632 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1633 {
1634 struct si_shader_info *info = &shader->selector->info;
1635 struct si_pm4_state *pm4;
1636 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1637 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1638 uint64_t va;
1639 unsigned input_ena = shader->config.spi_ps_input_ena;
1640
1641 /* we need to enable at least one of them, otherwise we hang the GPU */
1642 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1643 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1644 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1645 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1646 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1647 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1648 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1649 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1650 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1651 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1652 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1653 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1654 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1655 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1656
1657 /* Validate interpolation optimization flags (read as implications). */
1658 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1659 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1660 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1661 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1662 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1663 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1664 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1665 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1666 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1667 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1668 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1669 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1670 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1671 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1672 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1673 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1674 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1675 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1676
1677 /* Validate cases when the optimizations are off (read as implications). */
1678 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1679 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1680 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1681 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1682 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1683 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1684
1685 pm4 = si_get_shader_pm4_state(shader);
1686 if (!pm4)
1687 return;
1688
1689 pm4->atom.emit = si_emit_shader_ps;
1690
1691 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1692 * Possible vaules:
1693 * 0 -> Position = pixel center
1694 * 1 -> Position = pixel centroid
1695 * 2 -> Position = at sample position
1696 *
1697 * From GLSL 4.5 specification, section 7.1:
1698 * "The variable gl_FragCoord is available as an input variable from
1699 * within fragment shaders and it holds the window relative coordinates
1700 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1701 * value can be for any location within the pixel, or one of the
1702 * fragment samples. The use of centroid does not further restrict
1703 * this value to be inside the current primitive."
1704 *
1705 * Meaning that centroid has no effect and we can return anything within
1706 * the pixel. Thus, return the value at sample position, because that's
1707 * the most accurate one shaders can get.
1708 */
1709 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1710
1711 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1712 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1713 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1714
1715 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1716 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1717
1718 /* Ensure that some export memory is always allocated, for two reasons:
1719 *
1720 * 1) Correctness: The hardware ignores the EXEC mask if no export
1721 * memory is allocated, so KILL and alpha test do not work correctly
1722 * without this.
1723 * 2) Performance: Every shader needs at least a NULL export, even when
1724 * it writes no color/depth output. The NULL export instruction
1725 * stalls without this setting.
1726 *
1727 * Don't add this to CB_SHADER_MASK.
1728 *
1729 * GFX10 supports pixel shaders without exports by setting both
1730 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1731 * instructions if any are present.
1732 */
1733 if ((sscreen->info.chip_class <= GFX9 ||
1734 info->uses_kill ||
1735 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1736 !spi_shader_col_format &&
1737 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1738 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1739
1740 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1741 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1742
1743 /* Set interpolation controls. */
1744 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1745 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1746
1747 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1748 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1749 shader->ctx_reg.ps.spi_shader_z_format =
1750 ac_get_spi_shader_z_format(info->writes_z,
1751 info->writes_stencil,
1752 info->writes_samplemask);
1753 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1754 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1755
1756 va = shader->bo->gpu_address;
1757 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1758 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1759 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1760
1761 uint32_t rsrc1 =
1762 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1763 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1764 S_00B028_DX10_CLAMP(1) |
1765 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1766 S_00B028_FLOAT_MODE(shader->config.float_mode);
1767
1768 if (sscreen->info.chip_class < GFX10) {
1769 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1770 }
1771
1772 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1773 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1774 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1775 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1776 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1777 }
1778
1779 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1780 struct si_shader *shader)
1781 {
1782 switch (shader->selector->type) {
1783 case PIPE_SHADER_VERTEX:
1784 if (shader->key.as_ls)
1785 si_shader_ls(sscreen, shader);
1786 else if (shader->key.as_es)
1787 si_shader_es(sscreen, shader);
1788 else if (shader->key.as_ngg)
1789 gfx10_shader_ngg(sscreen, shader);
1790 else
1791 si_shader_vs(sscreen, shader, NULL);
1792 break;
1793 case PIPE_SHADER_TESS_CTRL:
1794 si_shader_hs(sscreen, shader);
1795 break;
1796 case PIPE_SHADER_TESS_EVAL:
1797 if (shader->key.as_es)
1798 si_shader_es(sscreen, shader);
1799 else if (shader->key.as_ngg)
1800 gfx10_shader_ngg(sscreen, shader);
1801 else
1802 si_shader_vs(sscreen, shader, NULL);
1803 break;
1804 case PIPE_SHADER_GEOMETRY:
1805 if (shader->key.as_ngg)
1806 gfx10_shader_ngg(sscreen, shader);
1807 else
1808 si_shader_gs(sscreen, shader);
1809 break;
1810 case PIPE_SHADER_FRAGMENT:
1811 si_shader_ps(sscreen, shader);
1812 break;
1813 default:
1814 assert(0);
1815 }
1816 }
1817
1818 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1819 {
1820 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1821 return sctx->queued.named.dsa->alpha_func;
1822 }
1823
1824 void si_shader_selector_key_vs(struct si_context *sctx,
1825 struct si_shader_selector *vs,
1826 struct si_shader_key *key,
1827 struct si_vs_prolog_bits *prolog_key)
1828 {
1829 if (!sctx->vertex_elements ||
1830 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1831 return;
1832
1833 struct si_vertex_elements *elts = sctx->vertex_elements;
1834
1835 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1836 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1837 prolog_key->unpack_instance_id_from_vertex_id =
1838 sctx->prim_discard_cs_instancing;
1839
1840 /* Prefer a monolithic shader to allow scheduling divisions around
1841 * VBO loads. */
1842 if (prolog_key->instance_divisor_is_fetched)
1843 key->opt.prefer_mono = 1;
1844
1845 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1846 unsigned count_mask = (1 << count) - 1;
1847 unsigned fix = elts->fix_fetch_always & count_mask;
1848 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1849
1850 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1851 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1852 while (mask) {
1853 unsigned i = u_bit_scan(&mask);
1854 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1855 unsigned vbidx = elts->vertex_buffer_index[i];
1856 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1857 unsigned align_mask = (1 << log_hw_load_size) - 1;
1858 if (vb->buffer_offset & align_mask ||
1859 vb->stride & align_mask) {
1860 fix |= 1 << i;
1861 opencode |= 1 << i;
1862 }
1863 }
1864 }
1865
1866 while (fix) {
1867 unsigned i = u_bit_scan(&fix);
1868 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1869 }
1870 key->mono.vs_fetch_opencode = opencode;
1871 }
1872
1873 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1874 struct si_shader_selector *vs,
1875 struct si_shader_key *key)
1876 {
1877 struct si_shader_selector *ps = sctx->ps_shader.cso;
1878
1879 key->opt.clip_disable =
1880 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1881 (vs->info.clipdist_writemask ||
1882 vs->info.writes_clipvertex) &&
1883 !vs->info.culldist_writemask;
1884
1885 /* Find out if PS is disabled. */
1886 bool ps_disabled = true;
1887 if (ps) {
1888 bool ps_modifies_zs = ps->info.uses_kill ||
1889 ps->info.writes_z ||
1890 ps->info.writes_stencil ||
1891 ps->info.writes_samplemask ||
1892 sctx->queued.named.blend->alpha_to_coverage ||
1893 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1894 unsigned ps_colormask = si_get_total_colormask(sctx);
1895
1896 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1897 (!ps_colormask &&
1898 !ps_modifies_zs &&
1899 !ps->info.writes_memory);
1900 }
1901
1902 /* Find out which VS outputs aren't used by the PS. */
1903 uint64_t outputs_written = vs->outputs_written_before_ps;
1904 uint64_t inputs_read = 0;
1905
1906 /* Ignore outputs that are not passed from VS to PS. */
1907 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1908 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1909 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1910
1911 if (!ps_disabled) {
1912 inputs_read = ps->inputs_read;
1913 }
1914
1915 uint64_t linked = outputs_written & inputs_read;
1916
1917 key->opt.kill_outputs = ~linked & outputs_written;
1918 key->opt.ngg_culling = sctx->ngg_culling;
1919 }
1920
1921 /* Compute the key for the hw shader variant */
1922 static inline void si_shader_selector_key(struct pipe_context *ctx,
1923 struct si_shader_selector *sel,
1924 union si_vgt_stages_key stages_key,
1925 struct si_shader_key *key)
1926 {
1927 struct si_context *sctx = (struct si_context *)ctx;
1928
1929 memset(key, 0, sizeof(*key));
1930
1931 switch (sel->type) {
1932 case PIPE_SHADER_VERTEX:
1933 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1934
1935 if (sctx->tes_shader.cso)
1936 key->as_ls = 1;
1937 else if (sctx->gs_shader.cso) {
1938 key->as_es = 1;
1939 key->as_ngg = stages_key.u.ngg;
1940 } else {
1941 key->as_ngg = stages_key.u.ngg;
1942 si_shader_selector_key_hw_vs(sctx, sel, key);
1943
1944 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1945 key->mono.u.vs_export_prim_id = 1;
1946 }
1947 break;
1948 case PIPE_SHADER_TESS_CTRL:
1949 if (sctx->chip_class >= GFX9) {
1950 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1951 key, &key->part.tcs.ls_prolog);
1952 key->part.tcs.ls = sctx->vs_shader.cso;
1953
1954 /* When the LS VGPR fix is needed, monolithic shaders
1955 * can:
1956 * - avoid initializing EXEC in both the LS prolog
1957 * and the LS main part when !vs_needs_prolog
1958 * - remove the fixup for unused input VGPRs
1959 */
1960 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1961
1962 /* The LS output / HS input layout can be communicated
1963 * directly instead of via user SGPRs for merged LS-HS.
1964 * The LS VGPR fix prefers this too.
1965 */
1966 key->opt.prefer_mono = 1;
1967 }
1968
1969 key->part.tcs.epilog.prim_mode =
1970 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1971 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1972 sel->info.tessfactors_are_def_in_all_invocs;
1973 key->part.tcs.epilog.tes_reads_tess_factors =
1974 sctx->tes_shader.cso->info.reads_tess_factors;
1975
1976 if (sel == sctx->fixed_func_tcs_shader.cso)
1977 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1978 break;
1979 case PIPE_SHADER_TESS_EVAL:
1980 key->as_ngg = stages_key.u.ngg;
1981
1982 if (sctx->gs_shader.cso)
1983 key->as_es = 1;
1984 else {
1985 si_shader_selector_key_hw_vs(sctx, sel, key);
1986
1987 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1988 key->mono.u.vs_export_prim_id = 1;
1989 }
1990 break;
1991 case PIPE_SHADER_GEOMETRY:
1992 if (sctx->chip_class >= GFX9) {
1993 if (sctx->tes_shader.cso) {
1994 key->part.gs.es = sctx->tes_shader.cso;
1995 } else {
1996 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1997 key, &key->part.gs.vs_prolog);
1998 key->part.gs.es = sctx->vs_shader.cso;
1999 key->part.gs.prolog.gfx9_prev_is_vs = 1;
2000 }
2001
2002 key->as_ngg = stages_key.u.ngg;
2003
2004 /* Merged ES-GS can have unbalanced wave usage.
2005 *
2006 * ES threads are per-vertex, while GS threads are
2007 * per-primitive. So without any amplification, there
2008 * are fewer GS threads than ES threads, which can result
2009 * in empty (no-op) GS waves. With too much amplification,
2010 * there are more GS threads than ES threads, which
2011 * can result in empty (no-op) ES waves.
2012 *
2013 * Non-monolithic shaders are implemented by setting EXEC
2014 * at the beginning of shader parts, and don't jump to
2015 * the end if EXEC is 0.
2016 *
2017 * Monolithic shaders use conditional blocks, so they can
2018 * jump and skip empty waves of ES or GS. So set this to
2019 * always use optimized variants, which are monolithic.
2020 */
2021 key->opt.prefer_mono = 1;
2022 }
2023 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
2024 break;
2025 case PIPE_SHADER_FRAGMENT: {
2026 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
2027 struct si_state_blend *blend = sctx->queued.named.blend;
2028
2029 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
2030 sel->info.colors_written == 0x1)
2031 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
2032
2033 /* Select the shader color format based on whether
2034 * blending or alpha are needed.
2035 */
2036 key->part.ps.epilog.spi_shader_col_format =
2037 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
2038 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
2039 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
2040 sctx->framebuffer.spi_shader_col_format_blend) |
2041 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
2042 sctx->framebuffer.spi_shader_col_format_alpha) |
2043 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
2044 sctx->framebuffer.spi_shader_col_format);
2045 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
2046
2047 /* The output for dual source blending should have
2048 * the same format as the first output.
2049 */
2050 if (blend->dual_src_blend) {
2051 key->part.ps.epilog.spi_shader_col_format |=
2052 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
2053 }
2054
2055 /* If alpha-to-coverage is enabled, we have to export alpha
2056 * even if there is no color buffer.
2057 */
2058 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
2059 blend->alpha_to_coverage)
2060 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
2061
2062 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
2063 * to the range supported by the type if a channel has less
2064 * than 16 bits and the export format is 16_ABGR.
2065 */
2066 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
2067 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
2068 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
2069 }
2070
2071 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
2072 if (!key->part.ps.epilog.last_cbuf) {
2073 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
2074 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
2075 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
2076 }
2077
2078 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
2079 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
2080
2081 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
2082 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
2083
2084 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
2085 rs->multisample_enable;
2086
2087 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
2088 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
2089 (is_line && rs->line_smooth)) &&
2090 sctx->framebuffer.nr_samples <= 1;
2091 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
2092
2093 if (sctx->ps_iter_samples > 1 &&
2094 sel->info.reads_samplemask) {
2095 key->part.ps.prolog.samplemask_log_ps_iter =
2096 util_logbase2(sctx->ps_iter_samples);
2097 }
2098
2099 if (rs->force_persample_interp &&
2100 rs->multisample_enable &&
2101 sctx->framebuffer.nr_samples > 1 &&
2102 sctx->ps_iter_samples > 1) {
2103 key->part.ps.prolog.force_persp_sample_interp =
2104 sel->info.uses_persp_center ||
2105 sel->info.uses_persp_centroid;
2106
2107 key->part.ps.prolog.force_linear_sample_interp =
2108 sel->info.uses_linear_center ||
2109 sel->info.uses_linear_centroid;
2110 } else if (rs->multisample_enable &&
2111 sctx->framebuffer.nr_samples > 1) {
2112 key->part.ps.prolog.bc_optimize_for_persp =
2113 sel->info.uses_persp_center &&
2114 sel->info.uses_persp_centroid;
2115 key->part.ps.prolog.bc_optimize_for_linear =
2116 sel->info.uses_linear_center &&
2117 sel->info.uses_linear_centroid;
2118 } else {
2119 /* Make sure SPI doesn't compute more than 1 pair
2120 * of (i,j), which is the optimization here. */
2121 key->part.ps.prolog.force_persp_center_interp =
2122 sel->info.uses_persp_center +
2123 sel->info.uses_persp_centroid +
2124 sel->info.uses_persp_sample > 1;
2125
2126 key->part.ps.prolog.force_linear_center_interp =
2127 sel->info.uses_linear_center +
2128 sel->info.uses_linear_centroid +
2129 sel->info.uses_linear_sample > 1;
2130
2131 if (sel->info.uses_persp_opcode_interp_sample ||
2132 sel->info.uses_linear_opcode_interp_sample)
2133 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2134 }
2135
2136 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2137
2138 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2139 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2140 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2141 struct pipe_resource *tex = cb0->texture;
2142
2143 /* 1D textures are allocated and used as 2D on GFX9. */
2144 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2145 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2146 (tex->target == PIPE_TEXTURE_1D ||
2147 tex->target == PIPE_TEXTURE_1D_ARRAY);
2148 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2149 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2150 tex->target == PIPE_TEXTURE_CUBE ||
2151 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2152 tex->target == PIPE_TEXTURE_3D;
2153 }
2154 break;
2155 }
2156 default:
2157 assert(0);
2158 }
2159
2160 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2161 memset(&key->opt, 0, sizeof(key->opt));
2162 }
2163
2164 static void si_build_shader_variant(struct si_shader *shader,
2165 int thread_index,
2166 bool low_priority)
2167 {
2168 struct si_shader_selector *sel = shader->selector;
2169 struct si_screen *sscreen = sel->screen;
2170 struct ac_llvm_compiler *compiler;
2171 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2172
2173 if (thread_index >= 0) {
2174 if (low_priority) {
2175 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2176 compiler = &sscreen->compiler_lowp[thread_index];
2177 } else {
2178 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2179 compiler = &sscreen->compiler[thread_index];
2180 }
2181 if (!debug->async)
2182 debug = NULL;
2183 } else {
2184 assert(!low_priority);
2185 compiler = shader->compiler_ctx_state.compiler;
2186 }
2187
2188 if (!compiler->passes)
2189 si_init_compiler(sscreen, compiler);
2190
2191 if (unlikely(!si_create_shader_variant(sscreen, compiler, shader, debug))) {
2192 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2193 sel->type);
2194 shader->compilation_failed = true;
2195 return;
2196 }
2197
2198 if (shader->compiler_ctx_state.is_debug_context) {
2199 FILE *f = open_memstream(&shader->shader_log,
2200 &shader->shader_log_size);
2201 if (f) {
2202 si_shader_dump(sscreen, shader, NULL, f, false);
2203 fclose(f);
2204 }
2205 }
2206
2207 si_shader_init_pm4_state(sscreen, shader);
2208 }
2209
2210 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2211 {
2212 struct si_shader *shader = (struct si_shader *)job;
2213
2214 assert(thread_index >= 0);
2215
2216 si_build_shader_variant(shader, thread_index, true);
2217 }
2218
2219 static const struct si_shader_key zeroed;
2220
2221 static bool si_check_missing_main_part(struct si_screen *sscreen,
2222 struct si_shader_selector *sel,
2223 struct si_compiler_ctx_state *compiler_state,
2224 struct si_shader_key *key)
2225 {
2226 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2227
2228 if (!*mainp) {
2229 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2230
2231 if (!main_part)
2232 return false;
2233
2234 /* We can leave the fence as permanently signaled because the
2235 * main part becomes visible globally only after it has been
2236 * compiled. */
2237 util_queue_fence_init(&main_part->ready);
2238
2239 main_part->selector = sel;
2240 main_part->key.as_es = key->as_es;
2241 main_part->key.as_ls = key->as_ls;
2242 main_part->key.as_ngg = key->as_ngg;
2243 main_part->is_monolithic = false;
2244
2245 if (si_compile_shader(sscreen, compiler_state->compiler,
2246 main_part, &compiler_state->debug) != 0) {
2247 FREE(main_part);
2248 return false;
2249 }
2250 *mainp = main_part;
2251 }
2252 return true;
2253 }
2254
2255 /**
2256 * Select a shader variant according to the shader key.
2257 *
2258 * \param optimized_or_none If the key describes an optimized shader variant and
2259 * the compilation isn't finished, don't select any
2260 * shader and return an error.
2261 */
2262 int si_shader_select_with_key(struct si_screen *sscreen,
2263 struct si_shader_ctx_state *state,
2264 struct si_compiler_ctx_state *compiler_state,
2265 struct si_shader_key *key,
2266 int thread_index,
2267 bool optimized_or_none)
2268 {
2269 struct si_shader_selector *sel = state->cso;
2270 struct si_shader_selector *previous_stage_sel = NULL;
2271 struct si_shader *current = state->current;
2272 struct si_shader *iter, *shader = NULL;
2273
2274 again:
2275 /* Check if we don't need to change anything.
2276 * This path is also used for most shaders that don't need multiple
2277 * variants, it will cost just a computation of the key and this
2278 * test. */
2279 if (likely(current &&
2280 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2281 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2282 if (current->is_optimized) {
2283 if (optimized_or_none)
2284 return -1;
2285
2286 memset(&key->opt, 0, sizeof(key->opt));
2287 goto current_not_ready;
2288 }
2289
2290 util_queue_fence_wait(&current->ready);
2291 }
2292
2293 return current->compilation_failed ? -1 : 0;
2294 }
2295 current_not_ready:
2296
2297 /* This must be done before the mutex is locked, because async GS
2298 * compilation calls this function too, and therefore must enter
2299 * the mutex first.
2300 *
2301 * Only wait if we are in a draw call. Don't wait if we are
2302 * in a compiler thread.
2303 */
2304 if (thread_index < 0)
2305 util_queue_fence_wait(&sel->ready);
2306
2307 simple_mtx_lock(&sel->mutex);
2308
2309 /* Find the shader variant. */
2310 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2311 /* Don't check the "current" shader. We checked it above. */
2312 if (current != iter &&
2313 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2314 simple_mtx_unlock(&sel->mutex);
2315
2316 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2317 /* If it's an optimized shader and its compilation has
2318 * been started but isn't done, use the unoptimized
2319 * shader so as not to cause a stall due to compilation.
2320 */
2321 if (iter->is_optimized) {
2322 if (optimized_or_none)
2323 return -1;
2324 memset(&key->opt, 0, sizeof(key->opt));
2325 goto again;
2326 }
2327
2328 util_queue_fence_wait(&iter->ready);
2329 }
2330
2331 if (iter->compilation_failed) {
2332 return -1; /* skip the draw call */
2333 }
2334
2335 state->current = iter;
2336 return 0;
2337 }
2338 }
2339
2340 /* Build a new shader. */
2341 shader = CALLOC_STRUCT(si_shader);
2342 if (!shader) {
2343 simple_mtx_unlock(&sel->mutex);
2344 return -ENOMEM;
2345 }
2346
2347 util_queue_fence_init(&shader->ready);
2348
2349 shader->selector = sel;
2350 shader->key = *key;
2351 shader->compiler_ctx_state = *compiler_state;
2352
2353 /* If this is a merged shader, get the first shader's selector. */
2354 if (sscreen->info.chip_class >= GFX9) {
2355 if (sel->type == PIPE_SHADER_TESS_CTRL)
2356 previous_stage_sel = key->part.tcs.ls;
2357 else if (sel->type == PIPE_SHADER_GEOMETRY)
2358 previous_stage_sel = key->part.gs.es;
2359
2360 /* We need to wait for the previous shader. */
2361 if (previous_stage_sel && thread_index < 0)
2362 util_queue_fence_wait(&previous_stage_sel->ready);
2363 }
2364
2365 bool is_pure_monolithic =
2366 sscreen->use_monolithic_shaders ||
2367 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2368
2369 /* Compile the main shader part if it doesn't exist. This can happen
2370 * if the initial guess was wrong.
2371 *
2372 * The prim discard CS doesn't need the main shader part.
2373 */
2374 if (!is_pure_monolithic &&
2375 !key->opt.vs_as_prim_discard_cs) {
2376 bool ok = true;
2377
2378 /* Make sure the main shader part is present. This is needed
2379 * for shaders that can be compiled as VS, LS, or ES, and only
2380 * one of them is compiled at creation.
2381 *
2382 * It is also needed for GS, which can be compiled as non-NGG
2383 * and NGG.
2384 *
2385 * For merged shaders, check that the starting shader's main
2386 * part is present.
2387 */
2388 if (previous_stage_sel) {
2389 struct si_shader_key shader1_key = zeroed;
2390
2391 if (sel->type == PIPE_SHADER_TESS_CTRL) {
2392 shader1_key.as_ls = 1;
2393 } else if (sel->type == PIPE_SHADER_GEOMETRY) {
2394 shader1_key.as_es = 1;
2395 shader1_key.as_ngg = key->as_ngg; /* for Wave32 vs Wave64 */
2396 } else {
2397 assert(0);
2398 }
2399
2400 simple_mtx_lock(&previous_stage_sel->mutex);
2401 ok = si_check_missing_main_part(sscreen,
2402 previous_stage_sel,
2403 compiler_state, &shader1_key);
2404 simple_mtx_unlock(&previous_stage_sel->mutex);
2405 }
2406
2407 if (ok) {
2408 ok = si_check_missing_main_part(sscreen, sel,
2409 compiler_state, key);
2410 }
2411
2412 if (!ok) {
2413 FREE(shader);
2414 simple_mtx_unlock(&sel->mutex);
2415 return -ENOMEM; /* skip the draw call */
2416 }
2417 }
2418
2419 /* Keep the reference to the 1st shader of merged shaders, so that
2420 * Gallium can't destroy it before we destroy the 2nd shader.
2421 *
2422 * Set sctx = NULL, because it's unused if we're not releasing
2423 * the shader, and we don't have any sctx here.
2424 */
2425 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2426 previous_stage_sel);
2427
2428 /* Monolithic-only shaders don't make a distinction between optimized
2429 * and unoptimized. */
2430 shader->is_monolithic =
2431 is_pure_monolithic ||
2432 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2433
2434 /* The prim discard CS is always optimized. */
2435 shader->is_optimized =
2436 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2437 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2438
2439 /* If it's an optimized shader, compile it asynchronously. */
2440 if (shader->is_optimized && thread_index < 0) {
2441 /* Compile it asynchronously. */
2442 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2443 shader, &shader->ready,
2444 si_build_shader_variant_low_priority, NULL,
2445 0);
2446
2447 /* Add only after the ready fence was reset, to guard against a
2448 * race with si_bind_XX_shader. */
2449 if (!sel->last_variant) {
2450 sel->first_variant = shader;
2451 sel->last_variant = shader;
2452 } else {
2453 sel->last_variant->next_variant = shader;
2454 sel->last_variant = shader;
2455 }
2456
2457 /* Use the default (unoptimized) shader for now. */
2458 memset(&key->opt, 0, sizeof(key->opt));
2459 simple_mtx_unlock(&sel->mutex);
2460
2461 if (sscreen->options.sync_compile)
2462 util_queue_fence_wait(&shader->ready);
2463
2464 if (optimized_or_none)
2465 return -1;
2466 goto again;
2467 }
2468
2469 /* Reset the fence before adding to the variant list. */
2470 util_queue_fence_reset(&shader->ready);
2471
2472 if (!sel->last_variant) {
2473 sel->first_variant = shader;
2474 sel->last_variant = shader;
2475 } else {
2476 sel->last_variant->next_variant = shader;
2477 sel->last_variant = shader;
2478 }
2479
2480 simple_mtx_unlock(&sel->mutex);
2481
2482 assert(!shader->is_optimized);
2483 si_build_shader_variant(shader, thread_index, false);
2484
2485 util_queue_fence_signal(&shader->ready);
2486
2487 if (!shader->compilation_failed)
2488 state->current = shader;
2489
2490 return shader->compilation_failed ? -1 : 0;
2491 }
2492
2493 static int si_shader_select(struct pipe_context *ctx,
2494 struct si_shader_ctx_state *state,
2495 union si_vgt_stages_key stages_key,
2496 struct si_compiler_ctx_state *compiler_state)
2497 {
2498 struct si_context *sctx = (struct si_context *)ctx;
2499 struct si_shader_key key;
2500
2501 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2502 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2503 &key, -1, false);
2504 }
2505
2506 static void si_parse_next_shader_property(const struct si_shader_info *info,
2507 bool streamout,
2508 struct si_shader_key *key)
2509 {
2510 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2511
2512 switch (info->processor) {
2513 case PIPE_SHADER_VERTEX:
2514 switch (next_shader) {
2515 case PIPE_SHADER_GEOMETRY:
2516 key->as_es = 1;
2517 break;
2518 case PIPE_SHADER_TESS_CTRL:
2519 case PIPE_SHADER_TESS_EVAL:
2520 key->as_ls = 1;
2521 break;
2522 default:
2523 /* If POSITION isn't written, it can only be a HW VS
2524 * if streamout is used. If streamout isn't used,
2525 * assume that it's a HW LS. (the next shader is TCS)
2526 * This heuristic is needed for separate shader objects.
2527 */
2528 if (!info->writes_position && !streamout)
2529 key->as_ls = 1;
2530 }
2531 break;
2532
2533 case PIPE_SHADER_TESS_EVAL:
2534 if (next_shader == PIPE_SHADER_GEOMETRY ||
2535 !info->writes_position)
2536 key->as_es = 1;
2537 break;
2538 }
2539 }
2540
2541 /**
2542 * Compile the main shader part or the monolithic shader as part of
2543 * si_shader_selector initialization. Since it can be done asynchronously,
2544 * there is no way to report compile failures to applications.
2545 */
2546 static void si_init_shader_selector_async(void *job, int thread_index)
2547 {
2548 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2549 struct si_screen *sscreen = sel->screen;
2550 struct ac_llvm_compiler *compiler;
2551 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2552
2553 assert(!debug->debug_message || debug->async);
2554 assert(thread_index >= 0);
2555 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2556 compiler = &sscreen->compiler[thread_index];
2557
2558 if (!compiler->passes)
2559 si_init_compiler(sscreen, compiler);
2560
2561 /* Serialize NIR to save memory. Monolithic shader variants
2562 * have to deserialize NIR before compilation.
2563 */
2564 if (sel->nir) {
2565 struct blob blob;
2566 size_t size;
2567
2568 blob_init(&blob);
2569 /* true = remove optional debugging data to increase
2570 * the likehood of getting more shader cache hits.
2571 * It also drops variable names, so we'll save more memory.
2572 */
2573 nir_serialize(&blob, sel->nir, true);
2574 blob_finish_get_buffer(&blob, &sel->nir_binary, &size);
2575 sel->nir_size = size;
2576 }
2577
2578 /* Compile the main shader part for use with a prolog and/or epilog.
2579 * If this fails, the driver will try to compile a monolithic shader
2580 * on demand.
2581 */
2582 if (!sscreen->use_monolithic_shaders) {
2583 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2584 unsigned char ir_sha1_cache_key[20];
2585
2586 if (!shader) {
2587 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2588 return;
2589 }
2590
2591 /* We can leave the fence signaled because use of the default
2592 * main part is guarded by the selector's ready fence. */
2593 util_queue_fence_init(&shader->ready);
2594
2595 shader->selector = sel;
2596 shader->is_monolithic = false;
2597 si_parse_next_shader_property(&sel->info,
2598 sel->so.num_outputs != 0,
2599 &shader->key);
2600
2601 if (sscreen->use_ngg &&
2602 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2603 ((sel->type == PIPE_SHADER_VERTEX && !shader->key.as_ls) ||
2604 sel->type == PIPE_SHADER_TESS_EVAL ||
2605 sel->type == PIPE_SHADER_GEOMETRY))
2606 shader->key.as_ngg = 1;
2607
2608 if (sel->nir) {
2609 si_get_ir_cache_key(sel, shader->key.as_ngg,
2610 shader->key.as_es, ir_sha1_cache_key);
2611 }
2612
2613 /* Try to load the shader from the shader cache. */
2614 simple_mtx_lock(&sscreen->shader_cache_mutex);
2615
2616 if (si_shader_cache_load_shader(sscreen, ir_sha1_cache_key, shader)) {
2617 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2618 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2619 } else {
2620 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2621
2622 /* Compile the shader if it hasn't been loaded from the cache. */
2623 if (si_compile_shader(sscreen, compiler, shader,
2624 debug) != 0) {
2625 FREE(shader);
2626 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2627 return;
2628 }
2629
2630 simple_mtx_lock(&sscreen->shader_cache_mutex);
2631 si_shader_cache_insert_shader(sscreen, ir_sha1_cache_key,
2632 shader, true);
2633 simple_mtx_unlock(&sscreen->shader_cache_mutex);
2634 }
2635
2636 *si_get_main_shader_part(sel, &shader->key) = shader;
2637
2638 /* Unset "outputs_written" flags for outputs converted to
2639 * DEFAULT_VAL, so that later inter-shader optimizations don't
2640 * try to eliminate outputs that don't exist in the final
2641 * shader.
2642 *
2643 * This is only done if non-monolithic shaders are enabled.
2644 */
2645 if ((sel->type == PIPE_SHADER_VERTEX ||
2646 sel->type == PIPE_SHADER_TESS_EVAL) &&
2647 !shader->key.as_ls &&
2648 !shader->key.as_es) {
2649 unsigned i;
2650
2651 for (i = 0; i < sel->info.num_outputs; i++) {
2652 unsigned offset = shader->info.vs_output_param_offset[i];
2653
2654 if (offset <= AC_EXP_PARAM_OFFSET_31)
2655 continue;
2656
2657 unsigned name = sel->info.output_semantic_name[i];
2658 unsigned index = sel->info.output_semantic_index[i];
2659 unsigned id;
2660
2661 switch (name) {
2662 case TGSI_SEMANTIC_GENERIC:
2663 /* don't process indices the function can't handle */
2664 if (index >= SI_MAX_IO_GENERIC)
2665 break;
2666 /* fall through */
2667 default:
2668 id = si_shader_io_get_unique_index(name, index, true);
2669 sel->outputs_written_before_ps &= ~(1ull << id);
2670 break;
2671 case TGSI_SEMANTIC_POSITION: /* ignore these */
2672 case TGSI_SEMANTIC_PSIZE:
2673 case TGSI_SEMANTIC_CLIPVERTEX:
2674 case TGSI_SEMANTIC_EDGEFLAG:
2675 break;
2676 }
2677 }
2678 }
2679 }
2680
2681 /* The GS copy shader is always pre-compiled. */
2682 if (sel->type == PIPE_SHADER_GEOMETRY &&
2683 (!sscreen->use_ngg ||
2684 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2685 sel->tess_turns_off_ngg)) {
2686 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2687 if (!sel->gs_copy_shader) {
2688 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2689 return;
2690 }
2691
2692 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2693 }
2694
2695 /* Free NIR. We only keep serialized NIR after this point. */
2696 if (sel->nir) {
2697 ralloc_free(sel->nir);
2698 sel->nir = NULL;
2699 }
2700 }
2701
2702 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2703 struct util_queue_fence *ready_fence,
2704 struct si_compiler_ctx_state *compiler_ctx_state,
2705 void *job, util_queue_execute_func execute)
2706 {
2707 util_queue_fence_init(ready_fence);
2708
2709 struct util_async_debug_callback async_debug;
2710 bool debug =
2711 (sctx->debug.debug_message && !sctx->debug.async) ||
2712 sctx->is_debug ||
2713 si_can_dump_shader(sctx->screen, processor);
2714
2715 if (debug) {
2716 u_async_debug_init(&async_debug);
2717 compiler_ctx_state->debug = async_debug.base;
2718 }
2719
2720 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2721 ready_fence, execute, NULL, 0);
2722
2723 if (debug) {
2724 util_queue_fence_wait(ready_fence);
2725 u_async_debug_drain(&async_debug, &sctx->debug);
2726 u_async_debug_cleanup(&async_debug);
2727 }
2728
2729 if (sctx->screen->options.sync_compile)
2730 util_queue_fence_wait(ready_fence);
2731 }
2732
2733 /* Return descriptor slot usage masks from the given shader info. */
2734 void si_get_active_slot_masks(const struct si_shader_info *info,
2735 uint32_t *const_and_shader_buffers,
2736 uint64_t *samplers_and_images)
2737 {
2738 unsigned start, num_shaderbufs, num_constbufs, num_images, num_msaa_images, num_samplers;
2739
2740 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2741 num_constbufs = util_last_bit(info->const_buffers_declared);
2742 /* two 8-byte images share one 16-byte slot */
2743 num_images = align(util_last_bit(info->images_declared), 2);
2744 num_msaa_images = align(util_last_bit(info->msaa_images_declared), 2);
2745 num_samplers = util_last_bit(info->samplers_declared);
2746
2747 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2748 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2749 *const_and_shader_buffers =
2750 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2751
2752 /* The layout is:
2753 * - fmask[last] ... fmask[0] go to [15-last .. 15]
2754 * - image[last] ... image[0] go to [31-last .. 31]
2755 * - sampler[0] ... sampler[last] go to [32 .. 32+last*2]
2756 *
2757 * FMASKs for images are placed separately, because MSAA images are rare,
2758 * and so we can benefit from a better cache hit rate if we keep image
2759 * descriptors together.
2760 */
2761 if (num_msaa_images)
2762 num_images = SI_NUM_IMAGES + num_msaa_images; /* add FMASK descriptors */
2763
2764 start = si_get_image_slot(num_images - 1) / 2;
2765 *samplers_and_images =
2766 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2767 }
2768
2769 static void *si_create_shader_selector(struct pipe_context *ctx,
2770 const struct pipe_shader_state *state)
2771 {
2772 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2773 struct si_context *sctx = (struct si_context*)ctx;
2774 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2775 int i;
2776
2777 if (!sel)
2778 return NULL;
2779
2780 pipe_reference_init(&sel->reference, 1);
2781 sel->screen = sscreen;
2782 sel->compiler_ctx_state.debug = sctx->debug;
2783 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2784
2785 sel->so = state->stream_output;
2786
2787 if (state->type == PIPE_SHADER_IR_TGSI) {
2788 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2789 } else {
2790 assert(state->type == PIPE_SHADER_IR_NIR);
2791 sel->nir = state->ir.nir;
2792 }
2793
2794 si_nir_scan_shader(sel->nir, &sel->info);
2795 si_nir_adjust_driver_locations(sel->nir);
2796
2797 sel->type = sel->info.processor;
2798 p_atomic_inc(&sscreen->num_shaders_created);
2799 si_get_active_slot_masks(&sel->info,
2800 &sel->active_const_and_shader_buffers,
2801 &sel->active_samplers_and_images);
2802
2803 /* Record which streamout buffers are enabled. */
2804 for (i = 0; i < sel->so.num_outputs; i++) {
2805 sel->enabled_streamout_buffer_mask |=
2806 (1 << sel->so.output[i].output_buffer) <<
2807 (sel->so.output[i].stream * 4);
2808 }
2809
2810 sel->num_vs_inputs = sel->type == PIPE_SHADER_VERTEX &&
2811 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] ?
2812 sel->info.num_inputs : 0;
2813 sel->num_vbos_in_user_sgprs =
2814 MIN2(sel->num_vs_inputs, sscreen->num_vbos_in_user_sgprs);
2815
2816 /* The prolog is a no-op if there are no inputs. */
2817 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2818 sel->info.num_inputs &&
2819 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2820
2821 sel->force_correct_derivs_after_kill =
2822 sel->type == PIPE_SHADER_FRAGMENT &&
2823 sel->info.uses_derivatives &&
2824 sel->info.uses_kill &&
2825 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2826
2827 sel->prim_discard_cs_allowed =
2828 sel->type == PIPE_SHADER_VERTEX &&
2829 !sel->info.uses_bindless_images &&
2830 !sel->info.uses_bindless_samplers &&
2831 !sel->info.writes_memory &&
2832 !sel->info.writes_viewport_index &&
2833 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2834 !sel->so.num_outputs;
2835
2836 switch (sel->type) {
2837 case PIPE_SHADER_GEOMETRY:
2838 sel->gs_output_prim =
2839 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2840
2841 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2842 sel->rast_prim = sel->gs_output_prim;
2843 if (util_rast_prim_is_triangles(sel->rast_prim))
2844 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2845
2846 sel->gs_max_out_vertices =
2847 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2848 sel->gs_num_invocations =
2849 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2850 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2851 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2852 sel->gs_max_out_vertices;
2853
2854 sel->max_gs_stream = 0;
2855 for (i = 0; i < sel->so.num_outputs; i++)
2856 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2857 sel->so.output[i].stream);
2858
2859 sel->gs_input_verts_per_prim =
2860 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2861
2862 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2863 sel->tess_turns_off_ngg =
2864 sscreen->info.chip_class == GFX10 &&
2865 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2866 break;
2867
2868 case PIPE_SHADER_TESS_CTRL:
2869 /* Always reserve space for these. */
2870 sel->patch_outputs_written |=
2871 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2872 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2873 /* fall through */
2874 case PIPE_SHADER_VERTEX:
2875 case PIPE_SHADER_TESS_EVAL:
2876 for (i = 0; i < sel->info.num_outputs; i++) {
2877 unsigned name = sel->info.output_semantic_name[i];
2878 unsigned index = sel->info.output_semantic_index[i];
2879
2880 switch (name) {
2881 case TGSI_SEMANTIC_TESSINNER:
2882 case TGSI_SEMANTIC_TESSOUTER:
2883 case TGSI_SEMANTIC_PATCH:
2884 sel->patch_outputs_written |=
2885 1ull << si_shader_io_get_unique_index_patch(name, index);
2886 break;
2887
2888 case TGSI_SEMANTIC_GENERIC:
2889 /* don't process indices the function can't handle */
2890 if (index >= SI_MAX_IO_GENERIC)
2891 break;
2892 /* fall through */
2893 default:
2894 sel->outputs_written |=
2895 1ull << si_shader_io_get_unique_index(name, index, false);
2896 sel->outputs_written_before_ps |=
2897 1ull << si_shader_io_get_unique_index(name, index, true);
2898 break;
2899 case TGSI_SEMANTIC_EDGEFLAG:
2900 break;
2901 }
2902 }
2903 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2904 sel->lshs_vertex_stride = sel->esgs_itemsize;
2905
2906 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2907 * will start on a different bank. (except for the maximum 32*16).
2908 */
2909 if (sel->lshs_vertex_stride < 32*16)
2910 sel->lshs_vertex_stride += 4;
2911
2912 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2913 * conflicts, i.e. each vertex will start at a different bank.
2914 */
2915 if (sctx->chip_class >= GFX9)
2916 sel->esgs_itemsize += 4;
2917
2918 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2919
2920 /* Only for TES: */
2921 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2922 sel->rast_prim = PIPE_PRIM_POINTS;
2923 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2924 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2925 else
2926 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2927 break;
2928
2929 case PIPE_SHADER_FRAGMENT:
2930 for (i = 0; i < sel->info.num_inputs; i++) {
2931 unsigned name = sel->info.input_semantic_name[i];
2932 unsigned index = sel->info.input_semantic_index[i];
2933
2934 switch (name) {
2935 case TGSI_SEMANTIC_GENERIC:
2936 /* don't process indices the function can't handle */
2937 if (index >= SI_MAX_IO_GENERIC)
2938 break;
2939 /* fall through */
2940 default:
2941 sel->inputs_read |=
2942 1ull << si_shader_io_get_unique_index(name, index, true);
2943 break;
2944 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2945 break;
2946 }
2947 }
2948
2949 for (i = 0; i < 8; i++)
2950 if (sel->info.colors_written & (1 << i))
2951 sel->colors_written_4bit |= 0xf << (4 * i);
2952
2953 for (i = 0; i < sel->info.num_inputs; i++) {
2954 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2955 int index = sel->info.input_semantic_index[i];
2956 sel->color_attr_index[index] = i;
2957 }
2958 }
2959 break;
2960 default:;
2961 }
2962
2963 sel->ngg_culling_allowed =
2964 sscreen->info.chip_class == GFX10 &&
2965 sscreen->info.has_dedicated_vram &&
2966 sscreen->use_ngg_culling &&
2967 /* Disallow TES by default, because TessMark results are mixed. */
2968 (sel->type == PIPE_SHADER_VERTEX ||
2969 (sscreen->always_use_ngg_culling && sel->type == PIPE_SHADER_TESS_EVAL)) &&
2970 sel->info.writes_position &&
2971 !sel->info.writes_viewport_index && /* cull only against viewport 0 */
2972 !sel->info.writes_memory &&
2973 !sel->so.num_outputs &&
2974 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] &&
2975 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
2976
2977 /* PA_CL_VS_OUT_CNTL */
2978 if (sctx->chip_class <= GFX9)
2979 sel->pa_cl_vs_out_cntl = si_get_vs_out_cntl(sel, false);
2980
2981 sel->clipdist_mask = sel->info.writes_clipvertex ?
2982 SIX_BITS : sel->info.clipdist_writemask;
2983 sel->culldist_mask = sel->info.culldist_writemask <<
2984 sel->info.num_written_clipdistance;
2985
2986 /* DB_SHADER_CONTROL */
2987 sel->db_shader_control =
2988 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2989 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2990 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2991 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2992
2993 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2994 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2995 sel->db_shader_control |=
2996 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2997 break;
2998 case TGSI_FS_DEPTH_LAYOUT_LESS:
2999 sel->db_shader_control |=
3000 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
3001 break;
3002 }
3003
3004 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
3005 *
3006 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
3007 * --|-----------|------------|------------|--------------------|-------------------|-------------
3008 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
3009 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
3010 * 2 | false | true | n/a | LateZ | 1 | 0
3011 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
3012 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
3013 *
3014 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
3015 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
3016 *
3017 * Don't use ReZ without profiling !!!
3018 *
3019 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
3020 * shaders.
3021 */
3022 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
3023 /* Cases 3, 4. */
3024 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
3025 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
3026 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
3027 } else if (sel->info.writes_memory) {
3028 /* Case 2. */
3029 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
3030 S_02880C_EXEC_ON_HIER_FAIL(1);
3031 } else {
3032 /* Case 1. */
3033 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
3034 }
3035
3036 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
3037 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
3038
3039 (void) simple_mtx_init(&sel->mutex, mtx_plain);
3040
3041 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
3042 &sel->compiler_ctx_state, sel,
3043 si_init_shader_selector_async);
3044 return sel;
3045 }
3046
3047 static void si_update_streamout_state(struct si_context *sctx)
3048 {
3049 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
3050
3051 if (!shader_with_so)
3052 return;
3053
3054 sctx->streamout.enabled_stream_buffers_mask =
3055 shader_with_so->enabled_streamout_buffer_mask;
3056 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
3057 }
3058
3059 static void si_update_clip_regs(struct si_context *sctx,
3060 struct si_shader_selector *old_hw_vs,
3061 struct si_shader *old_hw_vs_variant,
3062 struct si_shader_selector *next_hw_vs,
3063 struct si_shader *next_hw_vs_variant)
3064 {
3065 if (next_hw_vs &&
3066 (!old_hw_vs ||
3067 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
3068 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
3069 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
3070 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
3071 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
3072 !old_hw_vs_variant ||
3073 !next_hw_vs_variant ||
3074 old_hw_vs_variant->key.opt.clip_disable !=
3075 next_hw_vs_variant->key.opt.clip_disable))
3076 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3077 }
3078
3079 static void si_update_common_shader_state(struct si_context *sctx)
3080 {
3081 sctx->uses_bindless_samplers =
3082 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
3083 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
3084 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
3085 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
3086 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
3087 sctx->uses_bindless_images =
3088 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
3089 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
3090 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
3091 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
3092 si_shader_uses_bindless_images(sctx->tes_shader.cso);
3093 sctx->do_update_shaders = true;
3094 }
3095
3096 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
3097 {
3098 struct si_context *sctx = (struct si_context *)ctx;
3099 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3100 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3101 struct si_shader_selector *sel = state;
3102
3103 if (sctx->vs_shader.cso == sel)
3104 return;
3105
3106 sctx->vs_shader.cso = sel;
3107 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3108 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3109
3110 if (si_update_ngg(sctx))
3111 si_shader_change_notify(sctx);
3112
3113 si_update_common_shader_state(sctx);
3114 si_update_vs_viewport_state(sctx);
3115 si_set_active_descriptors_for_shader(sctx, sel);
3116 si_update_streamout_state(sctx);
3117 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3118 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3119 }
3120
3121 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3122 {
3123 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3124 (sctx->tes_shader.cso &&
3125 sctx->tes_shader.cso->info.uses_primid) ||
3126 (sctx->tcs_shader.cso &&
3127 sctx->tcs_shader.cso->info.uses_primid) ||
3128 (sctx->gs_shader.cso &&
3129 sctx->gs_shader.cso->info.uses_primid) ||
3130 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3131 sctx->ps_shader.cso->info.uses_primid);
3132 }
3133
3134 bool si_update_ngg(struct si_context *sctx)
3135 {
3136 if (!sctx->screen->use_ngg) {
3137 assert(!sctx->ngg);
3138 return false;
3139 }
3140
3141 bool new_ngg = true;
3142
3143 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3144 sctx->gs_shader.cso->tess_turns_off_ngg) {
3145 new_ngg = false;
3146 } else if (!sctx->screen->use_ngg_streamout) {
3147 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3148
3149 if ((last && last->so.num_outputs) ||
3150 sctx->streamout.prims_gen_query_enabled)
3151 new_ngg = false;
3152 }
3153
3154 if (new_ngg != sctx->ngg) {
3155 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3156 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3157 * pointers are set.
3158 */
3159 if ((sctx->family == CHIP_NAVI10 ||
3160 sctx->family == CHIP_NAVI12 ||
3161 sctx->family == CHIP_NAVI14) &&
3162 !new_ngg)
3163 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3164
3165 sctx->ngg = new_ngg;
3166 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3167 return true;
3168 }
3169 return false;
3170 }
3171
3172 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3173 {
3174 struct si_context *sctx = (struct si_context *)ctx;
3175 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3176 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3177 struct si_shader_selector *sel = state;
3178 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3179 bool ngg_changed;
3180
3181 if (sctx->gs_shader.cso == sel)
3182 return;
3183
3184 sctx->gs_shader.cso = sel;
3185 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3186 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3187
3188 si_update_common_shader_state(sctx);
3189 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3190
3191 ngg_changed = si_update_ngg(sctx);
3192 if (ngg_changed || enable_changed)
3193 si_shader_change_notify(sctx);
3194 if (enable_changed) {
3195 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3196 si_update_tess_uses_prim_id(sctx);
3197 }
3198 si_update_vs_viewport_state(sctx);
3199 si_set_active_descriptors_for_shader(sctx, sel);
3200 si_update_streamout_state(sctx);
3201 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3202 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3203 }
3204
3205 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3206 {
3207 struct si_context *sctx = (struct si_context *)ctx;
3208 struct si_shader_selector *sel = state;
3209 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3210
3211 if (sctx->tcs_shader.cso == sel)
3212 return;
3213
3214 sctx->tcs_shader.cso = sel;
3215 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3216 si_update_tess_uses_prim_id(sctx);
3217
3218 si_update_common_shader_state(sctx);
3219
3220 if (enable_changed)
3221 sctx->last_tcs = NULL; /* invalidate derived tess state */
3222
3223 si_set_active_descriptors_for_shader(sctx, sel);
3224 }
3225
3226 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3227 {
3228 struct si_context *sctx = (struct si_context *)ctx;
3229 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3230 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3231 struct si_shader_selector *sel = state;
3232 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3233
3234 if (sctx->tes_shader.cso == sel)
3235 return;
3236
3237 sctx->tes_shader.cso = sel;
3238 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3239 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3240 si_update_tess_uses_prim_id(sctx);
3241
3242 si_update_common_shader_state(sctx);
3243 sctx->last_gs_out_prim = -1; /* reset this so that it gets updated */
3244
3245 bool ngg_changed = si_update_ngg(sctx);
3246 if (ngg_changed || enable_changed)
3247 si_shader_change_notify(sctx);
3248 if (enable_changed)
3249 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3250 si_update_vs_viewport_state(sctx);
3251 si_set_active_descriptors_for_shader(sctx, sel);
3252 si_update_streamout_state(sctx);
3253 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3254 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3255 }
3256
3257 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3258 {
3259 struct si_context *sctx = (struct si_context *)ctx;
3260 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3261 struct si_shader_selector *sel = state;
3262
3263 /* skip if supplied shader is one already in use */
3264 if (old_sel == sel)
3265 return;
3266
3267 sctx->ps_shader.cso = sel;
3268 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3269
3270 si_update_common_shader_state(sctx);
3271 if (sel) {
3272 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3273 si_update_tess_uses_prim_id(sctx);
3274
3275 if (!old_sel ||
3276 old_sel->info.colors_written != sel->info.colors_written)
3277 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3278
3279 if (sctx->screen->has_out_of_order_rast &&
3280 (!old_sel ||
3281 old_sel->info.writes_memory != sel->info.writes_memory ||
3282 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3283 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3284 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3285 }
3286 si_set_active_descriptors_for_shader(sctx, sel);
3287 si_update_ps_colorbuf0_slot(sctx);
3288 }
3289
3290 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3291 {
3292 if (shader->is_optimized) {
3293 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3294 &shader->ready);
3295 }
3296
3297 util_queue_fence_destroy(&shader->ready);
3298
3299 if (shader->pm4) {
3300 /* If destroyed shaders were not unbound, the next compiled
3301 * shader variant could get the same pointer address and so
3302 * binding it to the same shader stage would be considered
3303 * a no-op, causing random behavior.
3304 */
3305 switch (shader->selector->type) {
3306 case PIPE_SHADER_VERTEX:
3307 if (shader->key.as_ls) {
3308 assert(sctx->chip_class <= GFX8);
3309 si_pm4_delete_state(sctx, ls, shader->pm4);
3310 } else if (shader->key.as_es) {
3311 assert(sctx->chip_class <= GFX8);
3312 si_pm4_delete_state(sctx, es, shader->pm4);
3313 } else if (shader->key.as_ngg) {
3314 si_pm4_delete_state(sctx, gs, shader->pm4);
3315 } else {
3316 si_pm4_delete_state(sctx, vs, shader->pm4);
3317 }
3318 break;
3319 case PIPE_SHADER_TESS_CTRL:
3320 si_pm4_delete_state(sctx, hs, shader->pm4);
3321 break;
3322 case PIPE_SHADER_TESS_EVAL:
3323 if (shader->key.as_es) {
3324 assert(sctx->chip_class <= GFX8);
3325 si_pm4_delete_state(sctx, es, shader->pm4);
3326 } else if (shader->key.as_ngg) {
3327 si_pm4_delete_state(sctx, gs, shader->pm4);
3328 } else {
3329 si_pm4_delete_state(sctx, vs, shader->pm4);
3330 }
3331 break;
3332 case PIPE_SHADER_GEOMETRY:
3333 if (shader->is_gs_copy_shader)
3334 si_pm4_delete_state(sctx, vs, shader->pm4);
3335 else
3336 si_pm4_delete_state(sctx, gs, shader->pm4);
3337 break;
3338 case PIPE_SHADER_FRAGMENT:
3339 si_pm4_delete_state(sctx, ps, shader->pm4);
3340 break;
3341 default:;
3342 }
3343 }
3344
3345 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3346 si_shader_destroy(shader);
3347 free(shader);
3348 }
3349
3350 void si_destroy_shader_selector(struct si_context *sctx,
3351 struct si_shader_selector *sel)
3352 {
3353 struct si_shader *p = sel->first_variant, *c;
3354 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3355 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3356 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3357 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3358 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3359 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3360 };
3361
3362 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3363
3364 if (current_shader[sel->type]->cso == sel) {
3365 current_shader[sel->type]->cso = NULL;
3366 current_shader[sel->type]->current = NULL;
3367 }
3368
3369 while (p) {
3370 c = p->next_variant;
3371 si_delete_shader(sctx, p);
3372 p = c;
3373 }
3374
3375 if (sel->main_shader_part)
3376 si_delete_shader(sctx, sel->main_shader_part);
3377 if (sel->main_shader_part_ls)
3378 si_delete_shader(sctx, sel->main_shader_part_ls);
3379 if (sel->main_shader_part_es)
3380 si_delete_shader(sctx, sel->main_shader_part_es);
3381 if (sel->main_shader_part_ngg)
3382 si_delete_shader(sctx, sel->main_shader_part_ngg);
3383 if (sel->gs_copy_shader)
3384 si_delete_shader(sctx, sel->gs_copy_shader);
3385
3386 util_queue_fence_destroy(&sel->ready);
3387 simple_mtx_destroy(&sel->mutex);
3388 ralloc_free(sel->nir);
3389 free(sel->nir_binary);
3390 free(sel);
3391 }
3392
3393 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3394 {
3395 struct si_context *sctx = (struct si_context *)ctx;
3396 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3397
3398 si_shader_selector_reference(sctx, &sel, NULL);
3399 }
3400
3401 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3402 struct si_shader *vs, unsigned name,
3403 unsigned index, unsigned interpolate)
3404 {
3405 struct si_shader_info *vsinfo = &vs->selector->info;
3406 unsigned j, offset, ps_input_cntl = 0;
3407
3408 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3409 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3410 name == TGSI_SEMANTIC_PRIMID)
3411 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3412
3413 if (name == TGSI_SEMANTIC_PCOORD ||
3414 (name == TGSI_SEMANTIC_TEXCOORD &&
3415 sctx->sprite_coord_enable & (1 << index))) {
3416 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3417 }
3418
3419 for (j = 0; j < vsinfo->num_outputs; j++) {
3420 if (name == vsinfo->output_semantic_name[j] &&
3421 index == vsinfo->output_semantic_index[j]) {
3422 offset = vs->info.vs_output_param_offset[j];
3423
3424 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3425 /* The input is loaded from parameter memory. */
3426 ps_input_cntl |= S_028644_OFFSET(offset);
3427 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3428 if (offset == AC_EXP_PARAM_UNDEFINED) {
3429 /* This can happen with depth-only rendering. */
3430 offset = 0;
3431 } else {
3432 /* The input is a DEFAULT_VAL constant. */
3433 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3434 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3435 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3436 }
3437
3438 ps_input_cntl = S_028644_OFFSET(0x20) |
3439 S_028644_DEFAULT_VAL(offset);
3440 }
3441 break;
3442 }
3443 }
3444
3445 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3446 /* PrimID is written after the last output when HW VS is used. */
3447 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3448 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3449 /* No corresponding output found, load defaults into input.
3450 * Don't set any other bits.
3451 * (FLAT_SHADE=1 completely changes behavior) */
3452 ps_input_cntl = S_028644_OFFSET(0x20);
3453 /* D3D 9 behaviour. GL is undefined */
3454 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3455 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3456 }
3457 return ps_input_cntl;
3458 }
3459
3460 static void si_emit_spi_map(struct si_context *sctx)
3461 {
3462 struct si_shader *ps = sctx->ps_shader.current;
3463 struct si_shader *vs = si_get_vs_state(sctx);
3464 struct si_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3465 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3466 unsigned spi_ps_input_cntl[32];
3467
3468 if (!ps || !ps->selector->info.num_inputs)
3469 return;
3470
3471 num_interp = si_get_ps_num_interp(ps);
3472 assert(num_interp > 0);
3473
3474 for (i = 0; i < psinfo->num_inputs; i++) {
3475 unsigned name = psinfo->input_semantic_name[i];
3476 unsigned index = psinfo->input_semantic_index[i];
3477 unsigned interpolate = psinfo->input_interpolate[i];
3478
3479 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3480 index, interpolate);
3481
3482 if (name == TGSI_SEMANTIC_COLOR) {
3483 assert(index < ARRAY_SIZE(bcol_interp));
3484 bcol_interp[index] = interpolate;
3485 }
3486 }
3487
3488 if (ps->key.part.ps.prolog.color_two_side) {
3489 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3490
3491 for (i = 0; i < 2; i++) {
3492 if (!(psinfo->colors_read & (0xf << (i * 4))))
3493 continue;
3494
3495 spi_ps_input_cntl[num_written++] =
3496 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3497
3498 }
3499 }
3500 assert(num_interp == num_written);
3501
3502 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3503 /* Dota 2: Only ~16% of SPI map updates set different values. */
3504 /* Talos: Only ~9% of SPI map updates set different values. */
3505 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3506 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3507 spi_ps_input_cntl,
3508 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3509
3510 if (initial_cdw != sctx->gfx_cs->current.cdw)
3511 sctx->context_roll = true;
3512 }
3513
3514 /**
3515 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3516 */
3517 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3518 {
3519 if (sctx->init_config_has_vgt_flush)
3520 return;
3521
3522 /* Done by Vulkan before VGT_FLUSH. */
3523 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3524 si_pm4_cmd_add(sctx->init_config,
3525 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3526 si_pm4_cmd_end(sctx->init_config, false);
3527
3528 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3529 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3530 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3531 si_pm4_cmd_end(sctx->init_config, false);
3532 sctx->init_config_has_vgt_flush = true;
3533 }
3534
3535 /* Initialize state related to ESGS / GSVS ring buffers */
3536 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3537 {
3538 struct si_shader_selector *es =
3539 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3540 struct si_shader_selector *gs = sctx->gs_shader.cso;
3541 struct si_pm4_state *pm4;
3542
3543 /* Chip constants. */
3544 unsigned num_se = sctx->screen->info.max_se;
3545 unsigned wave_size = 64;
3546 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3547 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3548 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3549 */
3550 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3551 unsigned alignment = 256 * num_se;
3552 /* The maximum size is 63.999 MB per SE. */
3553 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3554
3555 /* Calculate the minimum size. */
3556 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3557 wave_size, alignment);
3558
3559 /* These are recommended sizes, not minimum sizes. */
3560 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3561 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3562 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3563 gs->max_gsvs_emit_size;
3564
3565 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3566 esgs_ring_size = align(esgs_ring_size, alignment);
3567 gsvs_ring_size = align(gsvs_ring_size, alignment);
3568
3569 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3570 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3571
3572 /* Some rings don't have to be allocated if shaders don't use them.
3573 * (e.g. no varyings between ES and GS or GS and VS)
3574 *
3575 * GFX9 doesn't have the ESGS ring.
3576 */
3577 bool update_esgs = sctx->chip_class <= GFX8 &&
3578 esgs_ring_size &&
3579 (!sctx->esgs_ring ||
3580 sctx->esgs_ring->width0 < esgs_ring_size);
3581 bool update_gsvs = gsvs_ring_size &&
3582 (!sctx->gsvs_ring ||
3583 sctx->gsvs_ring->width0 < gsvs_ring_size);
3584
3585 if (!update_esgs && !update_gsvs)
3586 return true;
3587
3588 if (update_esgs) {
3589 pipe_resource_reference(&sctx->esgs_ring, NULL);
3590 sctx->esgs_ring =
3591 pipe_aligned_buffer_create(sctx->b.screen,
3592 SI_RESOURCE_FLAG_UNMAPPABLE,
3593 PIPE_USAGE_DEFAULT,
3594 esgs_ring_size,
3595 sctx->screen->info.pte_fragment_size);
3596 if (!sctx->esgs_ring)
3597 return false;
3598 }
3599
3600 if (update_gsvs) {
3601 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3602 sctx->gsvs_ring =
3603 pipe_aligned_buffer_create(sctx->b.screen,
3604 SI_RESOURCE_FLAG_UNMAPPABLE,
3605 PIPE_USAGE_DEFAULT,
3606 gsvs_ring_size,
3607 sctx->screen->info.pte_fragment_size);
3608 if (!sctx->gsvs_ring)
3609 return false;
3610 }
3611
3612 /* Create the "init_config_gs_rings" state. */
3613 pm4 = CALLOC_STRUCT(si_pm4_state);
3614 if (!pm4)
3615 return false;
3616
3617 if (sctx->chip_class >= GFX7) {
3618 if (sctx->esgs_ring) {
3619 assert(sctx->chip_class <= GFX8);
3620 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3621 sctx->esgs_ring->width0 / 256);
3622 }
3623 if (sctx->gsvs_ring)
3624 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3625 sctx->gsvs_ring->width0 / 256);
3626 } else {
3627 if (sctx->esgs_ring)
3628 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3629 sctx->esgs_ring->width0 / 256);
3630 if (sctx->gsvs_ring)
3631 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3632 sctx->gsvs_ring->width0 / 256);
3633 }
3634
3635 /* Set the state. */
3636 if (sctx->init_config_gs_rings)
3637 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3638 sctx->init_config_gs_rings = pm4;
3639
3640 if (!sctx->init_config_has_vgt_flush) {
3641 si_init_config_add_vgt_flush(sctx);
3642 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3643 }
3644
3645 /* Flush the context to re-emit both init_config states. */
3646 sctx->initial_gfx_cs_size = 0; /* force flush */
3647 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3648
3649 /* Set ring bindings. */
3650 if (sctx->esgs_ring) {
3651 assert(sctx->chip_class <= GFX8);
3652 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3653 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3654 true, true, 4, 64, 0);
3655 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3656 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3657 false, false, 0, 0, 0);
3658 }
3659 if (sctx->gsvs_ring) {
3660 si_set_ring_buffer(sctx, SI_RING_GSVS,
3661 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3662 false, false, 0, 0, 0);
3663 }
3664
3665 return true;
3666 }
3667
3668 static void si_shader_lock(struct si_shader *shader)
3669 {
3670 simple_mtx_lock(&shader->selector->mutex);
3671 if (shader->previous_stage_sel) {
3672 assert(shader->previous_stage_sel != shader->selector);
3673 simple_mtx_lock(&shader->previous_stage_sel->mutex);
3674 }
3675 }
3676
3677 static void si_shader_unlock(struct si_shader *shader)
3678 {
3679 if (shader->previous_stage_sel)
3680 simple_mtx_unlock(&shader->previous_stage_sel->mutex);
3681 simple_mtx_unlock(&shader->selector->mutex);
3682 }
3683
3684 /**
3685 * @returns 1 if \p sel has been updated to use a new scratch buffer
3686 * 0 if not
3687 * < 0 if there was a failure
3688 */
3689 static int si_update_scratch_buffer(struct si_context *sctx,
3690 struct si_shader *shader)
3691 {
3692 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3693
3694 if (!shader)
3695 return 0;
3696
3697 /* This shader doesn't need a scratch buffer */
3698 if (shader->config.scratch_bytes_per_wave == 0)
3699 return 0;
3700
3701 /* Prevent race conditions when updating:
3702 * - si_shader::scratch_bo
3703 * - si_shader::binary::code
3704 * - si_shader::previous_stage::binary::code.
3705 */
3706 si_shader_lock(shader);
3707
3708 /* This shader is already configured to use the current
3709 * scratch buffer. */
3710 if (shader->scratch_bo == sctx->scratch_buffer) {
3711 si_shader_unlock(shader);
3712 return 0;
3713 }
3714
3715 assert(sctx->scratch_buffer);
3716
3717 /* Replace the shader bo with a new bo that has the relocs applied. */
3718 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3719 si_shader_unlock(shader);
3720 return -1;
3721 }
3722
3723 /* Update the shader state to use the new shader bo. */
3724 si_shader_init_pm4_state(sctx->screen, shader);
3725
3726 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3727
3728 si_shader_unlock(shader);
3729 return 1;
3730 }
3731
3732 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3733 {
3734 return shader ? shader->config.scratch_bytes_per_wave : 0;
3735 }
3736
3737 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3738 {
3739 if (!sctx->tes_shader.cso)
3740 return NULL; /* tessellation disabled */
3741
3742 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3743 sctx->fixed_func_tcs_shader.current;
3744 }
3745
3746 static bool si_update_scratch_relocs(struct si_context *sctx)
3747 {
3748 struct si_shader *tcs = si_get_tcs_current(sctx);
3749 int r;
3750
3751 /* Update the shaders, so that they are using the latest scratch.
3752 * The scratch buffer may have been changed since these shaders were
3753 * last used, so we still need to try to update them, even if they
3754 * require scratch buffers smaller than the current size.
3755 */
3756 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3757 if (r < 0)
3758 return false;
3759 if (r == 1)
3760 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3761
3762 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3763 if (r < 0)
3764 return false;
3765 if (r == 1)
3766 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3767
3768 r = si_update_scratch_buffer(sctx, tcs);
3769 if (r < 0)
3770 return false;
3771 if (r == 1)
3772 si_pm4_bind_state(sctx, hs, tcs->pm4);
3773
3774 /* VS can be bound as LS, ES, or VS. */
3775 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3776 if (r < 0)
3777 return false;
3778 if (r == 1) {
3779 if (sctx->vs_shader.current->key.as_ls)
3780 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3781 else if (sctx->vs_shader.current->key.as_es)
3782 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3783 else if (sctx->vs_shader.current->key.as_ngg)
3784 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3785 else
3786 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3787 }
3788
3789 /* TES can be bound as ES or VS. */
3790 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3791 if (r < 0)
3792 return false;
3793 if (r == 1) {
3794 if (sctx->tes_shader.current->key.as_es)
3795 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3796 else if (sctx->tes_shader.current->key.as_ngg)
3797 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3798 else
3799 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3800 }
3801
3802 return true;
3803 }
3804
3805 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3806 {
3807 /* SPI_TMPRING_SIZE.WAVESIZE must be constant for each scratch buffer.
3808 * There are 2 cases to handle:
3809 *
3810 * - If the current needed size is less than the maximum seen size,
3811 * use the maximum seen size, so that WAVESIZE remains the same.
3812 *
3813 * - If the current needed size is greater than the maximum seen size,
3814 * the scratch buffer is reallocated, so we can increase WAVESIZE.
3815 *
3816 * Shaders that set SCRATCH_EN=0 don't allocate scratch space.
3817 * Otherwise, the number of waves that can use scratch is
3818 * SPI_TMPRING_SIZE.WAVES.
3819 */
3820 unsigned bytes = 0;
3821
3822 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3823 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3824 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3825
3826 if (sctx->tes_shader.cso) {
3827 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3828 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(si_get_tcs_current(sctx)));
3829 }
3830
3831 sctx->max_seen_scratch_bytes_per_wave =
3832 MAX2(sctx->max_seen_scratch_bytes_per_wave, bytes);
3833
3834 unsigned scratch_needed_size =
3835 sctx->max_seen_scratch_bytes_per_wave * sctx->scratch_waves;
3836 unsigned spi_tmpring_size;
3837
3838 if (scratch_needed_size > 0) {
3839 if (!sctx->scratch_buffer ||
3840 scratch_needed_size > sctx->scratch_buffer->b.b.width0) {
3841 /* Create a bigger scratch buffer */
3842 si_resource_reference(&sctx->scratch_buffer, NULL);
3843
3844 sctx->scratch_buffer =
3845 si_aligned_buffer_create(&sctx->screen->b,
3846 SI_RESOURCE_FLAG_UNMAPPABLE,
3847 PIPE_USAGE_DEFAULT,
3848 scratch_needed_size,
3849 sctx->screen->info.pte_fragment_size);
3850 if (!sctx->scratch_buffer)
3851 return false;
3852
3853 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3854 si_context_add_resource_size(sctx,
3855 &sctx->scratch_buffer->b.b);
3856 }
3857
3858 if (!si_update_scratch_relocs(sctx))
3859 return false;
3860 }
3861
3862 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3863 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3864 "scratch size should already be aligned correctly.");
3865
3866 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3867 S_0286E8_WAVESIZE(sctx->max_seen_scratch_bytes_per_wave >> 10);
3868 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3869 sctx->spi_tmpring_size = spi_tmpring_size;
3870 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3871 }
3872 return true;
3873 }
3874
3875 static void si_init_tess_factor_ring(struct si_context *sctx)
3876 {
3877 assert(!sctx->tess_rings);
3878 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3879
3880 /* The address must be aligned to 2^19, because the shader only
3881 * receives the high 13 bits.
3882 */
3883 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3884 SI_RESOURCE_FLAG_32BIT,
3885 PIPE_USAGE_DEFAULT,
3886 sctx->screen->tess_offchip_ring_size +
3887 sctx->screen->tess_factor_ring_size,
3888 1 << 19);
3889 if (!sctx->tess_rings)
3890 return;
3891
3892 si_init_config_add_vgt_flush(sctx);
3893
3894 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3895 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3896
3897 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3898 sctx->screen->tess_offchip_ring_size;
3899
3900 /* Append these registers to the init config state. */
3901 if (sctx->chip_class >= GFX7) {
3902 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3903 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3904 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3905 factor_va >> 8);
3906 if (sctx->chip_class >= GFX10)
3907 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3908 S_030984_BASE_HI(factor_va >> 40));
3909 else if (sctx->chip_class == GFX9)
3910 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3911 S_030944_BASE_HI(factor_va >> 40));
3912 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3913 sctx->screen->vgt_hs_offchip_param);
3914 } else {
3915 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3916 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3917 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3918 factor_va >> 8);
3919 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3920 sctx->screen->vgt_hs_offchip_param);
3921 }
3922
3923 /* Flush the context to re-emit the init_config state.
3924 * This is done only once in a lifetime of a context.
3925 */
3926 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3927 sctx->initial_gfx_cs_size = 0; /* force flush */
3928 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3929 }
3930
3931 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3932 union si_vgt_stages_key key)
3933 {
3934 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3935 uint32_t stages = 0;
3936
3937 if (key.u.tess) {
3938 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3939 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3940
3941 if (key.u.gs)
3942 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3943 S_028B54_GS_EN(1);
3944 else if (key.u.ngg)
3945 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3946 else
3947 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3948 } else if (key.u.gs) {
3949 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3950 S_028B54_GS_EN(1);
3951 } else if (key.u.ngg) {
3952 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3953 }
3954
3955 if (key.u.ngg) {
3956 stages |= S_028B54_PRIMGEN_EN(1) |
3957 S_028B54_NGG_WAVE_ID_EN(key.u.streamout) |
3958 S_028B54_PRIMGEN_PASSTHRU_EN(key.u.ngg_passthrough);
3959 } else if (key.u.gs)
3960 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3961
3962 if (screen->info.chip_class >= GFX9)
3963 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3964
3965 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3966 stages |= S_028B54_HS_W32_EN(1) |
3967 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3968 S_028B54_VS_W32_EN(1);
3969 }
3970
3971 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3972 return pm4;
3973 }
3974
3975 static void si_update_vgt_shader_config(struct si_context *sctx,
3976 union si_vgt_stages_key key)
3977 {
3978 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3979
3980 if (unlikely(!*pm4))
3981 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3982 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3983 }
3984
3985 bool si_update_shaders(struct si_context *sctx)
3986 {
3987 struct pipe_context *ctx = (struct pipe_context*)sctx;
3988 struct si_compiler_ctx_state compiler_state;
3989 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3990 struct si_shader *old_vs = si_get_vs_state(sctx);
3991 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3992 struct si_shader *old_ps = sctx->ps_shader.current;
3993 union si_vgt_stages_key key;
3994 unsigned old_spi_shader_col_format =
3995 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3996 int r;
3997
3998 if (!sctx->compiler.passes)
3999 si_init_compiler(sctx->screen, &sctx->compiler);
4000
4001 compiler_state.compiler = &sctx->compiler;
4002 compiler_state.debug = sctx->debug;
4003 compiler_state.is_debug_context = sctx->is_debug;
4004
4005 key.index = 0;
4006
4007 if (sctx->tes_shader.cso)
4008 key.u.tess = 1;
4009 if (sctx->gs_shader.cso)
4010 key.u.gs = 1;
4011
4012 if (sctx->ngg) {
4013 key.u.ngg = 1;
4014 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
4015 }
4016
4017 /* Update TCS and TES. */
4018 if (sctx->tes_shader.cso) {
4019 if (!sctx->tess_rings) {
4020 si_init_tess_factor_ring(sctx);
4021 if (!sctx->tess_rings)
4022 return false;
4023 }
4024
4025 if (sctx->tcs_shader.cso) {
4026 r = si_shader_select(ctx, &sctx->tcs_shader, key,
4027 &compiler_state);
4028 if (r)
4029 return false;
4030 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
4031 } else {
4032 if (!sctx->fixed_func_tcs_shader.cso) {
4033 sctx->fixed_func_tcs_shader.cso =
4034 si_create_fixed_func_tcs(sctx);
4035 if (!sctx->fixed_func_tcs_shader.cso)
4036 return false;
4037 }
4038
4039 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
4040 key, &compiler_state);
4041 if (r)
4042 return false;
4043 si_pm4_bind_state(sctx, hs,
4044 sctx->fixed_func_tcs_shader.current->pm4);
4045 }
4046
4047 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
4048 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
4049 if (r)
4050 return false;
4051
4052 if (sctx->gs_shader.cso) {
4053 /* TES as ES */
4054 assert(sctx->chip_class <= GFX8);
4055 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
4056 } else if (key.u.ngg) {
4057 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
4058 } else {
4059 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
4060 }
4061 }
4062 } else {
4063 if (sctx->chip_class <= GFX8)
4064 si_pm4_bind_state(sctx, ls, NULL);
4065 si_pm4_bind_state(sctx, hs, NULL);
4066 }
4067
4068 /* Update GS. */
4069 if (sctx->gs_shader.cso) {
4070 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
4071 if (r)
4072 return false;
4073 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
4074 if (!key.u.ngg) {
4075 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
4076
4077 if (!si_update_gs_ring_buffers(sctx))
4078 return false;
4079 } else {
4080 si_pm4_bind_state(sctx, vs, NULL);
4081 }
4082 } else {
4083 if (!key.u.ngg) {
4084 si_pm4_bind_state(sctx, gs, NULL);
4085 if (sctx->chip_class <= GFX8)
4086 si_pm4_bind_state(sctx, es, NULL);
4087 }
4088 }
4089
4090 /* Update VS. */
4091 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
4092 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
4093 if (r)
4094 return false;
4095
4096 if (!key.u.tess && !key.u.gs) {
4097 if (key.u.ngg) {
4098 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
4099 si_pm4_bind_state(sctx, vs, NULL);
4100 } else {
4101 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
4102 }
4103 } else if (sctx->tes_shader.cso) {
4104 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
4105 } else {
4106 assert(sctx->gs_shader.cso);
4107 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
4108 }
4109 }
4110
4111 /* This must be done after the shader variant is selected. */
4112 if (sctx->ngg)
4113 key.u.ngg_passthrough = gfx10_is_ngg_passthrough(si_get_vs(sctx)->current);
4114
4115 si_update_vgt_shader_config(sctx, key);
4116
4117 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
4118 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4119
4120 if (sctx->ps_shader.cso) {
4121 unsigned db_shader_control;
4122
4123 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4124 if (r)
4125 return false;
4126 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4127
4128 db_shader_control =
4129 sctx->ps_shader.cso->db_shader_control |
4130 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4131
4132 if (si_pm4_state_changed(sctx, ps) ||
4133 si_pm4_state_changed(sctx, vs) ||
4134 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4135 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4136 sctx->flatshade != rs->flatshade) {
4137 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4138 sctx->flatshade = rs->flatshade;
4139 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4140 }
4141
4142 if (sctx->screen->info.rbplus_allowed &&
4143 si_pm4_state_changed(sctx, ps) &&
4144 (!old_ps ||
4145 old_spi_shader_col_format !=
4146 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4147 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4148
4149 if (sctx->ps_db_shader_control != db_shader_control) {
4150 sctx->ps_db_shader_control = db_shader_control;
4151 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4152 if (sctx->screen->dpbb_allowed)
4153 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4154 }
4155
4156 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4157 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4158 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4159
4160 if (sctx->chip_class == GFX6)
4161 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4162
4163 if (sctx->framebuffer.nr_samples <= 1)
4164 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4165 }
4166 }
4167
4168 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4169 si_pm4_state_enabled_and_changed(sctx, hs) ||
4170 si_pm4_state_enabled_and_changed(sctx, es) ||
4171 si_pm4_state_enabled_and_changed(sctx, gs) ||
4172 si_pm4_state_enabled_and_changed(sctx, vs) ||
4173 si_pm4_state_enabled_and_changed(sctx, ps)) {
4174 if (!si_update_spi_tmpring_size(sctx))
4175 return false;
4176 }
4177
4178 if (sctx->chip_class >= GFX7) {
4179 if (si_pm4_state_enabled_and_changed(sctx, ls))
4180 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4181 else if (!sctx->queued.named.ls)
4182 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4183
4184 if (si_pm4_state_enabled_and_changed(sctx, hs))
4185 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4186 else if (!sctx->queued.named.hs)
4187 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4188
4189 if (si_pm4_state_enabled_and_changed(sctx, es))
4190 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4191 else if (!sctx->queued.named.es)
4192 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4193
4194 if (si_pm4_state_enabled_and_changed(sctx, gs))
4195 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4196 else if (!sctx->queued.named.gs)
4197 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4198
4199 if (si_pm4_state_enabled_and_changed(sctx, vs))
4200 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4201 else if (!sctx->queued.named.vs)
4202 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4203
4204 if (si_pm4_state_enabled_and_changed(sctx, ps))
4205 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4206 else if (!sctx->queued.named.ps)
4207 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4208 }
4209
4210 sctx->do_update_shaders = false;
4211 return true;
4212 }
4213
4214 static void si_emit_scratch_state(struct si_context *sctx)
4215 {
4216 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4217
4218 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4219 sctx->spi_tmpring_size);
4220
4221 if (sctx->scratch_buffer) {
4222 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4223 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4224 RADEON_PRIO_SCRATCH_BUFFER);
4225 }
4226 }
4227
4228 void si_init_shader_functions(struct si_context *sctx)
4229 {
4230 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4231 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4232
4233 sctx->b.create_vs_state = si_create_shader_selector;
4234 sctx->b.create_tcs_state = si_create_shader_selector;
4235 sctx->b.create_tes_state = si_create_shader_selector;
4236 sctx->b.create_gs_state = si_create_shader_selector;
4237 sctx->b.create_fs_state = si_create_shader_selector;
4238
4239 sctx->b.bind_vs_state = si_bind_vs_shader;
4240 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4241 sctx->b.bind_tes_state = si_bind_tes_shader;
4242 sctx->b.bind_gs_state = si_bind_gs_shader;
4243 sctx->b.bind_fs_state = si_bind_ps_shader;
4244
4245 sctx->b.delete_vs_state = si_delete_shader_selector;
4246 sctx->b.delete_tcs_state = si_delete_shader_selector;
4247 sctx->b.delete_tes_state = si_delete_shader_selector;
4248 sctx->b.delete_gs_state = si_delete_shader_selector;
4249 sctx->b.delete_fs_state = si_delete_shader_selector;
4250 }