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radeonsi/gfx10: implement a GE bug workaround
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 void *si_get_ir_binary(struct si_shader_selector *sel)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 unsigned size = 4 + ir_size + sizeof(sel->so);
68 char *result = (char*)MALLOC(size);
69 if (!result)
70 return NULL;
71
72 *((uint32_t*)result) = size;
73 memcpy(result + 4, ir_binary, ir_size);
74 memcpy(result + 4 + ir_size, &sel->so, sizeof(sel->so));
75
76 if (sel->nir)
77 blob_finish(&blob);
78
79 return result;
80 }
81
82 /** Copy "data" to "ptr" and return the next dword following copied data. */
83 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
84 {
85 /* data may be NULL if size == 0 */
86 if (size)
87 memcpy(ptr, data, size);
88 ptr += DIV_ROUND_UP(size, 4);
89 return ptr;
90 }
91
92 /** Read data from "ptr". Return the next dword following the data. */
93 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
94 {
95 memcpy(data, ptr, size);
96 ptr += DIV_ROUND_UP(size, 4);
97 return ptr;
98 }
99
100 /**
101 * Write the size as uint followed by the data. Return the next dword
102 * following the copied data.
103 */
104 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
105 {
106 *ptr++ = size;
107 return write_data(ptr, data, size);
108 }
109
110 /**
111 * Read the size as uint followed by the data. Return both via parameters.
112 * Return the next dword following the data.
113 */
114 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
115 {
116 *size = *ptr++;
117 assert(*data == NULL);
118 if (!*size)
119 return ptr;
120 *data = malloc(*size);
121 return read_data(ptr, *data, *size);
122 }
123
124 /**
125 * Return the shader binary in a buffer. The first 4 bytes contain its size
126 * as integer.
127 */
128 static void *si_get_shader_binary(struct si_shader *shader)
129 {
130 /* There is always a size of data followed by the data itself. */
131 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
132 strlen(shader->binary.llvm_ir_string) + 1 : 0;
133
134 /* Refuse to allocate overly large buffers and guard against integer
135 * overflow. */
136 if (shader->binary.elf_size > UINT_MAX / 4 ||
137 llvm_ir_size > UINT_MAX / 4)
138 return NULL;
139
140 unsigned size =
141 4 + /* total size */
142 4 + /* CRC32 of the data below */
143 align(sizeof(shader->config), 4) +
144 align(sizeof(shader->info), 4) +
145 4 + align(shader->binary.elf_size, 4) +
146 4 + align(llvm_ir_size, 4);
147 void *buffer = CALLOC(1, size);
148 uint32_t *ptr = (uint32_t*)buffer;
149
150 if (!buffer)
151 return NULL;
152
153 *ptr++ = size;
154 ptr++; /* CRC32 is calculated at the end. */
155
156 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
157 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
158 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
159 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
160 assert((char *)ptr - (char *)buffer == size);
161
162 /* Compute CRC32. */
163 ptr = (uint32_t*)buffer;
164 ptr++;
165 *ptr = util_hash_crc32(ptr + 1, size - 8);
166
167 return buffer;
168 }
169
170 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
171 {
172 uint32_t *ptr = (uint32_t*)binary;
173 uint32_t size = *ptr++;
174 uint32_t crc32 = *ptr++;
175 unsigned chunk_size;
176 unsigned elf_size;
177
178 if (util_hash_crc32(ptr, size - 8) != crc32) {
179 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
180 return false;
181 }
182
183 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
184 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
185 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
186 &elf_size);
187 shader->binary.elf_size = elf_size;
188 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
189
190 return true;
191 }
192
193 /**
194 * Insert a shader into the cache. It's assumed the shader is not in the cache.
195 * Use si_shader_cache_load_shader before calling this.
196 *
197 * Returns false on failure, in which case the ir_binary should be freed.
198 */
199 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
200 struct si_shader *shader,
201 bool insert_into_disk_cache)
202 {
203 void *hw_binary;
204 struct hash_entry *entry;
205 uint8_t key[CACHE_KEY_SIZE];
206
207 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
208 if (entry)
209 return false; /* already added */
210
211 hw_binary = si_get_shader_binary(shader);
212 if (!hw_binary)
213 return false;
214
215 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
216 hw_binary) == NULL) {
217 FREE(hw_binary);
218 return false;
219 }
220
221 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
222 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
223 *((uint32_t *)ir_binary), key);
224 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
225 *((uint32_t *) hw_binary), NULL);
226 }
227
228 return true;
229 }
230
231 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
232 struct si_shader *shader)
233 {
234 struct hash_entry *entry =
235 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
236 if (!entry) {
237 if (sscreen->disk_shader_cache) {
238 unsigned char sha1[CACHE_KEY_SIZE];
239 size_t tg_size = *((uint32_t *) ir_binary);
240
241 disk_cache_compute_key(sscreen->disk_shader_cache,
242 ir_binary, tg_size, sha1);
243
244 size_t binary_size;
245 uint8_t *buffer =
246 disk_cache_get(sscreen->disk_shader_cache,
247 sha1, &binary_size);
248 if (!buffer)
249 return false;
250
251 if (binary_size < sizeof(uint32_t) ||
252 *((uint32_t*)buffer) != binary_size) {
253 /* Something has gone wrong discard the item
254 * from the cache and rebuild/link from
255 * source.
256 */
257 assert(!"Invalid radeonsi shader disk cache "
258 "item!");
259
260 disk_cache_remove(sscreen->disk_shader_cache,
261 sha1);
262 free(buffer);
263
264 return false;
265 }
266
267 if (!si_load_shader_binary(shader, buffer)) {
268 free(buffer);
269 return false;
270 }
271 free(buffer);
272
273 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
274 shader, false))
275 FREE(ir_binary);
276 } else {
277 return false;
278 }
279 } else {
280 if (si_load_shader_binary(shader, entry->data))
281 FREE(ir_binary);
282 else
283 return false;
284 }
285 p_atomic_inc(&sscreen->num_shader_cache_hits);
286 return true;
287 }
288
289 static uint32_t si_shader_cache_key_hash(const void *key)
290 {
291 /* The first dword is the key size. */
292 return util_hash_crc32(key, *(uint32_t*)key);
293 }
294
295 static bool si_shader_cache_key_equals(const void *a, const void *b)
296 {
297 uint32_t *keya = (uint32_t*)a;
298 uint32_t *keyb = (uint32_t*)b;
299
300 /* The first dword is the key size. */
301 if (*keya != *keyb)
302 return false;
303
304 return memcmp(keya, keyb, *keya) == 0;
305 }
306
307 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
308 {
309 FREE((void*)entry->key);
310 FREE(entry->data);
311 }
312
313 bool si_init_shader_cache(struct si_screen *sscreen)
314 {
315 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
316 sscreen->shader_cache =
317 _mesa_hash_table_create(NULL,
318 si_shader_cache_key_hash,
319 si_shader_cache_key_equals);
320
321 return sscreen->shader_cache != NULL;
322 }
323
324 void si_destroy_shader_cache(struct si_screen *sscreen)
325 {
326 if (sscreen->shader_cache)
327 _mesa_hash_table_destroy(sscreen->shader_cache,
328 si_destroy_shader_cache_entry);
329 mtx_destroy(&sscreen->shader_cache_mutex);
330 }
331
332 /* SHADER STATES */
333
334 static void si_set_tesseval_regs(struct si_screen *sscreen,
335 const struct si_shader_selector *tes,
336 struct si_pm4_state *pm4)
337 {
338 const struct tgsi_shader_info *info = &tes->info;
339 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
340 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
341 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
342 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
343 unsigned type, partitioning, topology, distribution_mode;
344
345 switch (tes_prim_mode) {
346 case PIPE_PRIM_LINES:
347 type = V_028B6C_TESS_ISOLINE;
348 break;
349 case PIPE_PRIM_TRIANGLES:
350 type = V_028B6C_TESS_TRIANGLE;
351 break;
352 case PIPE_PRIM_QUADS:
353 type = V_028B6C_TESS_QUAD;
354 break;
355 default:
356 assert(0);
357 return;
358 }
359
360 switch (tes_spacing) {
361 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
362 partitioning = V_028B6C_PART_FRAC_ODD;
363 break;
364 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
365 partitioning = V_028B6C_PART_FRAC_EVEN;
366 break;
367 case PIPE_TESS_SPACING_EQUAL:
368 partitioning = V_028B6C_PART_INTEGER;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 if (tes_point_mode)
376 topology = V_028B6C_OUTPUT_POINT;
377 else if (tes_prim_mode == PIPE_PRIM_LINES)
378 topology = V_028B6C_OUTPUT_LINE;
379 else if (tes_vertex_order_cw)
380 /* for some reason, this must be the other way around */
381 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
382 else
383 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
384
385 if (sscreen->has_distributed_tess) {
386 if (sscreen->info.family == CHIP_FIJI ||
387 sscreen->info.family >= CHIP_POLARIS10)
388 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
389 else
390 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
391 } else
392 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
393
394 assert(pm4->shader);
395 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
396 S_028B6C_PARTITIONING(partitioning) |
397 S_028B6C_TOPOLOGY(topology) |
398 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
399 }
400
401 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
402 * whether the "fractional odd" tessellation spacing is used.
403 *
404 * Possible VGT configurations and which state should set the register:
405 *
406 * Reg set in | VGT shader configuration | Value
407 * ------------------------------------------------------
408 * VS as VS | VS | 30
409 * VS as ES | ES -> GS -> VS | 30
410 * TES as VS | LS -> HS -> VS | 14 or 30
411 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
412 *
413 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
414 */
415 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
416 struct si_shader_selector *sel,
417 struct si_shader *shader,
418 struct si_pm4_state *pm4)
419 {
420 unsigned type = sel->type;
421
422 if (sscreen->info.family < CHIP_POLARIS10 ||
423 sscreen->info.chip_class >= GFX10)
424 return;
425
426 /* VS as VS, or VS as ES: */
427 if ((type == PIPE_SHADER_VERTEX &&
428 (!shader ||
429 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
430 /* TES as VS, or TES as ES: */
431 type == PIPE_SHADER_TESS_EVAL) {
432 unsigned vtx_reuse_depth = 30;
433
434 if (type == PIPE_SHADER_TESS_EVAL &&
435 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
436 PIPE_TESS_SPACING_FRACTIONAL_ODD)
437 vtx_reuse_depth = 14;
438
439 assert(pm4->shader);
440 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
441 }
442 }
443
444 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
445 {
446 if (shader->pm4)
447 si_pm4_clear_state(shader->pm4);
448 else
449 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
450
451 if (shader->pm4) {
452 shader->pm4->shader = shader;
453 return shader->pm4;
454 } else {
455 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
456 return NULL;
457 }
458 }
459
460 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
461 {
462 /* Add the pointer to VBO descriptors. */
463 return num_always_on_user_sgprs + 1;
464 }
465
466 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
467 {
468 struct si_pm4_state *pm4;
469 unsigned vgpr_comp_cnt;
470 uint64_t va;
471
472 assert(sscreen->info.chip_class <= GFX8);
473
474 pm4 = si_get_shader_pm4_state(shader);
475 if (!pm4)
476 return;
477
478 va = shader->bo->gpu_address;
479 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
480
481 /* We need at least 2 components for LS.
482 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
483 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
484 */
485 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
486
487 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
488 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
489
490 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
491 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
492 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
493 S_00B528_DX10_CLAMP(1) |
494 S_00B528_FLOAT_MODE(shader->config.float_mode);
495 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
496 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
497 }
498
499 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
500 {
501 struct si_pm4_state *pm4;
502 uint64_t va;
503 unsigned ls_vgpr_comp_cnt = 0;
504
505 pm4 = si_get_shader_pm4_state(shader);
506 if (!pm4)
507 return;
508
509 va = shader->bo->gpu_address;
510 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
511
512 if (sscreen->info.chip_class >= GFX9) {
513 if (sscreen->info.chip_class >= GFX10) {
514 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
515 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
516 } else {
517 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
518 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
519 }
520
521 /* We need at least 2 components for LS.
522 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
523 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
524 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
525 * be loaded.
526 */
527 ls_vgpr_comp_cnt = 1;
528 if (shader->info.uses_instanceid) {
529 if (sscreen->info.chip_class >= GFX10)
530 ls_vgpr_comp_cnt = 3;
531 else
532 ls_vgpr_comp_cnt = 2;
533 }
534
535 unsigned num_user_sgprs =
536 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
537
538 shader->config.rsrc2 =
539 S_00B42C_USER_SGPR(num_user_sgprs) |
540 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
541
542 if (sscreen->info.chip_class >= GFX10)
543 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
544 else
545 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
546 } else {
547 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
548 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
549
550 shader->config.rsrc2 =
551 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
552 S_00B42C_OC_LDS_EN(1) |
553 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
554 }
555
556 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
557 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
558 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
559 (sscreen->info.chip_class <= GFX9 ?
560 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
561 S_00B428_DX10_CLAMP(1) |
562 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
563 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
564 S_00B428_FLOAT_MODE(shader->config.float_mode) |
565 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
566
567 if (sscreen->info.chip_class <= GFX8) {
568 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
569 shader->config.rsrc2);
570 }
571 }
572
573 static void si_emit_shader_es(struct si_context *sctx)
574 {
575 struct si_shader *shader = sctx->queued.named.es->shader;
576 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
577
578 if (!shader)
579 return;
580
581 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
582 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
583 shader->selector->esgs_itemsize / 4);
584
585 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
586 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
587 SI_TRACKED_VGT_TF_PARAM,
588 shader->vgt_tf_param);
589
590 if (shader->vgt_vertex_reuse_block_cntl)
591 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
592 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
593 shader->vgt_vertex_reuse_block_cntl);
594
595 if (initial_cdw != sctx->gfx_cs->current.cdw)
596 sctx->context_roll = true;
597 }
598
599 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
600 {
601 struct si_pm4_state *pm4;
602 unsigned num_user_sgprs;
603 unsigned vgpr_comp_cnt;
604 uint64_t va;
605 unsigned oc_lds_en;
606
607 assert(sscreen->info.chip_class <= GFX8);
608
609 pm4 = si_get_shader_pm4_state(shader);
610 if (!pm4)
611 return;
612
613 pm4->atom.emit = si_emit_shader_es;
614 va = shader->bo->gpu_address;
615 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
616
617 if (shader->selector->type == PIPE_SHADER_VERTEX) {
618 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
619 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
620 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
621 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
622 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
623 num_user_sgprs = SI_TES_NUM_USER_SGPR;
624 } else
625 unreachable("invalid shader selector type");
626
627 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
628
629 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
630 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
631 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
632 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
633 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
634 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
635 S_00B328_DX10_CLAMP(1) |
636 S_00B328_FLOAT_MODE(shader->config.float_mode));
637 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
638 S_00B32C_USER_SGPR(num_user_sgprs) |
639 S_00B32C_OC_LDS_EN(oc_lds_en) |
640 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
641
642 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
643 si_set_tesseval_regs(sscreen, shader->selector, pm4);
644
645 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
646 }
647
648 void gfx9_get_gs_info(struct si_shader_selector *es,
649 struct si_shader_selector *gs,
650 struct gfx9_gs_info *out)
651 {
652 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
653 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
654 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
655 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
656
657 /* All these are in dwords: */
658 /* We can't allow using the whole LDS, because GS waves compete with
659 * other shader stages for LDS space. */
660 const unsigned max_lds_size = 8 * 1024;
661 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
662 unsigned esgs_lds_size;
663
664 /* All these are per subgroup: */
665 const unsigned max_out_prims = 32 * 1024;
666 const unsigned max_es_verts = 255;
667 const unsigned ideal_gs_prims = 64;
668 unsigned max_gs_prims, gs_prims;
669 unsigned min_es_verts, es_verts, worst_case_es_verts;
670
671 if (uses_adjacency || gs_num_invocations > 1)
672 max_gs_prims = 127 / gs_num_invocations;
673 else
674 max_gs_prims = 255;
675
676 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
677 * Make sure we don't go over the maximum value.
678 */
679 if (gs->gs_max_out_vertices > 0) {
680 max_gs_prims = MIN2(max_gs_prims,
681 max_out_prims /
682 (gs->gs_max_out_vertices * gs_num_invocations));
683 }
684 assert(max_gs_prims > 0);
685
686 /* If the primitive has adjacency, halve the number of vertices
687 * that will be reused in multiple primitives.
688 */
689 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
690
691 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
692 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
693
694 /* Compute ESGS LDS size based on the worst case number of ES vertices
695 * needed to create the target number of GS prims per subgroup.
696 */
697 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
698
699 /* If total LDS usage is too big, refactor partitions based on ratio
700 * of ESGS item sizes.
701 */
702 if (esgs_lds_size > max_lds_size) {
703 /* Our target GS Prims Per Subgroup was too large. Calculate
704 * the maximum number of GS Prims Per Subgroup that will fit
705 * into LDS, capped by the maximum that the hardware can support.
706 */
707 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
708 max_gs_prims);
709 assert(gs_prims > 0);
710 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
711 max_es_verts);
712
713 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
714 assert(esgs_lds_size <= max_lds_size);
715 }
716
717 /* Now calculate remaining ESGS information. */
718 if (esgs_lds_size)
719 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
720 else
721 es_verts = max_es_verts;
722
723 /* Vertices for adjacency primitives are not always reused, so restore
724 * it for ES_VERTS_PER_SUBGRP.
725 */
726 min_es_verts = gs->gs_input_verts_per_prim;
727
728 /* For normal primitives, the VGT only checks if they are past the ES
729 * verts per subgroup after allocating a full GS primitive and if they
730 * are, kick off a new subgroup. But if those additional ES verts are
731 * unique (e.g. not reused) we need to make sure there is enough LDS
732 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
733 */
734 es_verts -= min_es_verts - 1;
735
736 out->es_verts_per_subgroup = es_verts;
737 out->gs_prims_per_subgroup = gs_prims;
738 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
739 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
740 gs->gs_max_out_vertices;
741 out->esgs_ring_size = 4 * esgs_lds_size;
742
743 assert(out->max_prims_per_subgroup <= max_out_prims);
744 }
745
746 static void si_emit_shader_gs(struct si_context *sctx)
747 {
748 struct si_shader *shader = sctx->queued.named.gs->shader;
749 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
750
751 if (!shader)
752 return;
753
754 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
755 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
756 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
757 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
758 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
759 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
760 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
761
762 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
763 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
764 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
765 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
766
767 /* R_028B38_VGT_GS_MAX_VERT_OUT */
768 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
769 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
770 shader->ctx_reg.gs.vgt_gs_max_vert_out);
771
772 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
773 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
774 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
775 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
776 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
777 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
778 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
779 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
780
781 /* R_028B90_VGT_GS_INSTANCE_CNT */
782 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
783 SI_TRACKED_VGT_GS_INSTANCE_CNT,
784 shader->ctx_reg.gs.vgt_gs_instance_cnt);
785
786 if (sctx->chip_class >= GFX9) {
787 /* R_028A44_VGT_GS_ONCHIP_CNTL */
788 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
789 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
790 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
791 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
792 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
793 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
794 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
795 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
796 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
797 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
798 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
799
800 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
801 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
802 SI_TRACKED_VGT_TF_PARAM,
803 shader->vgt_tf_param);
804 if (shader->vgt_vertex_reuse_block_cntl)
805 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
806 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
807 shader->vgt_vertex_reuse_block_cntl);
808 }
809
810 if (initial_cdw != sctx->gfx_cs->current.cdw)
811 sctx->context_roll = true;
812 }
813
814 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
815 {
816 struct si_shader_selector *sel = shader->selector;
817 const ubyte *num_components = sel->info.num_stream_output_components;
818 unsigned gs_num_invocations = sel->gs_num_invocations;
819 struct si_pm4_state *pm4;
820 uint64_t va;
821 unsigned max_stream = sel->max_gs_stream;
822 unsigned offset;
823
824 pm4 = si_get_shader_pm4_state(shader);
825 if (!pm4)
826 return;
827
828 pm4->atom.emit = si_emit_shader_gs;
829
830 offset = num_components[0] * sel->gs_max_out_vertices;
831 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
832
833 if (max_stream >= 1)
834 offset += num_components[1] * sel->gs_max_out_vertices;
835 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
836
837 if (max_stream >= 2)
838 offset += num_components[2] * sel->gs_max_out_vertices;
839 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
840
841 if (max_stream >= 3)
842 offset += num_components[3] * sel->gs_max_out_vertices;
843 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
844
845 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
846 assert(offset < (1 << 15));
847
848 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
849
850 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
851 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
852 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
853 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
854
855 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
856 S_028B90_ENABLE(gs_num_invocations > 0);
857
858 va = shader->bo->gpu_address;
859 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
860
861 if (sscreen->info.chip_class >= GFX9) {
862 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
863 unsigned es_type = shader->key.part.gs.es->type;
864 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
865
866 if (es_type == PIPE_SHADER_VERTEX)
867 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
868 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
869 else if (es_type == PIPE_SHADER_TESS_EVAL)
870 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
871 else
872 unreachable("invalid shader selector type");
873
874 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
875 * VGPR[0:4] are always loaded.
876 */
877 if (sel->info.uses_invocationid)
878 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
879 else if (sel->info.uses_primid)
880 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
881 else if (input_prim >= PIPE_PRIM_TRIANGLES)
882 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
883 else
884 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
885
886 unsigned num_user_sgprs;
887 if (es_type == PIPE_SHADER_VERTEX)
888 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
889 else
890 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
891
892 if (sscreen->info.chip_class >= GFX10) {
893 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
894 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
895 } else {
896 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
897 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
898 }
899
900 uint32_t rsrc1 =
901 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
902 S_00B228_DX10_CLAMP(1) |
903 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
904 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
905 S_00B228_FLOAT_MODE(shader->config.float_mode) |
906 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
907 uint32_t rsrc2 =
908 S_00B22C_USER_SGPR(num_user_sgprs) |
909 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
910 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
911 S_00B22C_LDS_SIZE(shader->config.lds_size) |
912 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
913
914 if (sscreen->info.chip_class >= GFX10) {
915 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
916 } else {
917 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
918 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
919 }
920
921 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
922 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
923
924 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
925 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
926 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
927 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
928 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
929 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
930 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
931 shader->key.part.gs.es->esgs_itemsize / 4;
932
933 if (es_type == PIPE_SHADER_TESS_EVAL)
934 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
935
936 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
937 NULL, pm4);
938 } else {
939 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
940 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
941
942 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
943 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
944 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
945 S_00B228_DX10_CLAMP(1) |
946 S_00B228_FLOAT_MODE(shader->config.float_mode));
947 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
948 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
949 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
950 }
951 }
952
953 /* Common tail code for NGG primitive shaders. */
954 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
955 struct si_shader *shader,
956 unsigned initial_cdw)
957 {
958 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
959 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
960 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
961 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
962 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
963 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
964 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
965 SI_TRACKED_VGT_PRIMITIVEID_EN,
966 shader->ctx_reg.ngg.vgt_primitiveid_en);
967 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
968 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
969 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
970 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
971 SI_TRACKED_VGT_GS_INSTANCE_CNT,
972 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
973 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
974 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
975 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
976 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
977 SI_TRACKED_VGT_REUSE_OFF,
978 shader->ctx_reg.ngg.vgt_reuse_off);
979 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
980 SI_TRACKED_SPI_VS_OUT_CONFIG,
981 shader->ctx_reg.ngg.spi_vs_out_config);
982 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
983 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
984 shader->ctx_reg.ngg.spi_shader_idx_format,
985 shader->ctx_reg.ngg.spi_shader_pos_format);
986 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
987 SI_TRACKED_PA_CL_VTE_CNTL,
988 shader->ctx_reg.ngg.pa_cl_vte_cntl);
989 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
990 SI_TRACKED_PA_CL_NGG_CNTL,
991 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
992
993 if (initial_cdw != sctx->gfx_cs->current.cdw)
994 sctx->context_roll = true;
995 }
996
997 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
998 {
999 struct si_shader *shader = sctx->queued.named.gs->shader;
1000 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1001
1002 if (!shader)
1003 return;
1004
1005 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1006 }
1007
1008 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1009 {
1010 struct si_shader *shader = sctx->queued.named.gs->shader;
1011 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1012
1013 if (!shader)
1014 return;
1015
1016 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1017 SI_TRACKED_VGT_TF_PARAM,
1018 shader->vgt_tf_param);
1019
1020 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1021 }
1022
1023 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1024 {
1025 struct si_shader *shader = sctx->queued.named.gs->shader;
1026 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1027
1028 if (!shader)
1029 return;
1030
1031 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1032 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1033 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1034
1035 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1036 }
1037
1038 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1039 {
1040 struct si_shader *shader = sctx->queued.named.gs->shader;
1041 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1042
1043 if (!shader)
1044 return;
1045
1046 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1047 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1048 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1049 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1050 SI_TRACKED_VGT_TF_PARAM,
1051 shader->vgt_tf_param);
1052
1053 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1054 }
1055
1056 static void si_set_ge_pc_alloc(struct si_screen *sscreen,
1057 struct si_pm4_state *pm4, bool culling)
1058 {
1059 si_pm4_set_reg(pm4, R_030980_GE_PC_ALLOC,
1060 S_030980_OVERSUB_EN(1) |
1061 S_030980_NUM_PC_LINES((culling ? 256 : 128) * sscreen->info.max_se - 1));
1062 }
1063
1064 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1065 {
1066 if (gs->type == PIPE_SHADER_GEOMETRY)
1067 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1068
1069 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1070 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1071 return PIPE_PRIM_POINTS;
1072 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1073 return PIPE_PRIM_LINES;
1074 return PIPE_PRIM_TRIANGLES;
1075 }
1076
1077 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1078 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1079 }
1080
1081 /**
1082 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1083 * in NGG mode.
1084 */
1085 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1086 {
1087 const struct si_shader_selector *gs_sel = shader->selector;
1088 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1089 enum pipe_shader_type gs_type = shader->selector->type;
1090 const struct si_shader_selector *es_sel =
1091 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1092 const struct tgsi_shader_info *es_info = &es_sel->info;
1093 enum pipe_shader_type es_type = es_sel->type;
1094 unsigned num_user_sgprs;
1095 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1096 uint64_t va;
1097 unsigned window_space =
1098 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1099 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1100 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1101 unsigned input_prim = si_get_input_prim(gs_sel);
1102 bool break_wave_at_eoi = false;
1103 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1104 if (!pm4)
1105 return;
1106
1107 if (es_type == PIPE_SHADER_TESS_EVAL) {
1108 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1109 : gfx10_emit_shader_ngg_tess_nogs;
1110 } else {
1111 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1112 : gfx10_emit_shader_ngg_notess_nogs;
1113 }
1114
1115 va = shader->bo->gpu_address;
1116 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1117
1118 if (es_type == PIPE_SHADER_VERTEX) {
1119 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1120 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1121
1122 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1123 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1124 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1125 } else {
1126 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1127 }
1128 } else {
1129 assert(es_type == PIPE_SHADER_TESS_EVAL);
1130 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1131 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1132
1133 if (es_enable_prim_id || gs_info->uses_primid)
1134 break_wave_at_eoi = true;
1135 }
1136
1137 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1138 * VGPR[0:4] are always loaded.
1139 *
1140 * Vertex shaders always need to load VGPR3, because they need to
1141 * pass edge flags for decomposed primitives (such as quads) to the PA
1142 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1143 */
1144 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1145 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1146 else if (gs_info->uses_primid)
1147 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1148 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1149 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1150 else
1151 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1152
1153 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1154 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1155 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1156 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1157 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1158 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1159 S_00B228_DX10_CLAMP(1) |
1160 S_00B228_MEM_ORDERED(1) |
1161 S_00B228_WGP_MODE(1) |
1162 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1163 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1164 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1165 S_00B22C_USER_SGPR(num_user_sgprs) |
1166 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1167 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1168 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1169 S_00B22C_LDS_SIZE(shader->config.lds_size));
1170 si_set_ge_pc_alloc(sscreen, pm4, false);
1171
1172 nparams = MAX2(shader->info.nr_param_exports, 1);
1173 shader->ctx_reg.ngg.spi_vs_out_config =
1174 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1175 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1176
1177 shader->ctx_reg.ngg.spi_shader_idx_format =
1178 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1179 shader->ctx_reg.ngg.spi_shader_pos_format =
1180 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1181 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1182 V_02870C_SPI_SHADER_4COMP :
1183 V_02870C_SPI_SHADER_NONE) |
1184 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1185 V_02870C_SPI_SHADER_4COMP :
1186 V_02870C_SPI_SHADER_NONE) |
1187 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1188 V_02870C_SPI_SHADER_4COMP :
1189 V_02870C_SPI_SHADER_NONE);
1190
1191 shader->ctx_reg.ngg.vgt_primitiveid_en =
1192 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1193 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1194
1195 if (gs_type == PIPE_SHADER_GEOMETRY) {
1196 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1197 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1198 } else {
1199 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1200 }
1201
1202 if (es_type == PIPE_SHADER_TESS_EVAL)
1203 si_set_tesseval_regs(sscreen, es_sel, pm4);
1204
1205 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1206 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1207 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1208 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1209 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1210 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1211 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1212 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1213 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1214 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1215 S_028B90_CNT(gs_num_invocations) |
1216 S_028B90_ENABLE(gs_num_invocations > 1) |
1217 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1218 shader->ngg.max_vert_out_per_gs_instance);
1219
1220 /* Always output hw-generated edge flags and pass them via the prim
1221 * export to prevent drawing lines on internal edges of decomposed
1222 * primitives (such as quads) with polygon mode = lines. Only VS needs
1223 * this.
1224 */
1225 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1226 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1227
1228 shader->ge_cntl =
1229 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1230 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1231 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1232
1233 /* Bug workaround for a possible hang with non-tessellation cases.
1234 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1235 *
1236 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1237 */
1238 if ((sscreen->info.family == CHIP_NAVI10 ||
1239 sscreen->info.family == CHIP_NAVI12 ||
1240 sscreen->info.family == CHIP_NAVI14) &&
1241 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1242 shader->ngg.hw_max_esverts != 256) {
1243 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1244
1245 if (shader->ngg.hw_max_esverts > 5) {
1246 shader->ge_cntl |=
1247 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1248 }
1249 }
1250
1251 if (window_space) {
1252 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1253 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1254 } else {
1255 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1256 S_028818_VTX_W0_FMT(1) |
1257 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1258 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1259 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1260 }
1261
1262 shader->ctx_reg.ngg.vgt_reuse_off =
1263 S_028AB4_REUSE_OFF(sscreen->info.family == CHIP_NAVI10 &&
1264 sscreen->info.chip_external_rev == 0x1 &&
1265 es_type == PIPE_SHADER_TESS_EVAL);
1266 }
1267
1268 static void si_emit_shader_vs(struct si_context *sctx)
1269 {
1270 struct si_shader *shader = sctx->queued.named.vs->shader;
1271 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1272
1273 if (!shader)
1274 return;
1275
1276 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1277 SI_TRACKED_VGT_GS_MODE,
1278 shader->ctx_reg.vs.vgt_gs_mode);
1279 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1280 SI_TRACKED_VGT_PRIMITIVEID_EN,
1281 shader->ctx_reg.vs.vgt_primitiveid_en);
1282
1283 if (sctx->chip_class <= GFX8) {
1284 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1285 SI_TRACKED_VGT_REUSE_OFF,
1286 shader->ctx_reg.vs.vgt_reuse_off);
1287 }
1288
1289 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1290 SI_TRACKED_SPI_VS_OUT_CONFIG,
1291 shader->ctx_reg.vs.spi_vs_out_config);
1292
1293 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1294 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1295 shader->ctx_reg.vs.spi_shader_pos_format);
1296
1297 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1298 SI_TRACKED_PA_CL_VTE_CNTL,
1299 shader->ctx_reg.vs.pa_cl_vte_cntl);
1300
1301 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1302 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1303 SI_TRACKED_VGT_TF_PARAM,
1304 shader->vgt_tf_param);
1305
1306 if (shader->vgt_vertex_reuse_block_cntl)
1307 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1308 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1309 shader->vgt_vertex_reuse_block_cntl);
1310
1311 if (initial_cdw != sctx->gfx_cs->current.cdw)
1312 sctx->context_roll = true;
1313 }
1314
1315 /**
1316 * Compute the state for \p shader, which will run as a vertex shader on the
1317 * hardware.
1318 *
1319 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1320 * is the copy shader.
1321 */
1322 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1323 struct si_shader_selector *gs)
1324 {
1325 const struct tgsi_shader_info *info = &shader->selector->info;
1326 struct si_pm4_state *pm4;
1327 unsigned num_user_sgprs, vgpr_comp_cnt;
1328 uint64_t va;
1329 unsigned nparams, oc_lds_en;
1330 unsigned window_space =
1331 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1332 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1333
1334 pm4 = si_get_shader_pm4_state(shader);
1335 if (!pm4)
1336 return;
1337
1338 pm4->atom.emit = si_emit_shader_vs;
1339
1340 /* We always write VGT_GS_MODE in the VS state, because every switch
1341 * between different shader pipelines involving a different GS or no
1342 * GS at all involves a switch of the VS (different GS use different
1343 * copy shaders). On the other hand, when the API switches from a GS to
1344 * no GS and then back to the same GS used originally, the GS state is
1345 * not sent again.
1346 */
1347 if (!gs) {
1348 unsigned mode = V_028A40_GS_OFF;
1349
1350 /* PrimID needs GS scenario A. */
1351 if (enable_prim_id)
1352 mode = V_028A40_GS_SCENARIO_A;
1353
1354 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1355 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1356 } else {
1357 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1358 sscreen->info.chip_class);
1359 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1360 }
1361
1362 if (sscreen->info.chip_class <= GFX8) {
1363 /* Reuse needs to be set off if we write oViewport. */
1364 shader->ctx_reg.vs.vgt_reuse_off =
1365 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1366 }
1367
1368 va = shader->bo->gpu_address;
1369 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1370
1371 if (gs) {
1372 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1373 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1374 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1375 if (sscreen->info.chip_class >= GFX10) {
1376 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
1377 } else {
1378 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1379 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1380 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1381 */
1382 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1383 }
1384
1385 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS]) {
1386 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1387 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
1388 } else {
1389 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1390 }
1391 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1392 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1393 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1394 } else
1395 unreachable("invalid shader selector type");
1396
1397 /* VS is required to export at least one param. */
1398 nparams = MAX2(shader->info.nr_param_exports, 1);
1399 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1400
1401 if (sscreen->info.chip_class >= GFX10) {
1402 shader->ctx_reg.vs.spi_vs_out_config |=
1403 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1404 }
1405
1406 shader->ctx_reg.vs.spi_shader_pos_format =
1407 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1408 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1409 V_02870C_SPI_SHADER_4COMP :
1410 V_02870C_SPI_SHADER_NONE) |
1411 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1412 V_02870C_SPI_SHADER_4COMP :
1413 V_02870C_SPI_SHADER_NONE) |
1414 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1415 V_02870C_SPI_SHADER_4COMP :
1416 V_02870C_SPI_SHADER_NONE);
1417
1418 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1419
1420 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1421 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1422 if (sscreen->info.chip_class >= GFX10)
1423 si_set_ge_pc_alloc(sscreen, pm4, false);
1424
1425 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1426 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1427 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1428 S_00B128_DX10_CLAMP(1) |
1429 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1430 S_00B128_FLOAT_MODE(shader->config.float_mode);
1431 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1432 S_00B12C_OC_LDS_EN(oc_lds_en) |
1433 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1434
1435 if (sscreen->info.chip_class <= GFX9) {
1436 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1437 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1438 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1439 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1440 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1441 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1442 }
1443
1444 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1445 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1446
1447 if (window_space)
1448 shader->ctx_reg.vs.pa_cl_vte_cntl =
1449 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1450 else
1451 shader->ctx_reg.vs.pa_cl_vte_cntl =
1452 S_028818_VTX_W0_FMT(1) |
1453 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1454 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1455 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1456
1457 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1458 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1459
1460 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1461 }
1462
1463 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1464 {
1465 struct tgsi_shader_info *info = &ps->selector->info;
1466 unsigned num_colors = !!(info->colors_read & 0x0f) +
1467 !!(info->colors_read & 0xf0);
1468 unsigned num_interp = ps->selector->info.num_inputs +
1469 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1470
1471 assert(num_interp <= 32);
1472 return MIN2(num_interp, 32);
1473 }
1474
1475 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1476 {
1477 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1478 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1479
1480 /* If the i-th target format is set, all previous target formats must
1481 * be non-zero to avoid hangs.
1482 */
1483 for (i = 0; i < num_targets; i++)
1484 if (!(value & (0xf << (i * 4))))
1485 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1486
1487 return value;
1488 }
1489
1490 static void si_emit_shader_ps(struct si_context *sctx)
1491 {
1492 struct si_shader *shader = sctx->queued.named.ps->shader;
1493 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1494
1495 if (!shader)
1496 return;
1497
1498 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1499 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1500 SI_TRACKED_SPI_PS_INPUT_ENA,
1501 shader->ctx_reg.ps.spi_ps_input_ena,
1502 shader->ctx_reg.ps.spi_ps_input_addr);
1503
1504 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1505 SI_TRACKED_SPI_BARYC_CNTL,
1506 shader->ctx_reg.ps.spi_baryc_cntl);
1507 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1508 SI_TRACKED_SPI_PS_IN_CONTROL,
1509 shader->ctx_reg.ps.spi_ps_in_control);
1510
1511 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1512 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1513 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1514 shader->ctx_reg.ps.spi_shader_z_format,
1515 shader->ctx_reg.ps.spi_shader_col_format);
1516
1517 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1518 SI_TRACKED_CB_SHADER_MASK,
1519 shader->ctx_reg.ps.cb_shader_mask);
1520
1521 if (initial_cdw != sctx->gfx_cs->current.cdw)
1522 sctx->context_roll = true;
1523 }
1524
1525 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1526 {
1527 struct tgsi_shader_info *info = &shader->selector->info;
1528 struct si_pm4_state *pm4;
1529 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1530 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1531 uint64_t va;
1532 unsigned input_ena = shader->config.spi_ps_input_ena;
1533
1534 /* we need to enable at least one of them, otherwise we hang the GPU */
1535 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1536 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1537 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1538 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1539 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1540 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1541 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1542 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1543 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1544 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1545 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1546 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1547 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1548 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1549
1550 /* Validate interpolation optimization flags (read as implications). */
1551 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1552 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1553 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1554 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1555 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1556 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1557 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1558 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1559 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1560 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1561 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1562 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1563 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1564 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1565 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1566 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1567 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1568 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1569
1570 /* Validate cases when the optimizations are off (read as implications). */
1571 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1572 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1573 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1574 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1575 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1576 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1577
1578 pm4 = si_get_shader_pm4_state(shader);
1579 if (!pm4)
1580 return;
1581
1582 pm4->atom.emit = si_emit_shader_ps;
1583
1584 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1585 * Possible vaules:
1586 * 0 -> Position = pixel center
1587 * 1 -> Position = pixel centroid
1588 * 2 -> Position = at sample position
1589 *
1590 * From GLSL 4.5 specification, section 7.1:
1591 * "The variable gl_FragCoord is available as an input variable from
1592 * within fragment shaders and it holds the window relative coordinates
1593 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1594 * value can be for any location within the pixel, or one of the
1595 * fragment samples. The use of centroid does not further restrict
1596 * this value to be inside the current primitive."
1597 *
1598 * Meaning that centroid has no effect and we can return anything within
1599 * the pixel. Thus, return the value at sample position, because that's
1600 * the most accurate one shaders can get.
1601 */
1602 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1603
1604 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1605 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1606 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1607
1608 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1609 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1610
1611 /* Ensure that some export memory is always allocated, for two reasons:
1612 *
1613 * 1) Correctness: The hardware ignores the EXEC mask if no export
1614 * memory is allocated, so KILL and alpha test do not work correctly
1615 * without this.
1616 * 2) Performance: Every shader needs at least a NULL export, even when
1617 * it writes no color/depth output. The NULL export instruction
1618 * stalls without this setting.
1619 *
1620 * Don't add this to CB_SHADER_MASK.
1621 *
1622 * GFX10 supports pixel shaders without exports by setting both
1623 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1624 * instructions if any are present.
1625 */
1626 if ((sscreen->info.chip_class <= GFX9 ||
1627 info->uses_kill ||
1628 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1629 !spi_shader_col_format &&
1630 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1631 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1632
1633 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1634 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1635
1636 /* Set interpolation controls. */
1637 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1638 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1639
1640 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1641 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1642 shader->ctx_reg.ps.spi_shader_z_format =
1643 ac_get_spi_shader_z_format(info->writes_z,
1644 info->writes_stencil,
1645 info->writes_samplemask);
1646 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1647 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1648
1649 va = shader->bo->gpu_address;
1650 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1651 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1652 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1653
1654 uint32_t rsrc1 =
1655 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1656 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1657 S_00B028_DX10_CLAMP(1) |
1658 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1659 S_00B028_FLOAT_MODE(shader->config.float_mode);
1660
1661 if (sscreen->info.chip_class < GFX10) {
1662 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1663 }
1664
1665 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1666 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1667 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1668 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1669 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1670 }
1671
1672 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1673 struct si_shader *shader)
1674 {
1675 switch (shader->selector->type) {
1676 case PIPE_SHADER_VERTEX:
1677 if (shader->key.as_ls)
1678 si_shader_ls(sscreen, shader);
1679 else if (shader->key.as_es)
1680 si_shader_es(sscreen, shader);
1681 else if (shader->key.as_ngg)
1682 gfx10_shader_ngg(sscreen, shader);
1683 else
1684 si_shader_vs(sscreen, shader, NULL);
1685 break;
1686 case PIPE_SHADER_TESS_CTRL:
1687 si_shader_hs(sscreen, shader);
1688 break;
1689 case PIPE_SHADER_TESS_EVAL:
1690 if (shader->key.as_es)
1691 si_shader_es(sscreen, shader);
1692 else if (shader->key.as_ngg)
1693 gfx10_shader_ngg(sscreen, shader);
1694 else
1695 si_shader_vs(sscreen, shader, NULL);
1696 break;
1697 case PIPE_SHADER_GEOMETRY:
1698 if (shader->key.as_ngg)
1699 gfx10_shader_ngg(sscreen, shader);
1700 else
1701 si_shader_gs(sscreen, shader);
1702 break;
1703 case PIPE_SHADER_FRAGMENT:
1704 si_shader_ps(sscreen, shader);
1705 break;
1706 default:
1707 assert(0);
1708 }
1709 }
1710
1711 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1712 {
1713 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1714 return sctx->queued.named.dsa->alpha_func;
1715 }
1716
1717 void si_shader_selector_key_vs(struct si_context *sctx,
1718 struct si_shader_selector *vs,
1719 struct si_shader_key *key,
1720 struct si_vs_prolog_bits *prolog_key)
1721 {
1722 if (!sctx->vertex_elements ||
1723 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS])
1724 return;
1725
1726 struct si_vertex_elements *elts = sctx->vertex_elements;
1727
1728 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1729 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1730 prolog_key->unpack_instance_id_from_vertex_id =
1731 sctx->prim_discard_cs_instancing;
1732
1733 /* Prefer a monolithic shader to allow scheduling divisions around
1734 * VBO loads. */
1735 if (prolog_key->instance_divisor_is_fetched)
1736 key->opt.prefer_mono = 1;
1737
1738 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1739 unsigned count_mask = (1 << count) - 1;
1740 unsigned fix = elts->fix_fetch_always & count_mask;
1741 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1742
1743 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1744 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1745 while (mask) {
1746 unsigned i = u_bit_scan(&mask);
1747 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1748 unsigned vbidx = elts->vertex_buffer_index[i];
1749 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1750 unsigned align_mask = (1 << log_hw_load_size) - 1;
1751 if (vb->buffer_offset & align_mask ||
1752 vb->stride & align_mask) {
1753 fix |= 1 << i;
1754 opencode |= 1 << i;
1755 }
1756 }
1757 }
1758
1759 while (fix) {
1760 unsigned i = u_bit_scan(&fix);
1761 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1762 }
1763 key->mono.vs_fetch_opencode = opencode;
1764 }
1765
1766 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1767 struct si_shader_selector *vs,
1768 struct si_shader_key *key)
1769 {
1770 struct si_shader_selector *ps = sctx->ps_shader.cso;
1771
1772 key->opt.clip_disable =
1773 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1774 (vs->info.clipdist_writemask ||
1775 vs->info.writes_clipvertex) &&
1776 !vs->info.culldist_writemask;
1777
1778 /* Find out if PS is disabled. */
1779 bool ps_disabled = true;
1780 if (ps) {
1781 bool ps_modifies_zs = ps->info.uses_kill ||
1782 ps->info.writes_z ||
1783 ps->info.writes_stencil ||
1784 ps->info.writes_samplemask ||
1785 sctx->queued.named.blend->alpha_to_coverage ||
1786 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1787 unsigned ps_colormask = si_get_total_colormask(sctx);
1788
1789 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1790 (!ps_colormask &&
1791 !ps_modifies_zs &&
1792 !ps->info.writes_memory);
1793 }
1794
1795 /* Find out which VS outputs aren't used by the PS. */
1796 uint64_t outputs_written = vs->outputs_written_before_ps;
1797 uint64_t inputs_read = 0;
1798
1799 /* Ignore outputs that are not passed from VS to PS. */
1800 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1801 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1802 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1803
1804 if (!ps_disabled) {
1805 inputs_read = ps->inputs_read;
1806 }
1807
1808 uint64_t linked = outputs_written & inputs_read;
1809
1810 key->opt.kill_outputs = ~linked & outputs_written;
1811 }
1812
1813 /* Compute the key for the hw shader variant */
1814 static inline void si_shader_selector_key(struct pipe_context *ctx,
1815 struct si_shader_selector *sel,
1816 union si_vgt_stages_key stages_key,
1817 struct si_shader_key *key)
1818 {
1819 struct si_context *sctx = (struct si_context *)ctx;
1820
1821 memset(key, 0, sizeof(*key));
1822
1823 switch (sel->type) {
1824 case PIPE_SHADER_VERTEX:
1825 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1826
1827 if (sctx->tes_shader.cso)
1828 key->as_ls = 1;
1829 else if (sctx->gs_shader.cso)
1830 key->as_es = 1;
1831 else {
1832 key->as_ngg = stages_key.u.ngg;
1833 si_shader_selector_key_hw_vs(sctx, sel, key);
1834
1835 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1836 key->mono.u.vs_export_prim_id = 1;
1837 }
1838 break;
1839 case PIPE_SHADER_TESS_CTRL:
1840 if (sctx->chip_class >= GFX9) {
1841 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1842 key, &key->part.tcs.ls_prolog);
1843 key->part.tcs.ls = sctx->vs_shader.cso;
1844
1845 /* When the LS VGPR fix is needed, monolithic shaders
1846 * can:
1847 * - avoid initializing EXEC in both the LS prolog
1848 * and the LS main part when !vs_needs_prolog
1849 * - remove the fixup for unused input VGPRs
1850 */
1851 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1852
1853 /* The LS output / HS input layout can be communicated
1854 * directly instead of via user SGPRs for merged LS-HS.
1855 * The LS VGPR fix prefers this too.
1856 */
1857 key->opt.prefer_mono = 1;
1858 }
1859
1860 key->part.tcs.epilog.prim_mode =
1861 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1862 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1863 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1864 key->part.tcs.epilog.tes_reads_tess_factors =
1865 sctx->tes_shader.cso->info.reads_tess_factors;
1866
1867 if (sel == sctx->fixed_func_tcs_shader.cso)
1868 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1869 break;
1870 case PIPE_SHADER_TESS_EVAL:
1871 key->as_ngg = stages_key.u.ngg;
1872
1873 if (sctx->gs_shader.cso)
1874 key->as_es = 1;
1875 else {
1876 si_shader_selector_key_hw_vs(sctx, sel, key);
1877
1878 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1879 key->mono.u.vs_export_prim_id = 1;
1880 }
1881 break;
1882 case PIPE_SHADER_GEOMETRY:
1883 if (sctx->chip_class >= GFX9) {
1884 if (sctx->tes_shader.cso) {
1885 key->part.gs.es = sctx->tes_shader.cso;
1886 } else {
1887 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1888 key, &key->part.gs.vs_prolog);
1889 key->part.gs.es = sctx->vs_shader.cso;
1890 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1891 }
1892
1893 key->as_ngg = stages_key.u.ngg;
1894
1895 /* Merged ES-GS can have unbalanced wave usage.
1896 *
1897 * ES threads are per-vertex, while GS threads are
1898 * per-primitive. So without any amplification, there
1899 * are fewer GS threads than ES threads, which can result
1900 * in empty (no-op) GS waves. With too much amplification,
1901 * there are more GS threads than ES threads, which
1902 * can result in empty (no-op) ES waves.
1903 *
1904 * Non-monolithic shaders are implemented by setting EXEC
1905 * at the beginning of shader parts, and don't jump to
1906 * the end if EXEC is 0.
1907 *
1908 * Monolithic shaders use conditional blocks, so they can
1909 * jump and skip empty waves of ES or GS. So set this to
1910 * always use optimized variants, which are monolithic.
1911 */
1912 key->opt.prefer_mono = 1;
1913 }
1914 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1915 break;
1916 case PIPE_SHADER_FRAGMENT: {
1917 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1918 struct si_state_blend *blend = sctx->queued.named.blend;
1919
1920 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1921 sel->info.colors_written == 0x1)
1922 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1923
1924 /* Select the shader color format based on whether
1925 * blending or alpha are needed.
1926 */
1927 key->part.ps.epilog.spi_shader_col_format =
1928 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1929 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1930 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1931 sctx->framebuffer.spi_shader_col_format_blend) |
1932 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1933 sctx->framebuffer.spi_shader_col_format_alpha) |
1934 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1935 sctx->framebuffer.spi_shader_col_format);
1936 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1937
1938 /* The output for dual source blending should have
1939 * the same format as the first output.
1940 */
1941 if (blend->dual_src_blend) {
1942 key->part.ps.epilog.spi_shader_col_format |=
1943 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1944 }
1945
1946 /* If alpha-to-coverage is enabled, we have to export alpha
1947 * even if there is no color buffer.
1948 */
1949 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1950 blend->alpha_to_coverage)
1951 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1952
1953 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1954 * to the range supported by the type if a channel has less
1955 * than 16 bits and the export format is 16_ABGR.
1956 */
1957 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1958 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1959 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1960 }
1961
1962 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1963 if (!key->part.ps.epilog.last_cbuf) {
1964 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1965 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1966 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1967 }
1968
1969 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1970 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1971
1972 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1973 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1974
1975 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
1976 rs->multisample_enable;
1977
1978 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1979 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1980 (is_line && rs->line_smooth)) &&
1981 sctx->framebuffer.nr_samples <= 1;
1982 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1983
1984 if (sctx->ps_iter_samples > 1 &&
1985 sel->info.reads_samplemask) {
1986 key->part.ps.prolog.samplemask_log_ps_iter =
1987 util_logbase2(sctx->ps_iter_samples);
1988 }
1989
1990 if (rs->force_persample_interp &&
1991 rs->multisample_enable &&
1992 sctx->framebuffer.nr_samples > 1 &&
1993 sctx->ps_iter_samples > 1) {
1994 key->part.ps.prolog.force_persp_sample_interp =
1995 sel->info.uses_persp_center ||
1996 sel->info.uses_persp_centroid;
1997
1998 key->part.ps.prolog.force_linear_sample_interp =
1999 sel->info.uses_linear_center ||
2000 sel->info.uses_linear_centroid;
2001 } else if (rs->multisample_enable &&
2002 sctx->framebuffer.nr_samples > 1) {
2003 key->part.ps.prolog.bc_optimize_for_persp =
2004 sel->info.uses_persp_center &&
2005 sel->info.uses_persp_centroid;
2006 key->part.ps.prolog.bc_optimize_for_linear =
2007 sel->info.uses_linear_center &&
2008 sel->info.uses_linear_centroid;
2009 } else {
2010 /* Make sure SPI doesn't compute more than 1 pair
2011 * of (i,j), which is the optimization here. */
2012 key->part.ps.prolog.force_persp_center_interp =
2013 sel->info.uses_persp_center +
2014 sel->info.uses_persp_centroid +
2015 sel->info.uses_persp_sample > 1;
2016
2017 key->part.ps.prolog.force_linear_center_interp =
2018 sel->info.uses_linear_center +
2019 sel->info.uses_linear_centroid +
2020 sel->info.uses_linear_sample > 1;
2021
2022 if (sel->info.uses_persp_opcode_interp_sample ||
2023 sel->info.uses_linear_opcode_interp_sample)
2024 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2025 }
2026
2027 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2028
2029 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2030 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2031 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2032 struct pipe_resource *tex = cb0->texture;
2033
2034 /* 1D textures are allocated and used as 2D on GFX9. */
2035 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2036 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2037 (tex->target == PIPE_TEXTURE_1D ||
2038 tex->target == PIPE_TEXTURE_1D_ARRAY);
2039 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2040 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2041 tex->target == PIPE_TEXTURE_CUBE ||
2042 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2043 tex->target == PIPE_TEXTURE_3D;
2044 }
2045 break;
2046 }
2047 default:
2048 assert(0);
2049 }
2050
2051 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2052 memset(&key->opt, 0, sizeof(key->opt));
2053 }
2054
2055 static void si_build_shader_variant(struct si_shader *shader,
2056 int thread_index,
2057 bool low_priority)
2058 {
2059 struct si_shader_selector *sel = shader->selector;
2060 struct si_screen *sscreen = sel->screen;
2061 struct ac_llvm_compiler *compiler;
2062 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2063
2064 if (thread_index >= 0) {
2065 if (low_priority) {
2066 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2067 compiler = &sscreen->compiler_lowp[thread_index];
2068 } else {
2069 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2070 compiler = &sscreen->compiler[thread_index];
2071 }
2072 if (!debug->async)
2073 debug = NULL;
2074 } else {
2075 assert(!low_priority);
2076 compiler = shader->compiler_ctx_state.compiler;
2077 }
2078
2079 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2080 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2081 sel->type);
2082 shader->compilation_failed = true;
2083 return;
2084 }
2085
2086 if (shader->compiler_ctx_state.is_debug_context) {
2087 FILE *f = open_memstream(&shader->shader_log,
2088 &shader->shader_log_size);
2089 if (f) {
2090 si_shader_dump(sscreen, shader, NULL, f, false);
2091 fclose(f);
2092 }
2093 }
2094
2095 si_shader_init_pm4_state(sscreen, shader);
2096 }
2097
2098 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2099 {
2100 struct si_shader *shader = (struct si_shader *)job;
2101
2102 assert(thread_index >= 0);
2103
2104 si_build_shader_variant(shader, thread_index, true);
2105 }
2106
2107 static const struct si_shader_key zeroed;
2108
2109 static bool si_check_missing_main_part(struct si_screen *sscreen,
2110 struct si_shader_selector *sel,
2111 struct si_compiler_ctx_state *compiler_state,
2112 struct si_shader_key *key)
2113 {
2114 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2115
2116 if (!*mainp) {
2117 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2118
2119 if (!main_part)
2120 return false;
2121
2122 /* We can leave the fence as permanently signaled because the
2123 * main part becomes visible globally only after it has been
2124 * compiled. */
2125 util_queue_fence_init(&main_part->ready);
2126
2127 main_part->selector = sel;
2128 main_part->key.as_es = key->as_es;
2129 main_part->key.as_ls = key->as_ls;
2130 main_part->key.as_ngg = key->as_ngg;
2131 main_part->is_monolithic = false;
2132
2133 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2134 main_part, &compiler_state->debug) != 0) {
2135 FREE(main_part);
2136 return false;
2137 }
2138 *mainp = main_part;
2139 }
2140 return true;
2141 }
2142
2143 /**
2144 * Select a shader variant according to the shader key.
2145 *
2146 * \param optimized_or_none If the key describes an optimized shader variant and
2147 * the compilation isn't finished, don't select any
2148 * shader and return an error.
2149 */
2150 int si_shader_select_with_key(struct si_screen *sscreen,
2151 struct si_shader_ctx_state *state,
2152 struct si_compiler_ctx_state *compiler_state,
2153 struct si_shader_key *key,
2154 int thread_index,
2155 bool optimized_or_none)
2156 {
2157 struct si_shader_selector *sel = state->cso;
2158 struct si_shader_selector *previous_stage_sel = NULL;
2159 struct si_shader *current = state->current;
2160 struct si_shader *iter, *shader = NULL;
2161
2162 again:
2163 /* Check if we don't need to change anything.
2164 * This path is also used for most shaders that don't need multiple
2165 * variants, it will cost just a computation of the key and this
2166 * test. */
2167 if (likely(current &&
2168 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2169 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2170 if (current->is_optimized) {
2171 if (optimized_or_none)
2172 return -1;
2173
2174 memset(&key->opt, 0, sizeof(key->opt));
2175 goto current_not_ready;
2176 }
2177
2178 util_queue_fence_wait(&current->ready);
2179 }
2180
2181 return current->compilation_failed ? -1 : 0;
2182 }
2183 current_not_ready:
2184
2185 /* This must be done before the mutex is locked, because async GS
2186 * compilation calls this function too, and therefore must enter
2187 * the mutex first.
2188 *
2189 * Only wait if we are in a draw call. Don't wait if we are
2190 * in a compiler thread.
2191 */
2192 if (thread_index < 0)
2193 util_queue_fence_wait(&sel->ready);
2194
2195 mtx_lock(&sel->mutex);
2196
2197 /* Find the shader variant. */
2198 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2199 /* Don't check the "current" shader. We checked it above. */
2200 if (current != iter &&
2201 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2202 mtx_unlock(&sel->mutex);
2203
2204 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2205 /* If it's an optimized shader and its compilation has
2206 * been started but isn't done, use the unoptimized
2207 * shader so as not to cause a stall due to compilation.
2208 */
2209 if (iter->is_optimized) {
2210 if (optimized_or_none)
2211 return -1;
2212 memset(&key->opt, 0, sizeof(key->opt));
2213 goto again;
2214 }
2215
2216 util_queue_fence_wait(&iter->ready);
2217 }
2218
2219 if (iter->compilation_failed) {
2220 return -1; /* skip the draw call */
2221 }
2222
2223 state->current = iter;
2224 return 0;
2225 }
2226 }
2227
2228 /* Build a new shader. */
2229 shader = CALLOC_STRUCT(si_shader);
2230 if (!shader) {
2231 mtx_unlock(&sel->mutex);
2232 return -ENOMEM;
2233 }
2234
2235 util_queue_fence_init(&shader->ready);
2236
2237 shader->selector = sel;
2238 shader->key = *key;
2239 shader->compiler_ctx_state = *compiler_state;
2240
2241 /* If this is a merged shader, get the first shader's selector. */
2242 if (sscreen->info.chip_class >= GFX9) {
2243 if (sel->type == PIPE_SHADER_TESS_CTRL)
2244 previous_stage_sel = key->part.tcs.ls;
2245 else if (sel->type == PIPE_SHADER_GEOMETRY)
2246 previous_stage_sel = key->part.gs.es;
2247
2248 /* We need to wait for the previous shader. */
2249 if (previous_stage_sel && thread_index < 0)
2250 util_queue_fence_wait(&previous_stage_sel->ready);
2251 }
2252
2253 bool is_pure_monolithic =
2254 sscreen->use_monolithic_shaders ||
2255 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2256
2257 /* Compile the main shader part if it doesn't exist. This can happen
2258 * if the initial guess was wrong.
2259 *
2260 * The prim discard CS doesn't need the main shader part.
2261 */
2262 if (!is_pure_monolithic &&
2263 !key->opt.vs_as_prim_discard_cs) {
2264 bool ok = true;
2265
2266 /* Make sure the main shader part is present. This is needed
2267 * for shaders that can be compiled as VS, LS, or ES, and only
2268 * one of them is compiled at creation.
2269 *
2270 * It is also needed for GS, which can be compiled as non-NGG
2271 * and NGG.
2272 *
2273 * For merged shaders, check that the starting shader's main
2274 * part is present.
2275 */
2276 if (previous_stage_sel) {
2277 struct si_shader_key shader1_key = zeroed;
2278
2279 if (sel->type == PIPE_SHADER_TESS_CTRL)
2280 shader1_key.as_ls = 1;
2281 else if (sel->type == PIPE_SHADER_GEOMETRY)
2282 shader1_key.as_es = 1;
2283 else
2284 assert(0);
2285
2286 if (sel->type == PIPE_SHADER_GEOMETRY &&
2287 previous_stage_sel->type == PIPE_SHADER_TESS_EVAL)
2288 shader1_key.as_ngg = key->as_ngg;
2289
2290 mtx_lock(&previous_stage_sel->mutex);
2291 ok = si_check_missing_main_part(sscreen,
2292 previous_stage_sel,
2293 compiler_state, &shader1_key);
2294 mtx_unlock(&previous_stage_sel->mutex);
2295 }
2296
2297 if (ok) {
2298 ok = si_check_missing_main_part(sscreen, sel,
2299 compiler_state, key);
2300 }
2301
2302 if (!ok) {
2303 FREE(shader);
2304 mtx_unlock(&sel->mutex);
2305 return -ENOMEM; /* skip the draw call */
2306 }
2307 }
2308
2309 /* Keep the reference to the 1st shader of merged shaders, so that
2310 * Gallium can't destroy it before we destroy the 2nd shader.
2311 *
2312 * Set sctx = NULL, because it's unused if we're not releasing
2313 * the shader, and we don't have any sctx here.
2314 */
2315 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2316 previous_stage_sel);
2317
2318 /* Monolithic-only shaders don't make a distinction between optimized
2319 * and unoptimized. */
2320 shader->is_monolithic =
2321 is_pure_monolithic ||
2322 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2323
2324 /* The prim discard CS is always optimized. */
2325 shader->is_optimized =
2326 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2327 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2328
2329 /* If it's an optimized shader, compile it asynchronously. */
2330 if (shader->is_optimized && thread_index < 0) {
2331 /* Compile it asynchronously. */
2332 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2333 shader, &shader->ready,
2334 si_build_shader_variant_low_priority, NULL);
2335
2336 /* Add only after the ready fence was reset, to guard against a
2337 * race with si_bind_XX_shader. */
2338 if (!sel->last_variant) {
2339 sel->first_variant = shader;
2340 sel->last_variant = shader;
2341 } else {
2342 sel->last_variant->next_variant = shader;
2343 sel->last_variant = shader;
2344 }
2345
2346 /* Use the default (unoptimized) shader for now. */
2347 memset(&key->opt, 0, sizeof(key->opt));
2348 mtx_unlock(&sel->mutex);
2349
2350 if (sscreen->options.sync_compile)
2351 util_queue_fence_wait(&shader->ready);
2352
2353 if (optimized_or_none)
2354 return -1;
2355 goto again;
2356 }
2357
2358 /* Reset the fence before adding to the variant list. */
2359 util_queue_fence_reset(&shader->ready);
2360
2361 if (!sel->last_variant) {
2362 sel->first_variant = shader;
2363 sel->last_variant = shader;
2364 } else {
2365 sel->last_variant->next_variant = shader;
2366 sel->last_variant = shader;
2367 }
2368
2369 mtx_unlock(&sel->mutex);
2370
2371 assert(!shader->is_optimized);
2372 si_build_shader_variant(shader, thread_index, false);
2373
2374 util_queue_fence_signal(&shader->ready);
2375
2376 if (!shader->compilation_failed)
2377 state->current = shader;
2378
2379 return shader->compilation_failed ? -1 : 0;
2380 }
2381
2382 static int si_shader_select(struct pipe_context *ctx,
2383 struct si_shader_ctx_state *state,
2384 union si_vgt_stages_key stages_key,
2385 struct si_compiler_ctx_state *compiler_state)
2386 {
2387 struct si_context *sctx = (struct si_context *)ctx;
2388 struct si_shader_key key;
2389
2390 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2391 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2392 &key, -1, false);
2393 }
2394
2395 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2396 bool streamout,
2397 struct si_shader_key *key)
2398 {
2399 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2400
2401 switch (info->processor) {
2402 case PIPE_SHADER_VERTEX:
2403 switch (next_shader) {
2404 case PIPE_SHADER_GEOMETRY:
2405 key->as_es = 1;
2406 break;
2407 case PIPE_SHADER_TESS_CTRL:
2408 case PIPE_SHADER_TESS_EVAL:
2409 key->as_ls = 1;
2410 break;
2411 default:
2412 /* If POSITION isn't written, it can only be a HW VS
2413 * if streamout is used. If streamout isn't used,
2414 * assume that it's a HW LS. (the next shader is TCS)
2415 * This heuristic is needed for separate shader objects.
2416 */
2417 if (!info->writes_position && !streamout)
2418 key->as_ls = 1;
2419 }
2420 break;
2421
2422 case PIPE_SHADER_TESS_EVAL:
2423 if (next_shader == PIPE_SHADER_GEOMETRY ||
2424 !info->writes_position)
2425 key->as_es = 1;
2426 break;
2427 }
2428 }
2429
2430 /**
2431 * Compile the main shader part or the monolithic shader as part of
2432 * si_shader_selector initialization. Since it can be done asynchronously,
2433 * there is no way to report compile failures to applications.
2434 */
2435 static void si_init_shader_selector_async(void *job, int thread_index)
2436 {
2437 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2438 struct si_screen *sscreen = sel->screen;
2439 struct ac_llvm_compiler *compiler;
2440 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2441
2442 assert(!debug->debug_message || debug->async);
2443 assert(thread_index >= 0);
2444 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2445 compiler = &sscreen->compiler[thread_index];
2446
2447 if (sel->nir) {
2448 /* TODO: GS always sets wave size = default. Legacy GS will have
2449 * incorrect subgroup_size and ballot_bit_size. */
2450 si_lower_nir(sel, si_get_wave_size(sscreen, sel->type, true, false));
2451 }
2452
2453 /* Compile the main shader part for use with a prolog and/or epilog.
2454 * If this fails, the driver will try to compile a monolithic shader
2455 * on demand.
2456 */
2457 if (!sscreen->use_monolithic_shaders) {
2458 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2459 void *ir_binary = NULL;
2460
2461 if (!shader) {
2462 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2463 return;
2464 }
2465
2466 /* We can leave the fence signaled because use of the default
2467 * main part is guarded by the selector's ready fence. */
2468 util_queue_fence_init(&shader->ready);
2469
2470 shader->selector = sel;
2471 shader->is_monolithic = false;
2472 si_parse_next_shader_property(&sel->info,
2473 sel->so.num_outputs != 0,
2474 &shader->key);
2475 if (sscreen->info.chip_class >= GFX10 &&
2476 ((sel->type == PIPE_SHADER_VERTEX &&
2477 !shader->key.as_ls && !shader->key.as_es) ||
2478 sel->type == PIPE_SHADER_TESS_EVAL ||
2479 sel->type == PIPE_SHADER_GEOMETRY))
2480 shader->key.as_ngg = 1;
2481
2482 if (sel->tokens || sel->nir)
2483 ir_binary = si_get_ir_binary(sel);
2484
2485 /* Try to load the shader from the shader cache. */
2486 mtx_lock(&sscreen->shader_cache_mutex);
2487
2488 if (ir_binary &&
2489 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2490 mtx_unlock(&sscreen->shader_cache_mutex);
2491 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2492 } else {
2493 mtx_unlock(&sscreen->shader_cache_mutex);
2494
2495 /* Compile the shader if it hasn't been loaded from the cache. */
2496 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2497 debug) != 0) {
2498 FREE(shader);
2499 FREE(ir_binary);
2500 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2501 return;
2502 }
2503
2504 if (ir_binary) {
2505 mtx_lock(&sscreen->shader_cache_mutex);
2506 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2507 FREE(ir_binary);
2508 mtx_unlock(&sscreen->shader_cache_mutex);
2509 }
2510 }
2511
2512 *si_get_main_shader_part(sel, &shader->key) = shader;
2513
2514 /* Unset "outputs_written" flags for outputs converted to
2515 * DEFAULT_VAL, so that later inter-shader optimizations don't
2516 * try to eliminate outputs that don't exist in the final
2517 * shader.
2518 *
2519 * This is only done if non-monolithic shaders are enabled.
2520 */
2521 if ((sel->type == PIPE_SHADER_VERTEX ||
2522 sel->type == PIPE_SHADER_TESS_EVAL) &&
2523 !shader->key.as_ls &&
2524 !shader->key.as_es) {
2525 unsigned i;
2526
2527 for (i = 0; i < sel->info.num_outputs; i++) {
2528 unsigned offset = shader->info.vs_output_param_offset[i];
2529
2530 if (offset <= AC_EXP_PARAM_OFFSET_31)
2531 continue;
2532
2533 unsigned name = sel->info.output_semantic_name[i];
2534 unsigned index = sel->info.output_semantic_index[i];
2535 unsigned id;
2536
2537 switch (name) {
2538 case TGSI_SEMANTIC_GENERIC:
2539 /* don't process indices the function can't handle */
2540 if (index >= SI_MAX_IO_GENERIC)
2541 break;
2542 /* fall through */
2543 default:
2544 id = si_shader_io_get_unique_index(name, index, true);
2545 sel->outputs_written_before_ps &= ~(1ull << id);
2546 break;
2547 case TGSI_SEMANTIC_POSITION: /* ignore these */
2548 case TGSI_SEMANTIC_PSIZE:
2549 case TGSI_SEMANTIC_CLIPVERTEX:
2550 case TGSI_SEMANTIC_EDGEFLAG:
2551 break;
2552 }
2553 }
2554 }
2555 }
2556
2557 /* The GS copy shader is always pre-compiled. */
2558 if (sel->type == PIPE_SHADER_GEOMETRY &&
2559 (sscreen->info.chip_class <= GFX9 || sel->tess_turns_off_ngg)) {
2560 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2561 if (!sel->gs_copy_shader) {
2562 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2563 return;
2564 }
2565
2566 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2567 }
2568 }
2569
2570 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2571 struct util_queue_fence *ready_fence,
2572 struct si_compiler_ctx_state *compiler_ctx_state,
2573 void *job, util_queue_execute_func execute)
2574 {
2575 util_queue_fence_init(ready_fence);
2576
2577 struct util_async_debug_callback async_debug;
2578 bool debug =
2579 (sctx->debug.debug_message && !sctx->debug.async) ||
2580 sctx->is_debug ||
2581 si_can_dump_shader(sctx->screen, processor);
2582
2583 if (debug) {
2584 u_async_debug_init(&async_debug);
2585 compiler_ctx_state->debug = async_debug.base;
2586 }
2587
2588 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2589 ready_fence, execute, NULL);
2590
2591 if (debug) {
2592 util_queue_fence_wait(ready_fence);
2593 u_async_debug_drain(&async_debug, &sctx->debug);
2594 u_async_debug_cleanup(&async_debug);
2595 }
2596
2597 if (sctx->screen->options.sync_compile)
2598 util_queue_fence_wait(ready_fence);
2599 }
2600
2601 /* Return descriptor slot usage masks from the given shader info. */
2602 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2603 uint32_t *const_and_shader_buffers,
2604 uint64_t *samplers_and_images)
2605 {
2606 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2607
2608 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2609 num_constbufs = util_last_bit(info->const_buffers_declared);
2610 /* two 8-byte images share one 16-byte slot */
2611 num_images = align(util_last_bit(info->images_declared), 2);
2612 num_samplers = util_last_bit(info->samplers_declared);
2613
2614 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2615 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2616 *const_and_shader_buffers =
2617 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2618
2619 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2620 start = si_get_image_slot(num_images - 1) / 2;
2621 *samplers_and_images =
2622 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2623 }
2624
2625 static void *si_create_shader_selector(struct pipe_context *ctx,
2626 const struct pipe_shader_state *state)
2627 {
2628 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2629 struct si_context *sctx = (struct si_context*)ctx;
2630 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2631 int i;
2632
2633 if (!sel)
2634 return NULL;
2635
2636 pipe_reference_init(&sel->reference, 1);
2637 sel->screen = sscreen;
2638 sel->compiler_ctx_state.debug = sctx->debug;
2639 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2640
2641 sel->so = state->stream_output;
2642
2643 if (state->type == PIPE_SHADER_IR_TGSI &&
2644 !sscreen->options.always_nir) {
2645 sel->tokens = tgsi_dup_tokens(state->tokens);
2646 if (!sel->tokens) {
2647 FREE(sel);
2648 return NULL;
2649 }
2650
2651 tgsi_scan_shader(state->tokens, &sel->info);
2652 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2653
2654 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2655 if (sel->info.uses_persp_opcode_interp_centroid)
2656 sel->info.uses_persp_centroid = true;
2657
2658 if (sel->info.uses_linear_opcode_interp_centroid)
2659 sel->info.uses_linear_centroid = true;
2660
2661 if (sel->info.uses_persp_opcode_interp_offset ||
2662 sel->info.uses_persp_opcode_interp_sample)
2663 sel->info.uses_persp_center = true;
2664
2665 if (sel->info.uses_linear_opcode_interp_offset ||
2666 sel->info.uses_linear_opcode_interp_sample)
2667 sel->info.uses_linear_center = true;
2668 } else {
2669 if (state->type == PIPE_SHADER_IR_TGSI) {
2670 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2671 } else {
2672 assert(state->type == PIPE_SHADER_IR_NIR);
2673 sel->nir = state->ir.nir;
2674 }
2675
2676 si_nir_lower_ps_inputs(sel->nir);
2677 si_nir_opts(sel->nir);
2678 si_nir_scan_shader(sel->nir, &sel->info);
2679 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2680 }
2681
2682 sel->type = sel->info.processor;
2683 p_atomic_inc(&sscreen->num_shaders_created);
2684 si_get_active_slot_masks(&sel->info,
2685 &sel->active_const_and_shader_buffers,
2686 &sel->active_samplers_and_images);
2687
2688 /* Record which streamout buffers are enabled. */
2689 for (i = 0; i < sel->so.num_outputs; i++) {
2690 sel->enabled_streamout_buffer_mask |=
2691 (1 << sel->so.output[i].output_buffer) <<
2692 (sel->so.output[i].stream * 4);
2693 }
2694
2695 /* The prolog is a no-op if there are no inputs. */
2696 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2697 sel->info.num_inputs &&
2698 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS];
2699
2700 sel->force_correct_derivs_after_kill =
2701 sel->type == PIPE_SHADER_FRAGMENT &&
2702 sel->info.uses_derivatives &&
2703 sel->info.uses_kill &&
2704 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2705
2706 sel->prim_discard_cs_allowed =
2707 sel->type == PIPE_SHADER_VERTEX &&
2708 !sel->info.uses_bindless_images &&
2709 !sel->info.uses_bindless_samplers &&
2710 !sel->info.writes_memory &&
2711 !sel->info.writes_viewport_index &&
2712 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2713 !sel->so.num_outputs;
2714
2715 if (sel->type == PIPE_SHADER_VERTEX &&
2716 sel->info.writes_edgeflag) {
2717 if (sscreen->info.chip_class >= GFX10)
2718 sel->ngg_writes_edgeflag = true;
2719 else
2720 sel->pos_writes_edgeflag = true;
2721 }
2722
2723 switch (sel->type) {
2724 case PIPE_SHADER_GEOMETRY:
2725 sel->gs_output_prim =
2726 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2727
2728 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2729 sel->rast_prim = sel->gs_output_prim;
2730 if (util_rast_prim_is_triangles(sel->rast_prim))
2731 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2732
2733 sel->gs_max_out_vertices =
2734 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2735 sel->gs_num_invocations =
2736 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2737 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2738 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2739 sel->gs_max_out_vertices;
2740
2741 sel->max_gs_stream = 0;
2742 for (i = 0; i < sel->so.num_outputs; i++)
2743 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2744 sel->so.output[i].stream);
2745
2746 sel->gs_input_verts_per_prim =
2747 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2748
2749 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2750 sel->tess_turns_off_ngg =
2751 (sscreen->info.family == CHIP_NAVI10 ||
2752 sscreen->info.family == CHIP_NAVI12 ||
2753 sscreen->info.family == CHIP_NAVI14) &&
2754 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2755 break;
2756
2757 case PIPE_SHADER_TESS_CTRL:
2758 /* Always reserve space for these. */
2759 sel->patch_outputs_written |=
2760 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2761 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2762 /* fall through */
2763 case PIPE_SHADER_VERTEX:
2764 case PIPE_SHADER_TESS_EVAL:
2765 for (i = 0; i < sel->info.num_outputs; i++) {
2766 unsigned name = sel->info.output_semantic_name[i];
2767 unsigned index = sel->info.output_semantic_index[i];
2768
2769 switch (name) {
2770 case TGSI_SEMANTIC_TESSINNER:
2771 case TGSI_SEMANTIC_TESSOUTER:
2772 case TGSI_SEMANTIC_PATCH:
2773 sel->patch_outputs_written |=
2774 1ull << si_shader_io_get_unique_index_patch(name, index);
2775 break;
2776
2777 case TGSI_SEMANTIC_GENERIC:
2778 /* don't process indices the function can't handle */
2779 if (index >= SI_MAX_IO_GENERIC)
2780 break;
2781 /* fall through */
2782 default:
2783 sel->outputs_written |=
2784 1ull << si_shader_io_get_unique_index(name, index, false);
2785 sel->outputs_written_before_ps |=
2786 1ull << si_shader_io_get_unique_index(name, index, true);
2787 break;
2788 case TGSI_SEMANTIC_EDGEFLAG:
2789 break;
2790 }
2791 }
2792 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2793 sel->lshs_vertex_stride = sel->esgs_itemsize;
2794
2795 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2796 * will start on a different bank. (except for the maximum 32*16).
2797 */
2798 if (sel->lshs_vertex_stride < 32*16)
2799 sel->lshs_vertex_stride += 4;
2800
2801 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2802 * conflicts, i.e. each vertex will start at a different bank.
2803 */
2804 if (sctx->chip_class >= GFX9)
2805 sel->esgs_itemsize += 4;
2806
2807 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2808
2809 /* Only for TES: */
2810 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2811 sel->rast_prim = PIPE_PRIM_POINTS;
2812 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2813 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2814 else
2815 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2816 break;
2817
2818 case PIPE_SHADER_FRAGMENT:
2819 for (i = 0; i < sel->info.num_inputs; i++) {
2820 unsigned name = sel->info.input_semantic_name[i];
2821 unsigned index = sel->info.input_semantic_index[i];
2822
2823 switch (name) {
2824 case TGSI_SEMANTIC_GENERIC:
2825 /* don't process indices the function can't handle */
2826 if (index >= SI_MAX_IO_GENERIC)
2827 break;
2828 /* fall through */
2829 default:
2830 sel->inputs_read |=
2831 1ull << si_shader_io_get_unique_index(name, index, true);
2832 break;
2833 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2834 break;
2835 }
2836 }
2837
2838 for (i = 0; i < 8; i++)
2839 if (sel->info.colors_written & (1 << i))
2840 sel->colors_written_4bit |= 0xf << (4 * i);
2841
2842 for (i = 0; i < sel->info.num_inputs; i++) {
2843 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2844 int index = sel->info.input_semantic_index[i];
2845 sel->color_attr_index[index] = i;
2846 }
2847 }
2848 break;
2849 default:;
2850 }
2851
2852 /* PA_CL_VS_OUT_CNTL */
2853 bool misc_vec_ena =
2854 sel->info.writes_psize || sel->pos_writes_edgeflag ||
2855 sel->info.writes_layer || sel->info.writes_viewport_index;
2856 sel->pa_cl_vs_out_cntl =
2857 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2858 S_02881C_USE_VTX_EDGE_FLAG(sel->pos_writes_edgeflag) |
2859 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2860 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2861 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2862 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2863 sel->clipdist_mask = sel->info.writes_clipvertex ?
2864 SIX_BITS : sel->info.clipdist_writemask;
2865 sel->culldist_mask = sel->info.culldist_writemask <<
2866 sel->info.num_written_clipdistance;
2867
2868 /* DB_SHADER_CONTROL */
2869 sel->db_shader_control =
2870 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2871 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2872 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2873 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2874
2875 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2876 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2877 sel->db_shader_control |=
2878 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2879 break;
2880 case TGSI_FS_DEPTH_LAYOUT_LESS:
2881 sel->db_shader_control |=
2882 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2883 break;
2884 }
2885
2886 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2887 *
2888 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2889 * --|-----------|------------|------------|--------------------|-------------------|-------------
2890 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2891 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2892 * 2 | false | true | n/a | LateZ | 1 | 0
2893 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2894 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2895 *
2896 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2897 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2898 *
2899 * Don't use ReZ without profiling !!!
2900 *
2901 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2902 * shaders.
2903 */
2904 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2905 /* Cases 3, 4. */
2906 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2907 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2908 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2909 } else if (sel->info.writes_memory) {
2910 /* Case 2. */
2911 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2912 S_02880C_EXEC_ON_HIER_FAIL(1);
2913 } else {
2914 /* Case 1. */
2915 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2916 }
2917
2918 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2919 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2920
2921 (void) mtx_init(&sel->mutex, mtx_plain);
2922
2923 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2924 &sel->compiler_ctx_state, sel,
2925 si_init_shader_selector_async);
2926 return sel;
2927 }
2928
2929 static void si_update_streamout_state(struct si_context *sctx)
2930 {
2931 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2932
2933 if (!shader_with_so)
2934 return;
2935
2936 sctx->streamout.enabled_stream_buffers_mask =
2937 shader_with_so->enabled_streamout_buffer_mask;
2938 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2939 }
2940
2941 static void si_update_clip_regs(struct si_context *sctx,
2942 struct si_shader_selector *old_hw_vs,
2943 struct si_shader *old_hw_vs_variant,
2944 struct si_shader_selector *next_hw_vs,
2945 struct si_shader *next_hw_vs_variant)
2946 {
2947 if (next_hw_vs &&
2948 (!old_hw_vs ||
2949 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2950 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2951 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2952 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2953 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2954 !old_hw_vs_variant ||
2955 !next_hw_vs_variant ||
2956 old_hw_vs_variant->key.opt.clip_disable !=
2957 next_hw_vs_variant->key.opt.clip_disable))
2958 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2959 }
2960
2961 static void si_update_common_shader_state(struct si_context *sctx)
2962 {
2963 sctx->uses_bindless_samplers =
2964 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2965 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2966 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2967 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2968 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2969 sctx->uses_bindless_images =
2970 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2971 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2972 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2973 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2974 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2975 sctx->do_update_shaders = true;
2976 }
2977
2978 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2979 {
2980 struct si_context *sctx = (struct si_context *)ctx;
2981 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2982 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2983 struct si_shader_selector *sel = state;
2984
2985 if (sctx->vs_shader.cso == sel)
2986 return;
2987
2988 sctx->vs_shader.cso = sel;
2989 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
2990 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS] : 0;
2991
2992 si_update_common_shader_state(sctx);
2993 si_update_vs_viewport_state(sctx);
2994 si_set_active_descriptors_for_shader(sctx, sel);
2995 si_update_streamout_state(sctx);
2996 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
2997 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
2998 }
2999
3000 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3001 {
3002 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3003 (sctx->tes_shader.cso &&
3004 sctx->tes_shader.cso->info.uses_primid) ||
3005 (sctx->tcs_shader.cso &&
3006 sctx->tcs_shader.cso->info.uses_primid) ||
3007 (sctx->gs_shader.cso &&
3008 sctx->gs_shader.cso->info.uses_primid) ||
3009 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3010 sctx->ps_shader.cso->info.uses_primid);
3011 }
3012
3013 static bool si_update_ngg(struct si_context *sctx)
3014 {
3015 if (sctx->chip_class <= GFX9)
3016 return false;
3017
3018 bool new_ngg = true;
3019
3020 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3021 sctx->gs_shader.cso->tess_turns_off_ngg)
3022 new_ngg = false;
3023
3024 if (new_ngg != sctx->ngg) {
3025 sctx->ngg = new_ngg;
3026 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3027 return true;
3028 }
3029 return false;
3030 }
3031
3032 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3033 {
3034 struct si_context *sctx = (struct si_context *)ctx;
3035 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3036 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3037 struct si_shader_selector *sel = state;
3038 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3039 bool ngg_changed;
3040
3041 if (sctx->gs_shader.cso == sel)
3042 return;
3043
3044 sctx->gs_shader.cso = sel;
3045 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3046 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3047
3048 si_update_common_shader_state(sctx);
3049 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3050
3051 ngg_changed = si_update_ngg(sctx);
3052 if (ngg_changed || enable_changed)
3053 si_shader_change_notify(sctx);
3054 if (enable_changed) {
3055 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3056 si_update_tess_uses_prim_id(sctx);
3057 }
3058 si_update_vs_viewport_state(sctx);
3059 si_set_active_descriptors_for_shader(sctx, sel);
3060 si_update_streamout_state(sctx);
3061 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3062 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3063 }
3064
3065 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3066 {
3067 struct si_context *sctx = (struct si_context *)ctx;
3068 struct si_shader_selector *sel = state;
3069 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3070
3071 if (sctx->tcs_shader.cso == sel)
3072 return;
3073
3074 sctx->tcs_shader.cso = sel;
3075 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3076 si_update_tess_uses_prim_id(sctx);
3077
3078 si_update_common_shader_state(sctx);
3079
3080 if (enable_changed)
3081 sctx->last_tcs = NULL; /* invalidate derived tess state */
3082
3083 si_set_active_descriptors_for_shader(sctx, sel);
3084 }
3085
3086 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3087 {
3088 struct si_context *sctx = (struct si_context *)ctx;
3089 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3090 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3091 struct si_shader_selector *sel = state;
3092 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3093
3094 if (sctx->tes_shader.cso == sel)
3095 return;
3096
3097 sctx->tes_shader.cso = sel;
3098 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3099 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3100 si_update_tess_uses_prim_id(sctx);
3101
3102 si_update_common_shader_state(sctx);
3103 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3104
3105 if (enable_changed) {
3106 si_update_ngg(sctx);
3107 si_shader_change_notify(sctx);
3108 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3109 }
3110 si_update_vs_viewport_state(sctx);
3111 si_set_active_descriptors_for_shader(sctx, sel);
3112 si_update_streamout_state(sctx);
3113 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3114 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3115 }
3116
3117 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3118 {
3119 struct si_context *sctx = (struct si_context *)ctx;
3120 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3121 struct si_shader_selector *sel = state;
3122
3123 /* skip if supplied shader is one already in use */
3124 if (old_sel == sel)
3125 return;
3126
3127 sctx->ps_shader.cso = sel;
3128 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3129
3130 si_update_common_shader_state(sctx);
3131 if (sel) {
3132 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3133 si_update_tess_uses_prim_id(sctx);
3134
3135 if (!old_sel ||
3136 old_sel->info.colors_written != sel->info.colors_written)
3137 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3138
3139 if (sctx->screen->has_out_of_order_rast &&
3140 (!old_sel ||
3141 old_sel->info.writes_memory != sel->info.writes_memory ||
3142 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3143 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3144 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3145 }
3146 si_set_active_descriptors_for_shader(sctx, sel);
3147 si_update_ps_colorbuf0_slot(sctx);
3148 }
3149
3150 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3151 {
3152 if (shader->is_optimized) {
3153 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3154 &shader->ready);
3155 }
3156
3157 util_queue_fence_destroy(&shader->ready);
3158
3159 if (shader->pm4) {
3160 /* If destroyed shaders were not unbound, the next compiled
3161 * shader variant could get the same pointer address and so
3162 * binding it to the same shader stage would be considered
3163 * a no-op, causing random behavior.
3164 */
3165 switch (shader->selector->type) {
3166 case PIPE_SHADER_VERTEX:
3167 if (shader->key.as_ls) {
3168 assert(sctx->chip_class <= GFX8);
3169 si_pm4_delete_state(sctx, ls, shader->pm4);
3170 } else if (shader->key.as_es) {
3171 assert(sctx->chip_class <= GFX8);
3172 si_pm4_delete_state(sctx, es, shader->pm4);
3173 } else if (shader->key.as_ngg) {
3174 si_pm4_delete_state(sctx, gs, shader->pm4);
3175 } else {
3176 si_pm4_delete_state(sctx, vs, shader->pm4);
3177 }
3178 break;
3179 case PIPE_SHADER_TESS_CTRL:
3180 si_pm4_delete_state(sctx, hs, shader->pm4);
3181 break;
3182 case PIPE_SHADER_TESS_EVAL:
3183 if (shader->key.as_es) {
3184 assert(sctx->chip_class <= GFX8);
3185 si_pm4_delete_state(sctx, es, shader->pm4);
3186 } else if (shader->key.as_ngg) {
3187 si_pm4_delete_state(sctx, gs, shader->pm4);
3188 } else {
3189 si_pm4_delete_state(sctx, vs, shader->pm4);
3190 }
3191 break;
3192 case PIPE_SHADER_GEOMETRY:
3193 if (shader->is_gs_copy_shader)
3194 si_pm4_delete_state(sctx, vs, shader->pm4);
3195 else
3196 si_pm4_delete_state(sctx, gs, shader->pm4);
3197 break;
3198 case PIPE_SHADER_FRAGMENT:
3199 si_pm4_delete_state(sctx, ps, shader->pm4);
3200 break;
3201 default:;
3202 }
3203 }
3204
3205 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3206 si_shader_destroy(shader);
3207 free(shader);
3208 }
3209
3210 void si_destroy_shader_selector(struct si_context *sctx,
3211 struct si_shader_selector *sel)
3212 {
3213 struct si_shader *p = sel->first_variant, *c;
3214 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3215 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3216 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3217 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3218 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3219 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3220 };
3221
3222 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3223
3224 if (current_shader[sel->type]->cso == sel) {
3225 current_shader[sel->type]->cso = NULL;
3226 current_shader[sel->type]->current = NULL;
3227 }
3228
3229 while (p) {
3230 c = p->next_variant;
3231 si_delete_shader(sctx, p);
3232 p = c;
3233 }
3234
3235 if (sel->main_shader_part)
3236 si_delete_shader(sctx, sel->main_shader_part);
3237 if (sel->main_shader_part_ls)
3238 si_delete_shader(sctx, sel->main_shader_part_ls);
3239 if (sel->main_shader_part_es)
3240 si_delete_shader(sctx, sel->main_shader_part_es);
3241 if (sel->main_shader_part_ngg)
3242 si_delete_shader(sctx, sel->main_shader_part_ngg);
3243 if (sel->gs_copy_shader)
3244 si_delete_shader(sctx, sel->gs_copy_shader);
3245
3246 util_queue_fence_destroy(&sel->ready);
3247 mtx_destroy(&sel->mutex);
3248 free(sel->tokens);
3249 ralloc_free(sel->nir);
3250 free(sel);
3251 }
3252
3253 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3254 {
3255 struct si_context *sctx = (struct si_context *)ctx;
3256 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3257
3258 si_shader_selector_reference(sctx, &sel, NULL);
3259 }
3260
3261 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3262 struct si_shader *vs, unsigned name,
3263 unsigned index, unsigned interpolate)
3264 {
3265 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3266 unsigned j, offset, ps_input_cntl = 0;
3267
3268 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3269 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3270 name == TGSI_SEMANTIC_PRIMID)
3271 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3272
3273 if (name == TGSI_SEMANTIC_PCOORD ||
3274 (name == TGSI_SEMANTIC_TEXCOORD &&
3275 sctx->sprite_coord_enable & (1 << index))) {
3276 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3277 }
3278
3279 for (j = 0; j < vsinfo->num_outputs; j++) {
3280 if (name == vsinfo->output_semantic_name[j] &&
3281 index == vsinfo->output_semantic_index[j]) {
3282 offset = vs->info.vs_output_param_offset[j];
3283
3284 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3285 /* The input is loaded from parameter memory. */
3286 ps_input_cntl |= S_028644_OFFSET(offset);
3287 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3288 if (offset == AC_EXP_PARAM_UNDEFINED) {
3289 /* This can happen with depth-only rendering. */
3290 offset = 0;
3291 } else {
3292 /* The input is a DEFAULT_VAL constant. */
3293 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3294 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3295 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3296 }
3297
3298 ps_input_cntl = S_028644_OFFSET(0x20) |
3299 S_028644_DEFAULT_VAL(offset);
3300 }
3301 break;
3302 }
3303 }
3304
3305 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3306 /* PrimID is written after the last output when HW VS is used. */
3307 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3308 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3309 /* No corresponding output found, load defaults into input.
3310 * Don't set any other bits.
3311 * (FLAT_SHADE=1 completely changes behavior) */
3312 ps_input_cntl = S_028644_OFFSET(0x20);
3313 /* D3D 9 behaviour. GL is undefined */
3314 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3315 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3316 }
3317 return ps_input_cntl;
3318 }
3319
3320 static void si_emit_spi_map(struct si_context *sctx)
3321 {
3322 struct si_shader *ps = sctx->ps_shader.current;
3323 struct si_shader *vs = si_get_vs_state(sctx);
3324 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3325 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3326 unsigned spi_ps_input_cntl[32];
3327
3328 if (!ps || !ps->selector->info.num_inputs)
3329 return;
3330
3331 num_interp = si_get_ps_num_interp(ps);
3332 assert(num_interp > 0);
3333
3334 for (i = 0; i < psinfo->num_inputs; i++) {
3335 unsigned name = psinfo->input_semantic_name[i];
3336 unsigned index = psinfo->input_semantic_index[i];
3337 unsigned interpolate = psinfo->input_interpolate[i];
3338
3339 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3340 index, interpolate);
3341
3342 if (name == TGSI_SEMANTIC_COLOR) {
3343 assert(index < ARRAY_SIZE(bcol_interp));
3344 bcol_interp[index] = interpolate;
3345 }
3346 }
3347
3348 if (ps->key.part.ps.prolog.color_two_side) {
3349 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3350
3351 for (i = 0; i < 2; i++) {
3352 if (!(psinfo->colors_read & (0xf << (i * 4))))
3353 continue;
3354
3355 spi_ps_input_cntl[num_written++] =
3356 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3357
3358 }
3359 }
3360 assert(num_interp == num_written);
3361
3362 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3363 /* Dota 2: Only ~16% of SPI map updates set different values. */
3364 /* Talos: Only ~9% of SPI map updates set different values. */
3365 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3366 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3367 spi_ps_input_cntl,
3368 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3369
3370 if (initial_cdw != sctx->gfx_cs->current.cdw)
3371 sctx->context_roll = true;
3372 }
3373
3374 /**
3375 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3376 */
3377 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3378 {
3379 if (sctx->init_config_has_vgt_flush)
3380 return;
3381
3382 /* Done by Vulkan before VGT_FLUSH. */
3383 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3384 si_pm4_cmd_add(sctx->init_config,
3385 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3386 si_pm4_cmd_end(sctx->init_config, false);
3387
3388 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3389 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3390 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3391 si_pm4_cmd_end(sctx->init_config, false);
3392 sctx->init_config_has_vgt_flush = true;
3393 }
3394
3395 /* Initialize state related to ESGS / GSVS ring buffers */
3396 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3397 {
3398 struct si_shader_selector *es =
3399 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3400 struct si_shader_selector *gs = sctx->gs_shader.cso;
3401 struct si_pm4_state *pm4;
3402
3403 /* Chip constants. */
3404 unsigned num_se = sctx->screen->info.max_se;
3405 unsigned wave_size = 64;
3406 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3407 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3408 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3409 */
3410 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3411 unsigned alignment = 256 * num_se;
3412 /* The maximum size is 63.999 MB per SE. */
3413 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3414
3415 /* Calculate the minimum size. */
3416 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3417 wave_size, alignment);
3418
3419 /* These are recommended sizes, not minimum sizes. */
3420 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3421 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3422 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3423 gs->max_gsvs_emit_size;
3424
3425 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3426 esgs_ring_size = align(esgs_ring_size, alignment);
3427 gsvs_ring_size = align(gsvs_ring_size, alignment);
3428
3429 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3430 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3431
3432 /* Some rings don't have to be allocated if shaders don't use them.
3433 * (e.g. no varyings between ES and GS or GS and VS)
3434 *
3435 * GFX9 doesn't have the ESGS ring.
3436 */
3437 bool update_esgs = sctx->chip_class <= GFX8 &&
3438 esgs_ring_size &&
3439 (!sctx->esgs_ring ||
3440 sctx->esgs_ring->width0 < esgs_ring_size);
3441 bool update_gsvs = gsvs_ring_size &&
3442 (!sctx->gsvs_ring ||
3443 sctx->gsvs_ring->width0 < gsvs_ring_size);
3444
3445 if (!update_esgs && !update_gsvs)
3446 return true;
3447
3448 if (update_esgs) {
3449 pipe_resource_reference(&sctx->esgs_ring, NULL);
3450 sctx->esgs_ring =
3451 pipe_aligned_buffer_create(sctx->b.screen,
3452 SI_RESOURCE_FLAG_UNMAPPABLE,
3453 PIPE_USAGE_DEFAULT,
3454 esgs_ring_size, alignment);
3455 if (!sctx->esgs_ring)
3456 return false;
3457 }
3458
3459 if (update_gsvs) {
3460 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3461 sctx->gsvs_ring =
3462 pipe_aligned_buffer_create(sctx->b.screen,
3463 SI_RESOURCE_FLAG_UNMAPPABLE,
3464 PIPE_USAGE_DEFAULT,
3465 gsvs_ring_size, alignment);
3466 if (!sctx->gsvs_ring)
3467 return false;
3468 }
3469
3470 /* Create the "init_config_gs_rings" state. */
3471 pm4 = CALLOC_STRUCT(si_pm4_state);
3472 if (!pm4)
3473 return false;
3474
3475 if (sctx->chip_class >= GFX7) {
3476 if (sctx->esgs_ring) {
3477 assert(sctx->chip_class <= GFX8);
3478 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3479 sctx->esgs_ring->width0 / 256);
3480 }
3481 if (sctx->gsvs_ring)
3482 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3483 sctx->gsvs_ring->width0 / 256);
3484 } else {
3485 if (sctx->esgs_ring)
3486 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3487 sctx->esgs_ring->width0 / 256);
3488 if (sctx->gsvs_ring)
3489 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3490 sctx->gsvs_ring->width0 / 256);
3491 }
3492
3493 /* Set the state. */
3494 if (sctx->init_config_gs_rings)
3495 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3496 sctx->init_config_gs_rings = pm4;
3497
3498 if (!sctx->init_config_has_vgt_flush) {
3499 si_init_config_add_vgt_flush(sctx);
3500 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3501 }
3502
3503 /* Flush the context to re-emit both init_config states. */
3504 sctx->initial_gfx_cs_size = 0; /* force flush */
3505 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3506
3507 /* Set ring bindings. */
3508 if (sctx->esgs_ring) {
3509 assert(sctx->chip_class <= GFX8);
3510 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3511 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3512 true, true, 4, 64, 0);
3513 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3514 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3515 false, false, 0, 0, 0);
3516 }
3517 if (sctx->gsvs_ring) {
3518 si_set_ring_buffer(sctx, SI_RING_GSVS,
3519 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3520 false, false, 0, 0, 0);
3521 }
3522
3523 return true;
3524 }
3525
3526 static void si_shader_lock(struct si_shader *shader)
3527 {
3528 mtx_lock(&shader->selector->mutex);
3529 if (shader->previous_stage_sel) {
3530 assert(shader->previous_stage_sel != shader->selector);
3531 mtx_lock(&shader->previous_stage_sel->mutex);
3532 }
3533 }
3534
3535 static void si_shader_unlock(struct si_shader *shader)
3536 {
3537 if (shader->previous_stage_sel)
3538 mtx_unlock(&shader->previous_stage_sel->mutex);
3539 mtx_unlock(&shader->selector->mutex);
3540 }
3541
3542 /**
3543 * @returns 1 if \p sel has been updated to use a new scratch buffer
3544 * 0 if not
3545 * < 0 if there was a failure
3546 */
3547 static int si_update_scratch_buffer(struct si_context *sctx,
3548 struct si_shader *shader)
3549 {
3550 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3551
3552 if (!shader)
3553 return 0;
3554
3555 /* This shader doesn't need a scratch buffer */
3556 if (shader->config.scratch_bytes_per_wave == 0)
3557 return 0;
3558
3559 /* Prevent race conditions when updating:
3560 * - si_shader::scratch_bo
3561 * - si_shader::binary::code
3562 * - si_shader::previous_stage::binary::code.
3563 */
3564 si_shader_lock(shader);
3565
3566 /* This shader is already configured to use the current
3567 * scratch buffer. */
3568 if (shader->scratch_bo == sctx->scratch_buffer) {
3569 si_shader_unlock(shader);
3570 return 0;
3571 }
3572
3573 assert(sctx->scratch_buffer);
3574
3575 /* Replace the shader bo with a new bo that has the relocs applied. */
3576 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3577 si_shader_unlock(shader);
3578 return -1;
3579 }
3580
3581 /* Update the shader state to use the new shader bo. */
3582 si_shader_init_pm4_state(sctx->screen, shader);
3583
3584 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3585
3586 si_shader_unlock(shader);
3587 return 1;
3588 }
3589
3590 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3591 {
3592 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3593 }
3594
3595 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3596 {
3597 return shader ? shader->config.scratch_bytes_per_wave : 0;
3598 }
3599
3600 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3601 {
3602 if (!sctx->tes_shader.cso)
3603 return NULL; /* tessellation disabled */
3604
3605 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3606 sctx->fixed_func_tcs_shader.current;
3607 }
3608
3609 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3610 {
3611 unsigned bytes = 0;
3612
3613 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3614 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3615 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3616 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3617
3618 if (sctx->tes_shader.cso) {
3619 struct si_shader *tcs = si_get_tcs_current(sctx);
3620
3621 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3622 }
3623 return bytes;
3624 }
3625
3626 static bool si_update_scratch_relocs(struct si_context *sctx)
3627 {
3628 struct si_shader *tcs = si_get_tcs_current(sctx);
3629 int r;
3630
3631 /* Update the shaders, so that they are using the latest scratch.
3632 * The scratch buffer may have been changed since these shaders were
3633 * last used, so we still need to try to update them, even if they
3634 * require scratch buffers smaller than the current size.
3635 */
3636 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3637 if (r < 0)
3638 return false;
3639 if (r == 1)
3640 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3641
3642 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3643 if (r < 0)
3644 return false;
3645 if (r == 1)
3646 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3647
3648 r = si_update_scratch_buffer(sctx, tcs);
3649 if (r < 0)
3650 return false;
3651 if (r == 1)
3652 si_pm4_bind_state(sctx, hs, tcs->pm4);
3653
3654 /* VS can be bound as LS, ES, or VS. */
3655 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3656 if (r < 0)
3657 return false;
3658 if (r == 1) {
3659 if (sctx->vs_shader.current->key.as_ls)
3660 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3661 else if (sctx->vs_shader.current->key.as_es)
3662 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3663 else if (sctx->vs_shader.current->key.as_ngg)
3664 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3665 else
3666 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3667 }
3668
3669 /* TES can be bound as ES or VS. */
3670 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3671 if (r < 0)
3672 return false;
3673 if (r == 1) {
3674 if (sctx->tes_shader.current->key.as_es)
3675 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3676 else if (sctx->tes_shader.current->key.as_ngg)
3677 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3678 else
3679 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3680 }
3681
3682 return true;
3683 }
3684
3685 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3686 {
3687 unsigned current_scratch_buffer_size =
3688 si_get_current_scratch_buffer_size(sctx);
3689 unsigned scratch_bytes_per_wave =
3690 si_get_max_scratch_bytes_per_wave(sctx);
3691 unsigned scratch_needed_size = scratch_bytes_per_wave *
3692 sctx->scratch_waves;
3693 unsigned spi_tmpring_size;
3694
3695 if (scratch_needed_size > 0) {
3696 if (scratch_needed_size > current_scratch_buffer_size) {
3697 /* Create a bigger scratch buffer */
3698 si_resource_reference(&sctx->scratch_buffer, NULL);
3699
3700 sctx->scratch_buffer =
3701 si_aligned_buffer_create(&sctx->screen->b,
3702 SI_RESOURCE_FLAG_UNMAPPABLE,
3703 PIPE_USAGE_DEFAULT,
3704 scratch_needed_size, 256);
3705 if (!sctx->scratch_buffer)
3706 return false;
3707
3708 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3709 si_context_add_resource_size(sctx,
3710 &sctx->scratch_buffer->b.b);
3711 }
3712
3713 if (!si_update_scratch_relocs(sctx))
3714 return false;
3715 }
3716
3717 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3718 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3719 "scratch size should already be aligned correctly.");
3720
3721 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3722 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3723 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3724 sctx->spi_tmpring_size = spi_tmpring_size;
3725 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3726 }
3727 return true;
3728 }
3729
3730 static void si_init_tess_factor_ring(struct si_context *sctx)
3731 {
3732 assert(!sctx->tess_rings);
3733
3734 /* The address must be aligned to 2^19, because the shader only
3735 * receives the high 13 bits.
3736 */
3737 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3738 SI_RESOURCE_FLAG_32BIT,
3739 PIPE_USAGE_DEFAULT,
3740 sctx->screen->tess_offchip_ring_size +
3741 sctx->screen->tess_factor_ring_size,
3742 1 << 19);
3743 if (!sctx->tess_rings)
3744 return;
3745
3746 si_init_config_add_vgt_flush(sctx);
3747
3748 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3749 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3750
3751 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3752 sctx->screen->tess_offchip_ring_size;
3753
3754 /* Append these registers to the init config state. */
3755 if (sctx->chip_class >= GFX7) {
3756 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3757 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3758 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3759 factor_va >> 8);
3760 if (sctx->chip_class >= GFX10)
3761 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3762 S_030984_BASE_HI(factor_va >> 40));
3763 else if (sctx->chip_class == GFX9)
3764 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3765 S_030944_BASE_HI(factor_va >> 40));
3766 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3767 sctx->screen->vgt_hs_offchip_param);
3768 } else {
3769 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3770 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3771 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3772 factor_va >> 8);
3773 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3774 sctx->screen->vgt_hs_offchip_param);
3775 }
3776
3777 /* Flush the context to re-emit the init_config state.
3778 * This is done only once in a lifetime of a context.
3779 */
3780 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3781 sctx->initial_gfx_cs_size = 0; /* force flush */
3782 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3783 }
3784
3785 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3786 union si_vgt_stages_key key)
3787 {
3788 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3789 uint32_t stages = 0;
3790
3791 if (key.u.tess) {
3792 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3793 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3794
3795 if (key.u.gs)
3796 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3797 S_028B54_GS_EN(1);
3798 else if (key.u.ngg)
3799 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3800 else
3801 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3802 } else if (key.u.gs) {
3803 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3804 S_028B54_GS_EN(1);
3805 } else if (key.u.ngg) {
3806 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3807 }
3808
3809 if (key.u.ngg) {
3810 stages |= S_028B54_PRIMGEN_EN(1);
3811 if (key.u.streamout)
3812 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3813 } else if (key.u.gs)
3814 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3815
3816 if (screen->info.chip_class >= GFX9)
3817 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3818
3819 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3820 stages |= S_028B54_HS_W32_EN(1) |
3821 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3822 S_028B54_VS_W32_EN(1);
3823 }
3824
3825 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3826 return pm4;
3827 }
3828
3829 static void si_update_vgt_shader_config(struct si_context *sctx,
3830 union si_vgt_stages_key key)
3831 {
3832 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3833
3834 if (unlikely(!*pm4))
3835 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3836 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3837 }
3838
3839 bool si_update_shaders(struct si_context *sctx)
3840 {
3841 struct pipe_context *ctx = (struct pipe_context*)sctx;
3842 struct si_compiler_ctx_state compiler_state;
3843 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3844 struct si_shader *old_vs = si_get_vs_state(sctx);
3845 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3846 struct si_shader *old_ps = sctx->ps_shader.current;
3847 union si_vgt_stages_key key;
3848 unsigned old_spi_shader_col_format =
3849 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3850 int r;
3851
3852 compiler_state.compiler = &sctx->compiler;
3853 compiler_state.debug = sctx->debug;
3854 compiler_state.is_debug_context = sctx->is_debug;
3855
3856 key.index = 0;
3857
3858 if (sctx->tes_shader.cso)
3859 key.u.tess = 1;
3860 if (sctx->gs_shader.cso)
3861 key.u.gs = 1;
3862
3863 if (sctx->ngg) {
3864 key.u.ngg = 1;
3865 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3866 }
3867
3868 /* Update TCS and TES. */
3869 if (sctx->tes_shader.cso) {
3870 if (!sctx->tess_rings) {
3871 si_init_tess_factor_ring(sctx);
3872 if (!sctx->tess_rings)
3873 return false;
3874 }
3875
3876 if (sctx->tcs_shader.cso) {
3877 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3878 &compiler_state);
3879 if (r)
3880 return false;
3881 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3882 } else {
3883 if (!sctx->fixed_func_tcs_shader.cso) {
3884 sctx->fixed_func_tcs_shader.cso =
3885 si_create_fixed_func_tcs(sctx);
3886 if (!sctx->fixed_func_tcs_shader.cso)
3887 return false;
3888 }
3889
3890 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3891 key, &compiler_state);
3892 if (r)
3893 return false;
3894 si_pm4_bind_state(sctx, hs,
3895 sctx->fixed_func_tcs_shader.current->pm4);
3896 }
3897
3898 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3899 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3900 if (r)
3901 return false;
3902
3903 if (sctx->gs_shader.cso) {
3904 /* TES as ES */
3905 assert(sctx->chip_class <= GFX8);
3906 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3907 } else if (key.u.ngg) {
3908 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3909 } else {
3910 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3911 }
3912 }
3913 } else {
3914 if (sctx->chip_class <= GFX8)
3915 si_pm4_bind_state(sctx, ls, NULL);
3916 si_pm4_bind_state(sctx, hs, NULL);
3917 }
3918
3919 /* Update GS. */
3920 if (sctx->gs_shader.cso) {
3921 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3922 if (r)
3923 return false;
3924 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3925 if (!key.u.ngg) {
3926 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3927
3928 if (!si_update_gs_ring_buffers(sctx))
3929 return false;
3930 } else {
3931 si_pm4_bind_state(sctx, vs, NULL);
3932 }
3933 } else {
3934 if (!key.u.ngg) {
3935 si_pm4_bind_state(sctx, gs, NULL);
3936 if (sctx->chip_class <= GFX8)
3937 si_pm4_bind_state(sctx, es, NULL);
3938 }
3939 }
3940
3941 /* Update VS. */
3942 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3943 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3944 if (r)
3945 return false;
3946
3947 if (!key.u.tess && !key.u.gs) {
3948 if (key.u.ngg) {
3949 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3950 si_pm4_bind_state(sctx, vs, NULL);
3951 } else {
3952 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3953 }
3954 } else if (sctx->tes_shader.cso) {
3955 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3956 } else {
3957 assert(sctx->gs_shader.cso);
3958 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3959 }
3960 }
3961
3962 si_update_vgt_shader_config(sctx, key);
3963
3964 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3965 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
3966
3967 if (sctx->ps_shader.cso) {
3968 unsigned db_shader_control;
3969
3970 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
3971 if (r)
3972 return false;
3973 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3974
3975 db_shader_control =
3976 sctx->ps_shader.cso->db_shader_control |
3977 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
3978
3979 if (si_pm4_state_changed(sctx, ps) ||
3980 si_pm4_state_changed(sctx, vs) ||
3981 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
3982 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
3983 sctx->flatshade != rs->flatshade) {
3984 sctx->sprite_coord_enable = rs->sprite_coord_enable;
3985 sctx->flatshade = rs->flatshade;
3986 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
3987 }
3988
3989 if (sctx->screen->rbplus_allowed &&
3990 si_pm4_state_changed(sctx, ps) &&
3991 (!old_ps ||
3992 old_spi_shader_col_format !=
3993 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
3994 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3995
3996 if (sctx->ps_db_shader_control != db_shader_control) {
3997 sctx->ps_db_shader_control = db_shader_control;
3998 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
3999 if (sctx->screen->dpbb_allowed)
4000 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4001 }
4002
4003 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4004 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4005 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4006
4007 if (sctx->chip_class == GFX6)
4008 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4009
4010 if (sctx->framebuffer.nr_samples <= 1)
4011 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4012 }
4013 }
4014
4015 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4016 si_pm4_state_enabled_and_changed(sctx, hs) ||
4017 si_pm4_state_enabled_and_changed(sctx, es) ||
4018 si_pm4_state_enabled_and_changed(sctx, gs) ||
4019 si_pm4_state_enabled_and_changed(sctx, vs) ||
4020 si_pm4_state_enabled_and_changed(sctx, ps)) {
4021 if (!si_update_spi_tmpring_size(sctx))
4022 return false;
4023 }
4024
4025 if (sctx->chip_class >= GFX7) {
4026 if (si_pm4_state_enabled_and_changed(sctx, ls))
4027 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4028 else if (!sctx->queued.named.ls)
4029 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4030
4031 if (si_pm4_state_enabled_and_changed(sctx, hs))
4032 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4033 else if (!sctx->queued.named.hs)
4034 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4035
4036 if (si_pm4_state_enabled_and_changed(sctx, es))
4037 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4038 else if (!sctx->queued.named.es)
4039 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4040
4041 if (si_pm4_state_enabled_and_changed(sctx, gs))
4042 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4043 else if (!sctx->queued.named.gs)
4044 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4045
4046 if (si_pm4_state_enabled_and_changed(sctx, vs))
4047 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4048 else if (!sctx->queued.named.vs)
4049 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4050
4051 if (si_pm4_state_enabled_and_changed(sctx, ps))
4052 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4053 else if (!sctx->queued.named.ps)
4054 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4055 }
4056
4057 sctx->do_update_shaders = false;
4058 return true;
4059 }
4060
4061 static void si_emit_scratch_state(struct si_context *sctx)
4062 {
4063 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4064
4065 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4066 sctx->spi_tmpring_size);
4067
4068 if (sctx->scratch_buffer) {
4069 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4070 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4071 RADEON_PRIO_SCRATCH_BUFFER);
4072 }
4073 }
4074
4075 void si_init_shader_functions(struct si_context *sctx)
4076 {
4077 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4078 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4079
4080 sctx->b.create_vs_state = si_create_shader_selector;
4081 sctx->b.create_tcs_state = si_create_shader_selector;
4082 sctx->b.create_tes_state = si_create_shader_selector;
4083 sctx->b.create_gs_state = si_create_shader_selector;
4084 sctx->b.create_fs_state = si_create_shader_selector;
4085
4086 sctx->b.bind_vs_state = si_bind_vs_shader;
4087 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4088 sctx->b.bind_tes_state = si_bind_tes_shader;
4089 sctx->b.bind_gs_state = si_bind_gs_shader;
4090 sctx->b.bind_fs_state = si_bind_ps_shader;
4091
4092 sctx->b.delete_vs_state = si_delete_shader_selector;
4093 sctx->b.delete_tcs_state = si_delete_shader_selector;
4094 sctx->b.delete_tes_state = si_delete_shader_selector;
4095 sctx->b.delete_gs_state = si_delete_shader_selector;
4096 sctx->b.delete_fs_state = si_delete_shader_selector;
4097 }