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radeonsi/gfx10: create the GS copy shader if using legacy streamout
[mesa.git] / src / gallium / drivers / radeonsi / si_state_shaders.c
1 /*
2 * Copyright 2012 Advanced Micro Devices, Inc.
3 * All Rights Reserved.
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "si_build_pm4.h"
26 #include "sid.h"
27
28 #include "compiler/nir/nir_serialize.h"
29 #include "nir/tgsi_to_nir.h"
30 #include "tgsi/tgsi_parse.h"
31 #include "util/hash_table.h"
32 #include "util/crc32.h"
33 #include "util/u_async_debug.h"
34 #include "util/u_memory.h"
35 #include "util/u_prim.h"
36
37 #include "util/disk_cache.h"
38 #include "util/mesa-sha1.h"
39 #include "ac_exp_param.h"
40 #include "ac_shader_util.h"
41
42 /* SHADER_CACHE */
43
44 /**
45 * Return the IR binary in a buffer. For TGSI the first 4 bytes contain its
46 * size as integer.
47 */
48 void *si_get_ir_binary(struct si_shader_selector *sel, bool ngg, bool es)
49 {
50 struct blob blob;
51 unsigned ir_size;
52 void *ir_binary;
53
54 if (sel->tokens) {
55 ir_binary = sel->tokens;
56 ir_size = tgsi_num_tokens(sel->tokens) *
57 sizeof(struct tgsi_token);
58 } else {
59 assert(sel->nir);
60
61 blob_init(&blob);
62 nir_serialize(&blob, sel->nir);
63 ir_binary = blob.data;
64 ir_size = blob.size;
65 }
66
67 /* These settings affect the compilation, but they are not derived
68 * from the input shader IR.
69 */
70 unsigned shader_variant_flags = 0;
71
72 if (ngg)
73 shader_variant_flags |= 1 << 0;
74 if (sel->nir)
75 shader_variant_flags |= 1 << 1;
76 if (si_get_wave_size(sel->screen, sel->type, ngg, es) == 32)
77 shader_variant_flags |= 1 << 2;
78 if (sel->force_correct_derivs_after_kill)
79 shader_variant_flags |= 1 << 3;
80
81 unsigned size = 4 + 4 + ir_size + sizeof(sel->so);
82 char *result = (char*)MALLOC(size);
83 if (!result)
84 return NULL;
85
86 ((uint32_t*)result)[0] = size;
87 ((uint32_t*)result)[1] = shader_variant_flags;
88 memcpy(result + 8, ir_binary, ir_size);
89 memcpy(result + 8 + ir_size, &sel->so, sizeof(sel->so));
90
91 if (sel->nir)
92 blob_finish(&blob);
93
94 return result;
95 }
96
97 /** Copy "data" to "ptr" and return the next dword following copied data. */
98 static uint32_t *write_data(uint32_t *ptr, const void *data, unsigned size)
99 {
100 /* data may be NULL if size == 0 */
101 if (size)
102 memcpy(ptr, data, size);
103 ptr += DIV_ROUND_UP(size, 4);
104 return ptr;
105 }
106
107 /** Read data from "ptr". Return the next dword following the data. */
108 static uint32_t *read_data(uint32_t *ptr, void *data, unsigned size)
109 {
110 memcpy(data, ptr, size);
111 ptr += DIV_ROUND_UP(size, 4);
112 return ptr;
113 }
114
115 /**
116 * Write the size as uint followed by the data. Return the next dword
117 * following the copied data.
118 */
119 static uint32_t *write_chunk(uint32_t *ptr, const void *data, unsigned size)
120 {
121 *ptr++ = size;
122 return write_data(ptr, data, size);
123 }
124
125 /**
126 * Read the size as uint followed by the data. Return both via parameters.
127 * Return the next dword following the data.
128 */
129 static uint32_t *read_chunk(uint32_t *ptr, void **data, unsigned *size)
130 {
131 *size = *ptr++;
132 assert(*data == NULL);
133 if (!*size)
134 return ptr;
135 *data = malloc(*size);
136 return read_data(ptr, *data, *size);
137 }
138
139 /**
140 * Return the shader binary in a buffer. The first 4 bytes contain its size
141 * as integer.
142 */
143 static void *si_get_shader_binary(struct si_shader *shader)
144 {
145 /* There is always a size of data followed by the data itself. */
146 unsigned llvm_ir_size = shader->binary.llvm_ir_string ?
147 strlen(shader->binary.llvm_ir_string) + 1 : 0;
148
149 /* Refuse to allocate overly large buffers and guard against integer
150 * overflow. */
151 if (shader->binary.elf_size > UINT_MAX / 4 ||
152 llvm_ir_size > UINT_MAX / 4)
153 return NULL;
154
155 unsigned size =
156 4 + /* total size */
157 4 + /* CRC32 of the data below */
158 align(sizeof(shader->config), 4) +
159 align(sizeof(shader->info), 4) +
160 4 + align(shader->binary.elf_size, 4) +
161 4 + align(llvm_ir_size, 4);
162 void *buffer = CALLOC(1, size);
163 uint32_t *ptr = (uint32_t*)buffer;
164
165 if (!buffer)
166 return NULL;
167
168 *ptr++ = size;
169 ptr++; /* CRC32 is calculated at the end. */
170
171 ptr = write_data(ptr, &shader->config, sizeof(shader->config));
172 ptr = write_data(ptr, &shader->info, sizeof(shader->info));
173 ptr = write_chunk(ptr, shader->binary.elf_buffer, shader->binary.elf_size);
174 ptr = write_chunk(ptr, shader->binary.llvm_ir_string, llvm_ir_size);
175 assert((char *)ptr - (char *)buffer == size);
176
177 /* Compute CRC32. */
178 ptr = (uint32_t*)buffer;
179 ptr++;
180 *ptr = util_hash_crc32(ptr + 1, size - 8);
181
182 return buffer;
183 }
184
185 static bool si_load_shader_binary(struct si_shader *shader, void *binary)
186 {
187 uint32_t *ptr = (uint32_t*)binary;
188 uint32_t size = *ptr++;
189 uint32_t crc32 = *ptr++;
190 unsigned chunk_size;
191 unsigned elf_size;
192
193 if (util_hash_crc32(ptr, size - 8) != crc32) {
194 fprintf(stderr, "radeonsi: binary shader has invalid CRC32\n");
195 return false;
196 }
197
198 ptr = read_data(ptr, &shader->config, sizeof(shader->config));
199 ptr = read_data(ptr, &shader->info, sizeof(shader->info));
200 ptr = read_chunk(ptr, (void**)&shader->binary.elf_buffer,
201 &elf_size);
202 shader->binary.elf_size = elf_size;
203 ptr = read_chunk(ptr, (void**)&shader->binary.llvm_ir_string, &chunk_size);
204
205 return true;
206 }
207
208 /**
209 * Insert a shader into the cache. It's assumed the shader is not in the cache.
210 * Use si_shader_cache_load_shader before calling this.
211 *
212 * Returns false on failure, in which case the ir_binary should be freed.
213 */
214 bool si_shader_cache_insert_shader(struct si_screen *sscreen, void *ir_binary,
215 struct si_shader *shader,
216 bool insert_into_disk_cache)
217 {
218 void *hw_binary;
219 struct hash_entry *entry;
220 uint8_t key[CACHE_KEY_SIZE];
221
222 entry = _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
223 if (entry)
224 return false; /* already added */
225
226 hw_binary = si_get_shader_binary(shader);
227 if (!hw_binary)
228 return false;
229
230 if (_mesa_hash_table_insert(sscreen->shader_cache, ir_binary,
231 hw_binary) == NULL) {
232 FREE(hw_binary);
233 return false;
234 }
235
236 if (sscreen->disk_shader_cache && insert_into_disk_cache) {
237 disk_cache_compute_key(sscreen->disk_shader_cache, ir_binary,
238 *((uint32_t *)ir_binary), key);
239 disk_cache_put(sscreen->disk_shader_cache, key, hw_binary,
240 *((uint32_t *) hw_binary), NULL);
241 }
242
243 return true;
244 }
245
246 bool si_shader_cache_load_shader(struct si_screen *sscreen, void *ir_binary,
247 struct si_shader *shader)
248 {
249 struct hash_entry *entry =
250 _mesa_hash_table_search(sscreen->shader_cache, ir_binary);
251 if (!entry) {
252 if (sscreen->disk_shader_cache) {
253 unsigned char sha1[CACHE_KEY_SIZE];
254 size_t tg_size = *((uint32_t *) ir_binary);
255
256 disk_cache_compute_key(sscreen->disk_shader_cache,
257 ir_binary, tg_size, sha1);
258
259 size_t binary_size;
260 uint8_t *buffer =
261 disk_cache_get(sscreen->disk_shader_cache,
262 sha1, &binary_size);
263 if (!buffer)
264 return false;
265
266 if (binary_size < sizeof(uint32_t) ||
267 *((uint32_t*)buffer) != binary_size) {
268 /* Something has gone wrong discard the item
269 * from the cache and rebuild/link from
270 * source.
271 */
272 assert(!"Invalid radeonsi shader disk cache "
273 "item!");
274
275 disk_cache_remove(sscreen->disk_shader_cache,
276 sha1);
277 free(buffer);
278
279 return false;
280 }
281
282 if (!si_load_shader_binary(shader, buffer)) {
283 free(buffer);
284 return false;
285 }
286 free(buffer);
287
288 if (!si_shader_cache_insert_shader(sscreen, ir_binary,
289 shader, false))
290 FREE(ir_binary);
291 } else {
292 return false;
293 }
294 } else {
295 if (si_load_shader_binary(shader, entry->data))
296 FREE(ir_binary);
297 else
298 return false;
299 }
300 p_atomic_inc(&sscreen->num_shader_cache_hits);
301 return true;
302 }
303
304 static uint32_t si_shader_cache_key_hash(const void *key)
305 {
306 /* The first dword is the key size. */
307 return util_hash_crc32(key, *(uint32_t*)key);
308 }
309
310 static bool si_shader_cache_key_equals(const void *a, const void *b)
311 {
312 uint32_t *keya = (uint32_t*)a;
313 uint32_t *keyb = (uint32_t*)b;
314
315 /* The first dword is the key size. */
316 if (*keya != *keyb)
317 return false;
318
319 return memcmp(keya, keyb, *keya) == 0;
320 }
321
322 static void si_destroy_shader_cache_entry(struct hash_entry *entry)
323 {
324 FREE((void*)entry->key);
325 FREE(entry->data);
326 }
327
328 bool si_init_shader_cache(struct si_screen *sscreen)
329 {
330 (void) mtx_init(&sscreen->shader_cache_mutex, mtx_plain);
331 sscreen->shader_cache =
332 _mesa_hash_table_create(NULL,
333 si_shader_cache_key_hash,
334 si_shader_cache_key_equals);
335
336 return sscreen->shader_cache != NULL;
337 }
338
339 void si_destroy_shader_cache(struct si_screen *sscreen)
340 {
341 if (sscreen->shader_cache)
342 _mesa_hash_table_destroy(sscreen->shader_cache,
343 si_destroy_shader_cache_entry);
344 mtx_destroy(&sscreen->shader_cache_mutex);
345 }
346
347 /* SHADER STATES */
348
349 static void si_set_tesseval_regs(struct si_screen *sscreen,
350 const struct si_shader_selector *tes,
351 struct si_pm4_state *pm4)
352 {
353 const struct tgsi_shader_info *info = &tes->info;
354 unsigned tes_prim_mode = info->properties[TGSI_PROPERTY_TES_PRIM_MODE];
355 unsigned tes_spacing = info->properties[TGSI_PROPERTY_TES_SPACING];
356 bool tes_vertex_order_cw = info->properties[TGSI_PROPERTY_TES_VERTEX_ORDER_CW];
357 bool tes_point_mode = info->properties[TGSI_PROPERTY_TES_POINT_MODE];
358 unsigned type, partitioning, topology, distribution_mode;
359
360 switch (tes_prim_mode) {
361 case PIPE_PRIM_LINES:
362 type = V_028B6C_TESS_ISOLINE;
363 break;
364 case PIPE_PRIM_TRIANGLES:
365 type = V_028B6C_TESS_TRIANGLE;
366 break;
367 case PIPE_PRIM_QUADS:
368 type = V_028B6C_TESS_QUAD;
369 break;
370 default:
371 assert(0);
372 return;
373 }
374
375 switch (tes_spacing) {
376 case PIPE_TESS_SPACING_FRACTIONAL_ODD:
377 partitioning = V_028B6C_PART_FRAC_ODD;
378 break;
379 case PIPE_TESS_SPACING_FRACTIONAL_EVEN:
380 partitioning = V_028B6C_PART_FRAC_EVEN;
381 break;
382 case PIPE_TESS_SPACING_EQUAL:
383 partitioning = V_028B6C_PART_INTEGER;
384 break;
385 default:
386 assert(0);
387 return;
388 }
389
390 if (tes_point_mode)
391 topology = V_028B6C_OUTPUT_POINT;
392 else if (tes_prim_mode == PIPE_PRIM_LINES)
393 topology = V_028B6C_OUTPUT_LINE;
394 else if (tes_vertex_order_cw)
395 /* for some reason, this must be the other way around */
396 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
397 else
398 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
399
400 if (sscreen->info.has_distributed_tess) {
401 if (sscreen->info.family == CHIP_FIJI ||
402 sscreen->info.family >= CHIP_POLARIS10)
403 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
404 else
405 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
406 } else
407 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
408
409 assert(pm4->shader);
410 pm4->shader->vgt_tf_param = S_028B6C_TYPE(type) |
411 S_028B6C_PARTITIONING(partitioning) |
412 S_028B6C_TOPOLOGY(topology) |
413 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
414 }
415
416 /* Polaris needs different VTX_REUSE_DEPTH settings depending on
417 * whether the "fractional odd" tessellation spacing is used.
418 *
419 * Possible VGT configurations and which state should set the register:
420 *
421 * Reg set in | VGT shader configuration | Value
422 * ------------------------------------------------------
423 * VS as VS | VS | 30
424 * VS as ES | ES -> GS -> VS | 30
425 * TES as VS | LS -> HS -> VS | 14 or 30
426 * TES as ES | LS -> HS -> ES -> GS -> VS | 14 or 30
427 *
428 * If "shader" is NULL, it's assumed it's not LS or GS copy shader.
429 */
430 static void polaris_set_vgt_vertex_reuse(struct si_screen *sscreen,
431 struct si_shader_selector *sel,
432 struct si_shader *shader,
433 struct si_pm4_state *pm4)
434 {
435 unsigned type = sel->type;
436
437 if (sscreen->info.family < CHIP_POLARIS10 ||
438 sscreen->info.chip_class >= GFX10)
439 return;
440
441 /* VS as VS, or VS as ES: */
442 if ((type == PIPE_SHADER_VERTEX &&
443 (!shader ||
444 (!shader->key.as_ls && !shader->is_gs_copy_shader))) ||
445 /* TES as VS, or TES as ES: */
446 type == PIPE_SHADER_TESS_EVAL) {
447 unsigned vtx_reuse_depth = 30;
448
449 if (type == PIPE_SHADER_TESS_EVAL &&
450 sel->info.properties[TGSI_PROPERTY_TES_SPACING] ==
451 PIPE_TESS_SPACING_FRACTIONAL_ODD)
452 vtx_reuse_depth = 14;
453
454 assert(pm4->shader);
455 pm4->shader->vgt_vertex_reuse_block_cntl = vtx_reuse_depth;
456 }
457 }
458
459 static struct si_pm4_state *si_get_shader_pm4_state(struct si_shader *shader)
460 {
461 if (shader->pm4)
462 si_pm4_clear_state(shader->pm4);
463 else
464 shader->pm4 = CALLOC_STRUCT(si_pm4_state);
465
466 if (shader->pm4) {
467 shader->pm4->shader = shader;
468 return shader->pm4;
469 } else {
470 fprintf(stderr, "radeonsi: Failed to create pm4 state.\n");
471 return NULL;
472 }
473 }
474
475 static unsigned si_get_num_vs_user_sgprs(unsigned num_always_on_user_sgprs)
476 {
477 /* Add the pointer to VBO descriptors. */
478 return num_always_on_user_sgprs + 1;
479 }
480
481 static void si_shader_ls(struct si_screen *sscreen, struct si_shader *shader)
482 {
483 struct si_pm4_state *pm4;
484 unsigned vgpr_comp_cnt;
485 uint64_t va;
486
487 assert(sscreen->info.chip_class <= GFX8);
488
489 pm4 = si_get_shader_pm4_state(shader);
490 if (!pm4)
491 return;
492
493 va = shader->bo->gpu_address;
494 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
495
496 /* We need at least 2 components for LS.
497 * VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
498 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
499 */
500 vgpr_comp_cnt = shader->info.uses_instanceid ? 2 : 1;
501
502 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
503 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
504
505 shader->config.rsrc1 = S_00B528_VGPRS((shader->config.num_vgprs - 1) / 4) |
506 S_00B528_SGPRS((shader->config.num_sgprs - 1) / 8) |
507 S_00B528_VGPR_COMP_CNT(vgpr_comp_cnt) |
508 S_00B528_DX10_CLAMP(1) |
509 S_00B528_FLOAT_MODE(shader->config.float_mode);
510 shader->config.rsrc2 = S_00B52C_USER_SGPR(si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR)) |
511 S_00B52C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
512 }
513
514 static void si_shader_hs(struct si_screen *sscreen, struct si_shader *shader)
515 {
516 struct si_pm4_state *pm4;
517 uint64_t va;
518 unsigned ls_vgpr_comp_cnt = 0;
519
520 pm4 = si_get_shader_pm4_state(shader);
521 if (!pm4)
522 return;
523
524 va = shader->bo->gpu_address;
525 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
526
527 if (sscreen->info.chip_class >= GFX9) {
528 if (sscreen->info.chip_class >= GFX10) {
529 si_pm4_set_reg(pm4, R_00B520_SPI_SHADER_PGM_LO_LS, va >> 8);
530 si_pm4_set_reg(pm4, R_00B524_SPI_SHADER_PGM_HI_LS, S_00B524_MEM_BASE(va >> 40));
531 } else {
532 si_pm4_set_reg(pm4, R_00B410_SPI_SHADER_PGM_LO_LS, va >> 8);
533 si_pm4_set_reg(pm4, R_00B414_SPI_SHADER_PGM_HI_LS, S_00B414_MEM_BASE(va >> 40));
534 }
535
536 /* We need at least 2 components for LS.
537 * GFX9 VGPR0-3: (VertexID, RelAutoindex, InstanceID / StepRate0, InstanceID).
538 * GFX10 VGPR0-3: (VertexID, RelAutoindex, UserVGPR1, InstanceID).
539 * On gfx9, StepRate0 is set to 1 so that VGPR3 doesn't have to
540 * be loaded.
541 */
542 ls_vgpr_comp_cnt = 1;
543 if (shader->info.uses_instanceid) {
544 if (sscreen->info.chip_class >= GFX10)
545 ls_vgpr_comp_cnt = 3;
546 else
547 ls_vgpr_comp_cnt = 2;
548 }
549
550 unsigned num_user_sgprs =
551 si_get_num_vs_user_sgprs(GFX9_TCS_NUM_USER_SGPR);
552
553 shader->config.rsrc2 =
554 S_00B42C_USER_SGPR(num_user_sgprs) |
555 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
556
557 if (sscreen->info.chip_class >= GFX10)
558 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
559 else
560 shader->config.rsrc2 |= S_00B42C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
561 } else {
562 si_pm4_set_reg(pm4, R_00B420_SPI_SHADER_PGM_LO_HS, va >> 8);
563 si_pm4_set_reg(pm4, R_00B424_SPI_SHADER_PGM_HI_HS, S_00B424_MEM_BASE(va >> 40));
564
565 shader->config.rsrc2 =
566 S_00B42C_USER_SGPR(GFX6_TCS_NUM_USER_SGPR) |
567 S_00B42C_OC_LDS_EN(1) |
568 S_00B42C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
569 }
570
571 si_pm4_set_reg(pm4, R_00B428_SPI_SHADER_PGM_RSRC1_HS,
572 S_00B428_VGPRS((shader->config.num_vgprs - 1) /
573 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
574 (sscreen->info.chip_class <= GFX9 ?
575 S_00B428_SGPRS((shader->config.num_sgprs - 1) / 8) : 0) |
576 S_00B428_DX10_CLAMP(1) |
577 S_00B428_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
578 S_00B428_WGP_MODE(sscreen->info.chip_class >= GFX10) |
579 S_00B428_FLOAT_MODE(shader->config.float_mode) |
580 S_00B428_LS_VGPR_COMP_CNT(ls_vgpr_comp_cnt));
581
582 if (sscreen->info.chip_class <= GFX8) {
583 si_pm4_set_reg(pm4, R_00B42C_SPI_SHADER_PGM_RSRC2_HS,
584 shader->config.rsrc2);
585 }
586 }
587
588 static void si_emit_shader_es(struct si_context *sctx)
589 {
590 struct si_shader *shader = sctx->queued.named.es->shader;
591 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
592
593 if (!shader)
594 return;
595
596 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
597 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
598 shader->selector->esgs_itemsize / 4);
599
600 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
601 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
602 SI_TRACKED_VGT_TF_PARAM,
603 shader->vgt_tf_param);
604
605 if (shader->vgt_vertex_reuse_block_cntl)
606 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
607 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
608 shader->vgt_vertex_reuse_block_cntl);
609
610 if (initial_cdw != sctx->gfx_cs->current.cdw)
611 sctx->context_roll = true;
612 }
613
614 static void si_shader_es(struct si_screen *sscreen, struct si_shader *shader)
615 {
616 struct si_pm4_state *pm4;
617 unsigned num_user_sgprs;
618 unsigned vgpr_comp_cnt;
619 uint64_t va;
620 unsigned oc_lds_en;
621
622 assert(sscreen->info.chip_class <= GFX8);
623
624 pm4 = si_get_shader_pm4_state(shader);
625 if (!pm4)
626 return;
627
628 pm4->atom.emit = si_emit_shader_es;
629 va = shader->bo->gpu_address;
630 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
631
632 if (shader->selector->type == PIPE_SHADER_VERTEX) {
633 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
634 vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
635 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
636 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
637 vgpr_comp_cnt = shader->selector->info.uses_primid ? 3 : 2;
638 num_user_sgprs = SI_TES_NUM_USER_SGPR;
639 } else
640 unreachable("invalid shader selector type");
641
642 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
643
644 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
645 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
646 si_pm4_set_reg(pm4, R_00B328_SPI_SHADER_PGM_RSRC1_ES,
647 S_00B328_VGPRS((shader->config.num_vgprs - 1) / 4) |
648 S_00B328_SGPRS((shader->config.num_sgprs - 1) / 8) |
649 S_00B328_VGPR_COMP_CNT(vgpr_comp_cnt) |
650 S_00B328_DX10_CLAMP(1) |
651 S_00B328_FLOAT_MODE(shader->config.float_mode));
652 si_pm4_set_reg(pm4, R_00B32C_SPI_SHADER_PGM_RSRC2_ES,
653 S_00B32C_USER_SGPR(num_user_sgprs) |
654 S_00B32C_OC_LDS_EN(oc_lds_en) |
655 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
656
657 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
658 si_set_tesseval_regs(sscreen, shader->selector, pm4);
659
660 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
661 }
662
663 void gfx9_get_gs_info(struct si_shader_selector *es,
664 struct si_shader_selector *gs,
665 struct gfx9_gs_info *out)
666 {
667 unsigned gs_num_invocations = MAX2(gs->gs_num_invocations, 1);
668 unsigned input_prim = gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
669 bool uses_adjacency = input_prim >= PIPE_PRIM_LINES_ADJACENCY &&
670 input_prim <= PIPE_PRIM_TRIANGLE_STRIP_ADJACENCY;
671
672 /* All these are in dwords: */
673 /* We can't allow using the whole LDS, because GS waves compete with
674 * other shader stages for LDS space. */
675 const unsigned max_lds_size = 8 * 1024;
676 const unsigned esgs_itemsize = es->esgs_itemsize / 4;
677 unsigned esgs_lds_size;
678
679 /* All these are per subgroup: */
680 const unsigned max_out_prims = 32 * 1024;
681 const unsigned max_es_verts = 255;
682 const unsigned ideal_gs_prims = 64;
683 unsigned max_gs_prims, gs_prims;
684 unsigned min_es_verts, es_verts, worst_case_es_verts;
685
686 if (uses_adjacency || gs_num_invocations > 1)
687 max_gs_prims = 127 / gs_num_invocations;
688 else
689 max_gs_prims = 255;
690
691 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
692 * Make sure we don't go over the maximum value.
693 */
694 if (gs->gs_max_out_vertices > 0) {
695 max_gs_prims = MIN2(max_gs_prims,
696 max_out_prims /
697 (gs->gs_max_out_vertices * gs_num_invocations));
698 }
699 assert(max_gs_prims > 0);
700
701 /* If the primitive has adjacency, halve the number of vertices
702 * that will be reused in multiple primitives.
703 */
704 min_es_verts = gs->gs_input_verts_per_prim / (uses_adjacency ? 2 : 1);
705
706 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
707 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
708
709 /* Compute ESGS LDS size based on the worst case number of ES vertices
710 * needed to create the target number of GS prims per subgroup.
711 */
712 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
713
714 /* If total LDS usage is too big, refactor partitions based on ratio
715 * of ESGS item sizes.
716 */
717 if (esgs_lds_size > max_lds_size) {
718 /* Our target GS Prims Per Subgroup was too large. Calculate
719 * the maximum number of GS Prims Per Subgroup that will fit
720 * into LDS, capped by the maximum that the hardware can support.
721 */
722 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
723 max_gs_prims);
724 assert(gs_prims > 0);
725 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
726 max_es_verts);
727
728 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
729 assert(esgs_lds_size <= max_lds_size);
730 }
731
732 /* Now calculate remaining ESGS information. */
733 if (esgs_lds_size)
734 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
735 else
736 es_verts = max_es_verts;
737
738 /* Vertices for adjacency primitives are not always reused, so restore
739 * it for ES_VERTS_PER_SUBGRP.
740 */
741 min_es_verts = gs->gs_input_verts_per_prim;
742
743 /* For normal primitives, the VGT only checks if they are past the ES
744 * verts per subgroup after allocating a full GS primitive and if they
745 * are, kick off a new subgroup. But if those additional ES verts are
746 * unique (e.g. not reused) we need to make sure there is enough LDS
747 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
748 */
749 es_verts -= min_es_verts - 1;
750
751 out->es_verts_per_subgroup = es_verts;
752 out->gs_prims_per_subgroup = gs_prims;
753 out->gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
754 out->max_prims_per_subgroup = out->gs_inst_prims_in_subgroup *
755 gs->gs_max_out_vertices;
756 out->esgs_ring_size = 4 * esgs_lds_size;
757
758 assert(out->max_prims_per_subgroup <= max_out_prims);
759 }
760
761 static void si_emit_shader_gs(struct si_context *sctx)
762 {
763 struct si_shader *shader = sctx->queued.named.gs->shader;
764 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
765
766 if (!shader)
767 return;
768
769 /* R_028A60_VGT_GSVS_RING_OFFSET_1, R_028A64_VGT_GSVS_RING_OFFSET_2
770 * R_028A68_VGT_GSVS_RING_OFFSET_3 */
771 radeon_opt_set_context_reg3(sctx, R_028A60_VGT_GSVS_RING_OFFSET_1,
772 SI_TRACKED_VGT_GSVS_RING_OFFSET_1,
773 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1,
774 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2,
775 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3);
776
777 /* R_028AB0_VGT_GSVS_RING_ITEMSIZE */
778 radeon_opt_set_context_reg(sctx, R_028AB0_VGT_GSVS_RING_ITEMSIZE,
779 SI_TRACKED_VGT_GSVS_RING_ITEMSIZE,
780 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize);
781
782 /* R_028B38_VGT_GS_MAX_VERT_OUT */
783 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
784 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
785 shader->ctx_reg.gs.vgt_gs_max_vert_out);
786
787 /* R_028B5C_VGT_GS_VERT_ITEMSIZE, R_028B60_VGT_GS_VERT_ITEMSIZE_1
788 * R_028B64_VGT_GS_VERT_ITEMSIZE_2, R_028B68_VGT_GS_VERT_ITEMSIZE_3 */
789 radeon_opt_set_context_reg4(sctx, R_028B5C_VGT_GS_VERT_ITEMSIZE,
790 SI_TRACKED_VGT_GS_VERT_ITEMSIZE,
791 shader->ctx_reg.gs.vgt_gs_vert_itemsize,
792 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1,
793 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2,
794 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3);
795
796 /* R_028B90_VGT_GS_INSTANCE_CNT */
797 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
798 SI_TRACKED_VGT_GS_INSTANCE_CNT,
799 shader->ctx_reg.gs.vgt_gs_instance_cnt);
800
801 if (sctx->chip_class >= GFX9) {
802 /* R_028A44_VGT_GS_ONCHIP_CNTL */
803 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
804 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
805 shader->ctx_reg.gs.vgt_gs_onchip_cntl);
806 /* R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP */
807 radeon_opt_set_context_reg(sctx, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
808 SI_TRACKED_VGT_GS_MAX_PRIMS_PER_SUBGROUP,
809 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup);
810 /* R_028AAC_VGT_ESGS_RING_ITEMSIZE */
811 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
812 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
813 shader->ctx_reg.gs.vgt_esgs_ring_itemsize);
814
815 if (shader->key.part.gs.es->type == PIPE_SHADER_TESS_EVAL)
816 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
817 SI_TRACKED_VGT_TF_PARAM,
818 shader->vgt_tf_param);
819 if (shader->vgt_vertex_reuse_block_cntl)
820 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
821 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
822 shader->vgt_vertex_reuse_block_cntl);
823 }
824
825 if (initial_cdw != sctx->gfx_cs->current.cdw)
826 sctx->context_roll = true;
827 }
828
829 static void si_shader_gs(struct si_screen *sscreen, struct si_shader *shader)
830 {
831 struct si_shader_selector *sel = shader->selector;
832 const ubyte *num_components = sel->info.num_stream_output_components;
833 unsigned gs_num_invocations = sel->gs_num_invocations;
834 struct si_pm4_state *pm4;
835 uint64_t va;
836 unsigned max_stream = sel->max_gs_stream;
837 unsigned offset;
838
839 pm4 = si_get_shader_pm4_state(shader);
840 if (!pm4)
841 return;
842
843 pm4->atom.emit = si_emit_shader_gs;
844
845 offset = num_components[0] * sel->gs_max_out_vertices;
846 shader->ctx_reg.gs.vgt_gsvs_ring_offset_1 = offset;
847
848 if (max_stream >= 1)
849 offset += num_components[1] * sel->gs_max_out_vertices;
850 shader->ctx_reg.gs.vgt_gsvs_ring_offset_2 = offset;
851
852 if (max_stream >= 2)
853 offset += num_components[2] * sel->gs_max_out_vertices;
854 shader->ctx_reg.gs.vgt_gsvs_ring_offset_3 = offset;
855
856 if (max_stream >= 3)
857 offset += num_components[3] * sel->gs_max_out_vertices;
858 shader->ctx_reg.gs.vgt_gsvs_ring_itemsize = offset;
859
860 /* The GSVS_RING_ITEMSIZE register takes 15 bits */
861 assert(offset < (1 << 15));
862
863 shader->ctx_reg.gs.vgt_gs_max_vert_out = sel->gs_max_out_vertices;
864
865 shader->ctx_reg.gs.vgt_gs_vert_itemsize = num_components[0];
866 shader->ctx_reg.gs.vgt_gs_vert_itemsize_1 = (max_stream >= 1) ? num_components[1] : 0;
867 shader->ctx_reg.gs.vgt_gs_vert_itemsize_2 = (max_stream >= 2) ? num_components[2] : 0;
868 shader->ctx_reg.gs.vgt_gs_vert_itemsize_3 = (max_stream >= 3) ? num_components[3] : 0;
869
870 shader->ctx_reg.gs.vgt_gs_instance_cnt = S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
871 S_028B90_ENABLE(gs_num_invocations > 0);
872
873 va = shader->bo->gpu_address;
874 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
875
876 if (sscreen->info.chip_class >= GFX9) {
877 unsigned input_prim = sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
878 unsigned es_type = shader->key.part.gs.es->type;
879 unsigned es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
880
881 if (es_type == PIPE_SHADER_VERTEX)
882 /* VGPR0-3: (VertexID, InstanceID / StepRate0, ...) */
883 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 1 : 0;
884 else if (es_type == PIPE_SHADER_TESS_EVAL)
885 es_vgpr_comp_cnt = shader->key.part.gs.es->info.uses_primid ? 3 : 2;
886 else
887 unreachable("invalid shader selector type");
888
889 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
890 * VGPR[0:4] are always loaded.
891 */
892 if (sel->info.uses_invocationid)
893 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID. */
894 else if (sel->info.uses_primid)
895 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
896 else if (input_prim >= PIPE_PRIM_TRIANGLES)
897 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
898 else
899 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
900
901 unsigned num_user_sgprs;
902 if (es_type == PIPE_SHADER_VERTEX)
903 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
904 else
905 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
906
907 if (sscreen->info.chip_class >= GFX10) {
908 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
909 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, S_00B324_MEM_BASE(va >> 40));
910 } else {
911 si_pm4_set_reg(pm4, R_00B210_SPI_SHADER_PGM_LO_ES, va >> 8);
912 si_pm4_set_reg(pm4, R_00B214_SPI_SHADER_PGM_HI_ES, S_00B214_MEM_BASE(va >> 40));
913 }
914
915 uint32_t rsrc1 =
916 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
917 S_00B228_DX10_CLAMP(1) |
918 S_00B228_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
919 S_00B228_WGP_MODE(sscreen->info.chip_class >= GFX10) |
920 S_00B228_FLOAT_MODE(shader->config.float_mode) |
921 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt);
922 uint32_t rsrc2 =
923 S_00B22C_USER_SGPR(num_user_sgprs) |
924 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
925 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
926 S_00B22C_LDS_SIZE(shader->config.lds_size) |
927 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
928
929 if (sscreen->info.chip_class >= GFX10) {
930 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5);
931 } else {
932 rsrc1 |= S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8);
933 rsrc2 |= S_00B22C_USER_SGPR_MSB_GFX9(num_user_sgprs >> 5);
934 }
935
936 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS, rsrc1);
937 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS, rsrc2);
938
939 shader->ctx_reg.gs.vgt_gs_onchip_cntl =
940 S_028A44_ES_VERTS_PER_SUBGRP(shader->gs_info.es_verts_per_subgroup) |
941 S_028A44_GS_PRIMS_PER_SUBGRP(shader->gs_info.gs_prims_per_subgroup) |
942 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->gs_info.gs_inst_prims_in_subgroup);
943 shader->ctx_reg.gs.vgt_gs_max_prims_per_subgroup =
944 S_028A94_MAX_PRIMS_PER_SUBGROUP(shader->gs_info.max_prims_per_subgroup);
945 shader->ctx_reg.gs.vgt_esgs_ring_itemsize =
946 shader->key.part.gs.es->esgs_itemsize / 4;
947
948 if (es_type == PIPE_SHADER_TESS_EVAL)
949 si_set_tesseval_regs(sscreen, shader->key.part.gs.es, pm4);
950
951 polaris_set_vgt_vertex_reuse(sscreen, shader->key.part.gs.es,
952 NULL, pm4);
953 } else {
954 si_pm4_set_reg(pm4, R_00B220_SPI_SHADER_PGM_LO_GS, va >> 8);
955 si_pm4_set_reg(pm4, R_00B224_SPI_SHADER_PGM_HI_GS, S_00B224_MEM_BASE(va >> 40));
956
957 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
958 S_00B228_VGPRS((shader->config.num_vgprs - 1) / 4) |
959 S_00B228_SGPRS((shader->config.num_sgprs - 1) / 8) |
960 S_00B228_DX10_CLAMP(1) |
961 S_00B228_FLOAT_MODE(shader->config.float_mode));
962 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
963 S_00B22C_USER_SGPR(GFX6_GS_NUM_USER_SGPR) |
964 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
965 }
966 }
967
968 /* Common tail code for NGG primitive shaders. */
969 static void gfx10_emit_shader_ngg_tail(struct si_context *sctx,
970 struct si_shader *shader,
971 unsigned initial_cdw)
972 {
973 radeon_opt_set_context_reg(sctx, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
974 SI_TRACKED_GE_MAX_OUTPUT_PER_SUBGROUP,
975 shader->ctx_reg.ngg.ge_max_output_per_subgroup);
976 radeon_opt_set_context_reg(sctx, R_028B4C_GE_NGG_SUBGRP_CNTL,
977 SI_TRACKED_GE_NGG_SUBGRP_CNTL,
978 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl);
979 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
980 SI_TRACKED_VGT_PRIMITIVEID_EN,
981 shader->ctx_reg.ngg.vgt_primitiveid_en);
982 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
983 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
984 shader->ctx_reg.ngg.vgt_gs_onchip_cntl);
985 radeon_opt_set_context_reg(sctx, R_028B90_VGT_GS_INSTANCE_CNT,
986 SI_TRACKED_VGT_GS_INSTANCE_CNT,
987 shader->ctx_reg.ngg.vgt_gs_instance_cnt);
988 radeon_opt_set_context_reg(sctx, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
989 SI_TRACKED_VGT_ESGS_RING_ITEMSIZE,
990 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize);
991 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
992 SI_TRACKED_SPI_VS_OUT_CONFIG,
993 shader->ctx_reg.ngg.spi_vs_out_config);
994 radeon_opt_set_context_reg2(sctx, R_028708_SPI_SHADER_IDX_FORMAT,
995 SI_TRACKED_SPI_SHADER_IDX_FORMAT,
996 shader->ctx_reg.ngg.spi_shader_idx_format,
997 shader->ctx_reg.ngg.spi_shader_pos_format);
998 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
999 SI_TRACKED_PA_CL_VTE_CNTL,
1000 shader->ctx_reg.ngg.pa_cl_vte_cntl);
1001 radeon_opt_set_context_reg(sctx, R_028838_PA_CL_NGG_CNTL,
1002 SI_TRACKED_PA_CL_NGG_CNTL,
1003 shader->ctx_reg.ngg.pa_cl_ngg_cntl);
1004
1005 if (initial_cdw != sctx->gfx_cs->current.cdw)
1006 sctx->context_roll = true;
1007 }
1008
1009 static void gfx10_emit_shader_ngg_notess_nogs(struct si_context *sctx)
1010 {
1011 struct si_shader *shader = sctx->queued.named.gs->shader;
1012 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1013
1014 if (!shader)
1015 return;
1016
1017 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1018 }
1019
1020 static void gfx10_emit_shader_ngg_tess_nogs(struct si_context *sctx)
1021 {
1022 struct si_shader *shader = sctx->queued.named.gs->shader;
1023 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1024
1025 if (!shader)
1026 return;
1027
1028 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1029 SI_TRACKED_VGT_TF_PARAM,
1030 shader->vgt_tf_param);
1031
1032 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1033 }
1034
1035 static void gfx10_emit_shader_ngg_notess_gs(struct si_context *sctx)
1036 {
1037 struct si_shader *shader = sctx->queued.named.gs->shader;
1038 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1039
1040 if (!shader)
1041 return;
1042
1043 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1044 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1045 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1046
1047 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1048 }
1049
1050 static void gfx10_emit_shader_ngg_tess_gs(struct si_context *sctx)
1051 {
1052 struct si_shader *shader = sctx->queued.named.gs->shader;
1053 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1054
1055 if (!shader)
1056 return;
1057
1058 radeon_opt_set_context_reg(sctx, R_028B38_VGT_GS_MAX_VERT_OUT,
1059 SI_TRACKED_VGT_GS_MAX_VERT_OUT,
1060 shader->ctx_reg.ngg.vgt_gs_max_vert_out);
1061 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1062 SI_TRACKED_VGT_TF_PARAM,
1063 shader->vgt_tf_param);
1064
1065 gfx10_emit_shader_ngg_tail(sctx, shader, initial_cdw);
1066 }
1067
1068 unsigned si_get_input_prim(const struct si_shader_selector *gs)
1069 {
1070 if (gs->type == PIPE_SHADER_GEOMETRY)
1071 return gs->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM];
1072
1073 if (gs->type == PIPE_SHADER_TESS_EVAL) {
1074 if (gs->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
1075 return PIPE_PRIM_POINTS;
1076 if (gs->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
1077 return PIPE_PRIM_LINES;
1078 return PIPE_PRIM_TRIANGLES;
1079 }
1080
1081 /* TODO: Set this correctly if the primitive type is set in the shader key. */
1082 return PIPE_PRIM_TRIANGLES; /* worst case for all callers */
1083 }
1084
1085 /**
1086 * Prepare the PM4 image for \p shader, which will run as a merged ESGS shader
1087 * in NGG mode.
1088 */
1089 static void gfx10_shader_ngg(struct si_screen *sscreen, struct si_shader *shader)
1090 {
1091 const struct si_shader_selector *gs_sel = shader->selector;
1092 const struct tgsi_shader_info *gs_info = &gs_sel->info;
1093 enum pipe_shader_type gs_type = shader->selector->type;
1094 const struct si_shader_selector *es_sel =
1095 shader->previous_stage_sel ? shader->previous_stage_sel : shader->selector;
1096 const struct tgsi_shader_info *es_info = &es_sel->info;
1097 enum pipe_shader_type es_type = es_sel->type;
1098 unsigned num_user_sgprs;
1099 unsigned nparams, es_vgpr_comp_cnt, gs_vgpr_comp_cnt;
1100 uint64_t va;
1101 unsigned window_space =
1102 gs_info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1103 bool es_enable_prim_id = shader->key.mono.u.vs_export_prim_id || es_info->uses_primid;
1104 unsigned gs_num_invocations = MAX2(gs_sel->gs_num_invocations, 1);
1105 unsigned input_prim = si_get_input_prim(gs_sel);
1106 bool break_wave_at_eoi = false;
1107 struct si_pm4_state *pm4 = si_get_shader_pm4_state(shader);
1108 if (!pm4)
1109 return;
1110
1111 if (es_type == PIPE_SHADER_TESS_EVAL) {
1112 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_tess_gs
1113 : gfx10_emit_shader_ngg_tess_nogs;
1114 } else {
1115 pm4->atom.emit = gs_type == PIPE_SHADER_GEOMETRY ? gfx10_emit_shader_ngg_notess_gs
1116 : gfx10_emit_shader_ngg_notess_nogs;
1117 }
1118
1119 va = shader->bo->gpu_address;
1120 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1121
1122 if (es_type == PIPE_SHADER_VERTEX) {
1123 /* VGPR5-8: (VertexID, UserVGPR0, UserVGPR1, UserVGPR2 / InstanceID) */
1124 es_vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : 0;
1125
1126 if (es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1127 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1128 es_info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1129 } else {
1130 num_user_sgprs = si_get_num_vs_user_sgprs(GFX9_VSGS_NUM_USER_SGPR);
1131 }
1132 } else {
1133 assert(es_type == PIPE_SHADER_TESS_EVAL);
1134 es_vgpr_comp_cnt = es_enable_prim_id ? 3 : 2;
1135 num_user_sgprs = GFX9_TESGS_NUM_USER_SGPR;
1136
1137 if (es_enable_prim_id || gs_info->uses_primid)
1138 break_wave_at_eoi = true;
1139 }
1140
1141 /* If offsets 4, 5 are used, GS_VGPR_COMP_CNT is ignored and
1142 * VGPR[0:4] are always loaded.
1143 *
1144 * Vertex shaders always need to load VGPR3, because they need to
1145 * pass edge flags for decomposed primitives (such as quads) to the PA
1146 * for the GL_LINE polygon mode to skip rendering lines on inner edges.
1147 */
1148 if (gs_info->uses_invocationid || gs_type == PIPE_SHADER_VERTEX)
1149 gs_vgpr_comp_cnt = 3; /* VGPR3 contains InvocationID, edge flags. */
1150 else if (gs_info->uses_primid)
1151 gs_vgpr_comp_cnt = 2; /* VGPR2 contains PrimitiveID. */
1152 else if (input_prim >= PIPE_PRIM_TRIANGLES)
1153 gs_vgpr_comp_cnt = 1; /* VGPR1 contains offsets 2, 3 */
1154 else
1155 gs_vgpr_comp_cnt = 0; /* VGPR0 contains offsets 0, 1 */
1156
1157 si_pm4_set_reg(pm4, R_00B320_SPI_SHADER_PGM_LO_ES, va >> 8);
1158 si_pm4_set_reg(pm4, R_00B324_SPI_SHADER_PGM_HI_ES, va >> 40);
1159 si_pm4_set_reg(pm4, R_00B228_SPI_SHADER_PGM_RSRC1_GS,
1160 S_00B228_VGPRS((shader->config.num_vgprs - 1) /
1161 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1162 S_00B228_FLOAT_MODE(shader->config.float_mode) |
1163 S_00B228_DX10_CLAMP(1) |
1164 S_00B228_MEM_ORDERED(1) |
1165 S_00B228_WGP_MODE(1) |
1166 S_00B228_GS_VGPR_COMP_CNT(gs_vgpr_comp_cnt));
1167 si_pm4_set_reg(pm4, R_00B22C_SPI_SHADER_PGM_RSRC2_GS,
1168 S_00B22C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0) |
1169 S_00B22C_USER_SGPR(num_user_sgprs) |
1170 S_00B22C_ES_VGPR_COMP_CNT(es_vgpr_comp_cnt) |
1171 S_00B22C_USER_SGPR_MSB_GFX10(num_user_sgprs >> 5) |
1172 S_00B22C_OC_LDS_EN(es_type == PIPE_SHADER_TESS_EVAL) |
1173 S_00B22C_LDS_SIZE(shader->config.lds_size));
1174
1175 nparams = MAX2(shader->info.nr_param_exports, 1);
1176 shader->ctx_reg.ngg.spi_vs_out_config =
1177 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
1178 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1179
1180 shader->ctx_reg.ngg.spi_shader_idx_format =
1181 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP);
1182 shader->ctx_reg.ngg.spi_shader_pos_format =
1183 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1184 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1185 V_02870C_SPI_SHADER_4COMP :
1186 V_02870C_SPI_SHADER_NONE) |
1187 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1188 V_02870C_SPI_SHADER_4COMP :
1189 V_02870C_SPI_SHADER_NONE) |
1190 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1191 V_02870C_SPI_SHADER_4COMP :
1192 V_02870C_SPI_SHADER_NONE);
1193
1194 shader->ctx_reg.ngg.vgt_primitiveid_en =
1195 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
1196 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id);
1197
1198 if (gs_type == PIPE_SHADER_GEOMETRY) {
1199 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = es_sel->esgs_itemsize / 4;
1200 shader->ctx_reg.ngg.vgt_gs_max_vert_out = gs_sel->gs_max_out_vertices;
1201 } else {
1202 shader->ctx_reg.ngg.vgt_esgs_ring_itemsize = 1;
1203 }
1204
1205 if (es_type == PIPE_SHADER_TESS_EVAL)
1206 si_set_tesseval_regs(sscreen, es_sel, pm4);
1207
1208 shader->ctx_reg.ngg.vgt_gs_onchip_cntl =
1209 S_028A44_ES_VERTS_PER_SUBGRP(shader->ngg.hw_max_esverts) |
1210 S_028A44_GS_PRIMS_PER_SUBGRP(shader->ngg.max_gsprims) |
1211 S_028A44_GS_INST_PRIMS_IN_SUBGRP(shader->ngg.max_gsprims * gs_num_invocations);
1212 shader->ctx_reg.ngg.ge_max_output_per_subgroup =
1213 S_0287FC_MAX_VERTS_PER_SUBGROUP(shader->ngg.max_out_verts);
1214 shader->ctx_reg.ngg.ge_ngg_subgrp_cntl =
1215 S_028B4C_PRIM_AMP_FACTOR(shader->ngg.prim_amp_factor) |
1216 S_028B4C_THDS_PER_SUBGRP(0); /* for fast launch */
1217 shader->ctx_reg.ngg.vgt_gs_instance_cnt =
1218 S_028B90_CNT(gs_num_invocations) |
1219 S_028B90_ENABLE(gs_num_invocations > 1) |
1220 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(
1221 shader->ngg.max_vert_out_per_gs_instance);
1222
1223 /* Always output hw-generated edge flags and pass them via the prim
1224 * export to prevent drawing lines on internal edges of decomposed
1225 * primitives (such as quads) with polygon mode = lines. Only VS needs
1226 * this.
1227 */
1228 shader->ctx_reg.ngg.pa_cl_ngg_cntl =
1229 S_028838_INDEX_BUF_EDGE_FLAG_ENA(gs_type == PIPE_SHADER_VERTEX);
1230
1231 shader->ge_cntl =
1232 S_03096C_PRIM_GRP_SIZE(shader->ngg.max_gsprims) |
1233 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts) |
1234 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
1235
1236 /* Bug workaround for a possible hang with non-tessellation cases.
1237 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
1238 *
1239 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
1240 */
1241 if ((sscreen->info.family == CHIP_NAVI10 ||
1242 sscreen->info.family == CHIP_NAVI12 ||
1243 sscreen->info.family == CHIP_NAVI14) &&
1244 (es_type == PIPE_SHADER_VERTEX || gs_type == PIPE_SHADER_VERTEX) && /* = no tess */
1245 shader->ngg.hw_max_esverts != 256) {
1246 shader->ge_cntl &= C_03096C_VERT_GRP_SIZE;
1247
1248 if (shader->ngg.hw_max_esverts > 5) {
1249 shader->ge_cntl |=
1250 S_03096C_VERT_GRP_SIZE(shader->ngg.hw_max_esverts - 5);
1251 }
1252 }
1253
1254 if (window_space) {
1255 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1256 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1257 } else {
1258 shader->ctx_reg.ngg.pa_cl_vte_cntl =
1259 S_028818_VTX_W0_FMT(1) |
1260 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1261 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1262 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1263 }
1264 }
1265
1266 static void si_emit_shader_vs(struct si_context *sctx)
1267 {
1268 struct si_shader *shader = sctx->queued.named.vs->shader;
1269 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1270
1271 if (!shader)
1272 return;
1273
1274 radeon_opt_set_context_reg(sctx, R_028A40_VGT_GS_MODE,
1275 SI_TRACKED_VGT_GS_MODE,
1276 shader->ctx_reg.vs.vgt_gs_mode);
1277 radeon_opt_set_context_reg(sctx, R_028A84_VGT_PRIMITIVEID_EN,
1278 SI_TRACKED_VGT_PRIMITIVEID_EN,
1279 shader->ctx_reg.vs.vgt_primitiveid_en);
1280
1281 if (sctx->chip_class <= GFX8) {
1282 radeon_opt_set_context_reg(sctx, R_028AB4_VGT_REUSE_OFF,
1283 SI_TRACKED_VGT_REUSE_OFF,
1284 shader->ctx_reg.vs.vgt_reuse_off);
1285 }
1286
1287 radeon_opt_set_context_reg(sctx, R_0286C4_SPI_VS_OUT_CONFIG,
1288 SI_TRACKED_SPI_VS_OUT_CONFIG,
1289 shader->ctx_reg.vs.spi_vs_out_config);
1290
1291 radeon_opt_set_context_reg(sctx, R_02870C_SPI_SHADER_POS_FORMAT,
1292 SI_TRACKED_SPI_SHADER_POS_FORMAT,
1293 shader->ctx_reg.vs.spi_shader_pos_format);
1294
1295 radeon_opt_set_context_reg(sctx, R_028818_PA_CL_VTE_CNTL,
1296 SI_TRACKED_PA_CL_VTE_CNTL,
1297 shader->ctx_reg.vs.pa_cl_vte_cntl);
1298
1299 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1300 radeon_opt_set_context_reg(sctx, R_028B6C_VGT_TF_PARAM,
1301 SI_TRACKED_VGT_TF_PARAM,
1302 shader->vgt_tf_param);
1303
1304 if (shader->vgt_vertex_reuse_block_cntl)
1305 radeon_opt_set_context_reg(sctx, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
1306 SI_TRACKED_VGT_VERTEX_REUSE_BLOCK_CNTL,
1307 shader->vgt_vertex_reuse_block_cntl);
1308
1309 if (initial_cdw != sctx->gfx_cs->current.cdw)
1310 sctx->context_roll = true;
1311
1312 /* Required programming for tessellation. (legacy pipeline only) */
1313 if (sctx->chip_class == GFX10 &&
1314 shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1315 radeon_opt_set_context_reg(sctx, R_028A44_VGT_GS_ONCHIP_CNTL,
1316 SI_TRACKED_VGT_GS_ONCHIP_CNTL,
1317 S_028A44_ES_VERTS_PER_SUBGRP(250) |
1318 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
1319 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
1320 }
1321 }
1322
1323 /**
1324 * Compute the state for \p shader, which will run as a vertex shader on the
1325 * hardware.
1326 *
1327 * If \p gs is non-NULL, it points to the geometry shader for which this shader
1328 * is the copy shader.
1329 */
1330 static void si_shader_vs(struct si_screen *sscreen, struct si_shader *shader,
1331 struct si_shader_selector *gs)
1332 {
1333 const struct tgsi_shader_info *info = &shader->selector->info;
1334 struct si_pm4_state *pm4;
1335 unsigned num_user_sgprs, vgpr_comp_cnt;
1336 uint64_t va;
1337 unsigned nparams, oc_lds_en;
1338 unsigned window_space =
1339 info->properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION];
1340 bool enable_prim_id = shader->key.mono.u.vs_export_prim_id || info->uses_primid;
1341
1342 pm4 = si_get_shader_pm4_state(shader);
1343 if (!pm4)
1344 return;
1345
1346 pm4->atom.emit = si_emit_shader_vs;
1347
1348 /* We always write VGT_GS_MODE in the VS state, because every switch
1349 * between different shader pipelines involving a different GS or no
1350 * GS at all involves a switch of the VS (different GS use different
1351 * copy shaders). On the other hand, when the API switches from a GS to
1352 * no GS and then back to the same GS used originally, the GS state is
1353 * not sent again.
1354 */
1355 if (!gs) {
1356 unsigned mode = V_028A40_GS_OFF;
1357
1358 /* PrimID needs GS scenario A. */
1359 if (enable_prim_id)
1360 mode = V_028A40_GS_SCENARIO_A;
1361
1362 shader->ctx_reg.vs.vgt_gs_mode = S_028A40_MODE(mode);
1363 shader->ctx_reg.vs.vgt_primitiveid_en = enable_prim_id;
1364 } else {
1365 shader->ctx_reg.vs.vgt_gs_mode = ac_vgt_gs_mode(gs->gs_max_out_vertices,
1366 sscreen->info.chip_class);
1367 shader->ctx_reg.vs.vgt_primitiveid_en = 0;
1368 }
1369
1370 if (sscreen->info.chip_class <= GFX8) {
1371 /* Reuse needs to be set off if we write oViewport. */
1372 shader->ctx_reg.vs.vgt_reuse_off =
1373 S_028AB4_REUSE_OFF(info->writes_viewport_index);
1374 }
1375
1376 va = shader->bo->gpu_address;
1377 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1378
1379 if (gs) {
1380 vgpr_comp_cnt = 0; /* only VertexID is needed for GS-COPY. */
1381 num_user_sgprs = SI_GSCOPY_NUM_USER_SGPR;
1382 } else if (shader->selector->type == PIPE_SHADER_VERTEX) {
1383 if (sscreen->info.chip_class >= GFX10) {
1384 vgpr_comp_cnt = shader->info.uses_instanceid ? 3 : (enable_prim_id ? 2 : 0);
1385 } else {
1386 /* VGPR0-3: (VertexID, InstanceID / StepRate0, PrimID, InstanceID)
1387 * If PrimID is disabled. InstanceID / StepRate1 is loaded instead.
1388 * StepRate0 is set to 1. so that VGPR3 doesn't have to be loaded.
1389 */
1390 vgpr_comp_cnt = enable_prim_id ? 2 : (shader->info.uses_instanceid ? 1 : 0);
1391 }
1392
1393 if (info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD]) {
1394 num_user_sgprs = SI_SGPR_VS_BLIT_DATA +
1395 info->properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
1396 } else {
1397 num_user_sgprs = si_get_num_vs_user_sgprs(SI_VS_NUM_USER_SGPR);
1398 }
1399 } else if (shader->selector->type == PIPE_SHADER_TESS_EVAL) {
1400 vgpr_comp_cnt = enable_prim_id ? 3 : 2;
1401 num_user_sgprs = SI_TES_NUM_USER_SGPR;
1402 } else
1403 unreachable("invalid shader selector type");
1404
1405 /* VS is required to export at least one param. */
1406 nparams = MAX2(shader->info.nr_param_exports, 1);
1407 shader->ctx_reg.vs.spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
1408
1409 if (sscreen->info.chip_class >= GFX10) {
1410 shader->ctx_reg.vs.spi_vs_out_config |=
1411 S_0286C4_NO_PC_EXPORT(shader->info.nr_param_exports == 0);
1412 }
1413
1414 shader->ctx_reg.vs.spi_shader_pos_format =
1415 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
1416 S_02870C_POS1_EXPORT_FORMAT(shader->info.nr_pos_exports > 1 ?
1417 V_02870C_SPI_SHADER_4COMP :
1418 V_02870C_SPI_SHADER_NONE) |
1419 S_02870C_POS2_EXPORT_FORMAT(shader->info.nr_pos_exports > 2 ?
1420 V_02870C_SPI_SHADER_4COMP :
1421 V_02870C_SPI_SHADER_NONE) |
1422 S_02870C_POS3_EXPORT_FORMAT(shader->info.nr_pos_exports > 3 ?
1423 V_02870C_SPI_SHADER_4COMP :
1424 V_02870C_SPI_SHADER_NONE);
1425
1426 oc_lds_en = shader->selector->type == PIPE_SHADER_TESS_EVAL ? 1 : 0;
1427
1428 si_pm4_set_reg(pm4, R_00B120_SPI_SHADER_PGM_LO_VS, va >> 8);
1429 si_pm4_set_reg(pm4, R_00B124_SPI_SHADER_PGM_HI_VS, S_00B124_MEM_BASE(va >> 40));
1430
1431 uint32_t rsrc1 = S_00B128_VGPRS((shader->config.num_vgprs - 1) /
1432 (sscreen->ge_wave_size == 32 ? 8 : 4)) |
1433 S_00B128_VGPR_COMP_CNT(vgpr_comp_cnt) |
1434 S_00B128_DX10_CLAMP(1) |
1435 S_00B128_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1436 S_00B128_FLOAT_MODE(shader->config.float_mode);
1437 uint32_t rsrc2 = S_00B12C_USER_SGPR(num_user_sgprs) |
1438 S_00B12C_OC_LDS_EN(oc_lds_en) |
1439 S_00B12C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0);
1440
1441 if (sscreen->info.chip_class <= GFX9)
1442 rsrc1 |= S_00B128_SGPRS((shader->config.num_sgprs - 1) / 8);
1443
1444 if (!sscreen->use_ngg_streamout) {
1445 rsrc2 |= S_00B12C_SO_BASE0_EN(!!shader->selector->so.stride[0]) |
1446 S_00B12C_SO_BASE1_EN(!!shader->selector->so.stride[1]) |
1447 S_00B12C_SO_BASE2_EN(!!shader->selector->so.stride[2]) |
1448 S_00B12C_SO_BASE3_EN(!!shader->selector->so.stride[3]) |
1449 S_00B12C_SO_EN(!!shader->selector->so.num_outputs);
1450 }
1451
1452 si_pm4_set_reg(pm4, R_00B128_SPI_SHADER_PGM_RSRC1_VS, rsrc1);
1453 si_pm4_set_reg(pm4, R_00B12C_SPI_SHADER_PGM_RSRC2_VS, rsrc2);
1454
1455 if (window_space)
1456 shader->ctx_reg.vs.pa_cl_vte_cntl =
1457 S_028818_VTX_XY_FMT(1) | S_028818_VTX_Z_FMT(1);
1458 else
1459 shader->ctx_reg.vs.pa_cl_vte_cntl =
1460 S_028818_VTX_W0_FMT(1) |
1461 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
1462 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
1463 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1);
1464
1465 if (shader->selector->type == PIPE_SHADER_TESS_EVAL)
1466 si_set_tesseval_regs(sscreen, shader->selector, pm4);
1467
1468 polaris_set_vgt_vertex_reuse(sscreen, shader->selector, shader, pm4);
1469 }
1470
1471 static unsigned si_get_ps_num_interp(struct si_shader *ps)
1472 {
1473 struct tgsi_shader_info *info = &ps->selector->info;
1474 unsigned num_colors = !!(info->colors_read & 0x0f) +
1475 !!(info->colors_read & 0xf0);
1476 unsigned num_interp = ps->selector->info.num_inputs +
1477 (ps->key.part.ps.prolog.color_two_side ? num_colors : 0);
1478
1479 assert(num_interp <= 32);
1480 return MIN2(num_interp, 32);
1481 }
1482
1483 static unsigned si_get_spi_shader_col_format(struct si_shader *shader)
1484 {
1485 unsigned value = shader->key.part.ps.epilog.spi_shader_col_format;
1486 unsigned i, num_targets = (util_last_bit(value) + 3) / 4;
1487
1488 /* If the i-th target format is set, all previous target formats must
1489 * be non-zero to avoid hangs.
1490 */
1491 for (i = 0; i < num_targets; i++)
1492 if (!(value & (0xf << (i * 4))))
1493 value |= V_028714_SPI_SHADER_32_R << (i * 4);
1494
1495 return value;
1496 }
1497
1498 static void si_emit_shader_ps(struct si_context *sctx)
1499 {
1500 struct si_shader *shader = sctx->queued.named.ps->shader;
1501 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
1502
1503 if (!shader)
1504 return;
1505
1506 /* R_0286CC_SPI_PS_INPUT_ENA, R_0286D0_SPI_PS_INPUT_ADDR*/
1507 radeon_opt_set_context_reg2(sctx, R_0286CC_SPI_PS_INPUT_ENA,
1508 SI_TRACKED_SPI_PS_INPUT_ENA,
1509 shader->ctx_reg.ps.spi_ps_input_ena,
1510 shader->ctx_reg.ps.spi_ps_input_addr);
1511
1512 radeon_opt_set_context_reg(sctx, R_0286E0_SPI_BARYC_CNTL,
1513 SI_TRACKED_SPI_BARYC_CNTL,
1514 shader->ctx_reg.ps.spi_baryc_cntl);
1515 radeon_opt_set_context_reg(sctx, R_0286D8_SPI_PS_IN_CONTROL,
1516 SI_TRACKED_SPI_PS_IN_CONTROL,
1517 shader->ctx_reg.ps.spi_ps_in_control);
1518
1519 /* R_028710_SPI_SHADER_Z_FORMAT, R_028714_SPI_SHADER_COL_FORMAT */
1520 radeon_opt_set_context_reg2(sctx, R_028710_SPI_SHADER_Z_FORMAT,
1521 SI_TRACKED_SPI_SHADER_Z_FORMAT,
1522 shader->ctx_reg.ps.spi_shader_z_format,
1523 shader->ctx_reg.ps.spi_shader_col_format);
1524
1525 radeon_opt_set_context_reg(sctx, R_02823C_CB_SHADER_MASK,
1526 SI_TRACKED_CB_SHADER_MASK,
1527 shader->ctx_reg.ps.cb_shader_mask);
1528
1529 if (initial_cdw != sctx->gfx_cs->current.cdw)
1530 sctx->context_roll = true;
1531 }
1532
1533 static void si_shader_ps(struct si_screen *sscreen, struct si_shader *shader)
1534 {
1535 struct tgsi_shader_info *info = &shader->selector->info;
1536 struct si_pm4_state *pm4;
1537 unsigned spi_ps_in_control, spi_shader_col_format, cb_shader_mask;
1538 unsigned spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
1539 uint64_t va;
1540 unsigned input_ena = shader->config.spi_ps_input_ena;
1541
1542 /* we need to enable at least one of them, otherwise we hang the GPU */
1543 assert(G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1544 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1545 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1546 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena) ||
1547 G_0286CC_LINEAR_SAMPLE_ENA(input_ena) ||
1548 G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1549 G_0286CC_LINEAR_CENTROID_ENA(input_ena) ||
1550 G_0286CC_LINE_STIPPLE_TEX_ENA(input_ena));
1551 /* POS_W_FLOAT_ENA requires one of the perspective weights. */
1552 assert(!G_0286CC_POS_W_FLOAT_ENA(input_ena) ||
1553 G_0286CC_PERSP_SAMPLE_ENA(input_ena) ||
1554 G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1555 G_0286CC_PERSP_CENTROID_ENA(input_ena) ||
1556 G_0286CC_PERSP_PULL_MODEL_ENA(input_ena));
1557
1558 /* Validate interpolation optimization flags (read as implications). */
1559 assert(!shader->key.part.ps.prolog.bc_optimize_for_persp ||
1560 (G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1561 G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1562 assert(!shader->key.part.ps.prolog.bc_optimize_for_linear ||
1563 (G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1564 G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1565 assert(!shader->key.part.ps.prolog.force_persp_center_interp ||
1566 (!G_0286CC_PERSP_SAMPLE_ENA(input_ena) &&
1567 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1568 assert(!shader->key.part.ps.prolog.force_linear_center_interp ||
1569 (!G_0286CC_LINEAR_SAMPLE_ENA(input_ena) &&
1570 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1571 assert(!shader->key.part.ps.prolog.force_persp_sample_interp ||
1572 (!G_0286CC_PERSP_CENTER_ENA(input_ena) &&
1573 !G_0286CC_PERSP_CENTROID_ENA(input_ena)));
1574 assert(!shader->key.part.ps.prolog.force_linear_sample_interp ||
1575 (!G_0286CC_LINEAR_CENTER_ENA(input_ena) &&
1576 !G_0286CC_LINEAR_CENTROID_ENA(input_ena)));
1577
1578 /* Validate cases when the optimizations are off (read as implications). */
1579 assert(shader->key.part.ps.prolog.bc_optimize_for_persp ||
1580 !G_0286CC_PERSP_CENTER_ENA(input_ena) ||
1581 !G_0286CC_PERSP_CENTROID_ENA(input_ena));
1582 assert(shader->key.part.ps.prolog.bc_optimize_for_linear ||
1583 !G_0286CC_LINEAR_CENTER_ENA(input_ena) ||
1584 !G_0286CC_LINEAR_CENTROID_ENA(input_ena));
1585
1586 pm4 = si_get_shader_pm4_state(shader);
1587 if (!pm4)
1588 return;
1589
1590 pm4->atom.emit = si_emit_shader_ps;
1591
1592 /* SPI_BARYC_CNTL.POS_FLOAT_LOCATION
1593 * Possible vaules:
1594 * 0 -> Position = pixel center
1595 * 1 -> Position = pixel centroid
1596 * 2 -> Position = at sample position
1597 *
1598 * From GLSL 4.5 specification, section 7.1:
1599 * "The variable gl_FragCoord is available as an input variable from
1600 * within fragment shaders and it holds the window relative coordinates
1601 * (x, y, z, 1/w) values for the fragment. If multi-sampling, this
1602 * value can be for any location within the pixel, or one of the
1603 * fragment samples. The use of centroid does not further restrict
1604 * this value to be inside the current primitive."
1605 *
1606 * Meaning that centroid has no effect and we can return anything within
1607 * the pixel. Thus, return the value at sample position, because that's
1608 * the most accurate one shaders can get.
1609 */
1610 spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1611
1612 if (info->properties[TGSI_PROPERTY_FS_COORD_PIXEL_CENTER] ==
1613 TGSI_FS_COORD_PIXEL_CENTER_INTEGER)
1614 spi_baryc_cntl |= S_0286E0_POS_FLOAT_ULC(1);
1615
1616 spi_shader_col_format = si_get_spi_shader_col_format(shader);
1617 cb_shader_mask = ac_get_cb_shader_mask(spi_shader_col_format);
1618
1619 /* Ensure that some export memory is always allocated, for two reasons:
1620 *
1621 * 1) Correctness: The hardware ignores the EXEC mask if no export
1622 * memory is allocated, so KILL and alpha test do not work correctly
1623 * without this.
1624 * 2) Performance: Every shader needs at least a NULL export, even when
1625 * it writes no color/depth output. The NULL export instruction
1626 * stalls without this setting.
1627 *
1628 * Don't add this to CB_SHADER_MASK.
1629 *
1630 * GFX10 supports pixel shaders without exports by setting both
1631 * the color and Z formats to SPI_SHADER_ZERO. The hw will skip export
1632 * instructions if any are present.
1633 */
1634 if ((sscreen->info.chip_class <= GFX9 ||
1635 info->uses_kill ||
1636 shader->key.part.ps.epilog.alpha_func != PIPE_FUNC_ALWAYS) &&
1637 !spi_shader_col_format &&
1638 !info->writes_z && !info->writes_stencil && !info->writes_samplemask)
1639 spi_shader_col_format = V_028714_SPI_SHADER_32_R;
1640
1641 shader->ctx_reg.ps.spi_ps_input_ena = input_ena;
1642 shader->ctx_reg.ps.spi_ps_input_addr = shader->config.spi_ps_input_addr;
1643
1644 /* Set interpolation controls. */
1645 spi_ps_in_control = S_0286D8_NUM_INTERP(si_get_ps_num_interp(shader)) |
1646 S_0286D8_PS_W32_EN(sscreen->ps_wave_size == 32);
1647
1648 shader->ctx_reg.ps.spi_baryc_cntl = spi_baryc_cntl;
1649 shader->ctx_reg.ps.spi_ps_in_control = spi_ps_in_control;
1650 shader->ctx_reg.ps.spi_shader_z_format =
1651 ac_get_spi_shader_z_format(info->writes_z,
1652 info->writes_stencil,
1653 info->writes_samplemask);
1654 shader->ctx_reg.ps.spi_shader_col_format = spi_shader_col_format;
1655 shader->ctx_reg.ps.cb_shader_mask = cb_shader_mask;
1656
1657 va = shader->bo->gpu_address;
1658 si_pm4_add_bo(pm4, shader->bo, RADEON_USAGE_READ, RADEON_PRIO_SHADER_BINARY);
1659 si_pm4_set_reg(pm4, R_00B020_SPI_SHADER_PGM_LO_PS, va >> 8);
1660 si_pm4_set_reg(pm4, R_00B024_SPI_SHADER_PGM_HI_PS, S_00B024_MEM_BASE(va >> 40));
1661
1662 uint32_t rsrc1 =
1663 S_00B028_VGPRS((shader->config.num_vgprs - 1) /
1664 (sscreen->ps_wave_size == 32 ? 8 : 4)) |
1665 S_00B028_DX10_CLAMP(1) |
1666 S_00B028_MEM_ORDERED(sscreen->info.chip_class >= GFX10) |
1667 S_00B028_FLOAT_MODE(shader->config.float_mode);
1668
1669 if (sscreen->info.chip_class < GFX10) {
1670 rsrc1 |= S_00B028_SGPRS((shader->config.num_sgprs - 1) / 8);
1671 }
1672
1673 si_pm4_set_reg(pm4, R_00B028_SPI_SHADER_PGM_RSRC1_PS, rsrc1);
1674 si_pm4_set_reg(pm4, R_00B02C_SPI_SHADER_PGM_RSRC2_PS,
1675 S_00B02C_EXTRA_LDS_SIZE(shader->config.lds_size) |
1676 S_00B02C_USER_SGPR(SI_PS_NUM_USER_SGPR) |
1677 S_00B32C_SCRATCH_EN(shader->config.scratch_bytes_per_wave > 0));
1678 }
1679
1680 static void si_shader_init_pm4_state(struct si_screen *sscreen,
1681 struct si_shader *shader)
1682 {
1683 switch (shader->selector->type) {
1684 case PIPE_SHADER_VERTEX:
1685 if (shader->key.as_ls)
1686 si_shader_ls(sscreen, shader);
1687 else if (shader->key.as_es)
1688 si_shader_es(sscreen, shader);
1689 else if (shader->key.as_ngg)
1690 gfx10_shader_ngg(sscreen, shader);
1691 else
1692 si_shader_vs(sscreen, shader, NULL);
1693 break;
1694 case PIPE_SHADER_TESS_CTRL:
1695 si_shader_hs(sscreen, shader);
1696 break;
1697 case PIPE_SHADER_TESS_EVAL:
1698 if (shader->key.as_es)
1699 si_shader_es(sscreen, shader);
1700 else if (shader->key.as_ngg)
1701 gfx10_shader_ngg(sscreen, shader);
1702 else
1703 si_shader_vs(sscreen, shader, NULL);
1704 break;
1705 case PIPE_SHADER_GEOMETRY:
1706 if (shader->key.as_ngg)
1707 gfx10_shader_ngg(sscreen, shader);
1708 else
1709 si_shader_gs(sscreen, shader);
1710 break;
1711 case PIPE_SHADER_FRAGMENT:
1712 si_shader_ps(sscreen, shader);
1713 break;
1714 default:
1715 assert(0);
1716 }
1717 }
1718
1719 static unsigned si_get_alpha_test_func(struct si_context *sctx)
1720 {
1721 /* Alpha-test should be disabled if colorbuffer 0 is integer. */
1722 return sctx->queued.named.dsa->alpha_func;
1723 }
1724
1725 void si_shader_selector_key_vs(struct si_context *sctx,
1726 struct si_shader_selector *vs,
1727 struct si_shader_key *key,
1728 struct si_vs_prolog_bits *prolog_key)
1729 {
1730 if (!sctx->vertex_elements ||
1731 vs->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD])
1732 return;
1733
1734 struct si_vertex_elements *elts = sctx->vertex_elements;
1735
1736 prolog_key->instance_divisor_is_one = elts->instance_divisor_is_one;
1737 prolog_key->instance_divisor_is_fetched = elts->instance_divisor_is_fetched;
1738 prolog_key->unpack_instance_id_from_vertex_id =
1739 sctx->prim_discard_cs_instancing;
1740
1741 /* Prefer a monolithic shader to allow scheduling divisions around
1742 * VBO loads. */
1743 if (prolog_key->instance_divisor_is_fetched)
1744 key->opt.prefer_mono = 1;
1745
1746 unsigned count = MIN2(vs->info.num_inputs, elts->count);
1747 unsigned count_mask = (1 << count) - 1;
1748 unsigned fix = elts->fix_fetch_always & count_mask;
1749 unsigned opencode = elts->fix_fetch_opencode & count_mask;
1750
1751 if (sctx->vertex_buffer_unaligned & elts->vb_alignment_check_mask) {
1752 uint32_t mask = elts->fix_fetch_unaligned & count_mask;
1753 while (mask) {
1754 unsigned i = u_bit_scan(&mask);
1755 unsigned log_hw_load_size = 1 + ((elts->hw_load_is_dword >> i) & 1);
1756 unsigned vbidx = elts->vertex_buffer_index[i];
1757 struct pipe_vertex_buffer *vb = &sctx->vertex_buffer[vbidx];
1758 unsigned align_mask = (1 << log_hw_load_size) - 1;
1759 if (vb->buffer_offset & align_mask ||
1760 vb->stride & align_mask) {
1761 fix |= 1 << i;
1762 opencode |= 1 << i;
1763 }
1764 }
1765 }
1766
1767 while (fix) {
1768 unsigned i = u_bit_scan(&fix);
1769 key->mono.vs_fix_fetch[i].bits = elts->fix_fetch[i];
1770 }
1771 key->mono.vs_fetch_opencode = opencode;
1772 }
1773
1774 static void si_shader_selector_key_hw_vs(struct si_context *sctx,
1775 struct si_shader_selector *vs,
1776 struct si_shader_key *key)
1777 {
1778 struct si_shader_selector *ps = sctx->ps_shader.cso;
1779
1780 key->opt.clip_disable =
1781 sctx->queued.named.rasterizer->clip_plane_enable == 0 &&
1782 (vs->info.clipdist_writemask ||
1783 vs->info.writes_clipvertex) &&
1784 !vs->info.culldist_writemask;
1785
1786 /* Find out if PS is disabled. */
1787 bool ps_disabled = true;
1788 if (ps) {
1789 bool ps_modifies_zs = ps->info.uses_kill ||
1790 ps->info.writes_z ||
1791 ps->info.writes_stencil ||
1792 ps->info.writes_samplemask ||
1793 sctx->queued.named.blend->alpha_to_coverage ||
1794 si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS;
1795 unsigned ps_colormask = si_get_total_colormask(sctx);
1796
1797 ps_disabled = sctx->queued.named.rasterizer->rasterizer_discard ||
1798 (!ps_colormask &&
1799 !ps_modifies_zs &&
1800 !ps->info.writes_memory);
1801 }
1802
1803 /* Find out which VS outputs aren't used by the PS. */
1804 uint64_t outputs_written = vs->outputs_written_before_ps;
1805 uint64_t inputs_read = 0;
1806
1807 /* Ignore outputs that are not passed from VS to PS. */
1808 outputs_written &= ~((1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_POSITION, 0, true)) |
1809 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_PSIZE, 0, true)) |
1810 (1ull << si_shader_io_get_unique_index(TGSI_SEMANTIC_CLIPVERTEX, 0, true)));
1811
1812 if (!ps_disabled) {
1813 inputs_read = ps->inputs_read;
1814 }
1815
1816 uint64_t linked = outputs_written & inputs_read;
1817
1818 key->opt.kill_outputs = ~linked & outputs_written;
1819 }
1820
1821 /* Compute the key for the hw shader variant */
1822 static inline void si_shader_selector_key(struct pipe_context *ctx,
1823 struct si_shader_selector *sel,
1824 union si_vgt_stages_key stages_key,
1825 struct si_shader_key *key)
1826 {
1827 struct si_context *sctx = (struct si_context *)ctx;
1828
1829 memset(key, 0, sizeof(*key));
1830
1831 switch (sel->type) {
1832 case PIPE_SHADER_VERTEX:
1833 si_shader_selector_key_vs(sctx, sel, key, &key->part.vs.prolog);
1834
1835 if (sctx->tes_shader.cso)
1836 key->as_ls = 1;
1837 else if (sctx->gs_shader.cso)
1838 key->as_es = 1;
1839 else {
1840 key->as_ngg = stages_key.u.ngg;
1841 si_shader_selector_key_hw_vs(sctx, sel, key);
1842
1843 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1844 key->mono.u.vs_export_prim_id = 1;
1845 }
1846 break;
1847 case PIPE_SHADER_TESS_CTRL:
1848 if (sctx->chip_class >= GFX9) {
1849 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1850 key, &key->part.tcs.ls_prolog);
1851 key->part.tcs.ls = sctx->vs_shader.cso;
1852
1853 /* When the LS VGPR fix is needed, monolithic shaders
1854 * can:
1855 * - avoid initializing EXEC in both the LS prolog
1856 * and the LS main part when !vs_needs_prolog
1857 * - remove the fixup for unused input VGPRs
1858 */
1859 key->part.tcs.ls_prolog.ls_vgpr_fix = sctx->ls_vgpr_fix;
1860
1861 /* The LS output / HS input layout can be communicated
1862 * directly instead of via user SGPRs for merged LS-HS.
1863 * The LS VGPR fix prefers this too.
1864 */
1865 key->opt.prefer_mono = 1;
1866 }
1867
1868 key->part.tcs.epilog.prim_mode =
1869 sctx->tes_shader.cso->info.properties[TGSI_PROPERTY_TES_PRIM_MODE];
1870 key->part.tcs.epilog.invoc0_tess_factors_are_def =
1871 sel->tcs_info.tessfactors_are_def_in_all_invocs;
1872 key->part.tcs.epilog.tes_reads_tess_factors =
1873 sctx->tes_shader.cso->info.reads_tess_factors;
1874
1875 if (sel == sctx->fixed_func_tcs_shader.cso)
1876 key->mono.u.ff_tcs_inputs_to_copy = sctx->vs_shader.cso->outputs_written;
1877 break;
1878 case PIPE_SHADER_TESS_EVAL:
1879 key->as_ngg = stages_key.u.ngg;
1880
1881 if (sctx->gs_shader.cso)
1882 key->as_es = 1;
1883 else {
1884 si_shader_selector_key_hw_vs(sctx, sel, key);
1885
1886 if (sctx->ps_shader.cso && sctx->ps_shader.cso->info.uses_primid)
1887 key->mono.u.vs_export_prim_id = 1;
1888 }
1889 break;
1890 case PIPE_SHADER_GEOMETRY:
1891 if (sctx->chip_class >= GFX9) {
1892 if (sctx->tes_shader.cso) {
1893 key->part.gs.es = sctx->tes_shader.cso;
1894 } else {
1895 si_shader_selector_key_vs(sctx, sctx->vs_shader.cso,
1896 key, &key->part.gs.vs_prolog);
1897 key->part.gs.es = sctx->vs_shader.cso;
1898 key->part.gs.prolog.gfx9_prev_is_vs = 1;
1899 }
1900
1901 key->as_ngg = stages_key.u.ngg;
1902
1903 /* Merged ES-GS can have unbalanced wave usage.
1904 *
1905 * ES threads are per-vertex, while GS threads are
1906 * per-primitive. So without any amplification, there
1907 * are fewer GS threads than ES threads, which can result
1908 * in empty (no-op) GS waves. With too much amplification,
1909 * there are more GS threads than ES threads, which
1910 * can result in empty (no-op) ES waves.
1911 *
1912 * Non-monolithic shaders are implemented by setting EXEC
1913 * at the beginning of shader parts, and don't jump to
1914 * the end if EXEC is 0.
1915 *
1916 * Monolithic shaders use conditional blocks, so they can
1917 * jump and skip empty waves of ES or GS. So set this to
1918 * always use optimized variants, which are monolithic.
1919 */
1920 key->opt.prefer_mono = 1;
1921 }
1922 key->part.gs.prolog.tri_strip_adj_fix = sctx->gs_tri_strip_adj_fix;
1923 break;
1924 case PIPE_SHADER_FRAGMENT: {
1925 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
1926 struct si_state_blend *blend = sctx->queued.named.blend;
1927
1928 if (sel->info.properties[TGSI_PROPERTY_FS_COLOR0_WRITES_ALL_CBUFS] &&
1929 sel->info.colors_written == 0x1)
1930 key->part.ps.epilog.last_cbuf = MAX2(sctx->framebuffer.state.nr_cbufs, 1) - 1;
1931
1932 /* Select the shader color format based on whether
1933 * blending or alpha are needed.
1934 */
1935 key->part.ps.epilog.spi_shader_col_format =
1936 (blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1937 sctx->framebuffer.spi_shader_col_format_blend_alpha) |
1938 (blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1939 sctx->framebuffer.spi_shader_col_format_blend) |
1940 (~blend->blend_enable_4bit & blend->need_src_alpha_4bit &
1941 sctx->framebuffer.spi_shader_col_format_alpha) |
1942 (~blend->blend_enable_4bit & ~blend->need_src_alpha_4bit &
1943 sctx->framebuffer.spi_shader_col_format);
1944 key->part.ps.epilog.spi_shader_col_format &= blend->cb_target_enabled_4bit;
1945
1946 /* The output for dual source blending should have
1947 * the same format as the first output.
1948 */
1949 if (blend->dual_src_blend) {
1950 key->part.ps.epilog.spi_shader_col_format |=
1951 (key->part.ps.epilog.spi_shader_col_format & 0xf) << 4;
1952 }
1953
1954 /* If alpha-to-coverage is enabled, we have to export alpha
1955 * even if there is no color buffer.
1956 */
1957 if (!(key->part.ps.epilog.spi_shader_col_format & 0xf) &&
1958 blend->alpha_to_coverage)
1959 key->part.ps.epilog.spi_shader_col_format |= V_028710_SPI_SHADER_32_AR;
1960
1961 /* On GFX6 and GFX7 except Hawaii, the CB doesn't clamp outputs
1962 * to the range supported by the type if a channel has less
1963 * than 16 bits and the export format is 16_ABGR.
1964 */
1965 if (sctx->chip_class <= GFX7 && sctx->family != CHIP_HAWAII) {
1966 key->part.ps.epilog.color_is_int8 = sctx->framebuffer.color_is_int8;
1967 key->part.ps.epilog.color_is_int10 = sctx->framebuffer.color_is_int10;
1968 }
1969
1970 /* Disable unwritten outputs (if WRITE_ALL_CBUFS isn't enabled). */
1971 if (!key->part.ps.epilog.last_cbuf) {
1972 key->part.ps.epilog.spi_shader_col_format &= sel->colors_written_4bit;
1973 key->part.ps.epilog.color_is_int8 &= sel->info.colors_written;
1974 key->part.ps.epilog.color_is_int10 &= sel->info.colors_written;
1975 }
1976
1977 bool is_poly = !util_prim_is_points_or_lines(sctx->current_rast_prim);
1978 bool is_line = util_prim_is_lines(sctx->current_rast_prim);
1979
1980 key->part.ps.prolog.color_two_side = rs->two_side && sel->info.colors_read;
1981 key->part.ps.prolog.flatshade_colors = rs->flatshade && sel->info.colors_read;
1982
1983 key->part.ps.epilog.alpha_to_one = blend->alpha_to_one &&
1984 rs->multisample_enable;
1985
1986 key->part.ps.prolog.poly_stipple = rs->poly_stipple_enable && is_poly;
1987 key->part.ps.epilog.poly_line_smoothing = ((is_poly && rs->poly_smooth) ||
1988 (is_line && rs->line_smooth)) &&
1989 sctx->framebuffer.nr_samples <= 1;
1990 key->part.ps.epilog.clamp_color = rs->clamp_fragment_color;
1991
1992 if (sctx->ps_iter_samples > 1 &&
1993 sel->info.reads_samplemask) {
1994 key->part.ps.prolog.samplemask_log_ps_iter =
1995 util_logbase2(sctx->ps_iter_samples);
1996 }
1997
1998 if (rs->force_persample_interp &&
1999 rs->multisample_enable &&
2000 sctx->framebuffer.nr_samples > 1 &&
2001 sctx->ps_iter_samples > 1) {
2002 key->part.ps.prolog.force_persp_sample_interp =
2003 sel->info.uses_persp_center ||
2004 sel->info.uses_persp_centroid;
2005
2006 key->part.ps.prolog.force_linear_sample_interp =
2007 sel->info.uses_linear_center ||
2008 sel->info.uses_linear_centroid;
2009 } else if (rs->multisample_enable &&
2010 sctx->framebuffer.nr_samples > 1) {
2011 key->part.ps.prolog.bc_optimize_for_persp =
2012 sel->info.uses_persp_center &&
2013 sel->info.uses_persp_centroid;
2014 key->part.ps.prolog.bc_optimize_for_linear =
2015 sel->info.uses_linear_center &&
2016 sel->info.uses_linear_centroid;
2017 } else {
2018 /* Make sure SPI doesn't compute more than 1 pair
2019 * of (i,j), which is the optimization here. */
2020 key->part.ps.prolog.force_persp_center_interp =
2021 sel->info.uses_persp_center +
2022 sel->info.uses_persp_centroid +
2023 sel->info.uses_persp_sample > 1;
2024
2025 key->part.ps.prolog.force_linear_center_interp =
2026 sel->info.uses_linear_center +
2027 sel->info.uses_linear_centroid +
2028 sel->info.uses_linear_sample > 1;
2029
2030 if (sel->info.uses_persp_opcode_interp_sample ||
2031 sel->info.uses_linear_opcode_interp_sample)
2032 key->mono.u.ps.interpolate_at_sample_force_center = 1;
2033 }
2034
2035 key->part.ps.epilog.alpha_func = si_get_alpha_test_func(sctx);
2036
2037 /* ps_uses_fbfetch is true only if the color buffer is bound. */
2038 if (sctx->ps_uses_fbfetch && !sctx->blitter->running) {
2039 struct pipe_surface *cb0 = sctx->framebuffer.state.cbufs[0];
2040 struct pipe_resource *tex = cb0->texture;
2041
2042 /* 1D textures are allocated and used as 2D on GFX9. */
2043 key->mono.u.ps.fbfetch_msaa = sctx->framebuffer.nr_samples > 1;
2044 key->mono.u.ps.fbfetch_is_1D = sctx->chip_class != GFX9 &&
2045 (tex->target == PIPE_TEXTURE_1D ||
2046 tex->target == PIPE_TEXTURE_1D_ARRAY);
2047 key->mono.u.ps.fbfetch_layered = tex->target == PIPE_TEXTURE_1D_ARRAY ||
2048 tex->target == PIPE_TEXTURE_2D_ARRAY ||
2049 tex->target == PIPE_TEXTURE_CUBE ||
2050 tex->target == PIPE_TEXTURE_CUBE_ARRAY ||
2051 tex->target == PIPE_TEXTURE_3D;
2052 }
2053 break;
2054 }
2055 default:
2056 assert(0);
2057 }
2058
2059 if (unlikely(sctx->screen->debug_flags & DBG(NO_OPT_VARIANT)))
2060 memset(&key->opt, 0, sizeof(key->opt));
2061 }
2062
2063 static void si_build_shader_variant(struct si_shader *shader,
2064 int thread_index,
2065 bool low_priority)
2066 {
2067 struct si_shader_selector *sel = shader->selector;
2068 struct si_screen *sscreen = sel->screen;
2069 struct ac_llvm_compiler *compiler;
2070 struct pipe_debug_callback *debug = &shader->compiler_ctx_state.debug;
2071
2072 if (thread_index >= 0) {
2073 if (low_priority) {
2074 assert(thread_index < ARRAY_SIZE(sscreen->compiler_lowp));
2075 compiler = &sscreen->compiler_lowp[thread_index];
2076 } else {
2077 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2078 compiler = &sscreen->compiler[thread_index];
2079 }
2080 if (!debug->async)
2081 debug = NULL;
2082 } else {
2083 assert(!low_priority);
2084 compiler = shader->compiler_ctx_state.compiler;
2085 }
2086
2087 if (unlikely(!si_shader_create(sscreen, compiler, shader, debug))) {
2088 PRINT_ERR("Failed to build shader variant (type=%u)\n",
2089 sel->type);
2090 shader->compilation_failed = true;
2091 return;
2092 }
2093
2094 if (shader->compiler_ctx_state.is_debug_context) {
2095 FILE *f = open_memstream(&shader->shader_log,
2096 &shader->shader_log_size);
2097 if (f) {
2098 si_shader_dump(sscreen, shader, NULL, f, false);
2099 fclose(f);
2100 }
2101 }
2102
2103 si_shader_init_pm4_state(sscreen, shader);
2104 }
2105
2106 static void si_build_shader_variant_low_priority(void *job, int thread_index)
2107 {
2108 struct si_shader *shader = (struct si_shader *)job;
2109
2110 assert(thread_index >= 0);
2111
2112 si_build_shader_variant(shader, thread_index, true);
2113 }
2114
2115 static const struct si_shader_key zeroed;
2116
2117 static bool si_check_missing_main_part(struct si_screen *sscreen,
2118 struct si_shader_selector *sel,
2119 struct si_compiler_ctx_state *compiler_state,
2120 struct si_shader_key *key)
2121 {
2122 struct si_shader **mainp = si_get_main_shader_part(sel, key);
2123
2124 if (!*mainp) {
2125 struct si_shader *main_part = CALLOC_STRUCT(si_shader);
2126
2127 if (!main_part)
2128 return false;
2129
2130 /* We can leave the fence as permanently signaled because the
2131 * main part becomes visible globally only after it has been
2132 * compiled. */
2133 util_queue_fence_init(&main_part->ready);
2134
2135 main_part->selector = sel;
2136 main_part->key.as_es = key->as_es;
2137 main_part->key.as_ls = key->as_ls;
2138 main_part->key.as_ngg = key->as_ngg;
2139 main_part->is_monolithic = false;
2140
2141 if (si_compile_tgsi_shader(sscreen, compiler_state->compiler,
2142 main_part, &compiler_state->debug) != 0) {
2143 FREE(main_part);
2144 return false;
2145 }
2146 *mainp = main_part;
2147 }
2148 return true;
2149 }
2150
2151 /**
2152 * Select a shader variant according to the shader key.
2153 *
2154 * \param optimized_or_none If the key describes an optimized shader variant and
2155 * the compilation isn't finished, don't select any
2156 * shader and return an error.
2157 */
2158 int si_shader_select_with_key(struct si_screen *sscreen,
2159 struct si_shader_ctx_state *state,
2160 struct si_compiler_ctx_state *compiler_state,
2161 struct si_shader_key *key,
2162 int thread_index,
2163 bool optimized_or_none)
2164 {
2165 struct si_shader_selector *sel = state->cso;
2166 struct si_shader_selector *previous_stage_sel = NULL;
2167 struct si_shader *current = state->current;
2168 struct si_shader *iter, *shader = NULL;
2169
2170 again:
2171 /* Check if we don't need to change anything.
2172 * This path is also used for most shaders that don't need multiple
2173 * variants, it will cost just a computation of the key and this
2174 * test. */
2175 if (likely(current &&
2176 memcmp(&current->key, key, sizeof(*key)) == 0)) {
2177 if (unlikely(!util_queue_fence_is_signalled(&current->ready))) {
2178 if (current->is_optimized) {
2179 if (optimized_or_none)
2180 return -1;
2181
2182 memset(&key->opt, 0, sizeof(key->opt));
2183 goto current_not_ready;
2184 }
2185
2186 util_queue_fence_wait(&current->ready);
2187 }
2188
2189 return current->compilation_failed ? -1 : 0;
2190 }
2191 current_not_ready:
2192
2193 /* This must be done before the mutex is locked, because async GS
2194 * compilation calls this function too, and therefore must enter
2195 * the mutex first.
2196 *
2197 * Only wait if we are in a draw call. Don't wait if we are
2198 * in a compiler thread.
2199 */
2200 if (thread_index < 0)
2201 util_queue_fence_wait(&sel->ready);
2202
2203 mtx_lock(&sel->mutex);
2204
2205 /* Find the shader variant. */
2206 for (iter = sel->first_variant; iter; iter = iter->next_variant) {
2207 /* Don't check the "current" shader. We checked it above. */
2208 if (current != iter &&
2209 memcmp(&iter->key, key, sizeof(*key)) == 0) {
2210 mtx_unlock(&sel->mutex);
2211
2212 if (unlikely(!util_queue_fence_is_signalled(&iter->ready))) {
2213 /* If it's an optimized shader and its compilation has
2214 * been started but isn't done, use the unoptimized
2215 * shader so as not to cause a stall due to compilation.
2216 */
2217 if (iter->is_optimized) {
2218 if (optimized_or_none)
2219 return -1;
2220 memset(&key->opt, 0, sizeof(key->opt));
2221 goto again;
2222 }
2223
2224 util_queue_fence_wait(&iter->ready);
2225 }
2226
2227 if (iter->compilation_failed) {
2228 return -1; /* skip the draw call */
2229 }
2230
2231 state->current = iter;
2232 return 0;
2233 }
2234 }
2235
2236 /* Build a new shader. */
2237 shader = CALLOC_STRUCT(si_shader);
2238 if (!shader) {
2239 mtx_unlock(&sel->mutex);
2240 return -ENOMEM;
2241 }
2242
2243 util_queue_fence_init(&shader->ready);
2244
2245 shader->selector = sel;
2246 shader->key = *key;
2247 shader->compiler_ctx_state = *compiler_state;
2248
2249 /* If this is a merged shader, get the first shader's selector. */
2250 if (sscreen->info.chip_class >= GFX9) {
2251 if (sel->type == PIPE_SHADER_TESS_CTRL)
2252 previous_stage_sel = key->part.tcs.ls;
2253 else if (sel->type == PIPE_SHADER_GEOMETRY)
2254 previous_stage_sel = key->part.gs.es;
2255
2256 /* We need to wait for the previous shader. */
2257 if (previous_stage_sel && thread_index < 0)
2258 util_queue_fence_wait(&previous_stage_sel->ready);
2259 }
2260
2261 bool is_pure_monolithic =
2262 sscreen->use_monolithic_shaders ||
2263 memcmp(&key->mono, &zeroed.mono, sizeof(key->mono)) != 0;
2264
2265 /* Compile the main shader part if it doesn't exist. This can happen
2266 * if the initial guess was wrong.
2267 *
2268 * The prim discard CS doesn't need the main shader part.
2269 */
2270 if (!is_pure_monolithic &&
2271 !key->opt.vs_as_prim_discard_cs) {
2272 bool ok = true;
2273
2274 /* Make sure the main shader part is present. This is needed
2275 * for shaders that can be compiled as VS, LS, or ES, and only
2276 * one of them is compiled at creation.
2277 *
2278 * It is also needed for GS, which can be compiled as non-NGG
2279 * and NGG.
2280 *
2281 * For merged shaders, check that the starting shader's main
2282 * part is present.
2283 */
2284 if (previous_stage_sel) {
2285 struct si_shader_key shader1_key = zeroed;
2286
2287 if (sel->type == PIPE_SHADER_TESS_CTRL)
2288 shader1_key.as_ls = 1;
2289 else if (sel->type == PIPE_SHADER_GEOMETRY)
2290 shader1_key.as_es = 1;
2291 else
2292 assert(0);
2293
2294 if (sel->type == PIPE_SHADER_GEOMETRY &&
2295 previous_stage_sel->type == PIPE_SHADER_TESS_EVAL)
2296 shader1_key.as_ngg = key->as_ngg;
2297
2298 mtx_lock(&previous_stage_sel->mutex);
2299 ok = si_check_missing_main_part(sscreen,
2300 previous_stage_sel,
2301 compiler_state, &shader1_key);
2302 mtx_unlock(&previous_stage_sel->mutex);
2303 }
2304
2305 if (ok) {
2306 ok = si_check_missing_main_part(sscreen, sel,
2307 compiler_state, key);
2308 }
2309
2310 if (!ok) {
2311 FREE(shader);
2312 mtx_unlock(&sel->mutex);
2313 return -ENOMEM; /* skip the draw call */
2314 }
2315 }
2316
2317 /* Keep the reference to the 1st shader of merged shaders, so that
2318 * Gallium can't destroy it before we destroy the 2nd shader.
2319 *
2320 * Set sctx = NULL, because it's unused if we're not releasing
2321 * the shader, and we don't have any sctx here.
2322 */
2323 si_shader_selector_reference(NULL, &shader->previous_stage_sel,
2324 previous_stage_sel);
2325
2326 /* Monolithic-only shaders don't make a distinction between optimized
2327 * and unoptimized. */
2328 shader->is_monolithic =
2329 is_pure_monolithic ||
2330 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2331
2332 /* The prim discard CS is always optimized. */
2333 shader->is_optimized =
2334 (!is_pure_monolithic || key->opt.vs_as_prim_discard_cs) &&
2335 memcmp(&key->opt, &zeroed.opt, sizeof(key->opt)) != 0;
2336
2337 /* If it's an optimized shader, compile it asynchronously. */
2338 if (shader->is_optimized && thread_index < 0) {
2339 /* Compile it asynchronously. */
2340 util_queue_add_job(&sscreen->shader_compiler_queue_low_priority,
2341 shader, &shader->ready,
2342 si_build_shader_variant_low_priority, NULL);
2343
2344 /* Add only after the ready fence was reset, to guard against a
2345 * race with si_bind_XX_shader. */
2346 if (!sel->last_variant) {
2347 sel->first_variant = shader;
2348 sel->last_variant = shader;
2349 } else {
2350 sel->last_variant->next_variant = shader;
2351 sel->last_variant = shader;
2352 }
2353
2354 /* Use the default (unoptimized) shader for now. */
2355 memset(&key->opt, 0, sizeof(key->opt));
2356 mtx_unlock(&sel->mutex);
2357
2358 if (sscreen->options.sync_compile)
2359 util_queue_fence_wait(&shader->ready);
2360
2361 if (optimized_or_none)
2362 return -1;
2363 goto again;
2364 }
2365
2366 /* Reset the fence before adding to the variant list. */
2367 util_queue_fence_reset(&shader->ready);
2368
2369 if (!sel->last_variant) {
2370 sel->first_variant = shader;
2371 sel->last_variant = shader;
2372 } else {
2373 sel->last_variant->next_variant = shader;
2374 sel->last_variant = shader;
2375 }
2376
2377 mtx_unlock(&sel->mutex);
2378
2379 assert(!shader->is_optimized);
2380 si_build_shader_variant(shader, thread_index, false);
2381
2382 util_queue_fence_signal(&shader->ready);
2383
2384 if (!shader->compilation_failed)
2385 state->current = shader;
2386
2387 return shader->compilation_failed ? -1 : 0;
2388 }
2389
2390 static int si_shader_select(struct pipe_context *ctx,
2391 struct si_shader_ctx_state *state,
2392 union si_vgt_stages_key stages_key,
2393 struct si_compiler_ctx_state *compiler_state)
2394 {
2395 struct si_context *sctx = (struct si_context *)ctx;
2396 struct si_shader_key key;
2397
2398 si_shader_selector_key(ctx, state->cso, stages_key, &key);
2399 return si_shader_select_with_key(sctx->screen, state, compiler_state,
2400 &key, -1, false);
2401 }
2402
2403 static void si_parse_next_shader_property(const struct tgsi_shader_info *info,
2404 bool streamout,
2405 struct si_shader_key *key)
2406 {
2407 unsigned next_shader = info->properties[TGSI_PROPERTY_NEXT_SHADER];
2408
2409 switch (info->processor) {
2410 case PIPE_SHADER_VERTEX:
2411 switch (next_shader) {
2412 case PIPE_SHADER_GEOMETRY:
2413 key->as_es = 1;
2414 break;
2415 case PIPE_SHADER_TESS_CTRL:
2416 case PIPE_SHADER_TESS_EVAL:
2417 key->as_ls = 1;
2418 break;
2419 default:
2420 /* If POSITION isn't written, it can only be a HW VS
2421 * if streamout is used. If streamout isn't used,
2422 * assume that it's a HW LS. (the next shader is TCS)
2423 * This heuristic is needed for separate shader objects.
2424 */
2425 if (!info->writes_position && !streamout)
2426 key->as_ls = 1;
2427 }
2428 break;
2429
2430 case PIPE_SHADER_TESS_EVAL:
2431 if (next_shader == PIPE_SHADER_GEOMETRY ||
2432 !info->writes_position)
2433 key->as_es = 1;
2434 break;
2435 }
2436 }
2437
2438 /**
2439 * Compile the main shader part or the monolithic shader as part of
2440 * si_shader_selector initialization. Since it can be done asynchronously,
2441 * there is no way to report compile failures to applications.
2442 */
2443 static void si_init_shader_selector_async(void *job, int thread_index)
2444 {
2445 struct si_shader_selector *sel = (struct si_shader_selector *)job;
2446 struct si_screen *sscreen = sel->screen;
2447 struct ac_llvm_compiler *compiler;
2448 struct pipe_debug_callback *debug = &sel->compiler_ctx_state.debug;
2449
2450 assert(!debug->debug_message || debug->async);
2451 assert(thread_index >= 0);
2452 assert(thread_index < ARRAY_SIZE(sscreen->compiler));
2453 compiler = &sscreen->compiler[thread_index];
2454
2455 if (sel->nir)
2456 si_lower_nir(sel);
2457
2458 /* Compile the main shader part for use with a prolog and/or epilog.
2459 * If this fails, the driver will try to compile a monolithic shader
2460 * on demand.
2461 */
2462 if (!sscreen->use_monolithic_shaders) {
2463 struct si_shader *shader = CALLOC_STRUCT(si_shader);
2464 void *ir_binary = NULL;
2465
2466 if (!shader) {
2467 fprintf(stderr, "radeonsi: can't allocate a main shader part\n");
2468 return;
2469 }
2470
2471 /* We can leave the fence signaled because use of the default
2472 * main part is guarded by the selector's ready fence. */
2473 util_queue_fence_init(&shader->ready);
2474
2475 shader->selector = sel;
2476 shader->is_monolithic = false;
2477 si_parse_next_shader_property(&sel->info,
2478 sel->so.num_outputs != 0,
2479 &shader->key);
2480
2481 if (sscreen->use_ngg &&
2482 (!sel->so.num_outputs || sscreen->use_ngg_streamout) &&
2483 ((sel->type == PIPE_SHADER_VERTEX &&
2484 !shader->key.as_ls && !shader->key.as_es) ||
2485 sel->type == PIPE_SHADER_TESS_EVAL ||
2486 sel->type == PIPE_SHADER_GEOMETRY))
2487 shader->key.as_ngg = 1;
2488
2489 if (sel->tokens || sel->nir) {
2490 ir_binary = si_get_ir_binary(sel, shader->key.as_ngg,
2491 shader->key.as_es);
2492 }
2493
2494 /* Try to load the shader from the shader cache. */
2495 mtx_lock(&sscreen->shader_cache_mutex);
2496
2497 if (ir_binary &&
2498 si_shader_cache_load_shader(sscreen, ir_binary, shader)) {
2499 mtx_unlock(&sscreen->shader_cache_mutex);
2500 si_shader_dump_stats_for_shader_db(sscreen, shader, debug);
2501 } else {
2502 mtx_unlock(&sscreen->shader_cache_mutex);
2503
2504 /* Compile the shader if it hasn't been loaded from the cache. */
2505 if (si_compile_tgsi_shader(sscreen, compiler, shader,
2506 debug) != 0) {
2507 FREE(shader);
2508 FREE(ir_binary);
2509 fprintf(stderr, "radeonsi: can't compile a main shader part\n");
2510 return;
2511 }
2512
2513 if (ir_binary) {
2514 mtx_lock(&sscreen->shader_cache_mutex);
2515 if (!si_shader_cache_insert_shader(sscreen, ir_binary, shader, true))
2516 FREE(ir_binary);
2517 mtx_unlock(&sscreen->shader_cache_mutex);
2518 }
2519 }
2520
2521 *si_get_main_shader_part(sel, &shader->key) = shader;
2522
2523 /* Unset "outputs_written" flags for outputs converted to
2524 * DEFAULT_VAL, so that later inter-shader optimizations don't
2525 * try to eliminate outputs that don't exist in the final
2526 * shader.
2527 *
2528 * This is only done if non-monolithic shaders are enabled.
2529 */
2530 if ((sel->type == PIPE_SHADER_VERTEX ||
2531 sel->type == PIPE_SHADER_TESS_EVAL) &&
2532 !shader->key.as_ls &&
2533 !shader->key.as_es) {
2534 unsigned i;
2535
2536 for (i = 0; i < sel->info.num_outputs; i++) {
2537 unsigned offset = shader->info.vs_output_param_offset[i];
2538
2539 if (offset <= AC_EXP_PARAM_OFFSET_31)
2540 continue;
2541
2542 unsigned name = sel->info.output_semantic_name[i];
2543 unsigned index = sel->info.output_semantic_index[i];
2544 unsigned id;
2545
2546 switch (name) {
2547 case TGSI_SEMANTIC_GENERIC:
2548 /* don't process indices the function can't handle */
2549 if (index >= SI_MAX_IO_GENERIC)
2550 break;
2551 /* fall through */
2552 default:
2553 id = si_shader_io_get_unique_index(name, index, true);
2554 sel->outputs_written_before_ps &= ~(1ull << id);
2555 break;
2556 case TGSI_SEMANTIC_POSITION: /* ignore these */
2557 case TGSI_SEMANTIC_PSIZE:
2558 case TGSI_SEMANTIC_CLIPVERTEX:
2559 case TGSI_SEMANTIC_EDGEFLAG:
2560 break;
2561 }
2562 }
2563 }
2564 }
2565
2566 /* The GS copy shader is always pre-compiled. */
2567 if (sel->type == PIPE_SHADER_GEOMETRY &&
2568 (!sscreen->use_ngg ||
2569 !sscreen->use_ngg_streamout || /* also for PRIMITIVES_GENERATED */
2570 sel->tess_turns_off_ngg)) {
2571 sel->gs_copy_shader = si_generate_gs_copy_shader(sscreen, compiler, sel, debug);
2572 if (!sel->gs_copy_shader) {
2573 fprintf(stderr, "radeonsi: can't create GS copy shader\n");
2574 return;
2575 }
2576
2577 si_shader_vs(sscreen, sel->gs_copy_shader, sel);
2578 }
2579 }
2580
2581 void si_schedule_initial_compile(struct si_context *sctx, unsigned processor,
2582 struct util_queue_fence *ready_fence,
2583 struct si_compiler_ctx_state *compiler_ctx_state,
2584 void *job, util_queue_execute_func execute)
2585 {
2586 util_queue_fence_init(ready_fence);
2587
2588 struct util_async_debug_callback async_debug;
2589 bool debug =
2590 (sctx->debug.debug_message && !sctx->debug.async) ||
2591 sctx->is_debug ||
2592 si_can_dump_shader(sctx->screen, processor);
2593
2594 if (debug) {
2595 u_async_debug_init(&async_debug);
2596 compiler_ctx_state->debug = async_debug.base;
2597 }
2598
2599 util_queue_add_job(&sctx->screen->shader_compiler_queue, job,
2600 ready_fence, execute, NULL);
2601
2602 if (debug) {
2603 util_queue_fence_wait(ready_fence);
2604 u_async_debug_drain(&async_debug, &sctx->debug);
2605 u_async_debug_cleanup(&async_debug);
2606 }
2607
2608 if (sctx->screen->options.sync_compile)
2609 util_queue_fence_wait(ready_fence);
2610 }
2611
2612 /* Return descriptor slot usage masks from the given shader info. */
2613 void si_get_active_slot_masks(const struct tgsi_shader_info *info,
2614 uint32_t *const_and_shader_buffers,
2615 uint64_t *samplers_and_images)
2616 {
2617 unsigned start, num_shaderbufs, num_constbufs, num_images, num_samplers;
2618
2619 num_shaderbufs = util_last_bit(info->shader_buffers_declared);
2620 num_constbufs = util_last_bit(info->const_buffers_declared);
2621 /* two 8-byte images share one 16-byte slot */
2622 num_images = align(util_last_bit(info->images_declared), 2);
2623 num_samplers = util_last_bit(info->samplers_declared);
2624
2625 /* The layout is: sb[last] ... sb[0], cb[0] ... cb[last] */
2626 start = si_get_shaderbuf_slot(num_shaderbufs - 1);
2627 *const_and_shader_buffers =
2628 u_bit_consecutive(start, num_shaderbufs + num_constbufs);
2629
2630 /* The layout is: image[last] ... image[0], sampler[0] ... sampler[last] */
2631 start = si_get_image_slot(num_images - 1) / 2;
2632 *samplers_and_images =
2633 u_bit_consecutive64(start, num_images / 2 + num_samplers);
2634 }
2635
2636 static void *si_create_shader_selector(struct pipe_context *ctx,
2637 const struct pipe_shader_state *state)
2638 {
2639 struct si_screen *sscreen = (struct si_screen *)ctx->screen;
2640 struct si_context *sctx = (struct si_context*)ctx;
2641 struct si_shader_selector *sel = CALLOC_STRUCT(si_shader_selector);
2642 int i;
2643
2644 if (!sel)
2645 return NULL;
2646
2647 pipe_reference_init(&sel->reference, 1);
2648 sel->screen = sscreen;
2649 sel->compiler_ctx_state.debug = sctx->debug;
2650 sel->compiler_ctx_state.is_debug_context = sctx->is_debug;
2651
2652 sel->so = state->stream_output;
2653
2654 if (state->type == PIPE_SHADER_IR_TGSI &&
2655 !sscreen->options.enable_nir) {
2656 sel->tokens = tgsi_dup_tokens(state->tokens);
2657 if (!sel->tokens) {
2658 FREE(sel);
2659 return NULL;
2660 }
2661
2662 tgsi_scan_shader(state->tokens, &sel->info);
2663 tgsi_scan_tess_ctrl(state->tokens, &sel->info, &sel->tcs_info);
2664
2665 /* Fixup for TGSI: Set which opcode uses which (i,j) pair. */
2666 if (sel->info.uses_persp_opcode_interp_centroid)
2667 sel->info.uses_persp_centroid = true;
2668
2669 if (sel->info.uses_linear_opcode_interp_centroid)
2670 sel->info.uses_linear_centroid = true;
2671
2672 if (sel->info.uses_persp_opcode_interp_offset ||
2673 sel->info.uses_persp_opcode_interp_sample)
2674 sel->info.uses_persp_center = true;
2675
2676 if (sel->info.uses_linear_opcode_interp_offset ||
2677 sel->info.uses_linear_opcode_interp_sample)
2678 sel->info.uses_linear_center = true;
2679 } else {
2680 if (state->type == PIPE_SHADER_IR_TGSI) {
2681 sel->nir = tgsi_to_nir(state->tokens, ctx->screen);
2682 } else {
2683 assert(state->type == PIPE_SHADER_IR_NIR);
2684 sel->nir = state->ir.nir;
2685 }
2686
2687 si_nir_lower_ps_inputs(sel->nir);
2688 si_nir_opts(sel->nir);
2689 si_nir_scan_shader(sel->nir, &sel->info);
2690 si_nir_scan_tess_ctrl(sel->nir, &sel->tcs_info);
2691 }
2692
2693 sel->type = sel->info.processor;
2694 p_atomic_inc(&sscreen->num_shaders_created);
2695 si_get_active_slot_masks(&sel->info,
2696 &sel->active_const_and_shader_buffers,
2697 &sel->active_samplers_and_images);
2698
2699 /* Record which streamout buffers are enabled. */
2700 for (i = 0; i < sel->so.num_outputs; i++) {
2701 sel->enabled_streamout_buffer_mask |=
2702 (1 << sel->so.output[i].output_buffer) <<
2703 (sel->so.output[i].stream * 4);
2704 }
2705
2706 /* The prolog is a no-op if there are no inputs. */
2707 sel->vs_needs_prolog = sel->type == PIPE_SHADER_VERTEX &&
2708 sel->info.num_inputs &&
2709 !sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD];
2710
2711 sel->force_correct_derivs_after_kill =
2712 sel->type == PIPE_SHADER_FRAGMENT &&
2713 sel->info.uses_derivatives &&
2714 sel->info.uses_kill &&
2715 sctx->screen->debug_flags & DBG(FS_CORRECT_DERIVS_AFTER_KILL);
2716
2717 sel->prim_discard_cs_allowed =
2718 sel->type == PIPE_SHADER_VERTEX &&
2719 !sel->info.uses_bindless_images &&
2720 !sel->info.uses_bindless_samplers &&
2721 !sel->info.writes_memory &&
2722 !sel->info.writes_viewport_index &&
2723 !sel->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] &&
2724 !sel->so.num_outputs;
2725
2726 if (sel->type == PIPE_SHADER_VERTEX &&
2727 sel->info.writes_edgeflag) {
2728 if (sscreen->info.chip_class >= GFX10)
2729 sel->ngg_writes_edgeflag = true;
2730 else
2731 sel->pos_writes_edgeflag = true;
2732 }
2733
2734 switch (sel->type) {
2735 case PIPE_SHADER_GEOMETRY:
2736 sel->gs_output_prim =
2737 sel->info.properties[TGSI_PROPERTY_GS_OUTPUT_PRIM];
2738
2739 /* Only possibilities: POINTS, LINE_STRIP, TRIANGLES */
2740 sel->rast_prim = sel->gs_output_prim;
2741 if (util_rast_prim_is_triangles(sel->rast_prim))
2742 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2743
2744 sel->gs_max_out_vertices =
2745 sel->info.properties[TGSI_PROPERTY_GS_MAX_OUTPUT_VERTICES];
2746 sel->gs_num_invocations =
2747 sel->info.properties[TGSI_PROPERTY_GS_INVOCATIONS];
2748 sel->gsvs_vertex_size = sel->info.num_outputs * 16;
2749 sel->max_gsvs_emit_size = sel->gsvs_vertex_size *
2750 sel->gs_max_out_vertices;
2751
2752 sel->max_gs_stream = 0;
2753 for (i = 0; i < sel->so.num_outputs; i++)
2754 sel->max_gs_stream = MAX2(sel->max_gs_stream,
2755 sel->so.output[i].stream);
2756
2757 sel->gs_input_verts_per_prim =
2758 u_vertices_per_prim(sel->info.properties[TGSI_PROPERTY_GS_INPUT_PRIM]);
2759
2760 /* EN_MAX_VERT_OUT_PER_GS_INSTANCE does not work with tesselation. */
2761 sel->tess_turns_off_ngg =
2762 (sscreen->info.family == CHIP_NAVI10 ||
2763 sscreen->info.family == CHIP_NAVI12 ||
2764 sscreen->info.family == CHIP_NAVI14) &&
2765 sel->gs_num_invocations * sel->gs_max_out_vertices > 256;
2766 break;
2767
2768 case PIPE_SHADER_TESS_CTRL:
2769 /* Always reserve space for these. */
2770 sel->patch_outputs_written |=
2771 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSINNER, 0)) |
2772 (1ull << si_shader_io_get_unique_index_patch(TGSI_SEMANTIC_TESSOUTER, 0));
2773 /* fall through */
2774 case PIPE_SHADER_VERTEX:
2775 case PIPE_SHADER_TESS_EVAL:
2776 for (i = 0; i < sel->info.num_outputs; i++) {
2777 unsigned name = sel->info.output_semantic_name[i];
2778 unsigned index = sel->info.output_semantic_index[i];
2779
2780 switch (name) {
2781 case TGSI_SEMANTIC_TESSINNER:
2782 case TGSI_SEMANTIC_TESSOUTER:
2783 case TGSI_SEMANTIC_PATCH:
2784 sel->patch_outputs_written |=
2785 1ull << si_shader_io_get_unique_index_patch(name, index);
2786 break;
2787
2788 case TGSI_SEMANTIC_GENERIC:
2789 /* don't process indices the function can't handle */
2790 if (index >= SI_MAX_IO_GENERIC)
2791 break;
2792 /* fall through */
2793 default:
2794 sel->outputs_written |=
2795 1ull << si_shader_io_get_unique_index(name, index, false);
2796 sel->outputs_written_before_ps |=
2797 1ull << si_shader_io_get_unique_index(name, index, true);
2798 break;
2799 case TGSI_SEMANTIC_EDGEFLAG:
2800 break;
2801 }
2802 }
2803 sel->esgs_itemsize = util_last_bit64(sel->outputs_written) * 16;
2804 sel->lshs_vertex_stride = sel->esgs_itemsize;
2805
2806 /* Add 1 dword to reduce LDS bank conflicts, so that each vertex
2807 * will start on a different bank. (except for the maximum 32*16).
2808 */
2809 if (sel->lshs_vertex_stride < 32*16)
2810 sel->lshs_vertex_stride += 4;
2811
2812 /* For the ESGS ring in LDS, add 1 dword to reduce LDS bank
2813 * conflicts, i.e. each vertex will start at a different bank.
2814 */
2815 if (sctx->chip_class >= GFX9)
2816 sel->esgs_itemsize += 4;
2817
2818 assert(((sel->esgs_itemsize / 4) & C_028AAC_ITEMSIZE) == 0);
2819
2820 /* Only for TES: */
2821 if (sel->info.properties[TGSI_PROPERTY_TES_POINT_MODE])
2822 sel->rast_prim = PIPE_PRIM_POINTS;
2823 else if (sel->info.properties[TGSI_PROPERTY_TES_PRIM_MODE] == PIPE_PRIM_LINES)
2824 sel->rast_prim = PIPE_PRIM_LINE_STRIP;
2825 else
2826 sel->rast_prim = PIPE_PRIM_TRIANGLES;
2827 break;
2828
2829 case PIPE_SHADER_FRAGMENT:
2830 for (i = 0; i < sel->info.num_inputs; i++) {
2831 unsigned name = sel->info.input_semantic_name[i];
2832 unsigned index = sel->info.input_semantic_index[i];
2833
2834 switch (name) {
2835 case TGSI_SEMANTIC_GENERIC:
2836 /* don't process indices the function can't handle */
2837 if (index >= SI_MAX_IO_GENERIC)
2838 break;
2839 /* fall through */
2840 default:
2841 sel->inputs_read |=
2842 1ull << si_shader_io_get_unique_index(name, index, true);
2843 break;
2844 case TGSI_SEMANTIC_PCOORD: /* ignore this */
2845 break;
2846 }
2847 }
2848
2849 for (i = 0; i < 8; i++)
2850 if (sel->info.colors_written & (1 << i))
2851 sel->colors_written_4bit |= 0xf << (4 * i);
2852
2853 for (i = 0; i < sel->info.num_inputs; i++) {
2854 if (sel->info.input_semantic_name[i] == TGSI_SEMANTIC_COLOR) {
2855 int index = sel->info.input_semantic_index[i];
2856 sel->color_attr_index[index] = i;
2857 }
2858 }
2859 break;
2860 default:;
2861 }
2862
2863 /* PA_CL_VS_OUT_CNTL */
2864 bool misc_vec_ena =
2865 sel->info.writes_psize || sel->pos_writes_edgeflag ||
2866 sel->info.writes_layer || sel->info.writes_viewport_index;
2867 sel->pa_cl_vs_out_cntl =
2868 S_02881C_USE_VTX_POINT_SIZE(sel->info.writes_psize) |
2869 S_02881C_USE_VTX_EDGE_FLAG(sel->pos_writes_edgeflag) |
2870 S_02881C_USE_VTX_RENDER_TARGET_INDX(sel->info.writes_layer) |
2871 S_02881C_USE_VTX_VIEWPORT_INDX(sel->info.writes_viewport_index) |
2872 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
2873 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena);
2874 sel->clipdist_mask = sel->info.writes_clipvertex ?
2875 SIX_BITS : sel->info.clipdist_writemask;
2876 sel->culldist_mask = sel->info.culldist_writemask <<
2877 sel->info.num_written_clipdistance;
2878
2879 /* DB_SHADER_CONTROL */
2880 sel->db_shader_control =
2881 S_02880C_Z_EXPORT_ENABLE(sel->info.writes_z) |
2882 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(sel->info.writes_stencil) |
2883 S_02880C_MASK_EXPORT_ENABLE(sel->info.writes_samplemask) |
2884 S_02880C_KILL_ENABLE(sel->info.uses_kill);
2885
2886 switch (sel->info.properties[TGSI_PROPERTY_FS_DEPTH_LAYOUT]) {
2887 case TGSI_FS_DEPTH_LAYOUT_GREATER:
2888 sel->db_shader_control |=
2889 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_GREATER_THAN_Z);
2890 break;
2891 case TGSI_FS_DEPTH_LAYOUT_LESS:
2892 sel->db_shader_control |=
2893 S_02880C_CONSERVATIVE_Z_EXPORT(V_02880C_EXPORT_LESS_THAN_Z);
2894 break;
2895 }
2896
2897 /* Z_ORDER, EXEC_ON_HIER_FAIL and EXEC_ON_NOOP should be set as following:
2898 *
2899 * | early Z/S | writes_mem | allow_ReZ? | Z_ORDER | EXEC_ON_HIER_FAIL | EXEC_ON_NOOP
2900 * --|-----------|------------|------------|--------------------|-------------------|-------------
2901 * 1a| false | false | true | EarlyZ_Then_ReZ | 0 | 0
2902 * 1b| false | false | false | EarlyZ_Then_LateZ | 0 | 0
2903 * 2 | false | true | n/a | LateZ | 1 | 0
2904 * 3 | true | false | n/a | EarlyZ_Then_LateZ | 0 | 0
2905 * 4 | true | true | n/a | EarlyZ_Then_LateZ | 0 | 1
2906 *
2907 * In cases 3 and 4, HW will force Z_ORDER to EarlyZ regardless of what's set in the register.
2908 * In case 2, NOOP_CULL is a don't care field. In case 2, 3 and 4, ReZ doesn't make sense.
2909 *
2910 * Don't use ReZ without profiling !!!
2911 *
2912 * ReZ decreases performance by 15% in DiRT: Showdown on Ultra settings, which has pretty complex
2913 * shaders.
2914 */
2915 if (sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]) {
2916 /* Cases 3, 4. */
2917 sel->db_shader_control |= S_02880C_DEPTH_BEFORE_SHADER(1) |
2918 S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z) |
2919 S_02880C_EXEC_ON_NOOP(sel->info.writes_memory);
2920 } else if (sel->info.writes_memory) {
2921 /* Case 2. */
2922 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_LATE_Z) |
2923 S_02880C_EXEC_ON_HIER_FAIL(1);
2924 } else {
2925 /* Case 1. */
2926 sel->db_shader_control |= S_02880C_Z_ORDER(V_02880C_EARLY_Z_THEN_LATE_Z);
2927 }
2928
2929 if (sel->info.properties[TGSI_PROPERTY_FS_POST_DEPTH_COVERAGE])
2930 sel->db_shader_control |= S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(1);
2931
2932 (void) mtx_init(&sel->mutex, mtx_plain);
2933
2934 si_schedule_initial_compile(sctx, sel->info.processor, &sel->ready,
2935 &sel->compiler_ctx_state, sel,
2936 si_init_shader_selector_async);
2937 return sel;
2938 }
2939
2940 static void si_update_streamout_state(struct si_context *sctx)
2941 {
2942 struct si_shader_selector *shader_with_so = si_get_vs(sctx)->cso;
2943
2944 if (!shader_with_so)
2945 return;
2946
2947 sctx->streamout.enabled_stream_buffers_mask =
2948 shader_with_so->enabled_streamout_buffer_mask;
2949 sctx->streamout.stride_in_dw = shader_with_so->so.stride;
2950 }
2951
2952 static void si_update_clip_regs(struct si_context *sctx,
2953 struct si_shader_selector *old_hw_vs,
2954 struct si_shader *old_hw_vs_variant,
2955 struct si_shader_selector *next_hw_vs,
2956 struct si_shader *next_hw_vs_variant)
2957 {
2958 if (next_hw_vs &&
2959 (!old_hw_vs ||
2960 old_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] !=
2961 next_hw_vs->info.properties[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION] ||
2962 old_hw_vs->pa_cl_vs_out_cntl != next_hw_vs->pa_cl_vs_out_cntl ||
2963 old_hw_vs->clipdist_mask != next_hw_vs->clipdist_mask ||
2964 old_hw_vs->culldist_mask != next_hw_vs->culldist_mask ||
2965 !old_hw_vs_variant ||
2966 !next_hw_vs_variant ||
2967 old_hw_vs_variant->key.opt.clip_disable !=
2968 next_hw_vs_variant->key.opt.clip_disable))
2969 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
2970 }
2971
2972 static void si_update_common_shader_state(struct si_context *sctx)
2973 {
2974 sctx->uses_bindless_samplers =
2975 si_shader_uses_bindless_samplers(sctx->vs_shader.cso) ||
2976 si_shader_uses_bindless_samplers(sctx->gs_shader.cso) ||
2977 si_shader_uses_bindless_samplers(sctx->ps_shader.cso) ||
2978 si_shader_uses_bindless_samplers(sctx->tcs_shader.cso) ||
2979 si_shader_uses_bindless_samplers(sctx->tes_shader.cso);
2980 sctx->uses_bindless_images =
2981 si_shader_uses_bindless_images(sctx->vs_shader.cso) ||
2982 si_shader_uses_bindless_images(sctx->gs_shader.cso) ||
2983 si_shader_uses_bindless_images(sctx->ps_shader.cso) ||
2984 si_shader_uses_bindless_images(sctx->tcs_shader.cso) ||
2985 si_shader_uses_bindless_images(sctx->tes_shader.cso);
2986 sctx->do_update_shaders = true;
2987 }
2988
2989 static void si_bind_vs_shader(struct pipe_context *ctx, void *state)
2990 {
2991 struct si_context *sctx = (struct si_context *)ctx;
2992 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
2993 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
2994 struct si_shader_selector *sel = state;
2995
2996 if (sctx->vs_shader.cso == sel)
2997 return;
2998
2999 sctx->vs_shader.cso = sel;
3000 sctx->vs_shader.current = sel ? sel->first_variant : NULL;
3001 sctx->num_vs_blit_sgprs = sel ? sel->info.properties[TGSI_PROPERTY_VS_BLIT_SGPRS_AMD] : 0;
3002
3003 if (si_update_ngg(sctx))
3004 si_shader_change_notify(sctx);
3005
3006 si_update_common_shader_state(sctx);
3007 si_update_vs_viewport_state(sctx);
3008 si_set_active_descriptors_for_shader(sctx, sel);
3009 si_update_streamout_state(sctx);
3010 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3011 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3012 }
3013
3014 static void si_update_tess_uses_prim_id(struct si_context *sctx)
3015 {
3016 sctx->ia_multi_vgt_param_key.u.tess_uses_prim_id =
3017 (sctx->tes_shader.cso &&
3018 sctx->tes_shader.cso->info.uses_primid) ||
3019 (sctx->tcs_shader.cso &&
3020 sctx->tcs_shader.cso->info.uses_primid) ||
3021 (sctx->gs_shader.cso &&
3022 sctx->gs_shader.cso->info.uses_primid) ||
3023 (sctx->ps_shader.cso && !sctx->gs_shader.cso &&
3024 sctx->ps_shader.cso->info.uses_primid);
3025 }
3026
3027 bool si_update_ngg(struct si_context *sctx)
3028 {
3029 if (!sctx->screen->use_ngg) {
3030 assert(!sctx->ngg);
3031 return false;
3032 }
3033
3034 bool new_ngg = true;
3035
3036 if (sctx->gs_shader.cso && sctx->tes_shader.cso &&
3037 sctx->gs_shader.cso->tess_turns_off_ngg) {
3038 new_ngg = false;
3039 } else if (!sctx->screen->use_ngg_streamout) {
3040 struct si_shader_selector *last = si_get_vs(sctx)->cso;
3041
3042 if ((last && last->so.num_outputs) ||
3043 sctx->streamout.prims_gen_query_enabled)
3044 new_ngg = false;
3045 }
3046
3047 if (new_ngg != sctx->ngg) {
3048 /* Transitioning from NGG to legacy GS requires VGT_FLUSH on Navi10-14.
3049 * VGT_FLUSH is also emitted at the beginning of IBs when legacy GS ring
3050 * pointers are set.
3051 */
3052 if ((sctx->family == CHIP_NAVI10 ||
3053 sctx->family == CHIP_NAVI12 ||
3054 sctx->family == CHIP_NAVI14) &&
3055 !new_ngg)
3056 sctx->flags |= SI_CONTEXT_VGT_FLUSH;
3057
3058 sctx->ngg = new_ngg;
3059 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3060 return true;
3061 }
3062 return false;
3063 }
3064
3065 static void si_bind_gs_shader(struct pipe_context *ctx, void *state)
3066 {
3067 struct si_context *sctx = (struct si_context *)ctx;
3068 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3069 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3070 struct si_shader_selector *sel = state;
3071 bool enable_changed = !!sctx->gs_shader.cso != !!sel;
3072 bool ngg_changed;
3073
3074 if (sctx->gs_shader.cso == sel)
3075 return;
3076
3077 sctx->gs_shader.cso = sel;
3078 sctx->gs_shader.current = sel ? sel->first_variant : NULL;
3079 sctx->ia_multi_vgt_param_key.u.uses_gs = sel != NULL;
3080
3081 si_update_common_shader_state(sctx);
3082 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3083
3084 ngg_changed = si_update_ngg(sctx);
3085 if (ngg_changed || enable_changed)
3086 si_shader_change_notify(sctx);
3087 if (enable_changed) {
3088 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3089 si_update_tess_uses_prim_id(sctx);
3090 }
3091 si_update_vs_viewport_state(sctx);
3092 si_set_active_descriptors_for_shader(sctx, sel);
3093 si_update_streamout_state(sctx);
3094 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3095 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3096 }
3097
3098 static void si_bind_tcs_shader(struct pipe_context *ctx, void *state)
3099 {
3100 struct si_context *sctx = (struct si_context *)ctx;
3101 struct si_shader_selector *sel = state;
3102 bool enable_changed = !!sctx->tcs_shader.cso != !!sel;
3103
3104 if (sctx->tcs_shader.cso == sel)
3105 return;
3106
3107 sctx->tcs_shader.cso = sel;
3108 sctx->tcs_shader.current = sel ? sel->first_variant : NULL;
3109 si_update_tess_uses_prim_id(sctx);
3110
3111 si_update_common_shader_state(sctx);
3112
3113 if (enable_changed)
3114 sctx->last_tcs = NULL; /* invalidate derived tess state */
3115
3116 si_set_active_descriptors_for_shader(sctx, sel);
3117 }
3118
3119 static void si_bind_tes_shader(struct pipe_context *ctx, void *state)
3120 {
3121 struct si_context *sctx = (struct si_context *)ctx;
3122 struct si_shader_selector *old_hw_vs = si_get_vs(sctx)->cso;
3123 struct si_shader *old_hw_vs_variant = si_get_vs_state(sctx);
3124 struct si_shader_selector *sel = state;
3125 bool enable_changed = !!sctx->tes_shader.cso != !!sel;
3126
3127 if (sctx->tes_shader.cso == sel)
3128 return;
3129
3130 sctx->tes_shader.cso = sel;
3131 sctx->tes_shader.current = sel ? sel->first_variant : NULL;
3132 sctx->ia_multi_vgt_param_key.u.uses_tess = sel != NULL;
3133 si_update_tess_uses_prim_id(sctx);
3134
3135 si_update_common_shader_state(sctx);
3136 sctx->last_rast_prim = -1; /* reset this so that it gets updated */
3137
3138 bool ngg_changed = si_update_ngg(sctx);
3139 if (ngg_changed || enable_changed)
3140 si_shader_change_notify(sctx);
3141 if (enable_changed)
3142 sctx->last_tes_sh_base = -1; /* invalidate derived tess state */
3143 si_update_vs_viewport_state(sctx);
3144 si_set_active_descriptors_for_shader(sctx, sel);
3145 si_update_streamout_state(sctx);
3146 si_update_clip_regs(sctx, old_hw_vs, old_hw_vs_variant,
3147 si_get_vs(sctx)->cso, si_get_vs_state(sctx));
3148 }
3149
3150 static void si_bind_ps_shader(struct pipe_context *ctx, void *state)
3151 {
3152 struct si_context *sctx = (struct si_context *)ctx;
3153 struct si_shader_selector *old_sel = sctx->ps_shader.cso;
3154 struct si_shader_selector *sel = state;
3155
3156 /* skip if supplied shader is one already in use */
3157 if (old_sel == sel)
3158 return;
3159
3160 sctx->ps_shader.cso = sel;
3161 sctx->ps_shader.current = sel ? sel->first_variant : NULL;
3162
3163 si_update_common_shader_state(sctx);
3164 if (sel) {
3165 if (sctx->ia_multi_vgt_param_key.u.uses_tess)
3166 si_update_tess_uses_prim_id(sctx);
3167
3168 if (!old_sel ||
3169 old_sel->info.colors_written != sel->info.colors_written)
3170 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
3171
3172 if (sctx->screen->has_out_of_order_rast &&
3173 (!old_sel ||
3174 old_sel->info.writes_memory != sel->info.writes_memory ||
3175 old_sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL] !=
3176 sel->info.properties[TGSI_PROPERTY_FS_EARLY_DEPTH_STENCIL]))
3177 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
3178 }
3179 si_set_active_descriptors_for_shader(sctx, sel);
3180 si_update_ps_colorbuf0_slot(sctx);
3181 }
3182
3183 static void si_delete_shader(struct si_context *sctx, struct si_shader *shader)
3184 {
3185 if (shader->is_optimized) {
3186 util_queue_drop_job(&sctx->screen->shader_compiler_queue_low_priority,
3187 &shader->ready);
3188 }
3189
3190 util_queue_fence_destroy(&shader->ready);
3191
3192 if (shader->pm4) {
3193 /* If destroyed shaders were not unbound, the next compiled
3194 * shader variant could get the same pointer address and so
3195 * binding it to the same shader stage would be considered
3196 * a no-op, causing random behavior.
3197 */
3198 switch (shader->selector->type) {
3199 case PIPE_SHADER_VERTEX:
3200 if (shader->key.as_ls) {
3201 assert(sctx->chip_class <= GFX8);
3202 si_pm4_delete_state(sctx, ls, shader->pm4);
3203 } else if (shader->key.as_es) {
3204 assert(sctx->chip_class <= GFX8);
3205 si_pm4_delete_state(sctx, es, shader->pm4);
3206 } else if (shader->key.as_ngg) {
3207 si_pm4_delete_state(sctx, gs, shader->pm4);
3208 } else {
3209 si_pm4_delete_state(sctx, vs, shader->pm4);
3210 }
3211 break;
3212 case PIPE_SHADER_TESS_CTRL:
3213 si_pm4_delete_state(sctx, hs, shader->pm4);
3214 break;
3215 case PIPE_SHADER_TESS_EVAL:
3216 if (shader->key.as_es) {
3217 assert(sctx->chip_class <= GFX8);
3218 si_pm4_delete_state(sctx, es, shader->pm4);
3219 } else if (shader->key.as_ngg) {
3220 si_pm4_delete_state(sctx, gs, shader->pm4);
3221 } else {
3222 si_pm4_delete_state(sctx, vs, shader->pm4);
3223 }
3224 break;
3225 case PIPE_SHADER_GEOMETRY:
3226 if (shader->is_gs_copy_shader)
3227 si_pm4_delete_state(sctx, vs, shader->pm4);
3228 else
3229 si_pm4_delete_state(sctx, gs, shader->pm4);
3230 break;
3231 case PIPE_SHADER_FRAGMENT:
3232 si_pm4_delete_state(sctx, ps, shader->pm4);
3233 break;
3234 default:;
3235 }
3236 }
3237
3238 si_shader_selector_reference(sctx, &shader->previous_stage_sel, NULL);
3239 si_shader_destroy(shader);
3240 free(shader);
3241 }
3242
3243 void si_destroy_shader_selector(struct si_context *sctx,
3244 struct si_shader_selector *sel)
3245 {
3246 struct si_shader *p = sel->first_variant, *c;
3247 struct si_shader_ctx_state *current_shader[SI_NUM_SHADERS] = {
3248 [PIPE_SHADER_VERTEX] = &sctx->vs_shader,
3249 [PIPE_SHADER_TESS_CTRL] = &sctx->tcs_shader,
3250 [PIPE_SHADER_TESS_EVAL] = &sctx->tes_shader,
3251 [PIPE_SHADER_GEOMETRY] = &sctx->gs_shader,
3252 [PIPE_SHADER_FRAGMENT] = &sctx->ps_shader,
3253 };
3254
3255 util_queue_drop_job(&sctx->screen->shader_compiler_queue, &sel->ready);
3256
3257 if (current_shader[sel->type]->cso == sel) {
3258 current_shader[sel->type]->cso = NULL;
3259 current_shader[sel->type]->current = NULL;
3260 }
3261
3262 while (p) {
3263 c = p->next_variant;
3264 si_delete_shader(sctx, p);
3265 p = c;
3266 }
3267
3268 if (sel->main_shader_part)
3269 si_delete_shader(sctx, sel->main_shader_part);
3270 if (sel->main_shader_part_ls)
3271 si_delete_shader(sctx, sel->main_shader_part_ls);
3272 if (sel->main_shader_part_es)
3273 si_delete_shader(sctx, sel->main_shader_part_es);
3274 if (sel->main_shader_part_ngg)
3275 si_delete_shader(sctx, sel->main_shader_part_ngg);
3276 if (sel->gs_copy_shader)
3277 si_delete_shader(sctx, sel->gs_copy_shader);
3278
3279 util_queue_fence_destroy(&sel->ready);
3280 mtx_destroy(&sel->mutex);
3281 free(sel->tokens);
3282 ralloc_free(sel->nir);
3283 free(sel);
3284 }
3285
3286 static void si_delete_shader_selector(struct pipe_context *ctx, void *state)
3287 {
3288 struct si_context *sctx = (struct si_context *)ctx;
3289 struct si_shader_selector *sel = (struct si_shader_selector *)state;
3290
3291 si_shader_selector_reference(sctx, &sel, NULL);
3292 }
3293
3294 static unsigned si_get_ps_input_cntl(struct si_context *sctx,
3295 struct si_shader *vs, unsigned name,
3296 unsigned index, unsigned interpolate)
3297 {
3298 struct tgsi_shader_info *vsinfo = &vs->selector->info;
3299 unsigned j, offset, ps_input_cntl = 0;
3300
3301 if (interpolate == TGSI_INTERPOLATE_CONSTANT ||
3302 (interpolate == TGSI_INTERPOLATE_COLOR && sctx->flatshade) ||
3303 name == TGSI_SEMANTIC_PRIMID)
3304 ps_input_cntl |= S_028644_FLAT_SHADE(1);
3305
3306 if (name == TGSI_SEMANTIC_PCOORD ||
3307 (name == TGSI_SEMANTIC_TEXCOORD &&
3308 sctx->sprite_coord_enable & (1 << index))) {
3309 ps_input_cntl |= S_028644_PT_SPRITE_TEX(1);
3310 }
3311
3312 for (j = 0; j < vsinfo->num_outputs; j++) {
3313 if (name == vsinfo->output_semantic_name[j] &&
3314 index == vsinfo->output_semantic_index[j]) {
3315 offset = vs->info.vs_output_param_offset[j];
3316
3317 if (offset <= AC_EXP_PARAM_OFFSET_31) {
3318 /* The input is loaded from parameter memory. */
3319 ps_input_cntl |= S_028644_OFFSET(offset);
3320 } else if (!G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3321 if (offset == AC_EXP_PARAM_UNDEFINED) {
3322 /* This can happen with depth-only rendering. */
3323 offset = 0;
3324 } else {
3325 /* The input is a DEFAULT_VAL constant. */
3326 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
3327 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
3328 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
3329 }
3330
3331 ps_input_cntl = S_028644_OFFSET(0x20) |
3332 S_028644_DEFAULT_VAL(offset);
3333 }
3334 break;
3335 }
3336 }
3337
3338 if (j == vsinfo->num_outputs && name == TGSI_SEMANTIC_PRIMID)
3339 /* PrimID is written after the last output when HW VS is used. */
3340 ps_input_cntl |= S_028644_OFFSET(vs->info.vs_output_param_offset[vsinfo->num_outputs]);
3341 else if (j == vsinfo->num_outputs && !G_028644_PT_SPRITE_TEX(ps_input_cntl)) {
3342 /* No corresponding output found, load defaults into input.
3343 * Don't set any other bits.
3344 * (FLAT_SHADE=1 completely changes behavior) */
3345 ps_input_cntl = S_028644_OFFSET(0x20);
3346 /* D3D 9 behaviour. GL is undefined */
3347 if (name == TGSI_SEMANTIC_COLOR && index == 0)
3348 ps_input_cntl |= S_028644_DEFAULT_VAL(3);
3349 }
3350 return ps_input_cntl;
3351 }
3352
3353 static void si_emit_spi_map(struct si_context *sctx)
3354 {
3355 struct si_shader *ps = sctx->ps_shader.current;
3356 struct si_shader *vs = si_get_vs_state(sctx);
3357 struct tgsi_shader_info *psinfo = ps ? &ps->selector->info : NULL;
3358 unsigned i, num_interp, num_written = 0, bcol_interp[2];
3359 unsigned spi_ps_input_cntl[32];
3360
3361 if (!ps || !ps->selector->info.num_inputs)
3362 return;
3363
3364 num_interp = si_get_ps_num_interp(ps);
3365 assert(num_interp > 0);
3366
3367 for (i = 0; i < psinfo->num_inputs; i++) {
3368 unsigned name = psinfo->input_semantic_name[i];
3369 unsigned index = psinfo->input_semantic_index[i];
3370 unsigned interpolate = psinfo->input_interpolate[i];
3371
3372 spi_ps_input_cntl[num_written++] = si_get_ps_input_cntl(sctx, vs, name,
3373 index, interpolate);
3374
3375 if (name == TGSI_SEMANTIC_COLOR) {
3376 assert(index < ARRAY_SIZE(bcol_interp));
3377 bcol_interp[index] = interpolate;
3378 }
3379 }
3380
3381 if (ps->key.part.ps.prolog.color_two_side) {
3382 unsigned bcol = TGSI_SEMANTIC_BCOLOR;
3383
3384 for (i = 0; i < 2; i++) {
3385 if (!(psinfo->colors_read & (0xf << (i * 4))))
3386 continue;
3387
3388 spi_ps_input_cntl[num_written++] =
3389 si_get_ps_input_cntl(sctx, vs, bcol, i, bcol_interp[i]);
3390
3391 }
3392 }
3393 assert(num_interp == num_written);
3394
3395 /* R_028644_SPI_PS_INPUT_CNTL_0 */
3396 /* Dota 2: Only ~16% of SPI map updates set different values. */
3397 /* Talos: Only ~9% of SPI map updates set different values. */
3398 unsigned initial_cdw = sctx->gfx_cs->current.cdw;
3399 radeon_opt_set_context_regn(sctx, R_028644_SPI_PS_INPUT_CNTL_0,
3400 spi_ps_input_cntl,
3401 sctx->tracked_regs.spi_ps_input_cntl, num_interp);
3402
3403 if (initial_cdw != sctx->gfx_cs->current.cdw)
3404 sctx->context_roll = true;
3405 }
3406
3407 /**
3408 * Writing CONFIG or UCONFIG VGT registers requires VGT_FLUSH before that.
3409 */
3410 static void si_init_config_add_vgt_flush(struct si_context *sctx)
3411 {
3412 if (sctx->init_config_has_vgt_flush)
3413 return;
3414
3415 /* Done by Vulkan before VGT_FLUSH. */
3416 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3417 si_pm4_cmd_add(sctx->init_config,
3418 EVENT_TYPE(V_028A90_VS_PARTIAL_FLUSH) | EVENT_INDEX(4));
3419 si_pm4_cmd_end(sctx->init_config, false);
3420
3421 /* VGT_FLUSH is required even if VGT is idle. It resets VGT pointers. */
3422 si_pm4_cmd_begin(sctx->init_config, PKT3_EVENT_WRITE);
3423 si_pm4_cmd_add(sctx->init_config, EVENT_TYPE(V_028A90_VGT_FLUSH) | EVENT_INDEX(0));
3424 si_pm4_cmd_end(sctx->init_config, false);
3425 sctx->init_config_has_vgt_flush = true;
3426 }
3427
3428 /* Initialize state related to ESGS / GSVS ring buffers */
3429 static bool si_update_gs_ring_buffers(struct si_context *sctx)
3430 {
3431 struct si_shader_selector *es =
3432 sctx->tes_shader.cso ? sctx->tes_shader.cso : sctx->vs_shader.cso;
3433 struct si_shader_selector *gs = sctx->gs_shader.cso;
3434 struct si_pm4_state *pm4;
3435
3436 /* Chip constants. */
3437 unsigned num_se = sctx->screen->info.max_se;
3438 unsigned wave_size = 64;
3439 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
3440 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
3441 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
3442 */
3443 unsigned gs_vertex_reuse = (sctx->chip_class >= GFX8 ? 32 : 16) * num_se;
3444 unsigned alignment = 256 * num_se;
3445 /* The maximum size is 63.999 MB per SE. */
3446 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
3447
3448 /* Calculate the minimum size. */
3449 unsigned min_esgs_ring_size = align(es->esgs_itemsize * gs_vertex_reuse *
3450 wave_size, alignment);
3451
3452 /* These are recommended sizes, not minimum sizes. */
3453 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
3454 es->esgs_itemsize * gs->gs_input_verts_per_prim;
3455 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
3456 gs->max_gsvs_emit_size;
3457
3458 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
3459 esgs_ring_size = align(esgs_ring_size, alignment);
3460 gsvs_ring_size = align(gsvs_ring_size, alignment);
3461
3462 esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
3463 gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
3464
3465 /* Some rings don't have to be allocated if shaders don't use them.
3466 * (e.g. no varyings between ES and GS or GS and VS)
3467 *
3468 * GFX9 doesn't have the ESGS ring.
3469 */
3470 bool update_esgs = sctx->chip_class <= GFX8 &&
3471 esgs_ring_size &&
3472 (!sctx->esgs_ring ||
3473 sctx->esgs_ring->width0 < esgs_ring_size);
3474 bool update_gsvs = gsvs_ring_size &&
3475 (!sctx->gsvs_ring ||
3476 sctx->gsvs_ring->width0 < gsvs_ring_size);
3477
3478 if (!update_esgs && !update_gsvs)
3479 return true;
3480
3481 if (update_esgs) {
3482 pipe_resource_reference(&sctx->esgs_ring, NULL);
3483 sctx->esgs_ring =
3484 pipe_aligned_buffer_create(sctx->b.screen,
3485 SI_RESOURCE_FLAG_UNMAPPABLE,
3486 PIPE_USAGE_DEFAULT,
3487 esgs_ring_size, alignment);
3488 if (!sctx->esgs_ring)
3489 return false;
3490 }
3491
3492 if (update_gsvs) {
3493 pipe_resource_reference(&sctx->gsvs_ring, NULL);
3494 sctx->gsvs_ring =
3495 pipe_aligned_buffer_create(sctx->b.screen,
3496 SI_RESOURCE_FLAG_UNMAPPABLE,
3497 PIPE_USAGE_DEFAULT,
3498 gsvs_ring_size, alignment);
3499 if (!sctx->gsvs_ring)
3500 return false;
3501 }
3502
3503 /* Create the "init_config_gs_rings" state. */
3504 pm4 = CALLOC_STRUCT(si_pm4_state);
3505 if (!pm4)
3506 return false;
3507
3508 if (sctx->chip_class >= GFX7) {
3509 if (sctx->esgs_ring) {
3510 assert(sctx->chip_class <= GFX8);
3511 si_pm4_set_reg(pm4, R_030900_VGT_ESGS_RING_SIZE,
3512 sctx->esgs_ring->width0 / 256);
3513 }
3514 if (sctx->gsvs_ring)
3515 si_pm4_set_reg(pm4, R_030904_VGT_GSVS_RING_SIZE,
3516 sctx->gsvs_ring->width0 / 256);
3517 } else {
3518 if (sctx->esgs_ring)
3519 si_pm4_set_reg(pm4, R_0088C8_VGT_ESGS_RING_SIZE,
3520 sctx->esgs_ring->width0 / 256);
3521 if (sctx->gsvs_ring)
3522 si_pm4_set_reg(pm4, R_0088CC_VGT_GSVS_RING_SIZE,
3523 sctx->gsvs_ring->width0 / 256);
3524 }
3525
3526 /* Set the state. */
3527 if (sctx->init_config_gs_rings)
3528 si_pm4_free_state(sctx, sctx->init_config_gs_rings, ~0);
3529 sctx->init_config_gs_rings = pm4;
3530
3531 if (!sctx->init_config_has_vgt_flush) {
3532 si_init_config_add_vgt_flush(sctx);
3533 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3534 }
3535
3536 /* Flush the context to re-emit both init_config states. */
3537 sctx->initial_gfx_cs_size = 0; /* force flush */
3538 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3539
3540 /* Set ring bindings. */
3541 if (sctx->esgs_ring) {
3542 assert(sctx->chip_class <= GFX8);
3543 si_set_ring_buffer(sctx, SI_ES_RING_ESGS,
3544 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3545 true, true, 4, 64, 0);
3546 si_set_ring_buffer(sctx, SI_GS_RING_ESGS,
3547 sctx->esgs_ring, 0, sctx->esgs_ring->width0,
3548 false, false, 0, 0, 0);
3549 }
3550 if (sctx->gsvs_ring) {
3551 si_set_ring_buffer(sctx, SI_RING_GSVS,
3552 sctx->gsvs_ring, 0, sctx->gsvs_ring->width0,
3553 false, false, 0, 0, 0);
3554 }
3555
3556 return true;
3557 }
3558
3559 static void si_shader_lock(struct si_shader *shader)
3560 {
3561 mtx_lock(&shader->selector->mutex);
3562 if (shader->previous_stage_sel) {
3563 assert(shader->previous_stage_sel != shader->selector);
3564 mtx_lock(&shader->previous_stage_sel->mutex);
3565 }
3566 }
3567
3568 static void si_shader_unlock(struct si_shader *shader)
3569 {
3570 if (shader->previous_stage_sel)
3571 mtx_unlock(&shader->previous_stage_sel->mutex);
3572 mtx_unlock(&shader->selector->mutex);
3573 }
3574
3575 /**
3576 * @returns 1 if \p sel has been updated to use a new scratch buffer
3577 * 0 if not
3578 * < 0 if there was a failure
3579 */
3580 static int si_update_scratch_buffer(struct si_context *sctx,
3581 struct si_shader *shader)
3582 {
3583 uint64_t scratch_va = sctx->scratch_buffer->gpu_address;
3584
3585 if (!shader)
3586 return 0;
3587
3588 /* This shader doesn't need a scratch buffer */
3589 if (shader->config.scratch_bytes_per_wave == 0)
3590 return 0;
3591
3592 /* Prevent race conditions when updating:
3593 * - si_shader::scratch_bo
3594 * - si_shader::binary::code
3595 * - si_shader::previous_stage::binary::code.
3596 */
3597 si_shader_lock(shader);
3598
3599 /* This shader is already configured to use the current
3600 * scratch buffer. */
3601 if (shader->scratch_bo == sctx->scratch_buffer) {
3602 si_shader_unlock(shader);
3603 return 0;
3604 }
3605
3606 assert(sctx->scratch_buffer);
3607
3608 /* Replace the shader bo with a new bo that has the relocs applied. */
3609 if (!si_shader_binary_upload(sctx->screen, shader, scratch_va)) {
3610 si_shader_unlock(shader);
3611 return -1;
3612 }
3613
3614 /* Update the shader state to use the new shader bo. */
3615 si_shader_init_pm4_state(sctx->screen, shader);
3616
3617 si_resource_reference(&shader->scratch_bo, sctx->scratch_buffer);
3618
3619 si_shader_unlock(shader);
3620 return 1;
3621 }
3622
3623 static unsigned si_get_current_scratch_buffer_size(struct si_context *sctx)
3624 {
3625 return sctx->scratch_buffer ? sctx->scratch_buffer->b.b.width0 : 0;
3626 }
3627
3628 static unsigned si_get_scratch_buffer_bytes_per_wave(struct si_shader *shader)
3629 {
3630 return shader ? shader->config.scratch_bytes_per_wave : 0;
3631 }
3632
3633 static struct si_shader *si_get_tcs_current(struct si_context *sctx)
3634 {
3635 if (!sctx->tes_shader.cso)
3636 return NULL; /* tessellation disabled */
3637
3638 return sctx->tcs_shader.cso ? sctx->tcs_shader.current :
3639 sctx->fixed_func_tcs_shader.current;
3640 }
3641
3642 static unsigned si_get_max_scratch_bytes_per_wave(struct si_context *sctx)
3643 {
3644 unsigned bytes = 0;
3645
3646 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->ps_shader.current));
3647 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->gs_shader.current));
3648 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->vs_shader.current));
3649 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(sctx->tes_shader.current));
3650
3651 if (sctx->tes_shader.cso) {
3652 struct si_shader *tcs = si_get_tcs_current(sctx);
3653
3654 bytes = MAX2(bytes, si_get_scratch_buffer_bytes_per_wave(tcs));
3655 }
3656 return bytes;
3657 }
3658
3659 static bool si_update_scratch_relocs(struct si_context *sctx)
3660 {
3661 struct si_shader *tcs = si_get_tcs_current(sctx);
3662 int r;
3663
3664 /* Update the shaders, so that they are using the latest scratch.
3665 * The scratch buffer may have been changed since these shaders were
3666 * last used, so we still need to try to update them, even if they
3667 * require scratch buffers smaller than the current size.
3668 */
3669 r = si_update_scratch_buffer(sctx, sctx->ps_shader.current);
3670 if (r < 0)
3671 return false;
3672 if (r == 1)
3673 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
3674
3675 r = si_update_scratch_buffer(sctx, sctx->gs_shader.current);
3676 if (r < 0)
3677 return false;
3678 if (r == 1)
3679 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3680
3681 r = si_update_scratch_buffer(sctx, tcs);
3682 if (r < 0)
3683 return false;
3684 if (r == 1)
3685 si_pm4_bind_state(sctx, hs, tcs->pm4);
3686
3687 /* VS can be bound as LS, ES, or VS. */
3688 r = si_update_scratch_buffer(sctx, sctx->vs_shader.current);
3689 if (r < 0)
3690 return false;
3691 if (r == 1) {
3692 if (sctx->vs_shader.current->key.as_ls)
3693 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3694 else if (sctx->vs_shader.current->key.as_es)
3695 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3696 else if (sctx->vs_shader.current->key.as_ngg)
3697 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3698 else
3699 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3700 }
3701
3702 /* TES can be bound as ES or VS. */
3703 r = si_update_scratch_buffer(sctx, sctx->tes_shader.current);
3704 if (r < 0)
3705 return false;
3706 if (r == 1) {
3707 if (sctx->tes_shader.current->key.as_es)
3708 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3709 else if (sctx->tes_shader.current->key.as_ngg)
3710 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3711 else
3712 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3713 }
3714
3715 return true;
3716 }
3717
3718 static bool si_update_spi_tmpring_size(struct si_context *sctx)
3719 {
3720 unsigned current_scratch_buffer_size =
3721 si_get_current_scratch_buffer_size(sctx);
3722 unsigned scratch_bytes_per_wave =
3723 si_get_max_scratch_bytes_per_wave(sctx);
3724 unsigned scratch_needed_size = scratch_bytes_per_wave *
3725 sctx->scratch_waves;
3726 unsigned spi_tmpring_size;
3727
3728 if (scratch_needed_size > 0) {
3729 if (scratch_needed_size > current_scratch_buffer_size) {
3730 /* Create a bigger scratch buffer */
3731 si_resource_reference(&sctx->scratch_buffer, NULL);
3732
3733 sctx->scratch_buffer =
3734 si_aligned_buffer_create(&sctx->screen->b,
3735 SI_RESOURCE_FLAG_UNMAPPABLE,
3736 PIPE_USAGE_DEFAULT,
3737 scratch_needed_size, 256);
3738 if (!sctx->scratch_buffer)
3739 return false;
3740
3741 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3742 si_context_add_resource_size(sctx,
3743 &sctx->scratch_buffer->b.b);
3744 }
3745
3746 if (!si_update_scratch_relocs(sctx))
3747 return false;
3748 }
3749
3750 /* The LLVM shader backend should be reporting aligned scratch_sizes. */
3751 assert((scratch_needed_size & ~0x3FF) == scratch_needed_size &&
3752 "scratch size should already be aligned correctly.");
3753
3754 spi_tmpring_size = S_0286E8_WAVES(sctx->scratch_waves) |
3755 S_0286E8_WAVESIZE(scratch_bytes_per_wave >> 10);
3756 if (spi_tmpring_size != sctx->spi_tmpring_size) {
3757 sctx->spi_tmpring_size = spi_tmpring_size;
3758 si_mark_atom_dirty(sctx, &sctx->atoms.s.scratch_state);
3759 }
3760 return true;
3761 }
3762
3763 static void si_init_tess_factor_ring(struct si_context *sctx)
3764 {
3765 assert(!sctx->tess_rings);
3766 assert(((sctx->screen->tess_factor_ring_size / 4) & C_030938_SIZE) == 0);
3767
3768 /* The address must be aligned to 2^19, because the shader only
3769 * receives the high 13 bits.
3770 */
3771 sctx->tess_rings = pipe_aligned_buffer_create(sctx->b.screen,
3772 SI_RESOURCE_FLAG_32BIT,
3773 PIPE_USAGE_DEFAULT,
3774 sctx->screen->tess_offchip_ring_size +
3775 sctx->screen->tess_factor_ring_size,
3776 1 << 19);
3777 if (!sctx->tess_rings)
3778 return;
3779
3780 si_init_config_add_vgt_flush(sctx);
3781
3782 si_pm4_add_bo(sctx->init_config, si_resource(sctx->tess_rings),
3783 RADEON_USAGE_READWRITE, RADEON_PRIO_SHADER_RINGS);
3784
3785 uint64_t factor_va = si_resource(sctx->tess_rings)->gpu_address +
3786 sctx->screen->tess_offchip_ring_size;
3787
3788 /* Append these registers to the init config state. */
3789 if (sctx->chip_class >= GFX7) {
3790 si_pm4_set_reg(sctx->init_config, R_030938_VGT_TF_RING_SIZE,
3791 S_030938_SIZE(sctx->screen->tess_factor_ring_size / 4));
3792 si_pm4_set_reg(sctx->init_config, R_030940_VGT_TF_MEMORY_BASE,
3793 factor_va >> 8);
3794 if (sctx->chip_class >= GFX10)
3795 si_pm4_set_reg(sctx->init_config, R_030984_VGT_TF_MEMORY_BASE_HI_UMD,
3796 S_030984_BASE_HI(factor_va >> 40));
3797 else if (sctx->chip_class == GFX9)
3798 si_pm4_set_reg(sctx->init_config, R_030944_VGT_TF_MEMORY_BASE_HI,
3799 S_030944_BASE_HI(factor_va >> 40));
3800 si_pm4_set_reg(sctx->init_config, R_03093C_VGT_HS_OFFCHIP_PARAM,
3801 sctx->screen->vgt_hs_offchip_param);
3802 } else {
3803 si_pm4_set_reg(sctx->init_config, R_008988_VGT_TF_RING_SIZE,
3804 S_008988_SIZE(sctx->screen->tess_factor_ring_size / 4));
3805 si_pm4_set_reg(sctx->init_config, R_0089B8_VGT_TF_MEMORY_BASE,
3806 factor_va >> 8);
3807 si_pm4_set_reg(sctx->init_config, R_0089B0_VGT_HS_OFFCHIP_PARAM,
3808 sctx->screen->vgt_hs_offchip_param);
3809 }
3810
3811 /* Flush the context to re-emit the init_config state.
3812 * This is done only once in a lifetime of a context.
3813 */
3814 si_pm4_upload_indirect_buffer(sctx, sctx->init_config);
3815 sctx->initial_gfx_cs_size = 0; /* force flush */
3816 si_flush_gfx_cs(sctx, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW, NULL);
3817 }
3818
3819 static struct si_pm4_state *si_build_vgt_shader_config(struct si_screen *screen,
3820 union si_vgt_stages_key key)
3821 {
3822 struct si_pm4_state *pm4 = CALLOC_STRUCT(si_pm4_state);
3823 uint32_t stages = 0;
3824
3825 if (key.u.tess) {
3826 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
3827 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
3828
3829 if (key.u.gs)
3830 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
3831 S_028B54_GS_EN(1);
3832 else if (key.u.ngg)
3833 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
3834 else
3835 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
3836 } else if (key.u.gs) {
3837 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
3838 S_028B54_GS_EN(1);
3839 } else if (key.u.ngg) {
3840 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
3841 }
3842
3843 if (key.u.ngg) {
3844 stages |= S_028B54_PRIMGEN_EN(1);
3845 if (key.u.streamout)
3846 stages |= S_028B54_NGG_WAVE_ID_EN(1);
3847 } else if (key.u.gs)
3848 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
3849
3850 if (screen->info.chip_class >= GFX9)
3851 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
3852
3853 if (screen->info.chip_class >= GFX10 && screen->ge_wave_size == 32) {
3854 stages |= S_028B54_HS_W32_EN(1) |
3855 S_028B54_GS_W32_EN(key.u.ngg) | /* legacy GS only supports Wave64 */
3856 S_028B54_VS_W32_EN(1);
3857 }
3858
3859 si_pm4_set_reg(pm4, R_028B54_VGT_SHADER_STAGES_EN, stages);
3860 return pm4;
3861 }
3862
3863 static void si_update_vgt_shader_config(struct si_context *sctx,
3864 union si_vgt_stages_key key)
3865 {
3866 struct si_pm4_state **pm4 = &sctx->vgt_shader_config[key.index];
3867
3868 if (unlikely(!*pm4))
3869 *pm4 = si_build_vgt_shader_config(sctx->screen, key);
3870 si_pm4_bind_state(sctx, vgt_shader_config, *pm4);
3871 }
3872
3873 bool si_update_shaders(struct si_context *sctx)
3874 {
3875 struct pipe_context *ctx = (struct pipe_context*)sctx;
3876 struct si_compiler_ctx_state compiler_state;
3877 struct si_state_rasterizer *rs = sctx->queued.named.rasterizer;
3878 struct si_shader *old_vs = si_get_vs_state(sctx);
3879 bool old_clip_disable = old_vs ? old_vs->key.opt.clip_disable : false;
3880 struct si_shader *old_ps = sctx->ps_shader.current;
3881 union si_vgt_stages_key key;
3882 unsigned old_spi_shader_col_format =
3883 old_ps ? old_ps->key.part.ps.epilog.spi_shader_col_format : 0;
3884 int r;
3885
3886 compiler_state.compiler = &sctx->compiler;
3887 compiler_state.debug = sctx->debug;
3888 compiler_state.is_debug_context = sctx->is_debug;
3889
3890 key.index = 0;
3891
3892 if (sctx->tes_shader.cso)
3893 key.u.tess = 1;
3894 if (sctx->gs_shader.cso)
3895 key.u.gs = 1;
3896
3897 if (sctx->ngg) {
3898 key.u.ngg = 1;
3899 key.u.streamout = !!si_get_vs(sctx)->cso->so.num_outputs;
3900 }
3901
3902 /* Update TCS and TES. */
3903 if (sctx->tes_shader.cso) {
3904 if (!sctx->tess_rings) {
3905 si_init_tess_factor_ring(sctx);
3906 if (!sctx->tess_rings)
3907 return false;
3908 }
3909
3910 if (sctx->tcs_shader.cso) {
3911 r = si_shader_select(ctx, &sctx->tcs_shader, key,
3912 &compiler_state);
3913 if (r)
3914 return false;
3915 si_pm4_bind_state(sctx, hs, sctx->tcs_shader.current->pm4);
3916 } else {
3917 if (!sctx->fixed_func_tcs_shader.cso) {
3918 sctx->fixed_func_tcs_shader.cso =
3919 si_create_fixed_func_tcs(sctx);
3920 if (!sctx->fixed_func_tcs_shader.cso)
3921 return false;
3922 }
3923
3924 r = si_shader_select(ctx, &sctx->fixed_func_tcs_shader,
3925 key, &compiler_state);
3926 if (r)
3927 return false;
3928 si_pm4_bind_state(sctx, hs,
3929 sctx->fixed_func_tcs_shader.current->pm4);
3930 }
3931
3932 if (!sctx->gs_shader.cso || sctx->chip_class <= GFX8) {
3933 r = si_shader_select(ctx, &sctx->tes_shader, key, &compiler_state);
3934 if (r)
3935 return false;
3936
3937 if (sctx->gs_shader.cso) {
3938 /* TES as ES */
3939 assert(sctx->chip_class <= GFX8);
3940 si_pm4_bind_state(sctx, es, sctx->tes_shader.current->pm4);
3941 } else if (key.u.ngg) {
3942 si_pm4_bind_state(sctx, gs, sctx->tes_shader.current->pm4);
3943 } else {
3944 si_pm4_bind_state(sctx, vs, sctx->tes_shader.current->pm4);
3945 }
3946 }
3947 } else {
3948 if (sctx->chip_class <= GFX8)
3949 si_pm4_bind_state(sctx, ls, NULL);
3950 si_pm4_bind_state(sctx, hs, NULL);
3951 }
3952
3953 /* Update GS. */
3954 if (sctx->gs_shader.cso) {
3955 r = si_shader_select(ctx, &sctx->gs_shader, key, &compiler_state);
3956 if (r)
3957 return false;
3958 si_pm4_bind_state(sctx, gs, sctx->gs_shader.current->pm4);
3959 if (!key.u.ngg) {
3960 si_pm4_bind_state(sctx, vs, sctx->gs_shader.cso->gs_copy_shader->pm4);
3961
3962 if (!si_update_gs_ring_buffers(sctx))
3963 return false;
3964 } else {
3965 si_pm4_bind_state(sctx, vs, NULL);
3966 }
3967 } else {
3968 if (!key.u.ngg) {
3969 si_pm4_bind_state(sctx, gs, NULL);
3970 if (sctx->chip_class <= GFX8)
3971 si_pm4_bind_state(sctx, es, NULL);
3972 }
3973 }
3974
3975 /* Update VS. */
3976 if ((!key.u.tess && !key.u.gs) || sctx->chip_class <= GFX8) {
3977 r = si_shader_select(ctx, &sctx->vs_shader, key, &compiler_state);
3978 if (r)
3979 return false;
3980
3981 if (!key.u.tess && !key.u.gs) {
3982 if (key.u.ngg) {
3983 si_pm4_bind_state(sctx, gs, sctx->vs_shader.current->pm4);
3984 si_pm4_bind_state(sctx, vs, NULL);
3985 } else {
3986 si_pm4_bind_state(sctx, vs, sctx->vs_shader.current->pm4);
3987 }
3988 } else if (sctx->tes_shader.cso) {
3989 si_pm4_bind_state(sctx, ls, sctx->vs_shader.current->pm4);
3990 } else {
3991 assert(sctx->gs_shader.cso);
3992 si_pm4_bind_state(sctx, es, sctx->vs_shader.current->pm4);
3993 }
3994 }
3995
3996 si_update_vgt_shader_config(sctx, key);
3997
3998 if (old_clip_disable != si_get_vs_state(sctx)->key.opt.clip_disable)
3999 si_mark_atom_dirty(sctx, &sctx->atoms.s.clip_regs);
4000
4001 if (sctx->ps_shader.cso) {
4002 unsigned db_shader_control;
4003
4004 r = si_shader_select(ctx, &sctx->ps_shader, key, &compiler_state);
4005 if (r)
4006 return false;
4007 si_pm4_bind_state(sctx, ps, sctx->ps_shader.current->pm4);
4008
4009 db_shader_control =
4010 sctx->ps_shader.cso->db_shader_control |
4011 S_02880C_KILL_ENABLE(si_get_alpha_test_func(sctx) != PIPE_FUNC_ALWAYS);
4012
4013 if (si_pm4_state_changed(sctx, ps) ||
4014 si_pm4_state_changed(sctx, vs) ||
4015 (key.u.ngg && si_pm4_state_changed(sctx, gs)) ||
4016 sctx->sprite_coord_enable != rs->sprite_coord_enable ||
4017 sctx->flatshade != rs->flatshade) {
4018 sctx->sprite_coord_enable = rs->sprite_coord_enable;
4019 sctx->flatshade = rs->flatshade;
4020 si_mark_atom_dirty(sctx, &sctx->atoms.s.spi_map);
4021 }
4022
4023 if (sctx->screen->info.rbplus_allowed &&
4024 si_pm4_state_changed(sctx, ps) &&
4025 (!old_ps ||
4026 old_spi_shader_col_format !=
4027 sctx->ps_shader.current->key.part.ps.epilog.spi_shader_col_format))
4028 si_mark_atom_dirty(sctx, &sctx->atoms.s.cb_render_state);
4029
4030 if (sctx->ps_db_shader_control != db_shader_control) {
4031 sctx->ps_db_shader_control = db_shader_control;
4032 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4033 if (sctx->screen->dpbb_allowed)
4034 si_mark_atom_dirty(sctx, &sctx->atoms.s.dpbb_state);
4035 }
4036
4037 if (sctx->smoothing_enabled != sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing) {
4038 sctx->smoothing_enabled = sctx->ps_shader.current->key.part.ps.epilog.poly_line_smoothing;
4039 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_config);
4040
4041 if (sctx->chip_class == GFX6)
4042 si_mark_atom_dirty(sctx, &sctx->atoms.s.db_render_state);
4043
4044 if (sctx->framebuffer.nr_samples <= 1)
4045 si_mark_atom_dirty(sctx, &sctx->atoms.s.msaa_sample_locs);
4046 }
4047 }
4048
4049 if (si_pm4_state_enabled_and_changed(sctx, ls) ||
4050 si_pm4_state_enabled_and_changed(sctx, hs) ||
4051 si_pm4_state_enabled_and_changed(sctx, es) ||
4052 si_pm4_state_enabled_and_changed(sctx, gs) ||
4053 si_pm4_state_enabled_and_changed(sctx, vs) ||
4054 si_pm4_state_enabled_and_changed(sctx, ps)) {
4055 if (!si_update_spi_tmpring_size(sctx))
4056 return false;
4057 }
4058
4059 if (sctx->chip_class >= GFX7) {
4060 if (si_pm4_state_enabled_and_changed(sctx, ls))
4061 sctx->prefetch_L2_mask |= SI_PREFETCH_LS;
4062 else if (!sctx->queued.named.ls)
4063 sctx->prefetch_L2_mask &= ~SI_PREFETCH_LS;
4064
4065 if (si_pm4_state_enabled_and_changed(sctx, hs))
4066 sctx->prefetch_L2_mask |= SI_PREFETCH_HS;
4067 else if (!sctx->queued.named.hs)
4068 sctx->prefetch_L2_mask &= ~SI_PREFETCH_HS;
4069
4070 if (si_pm4_state_enabled_and_changed(sctx, es))
4071 sctx->prefetch_L2_mask |= SI_PREFETCH_ES;
4072 else if (!sctx->queued.named.es)
4073 sctx->prefetch_L2_mask &= ~SI_PREFETCH_ES;
4074
4075 if (si_pm4_state_enabled_and_changed(sctx, gs))
4076 sctx->prefetch_L2_mask |= SI_PREFETCH_GS;
4077 else if (!sctx->queued.named.gs)
4078 sctx->prefetch_L2_mask &= ~SI_PREFETCH_GS;
4079
4080 if (si_pm4_state_enabled_and_changed(sctx, vs))
4081 sctx->prefetch_L2_mask |= SI_PREFETCH_VS;
4082 else if (!sctx->queued.named.vs)
4083 sctx->prefetch_L2_mask &= ~SI_PREFETCH_VS;
4084
4085 if (si_pm4_state_enabled_and_changed(sctx, ps))
4086 sctx->prefetch_L2_mask |= SI_PREFETCH_PS;
4087 else if (!sctx->queued.named.ps)
4088 sctx->prefetch_L2_mask &= ~SI_PREFETCH_PS;
4089 }
4090
4091 sctx->do_update_shaders = false;
4092 return true;
4093 }
4094
4095 static void si_emit_scratch_state(struct si_context *sctx)
4096 {
4097 struct radeon_cmdbuf *cs = sctx->gfx_cs;
4098
4099 radeon_set_context_reg(cs, R_0286E8_SPI_TMPRING_SIZE,
4100 sctx->spi_tmpring_size);
4101
4102 if (sctx->scratch_buffer) {
4103 radeon_add_to_buffer_list(sctx, sctx->gfx_cs,
4104 sctx->scratch_buffer, RADEON_USAGE_READWRITE,
4105 RADEON_PRIO_SCRATCH_BUFFER);
4106 }
4107 }
4108
4109 void si_init_shader_functions(struct si_context *sctx)
4110 {
4111 sctx->atoms.s.spi_map.emit = si_emit_spi_map;
4112 sctx->atoms.s.scratch_state.emit = si_emit_scratch_state;
4113
4114 sctx->b.create_vs_state = si_create_shader_selector;
4115 sctx->b.create_tcs_state = si_create_shader_selector;
4116 sctx->b.create_tes_state = si_create_shader_selector;
4117 sctx->b.create_gs_state = si_create_shader_selector;
4118 sctx->b.create_fs_state = si_create_shader_selector;
4119
4120 sctx->b.bind_vs_state = si_bind_vs_shader;
4121 sctx->b.bind_tcs_state = si_bind_tcs_shader;
4122 sctx->b.bind_tes_state = si_bind_tes_shader;
4123 sctx->b.bind_gs_state = si_bind_gs_shader;
4124 sctx->b.bind_fs_state = si_bind_ps_shader;
4125
4126 sctx->b.delete_vs_state = si_delete_shader_selector;
4127 sctx->b.delete_tcs_state = si_delete_shader_selector;
4128 sctx->b.delete_tes_state = si_delete_shader_selector;
4129 sctx->b.delete_gs_state = si_delete_shader_selector;
4130 sctx->b.delete_fs_state = si_delete_shader_selector;
4131 }