2 * Copyright 2012 Advanced Micro Devices, Inc.
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * on the rights to use, copy, modify, merge, publish, distribute, sub
9 * license, and/or sell copies of the Software, and to permit persons to whom
10 * the Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
20 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
21 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
22 * USE OR OTHER DEALINGS IN THE SOFTWARE.
25 #include "si_build_pm4.h"
26 #include "util/u_viewport.h"
28 #define SI_MAX_SCISSOR 16384
30 static void si_set_scissor_states(struct pipe_context
*pctx
,
32 unsigned num_scissors
,
33 const struct pipe_scissor_state
*state
)
35 struct si_context
*ctx
= (struct si_context
*)pctx
;
38 for (i
= 0; i
< num_scissors
; i
++)
39 ctx
->scissors
[start_slot
+ i
] = state
[i
];
41 if (!ctx
->queued
.named
.rasterizer
->scissor_enable
)
44 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
47 /* Since the guard band disables clipping, we have to clip per-pixel
50 static void si_get_scissor_from_viewport(struct si_context
*ctx
,
51 const struct pipe_viewport_state
*vp
,
52 struct si_signed_scissor
*scissor
)
54 float tmp
, minx
, miny
, maxx
, maxy
;
56 /* Convert (-1, -1) and (1, 1) from clip space into window space. */
57 minx
= -vp
->scale
[0] + vp
->translate
[0];
58 miny
= -vp
->scale
[1] + vp
->translate
[1];
59 maxx
= vp
->scale
[0] + vp
->translate
[0];
60 maxy
= vp
->scale
[1] + vp
->translate
[1];
62 /* Handle inverted viewports. */
74 /* Convert to integer and round up the max bounds. */
77 scissor
->maxx
= ceilf(maxx
);
78 scissor
->maxy
= ceilf(maxy
);
81 static void si_clamp_scissor(struct si_context
*ctx
,
82 struct pipe_scissor_state
*out
,
83 struct si_signed_scissor
*scissor
)
85 out
->minx
= CLAMP(scissor
->minx
, 0, SI_MAX_SCISSOR
);
86 out
->miny
= CLAMP(scissor
->miny
, 0, SI_MAX_SCISSOR
);
87 out
->maxx
= CLAMP(scissor
->maxx
, 0, SI_MAX_SCISSOR
);
88 out
->maxy
= CLAMP(scissor
->maxy
, 0, SI_MAX_SCISSOR
);
91 static void si_clip_scissor(struct pipe_scissor_state
*out
,
92 struct pipe_scissor_state
*clip
)
94 out
->minx
= MAX2(out
->minx
, clip
->minx
);
95 out
->miny
= MAX2(out
->miny
, clip
->miny
);
96 out
->maxx
= MIN2(out
->maxx
, clip
->maxx
);
97 out
->maxy
= MIN2(out
->maxy
, clip
->maxy
);
100 static void si_scissor_make_union(struct si_signed_scissor
*out
,
101 struct si_signed_scissor
*in
)
103 out
->minx
= MIN2(out
->minx
, in
->minx
);
104 out
->miny
= MIN2(out
->miny
, in
->miny
);
105 out
->maxx
= MAX2(out
->maxx
, in
->maxx
);
106 out
->maxy
= MAX2(out
->maxy
, in
->maxy
);
107 out
->quant_mode
= MIN2(out
->quant_mode
, in
->quant_mode
);
110 static void si_emit_one_scissor(struct si_context
*ctx
,
111 struct radeon_cmdbuf
*cs
,
112 struct si_signed_scissor
*vp_scissor
,
113 struct pipe_scissor_state
*scissor
)
115 struct pipe_scissor_state final
;
117 if (ctx
->vs_disables_clipping_viewport
) {
118 final
.minx
= final
.miny
= 0;
119 final
.maxx
= final
.maxy
= SI_MAX_SCISSOR
;
121 si_clamp_scissor(ctx
, &final
, vp_scissor
);
125 si_clip_scissor(&final
, scissor
);
127 /* Workaround for a hw bug on GFX6 that occurs when PA_SU_HARDWARE_-
128 * SCREEN_OFFSET != 0 and any_scissor.BR_X/Y <= 0.
130 if (ctx
->chip_class
== GFX6
&& (final
.maxx
== 0 || final
.maxy
== 0)) {
131 radeon_emit(cs
, S_028250_TL_X(1) |
133 S_028250_WINDOW_OFFSET_DISABLE(1));
134 radeon_emit(cs
, S_028254_BR_X(1) |
139 radeon_emit(cs
, S_028250_TL_X(final
.minx
) |
140 S_028250_TL_Y(final
.miny
) |
141 S_028250_WINDOW_OFFSET_DISABLE(1));
142 radeon_emit(cs
, S_028254_BR_X(final
.maxx
) |
143 S_028254_BR_Y(final
.maxy
));
146 #define MAX_PA_SU_HARDWARE_SCREEN_OFFSET 8176
148 static void si_emit_guardband(struct si_context
*ctx
)
150 const struct si_state_rasterizer
*rs
= ctx
->queued
.named
.rasterizer
;
151 struct si_signed_scissor vp_as_scissor
;
152 struct pipe_viewport_state vp
;
153 float left
, top
, right
, bottom
, max_range
, guardband_x
, guardband_y
;
154 float discard_x
, discard_y
;
156 if (ctx
->vs_writes_viewport_index
) {
157 /* Shaders can draw to any viewport. Make a union of all
159 vp_as_scissor
= ctx
->viewports
.as_scissor
[0];
160 for (unsigned i
= 1; i
< SI_MAX_VIEWPORTS
; i
++) {
161 si_scissor_make_union(&vp_as_scissor
,
162 &ctx
->viewports
.as_scissor
[i
]);
165 vp_as_scissor
= ctx
->viewports
.as_scissor
[0];
168 /* Blits don't set the viewport state. The vertex shader determines
169 * the viewport size by scaling the coordinates, so we don't know
170 * how large the viewport is. Assume the worst case.
172 if (ctx
->vs_disables_clipping_viewport
)
173 vp_as_scissor
.quant_mode
= SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
;
175 /* Determine the optimal hardware screen offset to center the viewport
176 * within the viewport range in order to maximize the guardband size.
178 int hw_screen_offset_x
= (vp_as_scissor
.maxx
+ vp_as_scissor
.minx
) / 2;
179 int hw_screen_offset_y
= (vp_as_scissor
.maxy
+ vp_as_scissor
.miny
) / 2;
181 /* GFX6-GFX7 need to align the offset to an ubertile consisting of all SEs. */
182 const unsigned hw_screen_offset_alignment
=
183 ctx
->chip_class
>= GFX8
? 16 : MAX2(ctx
->screen
->se_tile_repeat
, 16);
185 /* Indexed by quantization modes */
186 static int max_viewport_size
[] = {65535, 16383, 4095};
188 /* Ensure that the whole viewport stays representable in
189 * absolute coordinates.
190 * See comment in si_set_viewport_states.
192 assert(vp_as_scissor
.maxx
<= max_viewport_size
[vp_as_scissor
.quant_mode
] &&
193 vp_as_scissor
.maxy
<= max_viewport_size
[vp_as_scissor
.quant_mode
]);
195 hw_screen_offset_x
= CLAMP(hw_screen_offset_x
, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET
);
196 hw_screen_offset_y
= CLAMP(hw_screen_offset_y
, 0, MAX_PA_SU_HARDWARE_SCREEN_OFFSET
);
198 /* Align the screen offset by dropping the low bits. */
199 hw_screen_offset_x
&= ~(hw_screen_offset_alignment
- 1);
200 hw_screen_offset_y
&= ~(hw_screen_offset_alignment
- 1);
202 /* Apply the offset to center the viewport and maximize the guardband. */
203 vp_as_scissor
.minx
-= hw_screen_offset_x
;
204 vp_as_scissor
.maxx
-= hw_screen_offset_x
;
205 vp_as_scissor
.miny
-= hw_screen_offset_y
;
206 vp_as_scissor
.maxy
-= hw_screen_offset_y
;
208 /* Reconstruct the viewport transformation from the scissor. */
209 vp
.translate
[0] = (vp_as_scissor
.minx
+ vp_as_scissor
.maxx
) / 2.0;
210 vp
.translate
[1] = (vp_as_scissor
.miny
+ vp_as_scissor
.maxy
) / 2.0;
211 vp
.scale
[0] = vp_as_scissor
.maxx
- vp
.translate
[0];
212 vp
.scale
[1] = vp_as_scissor
.maxy
- vp
.translate
[1];
214 /* Treat a 0x0 viewport as 1x1 to prevent division by zero. */
215 if (vp_as_scissor
.minx
== vp_as_scissor
.maxx
)
217 if (vp_as_scissor
.miny
== vp_as_scissor
.maxy
)
220 /* Find the biggest guard band that is inside the supported viewport
221 * range. The guard band is specified as a horizontal and vertical
222 * distance from (0,0) in clip space.
224 * This is done by applying the inverse viewport transformation
225 * on the viewport limits to get those limits in clip space.
227 * The viewport range is [-max_viewport_size/2, max_viewport_size/2].
229 assert(vp_as_scissor
.quant_mode
< ARRAY_SIZE(max_viewport_size
));
230 max_range
= max_viewport_size
[vp_as_scissor
.quant_mode
] / 2;
231 left
= (-max_range
- vp
.translate
[0]) / vp
.scale
[0];
232 right
= ( max_range
- vp
.translate
[0]) / vp
.scale
[0];
233 top
= (-max_range
- vp
.translate
[1]) / vp
.scale
[1];
234 bottom
= ( max_range
- vp
.translate
[1]) / vp
.scale
[1];
236 assert(left
<= -1 && top
<= -1 && right
>= 1 && bottom
>= 1);
238 guardband_x
= MIN2(-left
, right
);
239 guardband_y
= MIN2(-top
, bottom
);
244 if (unlikely(util_prim_is_points_or_lines(ctx
->current_rast_prim
))) {
245 /* When rendering wide points or lines, we need to be more
246 * conservative about when to discard them entirely. */
249 if (ctx
->current_rast_prim
== PIPE_PRIM_POINTS
)
250 pixels
= rs
->max_point_size
;
252 pixels
= rs
->line_width
;
254 /* Add half the point size / line width */
255 discard_x
+= pixels
/ (2.0 * vp
.scale
[0]);
256 discard_y
+= pixels
/ (2.0 * vp
.scale
[1]);
258 /* Discard primitives that would lie entirely outside the clip
260 discard_x
= MIN2(discard_x
, guardband_x
);
261 discard_y
= MIN2(discard_y
, guardband_y
);
264 /* If any of the GB registers is updated, all of them must be updated.
265 * R_028BE8_PA_CL_GB_VERT_CLIP_ADJ, R_028BEC_PA_CL_GB_VERT_DISC_ADJ
266 * R_028BF0_PA_CL_GB_HORZ_CLIP_ADJ, R_028BF4_PA_CL_GB_HORZ_DISC_ADJ
268 unsigned initial_cdw
= ctx
->gfx_cs
->current
.cdw
;
269 radeon_opt_set_context_reg4(ctx
, R_028BE8_PA_CL_GB_VERT_CLIP_ADJ
,
270 SI_TRACKED_PA_CL_GB_VERT_CLIP_ADJ
,
271 fui(guardband_y
), fui(discard_y
),
272 fui(guardband_x
), fui(discard_x
));
273 radeon_opt_set_context_reg(ctx
, R_028234_PA_SU_HARDWARE_SCREEN_OFFSET
,
274 SI_TRACKED_PA_SU_HARDWARE_SCREEN_OFFSET
,
275 S_028234_HW_SCREEN_OFFSET_X(hw_screen_offset_x
>> 4) |
276 S_028234_HW_SCREEN_OFFSET_Y(hw_screen_offset_y
>> 4));
277 radeon_opt_set_context_reg(ctx
, R_028BE4_PA_SU_VTX_CNTL
,
278 SI_TRACKED_PA_SU_VTX_CNTL
,
279 S_028BE4_PIX_CENTER(rs
->half_pixel_center
) |
280 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
+
281 vp_as_scissor
.quant_mode
));
282 if (initial_cdw
!= ctx
->gfx_cs
->current
.cdw
)
283 ctx
->context_roll
= true;
286 static void si_emit_scissors(struct si_context
*ctx
)
288 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
289 struct pipe_scissor_state
*states
= ctx
->scissors
;
290 bool scissor_enabled
= ctx
->queued
.named
.rasterizer
->scissor_enable
;
292 /* The simple case: Only 1 viewport is active. */
293 if (!ctx
->vs_writes_viewport_index
) {
294 struct si_signed_scissor
*vp
= &ctx
->viewports
.as_scissor
[0];
296 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
, 2);
297 si_emit_one_scissor(ctx
, cs
, vp
, scissor_enabled
? &states
[0] : NULL
);
301 /* All registers in the array need to be updated if any of them is changed.
302 * This is a hardware requirement.
304 radeon_set_context_reg_seq(cs
, R_028250_PA_SC_VPORT_SCISSOR_0_TL
,
305 SI_MAX_VIEWPORTS
* 2);
306 for (unsigned i
= 0; i
< SI_MAX_VIEWPORTS
; i
++) {
307 si_emit_one_scissor(ctx
, cs
, &ctx
->viewports
.as_scissor
[i
],
308 scissor_enabled
? &states
[i
] : NULL
);
312 static void si_set_viewport_states(struct pipe_context
*pctx
,
314 unsigned num_viewports
,
315 const struct pipe_viewport_state
*state
)
317 struct si_context
*ctx
= (struct si_context
*)pctx
;
320 for (i
= 0; i
< num_viewports
; i
++) {
321 unsigned index
= start_slot
+ i
;
322 struct si_signed_scissor
*scissor
= &ctx
->viewports
.as_scissor
[index
];
324 ctx
->viewports
.states
[index
] = state
[i
];
326 si_get_scissor_from_viewport(ctx
, &state
[i
], scissor
);
328 unsigned w
= scissor
->maxx
- scissor
->minx
;
329 unsigned h
= scissor
->maxy
- scissor
->miny
;
330 unsigned max_extent
= MAX2(w
, h
);
332 int max_corner
= MAX2(scissor
->maxx
, scissor
->maxy
);
334 unsigned center_x
= (scissor
->maxx
+ scissor
->minx
) / 2;
335 unsigned center_y
= (scissor
->maxy
+ scissor
->miny
) / 2;
336 unsigned max_center
= MAX2(center_x
, center_y
);
338 /* PA_SU_HARDWARE_SCREEN_OFFSET can't center viewports whose
339 * center start farther than MAX_PA_SU_HARDWARE_SCREEN_OFFSET.
340 * (for example, a 1x1 viewport in the lower right corner of
341 * 16Kx16K) Such viewports need a greater guardband, so they
342 * have to use a worse quantization mode.
344 unsigned distance_off_center
=
345 MAX2(0, (int)max_center
- MAX_PA_SU_HARDWARE_SCREEN_OFFSET
);
346 max_extent
+= distance_off_center
;
348 /* Determine the best quantization mode (subpixel precision),
349 * but also leave enough space for the guardband.
351 * Note that primitive binning requires QUANT_MODE == 16_8 on Vega10
352 * and Raven1 for line and rectangle primitive types to work correctly.
353 * Always use 16_8 if primitive binning is possible to occur.
355 if ((ctx
->family
== CHIP_VEGA10
|| ctx
->family
== CHIP_RAVEN
) &&
356 ctx
->screen
->dpbb_allowed
)
357 max_extent
= 16384; /* Use QUANT_MODE == 16_8. */
359 /* Another constraint is that all coordinates in the viewport
360 * are representable in fixed point with respect to the
363 * It means that PA_SU_HARDWARE_SCREEN_OFFSET can't be given
364 * an offset that would make the upper corner of the viewport
365 * greater than the maximum representable number post
366 * quantization, ie 2^quant_bits.
368 * This does not matter for 14.10 and 16.8 formats since the
369 * offset is already limited at 8k, but it means we can't use
370 * 12.12 if we are drawing to some pixels outside the lower
371 * 4k x 4k of the render target.
374 if (max_extent
<= 1024 && max_corner
< 4096) /* 4K scanline area for guardband */
375 scissor
->quant_mode
= SI_QUANT_MODE_12_12_FIXED_POINT_1_4096TH
;
376 else if (max_extent
<= 4096) /* 16K scanline area for guardband */
377 scissor
->quant_mode
= SI_QUANT_MODE_14_10_FIXED_POINT_1_1024TH
;
378 else /* 64K scanline area for guardband */
379 scissor
->quant_mode
= SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
;
382 if (start_slot
== 0) {
383 ctx
->viewports
.y_inverted
=
384 -state
->scale
[1] + state
->translate
[1] >
385 state
->scale
[1] + state
->translate
[1];
388 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.viewports
);
389 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.guardband
);
390 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
393 static void si_emit_one_viewport(struct si_context
*ctx
,
394 struct pipe_viewport_state
*state
)
396 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
398 radeon_emit(cs
, fui(state
->scale
[0]));
399 radeon_emit(cs
, fui(state
->translate
[0]));
400 radeon_emit(cs
, fui(state
->scale
[1]));
401 radeon_emit(cs
, fui(state
->translate
[1]));
402 radeon_emit(cs
, fui(state
->scale
[2]));
403 radeon_emit(cs
, fui(state
->translate
[2]));
406 static void si_emit_viewports(struct si_context
*ctx
)
408 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
409 struct pipe_viewport_state
*states
= ctx
->viewports
.states
;
411 /* The simple case: Only 1 viewport is active. */
412 if (!ctx
->vs_writes_viewport_index
) {
413 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
, 6);
414 si_emit_one_viewport(ctx
, &states
[0]);
418 /* All registers in the array need to be updated if any of them is changed.
419 * This is a hardware requirement.
421 radeon_set_context_reg_seq(cs
, R_02843C_PA_CL_VPORT_XSCALE
+
422 0, SI_MAX_VIEWPORTS
* 6);
423 for (unsigned i
= 0; i
< SI_MAX_VIEWPORTS
; i
++)
424 si_emit_one_viewport(ctx
, &states
[i
]);
428 si_viewport_zmin_zmax(const struct pipe_viewport_state
*vp
, bool halfz
,
429 bool window_space_position
, float *zmin
, float *zmax
)
431 if (window_space_position
) {
436 util_viewport_zmin_zmax(vp
, halfz
, zmin
, zmax
);
439 static void si_emit_depth_ranges(struct si_context
*ctx
)
441 struct radeon_cmdbuf
*cs
= ctx
->gfx_cs
;
442 struct pipe_viewport_state
*states
= ctx
->viewports
.states
;
443 bool clip_halfz
= ctx
->queued
.named
.rasterizer
->clip_halfz
;
444 bool window_space
= ctx
->vs_disables_clipping_viewport
;
447 /* The simple case: Only 1 viewport is active. */
448 if (!ctx
->vs_writes_viewport_index
) {
449 si_viewport_zmin_zmax(&states
[0], clip_halfz
, window_space
,
452 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
, 2);
453 radeon_emit(cs
, fui(zmin
));
454 radeon_emit(cs
, fui(zmax
));
458 /* All registers in the array need to be updated if any of them is changed.
459 * This is a hardware requirement.
461 radeon_set_context_reg_seq(cs
, R_0282D0_PA_SC_VPORT_ZMIN_0
,
462 SI_MAX_VIEWPORTS
* 2);
463 for (unsigned i
= 0; i
< SI_MAX_VIEWPORTS
; i
++) {
464 si_viewport_zmin_zmax(&states
[i
], clip_halfz
, window_space
,
466 radeon_emit(cs
, fui(zmin
));
467 radeon_emit(cs
, fui(zmax
));
471 static void si_emit_viewport_states(struct si_context
*ctx
)
473 si_emit_viewports(ctx
);
474 si_emit_depth_ranges(ctx
);
478 * This reacts to 2 state changes:
479 * - VS.writes_viewport_index
480 * - VS output position in window space (enable/disable)
482 * Normally, we only emit 1 viewport and 1 scissor if no shader is using
483 * the VIEWPORT_INDEX output, and emitting the other viewports and scissors
484 * is delayed. When a shader with VIEWPORT_INDEX appears, this should be
485 * called to emit the rest.
487 void si_update_vs_viewport_state(struct si_context
*ctx
)
489 struct si_shader_info
*info
= si_get_vs_info(ctx
);
490 bool vs_window_space
;
495 /* When the VS disables clipping and viewport transformation. */
497 info
->properties
[TGSI_PROPERTY_VS_WINDOW_SPACE_POSITION
];
499 if (ctx
->vs_disables_clipping_viewport
!= vs_window_space
) {
500 ctx
->vs_disables_clipping_viewport
= vs_window_space
;
501 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
502 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.viewports
);
505 /* Viewport index handling. */
506 if (ctx
->vs_writes_viewport_index
== info
->writes_viewport_index
)
509 /* This changes how the guardband is computed. */
510 ctx
->vs_writes_viewport_index
= info
->writes_viewport_index
;
511 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.guardband
);
513 /* Emit scissors and viewports that were enabled by having
514 * the ViewportIndex output.
516 if (info
->writes_viewport_index
) {
517 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.scissors
);
518 si_mark_atom_dirty(ctx
, &ctx
->atoms
.s
.viewports
);
522 static void si_emit_window_rectangles(struct si_context
*sctx
)
524 /* There are four clipping rectangles. Their corner coordinates are inclusive.
525 * Every pixel is assigned a number from 0 and 15 by setting bits 0-3 depending
526 * on whether the pixel is inside cliprects 0-3, respectively. For example,
527 * if a pixel is inside cliprects 0 and 1, but outside 2 and 3, it is assigned
528 * the number 3 (binary 0011).
530 * If CLIPRECT_RULE & (1 << number), the pixel is rasterized.
532 struct radeon_cmdbuf
*cs
= sctx
->gfx_cs
;
533 static const unsigned outside
[4] = {
534 /* outside rectangle 0 */
543 /* outside rectangles 0, 1 */
548 /* outside rectangles 0, 1, 2 */
551 /* outside rectangles 0, 1, 2, 3 */
554 const unsigned disabled
= 0xffff; /* all inside and outside cases */
555 unsigned num_rectangles
= sctx
->num_window_rectangles
;
556 struct pipe_scissor_state
*rects
= sctx
->window_rectangles
;
559 assert(num_rectangles
<= 4);
561 if (num_rectangles
== 0)
563 else if (sctx
->window_rectangles_include
)
564 rule
= ~outside
[num_rectangles
- 1];
566 rule
= outside
[num_rectangles
- 1];
568 radeon_opt_set_context_reg(sctx
, R_02820C_PA_SC_CLIPRECT_RULE
,
569 SI_TRACKED_PA_SC_CLIPRECT_RULE
, rule
);
570 if (num_rectangles
== 0)
573 radeon_set_context_reg_seq(cs
, R_028210_PA_SC_CLIPRECT_0_TL
,
575 for (unsigned i
= 0; i
< num_rectangles
; i
++) {
576 radeon_emit(cs
, S_028210_TL_X(rects
[i
].minx
) |
577 S_028210_TL_Y(rects
[i
].miny
));
578 radeon_emit(cs
, S_028214_BR_X(rects
[i
].maxx
) |
579 S_028214_BR_Y(rects
[i
].maxy
));
583 static void si_set_window_rectangles(struct pipe_context
*ctx
,
585 unsigned num_rectangles
,
586 const struct pipe_scissor_state
*rects
)
588 struct si_context
*sctx
= (struct si_context
*)ctx
;
590 sctx
->num_window_rectangles
= num_rectangles
;
591 sctx
->window_rectangles_include
= include
;
592 if (num_rectangles
) {
593 memcpy(sctx
->window_rectangles
, rects
,
594 sizeof(*rects
) * num_rectangles
);
597 si_mark_atom_dirty(sctx
, &sctx
->atoms
.s
.window_rectangles
);
600 void si_init_viewport_functions(struct si_context
*ctx
)
602 ctx
->atoms
.s
.guardband
.emit
= si_emit_guardband
;
603 ctx
->atoms
.s
.scissors
.emit
= si_emit_scissors
;
604 ctx
->atoms
.s
.viewports
.emit
= si_emit_viewport_states
;
605 ctx
->atoms
.s
.window_rectangles
.emit
= si_emit_window_rectangles
;
607 ctx
->b
.set_scissor_states
= si_set_scissor_states
;
608 ctx
->b
.set_viewport_states
= si_set_viewport_states
;
609 ctx
->b
.set_window_rectangles
= si_set_window_rectangles
;
611 for (unsigned i
= 0; i
< 16; i
++)
612 ctx
->viewports
.as_scissor
[i
].quant_mode
= SI_QUANT_MODE_16_8_FIXED_POINT_1_256TH
;