2 * Copyright 2010 Jerome Glisse <glisse@freedesktop.org>
3 * Copyright 2018 Advanced Micro Devices, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * on the rights to use, copy, modify, merge, publish, distribute, sub
10 * license, and/or sell copies of the Software, and to permit persons to whom
11 * the Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHOR(S) AND/OR THEIR SUPPLIERS BE LIABLE FOR ANY CLAIM,
21 * DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR
22 * OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE
23 * USE OR OTHER DEALINGS IN THE SOFTWARE.
26 #include "drm-uapi/drm_fourcc.h"
30 #include "frontend/drm_driver.h"
31 #include "util/format/u_format.h"
32 #include "util/os_time.h"
33 #include "util/u_log.h"
34 #include "util/u_memory.h"
35 #include "util/u_pack_color.h"
36 #include "util/u_resource.h"
37 #include "util/u_surface.h"
38 #include "util/u_transfer.h"
43 #include "amd/addrlib/inc/addrinterface.h"
45 static enum radeon_surf_mode
si_choose_tiling(struct si_screen
*sscreen
,
46 const struct pipe_resource
*templ
,
47 bool tc_compatible_htile
);
49 bool si_prepare_for_dma_blit(struct si_context
*sctx
, struct si_texture
*dst
, unsigned dst_level
,
50 unsigned dstx
, unsigned dsty
, unsigned dstz
, struct si_texture
*src
,
51 unsigned src_level
, const struct pipe_box
*src_box
)
56 if (dst
->surface
.bpe
!= src
->surface
.bpe
)
59 /* MSAA: Blits don't exist in the real world. */
60 if (src
->buffer
.b
.b
.nr_samples
> 1 || dst
->buffer
.b
.b
.nr_samples
> 1)
63 /* Depth-stencil surfaces:
64 * When dst is linear, the DB->CB copy preserves HTILE.
65 * When dst is tiled, the 3D path must be used to update HTILE.
67 if (src
->is_depth
|| dst
->is_depth
)
71 * src: Use the 3D path. DCC decompression is expensive.
72 * dst: Use the 3D path to compress the pixels with DCC.
74 if (vi_dcc_enabled(src
, src_level
) || vi_dcc_enabled(dst
, dst_level
))
77 /* TMZ: mixing encrypted and non-encrypted buffer in a single command
78 * doesn't seem supported.
80 if ((src
->buffer
.flags
& RADEON_FLAG_ENCRYPTED
) !=
81 (dst
->buffer
.flags
& RADEON_FLAG_ENCRYPTED
))
85 * src: Both texture and SDMA paths need decompression. Use SDMA.
86 * dst: If overwriting the whole texture, discard CMASK and use
87 * SDMA. Otherwise, use the 3D path.
89 if (dst
->cmask_buffer
&& dst
->dirty_level_mask
& (1 << dst_level
)) {
90 /* The CMASK clear is only enabled for the first level. */
91 assert(dst_level
== 0);
92 if (!util_texrange_covers_whole_level(&dst
->buffer
.b
.b
, dst_level
, dstx
, dsty
, dstz
,
93 src_box
->width
, src_box
->height
, src_box
->depth
))
96 si_texture_discard_cmask(sctx
->screen
, dst
);
99 /* All requirements are met. Prepare textures for SDMA. */
100 if (src
->cmask_buffer
&& src
->dirty_level_mask
& (1 << src_level
))
101 sctx
->b
.flush_resource(&sctx
->b
, &src
->buffer
.b
.b
);
103 assert(!(src
->dirty_level_mask
& (1 << src_level
)));
104 assert(!(dst
->dirty_level_mask
& (1 << dst_level
)));
109 /* Same as resource_copy_region, except that both upsampling and downsampling are allowed. */
110 static void si_copy_region_with_blit(struct pipe_context
*pipe
, struct pipe_resource
*dst
,
111 unsigned dst_level
, unsigned dstx
, unsigned dsty
,
112 unsigned dstz
, struct pipe_resource
*src
, unsigned src_level
,
113 const struct pipe_box
*src_box
)
115 struct pipe_blit_info blit
;
117 memset(&blit
, 0, sizeof(blit
));
118 blit
.src
.resource
= src
;
119 blit
.src
.format
= src
->format
;
120 blit
.src
.level
= src_level
;
121 blit
.src
.box
= *src_box
;
122 blit
.dst
.resource
= dst
;
123 blit
.dst
.format
= dst
->format
;
124 blit
.dst
.level
= dst_level
;
125 blit
.dst
.box
.x
= dstx
;
126 blit
.dst
.box
.y
= dsty
;
127 blit
.dst
.box
.z
= dstz
;
128 blit
.dst
.box
.width
= src_box
->width
;
129 blit
.dst
.box
.height
= src_box
->height
;
130 blit
.dst
.box
.depth
= src_box
->depth
;
131 blit
.mask
= util_format_get_mask(dst
->format
);
132 blit
.filter
= PIPE_TEX_FILTER_NEAREST
;
135 pipe
->blit(pipe
, &blit
);
139 /* Copy from a full GPU texture to a transfer's staging one. */
140 static void si_copy_to_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
142 struct si_context
*sctx
= (struct si_context
*)ctx
;
143 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
144 struct pipe_resource
*dst
= &stransfer
->staging
->b
.b
;
145 struct pipe_resource
*src
= transfer
->resource
;
147 if (src
->nr_samples
> 1 || ((struct si_texture
*)src
)->is_depth
) {
148 si_copy_region_with_blit(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
, &transfer
->box
);
152 sctx
->dma_copy(ctx
, dst
, 0, 0, 0, 0, src
, transfer
->level
, &transfer
->box
);
155 /* Copy from a transfer's staging texture to a full GPU one. */
156 static void si_copy_from_staging_texture(struct pipe_context
*ctx
, struct si_transfer
*stransfer
)
158 struct si_context
*sctx
= (struct si_context
*)ctx
;
159 struct pipe_transfer
*transfer
= (struct pipe_transfer
*)stransfer
;
160 struct pipe_resource
*dst
= transfer
->resource
;
161 struct pipe_resource
*src
= &stransfer
->staging
->b
.b
;
162 struct pipe_box sbox
;
164 u_box_3d(0, 0, 0, transfer
->box
.width
, transfer
->box
.height
, transfer
->box
.depth
, &sbox
);
166 if (dst
->nr_samples
> 1 || ((struct si_texture
*)dst
)->is_depth
) {
167 si_copy_region_with_blit(ctx
, dst
, transfer
->level
, transfer
->box
.x
, transfer
->box
.y
,
168 transfer
->box
.z
, src
, 0, &sbox
);
172 if (util_format_is_compressed(dst
->format
)) {
173 sbox
.width
= util_format_get_nblocksx(dst
->format
, sbox
.width
);
174 sbox
.height
= util_format_get_nblocksx(dst
->format
, sbox
.height
);
177 sctx
->dma_copy(ctx
, dst
, transfer
->level
, transfer
->box
.x
, transfer
->box
.y
, transfer
->box
.z
, src
,
181 static unsigned si_texture_get_offset(struct si_screen
*sscreen
, struct si_texture
*tex
,
182 unsigned level
, const struct pipe_box
*box
, unsigned *stride
,
183 unsigned *layer_stride
)
185 if (sscreen
->info
.chip_class
>= GFX9
) {
186 *stride
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
187 *layer_stride
= tex
->surface
.u
.gfx9
.surf_slice_size
;
192 /* Each texture is an array of slices. Each slice is an array
193 * of mipmap levels. */
194 return tex
->surface
.u
.gfx9
.surf_offset
+ box
->z
* tex
->surface
.u
.gfx9
.surf_slice_size
+
195 tex
->surface
.u
.gfx9
.offset
[level
] +
196 (box
->y
/ tex
->surface
.blk_h
* tex
->surface
.u
.gfx9
.surf_pitch
+
197 box
->x
/ tex
->surface
.blk_w
) *
200 *stride
= tex
->surface
.u
.legacy
.level
[level
].nblk_x
* tex
->surface
.bpe
;
201 assert((uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 <= UINT_MAX
);
202 *layer_stride
= (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4;
205 return tex
->surface
.u
.legacy
.level
[level
].offset
;
207 /* Each texture is an array of mipmap levels. Each level is
208 * an array of slices. */
209 return tex
->surface
.u
.legacy
.level
[level
].offset
+
210 box
->z
* (uint64_t)tex
->surface
.u
.legacy
.level
[level
].slice_size_dw
* 4 +
211 (box
->y
/ tex
->surface
.blk_h
* tex
->surface
.u
.legacy
.level
[level
].nblk_x
+
212 box
->x
/ tex
->surface
.blk_w
) *
217 static int si_init_surface(struct si_screen
*sscreen
, struct radeon_surf
*surface
,
218 const struct pipe_resource
*ptex
, enum radeon_surf_mode array_mode
,
219 bool is_imported
, bool is_scanout
, bool is_flushed_depth
,
220 bool tc_compatible_htile
)
222 const struct util_format_description
*desc
= util_format_description(ptex
->format
);
223 bool is_depth
, is_stencil
;
225 unsigned bpe
, flags
= 0;
227 is_depth
= util_format_has_depth(desc
);
228 is_stencil
= util_format_has_stencil(desc
);
230 if (!is_flushed_depth
&& ptex
->format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
) {
231 bpe
= 4; /* stencil is allocated separately */
233 bpe
= util_format_get_blocksize(ptex
->format
);
234 assert(util_is_power_of_two_or_zero(bpe
));
237 if (!is_flushed_depth
&& is_depth
) {
238 flags
|= RADEON_SURF_ZBUFFER
;
240 if (sscreen
->debug_flags
& DBG(NO_HYPERZ
)) {
241 flags
|= RADEON_SURF_NO_HTILE
;
242 } else if (tc_compatible_htile
&&
243 (sscreen
->info
.chip_class
>= GFX9
|| array_mode
== RADEON_SURF_MODE_2D
)) {
244 /* TC-compatible HTILE only supports Z32_FLOAT.
245 * GFX9 also supports Z16_UNORM.
246 * On GFX8, promote Z16 to Z32. DB->CB copies will convert
247 * the format for transfers.
249 if (sscreen
->info
.chip_class
== GFX8
)
252 flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
256 flags
|= RADEON_SURF_SBUFFER
;
259 if (sscreen
->info
.chip_class
>= GFX8
&&
260 (ptex
->flags
& SI_RESOURCE_FLAG_DISABLE_DCC
||
261 (sscreen
->info
.chip_class
< GFX10_3
&&
262 ptex
->format
== PIPE_FORMAT_R9G9B9E5_FLOAT
) ||
263 (ptex
->nr_samples
>= 2 && !sscreen
->dcc_msaa_allowed
)))
264 flags
|= RADEON_SURF_DISABLE_DCC
;
266 /* Stoney: 128bpp MSAA textures randomly fail piglit tests with DCC. */
267 if (sscreen
->info
.family
== CHIP_STONEY
&& bpe
== 16 && ptex
->nr_samples
>= 2)
268 flags
|= RADEON_SURF_DISABLE_DCC
;
270 /* GFX8: DCC clear for 4x and 8x MSAA array textures unimplemented. */
271 if (sscreen
->info
.chip_class
== GFX8
&& ptex
->nr_storage_samples
>= 4 && ptex
->array_size
> 1)
272 flags
|= RADEON_SURF_DISABLE_DCC
;
274 /* GFX9: DCC clear for 4x and 8x MSAA textures unimplemented. */
275 if (sscreen
->info
.chip_class
== GFX9
&&
276 (ptex
->nr_storage_samples
>= 4 ||
277 (sscreen
->info
.family
== CHIP_RAVEN
&& ptex
->nr_storage_samples
>= 2 && bpe
< 4)))
278 flags
|= RADEON_SURF_DISABLE_DCC
;
280 /* TODO: GFX10: DCC causes corruption with MSAA. */
281 if (sscreen
->info
.chip_class
>= GFX10
&& ptex
->nr_storage_samples
>= 2)
282 flags
|= RADEON_SURF_DISABLE_DCC
;
284 /* Shared textures must always set up DCC.
285 * If it's not present, it will be disabled by
286 * si_get_opaque_metadata later.
288 if (!is_imported
&& (sscreen
->debug_flags
& DBG(NO_DCC
)))
289 flags
|= RADEON_SURF_DISABLE_DCC
;
292 /* This should catch bugs in gallium users setting incorrect flags. */
293 assert(ptex
->nr_samples
<= 1 && ptex
->array_size
== 1 && ptex
->depth0
== 1 &&
294 ptex
->last_level
== 0 && !(flags
& RADEON_SURF_Z_OR_SBUFFER
));
296 flags
|= RADEON_SURF_SCANOUT
;
299 if (ptex
->bind
& PIPE_BIND_SHARED
)
300 flags
|= RADEON_SURF_SHAREABLE
;
302 flags
|= RADEON_SURF_IMPORTED
| RADEON_SURF_SHAREABLE
;
303 if (sscreen
->debug_flags
& DBG(NO_FMASK
))
304 flags
|= RADEON_SURF_NO_FMASK
;
306 if (sscreen
->info
.chip_class
== GFX9
&& (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MICRO_TILE_MODE
)) {
307 flags
|= RADEON_SURF_FORCE_MICRO_TILE_MODE
;
308 surface
->micro_tile_mode
= SI_RESOURCE_FLAG_MICRO_TILE_MODE_GET(ptex
->flags
);
311 if (ptex
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
) {
312 flags
|= RADEON_SURF_FORCE_SWIZZLE_MODE
;
314 if (sscreen
->info
.chip_class
>= GFX10
)
315 surface
->u
.gfx9
.surf
.swizzle_mode
= ADDR_SW_64KB_R_X
;
318 r
= sscreen
->ws
->surface_init(sscreen
->ws
, ptex
, flags
, bpe
, array_mode
, surface
);
326 void si_eliminate_fast_color_clear(struct si_context
*sctx
, struct si_texture
*tex
,
329 struct si_screen
*sscreen
= sctx
->screen
;
330 struct pipe_context
*ctx
= &sctx
->b
;
332 if (ctx
== sscreen
->aux_context
)
333 simple_mtx_lock(&sscreen
->aux_context_lock
);
335 unsigned n
= sctx
->num_decompress_calls
;
336 ctx
->flush_resource(ctx
, &tex
->buffer
.b
.b
);
338 /* Flush only if any fast clear elimination took place. */
339 bool flushed
= false;
340 if (n
!= sctx
->num_decompress_calls
)
342 ctx
->flush(ctx
, NULL
, 0);
346 *ctx_flushed
= flushed
;
348 if (ctx
== sscreen
->aux_context
)
349 simple_mtx_unlock(&sscreen
->aux_context_lock
);
352 void si_texture_discard_cmask(struct si_screen
*sscreen
, struct si_texture
*tex
)
354 if (!tex
->cmask_buffer
)
357 assert(tex
->buffer
.b
.b
.nr_samples
<= 1);
360 tex
->cmask_base_address_reg
= tex
->buffer
.gpu_address
>> 8;
361 tex
->dirty_level_mask
= 0;
363 tex
->cb_color_info
&= ~S_028C70_FAST_CLEAR(1);
365 if (tex
->cmask_buffer
!= &tex
->buffer
)
366 si_resource_reference(&tex
->cmask_buffer
, NULL
);
368 tex
->cmask_buffer
= NULL
;
370 /* Notify all contexts about the change. */
371 p_atomic_inc(&sscreen
->dirty_tex_counter
);
372 p_atomic_inc(&sscreen
->compressed_colortex_counter
);
375 static bool si_can_disable_dcc(struct si_texture
*tex
)
377 /* We can't disable DCC if it can be written by another process. */
378 return tex
->surface
.dcc_offset
&&
379 (!tex
->buffer
.b
.is_shared
||
380 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
));
383 static bool si_texture_discard_dcc(struct si_screen
*sscreen
, struct si_texture
*tex
)
385 if (!si_can_disable_dcc(tex
))
388 assert(tex
->dcc_separate_buffer
== NULL
);
391 ac_surface_zero_dcc_fields(&tex
->surface
);
393 /* Notify all contexts about the change. */
394 p_atomic_inc(&sscreen
->dirty_tex_counter
);
399 * Disable DCC for the texture. (first decompress, then discard metadata).
401 * There is unresolved multi-context synchronization issue between
402 * screen::aux_context and the current context. If applications do this with
403 * multiple contexts, it's already undefined behavior for them and we don't
404 * have to worry about that. The scenario is:
406 * If context 1 disables DCC and context 2 has queued commands that write
407 * to the texture via CB with DCC enabled, and the order of operations is
409 * context 2 queues draw calls rendering to the texture, but doesn't flush
410 * context 1 disables DCC and flushes
411 * context 1 & 2 reset descriptors and FB state
412 * context 2 flushes (new compressed tiles written by the draw calls)
413 * context 1 & 2 read garbage, because DCC is disabled, yet there are
416 * \param sctx the current context if you have one, or sscreen->aux_context
419 bool si_texture_disable_dcc(struct si_context
*sctx
, struct si_texture
*tex
)
421 struct si_screen
*sscreen
= sctx
->screen
;
423 if (!sctx
->has_graphics
)
424 return si_texture_discard_dcc(sscreen
, tex
);
426 if (!si_can_disable_dcc(tex
))
429 if (&sctx
->b
== sscreen
->aux_context
)
430 simple_mtx_lock(&sscreen
->aux_context_lock
);
432 /* Decompress DCC. */
433 si_decompress_dcc(sctx
, tex
);
434 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
436 if (&sctx
->b
== sscreen
->aux_context
)
437 simple_mtx_unlock(&sscreen
->aux_context_lock
);
439 return si_texture_discard_dcc(sscreen
, tex
);
442 static void si_reallocate_texture_inplace(struct si_context
*sctx
, struct si_texture
*tex
,
443 unsigned new_bind_flag
, bool invalidate_storage
)
445 struct pipe_screen
*screen
= sctx
->b
.screen
;
446 struct si_texture
*new_tex
;
447 struct pipe_resource templ
= tex
->buffer
.b
.b
;
450 templ
.bind
|= new_bind_flag
;
452 if (tex
->buffer
.b
.is_shared
|| tex
->num_planes
> 1)
455 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
456 if (tex
->surface
.is_linear
)
459 /* This fails with MSAA, depth, and compressed textures. */
460 if (si_choose_tiling(sctx
->screen
, &templ
, false) != RADEON_SURF_MODE_LINEAR_ALIGNED
)
464 new_tex
= (struct si_texture
*)screen
->resource_create(screen
, &templ
);
468 /* Copy the pixels to the new texture. */
469 if (!invalidate_storage
) {
470 for (i
= 0; i
<= templ
.last_level
; i
++) {
473 u_box_3d(0, 0, 0, u_minify(templ
.width0
, i
), u_minify(templ
.height0
, i
),
474 util_num_layers(&templ
, i
), &box
);
476 sctx
->dma_copy(&sctx
->b
, &new_tex
->buffer
.b
.b
, i
, 0, 0, 0, &tex
->buffer
.b
.b
, i
, &box
);
480 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
481 si_texture_discard_cmask(sctx
->screen
, tex
);
482 si_texture_discard_dcc(sctx
->screen
, tex
);
485 /* Replace the structure fields of tex. */
486 tex
->buffer
.b
.b
.bind
= templ
.bind
;
487 pb_reference(&tex
->buffer
.buf
, new_tex
->buffer
.buf
);
488 tex
->buffer
.gpu_address
= new_tex
->buffer
.gpu_address
;
489 tex
->buffer
.vram_usage
= new_tex
->buffer
.vram_usage
;
490 tex
->buffer
.gart_usage
= new_tex
->buffer
.gart_usage
;
491 tex
->buffer
.bo_size
= new_tex
->buffer
.bo_size
;
492 tex
->buffer
.bo_alignment
= new_tex
->buffer
.bo_alignment
;
493 tex
->buffer
.domains
= new_tex
->buffer
.domains
;
494 tex
->buffer
.flags
= new_tex
->buffer
.flags
;
496 tex
->surface
= new_tex
->surface
;
497 si_texture_reference(&tex
->flushed_depth_texture
, new_tex
->flushed_depth_texture
);
499 tex
->surface
.fmask_offset
= new_tex
->surface
.fmask_offset
;
500 tex
->surface
.cmask_offset
= new_tex
->surface
.cmask_offset
;
501 tex
->cmask_base_address_reg
= new_tex
->cmask_base_address_reg
;
503 if (tex
->cmask_buffer
== &tex
->buffer
)
504 tex
->cmask_buffer
= NULL
;
506 si_resource_reference(&tex
->cmask_buffer
, NULL
);
508 if (new_tex
->cmask_buffer
== &new_tex
->buffer
)
509 tex
->cmask_buffer
= &tex
->buffer
;
511 si_resource_reference(&tex
->cmask_buffer
, new_tex
->cmask_buffer
);
513 tex
->surface
.dcc_offset
= new_tex
->surface
.dcc_offset
;
514 tex
->cb_color_info
= new_tex
->cb_color_info
;
515 memcpy(tex
->color_clear_value
, new_tex
->color_clear_value
, sizeof(tex
->color_clear_value
));
516 tex
->last_msaa_resolve_target_micro_mode
= new_tex
->last_msaa_resolve_target_micro_mode
;
518 tex
->surface
.htile_offset
= new_tex
->surface
.htile_offset
;
519 tex
->depth_clear_value
= new_tex
->depth_clear_value
;
520 tex
->dirty_level_mask
= new_tex
->dirty_level_mask
;
521 tex
->stencil_dirty_level_mask
= new_tex
->stencil_dirty_level_mask
;
522 tex
->db_render_format
= new_tex
->db_render_format
;
523 tex
->stencil_clear_value
= new_tex
->stencil_clear_value
;
524 tex
->tc_compatible_htile
= new_tex
->tc_compatible_htile
;
525 tex
->depth_cleared
= new_tex
->depth_cleared
;
526 tex
->stencil_cleared
= new_tex
->stencil_cleared
;
527 tex
->upgraded_depth
= new_tex
->upgraded_depth
;
528 tex
->db_compatible
= new_tex
->db_compatible
;
529 tex
->can_sample_z
= new_tex
->can_sample_z
;
530 tex
->can_sample_s
= new_tex
->can_sample_s
;
532 tex
->separate_dcc_dirty
= new_tex
->separate_dcc_dirty
;
533 tex
->displayable_dcc_dirty
= new_tex
->displayable_dcc_dirty
;
534 tex
->dcc_gather_statistics
= new_tex
->dcc_gather_statistics
;
535 si_resource_reference(&tex
->dcc_separate_buffer
, new_tex
->dcc_separate_buffer
);
536 si_resource_reference(&tex
->last_dcc_separate_buffer
, new_tex
->last_dcc_separate_buffer
);
538 if (new_bind_flag
== PIPE_BIND_LINEAR
) {
539 assert(!tex
->surface
.htile_offset
);
540 assert(!tex
->cmask_buffer
);
541 assert(!tex
->surface
.fmask_size
);
542 assert(!tex
->surface
.dcc_offset
);
543 assert(!tex
->is_depth
);
546 si_texture_reference(&new_tex
, NULL
);
548 p_atomic_inc(&sctx
->screen
->dirty_tex_counter
);
551 static void si_set_tex_bo_metadata(struct si_screen
*sscreen
, struct si_texture
*tex
)
553 struct pipe_resource
*res
= &tex
->buffer
.b
.b
;
554 struct radeon_bo_metadata md
;
556 memset(&md
, 0, sizeof(md
));
558 assert(tex
->dcc_separate_buffer
== NULL
);
559 assert(tex
->surface
.fmask_size
== 0);
561 static const unsigned char swizzle
[] = {PIPE_SWIZZLE_X
, PIPE_SWIZZLE_Y
, PIPE_SWIZZLE_Z
,
563 bool is_array
= util_texture_is_array(res
->target
);
566 sscreen
->make_texture_descriptor(sscreen
, tex
, true, res
->target
, res
->format
, swizzle
, 0,
567 res
->last_level
, 0, is_array
? res
->array_size
- 1 : 0,
568 res
->width0
, res
->height0
, res
->depth0
, desc
, NULL
);
569 si_set_mutable_tex_desc_fields(sscreen
, tex
, &tex
->surface
.u
.legacy
.level
[0], 0, 0,
570 tex
->surface
.blk_w
, false, false, desc
);
572 ac_surface_get_umd_metadata(&sscreen
->info
, &tex
->surface
,
573 tex
->buffer
.b
.b
.last_level
+ 1,
574 desc
, &md
.size_metadata
, md
.metadata
);
575 sscreen
->ws
->buffer_set_metadata(tex
->buffer
.buf
, &md
, &tex
->surface
);
578 static bool si_has_displayable_dcc(struct si_texture
*tex
)
580 struct si_screen
*sscreen
= (struct si_screen
*)tex
->buffer
.b
.b
.screen
;
582 if (sscreen
->info
.chip_class
<= GFX8
)
585 return tex
->surface
.is_displayable
&& tex
->surface
.dcc_offset
;
588 static bool si_resource_get_param(struct pipe_screen
*screen
, struct pipe_context
*context
,
589 struct pipe_resource
*resource
, unsigned plane
, unsigned layer
,
590 enum pipe_resource_param param
, unsigned handle_usage
,
593 for (unsigned i
= 0; i
< plane
; i
++)
594 resource
= resource
->next
;
596 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
597 struct si_texture
*tex
= (struct si_texture
*)resource
;
598 struct winsys_handle whandle
;
601 case PIPE_RESOURCE_PARAM_NPLANES
:
602 *value
= resource
->target
== PIPE_BUFFER
? 1 : tex
->num_planes
;
605 case PIPE_RESOURCE_PARAM_STRIDE
:
606 if (resource
->target
== PIPE_BUFFER
)
608 else if (sscreen
->info
.chip_class
>= GFX9
)
609 *value
= tex
->surface
.u
.gfx9
.surf_pitch
* tex
->surface
.bpe
;
611 *value
= tex
->surface
.u
.legacy
.level
[0].nblk_x
* tex
->surface
.bpe
;
614 case PIPE_RESOURCE_PARAM_OFFSET
:
615 if (resource
->target
== PIPE_BUFFER
)
617 else if (sscreen
->info
.chip_class
>= GFX9
)
618 *value
= tex
->surface
.u
.gfx9
.surf_offset
+ layer
* tex
->surface
.u
.gfx9
.surf_slice_size
;
620 *value
= tex
->surface
.u
.legacy
.level
[0].offset
+
621 layer
* (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
624 case PIPE_RESOURCE_PARAM_MODIFIER
:
625 *value
= DRM_FORMAT_MOD_INVALID
;
628 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
:
629 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
:
630 case PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
:
631 memset(&whandle
, 0, sizeof(whandle
));
633 if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_SHARED
)
634 whandle
.type
= WINSYS_HANDLE_TYPE_SHARED
;
635 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_KMS
)
636 whandle
.type
= WINSYS_HANDLE_TYPE_KMS
;
637 else if (param
== PIPE_RESOURCE_PARAM_HANDLE_TYPE_FD
)
638 whandle
.type
= WINSYS_HANDLE_TYPE_FD
;
640 if (!screen
->resource_get_handle(screen
, context
, resource
, &whandle
, handle_usage
))
643 *value
= whandle
.handle
;
649 static void si_texture_get_info(struct pipe_screen
*screen
, struct pipe_resource
*resource
,
650 unsigned *pstride
, unsigned *poffset
)
655 si_resource_get_param(screen
, NULL
, resource
, 0, 0, PIPE_RESOURCE_PARAM_STRIDE
, 0, &value
);
660 si_resource_get_param(screen
, NULL
, resource
, 0, 0, PIPE_RESOURCE_PARAM_OFFSET
, 0, &value
);
665 static bool si_texture_get_handle(struct pipe_screen
*screen
, struct pipe_context
*ctx
,
666 struct pipe_resource
*resource
, struct winsys_handle
*whandle
,
669 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
670 struct si_context
*sctx
;
671 struct si_resource
*res
= si_resource(resource
);
672 struct si_texture
*tex
= (struct si_texture
*)resource
;
673 bool update_metadata
= false;
674 unsigned stride
, offset
, slice_size
;
677 ctx
= threaded_context_unwrap_sync(ctx
);
678 sctx
= (struct si_context
*)(ctx
? ctx
: sscreen
->aux_context
);
680 if (resource
->target
!= PIPE_BUFFER
) {
681 /* Individual planes are chained pipe_resource instances. */
682 for (unsigned i
= 0; i
< whandle
->plane
; i
++) {
683 resource
= resource
->next
;
684 res
= si_resource(resource
);
685 tex
= (struct si_texture
*)resource
;
688 /* This is not supported now, but it might be required for OpenCL
689 * interop in the future.
691 if (resource
->nr_samples
> 1 || tex
->is_depth
)
694 /* Move a suballocated texture into a non-suballocated allocation. */
695 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) || tex
->surface
.tile_swizzle
||
696 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
697 sscreen
->info
.has_local_buffers
)) {
698 assert(!res
->b
.is_shared
);
699 si_reallocate_texture_inplace(sctx
, tex
, PIPE_BIND_SHARED
, false);
701 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
702 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
703 assert(!(res
->flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
));
704 assert(tex
->surface
.tile_swizzle
== 0);
707 /* Since shader image stores don't support DCC on GFX8,
708 * disable it for external clients that want write
711 if ((usage
& PIPE_HANDLE_USAGE_SHADER_WRITE
&& tex
->surface
.dcc_offset
) ||
712 /* Displayable DCC requires an explicit flush. */
713 (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) && si_has_displayable_dcc(tex
))) {
714 if (si_texture_disable_dcc(sctx
, tex
)) {
715 update_metadata
= true;
716 /* si_texture_disable_dcc flushes the context */
721 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
722 (tex
->cmask_buffer
|| tex
->surface
.dcc_offset
)) {
723 /* Eliminate fast clear (both CMASK and DCC) */
725 si_eliminate_fast_color_clear(sctx
, tex
, &flushed
);
726 /* eliminate_fast_color_clear sometimes flushes the context */
730 /* Disable CMASK if flush_resource isn't going
733 if (tex
->cmask_buffer
)
734 si_texture_discard_cmask(sscreen
, tex
);
738 if ((!res
->b
.is_shared
|| update_metadata
) && whandle
->offset
== 0)
739 si_set_tex_bo_metadata(sscreen
, tex
);
741 if (sscreen
->info
.chip_class
>= GFX9
) {
742 slice_size
= tex
->surface
.u
.gfx9
.surf_slice_size
;
744 slice_size
= (uint64_t)tex
->surface
.u
.legacy
.level
[0].slice_size_dw
* 4;
747 /* Buffer exports are for the OpenCL interop. */
748 /* Move a suballocated buffer into a non-suballocated allocation. */
749 if (sscreen
->ws
->buffer_is_suballocated(res
->buf
) ||
750 /* A DMABUF export always fails if the BO is local. */
751 (tex
->buffer
.flags
& RADEON_FLAG_NO_INTERPROCESS_SHARING
&&
752 sscreen
->info
.has_local_buffers
)) {
753 assert(!res
->b
.is_shared
);
755 /* Allocate a new buffer with PIPE_BIND_SHARED. */
756 struct pipe_resource templ
= res
->b
.b
;
757 templ
.bind
|= PIPE_BIND_SHARED
;
759 struct pipe_resource
*newb
= screen
->resource_create(screen
, &templ
);
763 /* Copy the old buffer contents to the new one. */
765 u_box_1d(0, newb
->width0
, &box
);
766 sctx
->b
.resource_copy_region(&sctx
->b
, newb
, 0, 0, 0, 0, &res
->b
.b
, 0, &box
);
768 /* Move the new buffer storage to the old pipe_resource. */
769 si_replace_buffer_storage(&sctx
->b
, &res
->b
.b
, newb
);
770 pipe_resource_reference(&newb
, NULL
);
772 assert(res
->b
.b
.bind
& PIPE_BIND_SHARED
);
773 assert(res
->flags
& RADEON_FLAG_NO_SUBALLOC
);
780 si_texture_get_info(screen
, resource
, &stride
, &offset
);
783 sctx
->b
.flush(&sctx
->b
, NULL
, 0);
785 if (res
->b
.is_shared
) {
786 /* USAGE_EXPLICIT_FLUSH must be cleared if at least one user
789 res
->external_usage
|= usage
& ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
790 if (!(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
))
791 res
->external_usage
&= ~PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
;
793 res
->b
.is_shared
= true;
794 res
->external_usage
= usage
;
797 whandle
->stride
= stride
;
798 whandle
->offset
= offset
+ slice_size
* whandle
->layer
;
800 return sscreen
->ws
->buffer_get_handle(sscreen
->ws
, res
->buf
, whandle
);
803 static void si_texture_destroy(struct pipe_screen
*screen
, struct pipe_resource
*ptex
)
805 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
806 struct si_texture
*tex
= (struct si_texture
*)ptex
;
807 struct si_resource
*resource
= &tex
->buffer
;
809 if (sscreen
->info
.chip_class
>= GFX9
)
810 free(tex
->surface
.u
.gfx9
.dcc_retile_map
);
812 si_texture_reference(&tex
->flushed_depth_texture
, NULL
);
814 if (tex
->cmask_buffer
!= &tex
->buffer
) {
815 si_resource_reference(&tex
->cmask_buffer
, NULL
);
817 pb_reference(&resource
->buf
, NULL
);
818 si_resource_reference(&tex
->dcc_separate_buffer
, NULL
);
819 si_resource_reference(&tex
->last_dcc_separate_buffer
, NULL
);
823 static const struct u_resource_vtbl si_texture_vtbl
;
825 void si_print_texture_info(struct si_screen
*sscreen
, struct si_texture
*tex
,
826 struct u_log_context
*log
)
830 /* Common parameters. */
832 " Info: npix_x=%u, npix_y=%u, npix_z=%u, blk_w=%u, "
833 "blk_h=%u, array_size=%u, last_level=%u, "
834 "bpe=%u, nsamples=%u, flags=0x%x, %s\n",
835 tex
->buffer
.b
.b
.width0
, tex
->buffer
.b
.b
.height0
, tex
->buffer
.b
.b
.depth0
,
836 tex
->surface
.blk_w
, tex
->surface
.blk_h
, tex
->buffer
.b
.b
.array_size
,
837 tex
->buffer
.b
.b
.last_level
, tex
->surface
.bpe
, tex
->buffer
.b
.b
.nr_samples
,
838 tex
->surface
.flags
, util_format_short_name(tex
->buffer
.b
.b
.format
));
840 if (sscreen
->info
.chip_class
>= GFX9
) {
842 " Surf: size=%" PRIu64
", slice_size=%" PRIu64
", "
843 "alignment=%u, swmode=%u, epitch=%u, pitch=%u\n",
844 tex
->surface
.surf_size
, tex
->surface
.u
.gfx9
.surf_slice_size
,
845 tex
->surface
.surf_alignment
, tex
->surface
.u
.gfx9
.surf
.swizzle_mode
,
846 tex
->surface
.u
.gfx9
.surf
.epitch
, tex
->surface
.u
.gfx9
.surf_pitch
);
848 if (tex
->surface
.fmask_offset
) {
850 " FMASK: offset=%" PRIu64
", size=%" PRIu64
", "
851 "alignment=%u, swmode=%u, epitch=%u\n",
852 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
,
853 tex
->surface
.fmask_alignment
, tex
->surface
.u
.gfx9
.fmask
.swizzle_mode
,
854 tex
->surface
.u
.gfx9
.fmask
.epitch
);
857 if (tex
->cmask_buffer
) {
859 " CMask: offset=%" PRIu64
", size=%u, "
861 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
,
862 tex
->surface
.cmask_alignment
);
865 if (tex
->surface
.htile_offset
) {
867 " HTile: offset=%" PRIu64
", size=%u, alignment=%u\n",
868 tex
->surface
.htile_offset
, tex
->surface
.htile_size
,
869 tex
->surface
.htile_alignment
);
872 if (tex
->surface
.dcc_offset
) {
874 " DCC: offset=%" PRIu64
", size=%u, "
875 "alignment=%u, pitch_max=%u, num_dcc_levels=%u\n",
876 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
,
877 tex
->surface
.u
.gfx9
.display_dcc_pitch_max
, tex
->surface
.num_dcc_levels
);
880 if (tex
->surface
.u
.gfx9
.stencil_offset
) {
881 u_log_printf(log
, " Stencil: offset=%" PRIu64
", swmode=%u, epitch=%u\n",
882 tex
->surface
.u
.gfx9
.stencil_offset
, tex
->surface
.u
.gfx9
.stencil
.swizzle_mode
,
883 tex
->surface
.u
.gfx9
.stencil
.epitch
);
889 " Layout: size=%" PRIu64
", alignment=%u, bankw=%u, "
890 "bankh=%u, nbanks=%u, mtilea=%u, tilesplit=%u, pipeconfig=%u, scanout=%u\n",
891 tex
->surface
.surf_size
, tex
->surface
.surf_alignment
, tex
->surface
.u
.legacy
.bankw
,
892 tex
->surface
.u
.legacy
.bankh
, tex
->surface
.u
.legacy
.num_banks
,
893 tex
->surface
.u
.legacy
.mtilea
, tex
->surface
.u
.legacy
.tile_split
,
894 tex
->surface
.u
.legacy
.pipe_config
, (tex
->surface
.flags
& RADEON_SURF_SCANOUT
) != 0);
896 if (tex
->surface
.fmask_offset
)
899 " FMask: offset=%" PRIu64
", size=%" PRIu64
", alignment=%u, pitch_in_pixels=%u, "
900 "bankh=%u, slice_tile_max=%u, tile_mode_index=%u\n",
901 tex
->surface
.fmask_offset
, tex
->surface
.fmask_size
, tex
->surface
.fmask_alignment
,
902 tex
->surface
.u
.legacy
.fmask
.pitch_in_pixels
, tex
->surface
.u
.legacy
.fmask
.bankh
,
903 tex
->surface
.u
.legacy
.fmask
.slice_tile_max
, tex
->surface
.u
.legacy
.fmask
.tiling_index
);
905 if (tex
->cmask_buffer
)
907 " CMask: offset=%" PRIu64
", size=%u, alignment=%u, "
908 "slice_tile_max=%u\n",
909 tex
->surface
.cmask_offset
, tex
->surface
.cmask_size
, tex
->surface
.cmask_alignment
,
910 tex
->surface
.u
.legacy
.cmask_slice_tile_max
);
912 if (tex
->surface
.htile_offset
)
914 " HTile: offset=%" PRIu64
", size=%u, "
915 "alignment=%u, TC_compatible = %u\n",
916 tex
->surface
.htile_offset
, tex
->surface
.htile_size
, tex
->surface
.htile_alignment
,
917 tex
->tc_compatible_htile
);
919 if (tex
->surface
.dcc_offset
) {
920 u_log_printf(log
, " DCC: offset=%" PRIu64
", size=%u, alignment=%u\n",
921 tex
->surface
.dcc_offset
, tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
);
922 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
924 " DCCLevel[%i]: enabled=%u, offset=%u, "
925 "fast_clear_size=%u\n",
926 i
, i
< tex
->surface
.num_dcc_levels
, tex
->surface
.u
.legacy
.level
[i
].dcc_offset
,
927 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
);
930 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++)
932 " Level[%i]: offset=%" PRIu64
", slice_size=%" PRIu64
", "
933 "npix_x=%u, npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
934 "mode=%u, tiling_index = %u\n",
935 i
, tex
->surface
.u
.legacy
.level
[i
].offset
,
936 (uint64_t)tex
->surface
.u
.legacy
.level
[i
].slice_size_dw
* 4,
937 u_minify(tex
->buffer
.b
.b
.width0
, i
), u_minify(tex
->buffer
.b
.b
.height0
, i
),
938 u_minify(tex
->buffer
.b
.b
.depth0
, i
), tex
->surface
.u
.legacy
.level
[i
].nblk_x
,
939 tex
->surface
.u
.legacy
.level
[i
].nblk_y
, tex
->surface
.u
.legacy
.level
[i
].mode
,
940 tex
->surface
.u
.legacy
.tiling_index
[i
]);
942 if (tex
->surface
.has_stencil
) {
943 u_log_printf(log
, " StencilLayout: tilesplit=%u\n",
944 tex
->surface
.u
.legacy
.stencil_tile_split
);
945 for (i
= 0; i
<= tex
->buffer
.b
.b
.last_level
; i
++) {
947 " StencilLevel[%i]: offset=%" PRIu64
", "
948 "slice_size=%" PRIu64
", npix_x=%u, "
949 "npix_y=%u, npix_z=%u, nblk_x=%u, nblk_y=%u, "
950 "mode=%u, tiling_index = %u\n",
951 i
, tex
->surface
.u
.legacy
.stencil_level
[i
].offset
,
952 (uint64_t)tex
->surface
.u
.legacy
.stencil_level
[i
].slice_size_dw
* 4,
953 u_minify(tex
->buffer
.b
.b
.width0
, i
), u_minify(tex
->buffer
.b
.b
.height0
, i
),
954 u_minify(tex
->buffer
.b
.b
.depth0
, i
),
955 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_x
,
956 tex
->surface
.u
.legacy
.stencil_level
[i
].nblk_y
,
957 tex
->surface
.u
.legacy
.stencil_level
[i
].mode
,
958 tex
->surface
.u
.legacy
.stencil_tiling_index
[i
]);
964 * Common function for si_texture_create and si_texture_from_handle.
966 * \param screen screen
967 * \param base resource template
968 * \param surface radeon_surf
969 * \param plane0 if a non-zero plane is being created, this is the first plane
970 * \param imported_buf from si_texture_from_handle
971 * \param offset offset for non-zero planes or imported buffers
972 * \param alloc_size the size to allocate if plane0 != NULL
973 * \param alignment alignment for the allocation
975 static struct si_texture
*si_texture_create_object(struct pipe_screen
*screen
,
976 const struct pipe_resource
*base
,
977 const struct radeon_surf
*surface
,
978 const struct si_texture
*plane0
,
979 struct pb_buffer
*imported_buf
,
980 uint64_t offset
, unsigned pitch_in_bytes
,
981 uint64_t alloc_size
, unsigned alignment
)
983 struct si_texture
*tex
;
984 struct si_resource
*resource
;
985 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
987 tex
= CALLOC_STRUCT(si_texture
);
991 resource
= &tex
->buffer
;
992 resource
->b
.b
= *base
;
993 resource
->b
.vtbl
= &si_texture_vtbl
;
994 pipe_reference_init(&resource
->b
.b
.reference
, 1);
995 resource
->b
.b
.screen
= screen
;
997 /* don't include stencil-only formats which we don't support for rendering */
998 tex
->is_depth
= util_format_has_depth(util_format_description(tex
->buffer
.b
.b
.format
));
999 tex
->surface
= *surface
;
1001 /* On GFX8, HTILE uses different tiling depending on the TC_COMPATIBLE_HTILE
1002 * setting, so we have to enable it if we enabled it at allocation.
1004 * GFX9 and later use the same tiling for both, so TC-compatible HTILE can be
1005 * enabled on demand.
1007 tex
->tc_compatible_htile
= sscreen
->info
.chip_class
== GFX8
&&
1008 tex
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1010 /* TC-compatible HTILE:
1011 * - GFX8 only supports Z32_FLOAT.
1012 * - GFX9 only supports Z32_FLOAT and Z16_UNORM. */
1013 if (tex
->surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
) {
1014 if (sscreen
->info
.chip_class
>= GFX9
&& base
->format
== PIPE_FORMAT_Z16_UNORM
)
1015 tex
->db_render_format
= base
->format
;
1017 tex
->db_render_format
= PIPE_FORMAT_Z32_FLOAT
;
1018 tex
->upgraded_depth
= base
->format
!= PIPE_FORMAT_Z32_FLOAT
&&
1019 base
->format
!= PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
;
1022 tex
->db_render_format
= base
->format
;
1025 /* Applies to GCN. */
1026 tex
->last_msaa_resolve_target_micro_mode
= tex
->surface
.micro_tile_mode
;
1028 /* Disable separate DCC at the beginning. DRI2 doesn't reuse buffers
1029 * between frames, so the only thing that can enable separate DCC
1030 * with DRI2 is multiple slow clears within a frame.
1032 tex
->ps_draw_ratio
= 0;
1034 ac_surface_override_offset_stride(&sscreen
->info
, &tex
->surface
,
1035 tex
->buffer
.b
.b
.last_level
+ 1,
1036 offset
, pitch_in_bytes
/ tex
->surface
.bpe
);
1038 if (tex
->is_depth
) {
1039 if (sscreen
->info
.chip_class
>= GFX9
) {
1040 tex
->can_sample_z
= true;
1041 tex
->can_sample_s
= true;
1043 /* Stencil texturing with HTILE doesn't work
1044 * with mipmapping on Navi10-14. */
1045 if (sscreen
->info
.chip_class
== GFX10
&& base
->last_level
> 0)
1046 tex
->htile_stencil_disabled
= true;
1048 tex
->can_sample_z
= !tex
->surface
.u
.legacy
.depth_adjusted
;
1049 tex
->can_sample_s
= !tex
->surface
.u
.legacy
.stencil_adjusted
;
1052 tex
->db_compatible
= surface
->flags
& RADEON_SURF_ZBUFFER
;
1054 if (tex
->surface
.cmask_offset
) {
1055 tex
->cb_color_info
|= S_028C70_FAST_CLEAR(1);
1056 tex
->cmask_buffer
= &tex
->buffer
;
1061 /* The buffer is shared with the first plane. */
1062 resource
->bo_size
= plane0
->buffer
.bo_size
;
1063 resource
->bo_alignment
= plane0
->buffer
.bo_alignment
;
1064 resource
->flags
= plane0
->buffer
.flags
;
1065 resource
->domains
= plane0
->buffer
.domains
;
1066 resource
->vram_usage
= plane0
->buffer
.vram_usage
;
1067 resource
->gart_usage
= plane0
->buffer
.gart_usage
;
1069 pb_reference(&resource
->buf
, plane0
->buffer
.buf
);
1070 resource
->gpu_address
= plane0
->buffer
.gpu_address
;
1071 } else if (!(surface
->flags
& RADEON_SURF_IMPORTED
)) {
1072 /* Create the backing buffer. */
1073 si_init_resource_fields(sscreen
, resource
, alloc_size
, alignment
);
1075 if (!si_alloc_resource(sscreen
, resource
))
1078 resource
->buf
= imported_buf
;
1079 resource
->gpu_address
= sscreen
->ws
->buffer_get_virtual_address(resource
->buf
);
1080 resource
->bo_size
= imported_buf
->size
;
1081 resource
->bo_alignment
= imported_buf
->alignment
;
1082 resource
->domains
= sscreen
->ws
->buffer_get_initial_domain(resource
->buf
);
1083 if (resource
->domains
& RADEON_DOMAIN_VRAM
)
1084 resource
->vram_usage
= resource
->bo_size
;
1085 else if (resource
->domains
& RADEON_DOMAIN_GTT
)
1086 resource
->gart_usage
= resource
->bo_size
;
1087 if (sscreen
->ws
->buffer_get_flags
)
1088 resource
->flags
= sscreen
->ws
->buffer_get_flags(resource
->buf
);
1091 if (tex
->cmask_buffer
) {
1092 /* Initialize the cmask to 0xCC (= compressed state). */
1093 si_screen_clear_buffer(sscreen
, &tex
->cmask_buffer
->b
.b
, tex
->surface
.cmask_offset
,
1094 tex
->surface
.cmask_size
, 0xCCCCCCCC);
1096 if (tex
->surface
.htile_offset
) {
1097 uint32_t clear_value
= 0;
1099 if (sscreen
->info
.chip_class
>= GFX9
|| tex
->tc_compatible_htile
)
1100 clear_value
= 0x0000030F;
1102 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.htile_offset
,
1103 tex
->surface
.htile_size
, clear_value
);
1106 /* Initialize DCC only if the texture is not being imported. */
1107 if (!(surface
->flags
& RADEON_SURF_IMPORTED
) && tex
->surface
.dcc_offset
) {
1108 /* Clear DCC to black for all tiles with DCC enabled.
1110 * This fixes corruption in 3DMark Slingshot Extreme, which
1111 * uses uninitialized textures, causing corruption.
1113 if (tex
->surface
.num_dcc_levels
== tex
->buffer
.b
.b
.last_level
+ 1 &&
1114 tex
->buffer
.b
.b
.nr_samples
<= 2) {
1115 /* Simple case - all tiles have DCC enabled. */
1116 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1117 tex
->surface
.dcc_size
, DCC_CLEAR_COLOR_0000
);
1118 } else if (sscreen
->info
.chip_class
>= GFX9
) {
1119 /* Clear to uncompressed. Clearing this to black is complicated. */
1120 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1121 tex
->surface
.dcc_size
, DCC_UNCOMPRESSED
);
1123 /* GFX8: Initialize mipmap levels and multisamples separately. */
1124 if (tex
->buffer
.b
.b
.nr_samples
>= 2) {
1125 /* Clearing this to black is complicated. */
1126 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
,
1127 tex
->surface
.dcc_size
, DCC_UNCOMPRESSED
);
1129 /* Clear the enabled mipmap levels to black. */
1132 for (unsigned i
= 0; i
< tex
->surface
.num_dcc_levels
; i
++) {
1133 if (!tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
)
1136 size
= tex
->surface
.u
.legacy
.level
[i
].dcc_offset
+
1137 tex
->surface
.u
.legacy
.level
[i
].dcc_fast_clear_size
;
1140 /* Mipmap levels with DCC. */
1142 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
, size
,
1143 DCC_CLEAR_COLOR_0000
);
1145 /* Mipmap levels without DCC. */
1146 if (size
!= tex
->surface
.dcc_size
) {
1147 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.dcc_offset
+ size
,
1148 tex
->surface
.dcc_size
- size
, DCC_UNCOMPRESSED
);
1153 /* Initialize displayable DCC that requires the retile blit. */
1154 if (tex
->surface
.dcc_retile_map_offset
) {
1155 /* Uninitialized DCC can hang the display hw.
1156 * Clear to white to indicate that. */
1157 si_screen_clear_buffer(sscreen
, &tex
->buffer
.b
.b
, tex
->surface
.display_dcc_offset
,
1158 tex
->surface
.u
.gfx9
.display_dcc_size
, DCC_CLEAR_COLOR_1111
);
1160 /* Upload the DCC retile map.
1161 * Use a staging buffer for the upload, because
1162 * the buffer backing the texture is unmappable.
1164 bool use_uint16
= tex
->surface
.u
.gfx9
.dcc_retile_use_uint16
;
1165 unsigned num_elements
= tex
->surface
.u
.gfx9
.dcc_retile_num_elements
;
1166 struct si_resource
*buf
= si_aligned_buffer_create(screen
, 0, PIPE_USAGE_STREAM
,
1167 num_elements
* (use_uint16
? 2 : 4),
1168 sscreen
->info
.tcc_cache_line_size
);
1169 uint32_t *ui
= (uint32_t *)sscreen
->ws
->buffer_map(buf
->buf
, NULL
, PIPE_TRANSFER_WRITE
);
1170 uint16_t *us
= (uint16_t *)ui
;
1172 /* Upload the retile map into a staging buffer. */
1174 for (unsigned i
= 0; i
< num_elements
; i
++)
1175 us
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1177 for (unsigned i
= 0; i
< num_elements
; i
++)
1178 ui
[i
] = tex
->surface
.u
.gfx9
.dcc_retile_map
[i
];
1181 /* Copy the staging buffer to the buffer backing the texture. */
1182 struct si_context
*sctx
= (struct si_context
*)sscreen
->aux_context
;
1184 assert(tex
->surface
.dcc_retile_map_offset
<= UINT_MAX
);
1185 simple_mtx_lock(&sscreen
->aux_context_lock
);
1186 si_sdma_copy_buffer(sctx
, &tex
->buffer
.b
.b
, &buf
->b
.b
, tex
->surface
.dcc_retile_map_offset
,
1187 0, buf
->b
.b
.width0
);
1188 sscreen
->aux_context
->flush(sscreen
->aux_context
, NULL
, 0);
1189 simple_mtx_unlock(&sscreen
->aux_context_lock
);
1191 si_resource_reference(&buf
, NULL
);
1195 /* Initialize the CMASK base register value. */
1196 tex
->cmask_base_address_reg
= (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1198 if (sscreen
->debug_flags
& DBG(VM
)) {
1200 "VM start=0x%" PRIX64
" end=0x%" PRIX64
1201 " | Texture %ix%ix%i, %i levels, %i samples, %s\n",
1202 tex
->buffer
.gpu_address
, tex
->buffer
.gpu_address
+ tex
->buffer
.buf
->size
,
1203 base
->width0
, base
->height0
, util_num_layers(base
, 0), base
->last_level
+ 1,
1204 base
->nr_samples
? base
->nr_samples
: 1, util_format_short_name(base
->format
));
1207 if (sscreen
->debug_flags
& DBG(TEX
)) {
1209 struct u_log_context log
;
1210 u_log_context_init(&log
);
1211 si_print_texture_info(sscreen
, tex
, &log
);
1212 u_log_new_page_print(&log
, stdout
);
1214 u_log_context_destroy(&log
);
1221 if (sscreen
->info
.chip_class
>= GFX9
)
1222 free(surface
->u
.gfx9
.dcc_retile_map
);
1226 static enum radeon_surf_mode
si_choose_tiling(struct si_screen
*sscreen
,
1227 const struct pipe_resource
*templ
,
1228 bool tc_compatible_htile
)
1230 const struct util_format_description
*desc
= util_format_description(templ
->format
);
1231 bool force_tiling
= templ
->flags
& SI_RESOURCE_FLAG_FORCE_MSAA_TILING
;
1232 bool is_depth_stencil
= util_format_is_depth_or_stencil(templ
->format
) &&
1233 !(templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
);
1235 /* MSAA resources must be 2D tiled. */
1236 if (templ
->nr_samples
> 1)
1237 return RADEON_SURF_MODE_2D
;
1239 /* Transfer resources should be linear. */
1240 if (templ
->flags
& SI_RESOURCE_FLAG_FORCE_LINEAR
)
1241 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1243 /* Avoid Z/S decompress blits by forcing TC-compatible HTILE on GFX8,
1244 * which requires 2D tiling.
1246 if (sscreen
->info
.chip_class
== GFX8
&& tc_compatible_htile
)
1247 return RADEON_SURF_MODE_2D
;
1249 /* Handle common candidates for the linear mode.
1250 * Compressed textures and DB surfaces must always be tiled.
1252 if (!force_tiling
&& !is_depth_stencil
&& !util_format_is_compressed(templ
->format
)) {
1253 if (sscreen
->debug_flags
& DBG(NO_TILING
))
1254 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1256 /* Tiling doesn't work with the 422 (SUBSAMPLED) formats. */
1257 if (desc
->layout
== UTIL_FORMAT_LAYOUT_SUBSAMPLED
)
1258 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1260 /* Cursors are linear on AMD GCN.
1261 * (XXX double-check, maybe also use RADEON_SURF_SCANOUT) */
1262 if (templ
->bind
& PIPE_BIND_CURSOR
)
1263 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1265 if (templ
->bind
& PIPE_BIND_LINEAR
)
1266 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1268 /* Textures with a very small height are recommended to be linear. */
1269 if (templ
->target
== PIPE_TEXTURE_1D
|| templ
->target
== PIPE_TEXTURE_1D_ARRAY
||
1270 /* Only very thin and long 2D textures should benefit from
1271 * linear_aligned. */
1272 (templ
->width0
> 8 && templ
->height0
<= 2))
1273 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1275 /* Textures likely to be mapped often. */
1276 if (templ
->usage
== PIPE_USAGE_STAGING
|| templ
->usage
== PIPE_USAGE_STREAM
)
1277 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
1280 /* Make small textures 1D tiled. */
1281 if (templ
->width0
<= 16 || templ
->height0
<= 16 || (sscreen
->debug_flags
& DBG(NO_2D_TILING
)))
1282 return RADEON_SURF_MODE_1D
;
1284 /* The allocator will switch to 1D if needed. */
1285 return RADEON_SURF_MODE_2D
;
1288 struct pipe_resource
*si_texture_create(struct pipe_screen
*screen
,
1289 const struct pipe_resource
*templ
)
1291 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1292 bool is_zs
= util_format_is_depth_or_stencil(templ
->format
);
1294 if (templ
->nr_samples
>= 2) {
1295 /* This is hackish (overwriting the const pipe_resource template),
1296 * but should be harmless and gallium frontends can also see
1297 * the overriden number of samples in the created pipe_resource.
1299 if (is_zs
&& sscreen
->eqaa_force_z_samples
) {
1300 ((struct pipe_resource
*)templ
)->nr_samples
=
1301 ((struct pipe_resource
*)templ
)->nr_storage_samples
= sscreen
->eqaa_force_z_samples
;
1302 } else if (!is_zs
&& sscreen
->eqaa_force_color_samples
) {
1303 ((struct pipe_resource
*)templ
)->nr_samples
= sscreen
->eqaa_force_coverage_samples
;
1304 ((struct pipe_resource
*)templ
)->nr_storage_samples
= sscreen
->eqaa_force_color_samples
;
1308 bool is_flushed_depth
= templ
->flags
& SI_RESOURCE_FLAG_FLUSHED_DEPTH
||
1309 templ
->flags
& SI_RESOURCE_FLAG_FORCE_LINEAR
;
1310 bool tc_compatible_htile
=
1311 sscreen
->info
.chip_class
>= GFX8
&&
1312 /* There are issues with TC-compatible HTILE on Tonga (and
1313 * Iceland is the same design), and documented bug workarounds
1314 * don't help. For example, this fails:
1315 * piglit/bin/tex-miplevel-selection 'texture()' 2DShadow -auto
1317 sscreen
->info
.family
!= CHIP_TONGA
&& sscreen
->info
.family
!= CHIP_ICELAND
&&
1318 (templ
->flags
& PIPE_RESOURCE_FLAG_TEXTURING_MORE_LIKELY
) &&
1319 !(sscreen
->debug_flags
& DBG(NO_HYPERZ
)) && !is_flushed_depth
&&
1320 templ
->nr_samples
<= 1 && /* TC-compat HTILE is less efficient with MSAA */
1322 enum radeon_surf_mode tile_mode
= si_choose_tiling(sscreen
, templ
, tc_compatible_htile
);
1324 /* This allocates textures with multiple planes like NV12 in 1 buffer. */
1327 SI_TEXTURE_MAX_PLANES
= 3
1329 struct radeon_surf surface
[SI_TEXTURE_MAX_PLANES
] = {};
1330 struct pipe_resource plane_templ
[SI_TEXTURE_MAX_PLANES
];
1331 uint64_t plane_offset
[SI_TEXTURE_MAX_PLANES
] = {};
1332 uint64_t total_size
= 0;
1333 unsigned max_alignment
= 0;
1334 unsigned num_planes
= util_format_get_num_planes(templ
->format
);
1335 assert(num_planes
<= SI_TEXTURE_MAX_PLANES
);
1337 /* Compute texture or plane layouts and offsets. */
1338 for (unsigned i
= 0; i
< num_planes
; i
++) {
1339 plane_templ
[i
] = *templ
;
1340 plane_templ
[i
].format
= util_format_get_plane_format(templ
->format
, i
);
1341 plane_templ
[i
].width0
= util_format_get_plane_width(templ
->format
, i
, templ
->width0
);
1342 plane_templ
[i
].height0
= util_format_get_plane_height(templ
->format
, i
, templ
->height0
);
1344 /* Multi-plane allocations need PIPE_BIND_SHARED, because we can't
1345 * reallocate the storage to add PIPE_BIND_SHARED, because it's
1346 * shared by 3 pipe_resources.
1349 plane_templ
[i
].bind
|= PIPE_BIND_SHARED
;
1351 if (si_init_surface(sscreen
, &surface
[i
], &plane_templ
[i
], tile_mode
, false,
1352 plane_templ
[i
].bind
& PIPE_BIND_SCANOUT
, is_flushed_depth
,
1353 tc_compatible_htile
))
1356 plane_offset
[i
] = align64(total_size
, surface
[i
].surf_alignment
);
1357 total_size
= plane_offset
[i
] + surface
[i
].total_size
;
1358 max_alignment
= MAX2(max_alignment
, surface
[i
].surf_alignment
);
1361 struct si_texture
*plane0
= NULL
, *last_plane
= NULL
;
1363 for (unsigned i
= 0; i
< num_planes
; i
++) {
1364 struct si_texture
*tex
=
1365 si_texture_create_object(screen
, &plane_templ
[i
], &surface
[i
], plane0
, NULL
,
1366 plane_offset
[i
], 0, total_size
, max_alignment
);
1368 si_texture_reference(&plane0
, NULL
);
1372 tex
->plane_index
= i
;
1373 tex
->num_planes
= num_planes
;
1376 plane0
= last_plane
= tex
;
1378 last_plane
->buffer
.b
.b
.next
= &tex
->buffer
.b
.b
;
1383 return (struct pipe_resource
*)plane0
;
1386 static struct pipe_resource
*si_texture_from_winsys_buffer(struct si_screen
*sscreen
,
1387 const struct pipe_resource
*templ
,
1388 struct pb_buffer
*buf
, unsigned stride
,
1389 uint64_t offset
, unsigned usage
,
1392 struct radeon_surf surface
= {};
1393 struct radeon_bo_metadata metadata
= {};
1394 struct si_texture
*tex
;
1397 /* Ignore metadata for non-zero planes. */
1402 sscreen
->ws
->buffer_get_metadata(buf
, &metadata
, &surface
);
1405 * The bo metadata is unset for un-dedicated images. So we fall
1406 * back to linear. See answer to question 5 of the
1407 * VK_KHX_external_memory spec for some details.
1409 * It is possible that this case isn't going to work if the
1410 * surface pitch isn't correctly aligned by default.
1412 * In order to support it correctly we require multi-image
1413 * metadata to be syncrhonized between radv and radeonsi. The
1414 * semantics of associating multiple image metadata to a memory
1415 * object on the vulkan export side are not concretely defined
1418 * All the use cases we are aware of at the moment for memory
1419 * objects use dedicated allocations. So lets keep the initial
1420 * implementation simple.
1422 * A possible alternative is to attempt to reconstruct the
1423 * tiling information when the TexParameter TEXTURE_TILING_EXT
1426 metadata
.mode
= RADEON_SURF_MODE_LINEAR_ALIGNED
;
1429 r
= si_init_surface(sscreen
, &surface
, templ
, metadata
.mode
, true,
1430 surface
.flags
& RADEON_SURF_SCANOUT
, false, false);
1434 tex
= si_texture_create_object(&sscreen
->b
, templ
, &surface
, NULL
, buf
,
1435 offset
, stride
, 0, 0);
1439 tex
->buffer
.b
.is_shared
= true;
1440 tex
->buffer
.external_usage
= usage
;
1441 tex
->num_planes
= 1;
1443 /* Account for multiple planes with lowered yuv import. */
1444 struct pipe_resource
*next_plane
= tex
->buffer
.b
.b
.next
;
1446 struct si_texture
*next_tex
= (struct si_texture
*)next_plane
;
1447 ++next_tex
->num_planes
;
1449 next_plane
= next_plane
->next
;
1452 if (!ac_surface_set_umd_metadata(&sscreen
->info
, &tex
->surface
,
1453 tex
->buffer
.b
.b
.nr_storage_samples
,
1454 tex
->buffer
.b
.b
.last_level
+ 1,
1455 metadata
.size_metadata
,
1456 metadata
.metadata
)) {
1457 si_texture_reference(&tex
, NULL
);
1461 /* Displayable DCC requires an explicit flush. */
1462 if (dedicated
&& offset
== 0 && !(usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) &&
1463 si_has_displayable_dcc(tex
)) {
1464 /* TODO: do we need to decompress DCC? */
1465 if (si_texture_discard_dcc(sscreen
, tex
)) {
1466 /* Update BO metadata after disabling DCC. */
1467 si_set_tex_bo_metadata(sscreen
, tex
);
1471 assert(tex
->surface
.tile_swizzle
== 0);
1472 return &tex
->buffer
.b
.b
;
1475 static struct pipe_resource
*si_texture_from_handle(struct pipe_screen
*screen
,
1476 const struct pipe_resource
*templ
,
1477 struct winsys_handle
*whandle
, unsigned usage
)
1479 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
1480 struct pb_buffer
*buf
= NULL
;
1482 /* Support only 2D textures without mipmaps */
1483 if ((templ
->target
!= PIPE_TEXTURE_2D
&& templ
->target
!= PIPE_TEXTURE_RECT
&&
1484 templ
->target
!= PIPE_TEXTURE_2D_ARRAY
) ||
1485 templ
->last_level
!= 0)
1488 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, sscreen
->info
.max_alignment
);
1492 return si_texture_from_winsys_buffer(sscreen
, templ
, buf
, whandle
->stride
, whandle
->offset
,
1496 bool si_init_flushed_depth_texture(struct pipe_context
*ctx
, struct pipe_resource
*texture
)
1498 struct si_texture
*tex
= (struct si_texture
*)texture
;
1499 struct pipe_resource resource
;
1500 enum pipe_format pipe_format
= texture
->format
;
1502 assert(!tex
->flushed_depth_texture
);
1504 if (!tex
->can_sample_z
&& tex
->can_sample_s
) {
1505 switch (pipe_format
) {
1506 case PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
:
1507 /* Save memory by not allocating the S plane. */
1508 pipe_format
= PIPE_FORMAT_Z32_FLOAT
;
1510 case PIPE_FORMAT_Z24_UNORM_S8_UINT
:
1511 case PIPE_FORMAT_S8_UINT_Z24_UNORM
:
1512 /* Save memory bandwidth by not copying the
1513 * stencil part during flush.
1515 * This potentially increases memory bandwidth
1516 * if an application uses both Z and S texturing
1517 * simultaneously (a flushed Z24S8 texture
1518 * would be stored compactly), but how often
1519 * does that really happen?
1521 pipe_format
= PIPE_FORMAT_Z24X8_UNORM
;
1525 } else if (!tex
->can_sample_s
&& tex
->can_sample_z
) {
1526 assert(util_format_has_stencil(util_format_description(pipe_format
)));
1528 /* DB->CB copies to an 8bpp surface don't work. */
1529 pipe_format
= PIPE_FORMAT_X24S8_UINT
;
1532 memset(&resource
, 0, sizeof(resource
));
1533 resource
.target
= texture
->target
;
1534 resource
.format
= pipe_format
;
1535 resource
.width0
= texture
->width0
;
1536 resource
.height0
= texture
->height0
;
1537 resource
.depth0
= texture
->depth0
;
1538 resource
.array_size
= texture
->array_size
;
1539 resource
.last_level
= texture
->last_level
;
1540 resource
.nr_samples
= texture
->nr_samples
;
1541 resource
.usage
= PIPE_USAGE_DEFAULT
;
1542 resource
.bind
= texture
->bind
& ~PIPE_BIND_DEPTH_STENCIL
;
1543 resource
.flags
= texture
->flags
| SI_RESOURCE_FLAG_FLUSHED_DEPTH
;
1545 tex
->flushed_depth_texture
=
1546 (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1547 if (!tex
->flushed_depth_texture
) {
1548 PRINT_ERR("failed to create temporary texture to hold flushed depth\n");
1555 * Initialize the pipe_resource descriptor to be of the same size as the box,
1556 * which is supposed to hold a subregion of the texture "orig" at the given
1559 static void si_init_temp_resource_from_box(struct pipe_resource
*res
, struct pipe_resource
*orig
,
1560 const struct pipe_box
*box
, unsigned level
,
1561 unsigned usage
, unsigned flags
)
1563 memset(res
, 0, sizeof(*res
));
1564 res
->format
= orig
->format
;
1565 res
->width0
= box
->width
;
1566 res
->height0
= box
->height
;
1568 res
->array_size
= 1;
1572 if (flags
& SI_RESOURCE_FLAG_FORCE_LINEAR
&& util_format_is_compressed(orig
->format
)) {
1573 /* Transfer resources are allocated with linear tiling, which is
1574 * not supported for compressed formats.
1576 unsigned blocksize
= util_format_get_blocksize(orig
->format
);
1578 if (blocksize
== 8) {
1579 res
->format
= PIPE_FORMAT_R16G16B16A16_UINT
;
1581 assert(blocksize
== 16);
1582 res
->format
= PIPE_FORMAT_R32G32B32A32_UINT
;
1585 res
->width0
= util_format_get_nblocksx(orig
->format
, box
->width
);
1586 res
->height0
= util_format_get_nblocksy(orig
->format
, box
->height
);
1589 /* We must set the correct texture target and dimensions for a 3D box. */
1590 if (box
->depth
> 1 && util_max_layer(orig
, level
) > 0) {
1591 res
->target
= PIPE_TEXTURE_2D_ARRAY
;
1592 res
->array_size
= box
->depth
;
1594 res
->target
= PIPE_TEXTURE_2D
;
1598 static bool si_can_invalidate_texture(struct si_screen
*sscreen
, struct si_texture
*tex
,
1599 unsigned transfer_usage
, const struct pipe_box
*box
)
1601 return !tex
->buffer
.b
.is_shared
&& !(tex
->surface
.flags
& RADEON_SURF_IMPORTED
) &&
1602 !(transfer_usage
& PIPE_TRANSFER_READ
) && tex
->buffer
.b
.b
.last_level
== 0 &&
1603 util_texrange_covers_whole_level(&tex
->buffer
.b
.b
, 0, box
->x
, box
->y
, box
->z
, box
->width
,
1604 box
->height
, box
->depth
);
1607 static void si_texture_invalidate_storage(struct si_context
*sctx
, struct si_texture
*tex
)
1609 struct si_screen
*sscreen
= sctx
->screen
;
1611 /* There is no point in discarding depth and tiled buffers. */
1612 assert(!tex
->is_depth
);
1613 assert(tex
->surface
.is_linear
);
1615 /* Reallocate the buffer in the same pipe_resource. */
1616 si_alloc_resource(sscreen
, &tex
->buffer
);
1618 /* Initialize the CMASK base address (needed even without CMASK). */
1619 tex
->cmask_base_address_reg
= (tex
->buffer
.gpu_address
+ tex
->surface
.cmask_offset
) >> 8;
1621 p_atomic_inc(&sscreen
->dirty_tex_counter
);
1623 sctx
->num_alloc_tex_transfer_bytes
+= tex
->surface
.total_size
;
1626 static void *si_texture_transfer_map(struct pipe_context
*ctx
, struct pipe_resource
*texture
,
1627 unsigned level
, unsigned usage
, const struct pipe_box
*box
,
1628 struct pipe_transfer
**ptransfer
)
1630 struct si_context
*sctx
= (struct si_context
*)ctx
;
1631 struct si_texture
*tex
= (struct si_texture
*)texture
;
1632 struct si_transfer
*trans
;
1633 struct si_resource
*buf
;
1634 unsigned offset
= 0;
1636 bool use_staging_texture
= false;
1638 assert(!(texture
->flags
& SI_RESOURCE_FLAG_FORCE_LINEAR
));
1639 assert(box
->width
&& box
->height
&& box
->depth
);
1641 /* If we are uploading into FP16 or R11G11B10_FLOAT via a blit, CB clobbers NaNs,
1642 * so in order to preserve them exactly, we have to use the compute blit.
1643 * The compute blit is used only when the destination doesn't have DCC, so
1644 * disable it here, which is kinda a hack.
1646 * This makes KHR-GL45.texture_view.view_classes pass on gfx9.
1647 * gfx10 has the same issue, but the test doesn't use a large enough texture
1648 * to enable DCC and fail, so it always passes.
1650 const struct util_format_description
*desc
= util_format_description(texture
->format
);
1651 if (vi_dcc_enabled(tex
, level
) &&
1652 desc
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
&&
1653 desc
->channel
[0].size
< 32)
1654 si_texture_disable_dcc(sctx
, tex
);
1656 if (tex
->is_depth
) {
1657 /* Depth textures use staging unconditionally. */
1658 use_staging_texture
= true;
1660 /* Degrade the tile mode if we get too many transfers on APUs.
1661 * On dGPUs, the staging texture is always faster.
1662 * Only count uploads that are at least 4x4 pixels large.
1664 if (!sctx
->screen
->info
.has_dedicated_vram
&& level
== 0 && box
->width
>= 4 &&
1665 box
->height
>= 4 && p_atomic_inc_return(&tex
->num_level0_transfers
) == 10) {
1666 bool can_invalidate
= si_can_invalidate_texture(sctx
->screen
, tex
, usage
, box
);
1668 si_reallocate_texture_inplace(sctx
, tex
, PIPE_BIND_LINEAR
, can_invalidate
);
1671 /* Tiled textures need to be converted into a linear texture for CPU
1672 * access. The staging texture is always linear and is placed in GART.
1674 * Reading from VRAM or GTT WC is slow, always use the staging
1675 * texture in this case.
1677 * Use the staging texture for uploads if the underlying BO
1680 if (!tex
->surface
.is_linear
|| (tex
->buffer
.flags
& RADEON_FLAG_ENCRYPTED
))
1681 use_staging_texture
= true;
1682 else if (usage
& PIPE_TRANSFER_READ
)
1683 use_staging_texture
=
1684 tex
->buffer
.domains
& RADEON_DOMAIN_VRAM
|| tex
->buffer
.flags
& RADEON_FLAG_GTT_WC
;
1685 /* Write & linear only: */
1686 else if (si_rings_is_buffer_referenced(sctx
, tex
->buffer
.buf
, RADEON_USAGE_READWRITE
) ||
1687 !sctx
->ws
->buffer_wait(tex
->buffer
.buf
, 0, RADEON_USAGE_READWRITE
)) {
1689 if (si_can_invalidate_texture(sctx
->screen
, tex
, usage
, box
))
1690 si_texture_invalidate_storage(sctx
, tex
);
1692 use_staging_texture
= true;
1696 trans
= CALLOC_STRUCT(si_transfer
);
1699 pipe_resource_reference(&trans
->b
.b
.resource
, texture
);
1700 trans
->b
.b
.level
= level
;
1701 trans
->b
.b
.usage
= usage
;
1702 trans
->b
.b
.box
= *box
;
1704 if (use_staging_texture
) {
1705 struct pipe_resource resource
;
1706 struct si_texture
*staging
;
1707 unsigned bo_usage
= usage
& PIPE_TRANSFER_READ
? PIPE_USAGE_STAGING
: PIPE_USAGE_STREAM
;
1708 unsigned bo_flags
= SI_RESOURCE_FLAG_FORCE_LINEAR
;
1710 /* The pixel shader has a bad access pattern for linear textures.
1711 * If a pixel shader is used to blit to/from staging, don't disable caches.
1713 * MSAA, depth/stencil textures, and compressed textures use the pixel shader
1716 if (texture
->nr_samples
<= 1 &&
1718 !util_format_is_compressed(texture
->format
) &&
1719 /* Texture uploads with DCC use the pixel shader to blit */
1720 (!(usage
& PIPE_TRANSFER_WRITE
) || !vi_dcc_enabled(tex
, level
)))
1721 bo_flags
|= SI_RESOURCE_FLAG_UNCACHED
;
1723 si_init_temp_resource_from_box(&resource
, texture
, box
, level
, bo_usage
,
1726 /* Since depth-stencil textures don't support linear tiling,
1727 * blit from ZS to color and vice versa. u_blitter will do
1728 * the packing for these formats.
1731 resource
.format
= util_blitter_get_color_format_for_zs(resource
.format
);
1733 /* Create the temporary texture. */
1734 staging
= (struct si_texture
*)ctx
->screen
->resource_create(ctx
->screen
, &resource
);
1736 PRINT_ERR("failed to create temporary texture to hold untiled copy\n");
1739 trans
->staging
= &staging
->buffer
;
1741 /* Just get the strides. */
1742 si_texture_get_offset(sctx
->screen
, staging
, 0, NULL
, &trans
->b
.b
.stride
,
1743 &trans
->b
.b
.layer_stride
);
1745 if (usage
& PIPE_TRANSFER_READ
)
1746 si_copy_to_staging_texture(ctx
, trans
);
1748 usage
|= PIPE_TRANSFER_UNSYNCHRONIZED
;
1750 buf
= trans
->staging
;
1752 /* the resource is mapped directly */
1753 offset
= si_texture_get_offset(sctx
->screen
, tex
, level
, box
, &trans
->b
.b
.stride
,
1754 &trans
->b
.b
.layer_stride
);
1758 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1759 * we don't run out of the CPU address space.
1761 if (sizeof(void *) == 4)
1762 usage
|= RADEON_TRANSFER_TEMPORARY
;
1764 if (!(map
= si_buffer_map_sync_with_rings(sctx
, buf
, usage
)))
1767 *ptransfer
= &trans
->b
.b
;
1768 return map
+ offset
;
1771 si_resource_reference(&trans
->staging
, NULL
);
1772 pipe_resource_reference(&trans
->b
.b
.resource
, NULL
);
1777 static void si_texture_transfer_unmap(struct pipe_context
*ctx
, struct pipe_transfer
*transfer
)
1779 struct si_context
*sctx
= (struct si_context
*)ctx
;
1780 struct si_transfer
*stransfer
= (struct si_transfer
*)transfer
;
1781 struct pipe_resource
*texture
= transfer
->resource
;
1782 struct si_texture
*tex
= (struct si_texture
*)texture
;
1784 /* Always unmap texture CPU mappings on 32-bit architectures, so that
1785 * we don't run out of the CPU address space.
1787 if (sizeof(void *) == 4) {
1788 struct si_resource
*buf
= stransfer
->staging
? stransfer
->staging
: &tex
->buffer
;
1790 sctx
->ws
->buffer_unmap(buf
->buf
);
1793 if ((transfer
->usage
& PIPE_TRANSFER_WRITE
) && stransfer
->staging
)
1794 si_copy_from_staging_texture(ctx
, stransfer
);
1796 if (stransfer
->staging
) {
1797 sctx
->num_alloc_tex_transfer_bytes
+= stransfer
->staging
->buf
->size
;
1798 si_resource_reference(&stransfer
->staging
, NULL
);
1801 /* Heuristic for {upload, draw, upload, draw, ..}:
1803 * Flush the gfx IB if we've allocated too much texture storage.
1805 * The idea is that we don't want to build IBs that use too much
1806 * memory and put pressure on the kernel memory manager and we also
1807 * want to make temporary and invalidated buffers go idle ASAP to
1808 * decrease the total memory usage or make them reusable. The memory
1809 * usage will be slightly higher than given here because of the buffer
1810 * cache in the winsys.
1812 * The result is that the kernel memory manager is never a bottleneck.
1814 if (sctx
->num_alloc_tex_transfer_bytes
> sctx
->screen
->info
.gart_size
/ 4) {
1815 si_flush_gfx_cs(sctx
, RADEON_FLUSH_ASYNC_START_NEXT_GFX_IB_NOW
, NULL
);
1816 sctx
->num_alloc_tex_transfer_bytes
= 0;
1819 pipe_resource_reference(&transfer
->resource
, NULL
);
1823 static const struct u_resource_vtbl si_texture_vtbl
= {
1824 NULL
, /* get_handle */
1825 si_texture_destroy
, /* resource_destroy */
1826 si_texture_transfer_map
, /* transfer_map */
1827 u_default_transfer_flush_region
, /* transfer_flush_region */
1828 si_texture_transfer_unmap
, /* transfer_unmap */
1831 /* Return if it's allowed to reinterpret one format as another with DCC enabled.
1833 bool vi_dcc_formats_compatible(struct si_screen
*sscreen
, enum pipe_format format1
,
1834 enum pipe_format format2
)
1836 const struct util_format_description
*desc1
, *desc2
;
1838 /* No format change - exit early. */
1839 if (format1
== format2
)
1842 format1
= si_simplify_cb_format(format1
);
1843 format2
= si_simplify_cb_format(format2
);
1845 /* Check again after format adjustments. */
1846 if (format1
== format2
)
1849 desc1
= util_format_description(format1
);
1850 desc2
= util_format_description(format2
);
1852 if (desc1
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
|| desc2
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1855 /* Float and non-float are totally incompatible. */
1856 if ((desc1
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
) !=
1857 (desc2
->channel
[0].type
== UTIL_FORMAT_TYPE_FLOAT
))
1860 /* Channel sizes must match across DCC formats.
1861 * Comparing just the first 2 channels should be enough.
1863 if (desc1
->channel
[0].size
!= desc2
->channel
[0].size
||
1864 (desc1
->nr_channels
>= 2 && desc1
->channel
[1].size
!= desc2
->channel
[1].size
))
1867 /* Everything below is not needed if the driver never uses the DCC
1868 * clear code with the value of 1.
1871 /* If the clear values are all 1 or all 0, this constraint can be
1873 if (vi_alpha_is_on_msb(sscreen
, format1
) != vi_alpha_is_on_msb(sscreen
, format2
))
1876 /* Channel types must match if the clear value of 1 is used.
1877 * The type categories are only float, signed, unsigned.
1878 * NORM and INT are always compatible.
1880 if (desc1
->channel
[0].type
!= desc2
->channel
[0].type
||
1881 (desc1
->nr_channels
>= 2 && desc1
->channel
[1].type
!= desc2
->channel
[1].type
))
1887 bool vi_dcc_formats_are_incompatible(struct pipe_resource
*tex
, unsigned level
,
1888 enum pipe_format view_format
)
1890 struct si_texture
*stex
= (struct si_texture
*)tex
;
1892 return vi_dcc_enabled(stex
, level
) &&
1893 !vi_dcc_formats_compatible((struct si_screen
*)tex
->screen
, tex
->format
, view_format
);
1896 /* This can't be merged with the above function, because
1897 * vi_dcc_formats_compatible should be called only when DCC is enabled. */
1898 void vi_disable_dcc_if_incompatible_format(struct si_context
*sctx
, struct pipe_resource
*tex
,
1899 unsigned level
, enum pipe_format view_format
)
1901 struct si_texture
*stex
= (struct si_texture
*)tex
;
1903 if (vi_dcc_formats_are_incompatible(tex
, level
, view_format
))
1904 if (!si_texture_disable_dcc(sctx
, stex
))
1905 si_decompress_dcc(sctx
, stex
);
1908 struct pipe_surface
*si_create_surface_custom(struct pipe_context
*pipe
,
1909 struct pipe_resource
*texture
,
1910 const struct pipe_surface
*templ
, unsigned width0
,
1911 unsigned height0
, unsigned width
, unsigned height
)
1913 struct si_surface
*surface
= CALLOC_STRUCT(si_surface
);
1918 assert(templ
->u
.tex
.first_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1919 assert(templ
->u
.tex
.last_layer
<= util_max_layer(texture
, templ
->u
.tex
.level
));
1921 pipe_reference_init(&surface
->base
.reference
, 1);
1922 pipe_resource_reference(&surface
->base
.texture
, texture
);
1923 surface
->base
.context
= pipe
;
1924 surface
->base
.format
= templ
->format
;
1925 surface
->base
.width
= width
;
1926 surface
->base
.height
= height
;
1927 surface
->base
.u
= templ
->u
;
1929 surface
->width0
= width0
;
1930 surface
->height0
= height0
;
1932 surface
->dcc_incompatible
=
1933 texture
->target
!= PIPE_BUFFER
&&
1934 vi_dcc_formats_are_incompatible(texture
, templ
->u
.tex
.level
, templ
->format
);
1935 return &surface
->base
;
1938 static struct pipe_surface
*si_create_surface(struct pipe_context
*pipe
, struct pipe_resource
*tex
,
1939 const struct pipe_surface
*templ
)
1941 unsigned level
= templ
->u
.tex
.level
;
1942 unsigned width
= u_minify(tex
->width0
, level
);
1943 unsigned height
= u_minify(tex
->height0
, level
);
1944 unsigned width0
= tex
->width0
;
1945 unsigned height0
= tex
->height0
;
1947 if (tex
->target
!= PIPE_BUFFER
&& templ
->format
!= tex
->format
) {
1948 const struct util_format_description
*tex_desc
= util_format_description(tex
->format
);
1949 const struct util_format_description
*templ_desc
= util_format_description(templ
->format
);
1951 assert(tex_desc
->block
.bits
== templ_desc
->block
.bits
);
1953 /* Adjust size of surface if and only if the block width or
1954 * height is changed. */
1955 if (tex_desc
->block
.width
!= templ_desc
->block
.width
||
1956 tex_desc
->block
.height
!= templ_desc
->block
.height
) {
1957 unsigned nblks_x
= util_format_get_nblocksx(tex
->format
, width
);
1958 unsigned nblks_y
= util_format_get_nblocksy(tex
->format
, height
);
1960 width
= nblks_x
* templ_desc
->block
.width
;
1961 height
= nblks_y
* templ_desc
->block
.height
;
1963 width0
= util_format_get_nblocksx(tex
->format
, width0
);
1964 height0
= util_format_get_nblocksy(tex
->format
, height0
);
1968 return si_create_surface_custom(pipe
, tex
, templ
, width0
, height0
, width
, height
);
1971 static void si_surface_destroy(struct pipe_context
*pipe
, struct pipe_surface
*surface
)
1973 pipe_resource_reference(&surface
->texture
, NULL
);
1977 unsigned si_translate_colorswap(enum pipe_format format
, bool do_endian_swap
)
1979 const struct util_format_description
*desc
= util_format_description(format
);
1981 #define HAS_SWIZZLE(chan, swz) (desc->swizzle[chan] == PIPE_SWIZZLE_##swz)
1983 if (format
== PIPE_FORMAT_R11G11B10_FLOAT
) /* isn't plain */
1984 return V_028C70_SWAP_STD
;
1986 if (desc
->layout
!= UTIL_FORMAT_LAYOUT_PLAIN
)
1989 switch (desc
->nr_channels
) {
1991 if (HAS_SWIZZLE(0, X
))
1992 return V_028C70_SWAP_STD
; /* X___ */
1993 else if (HAS_SWIZZLE(3, X
))
1994 return V_028C70_SWAP_ALT_REV
; /* ___X */
1997 if ((HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(1, Y
)) || (HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(1, NONE
)) ||
1998 (HAS_SWIZZLE(0, NONE
) && HAS_SWIZZLE(1, Y
)))
1999 return V_028C70_SWAP_STD
; /* XY__ */
2000 else if ((HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(1, X
)) ||
2001 (HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(1, NONE
)) ||
2002 (HAS_SWIZZLE(0, NONE
) && HAS_SWIZZLE(1, X
)))
2004 return (do_endian_swap
? V_028C70_SWAP_STD
: V_028C70_SWAP_STD_REV
);
2005 else if (HAS_SWIZZLE(0, X
) && HAS_SWIZZLE(3, Y
))
2006 return V_028C70_SWAP_ALT
; /* X__Y */
2007 else if (HAS_SWIZZLE(0, Y
) && HAS_SWIZZLE(3, X
))
2008 return V_028C70_SWAP_ALT_REV
; /* Y__X */
2011 if (HAS_SWIZZLE(0, X
))
2012 return (do_endian_swap
? V_028C70_SWAP_STD_REV
: V_028C70_SWAP_STD
);
2013 else if (HAS_SWIZZLE(0, Z
))
2014 return V_028C70_SWAP_STD_REV
; /* ZYX */
2017 /* check the middle channels, the 1st and 4th channel can be NONE */
2018 if (HAS_SWIZZLE(1, Y
) && HAS_SWIZZLE(2, Z
)) {
2019 return V_028C70_SWAP_STD
; /* XYZW */
2020 } else if (HAS_SWIZZLE(1, Z
) && HAS_SWIZZLE(2, Y
)) {
2021 return V_028C70_SWAP_STD_REV
; /* WZYX */
2022 } else if (HAS_SWIZZLE(1, Y
) && HAS_SWIZZLE(2, X
)) {
2023 return V_028C70_SWAP_ALT
; /* ZYXW */
2024 } else if (HAS_SWIZZLE(1, Z
) && HAS_SWIZZLE(2, W
)) {
2027 return V_028C70_SWAP_ALT_REV
;
2029 return (do_endian_swap
? V_028C70_SWAP_ALT
: V_028C70_SWAP_ALT_REV
);
2036 /* PIPELINE_STAT-BASED DCC ENABLEMENT FOR DISPLAYABLE SURFACES */
2038 static void vi_dcc_clean_up_context_slot(struct si_context
*sctx
, int slot
)
2042 if (sctx
->dcc_stats
[slot
].query_active
)
2043 vi_separate_dcc_stop_query(sctx
, sctx
->dcc_stats
[slot
].tex
);
2045 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
[slot
].ps_stats
); i
++)
2046 if (sctx
->dcc_stats
[slot
].ps_stats
[i
]) {
2047 sctx
->b
.destroy_query(&sctx
->b
, sctx
->dcc_stats
[slot
].ps_stats
[i
]);
2048 sctx
->dcc_stats
[slot
].ps_stats
[i
] = NULL
;
2051 si_texture_reference(&sctx
->dcc_stats
[slot
].tex
, NULL
);
2055 * Return the per-context slot where DCC statistics queries for the texture live.
2057 static unsigned vi_get_context_dcc_stats_index(struct si_context
*sctx
, struct si_texture
*tex
)
2059 int i
, empty_slot
= -1;
2061 /* Remove zombie textures (textures kept alive by this array only). */
2062 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2063 if (sctx
->dcc_stats
[i
].tex
&& sctx
->dcc_stats
[i
].tex
->buffer
.b
.b
.reference
.count
== 1)
2064 vi_dcc_clean_up_context_slot(sctx
, i
);
2066 /* Find the texture. */
2067 for (i
= 0; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++) {
2068 /* Return if found. */
2069 if (sctx
->dcc_stats
[i
].tex
== tex
) {
2070 sctx
->dcc_stats
[i
].last_use_timestamp
= os_time_get();
2074 /* Record the first seen empty slot. */
2075 if (empty_slot
== -1 && !sctx
->dcc_stats
[i
].tex
)
2079 /* Not found. Remove the oldest member to make space in the array. */
2080 if (empty_slot
== -1) {
2081 int oldest_slot
= 0;
2083 /* Find the oldest slot. */
2084 for (i
= 1; i
< ARRAY_SIZE(sctx
->dcc_stats
); i
++)
2085 if (sctx
->dcc_stats
[oldest_slot
].last_use_timestamp
>
2086 sctx
->dcc_stats
[i
].last_use_timestamp
)
2089 /* Clean up the oldest slot. */
2090 vi_dcc_clean_up_context_slot(sctx
, oldest_slot
);
2091 empty_slot
= oldest_slot
;
2094 /* Add the texture to the new slot. */
2095 si_texture_reference(&sctx
->dcc_stats
[empty_slot
].tex
, tex
);
2096 sctx
->dcc_stats
[empty_slot
].last_use_timestamp
= os_time_get();
2100 static struct pipe_query
*vi_create_resuming_pipestats_query(struct si_context
*sctx
)
2102 struct si_query_hw
*query
=
2103 (struct si_query_hw
*)sctx
->b
.create_query(&sctx
->b
, PIPE_QUERY_PIPELINE_STATISTICS
, 0);
2105 query
->flags
|= SI_QUERY_HW_FLAG_BEGIN_RESUMES
;
2106 return (struct pipe_query
*)query
;
2110 * Called when binding a color buffer.
2112 void vi_separate_dcc_start_query(struct si_context
*sctx
, struct si_texture
*tex
)
2114 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2116 assert(!sctx
->dcc_stats
[i
].query_active
);
2118 if (!sctx
->dcc_stats
[i
].ps_stats
[0])
2119 sctx
->dcc_stats
[i
].ps_stats
[0] = vi_create_resuming_pipestats_query(sctx
);
2121 /* begin or resume the query */
2122 sctx
->b
.begin_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2123 sctx
->dcc_stats
[i
].query_active
= true;
2127 * Called when unbinding a color buffer.
2129 void vi_separate_dcc_stop_query(struct si_context
*sctx
, struct si_texture
*tex
)
2131 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2133 assert(sctx
->dcc_stats
[i
].query_active
);
2134 assert(sctx
->dcc_stats
[i
].ps_stats
[0]);
2136 /* pause or end the query */
2137 sctx
->b
.end_query(&sctx
->b
, sctx
->dcc_stats
[i
].ps_stats
[0]);
2138 sctx
->dcc_stats
[i
].query_active
= false;
2141 static bool vi_should_enable_separate_dcc(struct si_texture
*tex
)
2143 /* The minimum number of fullscreen draws per frame that is required
2145 return tex
->ps_draw_ratio
+ tex
->num_slow_clears
>= 5;
2148 /* Called by fast clear. */
2149 void vi_separate_dcc_try_enable(struct si_context
*sctx
, struct si_texture
*tex
)
2151 /* The intent is to use this with shared displayable back buffers,
2152 * but it's not strictly limited only to them.
2154 if (!tex
->buffer
.b
.is_shared
||
2155 !(tex
->buffer
.external_usage
& PIPE_HANDLE_USAGE_EXPLICIT_FLUSH
) ||
2156 tex
->buffer
.b
.b
.target
!= PIPE_TEXTURE_2D
|| tex
->buffer
.b
.b
.last_level
> 0 ||
2157 !tex
->surface
.dcc_size
|| sctx
->screen
->debug_flags
& DBG(NO_DCC
) ||
2158 sctx
->screen
->debug_flags
& DBG(NO_DCC_FB
))
2161 assert(sctx
->chip_class
>= GFX8
);
2163 if (tex
->surface
.dcc_offset
)
2164 return; /* already enabled */
2166 /* Enable the DCC stat gathering. */
2167 if (!tex
->dcc_gather_statistics
) {
2168 tex
->dcc_gather_statistics
= true;
2169 vi_separate_dcc_start_query(sctx
, tex
);
2172 if (!vi_should_enable_separate_dcc(tex
))
2173 return; /* stats show that DCC decompression is too expensive */
2175 assert(tex
->surface
.num_dcc_levels
);
2176 assert(!tex
->dcc_separate_buffer
);
2178 si_texture_discard_cmask(sctx
->screen
, tex
);
2180 /* Get a DCC buffer. */
2181 if (tex
->last_dcc_separate_buffer
) {
2182 assert(tex
->dcc_gather_statistics
);
2183 assert(!tex
->dcc_separate_buffer
);
2184 tex
->dcc_separate_buffer
= tex
->last_dcc_separate_buffer
;
2185 tex
->last_dcc_separate_buffer
= NULL
;
2187 tex
->dcc_separate_buffer
=
2188 si_aligned_buffer_create(sctx
->b
.screen
, SI_RESOURCE_FLAG_UNMAPPABLE
, PIPE_USAGE_DEFAULT
,
2189 tex
->surface
.dcc_size
, tex
->surface
.dcc_alignment
);
2190 if (!tex
->dcc_separate_buffer
)
2194 /* dcc_offset is the absolute GPUVM address. */
2195 tex
->surface
.dcc_offset
= tex
->dcc_separate_buffer
->gpu_address
;
2197 /* no need to flag anything since this is called by fast clear that
2198 * flags framebuffer state
2203 * Called by pipe_context::flush_resource, the place where DCC decompression
2206 void vi_separate_dcc_process_and_reset_stats(struct pipe_context
*ctx
, struct si_texture
*tex
)
2208 struct si_context
*sctx
= (struct si_context
*)ctx
;
2209 struct pipe_query
*tmp
;
2210 unsigned i
= vi_get_context_dcc_stats_index(sctx
, tex
);
2211 bool query_active
= sctx
->dcc_stats
[i
].query_active
;
2212 bool disable
= false;
2214 if (sctx
->dcc_stats
[i
].ps_stats
[2]) {
2215 union pipe_query_result result
;
2217 /* Read the results. */
2218 struct pipe_query
*query
= sctx
->dcc_stats
[i
].ps_stats
[2];
2219 ctx
->get_query_result(ctx
, query
, true, &result
);
2220 si_query_buffer_reset(sctx
, &((struct si_query_hw
*)query
)->buffer
);
2222 /* Compute the approximate number of fullscreen draws. */
2223 tex
->ps_draw_ratio
= result
.pipeline_statistics
.ps_invocations
/
2224 (tex
->buffer
.b
.b
.width0
* tex
->buffer
.b
.b
.height0
);
2225 sctx
->last_tex_ps_draw_ratio
= tex
->ps_draw_ratio
;
2227 disable
= tex
->dcc_separate_buffer
&& !vi_should_enable_separate_dcc(tex
);
2230 tex
->num_slow_clears
= 0;
2232 /* stop the statistics query for ps_stats[0] */
2234 vi_separate_dcc_stop_query(sctx
, tex
);
2236 /* Move the queries in the queue by one. */
2237 tmp
= sctx
->dcc_stats
[i
].ps_stats
[2];
2238 sctx
->dcc_stats
[i
].ps_stats
[2] = sctx
->dcc_stats
[i
].ps_stats
[1];
2239 sctx
->dcc_stats
[i
].ps_stats
[1] = sctx
->dcc_stats
[i
].ps_stats
[0];
2240 sctx
->dcc_stats
[i
].ps_stats
[0] = tmp
;
2242 /* create and start a new query as ps_stats[0] */
2244 vi_separate_dcc_start_query(sctx
, tex
);
2247 assert(!tex
->last_dcc_separate_buffer
);
2248 tex
->last_dcc_separate_buffer
= tex
->dcc_separate_buffer
;
2249 tex
->dcc_separate_buffer
= NULL
;
2250 tex
->surface
.dcc_offset
= 0;
2251 /* no need to flag anything since this is called after
2252 * decompression that re-sets framebuffer state
2257 static struct pipe_memory_object
*
2258 si_memobj_from_handle(struct pipe_screen
*screen
, struct winsys_handle
*whandle
, bool dedicated
)
2260 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2261 struct si_memory_object
*memobj
= CALLOC_STRUCT(si_memory_object
);
2262 struct pb_buffer
*buf
= NULL
;
2267 buf
= sscreen
->ws
->buffer_from_handle(sscreen
->ws
, whandle
, sscreen
->info
.max_alignment
);
2273 memobj
->b
.dedicated
= dedicated
;
2275 memobj
->stride
= whandle
->stride
;
2277 return (struct pipe_memory_object
*)memobj
;
2280 static void si_memobj_destroy(struct pipe_screen
*screen
, struct pipe_memory_object
*_memobj
)
2282 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2284 pb_reference(&memobj
->buf
, NULL
);
2288 static struct pipe_resource
*si_texture_from_memobj(struct pipe_screen
*screen
,
2289 const struct pipe_resource
*templ
,
2290 struct pipe_memory_object
*_memobj
,
2293 struct si_screen
*sscreen
= (struct si_screen
*)screen
;
2294 struct si_memory_object
*memobj
= (struct si_memory_object
*)_memobj
;
2295 struct pipe_resource
*tex
= si_texture_from_winsys_buffer(
2296 sscreen
, templ
, memobj
->buf
, memobj
->stride
, offset
,
2297 PIPE_HANDLE_USAGE_FRAMEBUFFER_WRITE
| PIPE_HANDLE_USAGE_SHADER_WRITE
, memobj
->b
.dedicated
);
2301 /* si_texture_from_winsys_buffer doesn't increment refcount of
2302 * memobj->buf, so increment it here.
2304 struct pb_buffer
*buf
= NULL
;
2305 pb_reference(&buf
, memobj
->buf
);
2309 static bool si_check_resource_capability(struct pipe_screen
*screen
, struct pipe_resource
*resource
,
2312 struct si_texture
*tex
= (struct si_texture
*)resource
;
2314 /* Buffers only support the linear flag. */
2315 if (resource
->target
== PIPE_BUFFER
)
2316 return (bind
& ~PIPE_BIND_LINEAR
) == 0;
2318 if (bind
& PIPE_BIND_LINEAR
&& !tex
->surface
.is_linear
)
2321 if (bind
& PIPE_BIND_SCANOUT
&& !tex
->surface
.is_displayable
)
2324 /* TODO: PIPE_BIND_CURSOR - do we care? */
2328 void si_init_screen_texture_functions(struct si_screen
*sscreen
)
2330 sscreen
->b
.resource_from_handle
= si_texture_from_handle
;
2331 sscreen
->b
.resource_get_handle
= si_texture_get_handle
;
2332 sscreen
->b
.resource_get_param
= si_resource_get_param
;
2333 sscreen
->b
.resource_get_info
= si_texture_get_info
;
2334 sscreen
->b
.resource_from_memobj
= si_texture_from_memobj
;
2335 sscreen
->b
.memobj_create_from_handle
= si_memobj_from_handle
;
2336 sscreen
->b
.memobj_destroy
= si_memobj_destroy
;
2337 sscreen
->b
.check_resource_capability
= si_check_resource_capability
;
2340 void si_init_context_texture_functions(struct si_context
*sctx
)
2342 sctx
->b
.create_surface
= si_create_surface
;
2343 sctx
->b
.surface_destroy
= si_surface_destroy
;