Merge branch '7.8'
[mesa.git] / src / gallium / drivers / softpipe / sp_tex_tile_cache.h
1 /**************************************************************************
2 *
3 * Copyright 2007 Tungsten Graphics, Inc., Cedar Park, Texas.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL TUNGSTEN GRAPHICS AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef SP_TEX_TILE_CACHE_H
29 #define SP_TEX_TILE_CACHE_H
30
31
32 #include "pipe/p_compiler.h"
33
34
35 struct softpipe_context;
36 struct softpipe_tex_tile_cache;
37
38
39 /**
40 * Cache tile size (width and height). This needs to be a power of two.
41 */
42 #define TILE_SIZE 64
43
44
45 /* If we need to support > 4096, just expand this to be a 64 bit
46 * union, or consider tiling in Z as well.
47 */
48 union tex_tile_address {
49 struct {
50 unsigned x:6; /* 4096 / TILE_SIZE */
51 unsigned y:6; /* 4096 / TILE_SIZE */
52 unsigned z:12; /* 4096 -- z not tiled */
53 unsigned face:3;
54 unsigned level:4;
55 unsigned invalid:1;
56 } bits;
57 unsigned value;
58 };
59
60
61 struct softpipe_tex_cached_tile
62 {
63 union tex_tile_address addr;
64 union {
65 float color[TILE_SIZE][TILE_SIZE][4];
66 } data;
67 };
68
69 #define NUM_ENTRIES 50
70
71 struct softpipe_tex_tile_cache
72 {
73 struct pipe_context *pipe;
74 struct pipe_transfer *transfer;
75 void *transfer_map;
76
77 struct pipe_texture *texture; /**< if caching a texture */
78 unsigned timestamp;
79
80 struct softpipe_tex_cached_tile entries[NUM_ENTRIES];
81
82 struct pipe_transfer *tex_trans;
83 void *tex_trans_map;
84 int tex_face, tex_level, tex_z;
85
86 unsigned swizzle_r;
87 unsigned swizzle_g;
88 unsigned swizzle_b;
89 unsigned swizzle_a;
90 unsigned format;
91
92 struct softpipe_tex_cached_tile *last_tile; /**< most recently retrieved tile */
93 };
94
95
96 extern struct softpipe_tex_tile_cache *
97 sp_create_tex_tile_cache( struct pipe_context *pipe );
98
99 extern void
100 sp_destroy_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
101
102
103 extern void
104 sp_tex_tile_cache_map_transfers(struct softpipe_tex_tile_cache *tc);
105
106 extern void
107 sp_tex_tile_cache_unmap_transfers(struct softpipe_tex_tile_cache *tc);
108
109 extern void
110 sp_tex_tile_cache_set_sampler_view(struct softpipe_tex_tile_cache *tc,
111 struct pipe_sampler_view *view);
112
113 void
114 sp_tex_tile_cache_validate_texture(struct softpipe_tex_tile_cache *tc);
115
116 extern void
117 sp_flush_tex_tile_cache(struct softpipe_tex_tile_cache *tc);
118
119
120
121 extern const struct softpipe_tex_cached_tile *
122 sp_find_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
123 union tex_tile_address addr );
124
125 static INLINE union tex_tile_address
126 tex_tile_address( unsigned x,
127 unsigned y,
128 unsigned z,
129 unsigned face,
130 unsigned level )
131 {
132 union tex_tile_address addr;
133
134 addr.value = 0;
135 addr.bits.x = x / TILE_SIZE;
136 addr.bits.y = y / TILE_SIZE;
137 addr.bits.z = z;
138 addr.bits.face = face;
139 addr.bits.level = level;
140
141 return addr;
142 }
143
144 /* Quickly retrieve tile if it matches last lookup.
145 */
146 static INLINE const struct softpipe_tex_cached_tile *
147 sp_get_cached_tile_tex(struct softpipe_tex_tile_cache *tc,
148 union tex_tile_address addr )
149 {
150 if (tc->last_tile->addr.value == addr.value)
151 return tc->last_tile;
152
153 return sp_find_cached_tile_tex( tc, addr );
154 }
155
156
157
158
159
160 #endif /* SP_TEX_TILE_CACHE_H */
161