1 /**************************************************************************
3 * Copyright 2007 VMware, Inc.
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
26 **************************************************************************/
29 * Render target tile caching.
35 #include "util/u_inlines.h"
36 #include "util/format/u_format.h"
37 #include "util/u_memory.h"
38 #include "util/u_tile.h"
39 #include "sp_tile_cache.h"
41 static struct softpipe_cached_tile
*
42 sp_alloc_tile(struct softpipe_tile_cache
*tc
);
46 * Return the position in the cache for the tile that contains win pos (x,y).
47 * We currently use a direct mapped cache so this is like a hack key.
48 * At some point we should investige something more sophisticated, like
49 * a LRU replacement policy.
51 #define CACHE_POS(x, y, l) \
52 (((x) + (y) * 5 + (l) * 10) % NUM_ENTRIES)
55 static inline int addr_to_clear_pos(union tile_address addr
)
58 pos
= addr
.bits
.layer
* (MAX_WIDTH
/ TILE_SIZE
) * (MAX_HEIGHT
/ TILE_SIZE
);
59 pos
+= addr
.bits
.y
* (MAX_WIDTH
/ TILE_SIZE
);
64 * Is the tile at (x,y) in cleared state?
67 is_clear_flag_set(const uint
*bitvec
, union tile_address addr
, unsigned max
)
70 pos
= addr_to_clear_pos(addr
);
71 assert(pos
/ 32 < max
);
72 bit
= bitvec
[pos
/ 32] & (1 << (pos
& 31));
78 * Mark the tile at (x,y) as not cleared.
81 clear_clear_flag(uint
*bitvec
, union tile_address addr
, unsigned max
)
84 pos
= addr_to_clear_pos(addr
);
85 assert(pos
/ 32 < max
);
86 bitvec
[pos
/ 32] &= ~(1 << (pos
& 31));
90 struct softpipe_tile_cache
*
91 sp_create_tile_cache( struct pipe_context
*pipe
)
93 struct softpipe_tile_cache
*tc
;
96 /* sanity checking: max sure MAX_WIDTH/HEIGHT >= largest texture image */
97 assert(MAX_WIDTH
>= pipe
->screen
->get_param(pipe
->screen
,
98 PIPE_CAP_MAX_TEXTURE_2D_SIZE
));
100 STATIC_ASSERT(sizeof(union tile_address
) == 4);
102 STATIC_ASSERT((TILE_SIZE
<< TILE_ADDR_BITS
) >= MAX_WIDTH
);
104 tc
= CALLOC_STRUCT( softpipe_tile_cache
);
107 for (pos
= 0; pos
< ARRAY_SIZE(tc
->tile_addrs
); pos
++) {
108 tc
->tile_addrs
[pos
].bits
.invalid
= 1;
110 tc
->last_tile_addr
.bits
.invalid
= 1;
112 /* this allocation allows us to guarantee that allocation
113 * failures are never fatal later
115 tc
->tile
= MALLOC_STRUCT( softpipe_cached_tile
);
122 /* XXX this code prevents valgrind warnings about use of uninitialized
123 * memory in programs that don't clear the surface before rendering.
124 * However, it breaks clearing in other situations (such as in
125 * progs/tests/drawbuffers, see bug 24402).
128 /* set flags to indicate all the tiles are cleared */
129 memset(tc
->clear_flags
, 255, sizeof(tc
->clear_flags
));
137 sp_destroy_tile_cache(struct softpipe_tile_cache
*tc
)
142 for (pos
= 0; pos
< ARRAY_SIZE(tc
->entries
); pos
++) {
143 /*assert(tc->entries[pos].x < 0);*/
144 FREE( tc
->entries
[pos
] );
150 for (i
= 0; i
< tc
->num_maps
; i
++)
151 if (tc
->transfer
[i
]) {
152 tc
->pipe
->transfer_unmap(tc
->pipe
, tc
->transfer
[i
]);
155 FREE(tc
->transfer_map
);
156 FREE(tc
->clear_flags
);
165 * Specify the surface to cache.
168 sp_tile_cache_set_surface(struct softpipe_tile_cache
*tc
,
169 struct pipe_surface
*ps
)
171 struct pipe_context
*pipe
= tc
->pipe
;
175 if (ps
== tc
->surface
)
178 for (i
= 0; i
< tc
->num_maps
; i
++) {
179 pipe
->transfer_unmap(pipe
, tc
->transfer
[i
]);
180 tc
->transfer
[i
] = NULL
;
181 tc
->transfer_map
[i
] = NULL
;
184 FREE(tc
->transfer_map
);
187 FREE(tc
->clear_flags
);
188 tc
->clear_flags_size
= 0;
194 tc
->num_maps
= ps
->u
.tex
.last_layer
- ps
->u
.tex
.first_layer
+ 1;
195 tc
->transfer
= CALLOC(tc
->num_maps
, sizeof(struct pipe_transfer
*));
196 tc
->transfer_map
= CALLOC(tc
->num_maps
, sizeof(void *));
198 tc
->clear_flags_size
= (MAX_WIDTH
/ TILE_SIZE
) * (MAX_HEIGHT
/ TILE_SIZE
) * tc
->num_maps
/ 32 * sizeof(uint
);
199 tc
->clear_flags
= CALLOC(1, tc
->clear_flags_size
);
201 if (ps
->texture
->target
!= PIPE_BUFFER
) {
202 for (i
= 0; i
< tc
->num_maps
; i
++) {
203 tc
->transfer_map
[i
] = pipe_transfer_map(pipe
, ps
->texture
,
204 ps
->u
.tex
.level
, ps
->u
.tex
.first_layer
+ i
,
205 PIPE_TRANSFER_READ_WRITE
|
206 PIPE_TRANSFER_UNSYNCHRONIZED
,
207 0, 0, ps
->width
, ps
->height
,
212 /* can't render to buffers */
216 tc
->depth_stencil
= util_format_is_depth_or_stencil(ps
->format
);
222 * Return the transfer being cached.
224 struct pipe_surface
*
225 sp_tile_cache_get_surface(struct softpipe_tile_cache
*tc
)
232 * Set pixels in a tile to the given clear color/value, float.
235 clear_tile_rgba(struct softpipe_cached_tile
*tile
,
236 enum pipe_format format
,
237 const union pipe_color_union
*clear_value
)
239 if (clear_value
->f
[0] == 0.0 &&
240 clear_value
->f
[1] == 0.0 &&
241 clear_value
->f
[2] == 0.0 &&
242 clear_value
->f
[3] == 0.0) {
243 memset(tile
->data
.color
, 0, sizeof(tile
->data
.color
));
248 if (util_format_is_pure_uint(format
)) {
249 for (i
= 0; i
< TILE_SIZE
; i
++) {
250 for (j
= 0; j
< TILE_SIZE
; j
++) {
251 tile
->data
.colorui128
[i
][j
][0] = clear_value
->ui
[0];
252 tile
->data
.colorui128
[i
][j
][1] = clear_value
->ui
[1];
253 tile
->data
.colorui128
[i
][j
][2] = clear_value
->ui
[2];
254 tile
->data
.colorui128
[i
][j
][3] = clear_value
->ui
[3];
257 } else if (util_format_is_pure_sint(format
)) {
258 for (i
= 0; i
< TILE_SIZE
; i
++) {
259 for (j
= 0; j
< TILE_SIZE
; j
++) {
260 tile
->data
.colori128
[i
][j
][0] = clear_value
->i
[0];
261 tile
->data
.colori128
[i
][j
][1] = clear_value
->i
[1];
262 tile
->data
.colori128
[i
][j
][2] = clear_value
->i
[2];
263 tile
->data
.colori128
[i
][j
][3] = clear_value
->i
[3];
267 for (i
= 0; i
< TILE_SIZE
; i
++) {
268 for (j
= 0; j
< TILE_SIZE
; j
++) {
269 tile
->data
.color
[i
][j
][0] = clear_value
->f
[0];
270 tile
->data
.color
[i
][j
][1] = clear_value
->f
[1];
271 tile
->data
.color
[i
][j
][2] = clear_value
->f
[2];
272 tile
->data
.color
[i
][j
][3] = clear_value
->f
[3];
281 * Set a tile to a solid value/color.
284 clear_tile(struct softpipe_cached_tile
*tile
,
285 enum pipe_format format
,
286 uint64_t clear_value
)
290 switch (util_format_get_blocksize(format
)) {
292 memset(tile
->data
.any
, (int) clear_value
, TILE_SIZE
* TILE_SIZE
);
295 if (clear_value
== 0) {
296 memset(tile
->data
.any
, 0, 2 * TILE_SIZE
* TILE_SIZE
);
299 for (i
= 0; i
< TILE_SIZE
; i
++) {
300 for (j
= 0; j
< TILE_SIZE
; j
++) {
301 tile
->data
.depth16
[i
][j
] = (ushort
) clear_value
;
307 if (clear_value
== 0) {
308 memset(tile
->data
.any
, 0, 4 * TILE_SIZE
* TILE_SIZE
);
311 for (i
= 0; i
< TILE_SIZE
; i
++) {
312 for (j
= 0; j
< TILE_SIZE
; j
++) {
313 tile
->data
.depth32
[i
][j
] = (uint
) clear_value
;
319 if (clear_value
== 0) {
320 memset(tile
->data
.any
, 0, 8 * TILE_SIZE
* TILE_SIZE
);
323 for (i
= 0; i
< TILE_SIZE
; i
++) {
324 for (j
= 0; j
< TILE_SIZE
; j
++) {
325 tile
->data
.depth64
[i
][j
] = clear_value
;
337 * Actually clear the tiles which were flagged as being in a clear state.
340 sp_tile_cache_flush_clear(struct softpipe_tile_cache
*tc
, int layer
)
342 struct pipe_transfer
*pt
= tc
->transfer
[layer
];
343 const uint w
= tc
->transfer
[layer
]->box
.width
;
344 const uint h
= tc
->transfer
[layer
]->box
.height
;
348 assert(pt
->resource
);
350 /* clear the scratch tile to the clear value */
351 if (tc
->depth_stencil
) {
352 clear_tile(tc
->tile
, pt
->resource
->format
, tc
->clear_val
);
354 clear_tile_rgba(tc
->tile
, pt
->resource
->format
, &tc
->clear_color
);
357 /* push the tile to all positions marked as clear */
358 for (y
= 0; y
< h
; y
+= TILE_SIZE
) {
359 for (x
= 0; x
< w
; x
+= TILE_SIZE
) {
360 union tile_address addr
= tile_address(x
, y
, layer
);
362 if (is_clear_flag_set(tc
->clear_flags
, addr
, tc
->clear_flags_size
)) {
363 /* write the scratch tile to the surface */
364 if (tc
->depth_stencil
) {
365 pipe_put_tile_raw(pt
, tc
->transfer_map
[layer
],
366 x
, y
, TILE_SIZE
, TILE_SIZE
,
367 tc
->tile
->data
.any
, 0/*STRIDE*/);
370 if (util_format_is_pure_uint(tc
->surface
->format
)) {
371 pipe_put_tile_ui_format(pt
, tc
->transfer_map
[layer
],
372 x
, y
, TILE_SIZE
, TILE_SIZE
,
374 (unsigned *) tc
->tile
->data
.colorui128
);
375 } else if (util_format_is_pure_sint(tc
->surface
->format
)) {
376 pipe_put_tile_i_format(pt
, tc
->transfer_map
[layer
],
377 x
, y
, TILE_SIZE
, TILE_SIZE
,
379 (int *) tc
->tile
->data
.colori128
);
381 pipe_put_tile_rgba_format(pt
, tc
->transfer_map
[layer
],
382 x
, y
, TILE_SIZE
, TILE_SIZE
,
384 (float *) tc
->tile
->data
.color
);
394 debug_printf("num cleared: %u\n", numCleared
);
399 sp_flush_tile(struct softpipe_tile_cache
* tc
, unsigned pos
)
401 int layer
= tc
->tile_addrs
[pos
].bits
.layer
;
402 if (!tc
->tile_addrs
[pos
].bits
.invalid
) {
403 if (tc
->depth_stencil
) {
404 pipe_put_tile_raw(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
405 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
406 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
407 TILE_SIZE
, TILE_SIZE
,
408 tc
->entries
[pos
]->data
.depth32
, 0/*STRIDE*/);
411 if (util_format_is_pure_uint(tc
->surface
->format
)) {
412 pipe_put_tile_ui_format(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
413 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
414 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
415 TILE_SIZE
, TILE_SIZE
,
417 (unsigned *) tc
->entries
[pos
]->data
.colorui128
);
418 } else if (util_format_is_pure_sint(tc
->surface
->format
)) {
419 pipe_put_tile_i_format(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
420 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
421 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
422 TILE_SIZE
, TILE_SIZE
,
424 (int *) tc
->entries
[pos
]->data
.colori128
);
426 pipe_put_tile_rgba_format(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
427 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
428 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
429 TILE_SIZE
, TILE_SIZE
,
431 (float *) tc
->entries
[pos
]->data
.color
);
434 tc
->tile_addrs
[pos
].bits
.invalid
= 1; /* mark as empty */
439 * Flush the tile cache: write all dirty tiles back to the transfer.
440 * any tiles "flagged" as cleared will be "really" cleared.
443 sp_flush_tile_cache(struct softpipe_tile_cache
*tc
)
448 /* caching a drawing transfer */
449 for (pos
= 0; pos
< ARRAY_SIZE(tc
->entries
); pos
++) {
450 struct softpipe_cached_tile
*tile
= tc
->entries
[pos
];
453 assert(tc
->tile_addrs
[pos
].bits
.invalid
);
456 sp_flush_tile(tc
, pos
);
461 tc
->tile
= sp_alloc_tile(tc
);
463 for (i
= 0; i
< tc
->num_maps
; i
++)
464 sp_tile_cache_flush_clear(tc
, i
);
465 /* reset all clear flags to zero */
466 memset(tc
->clear_flags
, 0, tc
->clear_flags_size
);
468 tc
->last_tile_addr
.bits
.invalid
= 1;
472 debug_printf("flushed tiles in use: %d\n", inuse
);
476 static struct softpipe_cached_tile
*
477 sp_alloc_tile(struct softpipe_tile_cache
*tc
)
479 struct softpipe_cached_tile
* tile
= MALLOC_STRUCT(softpipe_cached_tile
);
482 /* in this case, steal an existing tile */
486 for (pos
= 0; pos
< ARRAY_SIZE(tc
->entries
); ++pos
) {
487 if (!tc
->entries
[pos
])
490 sp_flush_tile(tc
, pos
);
491 tc
->tile
= tc
->entries
[pos
];
492 tc
->entries
[pos
] = NULL
;
496 /* this should never happen */
504 tc
->last_tile_addr
.bits
.invalid
= 1;
510 * Get a tile from the cache.
511 * \param x, y position of tile, in pixels
513 struct softpipe_cached_tile
*
514 sp_find_cached_tile(struct softpipe_tile_cache
*tc
,
515 union tile_address addr
)
517 struct pipe_transfer
*pt
;
518 /* cache pos/entry: */
519 const int pos
= CACHE_POS(addr
.bits
.x
,
520 addr
.bits
.y
, addr
.bits
.layer
);
521 struct softpipe_cached_tile
*tile
= tc
->entries
[pos
];
524 tile
= sp_alloc_tile(tc
);
525 tc
->entries
[pos
] = tile
;
528 if (addr
.value
!= tc
->tile_addrs
[pos
].value
) {
530 layer
= tc
->tile_addrs
[pos
].bits
.layer
;
531 if (tc
->tile_addrs
[pos
].bits
.invalid
== 0) {
532 /* put dirty tile back in framebuffer */
533 if (tc
->depth_stencil
) {
534 pipe_put_tile_raw(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
535 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
536 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
537 TILE_SIZE
, TILE_SIZE
,
538 tile
->data
.depth32
, 0/*STRIDE*/);
541 if (util_format_is_pure_uint(tc
->surface
->format
)) {
542 pipe_put_tile_ui_format(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
543 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
544 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
545 TILE_SIZE
, TILE_SIZE
,
547 (unsigned *) tile
->data
.colorui128
);
548 } else if (util_format_is_pure_sint(tc
->surface
->format
)) {
549 pipe_put_tile_i_format(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
550 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
551 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
552 TILE_SIZE
, TILE_SIZE
,
554 (int *) tile
->data
.colori128
);
556 pipe_put_tile_rgba_format(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
557 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
558 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
559 TILE_SIZE
, TILE_SIZE
,
561 (float *) tile
->data
.color
);
566 tc
->tile_addrs
[pos
] = addr
;
568 layer
= tc
->tile_addrs
[pos
].bits
.layer
;
569 pt
= tc
->transfer
[layer
];
570 assert(pt
->resource
);
572 if (is_clear_flag_set(tc
->clear_flags
, addr
, tc
->clear_flags_size
)) {
573 /* don't get tile from framebuffer, just clear it */
574 if (tc
->depth_stencil
) {
575 clear_tile(tile
, pt
->resource
->format
, tc
->clear_val
);
578 clear_tile_rgba(tile
, pt
->resource
->format
, &tc
->clear_color
);
580 clear_clear_flag(tc
->clear_flags
, addr
, tc
->clear_flags_size
);
583 /* get new tile data from transfer */
584 if (tc
->depth_stencil
) {
585 pipe_get_tile_raw(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
586 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
587 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
588 TILE_SIZE
, TILE_SIZE
,
589 tile
->data
.depth32
, 0/*STRIDE*/);
592 if (util_format_is_pure_uint(tc
->surface
->format
)) {
593 pipe_get_tile_ui_format(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
594 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
595 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
596 TILE_SIZE
, TILE_SIZE
,
598 (unsigned *) tile
->data
.colorui128
);
599 } else if (util_format_is_pure_sint(tc
->surface
->format
)) {
600 pipe_get_tile_i_format(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
601 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
602 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
603 TILE_SIZE
, TILE_SIZE
,
605 (int *) tile
->data
.colori128
);
607 pipe_get_tile_rgba_format(tc
->transfer
[layer
], tc
->transfer_map
[layer
],
608 tc
->tile_addrs
[pos
].bits
.x
* TILE_SIZE
,
609 tc
->tile_addrs
[pos
].bits
.y
* TILE_SIZE
,
610 TILE_SIZE
, TILE_SIZE
,
612 (float *) tile
->data
.color
);
618 tc
->last_tile
= tile
;
619 tc
->last_tile_addr
= addr
;
628 * When a whole surface is being cleared to a value we can avoid
629 * fetching tiles above.
630 * Save the color and set a 'clearflag' for each tile of the screen.
633 sp_tile_cache_clear(struct softpipe_tile_cache
*tc
,
634 const union pipe_color_union
*color
,
639 tc
->clear_color
= *color
;
641 tc
->clear_val
= clearValue
;
643 /* set flags to indicate all the tiles are cleared */
644 memset(tc
->clear_flags
, 255, tc
->clear_flags_size
);
646 for (pos
= 0; pos
< ARRAY_SIZE(tc
->tile_addrs
); pos
++) {
647 tc
->tile_addrs
[pos
].bits
.invalid
= 1;
649 tc
->last_tile_addr
.bits
.invalid
= 1;