s/Tungsten Graphics/VMware/
[mesa.git] / src / gallium / drivers / softpipe / sp_tile_cache.h
1 /**************************************************************************
2 *
3 * Copyright 2007 VMware, Inc.
4 * All Rights Reserved.
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the
8 * "Software"), to deal in the Software without restriction, including
9 * without limitation the rights to use, copy, modify, merge, publish,
10 * distribute, sub license, and/or sell copies of the Software, and to
11 * permit persons to whom the Software is furnished to do so, subject to
12 * the following conditions:
13 *
14 * The above copyright notice and this permission notice (including the
15 * next paragraph) shall be included in all copies or substantial portions
16 * of the Software.
17 *
18 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
19 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
20 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT.
21 * IN NO EVENT SHALL VMWARE AND/OR ITS SUPPLIERS BE LIABLE FOR
22 * ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT,
23 * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE
24 * SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
25 *
26 **************************************************************************/
27
28 #ifndef SP_TILE_CACHE_H
29 #define SP_TILE_CACHE_H
30
31
32 #include "pipe/p_compiler.h"
33 #include "sp_texture.h"
34
35
36 struct softpipe_tile_cache;
37
38
39 /**
40 * Cache tile size (width and height). This needs to be a power of two.
41 */
42 #define TILE_SIZE_LOG2 6
43 #define TILE_SIZE (1 << TILE_SIZE_LOG2)
44
45
46 #define TILE_ADDR_BITS (SP_MAX_TEXTURE_2D_LEVELS - 1 - TILE_SIZE_LOG2)
47
48
49 /**
50 * Surface tile address as a union for fast compares.
51 */
52 union tile_address {
53 struct {
54 unsigned x:TILE_ADDR_BITS; /* 16K / TILE_SIZE */
55 unsigned y:TILE_ADDR_BITS; /* 16K / TILE_SIZE */
56 unsigned invalid:1;
57 unsigned pad:15;
58 } bits;
59 unsigned value;
60 };
61
62
63 struct softpipe_cached_tile
64 {
65 union {
66 float color[TILE_SIZE][TILE_SIZE][4];
67 uint color32[TILE_SIZE][TILE_SIZE];
68 uint depth32[TILE_SIZE][TILE_SIZE];
69 ushort depth16[TILE_SIZE][TILE_SIZE];
70 ubyte stencil8[TILE_SIZE][TILE_SIZE];
71 uint colorui128[TILE_SIZE][TILE_SIZE][4];
72 int colori128[TILE_SIZE][TILE_SIZE][4];
73 uint64_t depth64[TILE_SIZE][TILE_SIZE];
74 ubyte any[1];
75 } data;
76 };
77
78 #define NUM_ENTRIES 50
79
80
81 struct softpipe_tile_cache
82 {
83 struct pipe_context *pipe;
84 struct pipe_surface *surface; /**< the surface we're caching */
85 struct pipe_transfer *transfer;
86 void *transfer_map;
87
88 union tile_address tile_addrs[NUM_ENTRIES];
89 struct softpipe_cached_tile *entries[NUM_ENTRIES];
90 uint clear_flags[(MAX_WIDTH / TILE_SIZE) * (MAX_HEIGHT / TILE_SIZE) / 32];
91 union pipe_color_union clear_color; /**< for color bufs */
92 uint64_t clear_val; /**< for z+stencil */
93 boolean depth_stencil; /**< Is the surface a depth/stencil format? */
94
95 struct softpipe_cached_tile *tile; /**< scratch tile for clears */
96
97 union tile_address last_tile_addr;
98 struct softpipe_cached_tile *last_tile; /**< most recently retrieved tile */
99 };
100
101
102 extern struct softpipe_tile_cache *
103 sp_create_tile_cache( struct pipe_context *pipe );
104
105 extern void
106 sp_destroy_tile_cache(struct softpipe_tile_cache *tc);
107
108 extern void
109 sp_tile_cache_set_surface(struct softpipe_tile_cache *tc,
110 struct pipe_surface *sps);
111
112 extern struct pipe_surface *
113 sp_tile_cache_get_surface(struct softpipe_tile_cache *tc);
114
115 extern void
116 sp_flush_tile_cache(struct softpipe_tile_cache *tc);
117
118 extern void
119 sp_tile_cache_clear(struct softpipe_tile_cache *tc,
120 const union pipe_color_union *color,
121 uint64_t clearValue);
122
123 extern struct softpipe_cached_tile *
124 sp_find_cached_tile(struct softpipe_tile_cache *tc,
125 union tile_address addr );
126
127
128 static INLINE union tile_address
129 tile_address( unsigned x,
130 unsigned y )
131 {
132 union tile_address addr;
133
134 addr.value = 0;
135 addr.bits.x = x / TILE_SIZE;
136 addr.bits.y = y / TILE_SIZE;
137
138 return addr;
139 }
140
141 /* Quickly retrieve tile if it matches last lookup.
142 */
143 static INLINE struct softpipe_cached_tile *
144 sp_get_cached_tile(struct softpipe_tile_cache *tc,
145 int x, int y )
146 {
147 union tile_address addr = tile_address( x, y );
148
149 if (tc->last_tile_addr.value == addr.value)
150 return tc->last_tile;
151
152 return sp_find_cached_tile( tc, addr );
153 }
154
155
156
157
158 #endif /* SP_TILE_CACHE_H */
159