svga: set buffer bind_flags in svga_buffer_add_host_surface()
[mesa.git] / src / gallium / drivers / svga / svga_resource_buffer_upload.c
1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
3 *
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
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14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
22 * SOFTWARE.
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25
26
27 #include "os/os_thread.h"
28 #include "pipe/p_state.h"
29 #include "pipe/p_defines.h"
30 #include "util/u_inlines.h"
31 #include "util/u_math.h"
32 #include "util/u_memory.h"
33
34 #include "svga_cmd.h"
35 #include "svga_context.h"
36 #include "svga_debug.h"
37 #include "svga_resource_buffer.h"
38 #include "svga_resource_buffer_upload.h"
39 #include "svga_screen.h"
40 #include "svga_winsys.h"
41
42 /**
43 * Describes a complete SVGA_3D_CMD_UPDATE_GB_IMAGE command
44 *
45 */
46 struct svga_3d_update_gb_image {
47 SVGA3dCmdHeader header;
48 SVGA3dCmdUpdateGBImage body;
49 };
50
51 struct svga_3d_invalidate_gb_image {
52 SVGA3dCmdHeader header;
53 SVGA3dCmdInvalidateGBImage body;
54 };
55
56
57 /**
58 * Allocate a winsys_buffer (ie. DMA, aka GMR memory).
59 *
60 * It will flush and retry in case the first attempt to create a DMA buffer
61 * fails, so it should not be called from any function involved in flushing
62 * to avoid recursion.
63 */
64 struct svga_winsys_buffer *
65 svga_winsys_buffer_create( struct svga_context *svga,
66 unsigned alignment,
67 unsigned usage,
68 unsigned size )
69 {
70 struct svga_screen *svgascreen = svga_screen(svga->pipe.screen);
71 struct svga_winsys_screen *sws = svgascreen->sws;
72 struct svga_winsys_buffer *buf;
73
74 /* Just try */
75 buf = sws->buffer_create(sws, alignment, usage, size);
76 if (!buf) {
77 SVGA_DBG(DEBUG_DMA|DEBUG_PERF, "flushing context to find %d bytes GMR\n",
78 size);
79
80 /* Try flushing all pending DMAs */
81 svga_context_flush(svga, NULL);
82 buf = sws->buffer_create(sws, alignment, usage, size);
83 }
84
85 return buf;
86 }
87
88
89 /**
90 * Destroy HW storage if separate from the host surface.
91 * In the GB case, the HW storage is associated with the host surface
92 * and is therefore a No-op.
93 */
94 void
95 svga_buffer_destroy_hw_storage(struct svga_screen *ss, struct svga_buffer *sbuf)
96 {
97 struct svga_winsys_screen *sws = ss->sws;
98
99 assert(sbuf->map.count == 0);
100 assert(sbuf->hwbuf);
101 if (sbuf->hwbuf) {
102 sws->buffer_destroy(sws, sbuf->hwbuf);
103 sbuf->hwbuf = NULL;
104 }
105 }
106
107
108
109 /**
110 * Allocate DMA'ble or Updatable storage for the buffer.
111 *
112 * Called before mapping a buffer.
113 */
114 enum pipe_error
115 svga_buffer_create_hw_storage(struct svga_screen *ss,
116 struct svga_buffer *sbuf,
117 unsigned bind_flags)
118 {
119 assert(!sbuf->user);
120
121 if (ss->sws->have_gb_objects) {
122 assert(sbuf->handle || !sbuf->dma.pending);
123 return svga_buffer_create_host_surface(ss, sbuf, bind_flags);
124 }
125 if (!sbuf->hwbuf) {
126 struct svga_winsys_screen *sws = ss->sws;
127 unsigned alignment = 16;
128 unsigned usage = 0;
129 unsigned size = sbuf->b.b.width0;
130
131 sbuf->hwbuf = sws->buffer_create(sws, alignment, usage, size);
132 if (!sbuf->hwbuf)
133 return PIPE_ERROR_OUT_OF_MEMORY;
134
135 assert(!sbuf->dma.pending);
136 }
137
138 return PIPE_OK;
139 }
140
141
142 /**
143 * Allocate graphics memory for vertex/index/constant/etc buffer (not
144 * textures).
145 */
146 enum pipe_error
147 svga_buffer_create_host_surface(struct svga_screen *ss,
148 struct svga_buffer *sbuf,
149 unsigned bind_flags)
150 {
151 enum pipe_error ret = PIPE_OK;
152
153 assert(!sbuf->user);
154
155 if (!sbuf->handle) {
156 boolean validated;
157
158 sbuf->key.flags = 0;
159
160 sbuf->key.format = SVGA3D_BUFFER;
161 if (bind_flags & PIPE_BIND_VERTEX_BUFFER) {
162 sbuf->key.flags |= SVGA3D_SURFACE_HINT_VERTEXBUFFER;
163 sbuf->key.flags |= SVGA3D_SURFACE_BIND_VERTEX_BUFFER;
164 }
165 if (bind_flags & PIPE_BIND_INDEX_BUFFER) {
166 sbuf->key.flags |= SVGA3D_SURFACE_HINT_INDEXBUFFER;
167 sbuf->key.flags |= SVGA3D_SURFACE_BIND_INDEX_BUFFER;
168 }
169 if (bind_flags & PIPE_BIND_CONSTANT_BUFFER)
170 sbuf->key.flags |= SVGA3D_SURFACE_BIND_CONSTANT_BUFFER;
171
172 if (bind_flags & PIPE_BIND_STREAM_OUTPUT)
173 sbuf->key.flags |= SVGA3D_SURFACE_BIND_STREAM_OUTPUT;
174
175 if (bind_flags & PIPE_BIND_SAMPLER_VIEW)
176 sbuf->key.flags |= SVGA3D_SURFACE_BIND_SHADER_RESOURCE;
177
178 if (!bind_flags && sbuf->b.b.usage == PIPE_USAGE_STAGING) {
179 /* This surface is to be used with the
180 * SVGA3D_CMD_DX_TRANSFER_FROM_BUFFER command, and no other
181 * bind flags are allowed to be set for this surface.
182 */
183 sbuf->key.flags = SVGA3D_SURFACE_TRANSFER_FROM_BUFFER;
184 }
185
186 sbuf->key.size.width = sbuf->b.b.width0;
187 sbuf->key.size.height = 1;
188 sbuf->key.size.depth = 1;
189
190 sbuf->key.numFaces = 1;
191 sbuf->key.numMipLevels = 1;
192 sbuf->key.cachable = 1;
193 sbuf->key.arraySize = 1;
194 sbuf->key.sampleCount = 0;
195
196 SVGA_DBG(DEBUG_DMA, "surface_create for buffer sz %d\n",
197 sbuf->b.b.width0);
198
199 sbuf->handle = svga_screen_surface_create(ss, bind_flags,
200 sbuf->b.b.usage,
201 &validated, &sbuf->key);
202 if (!sbuf->handle)
203 return PIPE_ERROR_OUT_OF_MEMORY;
204
205 /* Always set the discard flag on the first time the buffer is written
206 * as svga_screen_surface_create might have passed a recycled host
207 * buffer.
208 */
209 sbuf->dma.flags.discard = TRUE;
210
211 SVGA_DBG(DEBUG_DMA, " --> got sid %p sz %d (buffer)\n",
212 sbuf->handle, sbuf->b.b.width0);
213
214 /* Add the new surface to the buffer surface list */
215 ret = svga_buffer_add_host_surface(sbuf, sbuf->handle, &sbuf->key,
216 bind_flags);
217 }
218
219 return ret;
220 }
221
222
223 /**
224 * Recreates a host surface with the new bind flags.
225 */
226 enum pipe_error
227 svga_buffer_recreate_host_surface(struct svga_context *svga,
228 struct svga_buffer *sbuf,
229 unsigned bind_flags)
230 {
231 enum pipe_error ret = PIPE_OK;
232 struct svga_winsys_surface *old_handle = sbuf->handle;
233
234 assert(sbuf->bind_flags != bind_flags);
235 assert(old_handle);
236
237 sbuf->handle = NULL;
238
239 /* Create a new resource with the requested bind_flags */
240 ret = svga_buffer_create_host_surface(svga_screen(svga->pipe.screen),
241 sbuf, bind_flags);
242 if (ret == PIPE_OK) {
243 /* Copy the surface data */
244 assert(sbuf->handle);
245 ret = SVGA3D_vgpu10_BufferCopy(svga->swc, old_handle, sbuf->handle,
246 0, 0, sbuf->b.b.width0);
247 if (ret != PIPE_OK) {
248 svga_context_flush(svga, NULL);
249 ret = SVGA3D_vgpu10_BufferCopy(svga->swc, old_handle, sbuf->handle,
250 0, 0, sbuf->b.b.width0);
251 assert(ret == PIPE_OK);
252 }
253 }
254
255 /* Set the new bind flags for this buffer resource */
256 sbuf->bind_flags = bind_flags;
257
258 return ret;
259 }
260
261
262 /**
263 * Returns TRUE if the surface bind flags is compatible with the new bind flags.
264 */
265 static boolean
266 compatible_bind_flags(unsigned bind_flags,
267 unsigned tobind_flags)
268 {
269 if ((bind_flags & tobind_flags) == tobind_flags)
270 return TRUE;
271 else if ((bind_flags|tobind_flags) & PIPE_BIND_CONSTANT_BUFFER)
272 return FALSE;
273 else
274 return TRUE;
275 }
276
277
278 /**
279 * Returns a buffer surface from the surface list
280 * that has the requested bind flags or its existing bind flags
281 * can be promoted to include the new bind flags.
282 */
283 static struct svga_buffer_surface *
284 svga_buffer_get_host_surface(struct svga_buffer *sbuf,
285 unsigned bind_flags)
286 {
287 struct svga_buffer_surface *bufsurf;
288
289 LIST_FOR_EACH_ENTRY(bufsurf, &sbuf->surfaces, list) {
290 if (compatible_bind_flags(bufsurf->bind_flags, bind_flags))
291 return bufsurf;
292 }
293 return NULL;
294 }
295
296
297 /**
298 * Adds the host surface to the buffer surface list.
299 */
300 enum pipe_error
301 svga_buffer_add_host_surface(struct svga_buffer *sbuf,
302 struct svga_winsys_surface *handle,
303 struct svga_host_surface_cache_key *key,
304 unsigned bind_flags)
305 {
306 struct svga_buffer_surface *bufsurf;
307
308 bufsurf = CALLOC_STRUCT(svga_buffer_surface);
309 if (!bufsurf)
310 return PIPE_ERROR_OUT_OF_MEMORY;
311
312 bufsurf->bind_flags = bind_flags;
313 bufsurf->handle = handle;
314 bufsurf->key = *key;
315
316 /* add the surface to the surface list */
317 LIST_ADD(&bufsurf->list, &sbuf->surfaces);
318
319 /* Set the new bind flags for this buffer resource */
320 sbuf->bind_flags = bind_flags;
321
322 return PIPE_OK;
323 }
324
325
326 /**
327 * Start using the specified surface for this buffer resource.
328 */
329 void
330 svga_buffer_bind_host_surface(struct svga_context *svga,
331 struct svga_buffer *sbuf,
332 struct svga_buffer_surface *bufsurf)
333 {
334 enum pipe_error ret;
335
336 /* Update the to-bind surface */
337 assert(bufsurf->handle);
338 assert(sbuf->handle);
339
340 /* If we are switching from stream output to other buffer,
341 * make sure to copy the buffer content.
342 */
343 if (sbuf->bind_flags & PIPE_BIND_STREAM_OUTPUT) {
344 ret = SVGA3D_vgpu10_BufferCopy(svga->swc, sbuf->handle, bufsurf->handle,
345 0, 0, sbuf->b.b.width0);
346 if (ret != PIPE_OK) {
347 svga_context_flush(svga, NULL);
348 ret = SVGA3D_vgpu10_BufferCopy(svga->swc, sbuf->handle, bufsurf->handle,
349 0, 0, sbuf->b.b.width0);
350 assert(ret == PIPE_OK);
351 }
352 }
353
354 /* Set this surface as the current one */
355 sbuf->handle = bufsurf->handle;
356 sbuf->key = bufsurf->key;
357 sbuf->bind_flags = bufsurf->bind_flags;
358 }
359
360
361 /**
362 * Prepare a host surface that can be used as indicated in the
363 * tobind_flags. If the existing host surface is not created
364 * with the necessary binding flags and if the new bind flags can be
365 * combined with the existing bind flags, then we will recreate a
366 * new surface with the combined bind flags. Otherwise, we will create
367 * a surface for that incompatible bind flags.
368 * For example, if a stream output buffer is reused as a constant buffer,
369 * since constant buffer surface cannot be bound as a stream output surface,
370 * two surfaces will be created, one for stream output,
371 * and another one for constant buffer.
372 */
373 enum pipe_error
374 svga_buffer_validate_host_surface(struct svga_context *svga,
375 struct svga_buffer *sbuf,
376 unsigned tobind_flags)
377 {
378 struct svga_buffer_surface *bufsurf;
379 enum pipe_error ret = PIPE_OK;
380
381 /* Flush any pending upload first */
382 svga_buffer_upload_flush(svga, sbuf);
383
384 /* First check from the cached buffer surface list to see if there is
385 * already a buffer surface that has the requested bind flags, or
386 * surface with compatible bind flags that can be promoted.
387 */
388 bufsurf = svga_buffer_get_host_surface(sbuf, tobind_flags);
389
390 if (bufsurf) {
391 if ((bufsurf->bind_flags & tobind_flags) == tobind_flags) {
392 /* there is a surface with the requested bind flags */
393 svga_buffer_bind_host_surface(svga, sbuf, bufsurf);
394 } else {
395
396 /* Recreate a host surface with the combined bind flags */
397 ret = svga_buffer_recreate_host_surface(svga, sbuf,
398 bufsurf->bind_flags |
399 tobind_flags);
400
401 /* Destroy the old surface */
402 svga_screen_surface_destroy(svga_screen(sbuf->b.b.screen),
403 &bufsurf->key, &bufsurf->handle);
404
405 LIST_DEL(&bufsurf->list);
406 FREE(bufsurf);
407 }
408 } else {
409 /* Need to create a new surface if the bind flags are incompatible,
410 * such as constant buffer surface & stream output surface.
411 */
412 ret = svga_buffer_recreate_host_surface(svga, sbuf,
413 tobind_flags);
414 }
415 return ret;
416 }
417
418
419 void
420 svga_buffer_destroy_host_surface(struct svga_screen *ss,
421 struct svga_buffer *sbuf)
422 {
423 struct svga_buffer_surface *bufsurf, *next;
424
425 LIST_FOR_EACH_ENTRY_SAFE(bufsurf, next, &sbuf->surfaces, list) {
426 SVGA_DBG(DEBUG_DMA, " ungrab sid %p sz %d\n",
427 bufsurf->handle, sbuf->b.b.width0);
428 svga_screen_surface_destroy(ss, &bufsurf->key, &bufsurf->handle);
429 FREE(bufsurf);
430 }
431 }
432
433
434 /**
435 * Insert a number of preliminary UPDATE_GB_IMAGE commands in the
436 * command buffer, equal to the current number of mapped ranges.
437 * The UPDATE_GB_IMAGE commands will be patched with the
438 * actual ranges just before flush.
439 */
440 static enum pipe_error
441 svga_buffer_upload_gb_command(struct svga_context *svga,
442 struct svga_buffer *sbuf)
443 {
444 struct svga_winsys_context *swc = svga->swc;
445 SVGA3dCmdUpdateGBImage *update_cmd;
446 struct svga_3d_update_gb_image *whole_update_cmd = NULL;
447 const uint32 numBoxes = sbuf->map.num_ranges;
448 struct pipe_resource *dummy;
449 unsigned i;
450
451 assert(svga_have_gb_objects(svga));
452 assert(numBoxes);
453 assert(sbuf->dma.updates == NULL);
454
455 if (sbuf->dma.flags.discard) {
456 struct svga_3d_invalidate_gb_image *cicmd = NULL;
457 SVGA3dCmdInvalidateGBImage *invalidate_cmd;
458 const unsigned total_commands_size =
459 sizeof(*invalidate_cmd) + numBoxes * sizeof(*whole_update_cmd);
460
461 /* Allocate FIFO space for one INVALIDATE_GB_IMAGE command followed by
462 * 'numBoxes' UPDATE_GB_IMAGE commands. Allocate all at once rather
463 * than with separate commands because we need to properly deal with
464 * filling the command buffer.
465 */
466 invalidate_cmd = SVGA3D_FIFOReserve(swc,
467 SVGA_3D_CMD_INVALIDATE_GB_IMAGE,
468 total_commands_size, 1 + numBoxes);
469 if (!invalidate_cmd)
470 return PIPE_ERROR_OUT_OF_MEMORY;
471
472 cicmd = container_of(invalidate_cmd, cicmd, body);
473 cicmd->header.size = sizeof(*invalidate_cmd);
474 swc->surface_relocation(swc, &invalidate_cmd->image.sid, NULL,
475 sbuf->handle,
476 (SVGA_RELOC_WRITE |
477 SVGA_RELOC_INTERNAL |
478 SVGA_RELOC_DMA));
479 invalidate_cmd->image.face = 0;
480 invalidate_cmd->image.mipmap = 0;
481
482 /* The whole_update_command is a SVGA3dCmdHeader plus the
483 * SVGA3dCmdUpdateGBImage command.
484 */
485 whole_update_cmd = (struct svga_3d_update_gb_image *) &invalidate_cmd[1];
486 /* initialize the first UPDATE_GB_IMAGE command */
487 whole_update_cmd->header.id = SVGA_3D_CMD_UPDATE_GB_IMAGE;
488 update_cmd = &whole_update_cmd->body;
489
490 } else {
491 /* Allocate FIFO space for 'numBoxes' UPDATE_GB_IMAGE commands */
492 const unsigned total_commands_size =
493 sizeof(*update_cmd) + (numBoxes - 1) * sizeof(*whole_update_cmd);
494
495 update_cmd = SVGA3D_FIFOReserve(swc,
496 SVGA_3D_CMD_UPDATE_GB_IMAGE,
497 total_commands_size, numBoxes);
498 if (!update_cmd)
499 return PIPE_ERROR_OUT_OF_MEMORY;
500
501 /* The whole_update_command is a SVGA3dCmdHeader plus the
502 * SVGA3dCmdUpdateGBImage command.
503 */
504 whole_update_cmd = container_of(update_cmd, whole_update_cmd, body);
505 }
506
507 /* Init the first UPDATE_GB_IMAGE command */
508 whole_update_cmd->header.size = sizeof(*update_cmd);
509 swc->surface_relocation(swc, &update_cmd->image.sid, NULL, sbuf->handle,
510 SVGA_RELOC_WRITE | SVGA_RELOC_INTERNAL);
511 update_cmd->image.face = 0;
512 update_cmd->image.mipmap = 0;
513
514 /* Save pointer to the first UPDATE_GB_IMAGE command so that we can
515 * fill in the box info below.
516 */
517 sbuf->dma.updates = whole_update_cmd;
518
519 /*
520 * Copy the face, mipmap, etc. info to all subsequent commands.
521 * Also do the surface relocation for each subsequent command.
522 */
523 for (i = 1; i < numBoxes; ++i) {
524 whole_update_cmd++;
525 memcpy(whole_update_cmd, sbuf->dma.updates, sizeof(*whole_update_cmd));
526
527 swc->surface_relocation(swc, &whole_update_cmd->body.image.sid, NULL,
528 sbuf->handle,
529 SVGA_RELOC_WRITE | SVGA_RELOC_INTERNAL);
530 }
531
532 /* Increment reference count */
533 sbuf->dma.svga = svga;
534 dummy = NULL;
535 pipe_resource_reference(&dummy, &sbuf->b.b);
536 SVGA_FIFOCommitAll(swc);
537
538 swc->hints |= SVGA_HINT_FLAG_CAN_PRE_FLUSH;
539 sbuf->dma.flags.discard = FALSE;
540
541 svga->hud.num_resource_updates++;
542
543 return PIPE_OK;
544 }
545
546
547 /**
548 * Issue DMA commands to transfer guest memory to the host.
549 * Note that the memory segments (offset, size) will be patched in
550 * later in the svga_buffer_upload_flush() function.
551 */
552 static enum pipe_error
553 svga_buffer_upload_hb_command(struct svga_context *svga,
554 struct svga_buffer *sbuf)
555 {
556 struct svga_winsys_context *swc = svga->swc;
557 struct svga_winsys_buffer *guest = sbuf->hwbuf;
558 struct svga_winsys_surface *host = sbuf->handle;
559 const SVGA3dTransferType transfer = SVGA3D_WRITE_HOST_VRAM;
560 SVGA3dCmdSurfaceDMA *cmd;
561 const uint32 numBoxes = sbuf->map.num_ranges;
562 SVGA3dCopyBox *boxes;
563 SVGA3dCmdSurfaceDMASuffix *pSuffix;
564 unsigned region_flags;
565 unsigned surface_flags;
566 struct pipe_resource *dummy;
567
568 assert(!svga_have_gb_objects(svga));
569
570 if (transfer == SVGA3D_WRITE_HOST_VRAM) {
571 region_flags = SVGA_RELOC_READ;
572 surface_flags = SVGA_RELOC_WRITE;
573 }
574 else if (transfer == SVGA3D_READ_HOST_VRAM) {
575 region_flags = SVGA_RELOC_WRITE;
576 surface_flags = SVGA_RELOC_READ;
577 }
578 else {
579 assert(0);
580 return PIPE_ERROR_BAD_INPUT;
581 }
582
583 assert(numBoxes);
584
585 cmd = SVGA3D_FIFOReserve(swc,
586 SVGA_3D_CMD_SURFACE_DMA,
587 sizeof *cmd + numBoxes * sizeof *boxes + sizeof *pSuffix,
588 2);
589 if (!cmd)
590 return PIPE_ERROR_OUT_OF_MEMORY;
591
592 swc->region_relocation(swc, &cmd->guest.ptr, guest, 0, region_flags);
593 cmd->guest.pitch = 0;
594
595 swc->surface_relocation(swc, &cmd->host.sid, NULL, host, surface_flags);
596 cmd->host.face = 0;
597 cmd->host.mipmap = 0;
598
599 cmd->transfer = transfer;
600
601 sbuf->dma.boxes = (SVGA3dCopyBox *)&cmd[1];
602 sbuf->dma.svga = svga;
603
604 /* Increment reference count */
605 dummy = NULL;
606 pipe_resource_reference(&dummy, &sbuf->b.b);
607
608 pSuffix = (SVGA3dCmdSurfaceDMASuffix *)((uint8_t*)cmd + sizeof *cmd + numBoxes * sizeof *boxes);
609 pSuffix->suffixSize = sizeof *pSuffix;
610 pSuffix->maximumOffset = sbuf->b.b.width0;
611 pSuffix->flags = sbuf->dma.flags;
612
613 SVGA_FIFOCommitAll(swc);
614
615 swc->hints |= SVGA_HINT_FLAG_CAN_PRE_FLUSH;
616 sbuf->dma.flags.discard = FALSE;
617
618 svga->hud.num_buffer_uploads++;
619
620 return PIPE_OK;
621 }
622
623
624 /**
625 * Issue commands to transfer guest memory to the host.
626 */
627 static enum pipe_error
628 svga_buffer_upload_command(struct svga_context *svga, struct svga_buffer *sbuf)
629 {
630 if (svga_have_gb_objects(svga)) {
631 return svga_buffer_upload_gb_command(svga, sbuf);
632 } else {
633 return svga_buffer_upload_hb_command(svga, sbuf);
634 }
635 }
636
637
638 /**
639 * Patch up the upload DMA command reserved by svga_buffer_upload_command
640 * with the final ranges.
641 */
642 void
643 svga_buffer_upload_flush(struct svga_context *svga, struct svga_buffer *sbuf)
644 {
645 unsigned i;
646 struct pipe_resource *dummy;
647
648 if (!sbuf->dma.pending) {
649 //debug_printf("no dma pending on buffer\n");
650 return;
651 }
652
653 assert(sbuf->handle);
654 assert(sbuf->map.num_ranges);
655 assert(sbuf->dma.svga == svga);
656
657 /*
658 * Patch the DMA/update command with the final copy box.
659 */
660 if (svga_have_gb_objects(svga)) {
661 struct svga_3d_update_gb_image *update = sbuf->dma.updates;
662 assert(update);
663
664 for (i = 0; i < sbuf->map.num_ranges; ++i, ++update) {
665 SVGA3dBox *box = &update->body.box;
666
667 SVGA_DBG(DEBUG_DMA, " bytes %u - %u\n",
668 sbuf->map.ranges[i].start, sbuf->map.ranges[i].end);
669
670 box->x = sbuf->map.ranges[i].start;
671 box->y = 0;
672 box->z = 0;
673 box->w = sbuf->map.ranges[i].end - sbuf->map.ranges[i].start;
674 box->h = 1;
675 box->d = 1;
676
677 assert(box->x <= sbuf->b.b.width0);
678 assert(box->x + box->w <= sbuf->b.b.width0);
679
680 svga->hud.num_bytes_uploaded += box->w;
681 svga->hud.num_buffer_uploads++;
682 }
683 }
684 else {
685 assert(sbuf->hwbuf);
686 assert(sbuf->dma.boxes);
687 SVGA_DBG(DEBUG_DMA, "dma to sid %p\n", sbuf->handle);
688
689 for (i = 0; i < sbuf->map.num_ranges; ++i) {
690 SVGA3dCopyBox *box = sbuf->dma.boxes + i;
691
692 SVGA_DBG(DEBUG_DMA, " bytes %u - %u\n",
693 sbuf->map.ranges[i].start, sbuf->map.ranges[i].end);
694
695 box->x = sbuf->map.ranges[i].start;
696 box->y = 0;
697 box->z = 0;
698 box->w = sbuf->map.ranges[i].end - sbuf->map.ranges[i].start;
699 box->h = 1;
700 box->d = 1;
701 box->srcx = sbuf->map.ranges[i].start;
702 box->srcy = 0;
703 box->srcz = 0;
704
705 assert(box->x <= sbuf->b.b.width0);
706 assert(box->x + box->w <= sbuf->b.b.width0);
707
708 svga->hud.num_bytes_uploaded += box->w;
709 svga->hud.num_buffer_uploads++;
710 }
711 }
712
713 /* Reset sbuf for next use/upload */
714
715 sbuf->map.num_ranges = 0;
716
717 assert(sbuf->head.prev && sbuf->head.next);
718 LIST_DEL(&sbuf->head); /* remove from svga->dirty_buffers list */
719 #ifdef DEBUG
720 sbuf->head.next = sbuf->head.prev = NULL;
721 #endif
722 sbuf->dma.pending = FALSE;
723 sbuf->dma.flags.discard = FALSE;
724 sbuf->dma.flags.unsynchronized = FALSE;
725
726 sbuf->dma.svga = NULL;
727 sbuf->dma.boxes = NULL;
728 sbuf->dma.updates = NULL;
729
730 /* Decrement reference count (and potentially destroy) */
731 dummy = &sbuf->b.b;
732 pipe_resource_reference(&dummy, NULL);
733 }
734
735
736 /**
737 * Note a dirty range.
738 *
739 * This function only notes the range down. It doesn't actually emit a DMA
740 * upload command. That only happens when a context tries to refer to this
741 * buffer, and the DMA upload command is added to that context's command
742 * buffer.
743 *
744 * We try to lump as many contiguous DMA transfers together as possible.
745 */
746 void
747 svga_buffer_add_range(struct svga_buffer *sbuf, unsigned start, unsigned end)
748 {
749 unsigned i;
750 unsigned nearest_range;
751 unsigned nearest_dist;
752
753 assert(end > start);
754
755 if (sbuf->map.num_ranges < SVGA_BUFFER_MAX_RANGES) {
756 nearest_range = sbuf->map.num_ranges;
757 nearest_dist = ~0;
758 } else {
759 nearest_range = SVGA_BUFFER_MAX_RANGES - 1;
760 nearest_dist = 0;
761 }
762
763 /*
764 * Try to grow one of the ranges.
765 */
766 for (i = 0; i < sbuf->map.num_ranges; ++i) {
767 const int left_dist = start - sbuf->map.ranges[i].end;
768 const int right_dist = sbuf->map.ranges[i].start - end;
769 const int dist = MAX2(left_dist, right_dist);
770
771 if (dist <= 0) {
772 /*
773 * Ranges are contiguous or overlapping -- extend this one and return.
774 *
775 * Note that it is not this function's task to prevent overlapping
776 * ranges, as the GMR was already given so it is too late to do
777 * anything. If the ranges overlap here it must surely be because
778 * PIPE_TRANSFER_UNSYNCHRONIZED was set.
779 */
780 sbuf->map.ranges[i].start = MIN2(sbuf->map.ranges[i].start, start);
781 sbuf->map.ranges[i].end = MAX2(sbuf->map.ranges[i].end, end);
782 return;
783 }
784 else {
785 /*
786 * Discontiguous ranges -- keep track of the nearest range.
787 */
788 if (dist < nearest_dist) {
789 nearest_range = i;
790 nearest_dist = dist;
791 }
792 }
793 }
794
795 /*
796 * We cannot add a new range to an existing DMA command, so patch-up the
797 * pending DMA upload and start clean.
798 */
799
800 svga_buffer_upload_flush(sbuf->dma.svga, sbuf);
801
802 assert(!sbuf->dma.pending);
803 assert(!sbuf->dma.svga);
804 assert(!sbuf->dma.boxes);
805
806 if (sbuf->map.num_ranges < SVGA_BUFFER_MAX_RANGES) {
807 /*
808 * Add a new range.
809 */
810
811 sbuf->map.ranges[sbuf->map.num_ranges].start = start;
812 sbuf->map.ranges[sbuf->map.num_ranges].end = end;
813 ++sbuf->map.num_ranges;
814 } else {
815 /*
816 * Everything else failed, so just extend the nearest range.
817 *
818 * It is OK to do this because we always keep a local copy of the
819 * host buffer data, for SW TNL, and the host never modifies the buffer.
820 */
821
822 assert(nearest_range < SVGA_BUFFER_MAX_RANGES);
823 assert(nearest_range < sbuf->map.num_ranges);
824 sbuf->map.ranges[nearest_range].start =
825 MIN2(sbuf->map.ranges[nearest_range].start, start);
826 sbuf->map.ranges[nearest_range].end =
827 MAX2(sbuf->map.ranges[nearest_range].end, end);
828 }
829 }
830
831
832
833 /**
834 * Copy the contents of the malloc buffer to a hardware buffer.
835 */
836 static enum pipe_error
837 svga_buffer_update_hw(struct svga_context *svga, struct svga_buffer *sbuf,
838 unsigned bind_flags)
839 {
840 assert(!sbuf->user);
841 if (!svga_buffer_has_hw_storage(sbuf)) {
842 struct svga_screen *ss = svga_screen(sbuf->b.b.screen);
843 enum pipe_error ret;
844 boolean retry;
845 void *map;
846 unsigned i;
847
848 assert(sbuf->swbuf);
849 if (!sbuf->swbuf)
850 return PIPE_ERROR;
851
852 ret = svga_buffer_create_hw_storage(svga_screen(sbuf->b.b.screen), sbuf,
853 bind_flags);
854 if (ret != PIPE_OK)
855 return ret;
856
857 mtx_lock(&ss->swc_mutex);
858 map = svga_buffer_hw_storage_map(svga, sbuf, PIPE_TRANSFER_WRITE, &retry);
859 assert(map);
860 assert(!retry);
861 if (!map) {
862 mtx_unlock(&ss->swc_mutex);
863 svga_buffer_destroy_hw_storage(ss, sbuf);
864 return PIPE_ERROR;
865 }
866
867 /* Copy data from malloc'd swbuf to the new hardware buffer */
868 for (i = 0; i < sbuf->map.num_ranges; i++) {
869 unsigned start = sbuf->map.ranges[i].start;
870 unsigned len = sbuf->map.ranges[i].end - start;
871 memcpy((uint8_t *) map + start, (uint8_t *) sbuf->swbuf + start, len);
872 }
873
874 svga_buffer_hw_storage_unmap(svga, sbuf);
875
876 /* This user/malloc buffer is now indistinguishable from a gpu buffer */
877 assert(sbuf->map.count == 0);
878 if (sbuf->map.count == 0) {
879 if (sbuf->user)
880 sbuf->user = FALSE;
881 else
882 align_free(sbuf->swbuf);
883 sbuf->swbuf = NULL;
884 }
885
886 mtx_unlock(&ss->swc_mutex);
887 }
888
889 return PIPE_OK;
890 }
891
892
893 /**
894 * Upload the buffer to the host in a piecewise fashion.
895 *
896 * Used when the buffer is too big to fit in the GMR aperture.
897 * This function should never get called in the guest-backed case
898 * since we always have a full-sized hardware storage backing the
899 * host surface.
900 */
901 static enum pipe_error
902 svga_buffer_upload_piecewise(struct svga_screen *ss,
903 struct svga_context *svga,
904 struct svga_buffer *sbuf)
905 {
906 struct svga_winsys_screen *sws = ss->sws;
907 const unsigned alignment = sizeof(void *);
908 const unsigned usage = 0;
909 unsigned i;
910
911 assert(sbuf->map.num_ranges);
912 assert(!sbuf->dma.pending);
913 assert(!svga_have_gb_objects(svga));
914
915 SVGA_DBG(DEBUG_DMA, "dma to sid %p\n", sbuf->handle);
916
917 for (i = 0; i < sbuf->map.num_ranges; ++i) {
918 const struct svga_buffer_range *range = &sbuf->map.ranges[i];
919 unsigned offset = range->start;
920 unsigned size = range->end - range->start;
921
922 while (offset < range->end) {
923 struct svga_winsys_buffer *hwbuf;
924 uint8_t *map;
925 enum pipe_error ret;
926
927 if (offset + size > range->end)
928 size = range->end - offset;
929
930 hwbuf = sws->buffer_create(sws, alignment, usage, size);
931 while (!hwbuf) {
932 size /= 2;
933 if (!size)
934 return PIPE_ERROR_OUT_OF_MEMORY;
935 hwbuf = sws->buffer_create(sws, alignment, usage, size);
936 }
937
938 SVGA_DBG(DEBUG_DMA, " bytes %u - %u\n",
939 offset, offset + size);
940
941 map = sws->buffer_map(sws, hwbuf,
942 PIPE_TRANSFER_WRITE |
943 PIPE_TRANSFER_DISCARD_RANGE);
944 assert(map);
945 if (map) {
946 memcpy(map, (const char *) sbuf->swbuf + offset, size);
947 sws->buffer_unmap(sws, hwbuf);
948 }
949
950 ret = SVGA3D_BufferDMA(svga->swc,
951 hwbuf, sbuf->handle,
952 SVGA3D_WRITE_HOST_VRAM,
953 size, 0, offset, sbuf->dma.flags);
954 if (ret != PIPE_OK) {
955 svga_context_flush(svga, NULL);
956 ret = SVGA3D_BufferDMA(svga->swc,
957 hwbuf, sbuf->handle,
958 SVGA3D_WRITE_HOST_VRAM,
959 size, 0, offset, sbuf->dma.flags);
960 assert(ret == PIPE_OK);
961 }
962
963 sbuf->dma.flags.discard = FALSE;
964
965 sws->buffer_destroy(sws, hwbuf);
966
967 offset += size;
968 }
969 }
970
971 sbuf->map.num_ranges = 0;
972
973 return PIPE_OK;
974 }
975
976
977 /**
978 * Get (or create/upload) the winsys surface handle so that we can
979 * refer to this buffer in fifo commands.
980 * This function will create the host surface, and in the GB case also the
981 * hardware storage. In the non-GB case, the hardware storage will be created
982 * if there are mapped ranges and the data is currently in a malloc'ed buffer.
983 */
984 struct svga_winsys_surface *
985 svga_buffer_handle(struct svga_context *svga, struct pipe_resource *buf,
986 unsigned tobind_flags)
987 {
988 struct pipe_screen *screen = svga->pipe.screen;
989 struct svga_screen *ss = svga_screen(screen);
990 struct svga_buffer *sbuf;
991 enum pipe_error ret;
992
993 if (!buf)
994 return NULL;
995
996 sbuf = svga_buffer(buf);
997
998 assert(!sbuf->user);
999
1000 if (sbuf->handle) {
1001 if ((sbuf->bind_flags & tobind_flags) != tobind_flags) {
1002 /* If the allocated resource's bind flags do not include the
1003 * requested bind flags, validate the host surface.
1004 */
1005 ret = svga_buffer_validate_host_surface(svga, sbuf, tobind_flags);
1006 if (ret != PIPE_OK)
1007 return NULL;
1008 }
1009 } else {
1010 /* If there is no resource handle yet, then combine the buffer bind
1011 * flags and the tobind_flags if they are compatible.
1012 * If not, just use the tobind_flags for creating the resource handle.
1013 */
1014 if (compatible_bind_flags(sbuf->bind_flags, tobind_flags))
1015 sbuf->bind_flags = sbuf->bind_flags | tobind_flags;
1016 else
1017 sbuf->bind_flags = tobind_flags;
1018
1019 assert((sbuf->bind_flags & tobind_flags) == tobind_flags);
1020
1021 /* This call will set sbuf->handle */
1022 if (svga_have_gb_objects(svga)) {
1023 ret = svga_buffer_update_hw(svga, sbuf, sbuf->bind_flags);
1024 } else {
1025 ret = svga_buffer_create_host_surface(ss, sbuf, sbuf->bind_flags);
1026 }
1027 if (ret != PIPE_OK)
1028 return NULL;
1029 }
1030
1031 assert(sbuf->handle);
1032
1033 if (sbuf->map.num_ranges) {
1034 if (!sbuf->dma.pending) {
1035 /* No pending DMA/update commands yet. */
1036
1037 /* Migrate the data from swbuf -> hwbuf if necessary */
1038 ret = svga_buffer_update_hw(svga, sbuf, sbuf->bind_flags);
1039 if (ret == PIPE_OK) {
1040 /* Emit DMA or UpdateGBImage commands */
1041 ret = svga_buffer_upload_command(svga, sbuf);
1042 if (ret == PIPE_ERROR_OUT_OF_MEMORY) {
1043 svga_context_flush(svga, NULL);
1044 ret = svga_buffer_upload_command(svga, sbuf);
1045 assert(ret == PIPE_OK);
1046 }
1047 if (ret == PIPE_OK) {
1048 sbuf->dma.pending = TRUE;
1049 assert(!sbuf->head.prev && !sbuf->head.next);
1050 LIST_ADDTAIL(&sbuf->head, &svga->dirty_buffers);
1051 }
1052 }
1053 else if (ret == PIPE_ERROR_OUT_OF_MEMORY) {
1054 /*
1055 * The buffer is too big to fit in the GMR aperture, so break it in
1056 * smaller pieces.
1057 */
1058 ret = svga_buffer_upload_piecewise(ss, svga, sbuf);
1059 }
1060
1061 if (ret != PIPE_OK) {
1062 /*
1063 * Something unexpected happened above. There is very little that
1064 * we can do other than proceeding while ignoring the dirty ranges.
1065 */
1066 assert(0);
1067 sbuf->map.num_ranges = 0;
1068 }
1069 }
1070 else {
1071 /*
1072 * There a pending dma already. Make sure it is from this context.
1073 */
1074 assert(sbuf->dma.svga == svga);
1075 }
1076 }
1077
1078 assert(sbuf->map.num_ranges == 0 || sbuf->dma.pending);
1079
1080 return sbuf->handle;
1081 }
1082
1083
1084 void
1085 svga_context_flush_buffers(struct svga_context *svga)
1086 {
1087 struct list_head *curr, *next;
1088
1089 SVGA_STATS_TIME_PUSH(svga_sws(svga), SVGA_STATS_TIME_BUFFERSFLUSH);
1090
1091 curr = svga->dirty_buffers.next;
1092 next = curr->next;
1093 while (curr != &svga->dirty_buffers) {
1094 struct svga_buffer *sbuf = LIST_ENTRY(struct svga_buffer, curr, head);
1095
1096 assert(p_atomic_read(&sbuf->b.b.reference.count) != 0);
1097 assert(sbuf->dma.pending);
1098
1099 svga_buffer_upload_flush(svga, sbuf);
1100
1101 curr = next;
1102 next = curr->next;
1103 }
1104
1105 SVGA_STATS_TIME_POP(svga_sws(svga));
1106 }