1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
27 #include "util/format/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_inlines.h"
30 #include "util/u_screen.h"
31 #include "util/u_string.h"
32 #include "util/u_math.h"
34 #include "os/os_process.h"
36 #include "svga_winsys.h"
37 #include "svga_public.h"
38 #include "svga_context.h"
39 #include "svga_format.h"
40 #include "svga_screen.h"
41 #include "svga_tgsi.h"
42 #include "svga_resource_texture.h"
43 #include "svga_resource.h"
44 #include "svga_debug.h"
46 #include "svga3d_shaderdefs.h"
47 #include "VGPU10ShaderTokens.h"
49 /* NOTE: this constant may get moved into a svga3d*.h header file */
50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
53 #define MESA_GIT_SHA1 "(unknown git revision)"
59 static const struct debug_named_value svga_debug_flags
[] = {
60 { "dma", DEBUG_DMA
, NULL
},
61 { "tgsi", DEBUG_TGSI
, NULL
},
62 { "pipe", DEBUG_PIPE
, NULL
},
63 { "state", DEBUG_STATE
, NULL
},
64 { "screen", DEBUG_SCREEN
, NULL
},
65 { "tex", DEBUG_TEX
, NULL
},
66 { "swtnl", DEBUG_SWTNL
, NULL
},
67 { "const", DEBUG_CONSTS
, NULL
},
68 { "viewport", DEBUG_VIEWPORT
, NULL
},
69 { "views", DEBUG_VIEWS
, NULL
},
70 { "perf", DEBUG_PERF
, NULL
},
71 { "flush", DEBUG_FLUSH
, NULL
},
72 { "sync", DEBUG_SYNC
, NULL
},
73 { "cache", DEBUG_CACHE
, NULL
},
74 { "streamout", DEBUG_STREAMOUT
, NULL
},
75 { "query", DEBUG_QUERY
, NULL
},
76 { "samplers", DEBUG_SAMPLERS
, NULL
},
82 svga_get_vendor( struct pipe_screen
*pscreen
)
84 return "VMware, Inc.";
89 svga_get_name( struct pipe_screen
*pscreen
)
91 const char *build
= "", *llvm
= "", *mutex
= "";
92 static char name
[100];
94 /* Only return internal details in the DEBUG version:
96 build
= "build: DEBUG;";
97 mutex
= "mutex: " PIPE_ATOMIC
";";
99 build
= "build: RELEASE;";
101 #ifdef LLVM_AVAILABLE
105 snprintf(name
, sizeof(name
), "SVGA3D; %s %s %s", build
, mutex
, llvm
);
110 /** Helper for querying float-valued device cap */
112 get_float_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
115 SVGA3dDevCapResult result
;
116 if (sws
->get_cap(sws
, cap
, &result
))
123 /** Helper for querying uint-valued device cap */
125 get_uint_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
128 SVGA3dDevCapResult result
;
129 if (sws
->get_cap(sws
, cap
, &result
))
136 /** Helper for querying boolean-valued device cap */
138 get_bool_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
141 SVGA3dDevCapResult result
;
142 if (sws
->get_cap(sws
, cap
, &result
))
150 svga_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
152 struct svga_screen
*svgascreen
= svga_screen(screen
);
153 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
156 case PIPE_CAPF_MAX_LINE_WIDTH
:
157 return svgascreen
->maxLineWidth
;
158 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
159 return svgascreen
->maxLineWidthAA
;
161 case PIPE_CAPF_MAX_POINT_WIDTH
:
163 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
164 return svgascreen
->maxPointSize
;
166 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
167 return (float) get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY
, 4);
169 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
172 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
174 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
176 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
181 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param
);
187 svga_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
189 struct svga_screen
*svgascreen
= svga_screen(screen
);
190 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
191 SVGA3dDevCapResult result
;
194 case PIPE_CAP_NPOT_TEXTURES
:
195 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
196 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
198 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
200 * "In virtually every OpenGL implementation and hardware,
201 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
202 * http://www.opengl.org/wiki/Blending
204 return sws
->have_vgpu10
? 1 : 0;
205 case PIPE_CAP_ANISOTROPIC_FILTER
:
207 case PIPE_CAP_POINT_SPRITE
:
209 case PIPE_CAP_TGSI_TEXCOORD
:
211 case PIPE_CAP_MAX_RENDER_TARGETS
:
212 return svgascreen
->max_color_buffers
;
213 case PIPE_CAP_OCCLUSION_QUERY
:
215 case PIPE_CAP_QUERY_TIME_ELAPSED
:
217 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
218 return sws
->have_vgpu10
;
219 case PIPE_CAP_TEXTURE_SWIZZLE
:
221 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
223 case PIPE_CAP_USER_VERTEX_BUFFERS
:
225 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
228 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
230 unsigned size
= 1 << (SVGA_MAX_TEXTURE_LEVELS
- 1);
231 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH
, &result
))
232 size
= MIN2(result
.u
, size
);
235 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT
, &result
))
236 size
= MIN2(result
.u
, size
);
242 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
243 if (!sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT
, &result
))
244 return 8; /* max 128x128x128 */
245 return MIN2(util_logbase2(result
.u
) + 1, SVGA_MAX_TEXTURE_LEVELS
);
247 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
249 * No mechanism to query the host, and at least limited to 2048x2048 on
252 return MIN2(util_last_bit(screen
->get_param(screen
, PIPE_CAP_MAX_TEXTURE_2D_SIZE
)),
255 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
256 return sws
->have_sm5
? SVGA3D_SM5_MAX_SURFACE_ARRAYSIZE
:
257 (sws
->have_vgpu10
? SVGA3D_SM4_MAX_SURFACE_ARRAYSIZE
: 0);
259 case PIPE_CAP_BLEND_EQUATION_SEPARATE
: /* req. for GL 1.5 */
262 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
264 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
265 return sws
->have_vgpu10
;
266 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
268 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
269 return !sws
->have_vgpu10
;
271 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
272 return 1; /* The color outputs of vertex shaders are not clamped */
273 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
274 return sws
->have_vgpu10
;
275 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
276 return 0; /* The driver can't clamp fragment colors */
278 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
279 return 1; /* expected for GL_ARB_framebuffer_object */
281 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
284 } else if (sws
->have_vgpu10
) {
290 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
291 return sws
->have_sm5
? 410 : (sws
->have_vgpu10
? 330 : 120);
293 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
294 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
297 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
298 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
299 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
302 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
303 case PIPE_CAP_INDEP_BLEND_ENABLE
:
304 case PIPE_CAP_CONDITIONAL_RENDER
:
305 case PIPE_CAP_QUERY_TIMESTAMP
:
306 case PIPE_CAP_TGSI_INSTANCEID
:
307 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
308 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
309 case PIPE_CAP_FAKE_SW_MSAA
:
310 return sws
->have_vgpu10
;
312 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
313 return sws
->have_vgpu10
? SVGA3D_DX_MAX_SOTARGETS
: 0;
314 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
315 return sws
->have_vgpu10
? 4 : 0;
316 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
317 return sws
->have_sm5
? SVGA3D_MAX_STREAMOUT_DECLS
:
318 (sws
->have_vgpu10
? SVGA3D_MAX_DX10_STREAMOUT_DECLS
: 0);
319 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
320 return sws
->have_sm5
;
321 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
322 return sws
->have_sm5
;
323 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
324 return svgascreen
->ms_samples
? 1 : 0;
326 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
327 /* convert bytes to texels for the case of the largest texel
330 return SVGA3D_DX_MAX_RESOURCE_SIZE
/ (4 * sizeof(float));
332 case PIPE_CAP_MIN_TEXEL_OFFSET
:
333 return sws
->have_vgpu10
? VGPU10_MIN_TEXEL_FETCH_OFFSET
: 0;
334 case PIPE_CAP_MAX_TEXEL_OFFSET
:
335 return sws
->have_vgpu10
? VGPU10_MAX_TEXEL_FETCH_OFFSET
: 0;
337 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
338 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
341 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
342 return sws
->have_vgpu10
? 256 : 0;
343 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
344 return sws
->have_vgpu10
? 1024 : 0;
346 case PIPE_CAP_PRIMITIVE_RESTART
:
347 case PIPE_CAP_PRIMITIVE_RESTART_FIXED_INDEX
:
348 return 1; /* may be a sw fallback, depending on restart index */
350 case PIPE_CAP_GENERATE_MIPMAP
:
351 return sws
->have_generate_mipmap_cmd
;
353 case PIPE_CAP_NATIVE_FENCE_FD
:
354 return sws
->have_fence_fd
;
356 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
359 case PIPE_CAP_CUBE_MAP_ARRAY
:
360 case PIPE_CAP_INDEP_BLEND_FUNC
:
361 case PIPE_CAP_SAMPLE_SHADING
:
362 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
363 case PIPE_CAP_TEXTURE_QUERY_LOD
:
364 return sws
->have_sm4_1
;
366 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
367 /* SM4_1 supports only single-channel textures where as SM5 supports
368 * all four channel textures */
369 return sws
->have_sm5
? 4 :
370 (sws
->have_sm4_1
? 1 : 0);
371 case PIPE_CAP_DRAW_INDIRECT
:
372 return sws
->have_sm5
;
373 case PIPE_CAP_MAX_VERTEX_STREAMS
:
374 return sws
->have_sm5
? 4 : 0;
375 case PIPE_CAP_COMPUTE
:
377 case PIPE_CAP_MAX_VARYINGS
:
378 return sws
->have_vgpu10
? VGPU10_MAX_FS_INPUTS
: 10;
379 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
380 return sws
->have_coherent
;
382 /* Unsupported features */
383 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
384 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
385 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
386 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
387 case PIPE_CAP_TEXTURE_BARRIER
:
388 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
389 case PIPE_CAP_START_INSTANCE
:
390 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
391 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
392 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
393 case PIPE_CAP_TEXTURE_GATHER_SM5
:
394 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
395 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
396 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
397 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
398 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
399 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
400 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
401 case PIPE_CAP_CLIP_HALFZ
:
402 case PIPE_CAP_VERTEXID_NOBASE
:
403 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
404 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
405 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
406 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
407 case PIPE_CAP_INVALIDATE_BUFFER
:
408 case PIPE_CAP_STRING_MARKER
:
409 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
410 case PIPE_CAP_QUERY_MEMORY_INFO
:
411 case PIPE_CAP_PCI_GROUP
:
412 case PIPE_CAP_PCI_BUS
:
413 case PIPE_CAP_PCI_DEVICE
:
414 case PIPE_CAP_PCI_FUNCTION
:
415 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
416 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
417 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
418 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
419 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
420 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
421 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
422 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
424 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
426 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
427 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
428 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
429 return 1; /* need 4-byte alignment for all offsets and strides */
430 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
432 case PIPE_CAP_MAX_VIEWPORTS
:
433 assert((!sws
->have_vgpu10
&& svgascreen
->max_viewports
== 1) ||
435 svgascreen
->max_viewports
== SVGA3D_DX_MAX_VIEWPORTS
));
436 return svgascreen
->max_viewports
;
437 case PIPE_CAP_ENDIANNESS
:
438 return PIPE_ENDIAN_LITTLE
;
440 case PIPE_CAP_VENDOR_ID
:
441 return 0x15ad; /* VMware Inc. */
442 case PIPE_CAP_DEVICE_ID
:
443 return 0x0405; /* assume SVGA II */
444 case PIPE_CAP_ACCELERATED
:
446 case PIPE_CAP_VIDEO_MEMORY
:
447 /* XXX: Query the host ? */
449 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
450 return sws
->have_vgpu10
;
451 case PIPE_CAP_CLEAR_TEXTURE
:
452 return sws
->have_vgpu10
;
453 case PIPE_CAP_DOUBLES
:
454 return sws
->have_sm5
;
456 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
457 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
458 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
459 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
460 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
461 case PIPE_CAP_TGSI_TXQS
:
462 case PIPE_CAP_SHAREABLE_SHADERS
:
463 case PIPE_CAP_DRAW_PARAMETERS
:
464 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
465 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
466 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
467 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
468 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
469 case PIPE_CAP_CULL_DISTANCE
:
470 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
471 case PIPE_CAP_TGSI_VOTE
:
472 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
473 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
474 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
475 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
476 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
477 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
478 case PIPE_CAP_FBFETCH
:
479 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
481 case PIPE_CAP_INT64_DIVMOD
:
482 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
483 case PIPE_CAP_TGSI_CLOCK
:
484 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
485 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
486 case PIPE_CAP_TGSI_BALLOT
:
487 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
488 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
489 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
490 case PIPE_CAP_POST_DEPTH_COVERAGE
:
491 case PIPE_CAP_BINDLESS_TEXTURE
:
492 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
493 case PIPE_CAP_QUERY_SO_OVERFLOW
:
494 case PIPE_CAP_MEMOBJ
:
495 case PIPE_CAP_LOAD_CONSTBUF
:
496 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
497 case PIPE_CAP_TILE_RASTER_ORDER
:
498 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
499 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
500 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
501 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
502 case PIPE_CAP_FENCE_SIGNAL
:
503 case PIPE_CAP_CONSTBUF0_FLAGS
:
504 case PIPE_CAP_PACKED_UNIFORMS
:
505 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
507 case PIPE_CAP_TGSI_DIV
:
509 case PIPE_CAP_MAX_GS_INVOCATIONS
:
511 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
513 /* Verify this once protocol is finalized. Setting it to minimum value. */
514 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
515 return sws
->have_sm5
? 30 : 0;
517 return u_pipe_screen_get_param_defaults(screen
, param
);
523 vgpu9_get_shader_param(struct pipe_screen
*screen
,
524 enum pipe_shader_type shader
,
525 enum pipe_shader_cap param
)
527 struct svga_screen
*svgascreen
= svga_screen(screen
);
528 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
531 assert(!sws
->have_vgpu10
);
535 case PIPE_SHADER_FRAGMENT
:
538 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
539 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
540 return get_uint_cap(sws
,
541 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS
,
543 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
544 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
546 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
547 return SVGA3D_MAX_NESTING_LEVEL
;
548 case PIPE_SHADER_CAP_MAX_INPUTS
:
550 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
551 return svgascreen
->max_color_buffers
;
552 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
553 return 224 * sizeof(float[4]);
554 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
556 case PIPE_SHADER_CAP_MAX_TEMPS
:
557 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS
, 32);
558 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
559 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
561 * Although PS 3.0 has some addressing abilities it can only represent
562 * loops that can be statically determined and unrolled. Given we can
563 * only handle a subset of the cases that the gallium frontend already
564 * does it is better to defer loop unrolling to the gallium frontend.
567 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
569 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
571 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
572 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
573 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
575 case PIPE_SHADER_CAP_SUBROUTINES
:
577 case PIPE_SHADER_CAP_INT64_ATOMICS
:
578 case PIPE_SHADER_CAP_INTEGERS
:
580 case PIPE_SHADER_CAP_FP16
:
581 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
582 case PIPE_SHADER_CAP_INT16
:
584 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
585 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
587 case PIPE_SHADER_CAP_PREFERRED_IR
:
588 return PIPE_SHADER_IR_TGSI
;
589 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
591 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
592 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
593 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
594 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
595 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
596 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
597 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
598 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
599 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
600 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
601 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
603 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
606 /* If we get here, we failed to handle a cap above */
607 debug_printf("Unexpected fragment shader query %u\n", param
);
609 case PIPE_SHADER_VERTEX
:
612 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
613 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
614 return get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS
,
616 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
617 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
618 /* XXX: until we have vertex texture support */
620 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
621 return SVGA3D_MAX_NESTING_LEVEL
;
622 case PIPE_SHADER_CAP_MAX_INPUTS
:
624 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
626 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
627 return 256 * sizeof(float[4]);
628 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
630 case PIPE_SHADER_CAP_MAX_TEMPS
:
631 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS
, 32);
632 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
633 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
635 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
637 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
638 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
640 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
642 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
644 case PIPE_SHADER_CAP_SUBROUTINES
:
646 case PIPE_SHADER_CAP_INT64_ATOMICS
:
647 case PIPE_SHADER_CAP_INTEGERS
:
649 case PIPE_SHADER_CAP_FP16
:
650 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
651 case PIPE_SHADER_CAP_INT16
:
653 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
654 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
656 case PIPE_SHADER_CAP_PREFERRED_IR
:
657 return PIPE_SHADER_IR_TGSI
;
658 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
660 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
661 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
662 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
663 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
664 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
665 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
666 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
667 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
668 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
669 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
670 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
672 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
675 /* If we get here, we failed to handle a cap above */
676 debug_printf("Unexpected vertex shader query %u\n", param
);
678 case PIPE_SHADER_GEOMETRY
:
679 case PIPE_SHADER_COMPUTE
:
680 case PIPE_SHADER_TESS_CTRL
:
681 case PIPE_SHADER_TESS_EVAL
:
682 /* no support for geometry, tess or compute shaders at this time */
685 debug_printf("Unexpected shader type (%u) query\n", shader
);
693 vgpu10_get_shader_param(struct pipe_screen
*screen
,
694 enum pipe_shader_type shader
,
695 enum pipe_shader_cap param
)
697 struct svga_screen
*svgascreen
= svga_screen(screen
);
698 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
700 assert(sws
->have_vgpu10
);
701 (void) sws
; /* silence unused var warnings in non-debug builds */
703 if ((!sws
->have_sm5
) &&
704 (shader
== PIPE_SHADER_TESS_CTRL
|| shader
== PIPE_SHADER_TESS_EVAL
))
707 if (shader
== PIPE_SHADER_COMPUTE
)
710 /* NOTE: we do not query the device for any caps/limits at this time */
712 /* Generally the same limits for vertex, geometry and fragment shaders */
714 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
715 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
716 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
717 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
719 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
721 case PIPE_SHADER_CAP_MAX_INPUTS
:
722 if (shader
== PIPE_SHADER_FRAGMENT
)
723 return VGPU10_MAX_FS_INPUTS
;
724 else if (shader
== PIPE_SHADER_GEOMETRY
)
725 return VGPU10_MAX_GS_INPUTS
;
726 else if (shader
== PIPE_SHADER_TESS_CTRL
)
727 return VGPU11_MAX_HS_INPUT_CONTROL_POINTS
;
728 else if (shader
== PIPE_SHADER_TESS_EVAL
)
729 return VGPU11_MAX_DS_INPUT_CONTROL_POINTS
;
731 return VGPU10_MAX_VS_INPUTS
;
732 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
733 if (shader
== PIPE_SHADER_FRAGMENT
)
734 return VGPU10_MAX_FS_OUTPUTS
;
735 else if (shader
== PIPE_SHADER_GEOMETRY
)
736 return VGPU10_MAX_GS_OUTPUTS
;
737 else if (shader
== PIPE_SHADER_TESS_CTRL
)
738 return VGPU11_MAX_HS_OUTPUTS
;
739 else if (shader
== PIPE_SHADER_TESS_EVAL
)
740 return VGPU11_MAX_DS_OUTPUTS
;
742 return VGPU10_MAX_VS_OUTPUTS
;
743 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
744 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
* sizeof(float[4]);
745 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
746 return svgascreen
->max_const_buffers
;
747 case PIPE_SHADER_CAP_MAX_TEMPS
:
748 return VGPU10_MAX_TEMPS
;
749 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
750 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
751 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
752 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
753 return TRUE
; /* XXX verify */
754 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
755 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
756 case PIPE_SHADER_CAP_SUBROUTINES
:
757 case PIPE_SHADER_CAP_INTEGERS
:
759 case PIPE_SHADER_CAP_FP16
:
760 case PIPE_SHADER_CAP_FP16_DERIVATIVES
:
761 case PIPE_SHADER_CAP_INT16
:
763 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
764 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
765 return SVGA3D_DX_MAX_SAMPLERS
;
766 case PIPE_SHADER_CAP_PREFERRED_IR
:
767 return PIPE_SHADER_IR_TGSI
;
768 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
770 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
771 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
772 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
773 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
774 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
775 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
776 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
777 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
778 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
779 case PIPE_SHADER_CAP_INT64_ATOMICS
:
780 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
781 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
783 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
786 debug_printf("Unexpected vgpu10 shader query %u\n", param
);
794 svga_get_shader_param(struct pipe_screen
*screen
, enum pipe_shader_type shader
,
795 enum pipe_shader_cap param
)
797 struct svga_screen
*svgascreen
= svga_screen(screen
);
798 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
799 if (sws
->have_vgpu10
) {
800 return vgpu10_get_shader_param(screen
, shader
, param
);
803 return vgpu9_get_shader_param(screen
, shader
, param
);
809 svga_fence_reference(struct pipe_screen
*screen
,
810 struct pipe_fence_handle
**ptr
,
811 struct pipe_fence_handle
*fence
)
813 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
814 sws
->fence_reference(sws
, ptr
, fence
);
819 svga_fence_finish(struct pipe_screen
*screen
,
820 struct pipe_context
*ctx
,
821 struct pipe_fence_handle
*fence
,
824 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
827 SVGA_STATS_TIME_PUSH(sws
, SVGA_STATS_TIME_FENCEFINISH
);
830 retVal
= sws
->fence_signalled(sws
, fence
, 0) == 0;
833 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "%s fence_ptr %p\n",
834 __FUNCTION__
, fence
);
836 retVal
= sws
->fence_finish(sws
, fence
, timeout
, 0) == 0;
839 SVGA_STATS_TIME_POP(sws
);
846 svga_fence_get_fd(struct pipe_screen
*screen
,
847 struct pipe_fence_handle
*fence
)
849 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
851 return sws
->fence_get_fd(sws
, fence
, TRUE
);
856 svga_get_driver_query_info(struct pipe_screen
*screen
,
858 struct pipe_driver_query_info
*info
)
860 #define QUERY(NAME, ENUM, UNITS) \
861 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
863 static const struct pipe_driver_query_info queries
[] = {
864 /* per-frame counters */
865 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS
,
866 PIPE_DRIVER_QUERY_TYPE_UINT64
),
867 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS
,
868 PIPE_DRIVER_QUERY_TYPE_UINT64
),
869 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES
,
870 PIPE_DRIVER_QUERY_TYPE_UINT64
),
871 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS
,
872 PIPE_DRIVER_QUERY_TYPE_UINT64
),
873 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME
,
874 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
875 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED
,
876 PIPE_DRIVER_QUERY_TYPE_UINT64
),
877 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED
,
878 PIPE_DRIVER_QUERY_TYPE_UINT64
),
879 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED
,
880 PIPE_DRIVER_QUERY_TYPE_BYTES
),
881 QUERY("num-command-buffers", SVGA_QUERY_NUM_COMMAND_BUFFERS
,
882 PIPE_DRIVER_QUERY_TYPE_UINT64
),
883 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE
,
884 PIPE_DRIVER_QUERY_TYPE_BYTES
),
885 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME
,
886 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
887 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES
,
888 PIPE_DRIVER_QUERY_TYPE_UINT64
),
889 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS
,
890 PIPE_DRIVER_QUERY_TYPE_UINT64
),
891 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES
,
892 PIPE_DRIVER_QUERY_TYPE_UINT64
),
893 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS
,
894 PIPE_DRIVER_QUERY_TYPE_UINT64
),
895 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES
,
896 PIPE_DRIVER_QUERY_TYPE_UINT64
),
897 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES
,
898 PIPE_DRIVER_QUERY_TYPE_UINT64
),
899 QUERY("num-shader-relocations", SVGA_QUERY_NUM_SHADER_RELOCATIONS
,
900 PIPE_DRIVER_QUERY_TYPE_UINT64
),
901 QUERY("num-surface-relocations", SVGA_QUERY_NUM_SURFACE_RELOCATIONS
,
902 PIPE_DRIVER_QUERY_TYPE_UINT64
),
904 /* running total counters */
905 QUERY("memory-used", SVGA_QUERY_MEMORY_USED
,
906 PIPE_DRIVER_QUERY_TYPE_BYTES
),
907 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS
,
908 PIPE_DRIVER_QUERY_TYPE_UINT64
),
909 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES
,
910 PIPE_DRIVER_QUERY_TYPE_UINT64
),
911 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS
,
912 PIPE_DRIVER_QUERY_TYPE_UINT64
),
913 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS
,
914 PIPE_DRIVER_QUERY_TYPE_UINT64
),
915 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP
,
916 PIPE_DRIVER_QUERY_TYPE_UINT64
),
917 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS
,
918 PIPE_DRIVER_QUERY_TYPE_UINT64
),
919 QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW
,
920 PIPE_DRIVER_QUERY_TYPE_FLOAT
),
921 QUERY("shader-mem-used", SVGA_QUERY_SHADER_MEM_USED
,
922 PIPE_DRIVER_QUERY_TYPE_UINT64
),
927 return ARRAY_SIZE(queries
);
929 if (index
>= ARRAY_SIZE(queries
))
932 *info
= queries
[index
];
938 init_logging(struct pipe_screen
*screen
)
940 struct svga_screen
*svgascreen
= svga_screen(screen
);
941 static const char *log_prefix
= "Mesa: ";
944 /* Log Version to Host */
945 snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
946 "%s%s\n", log_prefix
, svga_get_name(screen
));
947 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
949 snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
950 "%s" PACKAGE_VERSION MESA_GIT_SHA1
, log_prefix
);
951 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
953 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
954 * line (program name and arguments).
956 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE
)) {
958 if (os_get_command_line(cmdline
, sizeof(cmdline
))) {
959 snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
960 "%s%s\n", log_prefix
, cmdline
);
961 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
968 * no-op logging function to use when SVGA_NO_LOGGING is set.
971 nop_host_log(struct svga_winsys_screen
*sws
, const char *message
)
978 svga_destroy_screen( struct pipe_screen
*screen
)
980 struct svga_screen
*svgascreen
= svga_screen(screen
);
982 svga_screen_cache_cleanup(svgascreen
);
984 mtx_destroy(&svgascreen
->swc_mutex
);
985 mtx_destroy(&svgascreen
->tex_mutex
);
987 svgascreen
->sws
->destroy(svgascreen
->sws
);
994 * Create a new svga_screen object
997 svga_screen_create(struct svga_winsys_screen
*sws
)
999 struct svga_screen
*svgascreen
;
1000 struct pipe_screen
*screen
;
1003 SVGA_DEBUG
= debug_get_flags_option("SVGA_DEBUG", svga_debug_flags
, 0 );
1006 svgascreen
= CALLOC_STRUCT(svga_screen
);
1010 svgascreen
->debug
.force_level_surface_view
=
1011 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE
);
1012 svgascreen
->debug
.force_surface_view
=
1013 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE
);
1014 svgascreen
->debug
.force_sampler_view
=
1015 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE
);
1016 svgascreen
->debug
.no_surface_view
=
1017 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE
);
1018 svgascreen
->debug
.no_sampler_view
=
1019 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE
);
1020 svgascreen
->debug
.no_cache_index_buffers
=
1021 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE
);
1023 screen
= &svgascreen
->screen
;
1025 screen
->destroy
= svga_destroy_screen
;
1026 screen
->get_name
= svga_get_name
;
1027 screen
->get_vendor
= svga_get_vendor
;
1028 screen
->get_device_vendor
= svga_get_vendor
; // TODO actual device vendor
1029 screen
->get_param
= svga_get_param
;
1030 screen
->get_shader_param
= svga_get_shader_param
;
1031 screen
->get_paramf
= svga_get_paramf
;
1032 screen
->get_timestamp
= NULL
;
1033 screen
->is_format_supported
= svga_is_format_supported
;
1034 screen
->context_create
= svga_context_create
;
1035 screen
->fence_reference
= svga_fence_reference
;
1036 screen
->fence_finish
= svga_fence_finish
;
1037 screen
->fence_get_fd
= svga_fence_get_fd
;
1039 screen
->get_driver_query_info
= svga_get_driver_query_info
;
1040 svgascreen
->sws
= sws
;
1042 svga_init_screen_resource_functions(svgascreen
);
1044 if (sws
->get_hw_version
) {
1045 svgascreen
->hw_version
= sws
->get_hw_version(sws
);
1047 svgascreen
->hw_version
= SVGA3D_HWVERSION_WS65_B1
;
1050 if (svgascreen
->hw_version
< SVGA3D_HWVERSION_WS8_B1
) {
1051 /* too old for 3D acceleration */
1052 debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
1053 svgascreen
->hw_version
);
1057 debug_printf("%s enabled\n",
1058 sws
->have_sm5
? "SM5" :
1059 sws
->have_sm4_1
? "SM4_1" :
1060 sws
->have_vgpu10
? "VGPU10" : "VGPU9");
1062 debug_printf("Mesa: %s %s (%s)\n", svga_get_name(screen
),
1063 PACKAGE_VERSION
, MESA_GIT_SHA1
);
1066 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1067 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
1068 * we prefer the later when available.
1070 * This mimics hardware vendors extensions for D3D depth sampling. See also
1071 * http://aras-p.info/texts/D3D9GPUHacks.html
1075 boolean has_df16
, has_df24
, has_d24s8_int
;
1076 SVGA3dSurfaceFormatCaps caps
;
1077 SVGA3dSurfaceFormatCaps mask
;
1082 svgascreen
->depth
.z16
= SVGA3D_Z_D16
;
1083 svgascreen
->depth
.x8z24
= SVGA3D_Z_D24X8
;
1084 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8
;
1086 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF16
, &caps
);
1087 has_df16
= (caps
.value
& mask
.value
) == mask
.value
;
1089 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF24
, &caps
);
1090 has_df24
= (caps
.value
& mask
.value
) == mask
.value
;
1092 svga_get_format_cap(svgascreen
, SVGA3D_Z_D24S8_INT
, &caps
);
1093 has_d24s8_int
= (caps
.value
& mask
.value
) == mask
.value
;
1095 /* XXX: We might want some other logic here.
1096 * Like if we only have d24s8_int we should
1097 * emulate the other formats with that.
1100 svgascreen
->depth
.z16
= SVGA3D_Z_DF16
;
1103 svgascreen
->depth
.x8z24
= SVGA3D_Z_DF24
;
1105 if (has_d24s8_int
) {
1106 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8_INT
;
1110 /* Query device caps
1112 if (sws
->have_vgpu10
) {
1113 svgascreen
->haveProvokingVertex
1114 = get_bool_cap(sws
, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX
, FALSE
);
1115 svgascreen
->haveLineSmooth
= TRUE
;
1116 svgascreen
->maxPointSize
= 80.0F
;
1117 svgascreen
->max_color_buffers
= SVGA3D_DX_MAX_RENDER_TARGETS
;
1119 /* Multisample samples per pixel */
1120 if (sws
->have_sm4_1
&& debug_get_bool_option("SVGA_MSAA", TRUE
)) {
1121 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_2X
, FALSE
))
1122 svgascreen
->ms_samples
|= 1 << 1;
1123 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_4X
, FALSE
))
1124 svgascreen
->ms_samples
|= 1 << 3;
1127 if (sws
->have_sm5
&& debug_get_bool_option("SVGA_MSAA", TRUE
)) {
1128 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_8X
, FALSE
))
1129 svgascreen
->ms_samples
|= 1 << 7;
1132 /* Maximum number of constant buffers */
1133 svgascreen
->max_const_buffers
=
1134 get_uint_cap(sws
, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS
, 1);
1135 svgascreen
->max_const_buffers
= MIN2(svgascreen
->max_const_buffers
,
1136 SVGA_MAX_CONST_BUFS
);
1138 svgascreen
->haveBlendLogicops
=
1139 get_bool_cap(sws
, SVGA3D_DEVCAP_LOGIC_BLENDOPS
, FALSE
);
1141 screen
->is_format_supported
= svga_is_dx_format_supported
;
1143 svgascreen
->max_viewports
= SVGA3D_DX_MAX_VIEWPORTS
;
1147 unsigned vs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION
,
1148 SVGA3DVSVERSION_NONE
);
1149 unsigned fs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION
,
1150 SVGA3DPSVERSION_NONE
);
1152 /* we require Shader model 3.0 or later */
1153 if (fs_ver
< SVGA3DPSVERSION_30
|| vs_ver
< SVGA3DVSVERSION_30
) {
1157 svgascreen
->haveProvokingVertex
= FALSE
;
1159 svgascreen
->haveLineSmooth
=
1160 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_AA
, FALSE
);
1162 svgascreen
->maxPointSize
=
1163 get_float_cap(sws
, SVGA3D_DEVCAP_MAX_POINT_SIZE
, 1.0f
);
1164 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1165 svgascreen
->maxPointSize
= MIN2(svgascreen
->maxPointSize
, 80.0f
);
1167 /* The SVGA3D device always supports 4 targets at this time, regardless
1168 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1170 svgascreen
->max_color_buffers
= 4;
1172 /* Only support one constant buffer
1174 svgascreen
->max_const_buffers
= 1;
1176 /* No multisampling */
1177 svgascreen
->ms_samples
= 0;
1179 /* Only one viewport */
1180 svgascreen
->max_viewports
= 1;
1183 /* common VGPU9 / VGPU10 caps */
1184 svgascreen
->haveLineStipple
=
1185 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_STIPPLE
, FALSE
);
1187 svgascreen
->maxLineWidth
=
1188 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_LINE_WIDTH
, 1.0f
));
1190 svgascreen
->maxLineWidthAA
=
1191 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH
, 1.0f
));
1194 debug_printf("svga: haveProvokingVertex %u\n",
1195 svgascreen
->haveProvokingVertex
);
1196 debug_printf("svga: haveLineStip %u "
1197 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1198 svgascreen
->haveLineStipple
, svgascreen
->haveLineSmooth
,
1199 svgascreen
->maxLineWidth
, svgascreen
->maxLineWidthAA
);
1200 debug_printf("svga: maxPointSize %g\n", svgascreen
->maxPointSize
);
1201 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen
->ms_samples
);
1204 (void) mtx_init(&svgascreen
->tex_mutex
, mtx_plain
);
1205 (void) mtx_init(&svgascreen
->swc_mutex
, mtx_recursive
);
1207 svga_screen_cache_init(svgascreen
);
1209 if (debug_get_bool_option("SVGA_NO_LOGGING", FALSE
) == TRUE
) {
1210 svgascreen
->sws
->host_log
= nop_host_log
;
1212 init_logging(screen
);
1223 struct svga_winsys_screen
*
1224 svga_winsys_screen(struct pipe_screen
*screen
)
1226 return svga_screen(screen
)->sws
;
1231 struct svga_screen
*
1232 svga_screen(struct pipe_screen
*screen
)
1235 assert(screen
->destroy
== svga_destroy_screen
);
1236 return (struct svga_screen
*)screen
;