1 /**********************************************************
2 * Copyright 2008-2009 VMware, Inc. All rights reserved.
4 * Permission is hereby granted, free of charge, to any person
5 * obtaining a copy of this software and associated documentation
6 * files (the "Software"), to deal in the Software without
7 * restriction, including without limitation the rights to use, copy,
8 * modify, merge, publish, distribute, sublicense, and/or sell copies
9 * of the Software, and to permit persons to whom the Software is
10 * furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice shall be
13 * included in all copies or substantial portions of the Software.
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
16 * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
18 * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
19 * BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
20 * ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 **********************************************************/
26 #include "git_sha1.h" /* For MESA_GIT_SHA1 */
27 #include "util/u_format.h"
28 #include "util/u_memory.h"
29 #include "util/u_inlines.h"
30 #include "util/u_screen.h"
31 #include "util/u_string.h"
32 #include "util/u_math.h"
34 #include "os/os_process.h"
36 #include "svga_winsys.h"
37 #include "svga_public.h"
38 #include "svga_context.h"
39 #include "svga_format.h"
40 #include "svga_screen.h"
41 #include "svga_tgsi.h"
42 #include "svga_resource_texture.h"
43 #include "svga_resource.h"
44 #include "svga_debug.h"
46 #include "svga3d_shaderdefs.h"
47 #include "VGPU10ShaderTokens.h"
49 /* NOTE: this constant may get moved into a svga3d*.h header file */
50 #define SVGA3D_DX_MAX_RESOURCE_SIZE (128 * 1024 * 1024)
55 static const struct debug_named_value svga_debug_flags
[] = {
56 { "dma", DEBUG_DMA
, NULL
},
57 { "tgsi", DEBUG_TGSI
, NULL
},
58 { "pipe", DEBUG_PIPE
, NULL
},
59 { "state", DEBUG_STATE
, NULL
},
60 { "screen", DEBUG_SCREEN
, NULL
},
61 { "tex", DEBUG_TEX
, NULL
},
62 { "swtnl", DEBUG_SWTNL
, NULL
},
63 { "const", DEBUG_CONSTS
, NULL
},
64 { "viewport", DEBUG_VIEWPORT
, NULL
},
65 { "views", DEBUG_VIEWS
, NULL
},
66 { "perf", DEBUG_PERF
, NULL
},
67 { "flush", DEBUG_FLUSH
, NULL
},
68 { "sync", DEBUG_SYNC
, NULL
},
69 { "cache", DEBUG_CACHE
, NULL
},
70 { "streamout", DEBUG_STREAMOUT
, NULL
},
71 { "query", DEBUG_QUERY
, NULL
},
72 { "samplers", DEBUG_SAMPLERS
, NULL
},
78 svga_get_vendor( struct pipe_screen
*pscreen
)
80 return "VMware, Inc.";
85 svga_get_name( struct pipe_screen
*pscreen
)
87 const char *build
= "", *llvm
= "", *mutex
= "";
88 static char name
[100];
90 /* Only return internal details in the DEBUG version:
92 build
= "build: DEBUG;";
93 mutex
= "mutex: " PIPE_ATOMIC
";";
95 build
= "build: RELEASE;";
101 snprintf(name
, sizeof(name
), "SVGA3D; %s %s %s", build
, mutex
, llvm
);
106 /** Helper for querying float-valued device cap */
108 get_float_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
111 SVGA3dDevCapResult result
;
112 if (sws
->get_cap(sws
, cap
, &result
))
119 /** Helper for querying uint-valued device cap */
121 get_uint_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
124 SVGA3dDevCapResult result
;
125 if (sws
->get_cap(sws
, cap
, &result
))
132 /** Helper for querying boolean-valued device cap */
134 get_bool_cap(struct svga_winsys_screen
*sws
, SVGA3dDevCapIndex cap
,
137 SVGA3dDevCapResult result
;
138 if (sws
->get_cap(sws
, cap
, &result
))
146 svga_get_paramf(struct pipe_screen
*screen
, enum pipe_capf param
)
148 struct svga_screen
*svgascreen
= svga_screen(screen
);
149 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
152 case PIPE_CAPF_MAX_LINE_WIDTH
:
153 return svgascreen
->maxLineWidth
;
154 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
155 return svgascreen
->maxLineWidthAA
;
157 case PIPE_CAPF_MAX_POINT_WIDTH
:
159 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
160 return svgascreen
->maxPointSize
;
162 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
163 return (float) get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_ANISOTROPY
, 4);
165 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
168 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
170 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
172 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
177 debug_printf("Unexpected PIPE_CAPF_ query %u\n", param
);
183 svga_get_param(struct pipe_screen
*screen
, enum pipe_cap param
)
185 struct svga_screen
*svgascreen
= svga_screen(screen
);
186 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
187 SVGA3dDevCapResult result
;
190 case PIPE_CAP_NPOT_TEXTURES
:
191 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
192 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
194 case PIPE_CAP_MAX_DUAL_SOURCE_RENDER_TARGETS
:
196 * "In virtually every OpenGL implementation and hardware,
197 * GL_MAX_DUAL_SOURCE_DRAW_BUFFERS is 1"
198 * http://www.opengl.org/wiki/Blending
200 return sws
->have_vgpu10
? 1 : 0;
201 case PIPE_CAP_ANISOTROPIC_FILTER
:
203 case PIPE_CAP_POINT_SPRITE
:
205 case PIPE_CAP_TGSI_TEXCOORD
:
207 case PIPE_CAP_MAX_RENDER_TARGETS
:
208 return svgascreen
->max_color_buffers
;
209 case PIPE_CAP_OCCLUSION_QUERY
:
211 case PIPE_CAP_QUERY_TIME_ELAPSED
:
213 case PIPE_CAP_TEXTURE_BUFFER_OBJECTS
:
214 return sws
->have_vgpu10
;
215 case PIPE_CAP_TEXTURE_SWIZZLE
:
217 case PIPE_CAP_TEXTURE_BORDER_COLOR_QUIRK
:
219 case PIPE_CAP_USER_VERTEX_BUFFERS
:
221 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
224 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
226 unsigned size
= 1 << (SVGA_MAX_TEXTURE_LEVELS
- 1);
227 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_WIDTH
, &result
))
228 size
= MIN2(result
.u
, size
);
231 if (sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_TEXTURE_HEIGHT
, &result
))
232 size
= MIN2(result
.u
, size
);
238 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
239 if (!sws
->get_cap(sws
, SVGA3D_DEVCAP_MAX_VOLUME_EXTENT
, &result
))
240 return 8; /* max 128x128x128 */
241 return MIN2(util_logbase2(result
.u
) + 1, SVGA_MAX_TEXTURE_LEVELS
);
243 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
245 * No mechanism to query the host, and at least limited to 2048x2048 on
248 return MIN2(util_last_bit(screen
->get_param(screen
, PIPE_CAP_MAX_TEXTURE_2D_SIZE
)),
251 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
252 return sws
->have_vgpu10
? SVGA3D_MAX_SURFACE_ARRAYSIZE
: 0;
254 case PIPE_CAP_BLEND_EQUATION_SEPARATE
: /* req. for GL 1.5 */
257 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
259 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
260 return sws
->have_vgpu10
;
261 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
263 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
264 return !sws
->have_vgpu10
;
266 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
267 return 1; /* The color outputs of vertex shaders are not clamped */
268 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
269 return 0; /* The driver can't clamp vertex colors */
270 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
271 return 0; /* The driver can't clamp fragment colors */
273 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
274 return 1; /* expected for GL_ARB_framebuffer_object */
276 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
277 return sws
->have_vgpu10
? 330 : 120;
279 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
280 return sws
->have_vgpu10
? 330 : 120;
282 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
283 case PIPE_CAP_DEPTH_CLIP_DISABLE_SEPARATE
:
286 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
287 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
288 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
291 case PIPE_CAP_DEPTH_CLIP_DISABLE
:
292 case PIPE_CAP_INDEP_BLEND_ENABLE
:
293 case PIPE_CAP_CONDITIONAL_RENDER
:
294 case PIPE_CAP_QUERY_TIMESTAMP
:
295 case PIPE_CAP_TGSI_INSTANCEID
:
296 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
297 case PIPE_CAP_SEAMLESS_CUBE_MAP
:
298 case PIPE_CAP_FAKE_SW_MSAA
:
299 return sws
->have_vgpu10
;
301 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
302 return sws
->have_vgpu10
? SVGA3D_DX_MAX_SOTARGETS
: 0;
303 case PIPE_CAP_MAX_STREAM_OUTPUT_SEPARATE_COMPONENTS
:
304 return sws
->have_vgpu10
? 4 : 0;
305 case PIPE_CAP_MAX_STREAM_OUTPUT_INTERLEAVED_COMPONENTS
:
306 return sws
->have_vgpu10
? SVGA3D_MAX_STREAMOUT_DECLS
: 0;
307 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
308 case PIPE_CAP_STREAM_OUTPUT_INTERLEAVE_BUFFERS
:
310 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
311 return svgascreen
->ms_samples
? 1 : 0;
313 case PIPE_CAP_MAX_TEXTURE_BUFFER_SIZE
:
314 /* convert bytes to texels for the case of the largest texel
317 return SVGA3D_DX_MAX_RESOURCE_SIZE
/ (4 * sizeof(float));
319 case PIPE_CAP_MIN_TEXEL_OFFSET
:
320 return sws
->have_vgpu10
? VGPU10_MIN_TEXEL_FETCH_OFFSET
: 0;
321 case PIPE_CAP_MAX_TEXEL_OFFSET
:
322 return sws
->have_vgpu10
? VGPU10_MAX_TEXEL_FETCH_OFFSET
: 0;
324 case PIPE_CAP_MIN_TEXTURE_GATHER_OFFSET
:
325 case PIPE_CAP_MAX_TEXTURE_GATHER_OFFSET
:
328 case PIPE_CAP_MAX_GEOMETRY_OUTPUT_VERTICES
:
329 return sws
->have_vgpu10
? 256 : 0;
330 case PIPE_CAP_MAX_GEOMETRY_TOTAL_OUTPUT_COMPONENTS
:
331 return sws
->have_vgpu10
? 1024 : 0;
333 case PIPE_CAP_PRIMITIVE_RESTART
:
334 return 1; /* may be a sw fallback, depending on restart index */
336 case PIPE_CAP_GENERATE_MIPMAP
:
337 return sws
->have_generate_mipmap_cmd
;
339 case PIPE_CAP_NATIVE_FENCE_FD
:
340 return sws
->have_fence_fd
;
342 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
345 case PIPE_CAP_CUBE_MAP_ARRAY
:
346 case PIPE_CAP_INDEP_BLEND_FUNC
:
347 case PIPE_CAP_SAMPLE_SHADING
:
348 case PIPE_CAP_FORCE_PERSAMPLE_INTERP
:
349 case PIPE_CAP_TEXTURE_QUERY_LOD
:
350 return sws
->have_sm4_1
;
352 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
353 return sws
->have_sm4_1
? 1 : 0; /* only single-channel textures */
354 case PIPE_CAP_MAX_VARYINGS
:
355 return sws
->have_vgpu10
? VGPU10_MAX_FS_INPUTS
: 10;
356 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
357 return sws
->have_coherent
;
359 /* Unsupported features */
360 case PIPE_CAP_TEXTURE_MIRROR_CLAMP
:
361 case PIPE_CAP_TEXTURE_MIRROR_CLAMP_TO_EDGE
:
362 case PIPE_CAP_SHADER_STENCIL_EXPORT
:
363 case PIPE_CAP_SEAMLESS_CUBE_MAP_PER_TEXTURE
:
364 case PIPE_CAP_TEXTURE_BARRIER
:
365 case PIPE_CAP_MAX_VERTEX_STREAMS
:
366 case PIPE_CAP_TGSI_CAN_COMPACT_CONSTANTS
:
367 case PIPE_CAP_COMPUTE
:
368 case PIPE_CAP_START_INSTANCE
:
369 case PIPE_CAP_TEXTURE_BUFFER_OFFSET_ALIGNMENT
:
370 case PIPE_CAP_QUERY_PIPELINE_STATISTICS
:
371 case PIPE_CAP_TGSI_VS_LAYER_VIEWPORT
:
372 case PIPE_CAP_TEXTURE_GATHER_SM5
:
373 case PIPE_CAP_TEXTURE_GATHER_OFFSETS
:
374 case PIPE_CAP_TGSI_VS_WINDOW_SPACE_POSITION
:
375 case PIPE_CAP_DRAW_INDIRECT
:
376 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
377 case PIPE_CAP_MULTI_DRAW_INDIRECT_PARAMS
:
378 case PIPE_CAP_TGSI_FS_FINE_DERIVATIVE
:
379 case PIPE_CAP_CONDITIONAL_RENDER_INVERTED
:
380 case PIPE_CAP_SAMPLER_VIEW_TARGET
:
381 case PIPE_CAP_CLIP_HALFZ
:
382 case PIPE_CAP_VERTEXID_NOBASE
:
383 case PIPE_CAP_POLYGON_OFFSET_CLAMP
:
384 case PIPE_CAP_MULTISAMPLE_Z_RESOLVE
:
385 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
386 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
387 case PIPE_CAP_INVALIDATE_BUFFER
:
388 case PIPE_CAP_STRING_MARKER
:
389 case PIPE_CAP_SURFACE_REINTERPRET_BLOCKS
:
390 case PIPE_CAP_QUERY_MEMORY_INFO
:
391 case PIPE_CAP_PCI_GROUP
:
392 case PIPE_CAP_PCI_BUS
:
393 case PIPE_CAP_PCI_DEVICE
:
394 case PIPE_CAP_PCI_FUNCTION
:
395 case PIPE_CAP_ROBUST_BUFFER_ACCESS_BEHAVIOR
:
396 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_TRIANGLES
:
397 case PIPE_CAP_CONSERVATIVE_RASTER_POST_SNAP_POINTS_LINES
:
398 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_TRIANGLES
:
399 case PIPE_CAP_CONSERVATIVE_RASTER_PRE_SNAP_POINTS_LINES
:
400 case PIPE_CAP_CONSERVATIVE_RASTER_POST_DEPTH_COVERAGE
:
401 case PIPE_CAP_MAX_CONSERVATIVE_RASTER_SUBPIXEL_PRECISION_BIAS
:
402 case PIPE_CAP_MAX_TEXTURE_UPLOAD_MEMORY_BUDGET
:
404 case PIPE_CAP_MIN_MAP_BUFFER_ALIGNMENT
:
406 case PIPE_CAP_VERTEX_BUFFER_STRIDE_4BYTE_ALIGNED_ONLY
:
407 case PIPE_CAP_VERTEX_BUFFER_OFFSET_4BYTE_ALIGNED_ONLY
:
408 case PIPE_CAP_VERTEX_ELEMENT_SRC_OFFSET_4BYTE_ALIGNED_ONLY
:
409 return 1; /* need 4-byte alignment for all offsets and strides */
410 case PIPE_CAP_MAX_VERTEX_ATTRIB_STRIDE
:
412 case PIPE_CAP_MAX_VIEWPORTS
:
414 case PIPE_CAP_ENDIANNESS
:
415 return PIPE_ENDIAN_LITTLE
;
417 case PIPE_CAP_VENDOR_ID
:
418 return 0x15ad; /* VMware Inc. */
419 case PIPE_CAP_DEVICE_ID
:
420 return 0x0405; /* assume SVGA II */
421 case PIPE_CAP_ACCELERATED
:
423 case PIPE_CAP_VIDEO_MEMORY
:
424 /* XXX: Query the host ? */
426 case PIPE_CAP_COPY_BETWEEN_COMPRESSED_AND_PLAIN_FORMATS
:
427 return sws
->have_vgpu10
;
428 case PIPE_CAP_CLEAR_TEXTURE
:
429 return sws
->have_vgpu10
;
431 case PIPE_CAP_RESOURCE_FROM_USER_MEMORY
:
432 case PIPE_CAP_DEVICE_RESET_STATUS_QUERY
:
433 case PIPE_CAP_MAX_SHADER_PATCH_VARYINGS
:
434 case PIPE_CAP_TEXTURE_FLOAT_LINEAR
:
435 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
436 case PIPE_CAP_DEPTH_BOUNDS_TEST
:
437 case PIPE_CAP_TGSI_TXQS
:
438 case PIPE_CAP_SHAREABLE_SHADERS
:
439 case PIPE_CAP_DRAW_PARAMETERS
:
440 case PIPE_CAP_TGSI_FS_POSITION_IS_SYSVAL
:
441 case PIPE_CAP_TGSI_FS_FACE_IS_INTEGER_SYSVAL
:
442 case PIPE_CAP_BUFFER_SAMPLER_VIEW_RGBA_ONLY
:
443 case PIPE_CAP_QUERY_BUFFER_OBJECT
:
444 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
445 case PIPE_CAP_CULL_DISTANCE
:
446 case PIPE_CAP_PRIMITIVE_RESTART_FOR_PATCHES
:
447 case PIPE_CAP_TGSI_VOTE
:
448 case PIPE_CAP_MAX_WINDOW_RECTANGLES
:
449 case PIPE_CAP_POLYGON_OFFSET_UNITS_UNSCALED
:
450 case PIPE_CAP_VIEWPORT_SUBPIXEL_BITS
:
451 case PIPE_CAP_TGSI_ARRAY_COMPONENTS
:
452 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
453 case PIPE_CAP_GLSL_OPTIMIZE_CONSERVATIVELY
:
454 case PIPE_CAP_FBFETCH
:
455 case PIPE_CAP_TGSI_MUL_ZERO_WINS
:
456 case PIPE_CAP_DOUBLES
:
458 case PIPE_CAP_INT64_DIVMOD
:
459 case PIPE_CAP_TGSI_TEX_TXF_LZ
:
460 case PIPE_CAP_TGSI_CLOCK
:
461 case PIPE_CAP_POLYGON_MODE_FILL_RECTANGLE
:
462 case PIPE_CAP_SPARSE_BUFFER_PAGE_SIZE
:
463 case PIPE_CAP_TGSI_BALLOT
:
464 case PIPE_CAP_TGSI_TES_LAYER_VIEWPORT
:
465 case PIPE_CAP_CAN_BIND_CONST_BUFFER_AS_VERTEX
:
466 case PIPE_CAP_ALLOW_MAPPED_BUFFERS_DURING_EXECUTION
:
467 case PIPE_CAP_POST_DEPTH_COVERAGE
:
468 case PIPE_CAP_BINDLESS_TEXTURE
:
469 case PIPE_CAP_NIR_SAMPLERS_AS_DEREF
:
470 case PIPE_CAP_QUERY_SO_OVERFLOW
:
471 case PIPE_CAP_MEMOBJ
:
472 case PIPE_CAP_LOAD_CONSTBUF
:
473 case PIPE_CAP_TGSI_ANY_REG_AS_ADDRESS
:
474 case PIPE_CAP_TILE_RASTER_ORDER
:
475 case PIPE_CAP_MAX_COMBINED_SHADER_OUTPUT_RESOURCES
:
476 case PIPE_CAP_FRAMEBUFFER_MSAA_CONSTRAINTS
:
477 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
478 case PIPE_CAP_CONTEXT_PRIORITY_MASK
:
479 case PIPE_CAP_FENCE_SIGNAL
:
480 case PIPE_CAP_CONSTBUF0_FLAGS
:
481 case PIPE_CAP_PACKED_UNIFORMS
:
482 case PIPE_CAP_PROGRAMMABLE_SAMPLE_LOCATIONS
:
484 case PIPE_CAP_TGSI_DIV
:
486 case PIPE_CAP_MAX_GS_INVOCATIONS
:
488 case PIPE_CAP_MAX_SHADER_BUFFER_SIZE
:
491 return u_pipe_screen_get_param_defaults(screen
, param
);
497 vgpu9_get_shader_param(struct pipe_screen
*screen
,
498 enum pipe_shader_type shader
,
499 enum pipe_shader_cap param
)
501 struct svga_screen
*svgascreen
= svga_screen(screen
);
502 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
505 assert(!sws
->have_vgpu10
);
509 case PIPE_SHADER_FRAGMENT
:
512 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
513 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
514 return get_uint_cap(sws
,
515 SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_INSTRUCTIONS
,
517 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
518 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
520 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
521 return SVGA3D_MAX_NESTING_LEVEL
;
522 case PIPE_SHADER_CAP_MAX_INPUTS
:
524 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
525 return svgascreen
->max_color_buffers
;
526 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
527 return 224 * sizeof(float[4]);
528 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
530 case PIPE_SHADER_CAP_MAX_TEMPS
:
531 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_FRAGMENT_SHADER_TEMPS
, 32);
532 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
533 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
535 * Although PS 3.0 has some addressing abilities it can only represent
536 * loops that can be statically determined and unrolled. Given we can
537 * only handle a subset of the cases that the state tracker already
538 * does it is better to defer loop unrolling to the state tracker.
541 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
543 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
545 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
546 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
547 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
549 case PIPE_SHADER_CAP_SUBROUTINES
:
551 case PIPE_SHADER_CAP_INT64_ATOMICS
:
552 case PIPE_SHADER_CAP_INTEGERS
:
554 case PIPE_SHADER_CAP_FP16
:
556 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
557 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
559 case PIPE_SHADER_CAP_PREFERRED_IR
:
560 return PIPE_SHADER_IR_TGSI
;
561 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
563 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
564 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
565 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
566 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
567 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
568 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
569 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
570 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
571 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
572 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
573 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
575 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
578 /* If we get here, we failed to handle a cap above */
579 debug_printf("Unexpected fragment shader query %u\n", param
);
581 case PIPE_SHADER_VERTEX
:
584 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
585 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
586 return get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_INSTRUCTIONS
,
588 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
589 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
590 /* XXX: until we have vertex texture support */
592 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
593 return SVGA3D_MAX_NESTING_LEVEL
;
594 case PIPE_SHADER_CAP_MAX_INPUTS
:
596 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
598 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
599 return 256 * sizeof(float[4]);
600 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
602 case PIPE_SHADER_CAP_MAX_TEMPS
:
603 val
= get_uint_cap(sws
, SVGA3D_DEVCAP_MAX_VERTEX_SHADER_TEMPS
, 32);
604 return MIN2(val
, SVGA3D_TEMPREG_MAX
);
605 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
607 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
609 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
610 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
612 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
614 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
616 case PIPE_SHADER_CAP_SUBROUTINES
:
618 case PIPE_SHADER_CAP_INT64_ATOMICS
:
619 case PIPE_SHADER_CAP_INTEGERS
:
621 case PIPE_SHADER_CAP_FP16
:
623 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
624 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
626 case PIPE_SHADER_CAP_PREFERRED_IR
:
627 return PIPE_SHADER_IR_TGSI
;
628 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
630 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
631 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
632 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
633 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
634 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
635 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
636 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
637 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
638 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
639 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
640 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
642 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
645 /* If we get here, we failed to handle a cap above */
646 debug_printf("Unexpected vertex shader query %u\n", param
);
648 case PIPE_SHADER_GEOMETRY
:
649 case PIPE_SHADER_COMPUTE
:
650 case PIPE_SHADER_TESS_CTRL
:
651 case PIPE_SHADER_TESS_EVAL
:
652 /* no support for geometry, tess or compute shaders at this time */
655 debug_printf("Unexpected shader type (%u) query\n", shader
);
663 vgpu10_get_shader_param(struct pipe_screen
*screen
,
664 enum pipe_shader_type shader
,
665 enum pipe_shader_cap param
)
667 struct svga_screen
*svgascreen
= svga_screen(screen
);
668 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
670 assert(sws
->have_vgpu10
);
671 (void) sws
; /* silence unused var warnings in non-debug builds */
673 /* Only VS, GS, FS supported */
674 if (shader
!= PIPE_SHADER_VERTEX
&&
675 shader
!= PIPE_SHADER_GEOMETRY
&&
676 shader
!= PIPE_SHADER_FRAGMENT
) {
680 /* NOTE: we do not query the device for any caps/limits at this time */
682 /* Generally the same limits for vertex, geometry and fragment shaders */
684 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
685 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
686 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
687 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
689 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
691 case PIPE_SHADER_CAP_MAX_INPUTS
:
692 if (shader
== PIPE_SHADER_FRAGMENT
)
693 return VGPU10_MAX_FS_INPUTS
;
694 else if (shader
== PIPE_SHADER_GEOMETRY
)
695 return VGPU10_MAX_GS_INPUTS
;
697 return VGPU10_MAX_VS_INPUTS
;
698 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
699 if (shader
== PIPE_SHADER_FRAGMENT
)
700 return VGPU10_MAX_FS_OUTPUTS
;
701 else if (shader
== PIPE_SHADER_GEOMETRY
)
702 return VGPU10_MAX_GS_OUTPUTS
;
704 return VGPU10_MAX_VS_OUTPUTS
;
705 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
706 return VGPU10_MAX_CONSTANT_BUFFER_ELEMENT_COUNT
* sizeof(float[4]);
707 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
708 return svgascreen
->max_const_buffers
;
709 case PIPE_SHADER_CAP_MAX_TEMPS
:
710 return VGPU10_MAX_TEMPS
;
711 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
712 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
713 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
714 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
715 return TRUE
; /* XXX verify */
716 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
717 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
718 case PIPE_SHADER_CAP_SUBROUTINES
:
719 case PIPE_SHADER_CAP_INTEGERS
:
721 case PIPE_SHADER_CAP_FP16
:
723 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
724 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
725 return SVGA3D_DX_MAX_SAMPLERS
;
726 case PIPE_SHADER_CAP_PREFERRED_IR
:
727 return PIPE_SHADER_IR_TGSI
;
728 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
730 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
731 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
732 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
733 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
734 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
735 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
736 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
737 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
738 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
739 case PIPE_SHADER_CAP_INT64_ATOMICS
:
740 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
741 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
743 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
746 debug_printf("Unexpected vgpu10 shader query %u\n", param
);
754 svga_get_shader_param(struct pipe_screen
*screen
, enum pipe_shader_type shader
,
755 enum pipe_shader_cap param
)
757 struct svga_screen
*svgascreen
= svga_screen(screen
);
758 struct svga_winsys_screen
*sws
= svgascreen
->sws
;
759 if (sws
->have_vgpu10
) {
760 return vgpu10_get_shader_param(screen
, shader
, param
);
763 return vgpu9_get_shader_param(screen
, shader
, param
);
769 svga_fence_reference(struct pipe_screen
*screen
,
770 struct pipe_fence_handle
**ptr
,
771 struct pipe_fence_handle
*fence
)
773 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
774 sws
->fence_reference(sws
, ptr
, fence
);
779 svga_fence_finish(struct pipe_screen
*screen
,
780 struct pipe_context
*ctx
,
781 struct pipe_fence_handle
*fence
,
784 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
787 SVGA_STATS_TIME_PUSH(sws
, SVGA_STATS_TIME_FENCEFINISH
);
790 retVal
= sws
->fence_signalled(sws
, fence
, 0) == 0;
793 SVGA_DBG(DEBUG_DMA
|DEBUG_PERF
, "%s fence_ptr %p\n",
794 __FUNCTION__
, fence
);
796 retVal
= sws
->fence_finish(sws
, fence
, timeout
, 0) == 0;
799 SVGA_STATS_TIME_POP(sws
);
806 svga_fence_get_fd(struct pipe_screen
*screen
,
807 struct pipe_fence_handle
*fence
)
809 struct svga_winsys_screen
*sws
= svga_screen(screen
)->sws
;
811 return sws
->fence_get_fd(sws
, fence
, TRUE
);
816 svga_get_driver_query_info(struct pipe_screen
*screen
,
818 struct pipe_driver_query_info
*info
)
820 #define QUERY(NAME, ENUM, UNITS) \
821 {NAME, ENUM, {0}, UNITS, PIPE_DRIVER_QUERY_RESULT_TYPE_AVERAGE, 0, 0x0}
823 static const struct pipe_driver_query_info queries
[] = {
824 /* per-frame counters */
825 QUERY("num-draw-calls", SVGA_QUERY_NUM_DRAW_CALLS
,
826 PIPE_DRIVER_QUERY_TYPE_UINT64
),
827 QUERY("num-fallbacks", SVGA_QUERY_NUM_FALLBACKS
,
828 PIPE_DRIVER_QUERY_TYPE_UINT64
),
829 QUERY("num-flushes", SVGA_QUERY_NUM_FLUSHES
,
830 PIPE_DRIVER_QUERY_TYPE_UINT64
),
831 QUERY("num-validations", SVGA_QUERY_NUM_VALIDATIONS
,
832 PIPE_DRIVER_QUERY_TYPE_UINT64
),
833 QUERY("map-buffer-time", SVGA_QUERY_MAP_BUFFER_TIME
,
834 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
835 QUERY("num-buffers-mapped", SVGA_QUERY_NUM_BUFFERS_MAPPED
,
836 PIPE_DRIVER_QUERY_TYPE_UINT64
),
837 QUERY("num-textures-mapped", SVGA_QUERY_NUM_TEXTURES_MAPPED
,
838 PIPE_DRIVER_QUERY_TYPE_UINT64
),
839 QUERY("num-bytes-uploaded", SVGA_QUERY_NUM_BYTES_UPLOADED
,
840 PIPE_DRIVER_QUERY_TYPE_BYTES
),
841 QUERY("command-buffer-size", SVGA_QUERY_COMMAND_BUFFER_SIZE
,
842 PIPE_DRIVER_QUERY_TYPE_BYTES
),
843 QUERY("flush-time", SVGA_QUERY_FLUSH_TIME
,
844 PIPE_DRIVER_QUERY_TYPE_MICROSECONDS
),
845 QUERY("surface-write-flushes", SVGA_QUERY_SURFACE_WRITE_FLUSHES
,
846 PIPE_DRIVER_QUERY_TYPE_UINT64
),
847 QUERY("num-readbacks", SVGA_QUERY_NUM_READBACKS
,
848 PIPE_DRIVER_QUERY_TYPE_UINT64
),
849 QUERY("num-resource-updates", SVGA_QUERY_NUM_RESOURCE_UPDATES
,
850 PIPE_DRIVER_QUERY_TYPE_UINT64
),
851 QUERY("num-buffer-uploads", SVGA_QUERY_NUM_BUFFER_UPLOADS
,
852 PIPE_DRIVER_QUERY_TYPE_UINT64
),
853 QUERY("num-const-buf-updates", SVGA_QUERY_NUM_CONST_BUF_UPDATES
,
854 PIPE_DRIVER_QUERY_TYPE_UINT64
),
855 QUERY("num-const-updates", SVGA_QUERY_NUM_CONST_UPDATES
,
856 PIPE_DRIVER_QUERY_TYPE_UINT64
),
858 /* running total counters */
859 QUERY("memory-used", SVGA_QUERY_MEMORY_USED
,
860 PIPE_DRIVER_QUERY_TYPE_BYTES
),
861 QUERY("num-shaders", SVGA_QUERY_NUM_SHADERS
,
862 PIPE_DRIVER_QUERY_TYPE_UINT64
),
863 QUERY("num-resources", SVGA_QUERY_NUM_RESOURCES
,
864 PIPE_DRIVER_QUERY_TYPE_UINT64
),
865 QUERY("num-state-objects", SVGA_QUERY_NUM_STATE_OBJECTS
,
866 PIPE_DRIVER_QUERY_TYPE_UINT64
),
867 QUERY("num-surface-views", SVGA_QUERY_NUM_SURFACE_VIEWS
,
868 PIPE_DRIVER_QUERY_TYPE_UINT64
),
869 QUERY("num-generate-mipmap", SVGA_QUERY_NUM_GENERATE_MIPMAP
,
870 PIPE_DRIVER_QUERY_TYPE_UINT64
),
871 QUERY("num-failed-allocations", SVGA_QUERY_NUM_FAILED_ALLOCATIONS
,
872 PIPE_DRIVER_QUERY_TYPE_UINT64
),
873 QUERY("num-commands-per-draw", SVGA_QUERY_NUM_COMMANDS_PER_DRAW
,
874 PIPE_DRIVER_QUERY_TYPE_FLOAT
),
879 return ARRAY_SIZE(queries
);
881 if (index
>= ARRAY_SIZE(queries
))
884 *info
= queries
[index
];
890 init_logging(struct pipe_screen
*screen
)
892 struct svga_screen
*svgascreen
= svga_screen(screen
);
893 static const char *log_prefix
= "Mesa: ";
896 /* Log Version to Host */
897 snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
898 "%s%s\n", log_prefix
, svga_get_name(screen
));
899 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
901 snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
902 "%s" PACKAGE_VERSION MESA_GIT_SHA1
, log_prefix
);
903 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
905 /* If the SVGA_EXTRA_LOGGING env var is set, log the process's command
906 * line (program name and arguments).
908 if (debug_get_bool_option("SVGA_EXTRA_LOGGING", FALSE
)) {
910 if (os_get_command_line(cmdline
, sizeof(cmdline
))) {
911 snprintf(host_log
, sizeof(host_log
) - strlen(log_prefix
),
912 "%s%s\n", log_prefix
, cmdline
);
913 svgascreen
->sws
->host_log(svgascreen
->sws
, host_log
);
920 * no-op logging function to use when SVGA_NO_LOGGING is set.
923 nop_host_log(struct svga_winsys_screen
*sws
, const char *message
)
930 svga_destroy_screen( struct pipe_screen
*screen
)
932 struct svga_screen
*svgascreen
= svga_screen(screen
);
934 svga_screen_cache_cleanup(svgascreen
);
936 mtx_destroy(&svgascreen
->swc_mutex
);
937 mtx_destroy(&svgascreen
->tex_mutex
);
939 svgascreen
->sws
->destroy(svgascreen
->sws
);
946 * Create a new svga_screen object
949 svga_screen_create(struct svga_winsys_screen
*sws
)
951 struct svga_screen
*svgascreen
;
952 struct pipe_screen
*screen
;
955 SVGA_DEBUG
= debug_get_flags_option("SVGA_DEBUG", svga_debug_flags
, 0 );
958 svgascreen
= CALLOC_STRUCT(svga_screen
);
962 svgascreen
->debug
.force_level_surface_view
=
963 debug_get_bool_option("SVGA_FORCE_LEVEL_SURFACE_VIEW", FALSE
);
964 svgascreen
->debug
.force_surface_view
=
965 debug_get_bool_option("SVGA_FORCE_SURFACE_VIEW", FALSE
);
966 svgascreen
->debug
.force_sampler_view
=
967 debug_get_bool_option("SVGA_FORCE_SAMPLER_VIEW", FALSE
);
968 svgascreen
->debug
.no_surface_view
=
969 debug_get_bool_option("SVGA_NO_SURFACE_VIEW", FALSE
);
970 svgascreen
->debug
.no_sampler_view
=
971 debug_get_bool_option("SVGA_NO_SAMPLER_VIEW", FALSE
);
972 svgascreen
->debug
.no_cache_index_buffers
=
973 debug_get_bool_option("SVGA_NO_CACHE_INDEX_BUFFERS", FALSE
);
975 screen
= &svgascreen
->screen
;
977 screen
->destroy
= svga_destroy_screen
;
978 screen
->get_name
= svga_get_name
;
979 screen
->get_vendor
= svga_get_vendor
;
980 screen
->get_device_vendor
= svga_get_vendor
; // TODO actual device vendor
981 screen
->get_param
= svga_get_param
;
982 screen
->get_shader_param
= svga_get_shader_param
;
983 screen
->get_paramf
= svga_get_paramf
;
984 screen
->get_timestamp
= NULL
;
985 screen
->is_format_supported
= svga_is_format_supported
;
986 screen
->context_create
= svga_context_create
;
987 screen
->fence_reference
= svga_fence_reference
;
988 screen
->fence_finish
= svga_fence_finish
;
989 screen
->fence_get_fd
= svga_fence_get_fd
;
991 screen
->get_driver_query_info
= svga_get_driver_query_info
;
992 svgascreen
->sws
= sws
;
994 svga_init_screen_resource_functions(svgascreen
);
996 if (sws
->get_hw_version
) {
997 svgascreen
->hw_version
= sws
->get_hw_version(sws
);
999 svgascreen
->hw_version
= SVGA3D_HWVERSION_WS65_B1
;
1002 if (svgascreen
->hw_version
< SVGA3D_HWVERSION_WS8_B1
) {
1003 /* too old for 3D acceleration */
1004 debug_printf("Hardware version 0x%x is too old for accerated 3D\n",
1005 svgascreen
->hw_version
);
1009 debug_printf("%s enabled = %u\n",
1010 sws
->have_sm4_1
? "SM4_1" : "VGPU10",
1011 sws
->have_sm4_1
? 1 : sws
->have_vgpu10
);
1013 debug_printf("Mesa: %s %s (%s)\n", svga_get_name(screen
),
1014 PACKAGE_VERSION
, MESA_GIT_SHA1
);
1017 * The D16, D24X8, and D24S8 formats always do an implicit shadow compare
1018 * when sampled from, where as the DF16, DF24, and D24S8_INT do not. So
1019 * we prefer the later when available.
1021 * This mimics hardware vendors extensions for D3D depth sampling. See also
1022 * http://aras-p.info/texts/D3D9GPUHacks.html
1026 boolean has_df16
, has_df24
, has_d24s8_int
;
1027 SVGA3dSurfaceFormatCaps caps
;
1028 SVGA3dSurfaceFormatCaps mask
;
1033 svgascreen
->depth
.z16
= SVGA3D_Z_D16
;
1034 svgascreen
->depth
.x8z24
= SVGA3D_Z_D24X8
;
1035 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8
;
1037 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF16
, &caps
);
1038 has_df16
= (caps
.value
& mask
.value
) == mask
.value
;
1040 svga_get_format_cap(svgascreen
, SVGA3D_Z_DF24
, &caps
);
1041 has_df24
= (caps
.value
& mask
.value
) == mask
.value
;
1043 svga_get_format_cap(svgascreen
, SVGA3D_Z_D24S8_INT
, &caps
);
1044 has_d24s8_int
= (caps
.value
& mask
.value
) == mask
.value
;
1046 /* XXX: We might want some other logic here.
1047 * Like if we only have d24s8_int we should
1048 * emulate the other formats with that.
1051 svgascreen
->depth
.z16
= SVGA3D_Z_DF16
;
1054 svgascreen
->depth
.x8z24
= SVGA3D_Z_DF24
;
1056 if (has_d24s8_int
) {
1057 svgascreen
->depth
.s8z24
= SVGA3D_Z_D24S8_INT
;
1061 /* Query device caps
1063 if (sws
->have_vgpu10
) {
1064 svgascreen
->haveProvokingVertex
1065 = get_bool_cap(sws
, SVGA3D_DEVCAP_DX_PROVOKING_VERTEX
, FALSE
);
1066 svgascreen
->haveLineSmooth
= TRUE
;
1067 svgascreen
->maxPointSize
= 80.0F
;
1068 svgascreen
->max_color_buffers
= SVGA3D_DX_MAX_RENDER_TARGETS
;
1070 /* Multisample samples per pixel */
1071 if (sws
->have_sm4_1
&& debug_get_bool_option("SVGA_MSAA", TRUE
)) {
1072 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_2X
, FALSE
))
1073 svgascreen
->ms_samples
|= 1 << 1;
1074 if (get_bool_cap(sws
, SVGA3D_DEVCAP_MULTISAMPLE_4X
, FALSE
))
1075 svgascreen
->ms_samples
|= 1 << 3;
1078 /* Maximum number of constant buffers */
1079 svgascreen
->max_const_buffers
=
1080 get_uint_cap(sws
, SVGA3D_DEVCAP_DX_MAX_CONSTANT_BUFFERS
, 1);
1081 svgascreen
->max_const_buffers
= MIN2(svgascreen
->max_const_buffers
,
1082 SVGA_MAX_CONST_BUFS
);
1084 screen
->is_format_supported
= svga_is_dx_format_supported
;
1088 unsigned vs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_VERTEX_SHADER_VERSION
,
1089 SVGA3DVSVERSION_NONE
);
1090 unsigned fs_ver
= get_uint_cap(sws
, SVGA3D_DEVCAP_FRAGMENT_SHADER_VERSION
,
1091 SVGA3DPSVERSION_NONE
);
1093 /* we require Shader model 3.0 or later */
1094 if (fs_ver
< SVGA3DPSVERSION_30
|| vs_ver
< SVGA3DVSVERSION_30
) {
1098 svgascreen
->haveProvokingVertex
= FALSE
;
1100 svgascreen
->haveLineSmooth
=
1101 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_AA
, FALSE
);
1103 svgascreen
->maxPointSize
=
1104 get_float_cap(sws
, SVGA3D_DEVCAP_MAX_POINT_SIZE
, 1.0f
);
1105 /* Keep this to a reasonable size to avoid failures in conform/pntaa.c */
1106 svgascreen
->maxPointSize
= MIN2(svgascreen
->maxPointSize
, 80.0f
);
1108 /* The SVGA3D device always supports 4 targets at this time, regardless
1109 * of what querying SVGA3D_DEVCAP_MAX_RENDER_TARGETS might return.
1111 svgascreen
->max_color_buffers
= 4;
1113 /* Only support one constant buffer
1115 svgascreen
->max_const_buffers
= 1;
1117 /* No multisampling */
1118 svgascreen
->ms_samples
= 0;
1121 /* common VGPU9 / VGPU10 caps */
1122 svgascreen
->haveLineStipple
=
1123 get_bool_cap(sws
, SVGA3D_DEVCAP_LINE_STIPPLE
, FALSE
);
1125 svgascreen
->maxLineWidth
=
1126 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_LINE_WIDTH
, 1.0f
));
1128 svgascreen
->maxLineWidthAA
=
1129 MAX2(1.0, get_float_cap(sws
, SVGA3D_DEVCAP_MAX_AA_LINE_WIDTH
, 1.0f
));
1132 debug_printf("svga: haveProvokingVertex %u\n",
1133 svgascreen
->haveProvokingVertex
);
1134 debug_printf("svga: haveLineStip %u "
1135 "haveLineSmooth %u maxLineWidth %.2f maxLineWidthAA %.2f\n",
1136 svgascreen
->haveLineStipple
, svgascreen
->haveLineSmooth
,
1137 svgascreen
->maxLineWidth
, svgascreen
->maxLineWidthAA
);
1138 debug_printf("svga: maxPointSize %g\n", svgascreen
->maxPointSize
);
1139 debug_printf("svga: msaa samples mask: 0x%x\n", svgascreen
->ms_samples
);
1142 (void) mtx_init(&svgascreen
->tex_mutex
, mtx_plain
);
1143 (void) mtx_init(&svgascreen
->swc_mutex
, mtx_recursive
);
1145 svga_screen_cache_init(svgascreen
);
1147 if (debug_get_bool_option("SVGA_NO_LOGGING", FALSE
) == TRUE
) {
1148 svgascreen
->sws
->host_log
= nop_host_log
;
1150 init_logging(screen
);
1161 struct svga_winsys_screen
*
1162 svga_winsys_screen(struct pipe_screen
*screen
)
1164 return svga_screen(screen
)->sws
;
1169 struct svga_screen
*
1170 svga_screen(struct pipe_screen
*screen
)
1173 assert(screen
->destroy
== svga_destroy_screen
);
1174 return (struct svga_screen
*)screen
;