src/gallium/drivers/swr/rasterizer/jitter/functionpasses/lower_x86.cpp

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  23 * @file lower_x86.cpp
  24 *
  25 * @brief llvm pass to lower meta code to x86
  26 *
  27 * Notes:
  28 *
  29 ******************************************************************************/
  30
  31 #include "jit_pch.hpp"
  32 #include "passes.h"
  33 #include "JitManager.h"
  34
  35 #include <unordered_map>
  36
  37
  38 namespace llvm
  39 {
  40     // foward declare the initializer
  41     void initializeLowerX86Pass(PassRegistry&);
  42 }
  43
  44 namespace SwrJit
  45 {
  46     using namespace llvm;
  47
  48     enum TargetArch
  49     {
  50         AVX = 0,
  51         AVX2 = 1,
  52         AVX512 = 2
  53     };
  54
  55     enum TargetWidth
  56     {
  57         W256 = 0,
  58         W512 = 1,
  59         NUM_WIDTHS = 2
  60     };
  61
  62     struct LowerX86;
  63
  64     typedef std::function<Instruction*(LowerX86*, TargetArch, TargetWidth, CallInst*)> EmuFunc;
  65
  66     struct X86Intrinsic
  67     {
  68         Intrinsic::ID intrin[NUM_WIDTHS];
  69         EmuFunc emuFunc;
  70     };
  71
  72     // Map of intrinsics that haven't been moved to the new mechanism yet. If used, these get the previous behavior of
  73     // mapping directly to avx/avx2 intrinsics.
  74     static std::map<std::string, Intrinsic::ID> intrinsicMap = {
  75         {"meta.intrinsic.BEXTR_32",        Intrinsic::x86_bmi_bextr_32},
  76         {"meta.intrinsic.VPSHUFB",         Intrinsic::x86_avx2_pshuf_b},
  77         {"meta.intrinsic.VCVTPS2PH",       Intrinsic::x86_vcvtps2ph_256},
  78         {"meta.intrinsic.VPTESTC",         Intrinsic::x86_avx_ptestc_256},
  79         {"meta.intrinsic.VPTESTZ",         Intrinsic::x86_avx_ptestz_256},
  80         {"meta.intrinsic.VFMADDPS",        Intrinsic::x86_fma_vfmadd_ps_256},
  81         {"meta.intrinsic.VPHADDD",         Intrinsic::x86_avx2_phadd_d},
  82         {"meta.intrinsic.PDEP32",          Intrinsic::x86_bmi_pdep_32},
  83         {"meta.intrinsic.RDTSC",           Intrinsic::x86_rdtsc},
  84     };
  85
  86     // Forward decls
  87     Instruction* NO_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst);
  88     Instruction* VPERM_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst);
  89     Instruction* VGATHER_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst);
  90     Instruction* VROUND_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst);
  91     Instruction* VHSUB_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst);
  92
  93     Instruction* DOUBLE_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst, Intrinsic::ID intrin);
  94
  95     static Intrinsic::ID DOUBLE = (Intrinsic::ID)-1;
  96
  97     static std::map<std::string, X86Intrinsic> intrinsicMap2[] = {
  98         //                              256 wide                                    512 wide
  99     {   // AVX
 100         {"meta.intrinsic.VRCPPS",      {{Intrinsic::x86_avx_rcp_ps_256,              DOUBLE},                                        NO_EMU}},
 101         {"meta.intrinsic.VPERMPS",     {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VPERM_EMU}},
 102         {"meta.intrinsic.VPERMD",      {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VPERM_EMU}},
 103         {"meta.intrinsic.VGATHERPD",   {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VGATHER_EMU}},
 104         {"meta.intrinsic.VGATHERPS",   {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VGATHER_EMU}},
 105         {"meta.intrinsic.VGATHERDD",   {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VGATHER_EMU}},
 106         {"meta.intrinsic.VCVTPD2PS",   {{Intrinsic::x86_avx_cvt_pd2_ps_256,          Intrinsic::not_intrinsic},                      NO_EMU}},
 107         {"meta.intrinsic.VCVTPH2PS",   {{Intrinsic::x86_vcvtph2ps_256,               Intrinsic::not_intrinsic},                      NO_EMU}},
 108         {"meta.intrinsic.VROUND",      {{Intrinsic::x86_avx_round_ps_256,            DOUBLE},                                        NO_EMU}},
 109         {"meta.intrinsic.VHSUBPS",     {{Intrinsic::x86_avx_hsub_ps_256,             DOUBLE},                                        NO_EMU}},
 110     },
 111     {   // AVX2
 112         {"meta.intrinsic.VRCPPS",      {{Intrinsic::x86_avx_rcp_ps_256,              DOUBLE},                                        NO_EMU}},
 113         {"meta.intrinsic.VPERMPS",     {{Intrinsic::x86_avx2_permps,                 Intrinsic::not_intrinsic},                      VPERM_EMU}},
 114         {"meta.intrinsic.VPERMD",      {{Intrinsic::x86_avx2_permd,                  Intrinsic::not_intrinsic},                      VPERM_EMU}},
 115         {"meta.intrinsic.VGATHERPD",   {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VGATHER_EMU}},
 116         {"meta.intrinsic.VGATHERPS",   {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VGATHER_EMU}},
 117         {"meta.intrinsic.VGATHERDD",   {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VGATHER_EMU}},
 118         {"meta.intrinsic.VCVTPD2PS",   {{Intrinsic::x86_avx_cvt_pd2_ps_256,          DOUBLE},                                        NO_EMU}},
 119         {"meta.intrinsic.VCVTPH2PS",   {{Intrinsic::x86_vcvtph2ps_256,               Intrinsic::not_intrinsic},                      NO_EMU}},
 120         {"meta.intrinsic.VROUND",      {{Intrinsic::x86_avx_round_ps_256,            DOUBLE},                                        NO_EMU}},
 121         {"meta.intrinsic.VHSUBPS",     {{Intrinsic::x86_avx_hsub_ps_256,             DOUBLE},                                        NO_EMU}},
 122     },
 123     {   // AVX512
 124         {"meta.intrinsic.VRCPPS",      {{Intrinsic::x86_avx512_rcp14_ps_256,         Intrinsic::x86_avx512_rcp14_ps_512},            NO_EMU}},
 125         {"meta.intrinsic.VPERMPS",     {{Intrinsic::x86_avx512_mask_permvar_sf_256,  Intrinsic::x86_avx512_mask_permvar_sf_512},     NO_EMU}},
 126         {"meta.intrinsic.VPERMD",      {{Intrinsic::x86_avx512_mask_permvar_si_256,  Intrinsic::x86_avx512_mask_permvar_si_512},     NO_EMU}},
 127         {"meta.intrinsic.VGATHERPD",   {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VGATHER_EMU}},
 128         {"meta.intrinsic.VGATHERPS",   {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VGATHER_EMU}},
 129         {"meta.intrinsic.VGATHERDD",   {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VGATHER_EMU}},
 130         {"meta.intrinsic.VCVTPD2PS",   {{Intrinsic::x86_avx512_mask_cvtpd2ps_256,    Intrinsic::x86_avx512_mask_cvtpd2ps_512 },      NO_EMU}},
 131         {"meta.intrinsic.VCVTPH2PS",   {{Intrinsic::x86_avx512_mask_vcvtph2ps_256,   Intrinsic::x86_avx512_mask_vcvtph2ps_512 },     NO_EMU}},
 132         {"meta.intrinsic.VROUND",      {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VROUND_EMU}},
 133         {"meta.intrinsic.VHSUBPS",     {{Intrinsic::not_intrinsic,                   Intrinsic::not_intrinsic},                      VHSUB_EMU}},
 134     }
 135     };
 136
 137     struct LowerX86 : public FunctionPass
 138     {
 139         LowerX86(JitManager* pJitMgr = nullptr, Builder* b = nullptr)
 140             : FunctionPass(ID), mpJitMgr(pJitMgr), B(b)
 141         {
 142             initializeLowerX86Pass(*PassRegistry::getPassRegistry());
 143
 144             // Determine target arch
 145             if (mpJitMgr->mArch.AVX512F())
 146             {
 147                 mTarget = AVX512;
 148             }
 149             else if (mpJitMgr->mArch.AVX2())
 150             {
 151                 mTarget = AVX2;
 152             }
 153             else if (mpJitMgr->mArch.AVX())
 154             {
 155                 mTarget = AVX;
 156
 157             }
 158             else
 159             {
 160                 SWR_ASSERT(false, "Unsupported AVX architecture.");
 161                 mTarget = AVX;
 162             }
 163         }
 164
 165         // Try to decipher the vector type of the instruction. This does not work properly
 166         // across all intrinsics, and will have to be rethought. Probably need something
 167         // similar to llvm's getDeclaration() utility to map a set of inputs to a specific typed
 168         // intrinsic.
 169         void GetRequestedWidthAndType(CallInst* pCallInst, const StringRef intrinName, TargetWidth* pWidth, Type** pTy)
 170         {
 171             Type* pVecTy = pCallInst->getType();
 172
 173             // Check for intrinsic specific types
 174             // VCVTPD2PS type comes from src, not dst
 175             if (intrinName.equals("meta.intrinsic.VCVTPD2PS"))
 176             {
 177                 pVecTy = pCallInst->getOperand(0)->getType();
 178             }
 179
 180             if (!pVecTy->isVectorTy())
 181             {
 182                 for (auto& op : pCallInst->arg_operands())
 183                 {
 184                     if (op.get()->getType()->isVectorTy())
 185                     {
 186                         pVecTy = op.get()->getType();
 187                         break;
 188                     }
 189                 }
 190             }
 191             SWR_ASSERT(pVecTy->isVectorTy(), "Couldn't determine vector size");
 192
 193             uint32_t width = cast<VectorType>(pVecTy)->getBitWidth();
 194             switch (width)
 195             {
 196             case 256: *pWidth = W256; break;
 197             case 512: *pWidth = W512; break;
 198             default: SWR_ASSERT(false, "Unhandled vector width %d", width);
 199                 *pWidth = W256;
 200             }
 201
 202             *pTy = pVecTy->getScalarType();
 203         }
 204
 205         Value* GetZeroVec(TargetWidth width, Type* pTy)
 206         {
 207             uint32_t numElem = 0;
 208             switch (width)
 209             {
 210             case W256: numElem = 8; break;
 211             case W512: numElem = 16; break;
 212             default: SWR_ASSERT(false, "Unhandled vector width type %d\n", width);
 213             }
 214
 215             return ConstantVector::getNullValue(VectorType::get(pTy, numElem));
 216         }
 217
 218         Value* GetMask(TargetWidth width)
 219         {
 220             Value* mask;
 221             switch (width)
 222             {
 223             case W256: mask = B->C((uint8_t)-1); break;
 224             case W512: mask = B->C((uint16_t)-1); break;
 225             default: SWR_ASSERT(false, "Unhandled vector width type %d\n", width);
 226             }
 227             return mask;
 228         }
 229
 230         // Convert <N x i1> mask to <N x i32> x86 mask
 231         Value* VectorMask(Value* vi1Mask)
 232         {
 233             uint32_t numElem = vi1Mask->getType()->getVectorNumElements();
 234             return B->S_EXT(vi1Mask, VectorType::get(B->mInt32Ty, numElem));
 235         }
 236
 237         Instruction* ProcessIntrinsicAdvanced(CallInst* pCallInst)
 238         {
 239             Function* pFunc = pCallInst->getCalledFunction();
 240             auto& intrinsic = intrinsicMap2[mTarget][pFunc->getName()];
 241             TargetWidth vecWidth;
 242             Type* pElemTy;
 243             GetRequestedWidthAndType(pCallInst, pFunc->getName(), &vecWidth, &pElemTy);
 244
 245             // Check if there is a native intrinsic for this instruction
 246             Intrinsic::ID id = intrinsic.intrin[vecWidth];
 247             if (id == DOUBLE)
 248             {
 249                 // Double pump the next smaller SIMD intrinsic
 250                 SWR_ASSERT(vecWidth != 0, "Cannot double pump smallest SIMD width.");
 251                 Intrinsic::ID id2 = intrinsic.intrin[vecWidth - 1];
 252                 SWR_ASSERT(id2 != Intrinsic::not_intrinsic, "Cannot find intrinsic to double pump.");
 253                 return DOUBLE_EMU(this, mTarget, vecWidth, pCallInst, id2);
 254             }
 255             else if (id != Intrinsic::not_intrinsic)
 256             {
 257                 Function* pIntrin = Intrinsic::getDeclaration(B->JM()->mpCurrentModule, id);
 258                 SmallVector<Value*, 8> args;
 259                 for (auto& arg : pCallInst->arg_operands())
 260                 {
 261                     args.push_back(arg.get());
 262                 }
 263
 264                 // If AVX512, all instructions add a src operand and mask. We'll pass in 0 src and full mask for now
 265                 // Assuming the intrinsics are consistent and place the src operand and mask last in the argument list.
 266                 if (mTarget == AVX512)
 267                 {
 268                     args.push_back(GetZeroVec(vecWidth, pElemTy));
 269                     args.push_back(GetMask(vecWidth));
 270                 }
 271
 272                 return B->CALLA(pIntrin, args);
 273             }
 274             else
 275             {
 276                 // No native intrinsic, call emulation function
 277                 return intrinsic.emuFunc(this, mTarget, vecWidth, pCallInst);
 278             }
 279
 280             SWR_ASSERT(false);
 281             return nullptr;
 282         }
 283
 284         Instruction* ProcessIntrinsic(CallInst* pCallInst)
 285         {
 286             Function* pFunc = pCallInst->getCalledFunction();
 287
 288             // Forward to the advanced support if found
 289             if (intrinsicMap2[mTarget].find(pFunc->getName()) != intrinsicMap2[mTarget].end())
 290             {
 291                 return ProcessIntrinsicAdvanced(pCallInst);
 292             }
 293
 294             SWR_ASSERT(intrinsicMap.find(pFunc->getName()) != intrinsicMap.end(), "Unimplemented intrinsic %s.", pFunc->getName());
 295
 296             Intrinsic::ID x86Intrinsic = intrinsicMap[pFunc->getName()];
 297             Function* pX86IntrinFunc = Intrinsic::getDeclaration(B->JM()->mpCurrentModule, x86Intrinsic);
 298
 299             SmallVector<Value*, 8> args;
 300             for (auto& arg : pCallInst->arg_operands())
 301             {
 302                 args.push_back(arg.get());
 303             }
 304             return B->CALLA(pX86IntrinFunc, args);
 305         }
 306
 307         //////////////////////////////////////////////////////////////////////////
 308         /// @brief LLVM funtion pass run method.
 309         /// @param f- The function we're working on with this pass.
 310         virtual bool runOnFunction(Function& F)
 311         {
 312             std::vector<Instruction*> toRemove;
 313
 314             for (auto& BB : F.getBasicBlockList())
 315             {
 316                 for (auto& I : BB.getInstList())
 317                 {
 318                     if (CallInst* pCallInst = dyn_cast<CallInst>(&I))
 319                     {
 320                         Function* pFunc = pCallInst->getCalledFunction();
 321                         if (pFunc)
 322                         {
 323                             if (pFunc->getName().startswith("meta.intrinsic"))
 324                             {
 325                                 B->IRB()->SetInsertPoint(&I);
 326                                 Instruction* pReplace = ProcessIntrinsic(pCallInst);
 327                                 SWR_ASSERT(pReplace);
 328                                 toRemove.push_back(pCallInst);
 329                                 pCallInst->replaceAllUsesWith(pReplace);
 330                             }
 331                         }
 332
 333                     }
 334                 }
 335             }
 336
 337             for (auto* pInst : toRemove)
 338             {
 339                 pInst->eraseFromParent();
 340             }
 341
 342             JitManager::DumpToFile(&F, "lowerx86");
 343
 344             return true;
 345         }
 346
 347         virtual void getAnalysisUsage(AnalysisUsage& AU) const
 348         {
 349         }
 350
 351         JitManager* JM() { return mpJitMgr; }
 352
 353         JitManager* mpJitMgr;
 354         Builder* B;
 355
 356         TargetArch mTarget;
 357
 358         static char ID;  ///< Needed by LLVM to generate ID for FunctionPass.
 359     };
 360
 361     char LowerX86::ID = 0;   // LLVM uses address of ID as the actual ID.
 362
 363     FunctionPass* createLowerX86Pass(JitManager* pJitMgr, Builder* b)
 364     {
 365         return new LowerX86(pJitMgr, b);
 366     }
 367
 368     Instruction* NO_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst)
 369     {
 370         SWR_ASSERT(false, "Unimplemented intrinsic emulation.");
 371         return nullptr;
 372     }
 373
 374     Instruction* VPERM_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst)
 375     {
 376         // Only need vperm emulation for AVX
 377         SWR_ASSERT(arch == AVX);
 378
 379         Builder* B = pThis->B;
 380         auto v32A = pCallInst->getArgOperand(0);
 381         auto vi32Index = pCallInst->getArgOperand(1);
 382
 383         Value* v32Result;
 384         if (isa<Constant>(vi32Index))
 385         {
 386             // Can use llvm shuffle vector directly with constant shuffle indices
 387             v32Result = B->VSHUFFLE(v32A, v32A, vi32Index);
 388         }
 389         else
 390         {
 391             v32Result = UndefValue::get(v32A->getType());
 392             for (uint32_t l = 0; l < v32A->getType()->getVectorNumElements(); ++l)
 393             {
 394                 auto i32Index = B->VEXTRACT(vi32Index, B->C(l));
 395                 auto val = B->VEXTRACT(v32A, i32Index);
 396                 v32Result = B->VINSERT(v32Result, val, B->C(l));
 397             }
 398         }
 399         return cast<Instruction>(v32Result);
 400     }
 401
 402     Instruction* VGATHER_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst)
 403     {
 404         Builder* B = pThis->B;
 405         auto vSrc = pCallInst->getArgOperand(0);
 406         auto pBase = pCallInst->getArgOperand(1);
 407         auto vi32Indices = pCallInst->getArgOperand(2);
 408         auto vi1Mask = pCallInst->getArgOperand(3);
 409         auto i8Scale = pCallInst->getArgOperand(4);
 410
 411         pBase = B->INT_TO_PTR(pBase, PointerType::get(B->mInt8Ty, 0));
 412         uint32_t numElem = vSrc->getType()->getVectorNumElements();
 413         auto i32Scale = B->Z_EXT(i8Scale, B->mInt32Ty);
 414         auto srcTy = vSrc->getType()->getVectorElementType();
 415         Value* v32Gather;
 416         if (arch == AVX)
 417         {
 418             // Full emulation for AVX
 419             // Store source on stack to provide a valid address to load from inactive lanes
 420             auto pStack = B->STACKSAVE();
 421             auto pTmp = B->ALLOCA(vSrc->getType());
 422             B->STORE(vSrc, pTmp);
 423
 424             v32Gather = UndefValue::get(vSrc->getType());
 425             auto vi32Scale = ConstantVector::getSplat(numElem, cast<ConstantInt>(i32Scale));
 426             auto vi32Offsets = B->MUL(vi32Indices, vi32Scale);
 427
 428             for (uint32_t i = 0; i < numElem; ++i)
 429             {
 430                 auto i32Offset = B->VEXTRACT(vi32Offsets, B->C(i));
 431                 auto pLoadAddress = B->GEP(pBase, i32Offset);
 432                 pLoadAddress = B->BITCAST(pLoadAddress, PointerType::get(srcTy, 0));
 433                 auto pMaskedLoadAddress = B->GEP(pTmp, { 0, i });
 434                 auto i1Mask = B->VEXTRACT(vi1Mask, B->C(i));
 435                 auto pValidAddress = B->SELECT(i1Mask, pLoadAddress, pMaskedLoadAddress);
 436                 auto val = B->LOAD(pValidAddress);
 437                 v32Gather = B->VINSERT(v32Gather, val, B->C(i));
 438             }
 439
 440             B->STACKRESTORE(pStack);
 441         }
 442         else if (arch == AVX2 || (arch == AVX512 && width == W256))
 443         {
 444             Function* pX86IntrinFunc;
 445             if (srcTy == B->mFP32Ty)
 446             {
 447                 pX86IntrinFunc = Intrinsic::getDeclaration(B->JM()->mpCurrentModule, Intrinsic::x86_avx2_gather_d_ps_256);
 448             }
 449             else if (srcTy == B->mInt32Ty)
 450             {
 451                 pX86IntrinFunc = Intrinsic::getDeclaration(B->JM()->mpCurrentModule, Intrinsic::x86_avx2_gather_d_d_256);
 452             }
 453             else if (srcTy == B->mDoubleTy)
 454             {
 455                 pX86IntrinFunc = Intrinsic::getDeclaration(B->JM()->mpCurrentModule, Intrinsic::x86_avx2_gather_d_q_256);
 456             }
 457             else
 458             {
 459                 SWR_ASSERT(false, "Unsupported vector element type for gather.");
 460             }
 461
 462             if (width == W256)
 463             {
 464                 auto v32Mask = B->BITCAST(pThis->VectorMask(vi1Mask), vSrc->getType());
 465                 v32Gather = B->CALL(pX86IntrinFunc, { vSrc, pBase, vi32Indices, v32Mask, i8Scale });
 466             }
 467             else if (width == W512)
 468             {
 469                 // Double pump 4-wide for 64bit elements
 470                 if (vSrc->getType()->getVectorElementType() == B->mDoubleTy)
 471                 {
 472                     auto v64Mask = pThis->VectorMask(vi1Mask);
 473                     v64Mask = B->S_EXT(v64Mask,
 474                                        VectorType::get(B->mInt64Ty, v64Mask->getType()->getVectorNumElements()));
 475                     v64Mask = B->BITCAST(v64Mask, vSrc->getType());
 476
 477                     Value* src0 = B->VSHUFFLE(vSrc, vSrc, B->C({ 0, 1, 2, 3 }));
 478                     Value* src1 = B->VSHUFFLE(vSrc, vSrc, B->C({ 4, 5, 6, 7 }));
 479
 480                     Value* indices0 = B->VSHUFFLE(vi32Indices, vi32Indices, B->C({ 0, 1, 2, 3 }));
 481                     Value* indices1 = B->VSHUFFLE(vi32Indices, vi32Indices, B->C({ 4, 5, 6, 7 }));
 482
 483                     Value* mask0 = B->VSHUFFLE(v64Mask, v64Mask, B->C({ 0, 1, 2, 3 }));
 484                     Value* mask1 = B->VSHUFFLE(v64Mask, v64Mask, B->C({ 4, 5, 6, 7 }));
 485
 486                     src0 = B->BITCAST(src0, VectorType::get(B->mInt64Ty, src0->getType()->getVectorNumElements()));
 487                     mask0 = B->BITCAST(mask0, VectorType::get(B->mInt64Ty, mask0->getType()->getVectorNumElements()));
 488                     Value* gather0 = B->CALL(pX86IntrinFunc, { src0, pBase, indices0, mask0, i8Scale });
 489                     src1 = B->BITCAST(src1, VectorType::get(B->mInt64Ty, src1->getType()->getVectorNumElements()));
 490                     mask1 = B->BITCAST(mask1, VectorType::get(B->mInt64Ty, mask1->getType()->getVectorNumElements()));
 491                     Value* gather1 = B->CALL(pX86IntrinFunc, { src1, pBase, indices1, mask1, i8Scale });
 492
 493                     v32Gather = B->VSHUFFLE(gather0, gather1, B->C({ 0, 1, 2, 3, 4, 5, 6, 7 }));
 494                     v32Gather = B->BITCAST(v32Gather, vSrc->getType());
 495                 }
 496                 else
 497                 {
 498                     // Double pump 8-wide for 32bit elements
 499                     auto v32Mask = pThis->VectorMask(vi1Mask);
 500                     v32Mask = B->BITCAST(v32Mask, vSrc->getType());
 501                     Value* src0 = B->EXTRACT_16(vSrc, 0);
 502                     Value* src1 = B->EXTRACT_16(vSrc, 1);
 503
 504                     Value* indices0 = B->EXTRACT_16(vi32Indices, 0);
 505                     Value* indices1 = B->EXTRACT_16(vi32Indices, 1);
 506
 507                     Value* mask0 = B->EXTRACT_16(v32Mask, 0);
 508                     Value* mask1 = B->EXTRACT_16(v32Mask, 1);
 509
 510                     Value* gather0 = B->CALL(pX86IntrinFunc, { src0, pBase, indices0, mask0, i8Scale });
 511                     Value* gather1 = B->CALL(pX86IntrinFunc, { src1, pBase, indices1, mask1, i8Scale });
 512
 513                     v32Gather = B->JOIN_16(gather0, gather1);
 514                 }
 515             }
 516         }
 517         else if (arch == AVX512)
 518         {
 519             Value* iMask;
 520             Function* pX86IntrinFunc;
 521             if (srcTy == B->mFP32Ty)
 522             {
 523                 pX86IntrinFunc = Intrinsic::getDeclaration(B->JM()->mpCurrentModule, Intrinsic::x86_avx512_gather_dps_512);
 524                 iMask = B->BITCAST(vi1Mask, B->mInt16Ty);
 525             }
 526             else if (srcTy == B->mInt32Ty)
 527             {
 528                 pX86IntrinFunc = Intrinsic::getDeclaration(B->JM()->mpCurrentModule, Intrinsic::x86_avx512_gather_dpi_512);
 529                 iMask = B->BITCAST(vi1Mask, B->mInt16Ty);
 530             }
 531             else if (srcTy == B->mDoubleTy)
 532             {
 533                 pX86IntrinFunc = Intrinsic::getDeclaration(B->JM()->mpCurrentModule, Intrinsic::x86_avx512_gather_dpd_512);
 534                 iMask = B->BITCAST(vi1Mask, B->mInt8Ty);
 535             }
 536             else
 537             {
 538                 SWR_ASSERT(false, "Unsupported vector element type for gather.");
 539             }
 540
 541             auto i32Scale = B->Z_EXT(i8Scale, B->mInt32Ty);
 542             v32Gather = B->CALL(pX86IntrinFunc, { vSrc, pBase, vi32Indices, iMask, i32Scale });
 543         }
 544
 545         return cast<Instruction>(v32Gather);
 546     }
 547
 548     // No support for vroundps in avx512 (it is available in kncni), so emulate with avx instructions
 549     Instruction* VROUND_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst)
 550     {
 551         SWR_ASSERT(arch == AVX512);
 552
 553         auto B = pThis->B;
 554         auto vf32Src = pCallInst->getOperand(0);
 555         auto i8Round = pCallInst->getOperand(1);
 556         auto pfnFunc = Intrinsic::getDeclaration(B->JM()->mpCurrentModule, Intrinsic::x86_avx_round_ps_256);
 557
 558         if (width == W256)
 559         {
 560             return cast<Instruction>(B->CALL2(pfnFunc, vf32Src, i8Round));
 561         }
 562         else if (width == W512)
 563         {
 564             auto v8f32SrcLo = B->EXTRACT_16(vf32Src, 0);
 565             auto v8f32SrcHi = B->EXTRACT_16(vf32Src, 1);
 566
 567             auto v8f32ResLo = B->CALL2(pfnFunc, v8f32SrcLo, i8Round);
 568             auto v8f32ResHi = B->CALL2(pfnFunc, v8f32SrcHi, i8Round);
 569
 570             return cast<Instruction>(B->JOIN_16(v8f32ResLo, v8f32ResHi));
 571         }
 572         else
 573         {
 574             SWR_ASSERT(false, "Unimplemented vector width.");
 575         }
 576
 577         return nullptr;
 578     }
 579
 580     // No support for hsub in AVX512
 581     Instruction* VHSUB_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst)
 582     {
 583         SWR_ASSERT(arch == AVX512);
 584
 585         auto B = pThis->B;
 586         auto src0 = pCallInst->getOperand(0);
 587         auto src1 = pCallInst->getOperand(1);
 588
 589         // 256b hsub can just use avx intrinsic
 590         if (width == W256)
 591         {
 592             auto pX86IntrinFunc = Intrinsic::getDeclaration(B->JM()->mpCurrentModule, Intrinsic::x86_avx_hsub_ps_256);
 593             return cast<Instruction>(B->CALL2(pX86IntrinFunc, src0, src1));
 594         }
 595         else if (width == W512)
 596         {
 597             // 512b hsub can be accomplished with shuf/sub combo
 598             auto minuend = B->VSHUFFLE(src0, src1, B->C({ 0, 2, 8, 10, 4, 6, 12, 14 }));
 599             auto subtrahend = B->VSHUFFLE(src0, src1, B->C({ 1, 3, 9, 11, 5, 7, 13, 15 }));
 600             return cast<Instruction>(B->SUB(minuend, subtrahend));
 601         }
 602         else
 603         {
 604             SWR_ASSERT(false, "Unimplemented vector width.");
 605             return nullptr;
 606         }
 607     }
 608
 609     // Double pump input using Intrin template arg. This blindly extracts lower and upper 256 from each vector argument and
 610     // calls the 256 wide intrinsic, then merges the results to 512 wide
 611     Instruction* DOUBLE_EMU(LowerX86* pThis, TargetArch arch, TargetWidth width, CallInst* pCallInst, Intrinsic::ID intrin)
 612     {
 613         auto B = pThis->B;
 614         SWR_ASSERT(width == W512);
 615         Value* result[2];
 616         Function* pX86IntrinFunc = Intrinsic::getDeclaration(B->JM()->mpCurrentModule, intrin);
 617         for (uint32_t i = 0; i < 2; ++i)
 618         {
 619             SmallVector<Value*, 8> args;
 620             for (auto& arg : pCallInst->arg_operands())
 621             {
 622                 auto argType = arg.get()->getType();
 623                 if (argType->isVectorTy())
 624                 {
 625                     uint32_t vecWidth = argType->getVectorNumElements();
 626                     Value *lanes = B->CInc<int>(i*vecWidth/2, vecWidth/2);
 627                     Value *argToPush = B->VSHUFFLE(arg.get(), B->VUNDEF(argType->getVectorElementType(), vecWidth), lanes);
 628                     args.push_back(argToPush);
 629                 }
 630                 else
 631                 {
 632                     args.push_back(arg.get());
 633                 }
 634             }
 635             result[i] = B->CALLA(pX86IntrinFunc, args);
 636         }
 637         uint32_t vecWidth;
 638         if (result[0]->getType()->isVectorTy())
 639         {
 640             assert(result[1]->getType()->isVectorTy());
 641             vecWidth = result[0]->getType()->getVectorNumElements() +
 642                 result[1]->getType()->getVectorNumElements();
 643         }
 644         else
 645         {
 646             vecWidth = 2;
 647         }
 648         Value *lanes = B->CInc<int>(0, vecWidth);
 649         return cast<Instruction>(B->VSHUFFLE(result[0], result[1], lanes));
 650     }
 651
 652 }
 653
 654 using namespace SwrJit;
 655
 656 INITIALIZE_PASS_BEGIN(LowerX86, "LowerX86", "LowerX86", false, false)
 657 INITIALIZE_PASS_END(LowerX86, "LowerX86", "LowerX86", false, false)
 658