2 * Copyright © 2014-2017 Broadcom
3 * Copyright (C) 2012 Rob Clark <robclark@freedesktop.org>
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include <sys/sysinfo.h>
27 #include "util/os_misc.h"
28 #include "pipe/p_defines.h"
29 #include "pipe/p_screen.h"
30 #include "pipe/p_state.h"
32 #include "util/u_debug.h"
33 #include "util/u_memory.h"
34 #include "util/u_format.h"
35 #include "util/u_hash_table.h"
36 #include "util/u_screen.h"
37 #include "util/u_transfer_helper.h"
38 #include "util/ralloc.h"
39 #include "util/xmlconfig.h"
42 #include "v3d_screen.h"
43 #include "v3d_context.h"
44 #include "v3d_resource.h"
45 #include "compiler/v3d_compiler.h"
46 #include "drm-uapi/drm_fourcc.h"
49 v3d_screen_get_name(struct pipe_screen
*pscreen
)
51 struct v3d_screen
*screen
= v3d_screen(pscreen
);
54 screen
->name
= ralloc_asprintf(screen
,
56 screen
->devinfo
.ver
/ 10,
57 screen
->devinfo
.ver
% 10);
64 v3d_screen_get_vendor(struct pipe_screen
*pscreen
)
70 v3d_screen_destroy(struct pipe_screen
*pscreen
)
72 struct v3d_screen
*screen
= v3d_screen(pscreen
);
74 util_hash_table_destroy(screen
->bo_handles
);
75 v3d_bufmgr_destroy(pscreen
);
76 slab_destroy_parent(&screen
->transfer_pool
);
79 if (using_v3d_simulator
)
80 v3d_simulator_destroy(screen
);
82 v3d_compiler_free(screen
->compiler
);
83 u_transfer_helper_destroy(pscreen
->transfer_helper
);
90 v3d_has_feature(struct v3d_screen
*screen
, enum drm_v3d_param feature
)
92 struct drm_v3d_get_param p
= {
95 int ret
= v3d_ioctl(screen
->fd
, DRM_IOCTL_V3D_GET_PARAM
, &p
);
104 v3d_screen_get_param(struct pipe_screen
*pscreen
, enum pipe_cap param
)
106 struct v3d_screen
*screen
= v3d_screen(pscreen
);
109 /* Supported features (boolean caps). */
110 case PIPE_CAP_VERTEX_COLOR_CLAMPED
:
111 case PIPE_CAP_VERTEX_COLOR_UNCLAMPED
:
112 case PIPE_CAP_FRAGMENT_COLOR_CLAMPED
:
113 case PIPE_CAP_BUFFER_MAP_PERSISTENT_COHERENT
:
114 case PIPE_CAP_NPOT_TEXTURES
:
115 case PIPE_CAP_SHAREABLE_SHADERS
:
116 case PIPE_CAP_BLEND_EQUATION_SEPARATE
:
117 case PIPE_CAP_TEXTURE_MULTISAMPLE
:
118 case PIPE_CAP_TEXTURE_SWIZZLE
:
119 case PIPE_CAP_VERTEX_ELEMENT_INSTANCE_DIVISOR
:
120 case PIPE_CAP_START_INSTANCE
:
121 case PIPE_CAP_TGSI_INSTANCEID
:
122 case PIPE_CAP_FRAGMENT_SHADER_TEXTURE_LOD
:
123 case PIPE_CAP_FRAGMENT_SHADER_DERIVATIVES
:
124 case PIPE_CAP_VERTEX_SHADER_SATURATE
:
125 case PIPE_CAP_TEXTURE_QUERY_LOD
:
126 case PIPE_CAP_PRIMITIVE_RESTART
:
127 case PIPE_CAP_OCCLUSION_QUERY
:
128 case PIPE_CAP_POINT_SPRITE
:
129 case PIPE_CAP_STREAM_OUTPUT_PAUSE_RESUME
:
130 case PIPE_CAP_DRAW_INDIRECT
:
131 case PIPE_CAP_MULTI_DRAW_INDIRECT
:
132 case PIPE_CAP_QUADS_FOLLOW_PROVOKING_VERTEX_CONVENTION
:
133 case PIPE_CAP_SIGNED_VERTEX_BUFFER_OFFSET
:
134 case PIPE_CAP_TGSI_CAN_READ_OUTPUTS
:
135 case PIPE_CAP_TGSI_PACK_HALF_FLOAT
:
136 case PIPE_CAP_TEXTURE_HALF_FLOAT_LINEAR
:
137 case PIPE_CAP_FRAMEBUFFER_NO_ATTACHMENT
:
140 case PIPE_CAP_PACKED_UNIFORMS
:
141 /* We can't enable this flag, because it results in load_ubo
142 * intrinsics across a 16b boundary, but v3d's TMU general
143 * memory accesses wrap on 16b boundaries.
147 case PIPE_CAP_PREFER_BLIT_BASED_TEXTURE_TRANSFER
:
148 /* XXX perf: we don't want to emit these extra blits for
149 * glReadPixels(), since we still have to do an uncached read
150 * from the GPU of the result after waiting for the TFU blit
151 * to happen. However, disabling this introduces instability
153 * dEQP-GLES31.functional.image_load_store.early_fragment_tests.*
154 * and corruption in chromium's rendering.
158 case PIPE_CAP_COMPUTE
:
159 return screen
->has_csd
&& screen
->devinfo
.ver
>= 41;
161 case PIPE_CAP_GENERATE_MIPMAP
:
162 return v3d_has_feature(screen
, DRM_V3D_PARAM_SUPPORTS_TFU
);
164 case PIPE_CAP_INDEP_BLEND_ENABLE
:
165 return screen
->devinfo
.ver
>= 40;
167 case PIPE_CAP_CONSTANT_BUFFER_OFFSET_ALIGNMENT
:
170 case PIPE_CAP_MAX_TEXTURE_GATHER_COMPONENTS
:
171 if (screen
->devinfo
.ver
< 40)
175 case PIPE_CAP_SHADER_BUFFER_OFFSET_ALIGNMENT
:
178 case PIPE_CAP_GLSL_FEATURE_LEVEL
:
181 case PIPE_CAP_GLSL_FEATURE_LEVEL_COMPATIBILITY
:
184 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_UPPER_LEFT
:
186 case PIPE_CAP_TGSI_FS_COORD_ORIGIN_LOWER_LEFT
:
188 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_INTEGER
:
189 if (screen
->devinfo
.ver
>= 40)
193 case PIPE_CAP_TGSI_FS_COORD_PIXEL_CENTER_HALF_INTEGER
:
194 if (screen
->devinfo
.ver
>= 40)
199 case PIPE_CAP_MIXED_FRAMEBUFFER_SIZES
:
200 case PIPE_CAP_MIXED_COLORBUFFER_FORMATS
:
201 case PIPE_CAP_MIXED_COLOR_DEPTH_BITS
:
204 case PIPE_CAP_MAX_STREAM_OUTPUT_BUFFERS
:
207 case PIPE_CAP_MAX_VARYINGS
:
208 return V3D_MAX_FS_INPUTS
/ 4;
211 case PIPE_CAP_MAX_TEXTURE_2D_SIZE
:
212 if (screen
->devinfo
.ver
< 40)
214 else if (screen
->nonmsaa_texture_size_limit
)
218 case PIPE_CAP_MAX_TEXTURE_CUBE_LEVELS
:
219 case PIPE_CAP_MAX_TEXTURE_3D_LEVELS
:
220 if (screen
->devinfo
.ver
< 40)
223 return V3D_MAX_MIP_LEVELS
;
224 case PIPE_CAP_MAX_TEXTURE_ARRAY_LAYERS
:
227 /* Render targets. */
228 case PIPE_CAP_MAX_RENDER_TARGETS
:
231 case PIPE_CAP_VENDOR_ID
:
233 case PIPE_CAP_ACCELERATED
:
235 case PIPE_CAP_VIDEO_MEMORY
: {
236 uint64_t system_memory
;
238 if (!os_get_total_physical_memory(&system_memory
))
241 return (int)(system_memory
>> 20);
247 return u_pipe_screen_get_param_defaults(pscreen
, param
);
252 v3d_screen_get_paramf(struct pipe_screen
*pscreen
, enum pipe_capf param
)
255 case PIPE_CAPF_MAX_LINE_WIDTH
:
256 case PIPE_CAPF_MAX_LINE_WIDTH_AA
:
259 case PIPE_CAPF_MAX_POINT_WIDTH
:
260 case PIPE_CAPF_MAX_POINT_WIDTH_AA
:
263 case PIPE_CAPF_MAX_TEXTURE_ANISOTROPY
:
265 case PIPE_CAPF_MAX_TEXTURE_LOD_BIAS
:
268 case PIPE_CAPF_MIN_CONSERVATIVE_RASTER_DILATE
:
269 case PIPE_CAPF_MAX_CONSERVATIVE_RASTER_DILATE
:
270 case PIPE_CAPF_CONSERVATIVE_RASTER_DILATE_GRANULARITY
:
273 fprintf(stderr
, "unknown paramf %d\n", param
);
279 v3d_screen_get_shader_param(struct pipe_screen
*pscreen
, unsigned shader
,
280 enum pipe_shader_cap param
)
282 struct v3d_screen
*screen
= v3d_screen(pscreen
);
285 case PIPE_SHADER_VERTEX
:
286 case PIPE_SHADER_FRAGMENT
:
288 case PIPE_SHADER_COMPUTE
:
289 if (!screen
->has_csd
)
296 /* this is probably not totally correct.. but it's a start: */
298 case PIPE_SHADER_CAP_MAX_INSTRUCTIONS
:
299 case PIPE_SHADER_CAP_MAX_ALU_INSTRUCTIONS
:
300 case PIPE_SHADER_CAP_MAX_TEX_INSTRUCTIONS
:
301 case PIPE_SHADER_CAP_MAX_TEX_INDIRECTIONS
:
304 case PIPE_SHADER_CAP_MAX_CONTROL_FLOW_DEPTH
:
307 case PIPE_SHADER_CAP_MAX_INPUTS
:
308 if (shader
== PIPE_SHADER_FRAGMENT
)
309 return V3D_MAX_FS_INPUTS
/ 4;
311 return V3D_MAX_VS_INPUTS
/ 4;
312 case PIPE_SHADER_CAP_MAX_OUTPUTS
:
313 if (shader
== PIPE_SHADER_FRAGMENT
)
316 return V3D_MAX_FS_INPUTS
/ 4;
317 case PIPE_SHADER_CAP_MAX_TEMPS
:
318 return 256; /* GL_MAX_PROGRAM_TEMPORARIES_ARB */
319 case PIPE_SHADER_CAP_MAX_CONST_BUFFER_SIZE
:
320 /* Note: Limited by the offset size in
321 * v3d_unit_data_create().
323 return 16 * 1024 * sizeof(float);
324 case PIPE_SHADER_CAP_MAX_CONST_BUFFERS
:
326 case PIPE_SHADER_CAP_TGSI_CONT_SUPPORTED
:
328 case PIPE_SHADER_CAP_INDIRECT_INPUT_ADDR
:
329 case PIPE_SHADER_CAP_INDIRECT_OUTPUT_ADDR
:
331 case PIPE_SHADER_CAP_INDIRECT_TEMP_ADDR
:
333 case PIPE_SHADER_CAP_INDIRECT_CONST_ADDR
:
335 case PIPE_SHADER_CAP_SUBROUTINES
:
337 case PIPE_SHADER_CAP_INTEGERS
:
339 case PIPE_SHADER_CAP_FP16
:
340 case PIPE_SHADER_CAP_TGSI_DROUND_SUPPORTED
:
341 case PIPE_SHADER_CAP_TGSI_DFRACEXP_DLDEXP_SUPPORTED
:
342 case PIPE_SHADER_CAP_TGSI_LDEXP_SUPPORTED
:
343 case PIPE_SHADER_CAP_TGSI_FMA_SUPPORTED
:
344 case PIPE_SHADER_CAP_TGSI_ANY_INOUT_DECL_RANGE
:
345 case PIPE_SHADER_CAP_TGSI_SQRT_SUPPORTED
:
346 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTERS
:
347 case PIPE_SHADER_CAP_MAX_HW_ATOMIC_COUNTER_BUFFERS
:
349 case PIPE_SHADER_CAP_SCALAR_ISA
:
351 case PIPE_SHADER_CAP_MAX_TEXTURE_SAMPLERS
:
352 case PIPE_SHADER_CAP_MAX_SAMPLER_VIEWS
:
353 return V3D_MAX_TEXTURE_SAMPLERS
;
355 case PIPE_SHADER_CAP_MAX_SHADER_BUFFERS
:
356 if (shader
== PIPE_SHADER_VERTEX
)
359 return PIPE_MAX_SHADER_BUFFERS
;
361 case PIPE_SHADER_CAP_MAX_SHADER_IMAGES
:
362 if (screen
->devinfo
.ver
< 41)
365 return PIPE_MAX_SHADER_IMAGES
;
367 case PIPE_SHADER_CAP_PREFERRED_IR
:
368 return PIPE_SHADER_IR_NIR
;
369 case PIPE_SHADER_CAP_SUPPORTED_IRS
:
370 return 1 << PIPE_SHADER_IR_NIR
;
371 case PIPE_SHADER_CAP_MAX_UNROLL_ITERATIONS_HINT
:
373 case PIPE_SHADER_CAP_LOWER_IF_THRESHOLD
:
374 case PIPE_SHADER_CAP_TGSI_SKIP_MERGE_REGISTERS
:
377 fprintf(stderr
, "unknown shader param %d\n", param
);
384 v3d_get_compute_param(struct pipe_screen
*pscreen
, enum pipe_shader_ir ir_type
,
385 enum pipe_compute_cap param
, void *ret
)
387 struct v3d_screen
*screen
= v3d_screen(pscreen
);
389 if (!screen
->has_csd
)
392 #define RET(x) do { \
394 memcpy(ret, x, sizeof(x)); \
399 case PIPE_COMPUTE_CAP_ADDRESS_BITS
:
400 RET((uint32_t []) { 32 });
403 case PIPE_COMPUTE_CAP_IR_TARGET
:
407 case PIPE_COMPUTE_CAP_GRID_DIMENSION
:
408 RET((uint64_t []) { 3 });
410 case PIPE_COMPUTE_CAP_MAX_GRID_SIZE
:
411 /* GL_MAX_COMPUTE_SHADER_WORK_GROUP_COUNT: The CSD has a
412 * 16-bit field for the number of workgroups in each
415 RET(((uint64_t []) { 65535, 65535, 65535 }));
417 case PIPE_COMPUTE_CAP_MAX_BLOCK_SIZE
:
418 /* GL_MAX_COMPUTE_WORK_GROUP_SIZE */
419 RET(((uint64_t []) { 256, 256, 256 }));
421 case PIPE_COMPUTE_CAP_MAX_THREADS_PER_BLOCK
:
422 case PIPE_COMPUTE_CAP_MAX_VARIABLE_THREADS_PER_BLOCK
:
423 /* GL_MAX_COMPUTE_WORK_GROUP_INVOCATIONS: This is
424 * limited by WG_SIZE in the CSD.
426 RET((uint64_t []) { 256 });
428 case PIPE_COMPUTE_CAP_MAX_GLOBAL_SIZE
:
429 RET((uint64_t []) { 1024 * 1024 * 1024 });
431 case PIPE_COMPUTE_CAP_MAX_LOCAL_SIZE
:
432 /* GL_MAX_COMPUTE_SHARED_MEMORY_SIZE */
433 RET((uint64_t []) { 32768 });
435 case PIPE_COMPUTE_CAP_MAX_PRIVATE_SIZE
:
436 case PIPE_COMPUTE_CAP_MAX_INPUT_SIZE
:
437 RET((uint64_t []) { 4096 });
439 case PIPE_COMPUTE_CAP_MAX_MEM_ALLOC_SIZE
: {
442 RET((uint64_t []) { si
.totalram
});
445 case PIPE_COMPUTE_CAP_MAX_CLOCK_FREQUENCY
:
447 RET((uint32_t []) { 0 });
449 case PIPE_COMPUTE_CAP_MAX_COMPUTE_UNITS
:
450 RET((uint32_t []) { 1 });
452 case PIPE_COMPUTE_CAP_IMAGES_SUPPORTED
:
453 RET((uint32_t []) { 1 });
455 case PIPE_COMPUTE_CAP_SUBGROUP_SIZE
:
456 RET((uint32_t []) { 16 });
464 v3d_screen_is_format_supported(struct pipe_screen
*pscreen
,
465 enum pipe_format format
,
466 enum pipe_texture_target target
,
467 unsigned sample_count
,
468 unsigned storage_sample_count
,
471 struct v3d_screen
*screen
= v3d_screen(pscreen
);
473 if (MAX2(1, sample_count
) != MAX2(1, storage_sample_count
))
476 if (sample_count
> 1 && sample_count
!= V3D_MAX_SAMPLES
)
479 if (target
>= PIPE_MAX_TEXTURE_TYPES
) {
483 if (usage
& PIPE_BIND_VERTEX_BUFFER
) {
485 case PIPE_FORMAT_R32G32B32A32_FLOAT
:
486 case PIPE_FORMAT_R32G32B32_FLOAT
:
487 case PIPE_FORMAT_R32G32_FLOAT
:
488 case PIPE_FORMAT_R32_FLOAT
:
489 case PIPE_FORMAT_R32G32B32A32_SNORM
:
490 case PIPE_FORMAT_R32G32B32_SNORM
:
491 case PIPE_FORMAT_R32G32_SNORM
:
492 case PIPE_FORMAT_R32_SNORM
:
493 case PIPE_FORMAT_R32G32B32A32_SSCALED
:
494 case PIPE_FORMAT_R32G32B32_SSCALED
:
495 case PIPE_FORMAT_R32G32_SSCALED
:
496 case PIPE_FORMAT_R32_SSCALED
:
497 case PIPE_FORMAT_R16G16B16A16_UNORM
:
498 case PIPE_FORMAT_R16G16B16_UNORM
:
499 case PIPE_FORMAT_R16G16_UNORM
:
500 case PIPE_FORMAT_R16_UNORM
:
501 case PIPE_FORMAT_R16G16B16A16_SNORM
:
502 case PIPE_FORMAT_R16G16B16_SNORM
:
503 case PIPE_FORMAT_R16G16_SNORM
:
504 case PIPE_FORMAT_R16_SNORM
:
505 case PIPE_FORMAT_R16G16B16A16_USCALED
:
506 case PIPE_FORMAT_R16G16B16_USCALED
:
507 case PIPE_FORMAT_R16G16_USCALED
:
508 case PIPE_FORMAT_R16_USCALED
:
509 case PIPE_FORMAT_R16G16B16A16_SSCALED
:
510 case PIPE_FORMAT_R16G16B16_SSCALED
:
511 case PIPE_FORMAT_R16G16_SSCALED
:
512 case PIPE_FORMAT_R16_SSCALED
:
513 case PIPE_FORMAT_R8G8B8A8_UNORM
:
514 case PIPE_FORMAT_R8G8B8_UNORM
:
515 case PIPE_FORMAT_R8G8_UNORM
:
516 case PIPE_FORMAT_R8_UNORM
:
517 case PIPE_FORMAT_R8G8B8A8_SNORM
:
518 case PIPE_FORMAT_R8G8B8_SNORM
:
519 case PIPE_FORMAT_R8G8_SNORM
:
520 case PIPE_FORMAT_R8_SNORM
:
521 case PIPE_FORMAT_R8G8B8A8_USCALED
:
522 case PIPE_FORMAT_R8G8B8_USCALED
:
523 case PIPE_FORMAT_R8G8_USCALED
:
524 case PIPE_FORMAT_R8_USCALED
:
525 case PIPE_FORMAT_R8G8B8A8_SSCALED
:
526 case PIPE_FORMAT_R8G8B8_SSCALED
:
527 case PIPE_FORMAT_R8G8_SSCALED
:
528 case PIPE_FORMAT_R8_SSCALED
:
529 case PIPE_FORMAT_R10G10B10A2_UNORM
:
530 case PIPE_FORMAT_B10G10R10A2_UNORM
:
531 case PIPE_FORMAT_R10G10B10A2_SNORM
:
532 case PIPE_FORMAT_B10G10R10A2_SNORM
:
533 case PIPE_FORMAT_R10G10B10A2_USCALED
:
534 case PIPE_FORMAT_B10G10R10A2_USCALED
:
535 case PIPE_FORMAT_R10G10B10A2_SSCALED
:
536 case PIPE_FORMAT_B10G10R10A2_SSCALED
:
543 /* FORMAT_NONE gets allowed for ARB_framebuffer_no_attachments's probe
544 * of FRAMEBUFFER_MAX_SAMPLES
546 if ((usage
& PIPE_BIND_RENDER_TARGET
) &&
547 format
!= PIPE_FORMAT_NONE
&&
548 !v3d_rt_format_supported(&screen
->devinfo
, format
)) {
552 if ((usage
& PIPE_BIND_SAMPLER_VIEW
) &&
553 !v3d_tex_format_supported(&screen
->devinfo
, format
)) {
557 if ((usage
& PIPE_BIND_DEPTH_STENCIL
) &&
558 !(format
== PIPE_FORMAT_S8_UINT_Z24_UNORM
||
559 format
== PIPE_FORMAT_X8Z24_UNORM
||
560 format
== PIPE_FORMAT_Z16_UNORM
||
561 format
== PIPE_FORMAT_Z32_FLOAT
||
562 format
== PIPE_FORMAT_Z32_FLOAT_S8X24_UINT
)) {
566 if ((usage
& PIPE_BIND_INDEX_BUFFER
) &&
567 !(format
== PIPE_FORMAT_I8_UINT
||
568 format
== PIPE_FORMAT_I16_UINT
||
569 format
== PIPE_FORMAT_I32_UINT
)) {
576 #define PTR_TO_UINT(x) ((unsigned)((intptr_t)(x)))
578 static unsigned handle_hash(void *key
)
580 return PTR_TO_UINT(key
);
583 static int handle_compare(void *key1
, void *key2
)
585 return PTR_TO_UINT(key1
) != PTR_TO_UINT(key2
);
589 v3d_get_device_info(struct v3d_screen
*screen
)
591 struct drm_v3d_get_param ident0
= {
592 .param
= DRM_V3D_PARAM_V3D_CORE0_IDENT0
,
594 struct drm_v3d_get_param ident1
= {
595 .param
= DRM_V3D_PARAM_V3D_CORE0_IDENT1
,
599 ret
= v3d_ioctl(screen
->fd
, DRM_IOCTL_V3D_GET_PARAM
, &ident0
);
601 fprintf(stderr
, "Couldn't get V3D core IDENT0: %s\n",
605 ret
= v3d_ioctl(screen
->fd
, DRM_IOCTL_V3D_GET_PARAM
, &ident1
);
607 fprintf(stderr
, "Couldn't get V3D core IDENT1: %s\n",
612 uint32_t major
= (ident0
.value
>> 24) & 0xff;
613 uint32_t minor
= (ident1
.value
>> 0) & 0xf;
614 screen
->devinfo
.ver
= major
* 10 + minor
;
616 screen
->devinfo
.vpm_size
= (ident1
.value
>> 28 & 0xf) * 8192;
618 int nslc
= (ident1
.value
>> 4) & 0xf;
619 int qups
= (ident1
.value
>> 8) & 0xf;
620 screen
->devinfo
.qpu_count
= nslc
* qups
;
622 switch (screen
->devinfo
.ver
) {
629 "V3D %d.%d not supported by this version of Mesa.\n",
630 screen
->devinfo
.ver
/ 10,
631 screen
->devinfo
.ver
% 10);
639 v3d_screen_get_compiler_options(struct pipe_screen
*pscreen
,
640 enum pipe_shader_ir ir
, unsigned shader
)
642 return &v3d_nir_options
;
646 v3d_screen_query_dmabuf_modifiers(struct pipe_screen
*pscreen
,
647 enum pipe_format format
, int max
,
649 unsigned int *external_only
,
653 uint64_t available_modifiers
[] = {
654 DRM_FORMAT_MOD_BROADCOM_UIF
,
655 DRM_FORMAT_MOD_LINEAR
,
657 int num_modifiers
= ARRAY_SIZE(available_modifiers
);
660 *count
= num_modifiers
;
664 *count
= MIN2(max
, num_modifiers
);
665 for (i
= 0; i
< *count
; i
++) {
666 modifiers
[i
] = available_modifiers
[i
];
668 external_only
[i
] = false;
673 v3d_screen_create(int fd
, const struct pipe_screen_config
*config
,
674 struct renderonly
*ro
)
676 struct v3d_screen
*screen
= rzalloc(NULL
, struct v3d_screen
);
677 struct pipe_screen
*pscreen
;
679 pscreen
= &screen
->base
;
681 pscreen
->destroy
= v3d_screen_destroy
;
682 pscreen
->get_param
= v3d_screen_get_param
;
683 pscreen
->get_paramf
= v3d_screen_get_paramf
;
684 pscreen
->get_shader_param
= v3d_screen_get_shader_param
;
685 pscreen
->get_compute_param
= v3d_get_compute_param
;
686 pscreen
->context_create
= v3d_context_create
;
687 pscreen
->is_format_supported
= v3d_screen_is_format_supported
;
691 screen
->ro
= renderonly_dup(ro
);
693 fprintf(stderr
, "Failed to dup renderonly object\n");
698 list_inithead(&screen
->bo_cache
.time_list
);
699 (void)mtx_init(&screen
->bo_handles_mutex
, mtx_plain
);
700 screen
->bo_handles
= util_hash_table_create(handle_hash
, handle_compare
);
702 #if defined(USE_V3D_SIMULATOR)
703 v3d_simulator_init(screen
);
706 if (!v3d_get_device_info(screen
))
709 /* We have to driCheckOption for the simulator mode to not assertion
710 * fail on not having our XML config.
712 const char *nonmsaa_name
= "v3d_nonmsaa_texture_size_limit";
713 screen
->nonmsaa_texture_size_limit
=
714 driCheckOption(config
->options
, nonmsaa_name
, DRI_BOOL
) &&
715 driQueryOptionb(config
->options
, nonmsaa_name
);
717 slab_create_parent(&screen
->transfer_pool
, sizeof(struct v3d_transfer
), 16);
719 screen
->has_csd
= false; /* until the UABI is enabled. */
721 v3d_fence_init(screen
);
723 v3d_process_debug_variable();
725 v3d_resource_screen_init(pscreen
);
727 screen
->compiler
= v3d_compiler_init(&screen
->devinfo
);
729 pscreen
->get_name
= v3d_screen_get_name
;
730 pscreen
->get_vendor
= v3d_screen_get_vendor
;
731 pscreen
->get_device_vendor
= v3d_screen_get_vendor
;
732 pscreen
->get_compiler_options
= v3d_screen_get_compiler_options
;
733 pscreen
->query_dmabuf_modifiers
= v3d_screen_query_dmabuf_modifiers
;
739 ralloc_free(pscreen
);