src/gallium/drivers/v3d/v3dx_simulator.c

   1 /*
   2  * Copyright © 2014-2017 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 /**
  25  * @file v3d_simulator_hw.c
  26  *
  27  * Implements the actual HW interaction betweeh the GL driver's VC5 simulator and the simulator.
  28  *
  29  * The register headers between V3D versions will have conflicting defines, so
  30  * all register interactions appear in this file and are compiled per V3D version
  31  * we support.
  32  */
  33
  34 #ifdef USE_V3D_SIMULATOR
  35
  36 #include "v3d_screen.h"
  37 #include "v3d_context.h"
  38 #include "v3d_simulator_wrapper.h"
  39
  40 #define HW_REGISTER_RO(x) (x)
  41 #define HW_REGISTER_RW(x) (x)
  42 #if V3D_VERSION >= 41
  43 #include "libs/core/v3d/registers/4.1.34.0/v3d.h"
  44 #else
  45 #include "libs/core/v3d/registers/3.3.0.0/v3d.h"
  46 #endif
  47
  48 #define V3D_WRITE(reg, val) v3d_hw_write_reg(v3d, reg, val)
  49 #define V3D_READ(reg) v3d_hw_read_reg(v3d, reg)
  50
  51 static void
  52 v3d_invalidate_l3(struct v3d_hw *v3d)
  53 {
  54         if (!v3d_hw_has_gca(v3d))
  55                 return;
  56
  57 #if V3D_VERSION < 40
  58         uint32_t gca_ctrl = V3D_READ(V3D_GCA_CACHE_CTRL);
  59
  60         V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl | V3D_GCA_CACHE_CTRL_FLUSH_SET);
  61         V3D_WRITE(V3D_GCA_CACHE_CTRL, gca_ctrl & ~V3D_GCA_CACHE_CTRL_FLUSH_SET);
  62 #endif
  63 }
  64
  65 /* Invalidates the L2C cache.  This is a read-only cache for uniforms and instructions. */
  66 static void
  67 v3d_invalidate_l2c(struct v3d_hw *v3d)
  68 {
  69         if (V3D_VERSION >= 33)
  70                 return;
  71
  72         V3D_WRITE(V3D_CTL_0_L2CACTL,
  73                   V3D_CTL_0_L2CACTL_L2CCLR_SET |
  74                   V3D_CTL_0_L2CACTL_L2CENA_SET);
  75 }
  76
  77 /* Invalidates texture L2 cachelines */
  78 static void
  79 v3d_invalidate_l2t(struct v3d_hw *v3d)
  80 {
  81         V3D_WRITE(V3D_CTL_0_L2TFLSTA, 0);
  82         V3D_WRITE(V3D_CTL_0_L2TFLEND, ~0);
  83         V3D_WRITE(V3D_CTL_0_L2TCACTL,
  84                   V3D_CTL_0_L2TCACTL_L2TFLS_SET |
  85                   (0 << V3D_CTL_0_L2TCACTL_L2TFLM_LSB));
  86 }
  87
  88 /* Invalidates the slice caches.  These are read-only caches. */
  89 static void
  90 v3d_invalidate_slices(struct v3d_hw *v3d)
  91 {
  92         V3D_WRITE(V3D_CTL_0_SLCACTL, ~0);
  93 }
  94
  95 static void
  96 v3d_invalidate_caches(struct v3d_hw *v3d)
  97 {
  98         v3d_invalidate_l3(v3d);
  99         v3d_invalidate_l2c(v3d);
 100         v3d_invalidate_l2t(v3d);
 101         v3d_invalidate_slices(v3d);
 102 }
 103
 104 int
 105 v3dX(simulator_submit_tfu_ioctl)(struct v3d_hw *v3d,
 106                                  struct drm_v3d_submit_tfu *args)
 107 {
 108         int last_vtct = V3D_READ(V3D_TFU_CS) & V3D_TFU_CS_CVTCT_SET;
 109
 110         V3D_WRITE(V3D_TFU_IIA, args->iia);
 111         V3D_WRITE(V3D_TFU_IIS, args->iis);
 112         V3D_WRITE(V3D_TFU_ICA, args->ica);
 113         V3D_WRITE(V3D_TFU_IUA, args->iua);
 114         V3D_WRITE(V3D_TFU_IOA, args->ioa);
 115         V3D_WRITE(V3D_TFU_IOS, args->ios);
 116         V3D_WRITE(V3D_TFU_COEF0, args->coef[0]);
 117         V3D_WRITE(V3D_TFU_COEF1, args->coef[1]);
 118         V3D_WRITE(V3D_TFU_COEF2, args->coef[2]);
 119         V3D_WRITE(V3D_TFU_COEF3, args->coef[3]);
 120
 121         V3D_WRITE(V3D_TFU_ICFG, args->icfg);
 122
 123         while ((V3D_READ(V3D_TFU_CS) & V3D_TFU_CS_CVTCT_SET) == last_vtct) {
 124                 v3d_hw_tick(v3d);
 125         }
 126
 127         return 0;
 128 }
 129
 130 int
 131 v3dX(simulator_get_param_ioctl)(struct v3d_hw *v3d,
 132                                 struct drm_v3d_get_param *args)
 133 {
 134         static const uint32_t reg_map[] = {
 135                 [DRM_V3D_PARAM_V3D_UIFCFG] = V3D_HUB_CTL_UIFCFG,
 136                 [DRM_V3D_PARAM_V3D_HUB_IDENT1] = V3D_HUB_CTL_IDENT1,
 137                 [DRM_V3D_PARAM_V3D_HUB_IDENT2] = V3D_HUB_CTL_IDENT2,
 138                 [DRM_V3D_PARAM_V3D_HUB_IDENT3] = V3D_HUB_CTL_IDENT3,
 139                 [DRM_V3D_PARAM_V3D_CORE0_IDENT0] = V3D_CTL_0_IDENT0,
 140                 [DRM_V3D_PARAM_V3D_CORE0_IDENT1] = V3D_CTL_0_IDENT1,
 141                 [DRM_V3D_PARAM_V3D_CORE0_IDENT2] = V3D_CTL_0_IDENT2,
 142         };
 143
 144         switch (args->param) {
 145         case DRM_V3D_PARAM_SUPPORTS_TFU:
 146                 args->value = 1;
 147                 return 0;
 148         }
 149
 150         if (args->param < ARRAY_SIZE(reg_map) && reg_map[args->param]) {
 151                 args->value = V3D_READ(reg_map[args->param]);
 152                 return 0;
 153         }
 154
 155         fprintf(stderr, "Unknown DRM_IOCTL_VC5_GET_PARAM(%lld)\n",
 156                 (long long)args->value);
 157         abort();
 158 }
 159
 160 void
 161 v3dX(simulator_init_regs)(struct v3d_hw *v3d)
 162 {
 163 #if V3D_VERSION == 33
 164         /* Set OVRTMUOUT to match kernel behavior.
 165          *
 166          * This means that the texture sampler uniform configuration's tmu
 167          * output type field is used, instead of using the hardware default
 168          * behavior based on the texture type.  If you want the default
 169          * behavior, you can still put "2" in the indirect texture state's
 170          * output_type field.
 171          */
 172         V3D_WRITE(V3D_CTL_0_MISCCFG, V3D_CTL_1_MISCCFG_OVRTMUOUT_SET);
 173 #endif
 174 }
 175
 176 void
 177 v3dX(simulator_submit_cl_ioctl)(struct v3d_hw *v3d,
 178                                 struct drm_v3d_submit_cl *submit,
 179                                 uint32_t gmp_ofs)
 180 {
 181         /* Completely reset the GMP. */
 182         V3D_WRITE(V3D_GMP_0_CFG,
 183                   V3D_GMP_0_CFG_PROTENABLE_SET);
 184         V3D_WRITE(V3D_GMP_0_TABLE_ADDR, gmp_ofs);
 185         V3D_WRITE(V3D_GMP_0_CLEAR_LOAD, ~0);
 186         while (V3D_READ(V3D_GMP_0_STATUS) &
 187                V3D_GMP_0_STATUS_CFG_BUSY_SET) {
 188                 ;
 189         }
 190
 191         v3d_invalidate_caches(v3d);
 192
 193         if (submit->qma) {
 194                 V3D_WRITE(V3D_CLE_0_CT0QMA, submit->qma);
 195                 V3D_WRITE(V3D_CLE_0_CT0QMS, submit->qms);
 196         }
 197 #if V3D_VERSION >= 41
 198         if (submit->qts) {
 199                 V3D_WRITE(V3D_CLE_0_CT0QTS,
 200                           V3D_CLE_0_CT0QTS_CTQTSEN_SET |
 201                           submit->qts);
 202         }
 203 #endif
 204         V3D_WRITE(V3D_CLE_0_CT0QBA, submit->bcl_start);
 205         V3D_WRITE(V3D_CLE_0_CT0QEA, submit->bcl_end);
 206
 207         /* Wait for bin to complete before firing render.  The kernel's
 208          * scheduler implements this using the GPU scheduler blocking on the
 209          * bin fence completing.  (We don't use HW semaphores).
 210          */
 211         while (V3D_READ(V3D_CLE_0_CT0CA) !=
 212                V3D_READ(V3D_CLE_0_CT0EA)) {
 213                 v3d_hw_tick(v3d);
 214         }
 215
 216         v3d_invalidate_caches(v3d);
 217
 218         V3D_WRITE(V3D_CLE_0_CT1QBA, submit->rcl_start);
 219         V3D_WRITE(V3D_CLE_0_CT1QEA, submit->rcl_end);
 220
 221         while (V3D_READ(V3D_CLE_0_CT1CA) !=
 222                V3D_READ(V3D_CLE_0_CT1EA) ||
 223                V3D_READ(V3D_CLE_1_CT1CA) !=
 224                V3D_READ(V3D_CLE_1_CT1EA)) {
 225                 v3d_hw_tick(v3d);
 226         }
 227 }
 228
 229 #endif /* USE_V3D_SIMULATOR */