src/gallium/drivers/vc4/vc4_blit.c

   1 /*
   2  * Copyright © 2015 Broadcom
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24 #include "util/u_format.h"
  25 #include "util/u_surface.h"
  26 #include "util/u_blitter.h"
  27 #include "vc4_context.h"
  28
  29 static struct pipe_surface *
  30 vc4_get_blit_surface(struct pipe_context *pctx,
  31                      struct pipe_resource *prsc, unsigned level)
  32 {
  33         struct pipe_surface tmpl;
  34
  35         memset(&tmpl, 0, sizeof(tmpl));
  36         tmpl.format = prsc->format;
  37         tmpl.u.tex.level = level;
  38         tmpl.u.tex.first_layer = 0;
  39         tmpl.u.tex.last_layer = 0;
  40
  41         return pctx->create_surface(pctx, prsc, &tmpl);
  42 }
  43
  44 static bool
  45 is_tile_unaligned(unsigned size, unsigned tile_size)
  46 {
  47         return size & (tile_size - 1);
  48 }
  49
  50 static bool
  51 vc4_tile_blit(struct pipe_context *pctx, const struct pipe_blit_info *info)
  52 {
  53         struct vc4_context *vc4 = vc4_context(pctx);
  54         bool old_msaa = vc4->msaa;
  55         int old_tile_width = vc4->tile_width;
  56         int old_tile_height = vc4->tile_height;
  57         bool msaa = (info->src.resource->nr_samples > 1 ||
  58                      info->dst.resource->nr_samples > 1);
  59         int tile_width = msaa ? 32 : 64;
  60         int tile_height = msaa ? 32 : 64;
  61
  62         if (util_format_is_depth_or_stencil(info->dst.resource->format))
  63                 return false;
  64
  65         if (info->scissor_enable)
  66                 return false;
  67
  68         if ((info->mask & PIPE_MASK_RGBA) == 0)
  69                 return false;
  70
  71         if (info->dst.box.x != info->src.box.x ||
  72             info->dst.box.y != info->src.box.y ||
  73             info->dst.box.width != info->src.box.width ||
  74             info->dst.box.height != info->src.box.height) {
  75                 return false;
  76         }
  77
  78         int dst_surface_width = u_minify(info->dst.resource->width0,
  79                                          info->dst.level);
  80         int dst_surface_height = u_minify(info->dst.resource->height0,
  81                                          info->dst.level);
  82         if (is_tile_unaligned(info->dst.box.x, tile_width) ||
  83             is_tile_unaligned(info->dst.box.y, tile_height) ||
  84             (is_tile_unaligned(info->dst.box.width, tile_width) &&
  85              info->dst.box.x + info->dst.box.width != dst_surface_width) ||
  86             (is_tile_unaligned(info->dst.box.height, tile_height) &&
  87              info->dst.box.y + info->dst.box.height != dst_surface_height)) {
  88                 return false;
  89         }
  90
  91         /* VC4_PACKET_LOAD_TILE_BUFFER_GENERAL uses the
  92          * VC4_PACKET_TILE_RENDERING_MODE_CONFIG's width (determined by our
  93          * destination surface) to determine the stride.  This may be wrong
  94          * when reading from texture miplevels > 0, which are stored in
  95          * POT-sized areas.  For MSAA, the tile addresses are computed
  96          * explicitly by the RCL, but still use the destination width to
  97          * determine the stride (which could be fixed by explicitly supplying
  98          * it in the ABI).
  99          */
 100         struct vc4_resource *rsc = vc4_resource(info->src.resource);
 101
 102         uint32_t stride;
 103
 104         if (info->src.resource->nr_samples > 1)
 105                 stride = align(dst_surface_width, 32) * 4 * rsc->cpp;
 106         else if (rsc->slices[info->src.level].tiling == VC4_TILING_FORMAT_T)
 107                 stride = align(dst_surface_width * rsc->cpp, 128);
 108         else
 109                 stride = align(dst_surface_width * rsc->cpp, 16);
 110
 111         if (stride != rsc->slices[info->src.level].stride)
 112                 return false;
 113
 114         if (info->dst.resource->format != info->src.resource->format)
 115                 return false;
 116
 117         vc4_flush(pctx);
 118
 119         if (false) {
 120                 fprintf(stderr, "RCL blit from %d,%d to %d,%d (%d,%d)\n",
 121                         info->src.box.x,
 122                         info->src.box.y,
 123                         info->dst.box.x,
 124                         info->dst.box.y,
 125                         info->dst.box.width,
 126                         info->dst.box.height);
 127         }
 128
 129         struct pipe_surface *dst_surf =
 130                 vc4_get_blit_surface(pctx, info->dst.resource, info->dst.level);
 131         struct pipe_surface *src_surf =
 132                 vc4_get_blit_surface(pctx, info->src.resource, info->src.level);
 133
 134         pipe_surface_reference(&vc4->color_read, src_surf);
 135         pipe_surface_reference(&vc4->color_write,
 136                                dst_surf->texture->nr_samples > 1 ?
 137                                NULL : dst_surf);
 138         pipe_surface_reference(&vc4->msaa_color_write,
 139                                dst_surf->texture->nr_samples > 1 ?
 140                                dst_surf : NULL);
 141         pipe_surface_reference(&vc4->zs_read, NULL);
 142         pipe_surface_reference(&vc4->zs_write, NULL);
 143         pipe_surface_reference(&vc4->msaa_zs_write, NULL);
 144
 145         vc4->draw_min_x = info->dst.box.x;
 146         vc4->draw_min_y = info->dst.box.y;
 147         vc4->draw_max_x = info->dst.box.x + info->dst.box.width;
 148         vc4->draw_max_y = info->dst.box.y + info->dst.box.height;
 149         vc4->draw_width = dst_surf->width;
 150         vc4->draw_height = dst_surf->height;
 151
 152         vc4->tile_width = tile_width;
 153         vc4->tile_height = tile_height;
 154         vc4->msaa = msaa;
 155         vc4->needs_flush = true;
 156
 157         vc4_job_submit(vc4);
 158
 159         vc4->msaa = old_msaa;
 160         vc4->tile_width = old_tile_width;
 161         vc4->tile_height = old_tile_height;
 162
 163         pipe_surface_reference(&dst_surf, NULL);
 164         pipe_surface_reference(&src_surf, NULL);
 165
 166         return true;
 167 }
 168
 169 static bool
 170 vc4_render_blit(struct pipe_context *ctx, struct pipe_blit_info *info)
 171 {
 172         struct vc4_context *vc4 = vc4_context(ctx);
 173
 174         if (!util_blitter_is_blit_supported(vc4->blitter, info)) {
 175                 fprintf(stderr, "blit unsupported %s -> %s\n",
 176                     util_format_short_name(info->src.resource->format),
 177                     util_format_short_name(info->dst.resource->format));
 178                 return false;
 179         }
 180
 181         util_blitter_save_vertex_buffer_slot(vc4->blitter, vc4->vertexbuf.vb);
 182         util_blitter_save_vertex_elements(vc4->blitter, vc4->vtx);
 183         util_blitter_save_vertex_shader(vc4->blitter, vc4->prog.bind_vs);
 184         util_blitter_save_rasterizer(vc4->blitter, vc4->rasterizer);
 185         util_blitter_save_viewport(vc4->blitter, &vc4->viewport);
 186         util_blitter_save_scissor(vc4->blitter, &vc4->scissor);
 187         util_blitter_save_fragment_shader(vc4->blitter, vc4->prog.bind_fs);
 188         util_blitter_save_blend(vc4->blitter, vc4->blend);
 189         util_blitter_save_depth_stencil_alpha(vc4->blitter, vc4->zsa);
 190         util_blitter_save_stencil_ref(vc4->blitter, &vc4->stencil_ref);
 191         util_blitter_save_sample_mask(vc4->blitter, vc4->sample_mask);
 192         util_blitter_save_framebuffer(vc4->blitter, &vc4->framebuffer);
 193         util_blitter_save_fragment_sampler_states(vc4->blitter,
 194                         vc4->fragtex.num_samplers,
 195                         (void **)vc4->fragtex.samplers);
 196         util_blitter_save_fragment_sampler_views(vc4->blitter,
 197                         vc4->fragtex.num_textures, vc4->fragtex.textures);
 198
 199         util_blitter_blit(vc4->blitter, info);
 200
 201         return true;
 202 }
 203
 204 /* Optimal hardware path for blitting pixels.
 205  * Scaling, format conversion, up- and downsampling (resolve) are allowed.
 206  */
 207 void
 208 vc4_blit(struct pipe_context *pctx, const struct pipe_blit_info *blit_info)
 209 {
 210         struct pipe_blit_info info = *blit_info;
 211
 212         if (vc4_tile_blit(pctx, blit_info))
 213                 return;
 214
 215         if (util_try_blit_via_copy_region(pctx, &info)) {
 216                 return; /* done */
 217         }
 218
 219         if (info.mask & PIPE_MASK_S) {
 220                 fprintf(stderr, "cannot blit stencil, skipping\n");
 221                 info.mask &= ~PIPE_MASK_S;
 222         }
 223
 224         vc4_render_blit(pctx, &info);
 225 }