2 * Copyright © 2015 Broadcom
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 #include "compiler/nir/nir_builder.h"
26 #include "util/u_format.h"
29 * Walks the NIR generated by TGSI-to-NIR to lower its io intrinsics into
30 * something amenable to the VC4 architecture.
32 * Currently, it split inputs, outputs, and uniforms into scalars, drops any
33 * non-position outputs in coordinate shaders, and fixes up the addressing on
34 * indirect uniform loads.
38 replace_intrinsic_with_vec4(nir_builder
*b
, nir_intrinsic_instr
*intr
,
42 /* Batch things back together into a vec4. This will get split by the
43 * later ALU scalarization pass.
45 nir_ssa_def
*vec
= nir_vec4(b
, comps
[0], comps
[1], comps
[2], comps
[3]);
47 /* Replace the old intrinsic with a reference to our reconstructed
50 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(vec
));
51 nir_instr_remove(&intr
->instr
);
55 vc4_nir_unpack_8i(nir_builder
*b
, nir_ssa_def
*src
, unsigned chan
)
57 return nir_ubitfield_extract(b
,
59 nir_imm_int(b
, 8 * chan
),
63 /** Returns the 16 bit field as a sign-extended 32-bit value. */
65 vc4_nir_unpack_16i(nir_builder
*b
, nir_ssa_def
*src
, unsigned chan
)
67 return nir_ibitfield_extract(b
,
69 nir_imm_int(b
, 16 * chan
),
73 /** Returns the 16 bit field as an unsigned 32 bit value. */
75 vc4_nir_unpack_16u(nir_builder
*b
, nir_ssa_def
*src
, unsigned chan
)
78 return nir_iand(b
, src
, nir_imm_int(b
, 0xffff));
80 return nir_ushr(b
, src
, nir_imm_int(b
, 16));
85 vc4_nir_unpack_8f(nir_builder
*b
, nir_ssa_def
*src
, unsigned chan
)
87 return nir_channel(b
, nir_unpack_unorm_4x8(b
, src
), chan
);
91 vc4_nir_get_vattr_channel_vpm(struct vc4_compile
*c
,
93 nir_ssa_def
**vpm_reads
,
95 const struct util_format_description
*desc
)
97 const struct util_format_channel_description
*chan
=
101 if (swiz
> PIPE_SWIZZLE_W
) {
102 return vc4_nir_get_swizzled_channel(b
, vpm_reads
, swiz
);
103 } else if (chan
->size
== 32 && chan
->type
== UTIL_FORMAT_TYPE_FLOAT
) {
104 return vc4_nir_get_swizzled_channel(b
, vpm_reads
, swiz
);
105 } else if (chan
->size
== 32 && chan
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
106 if (chan
->normalized
) {
108 nir_i2f(b
, vpm_reads
[swiz
]),
112 return nir_i2f(b
, vpm_reads
[swiz
]);
114 } else if (chan
->size
== 8 &&
115 (chan
->type
== UTIL_FORMAT_TYPE_UNSIGNED
||
116 chan
->type
== UTIL_FORMAT_TYPE_SIGNED
)) {
117 nir_ssa_def
*vpm
= vpm_reads
[0];
118 if (chan
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
119 temp
= nir_ixor(b
, vpm
, nir_imm_int(b
, 0x80808080));
120 if (chan
->normalized
) {
121 return nir_fsub(b
, nir_fmul(b
,
122 vc4_nir_unpack_8f(b
, temp
, swiz
),
123 nir_imm_float(b
, 2.0)),
124 nir_imm_float(b
, 1.0));
128 vc4_nir_unpack_8i(b
, temp
,
130 nir_imm_float(b
, -128.0));
133 if (chan
->normalized
) {
134 return vc4_nir_unpack_8f(b
, vpm
, swiz
);
136 return nir_i2f(b
, vc4_nir_unpack_8i(b
, vpm
, swiz
));
139 } else if (chan
->size
== 16 &&
140 (chan
->type
== UTIL_FORMAT_TYPE_UNSIGNED
||
141 chan
->type
== UTIL_FORMAT_TYPE_SIGNED
)) {
142 nir_ssa_def
*vpm
= vpm_reads
[swiz
/ 2];
144 /* Note that UNPACK_16F eats a half float, not ints, so we use
145 * UNPACK_16_I for all of these.
147 if (chan
->type
== UTIL_FORMAT_TYPE_SIGNED
) {
148 temp
= nir_i2f(b
, vc4_nir_unpack_16i(b
, vpm
, swiz
& 1));
149 if (chan
->normalized
) {
150 return nir_fmul(b
, temp
,
151 nir_imm_float(b
, 1/32768.0f
));
156 temp
= nir_i2f(b
, vc4_nir_unpack_16u(b
, vpm
, swiz
& 1));
157 if (chan
->normalized
) {
158 return nir_fmul(b
, temp
,
159 nir_imm_float(b
, 1 / 65535.0));
170 vc4_nir_lower_vertex_attr(struct vc4_compile
*c
, nir_builder
*b
,
171 nir_intrinsic_instr
*intr
)
173 b
->cursor
= nir_before_instr(&intr
->instr
);
175 int attr
= intr
->const_index
[0];
176 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
177 uint32_t attr_size
= util_format_get_blocksize(format
);
179 /* All TGSI-to-NIR inputs are vec4. */
180 assert(intr
->num_components
== 4);
182 /* We only accept direct outputs and TGSI only ever gives them to us
183 * with an offset value of 0.
185 assert(nir_src_as_const_value(intr
->src
[0]) &&
186 nir_src_as_const_value(intr
->src
[0])->u32
[0] == 0);
188 /* Generate dword loads for the VPM values (Since these intrinsics may
189 * be reordered, the actual reads will be generated at the top of the
190 * shader by ntq_setup_inputs().
192 nir_ssa_def
*vpm_reads
[4];
193 for (int i
= 0; i
< align(attr_size
, 4) / 4; i
++) {
194 nir_intrinsic_instr
*intr_comp
=
195 nir_intrinsic_instr_create(c
->s
,
196 nir_intrinsic_load_input
);
197 intr_comp
->num_components
= 1;
198 intr_comp
->const_index
[0] = intr
->const_index
[0] * 4 + i
;
199 intr_comp
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
200 nir_ssa_dest_init(&intr_comp
->instr
, &intr_comp
->dest
, 1, 32, NULL
);
201 nir_builder_instr_insert(b
, &intr_comp
->instr
);
203 vpm_reads
[i
] = &intr_comp
->dest
.ssa
;
206 bool format_warned
= false;
207 const struct util_format_description
*desc
=
208 util_format_description(format
);
210 nir_ssa_def
*dests
[4];
211 for (int i
= 0; i
< 4; i
++) {
212 uint8_t swiz
= desc
->swizzle
[i
];
213 dests
[i
] = vc4_nir_get_vattr_channel_vpm(c
, b
, vpm_reads
, swiz
,
217 if (!format_warned
) {
219 "vtx element %d unsupported type: %s\n",
220 attr
, util_format_name(format
));
221 format_warned
= true;
223 dests
[i
] = nir_imm_float(b
, 0.0);
227 replace_intrinsic_with_vec4(b
, intr
, dests
);
231 vc4_nir_lower_fs_input(struct vc4_compile
*c
, nir_builder
*b
,
232 nir_intrinsic_instr
*intr
)
234 b
->cursor
= nir_before_instr(&intr
->instr
);
236 if (intr
->const_index
[0] >= VC4_NIR_TLB_COLOR_READ_INPUT
&&
237 intr
->const_index
[0] < (VC4_NIR_TLB_COLOR_READ_INPUT
+
239 /* This doesn't need any lowering. */
243 nir_variable
*input_var
= NULL
;
244 nir_foreach_variable(var
, &c
->s
->inputs
) {
245 if (var
->data
.driver_location
== intr
->const_index
[0]) {
252 /* All TGSI-to-NIR inputs are vec4. */
253 assert(intr
->num_components
== 4);
255 /* We only accept direct inputs and TGSI only ever gives them to us
256 * with an offset value of 0.
258 assert(nir_src_as_const_value(intr
->src
[0]) &&
259 nir_src_as_const_value(intr
->src
[0])->u32
[0] == 0);
261 /* Generate scalar loads equivalent to the original VEC4. */
262 nir_ssa_def
*dests
[4];
263 for (unsigned i
= 0; i
< intr
->num_components
; i
++) {
264 nir_intrinsic_instr
*intr_comp
=
265 nir_intrinsic_instr_create(c
->s
, nir_intrinsic_load_input
);
266 intr_comp
->num_components
= 1;
267 intr_comp
->const_index
[0] = intr
->const_index
[0] * 4 + i
;
268 intr_comp
->src
[0] = nir_src_for_ssa(nir_imm_int(b
, 0));
270 nir_ssa_dest_init(&intr_comp
->instr
, &intr_comp
->dest
, 1, 32, NULL
);
271 nir_builder_instr_insert(b
, &intr_comp
->instr
);
273 dests
[i
] = &intr_comp
->dest
.ssa
;
276 if (input_var
->data
.location
>= VARYING_SLOT_VAR0
) {
277 if (c
->fs_key
->point_sprite_mask
&
278 (1 << (input_var
->data
.location
-
279 VARYING_SLOT_VAR0
))) {
280 if (!c
->fs_key
->is_points
) {
281 dests
[0] = nir_imm_float(b
, 0.0);
282 dests
[1] = nir_imm_float(b
, 0.0);
284 if (c
->fs_key
->point_coord_upper_left
) {
285 dests
[1] = nir_fsub(b
,
286 nir_imm_float(b
, 1.0),
289 dests
[2] = nir_imm_float(b
, 0.0);
290 dests
[3] = nir_imm_float(b
, 1.0);
294 replace_intrinsic_with_vec4(b
, intr
, dests
);
298 vc4_nir_lower_output(struct vc4_compile
*c
, nir_builder
*b
,
299 nir_intrinsic_instr
*intr
)
301 nir_variable
*output_var
= NULL
;
302 nir_foreach_variable(var
, &c
->s
->outputs
) {
303 if (var
->data
.driver_location
== intr
->const_index
[0]) {
310 if (c
->stage
== QSTAGE_COORD
&&
311 output_var
->data
.location
!= VARYING_SLOT_POS
&&
312 output_var
->data
.location
!= VARYING_SLOT_PSIZ
) {
313 nir_instr_remove(&intr
->instr
);
317 /* Color output is lowered by vc4_nir_lower_blend(). */
318 if (c
->stage
== QSTAGE_FRAG
&&
319 (output_var
->data
.location
== FRAG_RESULT_COLOR
||
320 output_var
->data
.location
== FRAG_RESULT_DATA0
||
321 output_var
->data
.location
== FRAG_RESULT_SAMPLE_MASK
)) {
322 intr
->const_index
[0] *= 4;
326 /* All TGSI-to-NIR outputs are VEC4. */
327 assert(intr
->num_components
== 4);
329 /* We only accept direct outputs and TGSI only ever gives them to us
330 * with an offset value of 0.
332 assert(nir_src_as_const_value(intr
->src
[1]) &&
333 nir_src_as_const_value(intr
->src
[1])->u32
[0] == 0);
335 b
->cursor
= nir_before_instr(&intr
->instr
);
337 for (unsigned i
= 0; i
< intr
->num_components
; i
++) {
338 nir_intrinsic_instr
*intr_comp
=
339 nir_intrinsic_instr_create(c
->s
, nir_intrinsic_store_output
);
340 intr_comp
->num_components
= 1;
341 intr_comp
->const_index
[0] = intr
->const_index
[0] * 4 + i
;
343 assert(intr
->src
[0].is_ssa
);
345 nir_src_for_ssa(nir_channel(b
, intr
->src
[0].ssa
, i
));
346 intr_comp
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
347 nir_builder_instr_insert(b
, &intr_comp
->instr
);
350 nir_instr_remove(&intr
->instr
);
354 vc4_nir_lower_uniform(struct vc4_compile
*c
, nir_builder
*b
,
355 nir_intrinsic_instr
*intr
)
357 /* All TGSI-to-NIR uniform loads are vec4, but we need byte offsets
360 if (intr
->num_components
== 1)
362 assert(intr
->num_components
== 4);
364 b
->cursor
= nir_before_instr(&intr
->instr
);
366 /* Generate scalar loads equivalent to the original VEC4. */
367 nir_ssa_def
*dests
[4];
368 for (unsigned i
= 0; i
< intr
->num_components
; i
++) {
369 nir_intrinsic_instr
*intr_comp
=
370 nir_intrinsic_instr_create(c
->s
, intr
->intrinsic
);
371 intr_comp
->num_components
= 1;
372 nir_ssa_dest_init(&intr_comp
->instr
, &intr_comp
->dest
, 1, 32, NULL
);
374 /* Convert the uniform offset to bytes. If it happens to be a
375 * constant, constant-folding will clean up the shift for us.
377 intr_comp
->const_index
[0] = (intr
->const_index
[0] * 16 + i
* 4);
380 nir_src_for_ssa(nir_ishl(b
, intr
->src
[0].ssa
,
383 dests
[i
] = &intr_comp
->dest
.ssa
;
385 nir_builder_instr_insert(b
, &intr_comp
->instr
);
388 replace_intrinsic_with_vec4(b
, intr
, dests
);
392 vc4_nir_lower_io_instr(struct vc4_compile
*c
, nir_builder
*b
,
393 struct nir_instr
*instr
)
395 if (instr
->type
!= nir_instr_type_intrinsic
)
397 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
399 switch (intr
->intrinsic
) {
400 case nir_intrinsic_load_input
:
401 if (c
->stage
== QSTAGE_FRAG
)
402 vc4_nir_lower_fs_input(c
, b
, intr
);
404 vc4_nir_lower_vertex_attr(c
, b
, intr
);
407 case nir_intrinsic_store_output
:
408 vc4_nir_lower_output(c
, b
, intr
);
411 case nir_intrinsic_load_uniform
:
412 vc4_nir_lower_uniform(c
, b
, intr
);
415 case nir_intrinsic_load_user_clip_plane
:
422 vc4_nir_lower_io_impl(struct vc4_compile
*c
, nir_function_impl
*impl
)
425 nir_builder_init(&b
, impl
);
427 nir_foreach_block(block
, impl
) {
428 nir_foreach_instr_safe(instr
, block
)
429 vc4_nir_lower_io_instr(c
, &b
, instr
);
432 nir_metadata_preserve(impl
, nir_metadata_block_index
|
433 nir_metadata_dominance
);
439 vc4_nir_lower_io(nir_shader
*s
, struct vc4_compile
*c
)
441 nir_foreach_function(function
, s
) {
443 vc4_nir_lower_io_impl(c
, function
->impl
);