2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "util/u_format.h"
27 #include "util/crc32.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "compiler/nir_types.h"
37 #include "nir/tgsi_to_nir.h"
38 #include "vc4_context.h"
43 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
);
45 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
48 type_size(const struct glsl_type
*type
)
50 return glsl_count_attribute_slots(type
, false);
54 resize_qreg_array(struct vc4_compile
*c
,
59 if (*size
>= decl_size
)
62 uint32_t old_size
= *size
;
63 *size
= MAX2(*size
* 2, decl_size
);
64 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
66 fprintf(stderr
, "Malloc failure\n");
70 for (uint32_t i
= old_size
; i
< *size
; i
++)
71 (*regs
)[i
] = c
->undef
;
75 ntq_emit_thrsw(struct vc4_compile
*c
)
80 /* Always thread switch after each texture operation for now.
82 * We could do better by batching a bunch of texture fetches up and
83 * then doing one thread switch and collecting all their results
86 qir_emit_nondef(c
, qir_inst(QOP_THRSW
, c
->undef
,
88 c
->last_thrsw_at_top_level
= (c
->execute
.file
== QFILE_NULL
);
92 indirect_uniform_load(struct vc4_compile
*c
, nir_intrinsic_instr
*intr
)
94 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
95 uint32_t offset
= nir_intrinsic_base(intr
);
96 struct vc4_compiler_ubo_range
*range
= NULL
;
98 for (i
= 0; i
< c
->num_uniform_ranges
; i
++) {
99 range
= &c
->ubo_ranges
[i
];
100 if (offset
>= range
->src_offset
&&
101 offset
< range
->src_offset
+ range
->size
) {
105 /* The driver-location-based offset always has to be within a declared
111 range
->dst_offset
= c
->next_ubo_dst_offset
;
112 c
->next_ubo_dst_offset
+= range
->size
;
116 offset
-= range
->src_offset
;
118 /* Adjust for where we stored the TGSI register base. */
119 indirect_offset
= qir_ADD(c
, indirect_offset
,
120 qir_uniform_ui(c
, (range
->dst_offset
+
123 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
124 indirect_offset
= qir_MAX(c
, indirect_offset
, qir_uniform_ui(c
, 0));
125 indirect_offset
= qir_MIN_NOIMM(c
, indirect_offset
,
126 qir_uniform_ui(c
, (range
->dst_offset
+
129 qir_ADD_dest(c
, qir_reg(QFILE_TEX_S_DIRECT
, 0),
131 qir_uniform(c
, QUNIFORM_UBO_ADDR
, 0));
133 c
->num_texture_samples
++;
137 return qir_TEX_RESULT(c
);
141 vc4_ubo_load(struct vc4_compile
*c
, nir_intrinsic_instr
*intr
)
143 nir_const_value
*buffer_index
=
144 nir_src_as_const_value(intr
->src
[0]);
145 assert(buffer_index
->u32
[0] == 1);
146 assert(c
->stage
== QSTAGE_FRAG
);
148 struct qreg offset
= ntq_get_src(c
, intr
->src
[1], 0);
150 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
151 offset
= qir_MAX(c
, offset
, qir_uniform_ui(c
, 0));
152 offset
= qir_MIN_NOIMM(c
, offset
,
153 qir_uniform_ui(c
, c
->fs_key
->ubo_1_size
- 4));
155 qir_ADD_dest(c
, qir_reg(QFILE_TEX_S_DIRECT
, 0),
157 qir_uniform(c
, QUNIFORM_UBO_ADDR
, buffer_index
->u32
[0]));
159 c
->num_texture_samples
++;
163 return qir_TEX_RESULT(c
);
167 vc4_nir_get_swizzled_channel(nir_builder
*b
, nir_ssa_def
**srcs
, int swiz
)
171 case PIPE_SWIZZLE_NONE
:
172 fprintf(stderr
, "warning: unknown swizzle\n");
175 return nir_imm_float(b
, 0.0);
177 return nir_imm_float(b
, 1.0);
187 ntq_init_ssa_def(struct vc4_compile
*c
, nir_ssa_def
*def
)
189 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
190 def
->num_components
);
191 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
196 * This function is responsible for getting QIR results into the associated
197 * storage for a NIR instruction.
199 * If it's a NIR SSA def, then we just set the associated hash table entry to
202 * If it's a NIR reg, then we need to update the existing qreg assigned to the
203 * NIR destination with the incoming value. To do that without introducing
204 * new MOVs, we require that the incoming qreg either be a uniform, or be
205 * SSA-defined by the previous QIR instruction in the block and rewritable by
206 * this function. That lets us sneak ahead and insert the SF flag beforehand
207 * (knowing that the previous instruction doesn't depend on flags) and rewrite
208 * its destination to be the NIR reg's destination
211 ntq_store_dest(struct vc4_compile
*c
, nir_dest
*dest
, int chan
,
214 struct qinst
*last_inst
= NULL
;
215 if (!list_empty(&c
->cur_block
->instructions
))
216 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
218 assert(result
.file
== QFILE_UNIF
||
219 (result
.file
== QFILE_TEMP
&&
220 last_inst
&& last_inst
== c
->defs
[result
.index
]));
223 assert(chan
< dest
->ssa
.num_components
);
226 struct hash_entry
*entry
=
227 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
232 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
234 qregs
[chan
] = result
;
236 nir_register
*reg
= dest
->reg
.reg
;
237 assert(dest
->reg
.base_offset
== 0);
238 assert(reg
->num_array_elems
== 0);
239 struct hash_entry
*entry
=
240 _mesa_hash_table_search(c
->def_ht
, reg
);
241 struct qreg
*qregs
= entry
->data
;
243 /* Insert a MOV if the source wasn't an SSA def in the
244 * previous instruction.
246 if (result
.file
== QFILE_UNIF
) {
247 result
= qir_MOV(c
, result
);
248 last_inst
= c
->defs
[result
.index
];
251 /* We know they're both temps, so just rewrite index. */
252 c
->defs
[last_inst
->dst
.index
] = NULL
;
253 last_inst
->dst
.index
= qregs
[chan
].index
;
255 /* If we're in control flow, then make this update of the reg
256 * conditional on the execution mask.
258 if (c
->execute
.file
!= QFILE_NULL
) {
259 last_inst
->dst
.index
= qregs
[chan
].index
;
261 /* Set the flags to the current exec mask. To insert
262 * the SF, we temporarily remove our SSA instruction.
264 list_del(&last_inst
->link
);
265 qir_SF(c
, c
->execute
);
266 list_addtail(&last_inst
->link
,
267 &c
->cur_block
->instructions
);
269 last_inst
->cond
= QPU_COND_ZS
;
270 last_inst
->cond_is_exec_mask
= true;
276 ntq_get_dest(struct vc4_compile
*c
, nir_dest
*dest
)
279 struct qreg
*qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
280 for (int i
= 0; i
< dest
->ssa
.num_components
; i
++)
284 nir_register
*reg
= dest
->reg
.reg
;
285 assert(dest
->reg
.base_offset
== 0);
286 assert(reg
->num_array_elems
== 0);
287 struct hash_entry
*entry
=
288 _mesa_hash_table_search(c
->def_ht
, reg
);
294 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
)
296 struct hash_entry
*entry
;
298 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
299 assert(i
< src
.ssa
->num_components
);
301 nir_register
*reg
= src
.reg
.reg
;
302 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
303 assert(reg
->num_array_elems
== 0);
304 assert(src
.reg
.base_offset
== 0);
305 assert(i
< reg
->num_components
);
308 struct qreg
*qregs
= entry
->data
;
313 ntq_get_alu_src(struct vc4_compile
*c
, nir_alu_instr
*instr
,
316 assert(util_is_power_of_two(instr
->dest
.write_mask
));
317 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
318 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
319 instr
->src
[src
].swizzle
[chan
]);
321 assert(!instr
->src
[src
].abs
);
322 assert(!instr
->src
[src
].negate
);
327 static inline struct qreg
328 qir_SAT(struct vc4_compile
*c
, struct qreg val
)
331 qir_FMIN(c
, val
, qir_uniform_f(c
, 1.0)),
332 qir_uniform_f(c
, 0.0));
336 ntq_rcp(struct vc4_compile
*c
, struct qreg x
)
338 struct qreg r
= qir_RCP(c
, x
);
340 /* Apply a Newton-Raphson step to improve the accuracy. */
341 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
342 qir_uniform_f(c
, 2.0),
349 ntq_rsq(struct vc4_compile
*c
, struct qreg x
)
351 struct qreg r
= qir_RSQ(c
, x
);
353 /* Apply a Newton-Raphson step to improve the accuracy. */
354 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
355 qir_uniform_f(c
, 1.5),
357 qir_uniform_f(c
, 0.5),
359 qir_FMUL(c
, r
, r
)))));
365 ntq_umul(struct vc4_compile
*c
, struct qreg src0
, struct qreg src1
)
367 struct qreg src0_hi
= qir_SHR(c
, src0
,
368 qir_uniform_ui(c
, 24));
369 struct qreg src1_hi
= qir_SHR(c
, src1
,
370 qir_uniform_ui(c
, 24));
372 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1
);
373 struct qreg lohi
= qir_MUL24(c
, src0
, src1_hi
);
374 struct qreg lolo
= qir_MUL24(c
, src0
, src1
);
376 return qir_ADD(c
, lolo
, qir_SHL(c
,
377 qir_ADD(c
, hilo
, lohi
),
378 qir_uniform_ui(c
, 24)));
382 ntq_scale_depth_texture(struct vc4_compile
*c
, struct qreg src
)
384 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, src
,
385 qir_uniform_ui(c
, 8)));
386 return qir_FMUL(c
, depthf
, qir_uniform_f(c
, 1.0f
/0xffffff));
390 * Emits a lowered TXF_MS from an MSAA texture.
392 * The addressing math has been lowered in NIR, and now we just need to read
396 ntq_emit_txf(struct vc4_compile
*c
, nir_tex_instr
*instr
)
398 uint32_t tile_width
= 32;
399 uint32_t tile_height
= 32;
400 uint32_t tile_size
= (tile_height
* tile_width
*
401 VC4_MAX_SAMPLES
* sizeof(uint32_t));
403 unsigned unit
= instr
->texture_index
;
404 uint32_t w
= align(c
->key
->tex
[unit
].msaa_width
, tile_width
);
405 uint32_t w_tiles
= w
/ tile_width
;
406 uint32_t h
= align(c
->key
->tex
[unit
].msaa_height
, tile_height
);
407 uint32_t h_tiles
= h
/ tile_height
;
408 uint32_t size
= w_tiles
* h_tiles
* tile_size
;
411 assert(instr
->num_srcs
== 1);
412 assert(instr
->src
[0].src_type
== nir_tex_src_coord
);
413 addr
= ntq_get_src(c
, instr
->src
[0].src
, 0);
415 /* Perform the clamping required by kernel validation. */
416 addr
= qir_MAX(c
, addr
, qir_uniform_ui(c
, 0));
417 addr
= qir_MIN_NOIMM(c
, addr
, qir_uniform_ui(c
, size
- 4));
419 qir_ADD_dest(c
, qir_reg(QFILE_TEX_S_DIRECT
, 0),
420 addr
, qir_uniform(c
, QUNIFORM_TEXTURE_MSAA_ADDR
, unit
));
424 struct qreg tex
= qir_TEX_RESULT(c
);
425 c
->num_texture_samples
++;
427 enum pipe_format format
= c
->key
->tex
[unit
].format
;
428 if (util_format_is_depth_or_stencil(format
)) {
429 struct qreg scaled
= ntq_scale_depth_texture(c
, tex
);
430 for (int i
= 0; i
< 4; i
++)
431 ntq_store_dest(c
, &instr
->dest
, i
, qir_MOV(c
, scaled
));
433 for (int i
= 0; i
< 4; i
++)
434 ntq_store_dest(c
, &instr
->dest
, i
,
435 qir_UNPACK_8_F(c
, tex
, i
));
440 ntq_emit_tex(struct vc4_compile
*c
, nir_tex_instr
*instr
)
442 struct qreg s
, t
, r
, lod
, compare
;
443 bool is_txb
= false, is_txl
= false;
444 unsigned unit
= instr
->texture_index
;
446 if (instr
->op
== nir_texop_txf
) {
447 ntq_emit_txf(c
, instr
);
451 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
452 switch (instr
->src
[i
].src_type
) {
453 case nir_tex_src_coord
:
454 s
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
455 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
)
456 t
= qir_uniform_f(c
, 0.5);
458 t
= ntq_get_src(c
, instr
->src
[i
].src
, 1);
459 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
460 r
= ntq_get_src(c
, instr
->src
[i
].src
, 2);
462 case nir_tex_src_bias
:
463 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
466 case nir_tex_src_lod
:
467 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
470 case nir_tex_src_comparator
:
471 compare
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
474 unreachable("unknown texture source");
478 if (c
->stage
!= QSTAGE_FRAG
&& !is_txl
) {
479 /* From the GLSL 1.20 spec:
481 * "If it is mip-mapped and running on the vertex shader,
482 * then the base texture is used."
485 lod
= qir_uniform_ui(c
, 0);
488 if (c
->key
->tex
[unit
].force_first_level
) {
489 lod
= qir_uniform(c
, QUNIFORM_TEXTURE_FIRST_LEVEL
, unit
);
494 struct qreg texture_u
[] = {
495 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
),
496 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
, unit
),
497 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
498 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
500 uint32_t next_texture_u
= 0;
502 /* There is no native support for GL texture rectangle coordinates, so
503 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
506 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
) {
508 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_X
, unit
));
510 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_Y
, unit
));
513 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
|| is_txl
) {
514 texture_u
[2] = qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P2
,
515 unit
| (is_txl
<< 16));
519 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
520 tmu
= qir_MOV_dest(c
, qir_reg(QFILE_TEX_R
, 0), r
);
521 tmu
->src
[qir_get_tex_uniform_src(tmu
)] =
522 texture_u
[next_texture_u
++];
523 } else if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
524 c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
||
525 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
526 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
527 tmu
= qir_MOV_dest(c
, qir_reg(QFILE_TEX_R
, 0),
528 qir_uniform(c
, QUNIFORM_TEXTURE_BORDER_COLOR
,
530 tmu
->src
[qir_get_tex_uniform_src(tmu
)] =
531 texture_u
[next_texture_u
++];
534 if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
) {
538 if (c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
542 tmu
= qir_MOV_dest(c
, qir_reg(QFILE_TEX_T
, 0), t
);
543 tmu
->src
[qir_get_tex_uniform_src(tmu
)] =
544 texture_u
[next_texture_u
++];
546 if (is_txl
|| is_txb
) {
547 tmu
= qir_MOV_dest(c
, qir_reg(QFILE_TEX_B
, 0), lod
);
548 tmu
->src
[qir_get_tex_uniform_src(tmu
)] =
549 texture_u
[next_texture_u
++];
552 tmu
= qir_MOV_dest(c
, qir_reg(QFILE_TEX_S
, 0), s
);
553 tmu
->src
[qir_get_tex_uniform_src(tmu
)] = texture_u
[next_texture_u
++];
555 c
->num_texture_samples
++;
559 struct qreg tex
= qir_TEX_RESULT(c
);
561 enum pipe_format format
= c
->key
->tex
[unit
].format
;
563 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
);
564 if (util_format_is_depth_or_stencil(format
)) {
565 struct qreg normalized
= ntq_scale_depth_texture(c
, tex
);
566 struct qreg depth_output
;
568 struct qreg u0
= qir_uniform_f(c
, 0.0f
);
569 struct qreg u1
= qir_uniform_f(c
, 1.0f
);
570 if (c
->key
->tex
[unit
].compare_mode
) {
571 /* From the GL_ARB_shadow spec:
573 * "Let Dt (D subscript t) be the depth texture
574 * value, in the range [0, 1]. Let R be the
575 * interpolated texture coordinate clamped to the
578 compare
= qir_SAT(c
, compare
);
580 switch (c
->key
->tex
[unit
].compare_func
) {
581 case PIPE_FUNC_NEVER
:
582 depth_output
= qir_uniform_f(c
, 0.0f
);
584 case PIPE_FUNC_ALWAYS
:
587 case PIPE_FUNC_EQUAL
:
588 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
589 depth_output
= qir_SEL(c
, QPU_COND_ZS
, u1
, u0
);
591 case PIPE_FUNC_NOTEQUAL
:
592 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
593 depth_output
= qir_SEL(c
, QPU_COND_ZC
, u1
, u0
);
595 case PIPE_FUNC_GREATER
:
596 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
597 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
599 case PIPE_FUNC_GEQUAL
:
600 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
601 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
604 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
605 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
607 case PIPE_FUNC_LEQUAL
:
608 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
609 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
613 depth_output
= normalized
;
616 for (int i
= 0; i
< 4; i
++)
617 dest
[i
] = depth_output
;
619 for (int i
= 0; i
< 4; i
++)
620 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
625 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
629 ntq_ffract(struct vc4_compile
*c
, struct qreg src
)
631 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
632 struct qreg diff
= qir_FSUB(c
, src
, trunc
);
635 qir_FADD_dest(c
, diff
,
636 diff
, qir_uniform_f(c
, 1.0))->cond
= QPU_COND_NS
;
638 return qir_MOV(c
, diff
);
642 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
646 ntq_ffloor(struct vc4_compile
*c
, struct qreg src
)
648 struct qreg result
= qir_ITOF(c
, qir_FTOI(c
, src
));
650 /* This will be < 0 if we truncated and the truncation was of a value
651 * that was < 0 in the first place.
653 qir_SF(c
, qir_FSUB(c
, src
, result
));
655 struct qinst
*sub
= qir_FSUB_dest(c
, result
,
656 result
, qir_uniform_f(c
, 1.0));
657 sub
->cond
= QPU_COND_NS
;
659 return qir_MOV(c
, result
);
663 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
667 ntq_fceil(struct vc4_compile
*c
, struct qreg src
)
669 struct qreg result
= qir_ITOF(c
, qir_FTOI(c
, src
));
671 /* This will be < 0 if we truncated and the truncation was of a value
672 * that was > 0 in the first place.
674 qir_SF(c
, qir_FSUB(c
, result
, src
));
676 qir_FADD_dest(c
, result
,
677 result
, qir_uniform_f(c
, 1.0))->cond
= QPU_COND_NS
;
679 return qir_MOV(c
, result
);
683 ntq_fsin(struct vc4_compile
*c
, struct qreg src
)
687 pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
688 -pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
689 pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
690 -pow(2.0 * M_PI
, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
693 struct qreg scaled_x
=
696 qir_uniform_f(c
, 1.0 / (M_PI
* 2.0)));
698 struct qreg x
= qir_FADD(c
,
699 ntq_ffract(c
, scaled_x
),
700 qir_uniform_f(c
, -0.5));
701 struct qreg x2
= qir_FMUL(c
, x
, x
);
702 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
703 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
704 x
= qir_FMUL(c
, x
, x2
);
709 qir_uniform_f(c
, coeff
[i
])));
715 ntq_fcos(struct vc4_compile
*c
, struct qreg src
)
719 pow(2.0 * M_PI
, 2) / (2 * 1),
720 -pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
721 pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
722 -pow(2.0 * M_PI
, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
723 pow(2.0 * M_PI
, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
726 struct qreg scaled_x
=
728 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
729 struct qreg x_frac
= qir_FADD(c
,
730 ntq_ffract(c
, scaled_x
),
731 qir_uniform_f(c
, -0.5));
733 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
734 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
735 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
736 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
738 x
= qir_FMUL(c
, x
, x2
);
740 struct qreg mul
= qir_FMUL(c
,
742 qir_uniform_f(c
, coeff
[i
]));
746 sum
= qir_FADD(c
, sum
, mul
);
752 ntq_fsign(struct vc4_compile
*c
, struct qreg src
)
754 struct qreg t
= qir_get_temp(c
);
757 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 0.0));
758 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 1.0))->cond
= QPU_COND_ZC
;
759 qir_MOV_dest(c
, t
, qir_uniform_f(c
, -1.0))->cond
= QPU_COND_NS
;
760 return qir_MOV(c
, t
);
764 emit_vertex_input(struct vc4_compile
*c
, int attr
)
766 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
767 uint32_t attr_size
= util_format_get_blocksize(format
);
769 c
->vattr_sizes
[attr
] = align(attr_size
, 4);
770 for (int i
= 0; i
< align(attr_size
, 4) / 4; i
++) {
771 c
->inputs
[attr
* 4 + i
] =
772 qir_MOV(c
, qir_reg(QFILE_VPM
, attr
* 4 + i
));
778 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
780 c
->inputs
[attr
* 4 + 0] = qir_ITOF(c
, qir_reg(QFILE_FRAG_X
, 0));
781 c
->inputs
[attr
* 4 + 1] = qir_ITOF(c
, qir_reg(QFILE_FRAG_Y
, 0));
782 c
->inputs
[attr
* 4 + 2] =
784 qir_ITOF(c
, qir_FRAG_Z(c
)),
785 qir_uniform_f(c
, 1.0 / 0xffffff));
786 c
->inputs
[attr
* 4 + 3] = qir_RCP(c
, qir_FRAG_W(c
));
790 emit_fragment_varying(struct vc4_compile
*c
, gl_varying_slot slot
,
793 uint32_t i
= c
->num_input_slots
++;
799 if (c
->num_input_slots
>= c
->input_slots_array_size
) {
800 c
->input_slots_array_size
=
801 MAX2(4, c
->input_slots_array_size
* 2);
803 c
->input_slots
= reralloc(c
, c
->input_slots
,
804 struct vc4_varying_slot
,
805 c
->input_slots_array_size
);
808 c
->input_slots
[i
].slot
= slot
;
809 c
->input_slots
[i
].swizzle
= swizzle
;
811 return qir_VARY_ADD_C(c
, qir_FMUL(c
, vary
, qir_FRAG_W(c
)));
815 emit_fragment_input(struct vc4_compile
*c
, int attr
, gl_varying_slot slot
)
817 for (int i
= 0; i
< 4; i
++) {
818 c
->inputs
[attr
* 4 + i
] =
819 emit_fragment_varying(c
, slot
, i
);
825 add_output(struct vc4_compile
*c
,
826 uint32_t decl_offset
,
830 uint32_t old_array_size
= c
->outputs_array_size
;
831 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
834 if (old_array_size
!= c
->outputs_array_size
) {
835 c
->output_slots
= reralloc(c
,
837 struct vc4_varying_slot
,
838 c
->outputs_array_size
);
841 c
->output_slots
[decl_offset
].slot
= slot
;
842 c
->output_slots
[decl_offset
].swizzle
= swizzle
;
846 declare_uniform_range(struct vc4_compile
*c
, uint32_t start
, uint32_t size
)
848 unsigned array_id
= c
->num_uniform_ranges
++;
849 if (array_id
>= c
->ubo_ranges_array_size
) {
850 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
852 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
853 struct vc4_compiler_ubo_range
,
854 c
->ubo_ranges_array_size
);
857 c
->ubo_ranges
[array_id
].dst_offset
= 0;
858 c
->ubo_ranges
[array_id
].src_offset
= start
;
859 c
->ubo_ranges
[array_id
].size
= size
;
860 c
->ubo_ranges
[array_id
].used
= false;
864 ntq_src_is_only_ssa_def_user(nir_src
*src
)
869 if (!list_empty(&src
->ssa
->if_uses
))
872 return (src
->ssa
->uses
.next
== &src
->use_link
&&
873 src
->ssa
->uses
.next
->next
== &src
->ssa
->uses
);
877 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
880 * However, as an optimization, it tries to find the instructions generating
881 * the sources to be packed and just emit the pack flag there, if possible.
884 ntq_emit_pack_unorm_4x8(struct vc4_compile
*c
, nir_alu_instr
*instr
)
886 struct qreg result
= qir_get_temp(c
);
887 struct nir_alu_instr
*vec4
= NULL
;
889 /* If packing from a vec4 op (as expected), identify it so that we can
890 * peek back at what generated its sources.
892 if (instr
->src
[0].src
.is_ssa
&&
893 instr
->src
[0].src
.ssa
->parent_instr
->type
== nir_instr_type_alu
&&
894 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
)->op
==
896 vec4
= nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
899 /* If the pack is replicating the same channel 4 times, use the 8888
900 * pack flag. This is common for blending using the alpha
903 if (instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[1] &&
904 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[2] &&
905 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[3]) {
906 struct qreg rep
= ntq_get_src(c
,
908 instr
->src
[0].swizzle
[0]);
909 ntq_store_dest(c
, &instr
->dest
.dest
, 0, qir_PACK_8888_F(c
, rep
));
913 for (int i
= 0; i
< 4; i
++) {
914 int swiz
= instr
->src
[0].swizzle
[i
];
917 src
= ntq_get_src(c
, vec4
->src
[swiz
].src
,
918 vec4
->src
[swiz
].swizzle
[0]);
920 src
= ntq_get_src(c
, instr
->src
[0].src
, swiz
);
924 ntq_src_is_only_ssa_def_user(&vec4
->src
[swiz
].src
) &&
925 src
.file
== QFILE_TEMP
&&
926 c
->defs
[src
.index
] &&
927 qir_is_mul(c
->defs
[src
.index
]) &&
928 !c
->defs
[src
.index
]->dst
.pack
) {
929 struct qinst
*rewrite
= c
->defs
[src
.index
];
930 c
->defs
[src
.index
] = NULL
;
931 rewrite
->dst
= result
;
932 rewrite
->dst
.pack
= QPU_PACK_MUL_8A
+ i
;
936 qir_PACK_8_F(c
, result
, src
, i
);
939 ntq_store_dest(c
, &instr
->dest
.dest
, 0, qir_MOV(c
, result
));
942 /** Handles sign-extended bitfield extracts for 16 bits. */
944 ntq_emit_ibfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
947 assert(bits
.file
== QFILE_UNIF
&&
948 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
949 c
->uniform_data
[bits
.index
] == 16);
951 assert(offset
.file
== QFILE_UNIF
&&
952 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
953 int offset_bit
= c
->uniform_data
[offset
.index
];
954 assert(offset_bit
% 16 == 0);
956 return qir_UNPACK_16_I(c
, base
, offset_bit
/ 16);
959 /** Handles unsigned bitfield extracts for 8 bits. */
961 ntq_emit_ubfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
964 assert(bits
.file
== QFILE_UNIF
&&
965 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
966 c
->uniform_data
[bits
.index
] == 8);
968 assert(offset
.file
== QFILE_UNIF
&&
969 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
970 int offset_bit
= c
->uniform_data
[offset
.index
];
971 assert(offset_bit
% 8 == 0);
973 return qir_UNPACK_8_I(c
, base
, offset_bit
/ 8);
977 * If compare_instr is a valid comparison instruction, emits the
978 * compare_instr's comparison and returns the sel_instr's return value based
979 * on the compare_instr's result.
982 ntq_emit_comparison(struct vc4_compile
*c
, struct qreg
*dest
,
983 nir_alu_instr
*compare_instr
,
984 nir_alu_instr
*sel_instr
)
988 switch (compare_instr
->op
) {
1014 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
1015 struct qreg src1
= ntq_get_alu_src(c
, compare_instr
, 1);
1017 unsigned unsized_type
=
1018 nir_alu_type_get_base_type(nir_op_infos
[compare_instr
->op
].input_types
[0]);
1019 if (unsized_type
== nir_type_float
)
1020 qir_SF(c
, qir_FSUB(c
, src0
, src1
));
1022 qir_SF(c
, qir_SUB(c
, src0
, src1
));
1024 switch (sel_instr
->op
) {
1029 *dest
= qir_SEL(c
, cond
,
1030 qir_uniform_f(c
, 1.0), qir_uniform_f(c
, 0.0));
1034 *dest
= qir_SEL(c
, cond
,
1035 ntq_get_alu_src(c
, sel_instr
, 1),
1036 ntq_get_alu_src(c
, sel_instr
, 2));
1040 *dest
= qir_SEL(c
, cond
,
1041 qir_uniform_ui(c
, ~0), qir_uniform_ui(c
, 0));
1045 /* Make the temporary for nir_store_dest(). */
1046 *dest
= qir_MOV(c
, *dest
);
1052 * Attempts to fold a comparison generating a boolean result into the
1053 * condition code for selecting between two values, instead of comparing the
1054 * boolean result against 0 to generate the condition code.
1056 static struct qreg
ntq_emit_bcsel(struct vc4_compile
*c
, nir_alu_instr
*instr
,
1059 if (!instr
->src
[0].src
.is_ssa
)
1061 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
1063 nir_alu_instr
*compare
=
1064 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
1069 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
1074 return qir_MOV(c
, qir_SEL(c
, QPU_COND_NS
, src
[1], src
[2]));
1078 ntq_fddx(struct vc4_compile
*c
, struct qreg src
)
1080 /* Make sure that we have a bare temp to use for MUL rotation, so it
1081 * can be allocated to an accumulator.
1083 if (src
.pack
|| src
.file
!= QFILE_TEMP
)
1084 src
= qir_MOV(c
, src
);
1086 struct qreg from_left
= qir_ROT_MUL(c
, src
, 1);
1087 struct qreg from_right
= qir_ROT_MUL(c
, src
, 15);
1089 /* Distinguish left/right pixels of the quad. */
1090 qir_SF(c
, qir_AND(c
, qir_reg(QFILE_QPU_ELEMENT
, 0),
1091 qir_uniform_ui(c
, 1)));
1093 return qir_MOV(c
, qir_SEL(c
, QPU_COND_ZS
,
1094 qir_FSUB(c
, from_right
, src
),
1095 qir_FSUB(c
, src
, from_left
)));
1099 ntq_fddy(struct vc4_compile
*c
, struct qreg src
)
1101 if (src
.pack
|| src
.file
!= QFILE_TEMP
)
1102 src
= qir_MOV(c
, src
);
1104 struct qreg from_bottom
= qir_ROT_MUL(c
, src
, 2);
1105 struct qreg from_top
= qir_ROT_MUL(c
, src
, 14);
1107 /* Distinguish top/bottom pixels of the quad. */
1108 qir_SF(c
, qir_AND(c
,
1109 qir_reg(QFILE_QPU_ELEMENT
, 0),
1110 qir_uniform_ui(c
, 2)));
1112 return qir_MOV(c
, qir_SEL(c
, QPU_COND_ZS
,
1113 qir_FSUB(c
, from_top
, src
),
1114 qir_FSUB(c
, src
, from_bottom
)));
1118 ntq_emit_alu(struct vc4_compile
*c
, nir_alu_instr
*instr
)
1120 /* This should always be lowered to ALU operations for VC4. */
1121 assert(!instr
->dest
.saturate
);
1123 /* Vectors are special in that they have non-scalarized writemasks,
1124 * and just take the first swizzle channel for each argument in order
1125 * into each writemask channel.
1127 if (instr
->op
== nir_op_vec2
||
1128 instr
->op
== nir_op_vec3
||
1129 instr
->op
== nir_op_vec4
) {
1130 struct qreg srcs
[4];
1131 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1132 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
1133 instr
->src
[i
].swizzle
[0]);
1134 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1135 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
1136 qir_MOV(c
, srcs
[i
]));
1140 if (instr
->op
== nir_op_pack_unorm_4x8
) {
1141 ntq_emit_pack_unorm_4x8(c
, instr
);
1145 if (instr
->op
== nir_op_unpack_unorm_4x8
) {
1146 struct qreg src
= ntq_get_src(c
, instr
->src
[0].src
,
1147 instr
->src
[0].swizzle
[0]);
1148 for (int i
= 0; i
< 4; i
++) {
1149 if (instr
->dest
.write_mask
& (1 << i
))
1150 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
1151 qir_UNPACK_8_F(c
, src
, i
));
1156 /* General case: We can just grab the one used channel per src. */
1157 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
1158 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1159 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
1164 switch (instr
->op
) {
1167 result
= qir_MOV(c
, src
[0]);
1170 result
= qir_FMUL(c
, src
[0], src
[1]);
1173 result
= qir_FADD(c
, src
[0], src
[1]);
1176 result
= qir_FSUB(c
, src
[0], src
[1]);
1179 result
= qir_FMIN(c
, src
[0], src
[1]);
1182 result
= qir_FMAX(c
, src
[0], src
[1]);
1187 result
= qir_FTOI(c
, src
[0]);
1191 result
= qir_ITOF(c
, src
[0]);
1194 result
= qir_AND(c
, src
[0], qir_uniform_f(c
, 1.0));
1197 result
= qir_AND(c
, src
[0], qir_uniform_ui(c
, 1));
1202 result
= qir_MOV(c
, qir_SEL(c
, QPU_COND_ZC
,
1203 qir_uniform_ui(c
, ~0),
1204 qir_uniform_ui(c
, 0)));
1208 result
= qir_ADD(c
, src
[0], src
[1]);
1211 result
= qir_SHR(c
, src
[0], src
[1]);
1214 result
= qir_SUB(c
, src
[0], src
[1]);
1217 result
= qir_ASR(c
, src
[0], src
[1]);
1220 result
= qir_SHL(c
, src
[0], src
[1]);
1223 result
= qir_MIN(c
, src
[0], src
[1]);
1226 result
= qir_MAX(c
, src
[0], src
[1]);
1229 result
= qir_AND(c
, src
[0], src
[1]);
1232 result
= qir_OR(c
, src
[0], src
[1]);
1235 result
= qir_XOR(c
, src
[0], src
[1]);
1238 result
= qir_NOT(c
, src
[0]);
1242 result
= ntq_umul(c
, src
[0], src
[1]);
1258 if (!ntq_emit_comparison(c
, &result
, instr
, instr
)) {
1259 fprintf(stderr
, "Bad comparison instruction\n");
1264 result
= ntq_emit_bcsel(c
, instr
, src
);
1268 result
= qir_MOV(c
, qir_SEL(c
, QPU_COND_ZC
, src
[1], src
[2]));
1272 result
= ntq_rcp(c
, src
[0]);
1275 result
= ntq_rsq(c
, src
[0]);
1278 result
= qir_EXP2(c
, src
[0]);
1281 result
= qir_LOG2(c
, src
[0]);
1285 result
= qir_ITOF(c
, qir_FTOI(c
, src
[0]));
1288 result
= ntq_fceil(c
, src
[0]);
1291 result
= ntq_ffract(c
, src
[0]);
1294 result
= ntq_ffloor(c
, src
[0]);
1298 result
= ntq_fsin(c
, src
[0]);
1301 result
= ntq_fcos(c
, src
[0]);
1305 result
= ntq_fsign(c
, src
[0]);
1309 result
= qir_FMAXABS(c
, src
[0], src
[0]);
1312 result
= qir_MAX(c
, src
[0],
1313 qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0]));
1316 case nir_op_ibitfield_extract
:
1317 result
= ntq_emit_ibfe(c
, src
[0], src
[1], src
[2]);
1320 case nir_op_ubitfield_extract
:
1321 result
= ntq_emit_ubfe(c
, src
[0], src
[1], src
[2]);
1324 case nir_op_usadd_4x8
:
1325 result
= qir_V8ADDS(c
, src
[0], src
[1]);
1328 case nir_op_ussub_4x8
:
1329 result
= qir_V8SUBS(c
, src
[0], src
[1]);
1332 case nir_op_umin_4x8
:
1333 result
= qir_V8MIN(c
, src
[0], src
[1]);
1336 case nir_op_umax_4x8
:
1337 result
= qir_V8MAX(c
, src
[0], src
[1]);
1340 case nir_op_umul_unorm_4x8
:
1341 result
= qir_V8MULD(c
, src
[0], src
[1]);
1345 case nir_op_fddx_coarse
:
1346 case nir_op_fddx_fine
:
1347 result
= ntq_fddx(c
, src
[0]);
1351 case nir_op_fddy_coarse
:
1352 case nir_op_fddy_fine
:
1353 result
= ntq_fddy(c
, src
[0]);
1357 fprintf(stderr
, "unknown NIR ALU inst: ");
1358 nir_print_instr(&instr
->instr
, stderr
);
1359 fprintf(stderr
, "\n");
1363 /* We have a scalar result, so the instruction should only have a
1364 * single channel written to.
1366 assert(util_is_power_of_two(instr
->dest
.write_mask
));
1367 ntq_store_dest(c
, &instr
->dest
.dest
,
1368 ffs(instr
->dest
.write_mask
) - 1, result
);
1372 emit_frag_end(struct vc4_compile
*c
)
1375 if (c
->output_color_index
!= -1) {
1376 color
= c
->outputs
[c
->output_color_index
];
1378 color
= qir_uniform_ui(c
, 0);
1381 uint32_t discard_cond
= QPU_COND_ALWAYS
;
1382 if (c
->s
->info
.fs
.uses_discard
) {
1383 qir_SF(c
, c
->discard
);
1384 discard_cond
= QPU_COND_ZS
;
1387 if (c
->fs_key
->stencil_enabled
) {
1388 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1389 qir_uniform(c
, QUNIFORM_STENCIL
, 0));
1390 if (c
->fs_key
->stencil_twoside
) {
1391 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1392 qir_uniform(c
, QUNIFORM_STENCIL
, 1));
1394 if (c
->fs_key
->stencil_full_writemasks
) {
1395 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1396 qir_uniform(c
, QUNIFORM_STENCIL
, 2));
1400 if (c
->output_sample_mask_index
!= -1) {
1401 qir_MS_MASK(c
, c
->outputs
[c
->output_sample_mask_index
]);
1404 if (c
->fs_key
->depth_enabled
) {
1405 if (c
->output_position_index
!= -1) {
1406 qir_FTOI_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1408 c
->outputs
[c
->output_position_index
],
1409 qir_uniform_f(c
, 0xffffff)))->cond
= discard_cond
;
1411 qir_MOV_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1412 qir_FRAG_Z(c
))->cond
= discard_cond
;
1416 if (!c
->msaa_per_sample_output
) {
1417 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE
, 0),
1418 color
)->cond
= discard_cond
;
1420 for (int i
= 0; i
< VC4_MAX_SAMPLES
; i
++) {
1421 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE_MS
, 0),
1422 c
->sample_colors
[i
])->cond
= discard_cond
;
1428 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1430 struct qreg packed
= qir_get_temp(c
);
1432 for (int i
= 0; i
< 2; i
++) {
1434 qir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1436 struct qreg packed_chan
= packed
;
1437 packed_chan
.pack
= QPU_PACK_A_16A
+ i
;
1439 qir_FTOI_dest(c
, packed_chan
,
1442 c
->outputs
[c
->output_position_index
+ i
],
1447 qir_VPM_WRITE(c
, packed
);
1451 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1453 struct qreg zscale
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1454 struct qreg zoffset
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1456 qir_VPM_WRITE(c
, qir_FADD(c
, qir_FMUL(c
, qir_FMUL(c
,
1457 c
->outputs
[c
->output_position_index
+ 2],
1464 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1466 qir_VPM_WRITE(c
, rcp_w
);
1470 emit_point_size_write(struct vc4_compile
*c
)
1472 struct qreg point_size
;
1474 if (c
->output_point_size_index
!= -1)
1475 point_size
= c
->outputs
[c
->output_point_size_index
];
1477 point_size
= qir_uniform_f(c
, 1.0);
1479 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1482 point_size
= qir_FMAX(c
, point_size
, qir_uniform_f(c
, .125));
1484 qir_VPM_WRITE(c
, point_size
);
1488 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1490 * The simulator insists that there be at least one vertex attribute, so
1491 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1492 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1493 * to consume it here.
1496 emit_stub_vpm_read(struct vc4_compile
*c
)
1501 c
->vattr_sizes
[0] = 4;
1502 (void)qir_MOV(c
, qir_reg(QFILE_VPM
, 0));
1507 emit_vert_end(struct vc4_compile
*c
,
1508 struct vc4_varying_slot
*fs_inputs
,
1509 uint32_t num_fs_inputs
)
1511 struct qreg rcp_w
= ntq_rcp(c
, c
->outputs
[c
->output_position_index
+ 3]);
1513 emit_stub_vpm_read(c
);
1515 emit_scaled_viewport_write(c
, rcp_w
);
1516 emit_zs_write(c
, rcp_w
);
1517 emit_rcp_wc_write(c
, rcp_w
);
1518 if (c
->vs_key
->per_vertex_point_size
)
1519 emit_point_size_write(c
);
1521 for (int i
= 0; i
< num_fs_inputs
; i
++) {
1522 struct vc4_varying_slot
*input
= &fs_inputs
[i
];
1525 for (j
= 0; j
< c
->num_outputs
; j
++) {
1526 struct vc4_varying_slot
*output
=
1527 &c
->output_slots
[j
];
1529 if (input
->slot
== output
->slot
&&
1530 input
->swizzle
== output
->swizzle
) {
1531 qir_VPM_WRITE(c
, c
->outputs
[j
]);
1535 /* Emit padding if we didn't find a declared VS output for
1538 if (j
== c
->num_outputs
)
1539 qir_VPM_WRITE(c
, qir_uniform_f(c
, 0.0));
1544 emit_coord_end(struct vc4_compile
*c
)
1546 struct qreg rcp_w
= ntq_rcp(c
, c
->outputs
[c
->output_position_index
+ 3]);
1548 emit_stub_vpm_read(c
);
1550 for (int i
= 0; i
< 4; i
++)
1551 qir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
]);
1553 emit_scaled_viewport_write(c
, rcp_w
);
1554 emit_zs_write(c
, rcp_w
);
1555 emit_rcp_wc_write(c
, rcp_w
);
1556 if (c
->vs_key
->per_vertex_point_size
)
1557 emit_point_size_write(c
);
1561 vc4_optimize_nir(struct nir_shader
*s
)
1568 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1569 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
);
1570 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1571 NIR_PASS(progress
, s
, nir_copy_prop
);
1572 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1573 NIR_PASS(progress
, s
, nir_opt_dce
);
1574 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1575 NIR_PASS(progress
, s
, nir_opt_cse
);
1576 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8);
1577 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1578 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1579 NIR_PASS(progress
, s
, nir_opt_undef
);
1580 NIR_PASS(progress
, s
, nir_opt_loop_unroll
,
1582 nir_var_shader_out
|
1588 driver_location_compare(const void *in_a
, const void *in_b
)
1590 const nir_variable
*const *a
= in_a
;
1591 const nir_variable
*const *b
= in_b
;
1593 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1597 ntq_setup_inputs(struct vc4_compile
*c
)
1599 unsigned num_entries
= 0;
1600 nir_foreach_variable(var
, &c
->s
->inputs
)
1603 nir_variable
*vars
[num_entries
];
1606 nir_foreach_variable(var
, &c
->s
->inputs
)
1609 /* Sort the variables so that we emit the input setup in
1610 * driver_location order. This is required for VPM reads, whose data
1611 * is fetched into the VPM in driver_location (TGSI register index)
1614 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1616 for (unsigned i
= 0; i
< num_entries
; i
++) {
1617 nir_variable
*var
= vars
[i
];
1618 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1619 unsigned loc
= var
->data
.driver_location
;
1621 assert(array_len
== 1);
1623 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1626 if (c
->stage
== QSTAGE_FRAG
) {
1627 if (var
->data
.location
== VARYING_SLOT_POS
) {
1628 emit_fragcoord_input(c
, loc
);
1629 } else if (var
->data
.location
== VARYING_SLOT_PNTC
||
1630 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1631 (c
->fs_key
->point_sprite_mask
&
1632 (1 << (var
->data
.location
-
1633 VARYING_SLOT_VAR0
))))) {
1634 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1635 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1637 emit_fragment_input(c
, loc
, var
->data
.location
);
1640 emit_vertex_input(c
, loc
);
1646 ntq_setup_outputs(struct vc4_compile
*c
)
1648 nir_foreach_variable(var
, &c
->s
->outputs
) {
1649 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1650 unsigned loc
= var
->data
.driver_location
* 4;
1652 assert(array_len
== 1);
1655 for (int i
= 0; i
< 4; i
++)
1656 add_output(c
, loc
+ i
, var
->data
.location
, i
);
1658 if (c
->stage
== QSTAGE_FRAG
) {
1659 switch (var
->data
.location
) {
1660 case FRAG_RESULT_COLOR
:
1661 case FRAG_RESULT_DATA0
:
1662 c
->output_color_index
= loc
;
1664 case FRAG_RESULT_DEPTH
:
1665 c
->output_position_index
= loc
;
1667 case FRAG_RESULT_SAMPLE_MASK
:
1668 c
->output_sample_mask_index
= loc
;
1672 switch (var
->data
.location
) {
1673 case VARYING_SLOT_POS
:
1674 c
->output_position_index
= loc
;
1676 case VARYING_SLOT_PSIZ
:
1677 c
->output_point_size_index
= loc
;
1685 ntq_setup_uniforms(struct vc4_compile
*c
)
1687 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1688 uint32_t vec4_count
= type_size(var
->type
);
1689 unsigned vec4_size
= 4 * sizeof(float);
1691 declare_uniform_range(c
, var
->data
.driver_location
* vec4_size
,
1692 vec4_count
* vec4_size
);
1698 * Sets up the mapping from nir_register to struct qreg *.
1700 * Each nir_register gets a struct qreg per 32-bit component being stored.
1703 ntq_setup_registers(struct vc4_compile
*c
, struct exec_list
*list
)
1705 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1706 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1707 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1709 nir_reg
->num_components
);
1711 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1713 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1714 qregs
[i
] = qir_get_temp(c
);
1719 ntq_emit_load_const(struct vc4_compile
*c
, nir_load_const_instr
*instr
)
1721 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1722 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1723 qregs
[i
] = qir_uniform_ui(c
, instr
->value
.u32
[i
]);
1725 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1729 ntq_emit_ssa_undef(struct vc4_compile
*c
, nir_ssa_undef_instr
*instr
)
1731 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1733 /* QIR needs there to be *some* value, so pick 0 (same as for
1734 * ntq_setup_registers().
1736 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1737 qregs
[i
] = qir_uniform_ui(c
, 0);
1741 ntq_emit_color_read(struct vc4_compile
*c
, nir_intrinsic_instr
*instr
)
1743 assert(nir_src_as_const_value(instr
->src
[0])->u32
[0] == 0);
1745 /* Reads of the per-sample color need to be done in
1748 int sample_index
= (nir_intrinsic_base(instr
) -
1749 VC4_NIR_TLB_COLOR_READ_INPUT
);
1750 for (int i
= 0; i
<= sample_index
; i
++) {
1751 if (c
->color_reads
[i
].file
== QFILE_NULL
) {
1753 qir_TLB_COLOR_READ(c
);
1756 ntq_store_dest(c
, &instr
->dest
, 0,
1757 qir_MOV(c
, c
->color_reads
[sample_index
]));
1761 ntq_emit_load_input(struct vc4_compile
*c
, nir_intrinsic_instr
*instr
)
1763 assert(instr
->num_components
== 1);
1765 nir_const_value
*const_offset
= nir_src_as_const_value(instr
->src
[0]);
1766 assert(const_offset
&& "vc4 doesn't support indirect inputs");
1768 if (c
->stage
== QSTAGE_FRAG
&&
1769 nir_intrinsic_base(instr
) >= VC4_NIR_TLB_COLOR_READ_INPUT
) {
1770 ntq_emit_color_read(c
, instr
);
1774 uint32_t offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1775 int comp
= nir_intrinsic_component(instr
);
1776 ntq_store_dest(c
, &instr
->dest
, 0,
1777 qir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1781 ntq_emit_intrinsic(struct vc4_compile
*c
, nir_intrinsic_instr
*instr
)
1783 nir_const_value
*const_offset
;
1786 switch (instr
->intrinsic
) {
1787 case nir_intrinsic_load_uniform
:
1788 assert(instr
->num_components
== 1);
1789 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1791 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1792 assert(offset
% 4 == 0);
1793 /* We need dwords */
1794 offset
= offset
/ 4;
1795 ntq_store_dest(c
, &instr
->dest
, 0,
1796 qir_uniform(c
, QUNIFORM_UNIFORM
,
1799 ntq_store_dest(c
, &instr
->dest
, 0,
1800 indirect_uniform_load(c
, instr
));
1804 case nir_intrinsic_load_ubo
:
1805 assert(instr
->num_components
== 1);
1806 ntq_store_dest(c
, &instr
->dest
, 0, vc4_ubo_load(c
, instr
));
1809 case nir_intrinsic_load_user_clip_plane
:
1810 for (int i
= 0; i
< instr
->num_components
; i
++) {
1811 ntq_store_dest(c
, &instr
->dest
, i
,
1812 qir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1813 nir_intrinsic_ucp_id(instr
) *
1818 case nir_intrinsic_load_blend_const_color_r_float
:
1819 case nir_intrinsic_load_blend_const_color_g_float
:
1820 case nir_intrinsic_load_blend_const_color_b_float
:
1821 case nir_intrinsic_load_blend_const_color_a_float
:
1822 ntq_store_dest(c
, &instr
->dest
, 0,
1823 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_X
+
1825 nir_intrinsic_load_blend_const_color_r_float
),
1829 case nir_intrinsic_load_blend_const_color_rgba8888_unorm
:
1830 ntq_store_dest(c
, &instr
->dest
, 0,
1831 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_RGBA
,
1835 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm
:
1836 ntq_store_dest(c
, &instr
->dest
, 0,
1837 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_AAAA
,
1841 case nir_intrinsic_load_alpha_ref_float
:
1842 ntq_store_dest(c
, &instr
->dest
, 0,
1843 qir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1846 case nir_intrinsic_load_sample_mask_in
:
1847 ntq_store_dest(c
, &instr
->dest
, 0,
1848 qir_uniform(c
, QUNIFORM_SAMPLE_MASK
, 0));
1851 case nir_intrinsic_load_front_face
:
1852 /* The register contains 0 (front) or 1 (back), and we need to
1853 * turn it into a NIR bool where true means front.
1855 ntq_store_dest(c
, &instr
->dest
, 0,
1857 qir_uniform_ui(c
, -1),
1858 qir_reg(QFILE_FRAG_REV_FLAG
, 0)));
1861 case nir_intrinsic_load_input
:
1862 ntq_emit_load_input(c
, instr
);
1865 case nir_intrinsic_store_output
:
1866 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1867 assert(const_offset
&& "vc4 doesn't support indirect outputs");
1868 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1870 /* MSAA color outputs are the only case where we have an
1871 * output that's not lowered to being a store of a single 32
1874 if (c
->stage
== QSTAGE_FRAG
&& instr
->num_components
== 4) {
1875 assert(offset
== c
->output_color_index
);
1876 for (int i
= 0; i
< 4; i
++) {
1877 c
->sample_colors
[i
] =
1878 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0],
1882 offset
= offset
* 4 + nir_intrinsic_component(instr
);
1883 assert(instr
->num_components
== 1);
1884 c
->outputs
[offset
] =
1885 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0], 0));
1886 c
->num_outputs
= MAX2(c
->num_outputs
, offset
+ 1);
1890 case nir_intrinsic_discard
:
1891 if (c
->execute
.file
!= QFILE_NULL
) {
1892 qir_SF(c
, c
->execute
);
1893 qir_MOV_cond(c
, QPU_COND_ZS
, c
->discard
,
1894 qir_uniform_ui(c
, ~0));
1896 qir_MOV_dest(c
, c
->discard
, qir_uniform_ui(c
, ~0));
1900 case nir_intrinsic_discard_if
: {
1901 /* true (~0) if we're discarding */
1902 struct qreg cond
= ntq_get_src(c
, instr
->src
[0], 0);
1904 if (c
->execute
.file
!= QFILE_NULL
) {
1905 /* execute == 0 means the channel is active. Invert
1906 * the condition so that we can use zero as "executing
1909 qir_SF(c
, qir_AND(c
, c
->execute
, qir_NOT(c
, cond
)));
1910 qir_MOV_cond(c
, QPU_COND_ZS
, c
->discard
, cond
);
1912 qir_OR_dest(c
, c
->discard
, c
->discard
,
1913 ntq_get_src(c
, instr
->src
[0], 0));
1920 fprintf(stderr
, "Unknown intrinsic: ");
1921 nir_print_instr(&instr
->instr
, stderr
);
1922 fprintf(stderr
, "\n");
1927 /* Clears (activates) the execute flags for any channels whose jump target
1928 * matches this block.
1931 ntq_activate_execute_for_block(struct vc4_compile
*c
)
1933 qir_SF(c
, qir_SUB(c
,
1935 qir_uniform_ui(c
, c
->cur_block
->index
)));
1936 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
, qir_uniform_ui(c
, 0));
1940 ntq_emit_if(struct vc4_compile
*c
, nir_if
*if_stmt
)
1942 if (!c
->vc4
->screen
->has_control_flow
) {
1944 "IF statement support requires updated kernel.\n");
1948 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
1949 bool empty_else_block
=
1950 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
1951 exec_list_is_empty(&nir_else_block
->instr_list
));
1953 struct qblock
*then_block
= qir_new_block(c
);
1954 struct qblock
*after_block
= qir_new_block(c
);
1955 struct qblock
*else_block
;
1956 if (empty_else_block
)
1957 else_block
= after_block
;
1959 else_block
= qir_new_block(c
);
1961 bool was_top_level
= false;
1962 if (c
->execute
.file
== QFILE_NULL
) {
1963 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1964 was_top_level
= true;
1967 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1968 * 0) channels, and then update execute flags for those to point to
1973 ntq_get_src(c
, if_stmt
->condition
, 0)));
1974 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1975 qir_uniform_ui(c
, else_block
->index
));
1977 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1980 qir_SF(c
, c
->execute
);
1981 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZC
);
1982 qir_link_blocks(c
->cur_block
, else_block
);
1983 qir_link_blocks(c
->cur_block
, then_block
);
1985 /* Process the THEN block. */
1986 qir_set_emit_block(c
, then_block
);
1987 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1989 if (!empty_else_block
) {
1990 /* Handle the end of the THEN block. First, all currently
1991 * active channels update their execute flags to point to
1994 qir_SF(c
, c
->execute
);
1995 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1996 qir_uniform_ui(c
, after_block
->index
));
1998 /* If everything points at ENDIF, then jump there immediately. */
1999 qir_SF(c
, qir_SUB(c
, c
->execute
, qir_uniform_ui(c
, after_block
->index
)));
2000 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZS
);
2001 qir_link_blocks(c
->cur_block
, after_block
);
2002 qir_link_blocks(c
->cur_block
, else_block
);
2004 qir_set_emit_block(c
, else_block
);
2005 ntq_activate_execute_for_block(c
);
2006 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
2009 qir_link_blocks(c
->cur_block
, after_block
);
2011 qir_set_emit_block(c
, after_block
);
2012 if (was_top_level
) {
2013 c
->execute
= c
->undef
;
2014 c
->last_top_block
= c
->cur_block
;
2016 ntq_activate_execute_for_block(c
);
2021 ntq_emit_jump(struct vc4_compile
*c
, nir_jump_instr
*jump
)
2023 struct qblock
*jump_block
;
2024 switch (jump
->type
) {
2025 case nir_jump_break
:
2026 jump_block
= c
->loop_break_block
;
2028 case nir_jump_continue
:
2029 jump_block
= c
->loop_cont_block
;
2032 unreachable("Unsupported jump type\n");
2035 qir_SF(c
, c
->execute
);
2036 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
2037 qir_uniform_ui(c
, jump_block
->index
));
2039 /* Jump to the destination block if everyone has taken the jump. */
2040 qir_SF(c
, qir_SUB(c
, c
->execute
, qir_uniform_ui(c
, jump_block
->index
)));
2041 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZS
);
2042 struct qblock
*new_block
= qir_new_block(c
);
2043 qir_link_blocks(c
->cur_block
, jump_block
);
2044 qir_link_blocks(c
->cur_block
, new_block
);
2045 qir_set_emit_block(c
, new_block
);
2049 ntq_emit_instr(struct vc4_compile
*c
, nir_instr
*instr
)
2051 switch (instr
->type
) {
2052 case nir_instr_type_alu
:
2053 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
2056 case nir_instr_type_intrinsic
:
2057 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
2060 case nir_instr_type_load_const
:
2061 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
2064 case nir_instr_type_ssa_undef
:
2065 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
2068 case nir_instr_type_tex
:
2069 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
2072 case nir_instr_type_jump
:
2073 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
2077 fprintf(stderr
, "Unknown NIR instr type: ");
2078 nir_print_instr(instr
, stderr
);
2079 fprintf(stderr
, "\n");
2085 ntq_emit_block(struct vc4_compile
*c
, nir_block
*block
)
2087 nir_foreach_instr(instr
, block
) {
2088 ntq_emit_instr(c
, instr
);
2092 static void ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
2095 ntq_emit_loop(struct vc4_compile
*c
, nir_loop
*loop
)
2097 if (!c
->vc4
->screen
->has_control_flow
) {
2099 "loop support requires updated kernel.\n");
2100 ntq_emit_cf_list(c
, &loop
->body
);
2104 bool was_top_level
= false;
2105 if (c
->execute
.file
== QFILE_NULL
) {
2106 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
2107 was_top_level
= true;
2110 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
2111 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
2113 c
->loop_cont_block
= qir_new_block(c
);
2114 c
->loop_break_block
= qir_new_block(c
);
2116 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2117 qir_set_emit_block(c
, c
->loop_cont_block
);
2118 ntq_activate_execute_for_block(c
);
2120 ntq_emit_cf_list(c
, &loop
->body
);
2122 /* If anything had explicitly continued, or is here at the end of the
2123 * loop, then we need to loop again. SF updates are masked by the
2124 * instruction's condition, so we can do the OR of the two conditions
2127 qir_SF(c
, c
->execute
);
2128 struct qinst
*cont_check
=
2132 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
2133 cont_check
->cond
= QPU_COND_ZC
;
2134 cont_check
->sf
= true;
2136 qir_BRANCH(c
, QPU_COND_BRANCH_ANY_ZS
);
2137 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2138 qir_link_blocks(c
->cur_block
, c
->loop_break_block
);
2140 qir_set_emit_block(c
, c
->loop_break_block
);
2141 if (was_top_level
) {
2142 c
->execute
= c
->undef
;
2143 c
->last_top_block
= c
->cur_block
;
2145 ntq_activate_execute_for_block(c
);
2148 c
->loop_break_block
= save_loop_break_block
;
2149 c
->loop_cont_block
= save_loop_cont_block
;
2153 ntq_emit_function(struct vc4_compile
*c
, nir_function_impl
*func
)
2155 fprintf(stderr
, "FUNCTIONS not handled.\n");
2160 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
)
2162 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2163 switch (node
->type
) {
2164 case nir_cf_node_block
:
2165 ntq_emit_block(c
, nir_cf_node_as_block(node
));
2168 case nir_cf_node_if
:
2169 ntq_emit_if(c
, nir_cf_node_as_if(node
));
2172 case nir_cf_node_loop
:
2173 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
2176 case nir_cf_node_function
:
2177 ntq_emit_function(c
, nir_cf_node_as_function(node
));
2181 fprintf(stderr
, "Unknown NIR node type\n");
2188 ntq_emit_impl(struct vc4_compile
*c
, nir_function_impl
*impl
)
2190 ntq_setup_registers(c
, &impl
->registers
);
2191 ntq_emit_cf_list(c
, &impl
->body
);
2195 nir_to_qir(struct vc4_compile
*c
)
2197 if (c
->stage
== QSTAGE_FRAG
&& c
->s
->info
.fs
.uses_discard
)
2198 c
->discard
= qir_MOV(c
, qir_uniform_ui(c
, 0));
2200 ntq_setup_inputs(c
);
2201 ntq_setup_outputs(c
);
2202 ntq_setup_uniforms(c
);
2203 ntq_setup_registers(c
, &c
->s
->registers
);
2205 /* Find the main function and emit the body. */
2206 nir_foreach_function(function
, c
->s
) {
2207 assert(strcmp(function
->name
, "main") == 0);
2208 assert(function
->impl
);
2209 ntq_emit_impl(c
, function
->impl
);
2213 static const nir_shader_compiler_options nir_options
= {
2214 .lower_all_io_to_temps
= true,
2215 .lower_extract_byte
= true,
2216 .lower_extract_word
= true,
2218 .lower_flrp32
= true,
2221 .lower_fsqrt
= true,
2222 .lower_ldexp
= true,
2223 .lower_negate
= true,
2224 .native_integers
= true,
2225 .max_unroll_iterations
= 32,
2229 vc4_screen_get_compiler_options(struct pipe_screen
*pscreen
,
2230 enum pipe_shader_ir ir
,
2231 enum pipe_shader_type shader
)
2233 return &nir_options
;
2237 count_nir_instrs(nir_shader
*nir
)
2240 nir_foreach_function(function
, nir
) {
2241 if (!function
->impl
)
2243 nir_foreach_block(block
, function
->impl
) {
2244 nir_foreach_instr(instr
, block
)
2251 static struct vc4_compile
*
2252 vc4_shader_ntq(struct vc4_context
*vc4
, enum qstage stage
,
2253 struct vc4_key
*key
, bool fs_threaded
)
2255 struct vc4_compile
*c
= qir_compile_init();
2259 c
->shader_state
= &key
->shader_state
->base
;
2260 c
->program_id
= key
->shader_state
->program_id
;
2262 p_atomic_inc_return(&key
->shader_state
->compiled_variant_count
);
2263 c
->fs_threaded
= fs_threaded
;
2268 c
->fs_key
= (struct vc4_fs_key
*)key
;
2269 if (c
->fs_key
->is_points
) {
2270 c
->point_x
= emit_fragment_varying(c
, ~0, 0);
2271 c
->point_y
= emit_fragment_varying(c
, ~0, 0);
2272 } else if (c
->fs_key
->is_lines
) {
2273 c
->line_x
= emit_fragment_varying(c
, ~0, 0);
2277 c
->vs_key
= (struct vc4_vs_key
*)key
;
2280 c
->vs_key
= (struct vc4_vs_key
*)key
;
2284 c
->s
= nir_shader_clone(c
, key
->shader_state
->base
.ir
.nir
);
2286 if (stage
== QSTAGE_FRAG
) {
2287 if (c
->fs_key
->alpha_test_func
!= COMPARE_FUNC_ALWAYS
) {
2288 NIR_PASS_V(c
->s
, nir_lower_alpha_test
,
2289 c
->fs_key
->alpha_test_func
,
2290 c
->fs_key
->sample_alpha_to_one
&&
2293 NIR_PASS_V(c
->s
, vc4_nir_lower_blend
, c
);
2296 struct nir_lower_tex_options tex_options
= {
2297 /* We would need to implement txs, but we don't want the
2298 * int/float conversions
2300 .lower_rect
= false,
2304 /* Apply swizzles to all samplers. */
2305 .swizzle_result
= ~0,
2308 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2309 * The format swizzling applies before sRGB decode, and
2310 * ARB_texture_swizzle is the last thing before returning the sample.
2312 for (int i
= 0; i
< ARRAY_SIZE(key
->tex
); i
++) {
2313 enum pipe_format format
= c
->key
->tex
[i
].format
;
2318 const uint8_t *format_swizzle
= vc4_get_format_swizzle(format
);
2320 for (int j
= 0; j
< 4; j
++) {
2321 uint8_t arb_swiz
= c
->key
->tex
[i
].swizzle
[j
];
2323 if (arb_swiz
<= 3) {
2324 tex_options
.swizzles
[i
][j
] =
2325 format_swizzle
[arb_swiz
];
2327 tex_options
.swizzles
[i
][j
] = arb_swiz
;
2331 if (util_format_is_srgb(format
))
2332 tex_options
.lower_srgb
|= (1 << i
);
2335 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
2337 if (c
->fs_key
&& c
->fs_key
->light_twoside
)
2338 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
2340 if (c
->vs_key
&& c
->vs_key
->clamp_color
)
2341 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
2343 if (c
->key
->ucp_enables
) {
2344 if (stage
== QSTAGE_FRAG
) {
2345 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, c
->key
->ucp_enables
);
2347 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, c
->key
->ucp_enables
);
2348 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
,
2349 nir_var_shader_out
);
2353 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2354 * which only handles a vec4 at a time. Similarly, VS output
2355 * scalarizing must happen after nir_lower_clip_vs.
2357 if (c
->stage
== QSTAGE_FRAG
)
2358 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_in
);
2360 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
2362 NIR_PASS_V(c
->s
, vc4_nir_lower_io
, c
);
2363 NIR_PASS_V(c
->s
, vc4_nir_lower_txf_ms
, c
);
2364 NIR_PASS_V(c
->s
, nir_lower_idiv
);
2366 vc4_optimize_nir(c
->s
);
2368 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
2370 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2371 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2372 qir_get_stage_name(c
->stage
),
2373 c
->program_id
, c
->variant_id
,
2374 count_nir_instrs(c
->s
));
2377 if (vc4_debug
& VC4_DEBUG_NIR
) {
2378 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2379 qir_get_stage_name(c
->stage
),
2380 c
->program_id
, c
->variant_id
);
2381 nir_print_shader(c
->s
, stderr
);
2388 /* FS threading requires that the thread execute
2389 * QPU_SIG_LAST_THREAD_SWITCH exactly once before terminating
2390 * (with no other THRSW afterwards, obviously). If we didn't
2391 * fetch a texture at a top level block, this wouldn't be
2394 if (c
->fs_threaded
&& !c
->last_thrsw_at_top_level
) {
2403 c
->vs_key
->fs_inputs
->input_slots
,
2404 c
->vs_key
->fs_inputs
->num_inputs
);
2411 if (vc4_debug
& VC4_DEBUG_QIR
) {
2412 fprintf(stderr
, "%s prog %d/%d pre-opt QIR:\n",
2413 qir_get_stage_name(c
->stage
),
2414 c
->program_id
, c
->variant_id
);
2416 fprintf(stderr
, "\n");
2420 qir_lower_uniforms(c
);
2422 qir_schedule_instructions(c
);
2423 qir_emit_uniform_stream_resets(c
);
2425 if (vc4_debug
& VC4_DEBUG_QIR
) {
2426 fprintf(stderr
, "%s prog %d/%d QIR:\n",
2427 qir_get_stage_name(c
->stage
),
2428 c
->program_id
, c
->variant_id
);
2430 fprintf(stderr
, "\n");
2433 qir_reorder_uniforms(c
);
2434 vc4_generate_code(vc4
, c
);
2436 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2437 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2438 qir_get_stage_name(c
->stage
),
2439 c
->program_id
, c
->variant_id
,
2441 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2442 qir_get_stage_name(c
->stage
),
2443 c
->program_id
, c
->variant_id
,
2453 vc4_shader_state_create(struct pipe_context
*pctx
,
2454 const struct pipe_shader_state
*cso
)
2456 struct vc4_context
*vc4
= vc4_context(pctx
);
2457 struct vc4_uncompiled_shader
*so
= CALLOC_STRUCT(vc4_uncompiled_shader
);
2461 so
->program_id
= vc4
->next_uncompiled_program_id
++;
2465 if (cso
->type
== PIPE_SHADER_IR_NIR
) {
2466 /* The backend takes ownership of the NIR shader on state
2471 NIR_PASS_V(s
, nir_lower_io
, nir_var_all
, type_size
,
2472 (nir_lower_io_options
)0);
2474 assert(cso
->type
== PIPE_SHADER_IR_TGSI
);
2476 if (vc4_debug
& VC4_DEBUG_TGSI
) {
2477 fprintf(stderr
, "prog %d TGSI:\n",
2479 tgsi_dump(cso
->tokens
, 0);
2480 fprintf(stderr
, "\n");
2482 s
= tgsi_to_nir(cso
->tokens
, &nir_options
);
2485 NIR_PASS_V(s
, nir_opt_global_to_local
);
2486 NIR_PASS_V(s
, nir_lower_regs_to_ssa
);
2487 NIR_PASS_V(s
, nir_normalize_cubemap_coords
);
2489 NIR_PASS_V(s
, nir_lower_load_const_to_scalar
);
2491 vc4_optimize_nir(s
);
2493 NIR_PASS_V(s
, nir_remove_dead_variables
, nir_var_local
);
2495 /* Garbage collect dead instructions */
2498 so
->base
.type
= PIPE_SHADER_IR_NIR
;
2499 so
->base
.ir
.nir
= s
;
2501 if (vc4_debug
& VC4_DEBUG_NIR
) {
2502 fprintf(stderr
, "%s prog %d NIR:\n",
2503 gl_shader_stage_name(s
->info
.stage
),
2505 nir_print_shader(s
, stderr
);
2506 fprintf(stderr
, "\n");
2513 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
2514 struct vc4_compile
*c
)
2516 int count
= c
->num_uniforms
;
2517 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
;
2519 uinfo
->count
= count
;
2520 uinfo
->data
= ralloc_array(shader
, uint32_t, count
);
2521 memcpy(uinfo
->data
, c
->uniform_data
,
2522 count
* sizeof(*uinfo
->data
));
2523 uinfo
->contents
= ralloc_array(shader
, enum quniform_contents
, count
);
2524 memcpy(uinfo
->contents
, c
->uniform_contents
,
2525 count
* sizeof(*uinfo
->contents
));
2526 uinfo
->num_texture_samples
= c
->num_texture_samples
;
2528 vc4_set_shader_uniform_dirty_flags(shader
);
2532 vc4_setup_compiled_fs_inputs(struct vc4_context
*vc4
, struct vc4_compile
*c
,
2533 struct vc4_compiled_shader
*shader
)
2535 struct vc4_fs_inputs inputs
;
2537 memset(&inputs
, 0, sizeof(inputs
));
2538 inputs
.input_slots
= ralloc_array(shader
,
2539 struct vc4_varying_slot
,
2540 c
->num_input_slots
);
2542 bool input_live
[c
->num_input_slots
];
2544 memset(input_live
, 0, sizeof(input_live
));
2545 qir_for_each_inst_inorder(inst
, c
) {
2546 for (int i
= 0; i
< qir_get_nsrc(inst
); i
++) {
2547 if (inst
->src
[i
].file
== QFILE_VARY
)
2548 input_live
[inst
->src
[i
].index
] = true;
2552 for (int i
= 0; i
< c
->num_input_slots
; i
++) {
2553 struct vc4_varying_slot
*slot
= &c
->input_slots
[i
];
2558 /* Skip non-VS-output inputs. */
2559 if (slot
->slot
== (uint8_t)~0)
2562 if (slot
->slot
== VARYING_SLOT_COL0
||
2563 slot
->slot
== VARYING_SLOT_COL1
||
2564 slot
->slot
== VARYING_SLOT_BFC0
||
2565 slot
->slot
== VARYING_SLOT_BFC1
) {
2566 shader
->color_inputs
|= (1 << inputs
.num_inputs
);
2569 inputs
.input_slots
[inputs
.num_inputs
] = *slot
;
2570 inputs
.num_inputs
++;
2572 shader
->num_inputs
= inputs
.num_inputs
;
2574 /* Add our set of inputs to the set of all inputs seen. This way, we
2575 * can have a single pointer that identifies an FS inputs set,
2576 * allowing VS to avoid recompiling when the FS is recompiled (or a
2577 * new one is bound using separate shader objects) but the inputs
2580 struct set_entry
*entry
= _mesa_set_search(vc4
->fs_inputs_set
, &inputs
);
2582 shader
->fs_inputs
= entry
->key
;
2583 ralloc_free(inputs
.input_slots
);
2585 struct vc4_fs_inputs
*alloc_inputs
;
2587 alloc_inputs
= rzalloc(vc4
->fs_inputs_set
, struct vc4_fs_inputs
);
2588 memcpy(alloc_inputs
, &inputs
, sizeof(inputs
));
2589 ralloc_steal(alloc_inputs
, inputs
.input_slots
);
2590 _mesa_set_add(vc4
->fs_inputs_set
, alloc_inputs
);
2592 shader
->fs_inputs
= alloc_inputs
;
2596 static struct vc4_compiled_shader
*
2597 vc4_get_compiled_shader(struct vc4_context
*vc4
, enum qstage stage
,
2598 struct vc4_key
*key
)
2600 struct hash_table
*ht
;
2604 if (stage
== QSTAGE_FRAG
) {
2606 key_size
= sizeof(struct vc4_fs_key
);
2607 try_threading
= vc4
->screen
->has_threaded_fs
;
2610 key_size
= sizeof(struct vc4_vs_key
);
2611 try_threading
= false;
2614 struct vc4_compiled_shader
*shader
;
2615 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, key
);
2619 struct vc4_compile
*c
= vc4_shader_ntq(vc4
, stage
, key
, try_threading
);
2620 /* If the FS failed to compile threaded, fall back to single threaded. */
2621 if (try_threading
&& c
->failed
) {
2622 qir_compile_destroy(c
);
2623 c
= vc4_shader_ntq(vc4
, stage
, key
, false);
2626 shader
= rzalloc(NULL
, struct vc4_compiled_shader
);
2628 shader
->program_id
= vc4
->next_compiled_program_id
++;
2629 if (stage
== QSTAGE_FRAG
) {
2630 vc4_setup_compiled_fs_inputs(vc4
, c
, shader
);
2632 /* Note: the temporary clone in c->s has been freed. */
2633 nir_shader
*orig_shader
= key
->shader_state
->base
.ir
.nir
;
2634 if (orig_shader
->info
.outputs_written
& (1 << FRAG_RESULT_DEPTH
))
2635 shader
->disable_early_z
= true;
2637 shader
->num_inputs
= c
->num_inputs
;
2639 shader
->vattr_offsets
[0] = 0;
2640 for (int i
= 0; i
< 8; i
++) {
2641 shader
->vattr_offsets
[i
+ 1] =
2642 shader
->vattr_offsets
[i
] + c
->vattr_sizes
[i
];
2644 if (c
->vattr_sizes
[i
])
2645 shader
->vattrs_live
|= (1 << i
);
2649 shader
->failed
= c
->failed
;
2651 shader
->failed
= true;
2653 copy_uniform_state_to_shader(shader
, c
);
2654 shader
->bo
= vc4_bo_alloc_shader(vc4
->screen
, c
->qpu_insts
,
2659 shader
->fs_threaded
= c
->fs_threaded
;
2661 /* Copy the compiler UBO range state to the compiled shader, dropping
2662 * out arrays that were never referenced by an indirect load.
2664 * (Note that QIR dead code elimination of an array access still
2665 * leaves that array alive, though)
2667 if (c
->num_ubo_ranges
) {
2668 shader
->num_ubo_ranges
= c
->num_ubo_ranges
;
2669 shader
->ubo_ranges
= ralloc_array(shader
, struct vc4_ubo_range
,
2672 for (int i
= 0; i
< c
->num_uniform_ranges
; i
++) {
2673 struct vc4_compiler_ubo_range
*range
=
2678 shader
->ubo_ranges
[j
].dst_offset
= range
->dst_offset
;
2679 shader
->ubo_ranges
[j
].src_offset
= range
->src_offset
;
2680 shader
->ubo_ranges
[j
].size
= range
->size
;
2681 shader
->ubo_size
+= c
->ubo_ranges
[i
].size
;
2685 if (shader
->ubo_size
) {
2686 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2687 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2688 qir_get_stage_name(c
->stage
),
2689 c
->program_id
, c
->variant_id
,
2690 shader
->ubo_size
/ 4);
2694 if ((vc4_debug
& VC4_DEBUG_SHADERDB
) && stage
== QSTAGE_FRAG
) {
2695 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d FS threads\n",
2696 qir_get_stage_name(c
->stage
),
2697 c
->program_id
, c
->variant_id
,
2698 1 + shader
->fs_threaded
);
2701 qir_compile_destroy(c
);
2703 struct vc4_key
*dup_key
;
2704 dup_key
= rzalloc_size(shader
, key_size
); /* TODO: don't use rzalloc */
2705 memcpy(dup_key
, key
, key_size
);
2706 _mesa_hash_table_insert(ht
, dup_key
, shader
);
2712 vc4_setup_shared_key(struct vc4_context
*vc4
, struct vc4_key
*key
,
2713 struct vc4_texture_stateobj
*texstate
)
2715 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
2716 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
2717 struct vc4_sampler_view
*vc4_sampler
= vc4_sampler_view(sampler
);
2718 struct pipe_sampler_state
*sampler_state
=
2719 texstate
->samplers
[i
];
2724 key
->tex
[i
].format
= sampler
->format
;
2725 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
2726 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
2727 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
2728 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
2730 if (sampler
->texture
->nr_samples
> 1) {
2731 key
->tex
[i
].msaa_width
= sampler
->texture
->width0
;
2732 key
->tex
[i
].msaa_height
= sampler
->texture
->height0
;
2733 } else if (sampler
){
2734 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
2735 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
2736 key
->tex
[i
].wrap_s
= sampler_state
->wrap_s
;
2737 key
->tex
[i
].wrap_t
= sampler_state
->wrap_t
;
2738 key
->tex
[i
].force_first_level
=
2739 vc4_sampler
->force_first_level
;
2743 key
->ucp_enables
= vc4
->rasterizer
->base
.clip_plane_enable
;
2747 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2749 struct vc4_job
*job
= vc4
->job
;
2750 struct vc4_fs_key local_key
;
2751 struct vc4_fs_key
*key
= &local_key
;
2753 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2755 VC4_DIRTY_FRAMEBUFFER
|
2757 VC4_DIRTY_RASTERIZER
|
2758 VC4_DIRTY_SAMPLE_MASK
|
2760 VC4_DIRTY_UNCOMPILED_FS
|
2761 VC4_DIRTY_UBO_1_SIZE
))) {
2765 memset(key
, 0, sizeof(*key
));
2766 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->fragtex
);
2767 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
2768 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
2769 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
2770 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
2771 key
->blend
= vc4
->blend
->rt
[0];
2772 if (vc4
->blend
->logicop_enable
) {
2773 key
->logicop_func
= vc4
->blend
->logicop_func
;
2775 key
->logicop_func
= PIPE_LOGICOP_COPY
;
2778 key
->msaa
= vc4
->rasterizer
->base
.multisample
;
2779 key
->sample_coverage
= (vc4
->sample_mask
!= (1 << VC4_MAX_SAMPLES
) - 1);
2780 key
->sample_alpha_to_coverage
= vc4
->blend
->alpha_to_coverage
;
2781 key
->sample_alpha_to_one
= vc4
->blend
->alpha_to_one
;
2784 if (vc4
->framebuffer
.cbufs
[0])
2785 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
2787 key
->stencil_enabled
= vc4
->zsa
->stencil_uniforms
[0] != 0;
2788 key
->stencil_twoside
= vc4
->zsa
->stencil_uniforms
[1] != 0;
2789 key
->stencil_full_writemasks
= vc4
->zsa
->stencil_uniforms
[2] != 0;
2790 key
->depth_enabled
= (vc4
->zsa
->base
.depth
.enabled
||
2791 key
->stencil_enabled
);
2792 if (vc4
->zsa
->base
.alpha
.enabled
)
2793 key
->alpha_test_func
= vc4
->zsa
->base
.alpha
.func
;
2795 key
->alpha_test_func
= COMPARE_FUNC_ALWAYS
;
2797 if (key
->is_points
) {
2798 key
->point_sprite_mask
=
2799 vc4
->rasterizer
->base
.sprite_coord_enable
;
2800 key
->point_coord_upper_left
=
2801 (vc4
->rasterizer
->base
.sprite_coord_mode
==
2802 PIPE_SPRITE_COORD_UPPER_LEFT
);
2805 key
->ubo_1_size
= vc4
->constbuf
[PIPE_SHADER_FRAGMENT
].cb
[1].buffer_size
;
2806 key
->light_twoside
= vc4
->rasterizer
->base
.light_twoside
;
2808 struct vc4_compiled_shader
*old_fs
= vc4
->prog
.fs
;
2809 vc4
->prog
.fs
= vc4_get_compiled_shader(vc4
, QSTAGE_FRAG
, &key
->base
);
2810 if (vc4
->prog
.fs
== old_fs
)
2813 vc4
->dirty
|= VC4_DIRTY_COMPILED_FS
;
2815 if (vc4
->rasterizer
->base
.flatshade
&&
2816 (!old_fs
|| vc4
->prog
.fs
->color_inputs
!= old_fs
->color_inputs
)) {
2817 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
2820 if (!old_fs
|| vc4
->prog
.fs
->fs_inputs
!= old_fs
->fs_inputs
)
2821 vc4
->dirty
|= VC4_DIRTY_FS_INPUTS
;
2825 vc4_update_compiled_vs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2827 struct vc4_vs_key local_key
;
2828 struct vc4_vs_key
*key
= &local_key
;
2830 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2831 VC4_DIRTY_RASTERIZER
|
2833 VC4_DIRTY_VTXSTATE
|
2834 VC4_DIRTY_UNCOMPILED_VS
|
2835 VC4_DIRTY_FS_INPUTS
))) {
2839 memset(key
, 0, sizeof(*key
));
2840 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->verttex
);
2841 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
2842 key
->fs_inputs
= vc4
->prog
.fs
->fs_inputs
;
2843 key
->clamp_color
= vc4
->rasterizer
->base
.clamp_vertex_color
;
2845 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
2846 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
2848 key
->per_vertex_point_size
=
2849 (prim_mode
== PIPE_PRIM_POINTS
&&
2850 vc4
->rasterizer
->base
.point_size_per_vertex
);
2852 struct vc4_compiled_shader
*vs
=
2853 vc4_get_compiled_shader(vc4
, QSTAGE_VERT
, &key
->base
);
2854 if (vs
!= vc4
->prog
.vs
) {
2856 vc4
->dirty
|= VC4_DIRTY_COMPILED_VS
;
2859 key
->is_coord
= true;
2860 /* Coord shaders don't care what the FS inputs are. */
2861 key
->fs_inputs
= NULL
;
2862 struct vc4_compiled_shader
*cs
=
2863 vc4_get_compiled_shader(vc4
, QSTAGE_COORD
, &key
->base
);
2864 if (cs
!= vc4
->prog
.cs
) {
2866 vc4
->dirty
|= VC4_DIRTY_COMPILED_CS
;
2871 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
2873 vc4_update_compiled_fs(vc4
, prim_mode
);
2874 vc4_update_compiled_vs(vc4
, prim_mode
);
2876 return !(vc4
->prog
.cs
->failed
||
2877 vc4
->prog
.vs
->failed
||
2878 vc4
->prog
.fs
->failed
);
2882 fs_cache_hash(const void *key
)
2884 return _mesa_hash_data(key
, sizeof(struct vc4_fs_key
));
2888 vs_cache_hash(const void *key
)
2890 return _mesa_hash_data(key
, sizeof(struct vc4_vs_key
));
2894 fs_cache_compare(const void *key1
, const void *key2
)
2896 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
)) == 0;
2900 vs_cache_compare(const void *key1
, const void *key2
)
2902 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
)) == 0;
2906 fs_inputs_hash(const void *key
)
2908 const struct vc4_fs_inputs
*inputs
= key
;
2910 return _mesa_hash_data(inputs
->input_slots
,
2911 sizeof(*inputs
->input_slots
) *
2912 inputs
->num_inputs
);
2916 fs_inputs_compare(const void *key1
, const void *key2
)
2918 const struct vc4_fs_inputs
*inputs1
= key1
;
2919 const struct vc4_fs_inputs
*inputs2
= key2
;
2921 return (inputs1
->num_inputs
== inputs2
->num_inputs
&&
2922 memcmp(inputs1
->input_slots
,
2923 inputs2
->input_slots
,
2924 sizeof(*inputs1
->input_slots
) *
2925 inputs1
->num_inputs
) == 0);
2929 delete_from_cache_if_matches(struct hash_table
*ht
,
2930 struct vc4_compiled_shader
**last_compile
,
2931 struct hash_entry
*entry
,
2932 struct vc4_uncompiled_shader
*so
)
2934 const struct vc4_key
*key
= entry
->key
;
2936 if (key
->shader_state
== so
) {
2937 struct vc4_compiled_shader
*shader
= entry
->data
;
2938 _mesa_hash_table_remove(ht
, entry
);
2939 vc4_bo_unreference(&shader
->bo
);
2941 if (shader
== *last_compile
)
2942 *last_compile
= NULL
;
2944 ralloc_free(shader
);
2949 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
2951 struct vc4_context
*vc4
= vc4_context(pctx
);
2952 struct vc4_uncompiled_shader
*so
= hwcso
;
2954 struct hash_entry
*entry
;
2955 hash_table_foreach(vc4
->fs_cache
, entry
) {
2956 delete_from_cache_if_matches(vc4
->fs_cache
, &vc4
->prog
.fs
,
2959 hash_table_foreach(vc4
->vs_cache
, entry
) {
2960 delete_from_cache_if_matches(vc4
->vs_cache
, &vc4
->prog
.vs
,
2964 ralloc_free(so
->base
.ir
.nir
);
2969 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2971 struct vc4_context
*vc4
= vc4_context(pctx
);
2972 vc4
->prog
.bind_fs
= hwcso
;
2973 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_FS
;
2977 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2979 struct vc4_context
*vc4
= vc4_context(pctx
);
2980 vc4
->prog
.bind_vs
= hwcso
;
2981 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_VS
;
2985 vc4_program_init(struct pipe_context
*pctx
)
2987 struct vc4_context
*vc4
= vc4_context(pctx
);
2989 pctx
->create_vs_state
= vc4_shader_state_create
;
2990 pctx
->delete_vs_state
= vc4_shader_state_delete
;
2992 pctx
->create_fs_state
= vc4_shader_state_create
;
2993 pctx
->delete_fs_state
= vc4_shader_state_delete
;
2995 pctx
->bind_fs_state
= vc4_fp_state_bind
;
2996 pctx
->bind_vs_state
= vc4_vp_state_bind
;
2998 vc4
->fs_cache
= _mesa_hash_table_create(pctx
, fs_cache_hash
,
3000 vc4
->vs_cache
= _mesa_hash_table_create(pctx
, vs_cache_hash
,
3002 vc4
->fs_inputs_set
= _mesa_set_create(pctx
, fs_inputs_hash
,
3007 vc4_program_fini(struct pipe_context
*pctx
)
3009 struct vc4_context
*vc4
= vc4_context(pctx
);
3011 struct hash_entry
*entry
;
3012 hash_table_foreach(vc4
->fs_cache
, entry
) {
3013 struct vc4_compiled_shader
*shader
= entry
->data
;
3014 vc4_bo_unreference(&shader
->bo
);
3015 ralloc_free(shader
);
3016 _mesa_hash_table_remove(vc4
->fs_cache
, entry
);
3019 hash_table_foreach(vc4
->vs_cache
, entry
) {
3020 struct vc4_compiled_shader
*shader
= entry
->data
;
3021 vc4_bo_unreference(&shader
->bo
);
3022 ralloc_free(shader
);
3023 _mesa_hash_table_remove(vc4
->vs_cache
, entry
);