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vc4: do not report alpha-test as supported
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/crc32.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "compiler/nir_types.h"
37 #include "nir/tgsi_to_nir.h"
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41
42 static struct qreg
43 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
44 static void
45 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
46
47 static int
48 type_size(const struct glsl_type *type, bool bindless)
49 {
50 return glsl_count_attribute_slots(type, false);
51 }
52
53 static void
54 resize_qreg_array(struct vc4_compile *c,
55 struct qreg **regs,
56 uint32_t *size,
57 uint32_t decl_size)
58 {
59 if (*size >= decl_size)
60 return;
61
62 uint32_t old_size = *size;
63 *size = MAX2(*size * 2, decl_size);
64 *regs = reralloc(c, *regs, struct qreg, *size);
65 if (!*regs) {
66 fprintf(stderr, "Malloc failure\n");
67 abort();
68 }
69
70 for (uint32_t i = old_size; i < *size; i++)
71 (*regs)[i] = c->undef;
72 }
73
74 static void
75 ntq_emit_thrsw(struct vc4_compile *c)
76 {
77 if (!c->fs_threaded)
78 return;
79
80 /* Always thread switch after each texture operation for now.
81 *
82 * We could do better by batching a bunch of texture fetches up and
83 * then doing one thread switch and collecting all their results
84 * afterward.
85 */
86 qir_emit_nondef(c, qir_inst(QOP_THRSW, c->undef,
87 c->undef, c->undef));
88 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
89 }
90
91 static struct qreg
92 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
93 {
94 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
95
96 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
97 uint32_t range = nir_intrinsic_range(intr);
98 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
99 indirect_offset = qir_MIN_NOIMM(c, indirect_offset,
100 qir_uniform_ui(c, range - 4));
101
102 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
103 indirect_offset,
104 qir_uniform(c, QUNIFORM_UBO0_ADDR,
105 nir_intrinsic_base(intr)));
106
107 c->num_texture_samples++;
108
109 ntq_emit_thrsw(c);
110
111 return qir_TEX_RESULT(c);
112 }
113
114 static struct qreg
115 vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
116 {
117 int buffer_index = nir_src_as_uint(intr->src[0]);
118 assert(buffer_index == 1);
119 assert(c->stage == QSTAGE_FRAG);
120
121 struct qreg offset = ntq_get_src(c, intr->src[1], 0);
122
123 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
124 offset = qir_MAX(c, offset, qir_uniform_ui(c, 0));
125 offset = qir_MIN_NOIMM(c, offset,
126 qir_uniform_ui(c, c->fs_key->ubo_1_size - 4));
127
128 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
129 offset,
130 qir_uniform(c, QUNIFORM_UBO1_ADDR, 0));
131
132 c->num_texture_samples++;
133
134 ntq_emit_thrsw(c);
135
136 return qir_TEX_RESULT(c);
137 }
138
139 nir_ssa_def *
140 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
141 {
142 switch (swiz) {
143 default:
144 case PIPE_SWIZZLE_NONE:
145 fprintf(stderr, "warning: unknown swizzle\n");
146 /* FALLTHROUGH */
147 case PIPE_SWIZZLE_0:
148 return nir_imm_float(b, 0.0);
149 case PIPE_SWIZZLE_1:
150 return nir_imm_float(b, 1.0);
151 case PIPE_SWIZZLE_X:
152 case PIPE_SWIZZLE_Y:
153 case PIPE_SWIZZLE_Z:
154 case PIPE_SWIZZLE_W:
155 return srcs[swiz];
156 }
157 }
158
159 static struct qreg *
160 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
161 {
162 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
163 def->num_components);
164 _mesa_hash_table_insert(c->def_ht, def, qregs);
165 return qregs;
166 }
167
168 /**
169 * This function is responsible for getting QIR results into the associated
170 * storage for a NIR instruction.
171 *
172 * If it's a NIR SSA def, then we just set the associated hash table entry to
173 * the new result.
174 *
175 * If it's a NIR reg, then we need to update the existing qreg assigned to the
176 * NIR destination with the incoming value. To do that without introducing
177 * new MOVs, we require that the incoming qreg either be a uniform, or be
178 * SSA-defined by the previous QIR instruction in the block and rewritable by
179 * this function. That lets us sneak ahead and insert the SF flag beforehand
180 * (knowing that the previous instruction doesn't depend on flags) and rewrite
181 * its destination to be the NIR reg's destination
182 */
183 static void
184 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
185 struct qreg result)
186 {
187 struct qinst *last_inst = NULL;
188 if (!list_empty(&c->cur_block->instructions))
189 last_inst = (struct qinst *)c->cur_block->instructions.prev;
190
191 assert(result.file == QFILE_UNIF ||
192 (result.file == QFILE_TEMP &&
193 last_inst && last_inst == c->defs[result.index]));
194
195 if (dest->is_ssa) {
196 assert(chan < dest->ssa.num_components);
197
198 struct qreg *qregs;
199 struct hash_entry *entry =
200 _mesa_hash_table_search(c->def_ht, &dest->ssa);
201
202 if (entry)
203 qregs = entry->data;
204 else
205 qregs = ntq_init_ssa_def(c, &dest->ssa);
206
207 qregs[chan] = result;
208 } else {
209 nir_register *reg = dest->reg.reg;
210 assert(dest->reg.base_offset == 0);
211 assert(reg->num_array_elems == 0);
212 struct hash_entry *entry =
213 _mesa_hash_table_search(c->def_ht, reg);
214 struct qreg *qregs = entry->data;
215
216 /* Insert a MOV if the source wasn't an SSA def in the
217 * previous instruction.
218 */
219 if (result.file == QFILE_UNIF) {
220 result = qir_MOV(c, result);
221 last_inst = c->defs[result.index];
222 }
223
224 /* We know they're both temps, so just rewrite index. */
225 c->defs[last_inst->dst.index] = NULL;
226 last_inst->dst.index = qregs[chan].index;
227
228 /* If we're in control flow, then make this update of the reg
229 * conditional on the execution mask.
230 */
231 if (c->execute.file != QFILE_NULL) {
232 last_inst->dst.index = qregs[chan].index;
233
234 /* Set the flags to the current exec mask. To insert
235 * the SF, we temporarily remove our SSA instruction.
236 */
237 list_del(&last_inst->link);
238 qir_SF(c, c->execute);
239 list_addtail(&last_inst->link,
240 &c->cur_block->instructions);
241
242 last_inst->cond = QPU_COND_ZS;
243 last_inst->cond_is_exec_mask = true;
244 }
245 }
246 }
247
248 static struct qreg *
249 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
250 {
251 if (dest->is_ssa) {
252 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
253 for (int i = 0; i < dest->ssa.num_components; i++)
254 qregs[i] = c->undef;
255 return qregs;
256 } else {
257 nir_register *reg = dest->reg.reg;
258 assert(dest->reg.base_offset == 0);
259 assert(reg->num_array_elems == 0);
260 struct hash_entry *entry =
261 _mesa_hash_table_search(c->def_ht, reg);
262 return entry->data;
263 }
264 }
265
266 static struct qreg
267 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
268 {
269 struct hash_entry *entry;
270 if (src.is_ssa) {
271 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
272 assert(i < src.ssa->num_components);
273 } else {
274 nir_register *reg = src.reg.reg;
275 entry = _mesa_hash_table_search(c->def_ht, reg);
276 assert(reg->num_array_elems == 0);
277 assert(src.reg.base_offset == 0);
278 assert(i < reg->num_components);
279 }
280
281 struct qreg *qregs = entry->data;
282 return qregs[i];
283 }
284
285 static struct qreg
286 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
287 unsigned src)
288 {
289 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
290 unsigned chan = ffs(instr->dest.write_mask) - 1;
291 struct qreg r = ntq_get_src(c, instr->src[src].src,
292 instr->src[src].swizzle[chan]);
293
294 assert(!instr->src[src].abs);
295 assert(!instr->src[src].negate);
296
297 return r;
298 };
299
300 static inline struct qreg
301 qir_SAT(struct vc4_compile *c, struct qreg val)
302 {
303 return qir_FMAX(c,
304 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
305 qir_uniform_f(c, 0.0));
306 }
307
308 static struct qreg
309 ntq_rcp(struct vc4_compile *c, struct qreg x)
310 {
311 struct qreg r = qir_RCP(c, x);
312
313 /* Apply a Newton-Raphson step to improve the accuracy. */
314 r = qir_FMUL(c, r, qir_FSUB(c,
315 qir_uniform_f(c, 2.0),
316 qir_FMUL(c, x, r)));
317
318 return r;
319 }
320
321 static struct qreg
322 ntq_rsq(struct vc4_compile *c, struct qreg x)
323 {
324 struct qreg r = qir_RSQ(c, x);
325
326 /* Apply a Newton-Raphson step to improve the accuracy. */
327 r = qir_FMUL(c, r, qir_FSUB(c,
328 qir_uniform_f(c, 1.5),
329 qir_FMUL(c,
330 qir_uniform_f(c, 0.5),
331 qir_FMUL(c, x,
332 qir_FMUL(c, r, r)))));
333
334 return r;
335 }
336
337 static struct qreg
338 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
339 {
340 struct qreg src0_hi = qir_SHR(c, src0,
341 qir_uniform_ui(c, 24));
342 struct qreg src1_hi = qir_SHR(c, src1,
343 qir_uniform_ui(c, 24));
344
345 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
346 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
347 struct qreg lolo = qir_MUL24(c, src0, src1);
348
349 return qir_ADD(c, lolo, qir_SHL(c,
350 qir_ADD(c, hilo, lohi),
351 qir_uniform_ui(c, 24)));
352 }
353
354 static struct qreg
355 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
356 {
357 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
358 qir_uniform_ui(c, 8)));
359 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
360 }
361
362 /**
363 * Emits a lowered TXF_MS from an MSAA texture.
364 *
365 * The addressing math has been lowered in NIR, and now we just need to read
366 * it like a UBO.
367 */
368 static void
369 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
370 {
371 uint32_t tile_width = 32;
372 uint32_t tile_height = 32;
373 uint32_t tile_size = (tile_height * tile_width *
374 VC4_MAX_SAMPLES * sizeof(uint32_t));
375
376 unsigned unit = instr->texture_index;
377 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
378 uint32_t w_tiles = w / tile_width;
379 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
380 uint32_t h_tiles = h / tile_height;
381 uint32_t size = w_tiles * h_tiles * tile_size;
382
383 struct qreg addr;
384 assert(instr->num_srcs == 1);
385 assert(instr->src[0].src_type == nir_tex_src_coord);
386 addr = ntq_get_src(c, instr->src[0].src, 0);
387
388 /* Perform the clamping required by kernel validation. */
389 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
390 addr = qir_MIN_NOIMM(c, addr, qir_uniform_ui(c, size - 4));
391
392 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
393 addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
394
395 ntq_emit_thrsw(c);
396
397 struct qreg tex = qir_TEX_RESULT(c);
398 c->num_texture_samples++;
399
400 enum pipe_format format = c->key->tex[unit].format;
401 if (util_format_is_depth_or_stencil(format)) {
402 struct qreg scaled = ntq_scale_depth_texture(c, tex);
403 for (int i = 0; i < 4; i++)
404 ntq_store_dest(c, &instr->dest, i, qir_MOV(c, scaled));
405 } else {
406 for (int i = 0; i < 4; i++)
407 ntq_store_dest(c, &instr->dest, i,
408 qir_UNPACK_8_F(c, tex, i));
409 }
410 }
411
412 static void
413 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
414 {
415 struct qreg s, t, r, lod, compare;
416 bool is_txb = false, is_txl = false;
417 unsigned unit = instr->texture_index;
418
419 if (instr->op == nir_texop_txf) {
420 ntq_emit_txf(c, instr);
421 return;
422 }
423
424 for (unsigned i = 0; i < instr->num_srcs; i++) {
425 switch (instr->src[i].src_type) {
426 case nir_tex_src_coord:
427 s = ntq_get_src(c, instr->src[i].src, 0);
428 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
429 t = qir_uniform_f(c, 0.5);
430 else
431 t = ntq_get_src(c, instr->src[i].src, 1);
432 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
433 r = ntq_get_src(c, instr->src[i].src, 2);
434 break;
435 case nir_tex_src_bias:
436 lod = ntq_get_src(c, instr->src[i].src, 0);
437 is_txb = true;
438 break;
439 case nir_tex_src_lod:
440 lod = ntq_get_src(c, instr->src[i].src, 0);
441 is_txl = true;
442 break;
443 case nir_tex_src_comparator:
444 compare = ntq_get_src(c, instr->src[i].src, 0);
445 break;
446 default:
447 unreachable("unknown texture source");
448 }
449 }
450
451 if (c->stage != QSTAGE_FRAG && !is_txl) {
452 /* From the GLSL 1.20 spec:
453 *
454 * "If it is mip-mapped and running on the vertex shader,
455 * then the base texture is used."
456 */
457 is_txl = true;
458 lod = qir_uniform_ui(c, 0);
459 }
460
461 if (c->key->tex[unit].force_first_level) {
462 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
463 is_txl = true;
464 is_txb = false;
465 }
466
467 struct qreg texture_u[] = {
468 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
469 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
470 qir_uniform(c, QUNIFORM_CONSTANT, 0),
471 qir_uniform(c, QUNIFORM_CONSTANT, 0),
472 };
473 uint32_t next_texture_u = 0;
474
475 /* There is no native support for GL texture rectangle coordinates, so
476 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
477 * 1]).
478 */
479 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
480 s = qir_FMUL(c, s,
481 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
482 t = qir_FMUL(c, t,
483 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
484 }
485
486 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
487 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
488 unit | (is_txl << 16));
489 }
490
491 struct qinst *tmu;
492 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
493 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), r);
494 tmu->src[qir_get_tex_uniform_src(tmu)] =
495 texture_u[next_texture_u++];
496 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
497 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
498 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
499 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
500 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0),
501 qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR,
502 unit));
503 tmu->src[qir_get_tex_uniform_src(tmu)] =
504 texture_u[next_texture_u++];
505 }
506
507 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
508 s = qir_SAT(c, s);
509 }
510
511 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
512 t = qir_SAT(c, t);
513 }
514
515 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_T, 0), t);
516 tmu->src[qir_get_tex_uniform_src(tmu)] =
517 texture_u[next_texture_u++];
518
519 if (is_txl || is_txb) {
520 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_B, 0), lod);
521 tmu->src[qir_get_tex_uniform_src(tmu)] =
522 texture_u[next_texture_u++];
523 }
524
525 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_S, 0), s);
526 tmu->src[qir_get_tex_uniform_src(tmu)] = texture_u[next_texture_u++];
527
528 c->num_texture_samples++;
529
530 ntq_emit_thrsw(c);
531
532 struct qreg tex = qir_TEX_RESULT(c);
533
534 enum pipe_format format = c->key->tex[unit].format;
535
536 struct qreg *dest = ntq_get_dest(c, &instr->dest);
537 if (util_format_is_depth_or_stencil(format)) {
538 struct qreg normalized = ntq_scale_depth_texture(c, tex);
539 struct qreg depth_output;
540
541 struct qreg u0 = qir_uniform_f(c, 0.0f);
542 struct qreg u1 = qir_uniform_f(c, 1.0f);
543 if (c->key->tex[unit].compare_mode) {
544 /* From the GL_ARB_shadow spec:
545 *
546 * "Let Dt (D subscript t) be the depth texture
547 * value, in the range [0, 1]. Let R be the
548 * interpolated texture coordinate clamped to the
549 * range [0, 1]."
550 */
551 compare = qir_SAT(c, compare);
552
553 switch (c->key->tex[unit].compare_func) {
554 case PIPE_FUNC_NEVER:
555 depth_output = qir_uniform_f(c, 0.0f);
556 break;
557 case PIPE_FUNC_ALWAYS:
558 depth_output = u1;
559 break;
560 case PIPE_FUNC_EQUAL:
561 qir_SF(c, qir_FSUB(c, compare, normalized));
562 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
563 break;
564 case PIPE_FUNC_NOTEQUAL:
565 qir_SF(c, qir_FSUB(c, compare, normalized));
566 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
567 break;
568 case PIPE_FUNC_GREATER:
569 qir_SF(c, qir_FSUB(c, compare, normalized));
570 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
571 break;
572 case PIPE_FUNC_GEQUAL:
573 qir_SF(c, qir_FSUB(c, normalized, compare));
574 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
575 break;
576 case PIPE_FUNC_LESS:
577 qir_SF(c, qir_FSUB(c, compare, normalized));
578 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
579 break;
580 case PIPE_FUNC_LEQUAL:
581 qir_SF(c, qir_FSUB(c, normalized, compare));
582 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
583 break;
584 }
585 } else {
586 depth_output = normalized;
587 }
588
589 for (int i = 0; i < 4; i++)
590 dest[i] = depth_output;
591 } else {
592 for (int i = 0; i < 4; i++)
593 dest[i] = qir_UNPACK_8_F(c, tex, i);
594 }
595 }
596
597 /**
598 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
599 * to zero).
600 */
601 static struct qreg
602 ntq_ffract(struct vc4_compile *c, struct qreg src)
603 {
604 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
605 struct qreg diff = qir_FSUB(c, src, trunc);
606 qir_SF(c, diff);
607
608 qir_FADD_dest(c, diff,
609 diff, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
610
611 return qir_MOV(c, diff);
612 }
613
614 /**
615 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
616 * zero).
617 */
618 static struct qreg
619 ntq_ffloor(struct vc4_compile *c, struct qreg src)
620 {
621 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
622
623 /* This will be < 0 if we truncated and the truncation was of a value
624 * that was < 0 in the first place.
625 */
626 qir_SF(c, qir_FSUB(c, src, result));
627
628 struct qinst *sub = qir_FSUB_dest(c, result,
629 result, qir_uniform_f(c, 1.0));
630 sub->cond = QPU_COND_NS;
631
632 return qir_MOV(c, result);
633 }
634
635 /**
636 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
637 * zero).
638 */
639 static struct qreg
640 ntq_fceil(struct vc4_compile *c, struct qreg src)
641 {
642 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
643
644 /* This will be < 0 if we truncated and the truncation was of a value
645 * that was > 0 in the first place.
646 */
647 qir_SF(c, qir_FSUB(c, result, src));
648
649 qir_FADD_dest(c, result,
650 result, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
651
652 return qir_MOV(c, result);
653 }
654
655 static struct qreg
656 ntq_shrink_sincos_input_range(struct vc4_compile *c, struct qreg x)
657 {
658 /* Since we're using a Taylor approximation, we want to have a small
659 * number of coefficients and take advantage of sin/cos repeating
660 * every 2pi. We keep our x as close to 0 as we can, since the series
661 * will be less accurate as |x| increases. (Also, be careful of
662 * shifting the input x value to be tricky with sin/cos relations,
663 * because getting accurate values for x==0 is very important for SDL
664 * rendering)
665 */
666 struct qreg scaled_x =
667 qir_FMUL(c, x,
668 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
669 /* Note: FTOI truncates toward 0. */
670 struct qreg x_frac = qir_FSUB(c, scaled_x,
671 qir_ITOF(c, qir_FTOI(c, scaled_x)));
672 /* Map [0.5, 1] to [-0.5, 0] */
673 qir_SF(c, qir_FSUB(c, x_frac, qir_uniform_f(c, 0.5)));
674 qir_FSUB_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NC;
675 /* Map [-1, -0.5] to [0, 0.5] */
676 qir_SF(c, qir_FADD(c, x_frac, qir_uniform_f(c, 0.5)));
677 qir_FADD_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
678
679 return x_frac;
680 }
681
682 static struct qreg
683 ntq_fsin(struct vc4_compile *c, struct qreg src)
684 {
685 float coeff[] = {
686 2.0 * M_PI,
687 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
688 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
689 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
690 pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
691 };
692
693 struct qreg x = ntq_shrink_sincos_input_range(c, src);
694 struct qreg x2 = qir_FMUL(c, x, x);
695 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
696 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
697 x = qir_FMUL(c, x, x2);
698 sum = qir_FADD(c,
699 sum,
700 qir_FMUL(c,
701 x,
702 qir_uniform_f(c, coeff[i])));
703 }
704 return sum;
705 }
706
707 static struct qreg
708 ntq_fcos(struct vc4_compile *c, struct qreg src)
709 {
710 float coeff[] = {
711 1.0f,
712 -pow(2.0 * M_PI, 2) / (2 * 1),
713 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
714 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
715 pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
716 -pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
717 };
718
719 struct qreg x_frac = ntq_shrink_sincos_input_range(c, src);
720 struct qreg sum = qir_uniform_f(c, coeff[0]);
721 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
722 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
723 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
724 if (i != 1)
725 x = qir_FMUL(c, x, x2);
726
727 sum = qir_FADD(c, qir_FMUL(c,
728 x,
729 qir_uniform_f(c, coeff[i])),
730 sum);
731 }
732 return sum;
733 }
734
735 static struct qreg
736 ntq_fsign(struct vc4_compile *c, struct qreg src)
737 {
738 struct qreg t = qir_get_temp(c);
739
740 qir_SF(c, src);
741 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
742 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
743 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
744 return qir_MOV(c, t);
745 }
746
747 static void
748 emit_vertex_input(struct vc4_compile *c, int attr)
749 {
750 enum pipe_format format = c->vs_key->attr_formats[attr];
751 uint32_t attr_size = util_format_get_blocksize(format);
752
753 c->vattr_sizes[attr] = align(attr_size, 4);
754 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
755 c->inputs[attr * 4 + i] =
756 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
757 c->num_inputs++;
758 }
759 }
760
761 static void
762 emit_fragcoord_input(struct vc4_compile *c, int attr)
763 {
764 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
765 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
766 c->inputs[attr * 4 + 2] =
767 qir_FMUL(c,
768 qir_ITOF(c, qir_FRAG_Z(c)),
769 qir_uniform_f(c, 1.0 / 0xffffff));
770 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
771 }
772
773 static struct qreg
774 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
775 uint8_t swizzle)
776 {
777 uint32_t i = c->num_input_slots++;
778 struct qreg vary = {
779 QFILE_VARY,
780 i
781 };
782
783 if (c->num_input_slots >= c->input_slots_array_size) {
784 c->input_slots_array_size =
785 MAX2(4, c->input_slots_array_size * 2);
786
787 c->input_slots = reralloc(c, c->input_slots,
788 struct vc4_varying_slot,
789 c->input_slots_array_size);
790 }
791
792 c->input_slots[i].slot = slot;
793 c->input_slots[i].swizzle = swizzle;
794
795 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
796 }
797
798 static void
799 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
800 {
801 for (int i = 0; i < 4; i++) {
802 c->inputs[attr * 4 + i] =
803 emit_fragment_varying(c, slot, i);
804 c->num_inputs++;
805 }
806 }
807
808 static void
809 add_output(struct vc4_compile *c,
810 uint32_t decl_offset,
811 uint8_t slot,
812 uint8_t swizzle)
813 {
814 uint32_t old_array_size = c->outputs_array_size;
815 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
816 decl_offset + 1);
817
818 if (old_array_size != c->outputs_array_size) {
819 c->output_slots = reralloc(c,
820 c->output_slots,
821 struct vc4_varying_slot,
822 c->outputs_array_size);
823 }
824
825 c->output_slots[decl_offset].slot = slot;
826 c->output_slots[decl_offset].swizzle = swizzle;
827 }
828
829 static bool
830 ntq_src_is_only_ssa_def_user(nir_src *src)
831 {
832 if (!src->is_ssa)
833 return false;
834
835 if (!list_empty(&src->ssa->if_uses))
836 return false;
837
838 return (src->ssa->uses.next == &src->use_link &&
839 src->ssa->uses.next->next == &src->ssa->uses);
840 }
841
842 /**
843 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
844 * bit set.
845 *
846 * However, as an optimization, it tries to find the instructions generating
847 * the sources to be packed and just emit the pack flag there, if possible.
848 */
849 static void
850 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
851 {
852 struct qreg result = qir_get_temp(c);
853 struct nir_alu_instr *vec4 = NULL;
854
855 /* If packing from a vec4 op (as expected), identify it so that we can
856 * peek back at what generated its sources.
857 */
858 if (instr->src[0].src.is_ssa &&
859 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
860 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
861 nir_op_vec4) {
862 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
863 }
864
865 /* If the pack is replicating the same channel 4 times, use the 8888
866 * pack flag. This is common for blending using the alpha
867 * channel.
868 */
869 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
870 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
871 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
872 struct qreg rep = ntq_get_src(c,
873 instr->src[0].src,
874 instr->src[0].swizzle[0]);
875 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
876 return;
877 }
878
879 for (int i = 0; i < 4; i++) {
880 int swiz = instr->src[0].swizzle[i];
881 struct qreg src;
882 if (vec4) {
883 src = ntq_get_src(c, vec4->src[swiz].src,
884 vec4->src[swiz].swizzle[0]);
885 } else {
886 src = ntq_get_src(c, instr->src[0].src, swiz);
887 }
888
889 if (vec4 &&
890 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
891 src.file == QFILE_TEMP &&
892 c->defs[src.index] &&
893 qir_is_mul(c->defs[src.index]) &&
894 !c->defs[src.index]->dst.pack) {
895 struct qinst *rewrite = c->defs[src.index];
896 c->defs[src.index] = NULL;
897 rewrite->dst = result;
898 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
899 continue;
900 }
901
902 qir_PACK_8_F(c, result, src, i);
903 }
904
905 ntq_store_dest(c, &instr->dest.dest, 0, qir_MOV(c, result));
906 }
907
908 /** Handles sign-extended bitfield extracts for 16 bits. */
909 static struct qreg
910 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
911 struct qreg bits)
912 {
913 assert(bits.file == QFILE_UNIF &&
914 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
915 c->uniform_data[bits.index] == 16);
916
917 assert(offset.file == QFILE_UNIF &&
918 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
919 int offset_bit = c->uniform_data[offset.index];
920 assert(offset_bit % 16 == 0);
921
922 return qir_UNPACK_16_I(c, base, offset_bit / 16);
923 }
924
925 /** Handles unsigned bitfield extracts for 8 bits. */
926 static struct qreg
927 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
928 struct qreg bits)
929 {
930 assert(bits.file == QFILE_UNIF &&
931 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
932 c->uniform_data[bits.index] == 8);
933
934 assert(offset.file == QFILE_UNIF &&
935 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
936 int offset_bit = c->uniform_data[offset.index];
937 assert(offset_bit % 8 == 0);
938
939 return qir_UNPACK_8_I(c, base, offset_bit / 8);
940 }
941
942 /**
943 * If compare_instr is a valid comparison instruction, emits the
944 * compare_instr's comparison and returns the sel_instr's return value based
945 * on the compare_instr's result.
946 */
947 static bool
948 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
949 nir_alu_instr *compare_instr,
950 nir_alu_instr *sel_instr)
951 {
952 enum qpu_cond cond;
953
954 switch (compare_instr->op) {
955 case nir_op_feq32:
956 case nir_op_ieq32:
957 case nir_op_seq:
958 cond = QPU_COND_ZS;
959 break;
960 case nir_op_fne32:
961 case nir_op_ine32:
962 case nir_op_sne:
963 cond = QPU_COND_ZC;
964 break;
965 case nir_op_fge32:
966 case nir_op_ige32:
967 case nir_op_uge32:
968 case nir_op_sge:
969 cond = QPU_COND_NC;
970 break;
971 case nir_op_flt32:
972 case nir_op_ilt32:
973 case nir_op_slt:
974 cond = QPU_COND_NS;
975 break;
976 default:
977 return false;
978 }
979
980 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
981 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
982
983 unsigned unsized_type =
984 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
985 if (unsized_type == nir_type_float)
986 qir_SF(c, qir_FSUB(c, src0, src1));
987 else
988 qir_SF(c, qir_SUB(c, src0, src1));
989
990 switch (sel_instr->op) {
991 case nir_op_seq:
992 case nir_op_sne:
993 case nir_op_sge:
994 case nir_op_slt:
995 *dest = qir_SEL(c, cond,
996 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
997 break;
998
999 case nir_op_b32csel:
1000 *dest = qir_SEL(c, cond,
1001 ntq_get_alu_src(c, sel_instr, 1),
1002 ntq_get_alu_src(c, sel_instr, 2));
1003 break;
1004
1005 default:
1006 *dest = qir_SEL(c, cond,
1007 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
1008 break;
1009 }
1010
1011 /* Make the temporary for nir_store_dest(). */
1012 *dest = qir_MOV(c, *dest);
1013
1014 return true;
1015 }
1016
1017 /**
1018 * Attempts to fold a comparison generating a boolean result into the
1019 * condition code for selecting between two values, instead of comparing the
1020 * boolean result against 0 to generate the condition code.
1021 */
1022 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
1023 struct qreg *src)
1024 {
1025 if (!instr->src[0].src.is_ssa)
1026 goto out;
1027 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
1028 goto out;
1029 nir_alu_instr *compare =
1030 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
1031 if (!compare)
1032 goto out;
1033
1034 struct qreg dest;
1035 if (ntq_emit_comparison(c, &dest, compare, instr))
1036 return dest;
1037
1038 out:
1039 qir_SF(c, src[0]);
1040 return qir_MOV(c, qir_SEL(c, QPU_COND_NS, src[1], src[2]));
1041 }
1042
1043 static struct qreg
1044 ntq_fddx(struct vc4_compile *c, struct qreg src)
1045 {
1046 /* Make sure that we have a bare temp to use for MUL rotation, so it
1047 * can be allocated to an accumulator.
1048 */
1049 if (src.pack || src.file != QFILE_TEMP)
1050 src = qir_MOV(c, src);
1051
1052 struct qreg from_left = qir_ROT_MUL(c, src, 1);
1053 struct qreg from_right = qir_ROT_MUL(c, src, 15);
1054
1055 /* Distinguish left/right pixels of the quad. */
1056 qir_SF(c, qir_AND(c, qir_reg(QFILE_QPU_ELEMENT, 0),
1057 qir_uniform_ui(c, 1)));
1058
1059 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1060 qir_FSUB(c, from_right, src),
1061 qir_FSUB(c, src, from_left)));
1062 }
1063
1064 static struct qreg
1065 ntq_fddy(struct vc4_compile *c, struct qreg src)
1066 {
1067 if (src.pack || src.file != QFILE_TEMP)
1068 src = qir_MOV(c, src);
1069
1070 struct qreg from_bottom = qir_ROT_MUL(c, src, 2);
1071 struct qreg from_top = qir_ROT_MUL(c, src, 14);
1072
1073 /* Distinguish top/bottom pixels of the quad. */
1074 qir_SF(c, qir_AND(c,
1075 qir_reg(QFILE_QPU_ELEMENT, 0),
1076 qir_uniform_ui(c, 2)));
1077
1078 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1079 qir_FSUB(c, from_top, src),
1080 qir_FSUB(c, src, from_bottom)));
1081 }
1082
1083 static void
1084 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
1085 {
1086 /* This should always be lowered to ALU operations for VC4. */
1087 assert(!instr->dest.saturate);
1088
1089 /* Vectors are special in that they have non-scalarized writemasks,
1090 * and just take the first swizzle channel for each argument in order
1091 * into each writemask channel.
1092 */
1093 if (instr->op == nir_op_vec2 ||
1094 instr->op == nir_op_vec3 ||
1095 instr->op == nir_op_vec4) {
1096 struct qreg srcs[4];
1097 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1098 srcs[i] = ntq_get_src(c, instr->src[i].src,
1099 instr->src[i].swizzle[0]);
1100 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1101 ntq_store_dest(c, &instr->dest.dest, i,
1102 qir_MOV(c, srcs[i]));
1103 return;
1104 }
1105
1106 if (instr->op == nir_op_pack_unorm_4x8) {
1107 ntq_emit_pack_unorm_4x8(c, instr);
1108 return;
1109 }
1110
1111 if (instr->op == nir_op_unpack_unorm_4x8) {
1112 struct qreg src = ntq_get_src(c, instr->src[0].src,
1113 instr->src[0].swizzle[0]);
1114 for (int i = 0; i < 4; i++) {
1115 if (instr->dest.write_mask & (1 << i))
1116 ntq_store_dest(c, &instr->dest.dest, i,
1117 qir_UNPACK_8_F(c, src, i));
1118 }
1119 return;
1120 }
1121
1122 /* General case: We can just grab the one used channel per src. */
1123 struct qreg src[nir_op_infos[instr->op].num_inputs];
1124 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1125 src[i] = ntq_get_alu_src(c, instr, i);
1126 }
1127
1128 struct qreg result;
1129
1130 switch (instr->op) {
1131 case nir_op_mov:
1132 result = qir_MOV(c, src[0]);
1133 break;
1134 case nir_op_fmul:
1135 result = qir_FMUL(c, src[0], src[1]);
1136 break;
1137 case nir_op_fadd:
1138 result = qir_FADD(c, src[0], src[1]);
1139 break;
1140 case nir_op_fsub:
1141 result = qir_FSUB(c, src[0], src[1]);
1142 break;
1143 case nir_op_fmin:
1144 result = qir_FMIN(c, src[0], src[1]);
1145 break;
1146 case nir_op_fmax:
1147 result = qir_FMAX(c, src[0], src[1]);
1148 break;
1149
1150 case nir_op_f2i32:
1151 case nir_op_f2u32:
1152 result = qir_FTOI(c, src[0]);
1153 break;
1154 case nir_op_i2f32:
1155 case nir_op_u2f32:
1156 result = qir_ITOF(c, src[0]);
1157 break;
1158 case nir_op_b2f32:
1159 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1160 break;
1161 case nir_op_b2i32:
1162 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1163 break;
1164 case nir_op_i2b32:
1165 case nir_op_f2b32:
1166 qir_SF(c, src[0]);
1167 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC,
1168 qir_uniform_ui(c, ~0),
1169 qir_uniform_ui(c, 0)));
1170 break;
1171
1172 case nir_op_iadd:
1173 result = qir_ADD(c, src[0], src[1]);
1174 break;
1175 case nir_op_ushr:
1176 result = qir_SHR(c, src[0], src[1]);
1177 break;
1178 case nir_op_isub:
1179 result = qir_SUB(c, src[0], src[1]);
1180 break;
1181 case nir_op_ishr:
1182 result = qir_ASR(c, src[0], src[1]);
1183 break;
1184 case nir_op_ishl:
1185 result = qir_SHL(c, src[0], src[1]);
1186 break;
1187 case nir_op_imin:
1188 result = qir_MIN(c, src[0], src[1]);
1189 break;
1190 case nir_op_imax:
1191 result = qir_MAX(c, src[0], src[1]);
1192 break;
1193 case nir_op_iand:
1194 result = qir_AND(c, src[0], src[1]);
1195 break;
1196 case nir_op_ior:
1197 result = qir_OR(c, src[0], src[1]);
1198 break;
1199 case nir_op_ixor:
1200 result = qir_XOR(c, src[0], src[1]);
1201 break;
1202 case nir_op_inot:
1203 result = qir_NOT(c, src[0]);
1204 break;
1205
1206 case nir_op_imul:
1207 result = ntq_umul(c, src[0], src[1]);
1208 break;
1209
1210 case nir_op_seq:
1211 case nir_op_sne:
1212 case nir_op_sge:
1213 case nir_op_slt:
1214 case nir_op_feq32:
1215 case nir_op_fne32:
1216 case nir_op_fge32:
1217 case nir_op_flt32:
1218 case nir_op_ieq32:
1219 case nir_op_ine32:
1220 case nir_op_ige32:
1221 case nir_op_uge32:
1222 case nir_op_ilt32:
1223 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1224 fprintf(stderr, "Bad comparison instruction\n");
1225 }
1226 break;
1227
1228 case nir_op_b32csel:
1229 result = ntq_emit_bcsel(c, instr, src);
1230 break;
1231 case nir_op_fcsel:
1232 qir_SF(c, src[0]);
1233 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC, src[1], src[2]));
1234 break;
1235
1236 case nir_op_frcp:
1237 result = ntq_rcp(c, src[0]);
1238 break;
1239 case nir_op_frsq:
1240 result = ntq_rsq(c, src[0]);
1241 break;
1242 case nir_op_fexp2:
1243 result = qir_EXP2(c, src[0]);
1244 break;
1245 case nir_op_flog2:
1246 result = qir_LOG2(c, src[0]);
1247 break;
1248
1249 case nir_op_ftrunc:
1250 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1251 break;
1252 case nir_op_fceil:
1253 result = ntq_fceil(c, src[0]);
1254 break;
1255 case nir_op_ffract:
1256 result = ntq_ffract(c, src[0]);
1257 break;
1258 case nir_op_ffloor:
1259 result = ntq_ffloor(c, src[0]);
1260 break;
1261
1262 case nir_op_fsin:
1263 result = ntq_fsin(c, src[0]);
1264 break;
1265 case nir_op_fcos:
1266 result = ntq_fcos(c, src[0]);
1267 break;
1268
1269 case nir_op_fsign:
1270 result = ntq_fsign(c, src[0]);
1271 break;
1272
1273 case nir_op_fabs:
1274 result = qir_FMAXABS(c, src[0], src[0]);
1275 break;
1276 case nir_op_iabs:
1277 result = qir_MAX(c, src[0],
1278 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1279 break;
1280
1281 case nir_op_ibitfield_extract:
1282 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1283 break;
1284
1285 case nir_op_ubitfield_extract:
1286 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1287 break;
1288
1289 case nir_op_usadd_4x8:
1290 result = qir_V8ADDS(c, src[0], src[1]);
1291 break;
1292
1293 case nir_op_ussub_4x8:
1294 result = qir_V8SUBS(c, src[0], src[1]);
1295 break;
1296
1297 case nir_op_umin_4x8:
1298 result = qir_V8MIN(c, src[0], src[1]);
1299 break;
1300
1301 case nir_op_umax_4x8:
1302 result = qir_V8MAX(c, src[0], src[1]);
1303 break;
1304
1305 case nir_op_umul_unorm_4x8:
1306 result = qir_V8MULD(c, src[0], src[1]);
1307 break;
1308
1309 case nir_op_fddx:
1310 case nir_op_fddx_coarse:
1311 case nir_op_fddx_fine:
1312 result = ntq_fddx(c, src[0]);
1313 break;
1314
1315 case nir_op_fddy:
1316 case nir_op_fddy_coarse:
1317 case nir_op_fddy_fine:
1318 result = ntq_fddy(c, src[0]);
1319 break;
1320
1321 default:
1322 fprintf(stderr, "unknown NIR ALU inst: ");
1323 nir_print_instr(&instr->instr, stderr);
1324 fprintf(stderr, "\n");
1325 abort();
1326 }
1327
1328 /* We have a scalar result, so the instruction should only have a
1329 * single channel written to.
1330 */
1331 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1332 ntq_store_dest(c, &instr->dest.dest,
1333 ffs(instr->dest.write_mask) - 1, result);
1334 }
1335
1336 static void
1337 emit_frag_end(struct vc4_compile *c)
1338 {
1339 struct qreg color;
1340 if (c->output_color_index != -1) {
1341 color = c->outputs[c->output_color_index];
1342 } else {
1343 color = qir_uniform_ui(c, 0);
1344 }
1345
1346 uint32_t discard_cond = QPU_COND_ALWAYS;
1347 if (c->s->info.fs.uses_discard) {
1348 qir_SF(c, c->discard);
1349 discard_cond = QPU_COND_ZS;
1350 }
1351
1352 if (c->fs_key->stencil_enabled) {
1353 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1354 qir_uniform(c, QUNIFORM_STENCIL, 0));
1355 if (c->fs_key->stencil_twoside) {
1356 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1357 qir_uniform(c, QUNIFORM_STENCIL, 1));
1358 }
1359 if (c->fs_key->stencil_full_writemasks) {
1360 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1361 qir_uniform(c, QUNIFORM_STENCIL, 2));
1362 }
1363 }
1364
1365 if (c->output_sample_mask_index != -1) {
1366 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1367 }
1368
1369 if (c->fs_key->depth_enabled) {
1370 if (c->output_position_index != -1) {
1371 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1372 qir_FMUL(c,
1373 c->outputs[c->output_position_index],
1374 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1375 } else {
1376 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1377 qir_FRAG_Z(c))->cond = discard_cond;
1378 }
1379 }
1380
1381 if (!c->msaa_per_sample_output) {
1382 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1383 color)->cond = discard_cond;
1384 } else {
1385 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1386 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1387 c->sample_colors[i])->cond = discard_cond;
1388 }
1389 }
1390 }
1391
1392 static void
1393 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1394 {
1395 struct qreg packed = qir_get_temp(c);
1396
1397 for (int i = 0; i < 2; i++) {
1398 struct qreg scale =
1399 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1400
1401 struct qreg packed_chan = packed;
1402 packed_chan.pack = QPU_PACK_A_16A + i;
1403
1404 qir_FTOI_dest(c, packed_chan,
1405 qir_FMUL(c,
1406 qir_FMUL(c,
1407 c->outputs[c->output_position_index + i],
1408 scale),
1409 rcp_w));
1410 }
1411
1412 qir_VPM_WRITE(c, packed);
1413 }
1414
1415 static void
1416 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1417 {
1418 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1419 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1420
1421 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1422 c->outputs[c->output_position_index + 2],
1423 zscale),
1424 rcp_w),
1425 zoffset));
1426 }
1427
1428 static void
1429 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1430 {
1431 qir_VPM_WRITE(c, rcp_w);
1432 }
1433
1434 static void
1435 emit_point_size_write(struct vc4_compile *c)
1436 {
1437 struct qreg point_size;
1438
1439 if (c->output_point_size_index != -1)
1440 point_size = c->outputs[c->output_point_size_index];
1441 else
1442 point_size = qir_uniform_f(c, 1.0);
1443
1444 qir_VPM_WRITE(c, point_size);
1445 }
1446
1447 /**
1448 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1449 *
1450 * The simulator insists that there be at least one vertex attribute, so
1451 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1452 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1453 * to consume it here.
1454 */
1455 static void
1456 emit_stub_vpm_read(struct vc4_compile *c)
1457 {
1458 if (c->num_inputs)
1459 return;
1460
1461 c->vattr_sizes[0] = 4;
1462 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1463 c->num_inputs++;
1464 }
1465
1466 static void
1467 emit_vert_end(struct vc4_compile *c,
1468 struct vc4_varying_slot *fs_inputs,
1469 uint32_t num_fs_inputs)
1470 {
1471 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1472
1473 emit_stub_vpm_read(c);
1474
1475 emit_scaled_viewport_write(c, rcp_w);
1476 emit_zs_write(c, rcp_w);
1477 emit_rcp_wc_write(c, rcp_w);
1478 if (c->vs_key->per_vertex_point_size)
1479 emit_point_size_write(c);
1480
1481 for (int i = 0; i < num_fs_inputs; i++) {
1482 struct vc4_varying_slot *input = &fs_inputs[i];
1483 int j;
1484
1485 for (j = 0; j < c->num_outputs; j++) {
1486 struct vc4_varying_slot *output =
1487 &c->output_slots[j];
1488
1489 if (input->slot == output->slot &&
1490 input->swizzle == output->swizzle) {
1491 qir_VPM_WRITE(c, c->outputs[j]);
1492 break;
1493 }
1494 }
1495 /* Emit padding if we didn't find a declared VS output for
1496 * this FS input.
1497 */
1498 if (j == c->num_outputs)
1499 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1500 }
1501 }
1502
1503 static void
1504 emit_coord_end(struct vc4_compile *c)
1505 {
1506 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1507
1508 emit_stub_vpm_read(c);
1509
1510 for (int i = 0; i < 4; i++)
1511 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1512
1513 emit_scaled_viewport_write(c, rcp_w);
1514 emit_zs_write(c, rcp_w);
1515 emit_rcp_wc_write(c, rcp_w);
1516 if (c->vs_key->per_vertex_point_size)
1517 emit_point_size_write(c);
1518 }
1519
1520 static void
1521 vc4_optimize_nir(struct nir_shader *s)
1522 {
1523 bool progress;
1524 unsigned lower_flrp =
1525 (s->options->lower_flrp16 ? 16 : 0) |
1526 (s->options->lower_flrp32 ? 32 : 0) |
1527 (s->options->lower_flrp64 ? 64 : 0);
1528
1529 do {
1530 progress = false;
1531
1532 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1533 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL, NULL);
1534 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1535 NIR_PASS(progress, s, nir_copy_prop);
1536 NIR_PASS(progress, s, nir_opt_remove_phis);
1537 NIR_PASS(progress, s, nir_opt_dce);
1538 NIR_PASS(progress, s, nir_opt_dead_cf);
1539 NIR_PASS(progress, s, nir_opt_cse);
1540 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1541 NIR_PASS(progress, s, nir_opt_algebraic);
1542 NIR_PASS(progress, s, nir_opt_constant_folding);
1543 if (lower_flrp != 0) {
1544 bool lower_flrp_progress = false;
1545
1546 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1547 lower_flrp,
1548 false /* always_precise */,
1549 s->options->lower_ffma);
1550 if (lower_flrp_progress) {
1551 NIR_PASS(progress, s, nir_opt_constant_folding);
1552 progress = true;
1553 }
1554
1555 /* Nothing should rematerialize any flrps, so we only
1556 * need to do this lowering once.
1557 */
1558 lower_flrp = 0;
1559 }
1560
1561 NIR_PASS(progress, s, nir_opt_undef);
1562 NIR_PASS(progress, s, nir_opt_loop_unroll,
1563 nir_var_shader_in |
1564 nir_var_shader_out |
1565 nir_var_function_temp);
1566 } while (progress);
1567 }
1568
1569 static int
1570 driver_location_compare(const void *in_a, const void *in_b)
1571 {
1572 const nir_variable *const *a = in_a;
1573 const nir_variable *const *b = in_b;
1574
1575 return (*a)->data.driver_location - (*b)->data.driver_location;
1576 }
1577
1578 static void
1579 ntq_setup_inputs(struct vc4_compile *c)
1580 {
1581 unsigned num_entries = 0;
1582 nir_foreach_variable(var, &c->s->inputs)
1583 num_entries++;
1584
1585 nir_variable *vars[num_entries];
1586
1587 unsigned i = 0;
1588 nir_foreach_variable(var, &c->s->inputs)
1589 vars[i++] = var;
1590
1591 /* Sort the variables so that we emit the input setup in
1592 * driver_location order. This is required for VPM reads, whose data
1593 * is fetched into the VPM in driver_location (TGSI register index)
1594 * order.
1595 */
1596 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1597
1598 for (unsigned i = 0; i < num_entries; i++) {
1599 nir_variable *var = vars[i];
1600 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1601 unsigned loc = var->data.driver_location;
1602
1603 assert(array_len == 1);
1604 (void)array_len;
1605 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1606 (loc + 1) * 4);
1607
1608 if (c->stage == QSTAGE_FRAG) {
1609 if (var->data.location == VARYING_SLOT_POS) {
1610 emit_fragcoord_input(c, loc);
1611 } else if (var->data.location == VARYING_SLOT_PNTC ||
1612 (var->data.location >= VARYING_SLOT_VAR0 &&
1613 (c->fs_key->point_sprite_mask &
1614 (1 << (var->data.location -
1615 VARYING_SLOT_VAR0))))) {
1616 c->inputs[loc * 4 + 0] = c->point_x;
1617 c->inputs[loc * 4 + 1] = c->point_y;
1618 } else {
1619 emit_fragment_input(c, loc, var->data.location);
1620 }
1621 } else {
1622 emit_vertex_input(c, loc);
1623 }
1624 }
1625 }
1626
1627 static void
1628 ntq_setup_outputs(struct vc4_compile *c)
1629 {
1630 nir_foreach_variable(var, &c->s->outputs) {
1631 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1632 unsigned loc = var->data.driver_location * 4;
1633
1634 assert(array_len == 1);
1635 (void)array_len;
1636
1637 for (int i = 0; i < 4; i++)
1638 add_output(c, loc + i, var->data.location, i);
1639
1640 if (c->stage == QSTAGE_FRAG) {
1641 switch (var->data.location) {
1642 case FRAG_RESULT_COLOR:
1643 case FRAG_RESULT_DATA0:
1644 c->output_color_index = loc;
1645 break;
1646 case FRAG_RESULT_DEPTH:
1647 c->output_position_index = loc;
1648 break;
1649 case FRAG_RESULT_SAMPLE_MASK:
1650 c->output_sample_mask_index = loc;
1651 break;
1652 }
1653 } else {
1654 switch (var->data.location) {
1655 case VARYING_SLOT_POS:
1656 c->output_position_index = loc;
1657 break;
1658 case VARYING_SLOT_PSIZ:
1659 c->output_point_size_index = loc;
1660 break;
1661 }
1662 }
1663 }
1664 }
1665
1666 /**
1667 * Sets up the mapping from nir_register to struct qreg *.
1668 *
1669 * Each nir_register gets a struct qreg per 32-bit component being stored.
1670 */
1671 static void
1672 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1673 {
1674 foreach_list_typed(nir_register, nir_reg, node, list) {
1675 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1676 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1677 array_len *
1678 nir_reg->num_components);
1679
1680 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1681
1682 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1683 qregs[i] = qir_get_temp(c);
1684 }
1685 }
1686
1687 static void
1688 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1689 {
1690 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1691 for (int i = 0; i < instr->def.num_components; i++)
1692 qregs[i] = qir_uniform_ui(c, instr->value[i].u32);
1693
1694 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1695 }
1696
1697 static void
1698 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1699 {
1700 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1701
1702 /* QIR needs there to be *some* value, so pick 0 (same as for
1703 * ntq_setup_registers().
1704 */
1705 for (int i = 0; i < instr->def.num_components; i++)
1706 qregs[i] = qir_uniform_ui(c, 0);
1707 }
1708
1709 static void
1710 ntq_emit_color_read(struct vc4_compile *c, nir_intrinsic_instr *instr)
1711 {
1712 assert(nir_src_as_uint(instr->src[0]) == 0);
1713
1714 /* Reads of the per-sample color need to be done in
1715 * order.
1716 */
1717 int sample_index = (nir_intrinsic_base(instr) -
1718 VC4_NIR_TLB_COLOR_READ_INPUT);
1719 for (int i = 0; i <= sample_index; i++) {
1720 if (c->color_reads[i].file == QFILE_NULL) {
1721 c->color_reads[i] =
1722 qir_TLB_COLOR_READ(c);
1723 }
1724 }
1725 ntq_store_dest(c, &instr->dest, 0,
1726 qir_MOV(c, c->color_reads[sample_index]));
1727 }
1728
1729 static void
1730 ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
1731 {
1732 assert(instr->num_components == 1);
1733 assert(nir_src_is_const(instr->src[0]) &&
1734 "vc4 doesn't support indirect inputs");
1735
1736 if (c->stage == QSTAGE_FRAG &&
1737 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1738 ntq_emit_color_read(c, instr);
1739 return;
1740 }
1741
1742 uint32_t offset = nir_intrinsic_base(instr) +
1743 nir_src_as_uint(instr->src[0]);
1744 int comp = nir_intrinsic_component(instr);
1745 ntq_store_dest(c, &instr->dest, 0,
1746 qir_MOV(c, c->inputs[offset * 4 + comp]));
1747 }
1748
1749 static void
1750 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1751 {
1752 unsigned offset;
1753
1754 switch (instr->intrinsic) {
1755 case nir_intrinsic_load_uniform:
1756 assert(instr->num_components == 1);
1757 if (nir_src_is_const(instr->src[0])) {
1758 offset = nir_intrinsic_base(instr) +
1759 nir_src_as_uint(instr->src[0]);
1760 assert(offset % 4 == 0);
1761 /* We need dwords */
1762 offset = offset / 4;
1763 ntq_store_dest(c, &instr->dest, 0,
1764 qir_uniform(c, QUNIFORM_UNIFORM,
1765 offset));
1766 } else {
1767 ntq_store_dest(c, &instr->dest, 0,
1768 indirect_uniform_load(c, instr));
1769 }
1770 break;
1771
1772 case nir_intrinsic_load_ubo:
1773 assert(instr->num_components == 1);
1774 ntq_store_dest(c, &instr->dest, 0, vc4_ubo_load(c, instr));
1775 break;
1776
1777 case nir_intrinsic_load_user_clip_plane:
1778 for (int i = 0; i < instr->num_components; i++) {
1779 ntq_store_dest(c, &instr->dest, i,
1780 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1781 nir_intrinsic_ucp_id(instr) *
1782 4 + i));
1783 }
1784 break;
1785
1786 case nir_intrinsic_load_blend_const_color_r_float:
1787 case nir_intrinsic_load_blend_const_color_g_float:
1788 case nir_intrinsic_load_blend_const_color_b_float:
1789 case nir_intrinsic_load_blend_const_color_a_float:
1790 ntq_store_dest(c, &instr->dest, 0,
1791 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1792 (instr->intrinsic -
1793 nir_intrinsic_load_blend_const_color_r_float),
1794 0));
1795 break;
1796
1797 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1798 ntq_store_dest(c, &instr->dest, 0,
1799 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1800 0));
1801 break;
1802
1803 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1804 ntq_store_dest(c, &instr->dest, 0,
1805 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1806 0));
1807 break;
1808
1809 case nir_intrinsic_load_sample_mask_in:
1810 ntq_store_dest(c, &instr->dest, 0,
1811 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1812 break;
1813
1814 case nir_intrinsic_load_front_face:
1815 /* The register contains 0 (front) or 1 (back), and we need to
1816 * turn it into a NIR bool where true means front.
1817 */
1818 ntq_store_dest(c, &instr->dest, 0,
1819 qir_ADD(c,
1820 qir_uniform_ui(c, -1),
1821 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1822 break;
1823
1824 case nir_intrinsic_load_input:
1825 ntq_emit_load_input(c, instr);
1826 break;
1827
1828 case nir_intrinsic_store_output:
1829 assert(nir_src_is_const(instr->src[1]) &&
1830 "vc4 doesn't support indirect outputs");
1831 offset = nir_intrinsic_base(instr) +
1832 nir_src_as_uint(instr->src[1]);
1833
1834 /* MSAA color outputs are the only case where we have an
1835 * output that's not lowered to being a store of a single 32
1836 * bit value.
1837 */
1838 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1839 assert(offset == c->output_color_index);
1840 for (int i = 0; i < 4; i++) {
1841 c->sample_colors[i] =
1842 qir_MOV(c, ntq_get_src(c, instr->src[0],
1843 i));
1844 }
1845 } else {
1846 offset = offset * 4 + nir_intrinsic_component(instr);
1847 assert(instr->num_components == 1);
1848 c->outputs[offset] =
1849 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1850 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1851 }
1852 break;
1853
1854 case nir_intrinsic_discard:
1855 if (c->execute.file != QFILE_NULL) {
1856 qir_SF(c, c->execute);
1857 qir_MOV_cond(c, QPU_COND_ZS, c->discard,
1858 qir_uniform_ui(c, ~0));
1859 } else {
1860 qir_MOV_dest(c, c->discard, qir_uniform_ui(c, ~0));
1861 }
1862 break;
1863
1864 case nir_intrinsic_discard_if: {
1865 /* true (~0) if we're discarding */
1866 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1867
1868 if (c->execute.file != QFILE_NULL) {
1869 /* execute == 0 means the channel is active. Invert
1870 * the condition so that we can use zero as "executing
1871 * and discarding."
1872 */
1873 qir_SF(c, qir_AND(c, c->execute, qir_NOT(c, cond)));
1874 qir_MOV_cond(c, QPU_COND_ZS, c->discard, cond);
1875 } else {
1876 qir_OR_dest(c, c->discard, c->discard,
1877 ntq_get_src(c, instr->src[0], 0));
1878 }
1879
1880 break;
1881 }
1882
1883 default:
1884 fprintf(stderr, "Unknown intrinsic: ");
1885 nir_print_instr(&instr->instr, stderr);
1886 fprintf(stderr, "\n");
1887 break;
1888 }
1889 }
1890
1891 /* Clears (activates) the execute flags for any channels whose jump target
1892 * matches this block.
1893 */
1894 static void
1895 ntq_activate_execute_for_block(struct vc4_compile *c)
1896 {
1897 qir_SF(c, qir_SUB(c,
1898 c->execute,
1899 qir_uniform_ui(c, c->cur_block->index)));
1900 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1901 }
1902
1903 static void
1904 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1905 {
1906 if (!c->vc4->screen->has_control_flow) {
1907 fprintf(stderr,
1908 "IF statement support requires updated kernel.\n");
1909 return;
1910 }
1911
1912 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1913 bool empty_else_block =
1914 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1915 exec_list_is_empty(&nir_else_block->instr_list));
1916
1917 struct qblock *then_block = qir_new_block(c);
1918 struct qblock *after_block = qir_new_block(c);
1919 struct qblock *else_block;
1920 if (empty_else_block)
1921 else_block = after_block;
1922 else
1923 else_block = qir_new_block(c);
1924
1925 bool was_top_level = false;
1926 if (c->execute.file == QFILE_NULL) {
1927 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1928 was_top_level = true;
1929 }
1930
1931 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1932 * 0) channels, and then update execute flags for those to point to
1933 * the ELSE block.
1934 */
1935 qir_SF(c, qir_OR(c,
1936 c->execute,
1937 ntq_get_src(c, if_stmt->condition, 0)));
1938 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1939 qir_uniform_ui(c, else_block->index));
1940
1941 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1942 * through.
1943 */
1944 qir_SF(c, c->execute);
1945 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
1946 qir_link_blocks(c->cur_block, else_block);
1947 qir_link_blocks(c->cur_block, then_block);
1948
1949 /* Process the THEN block. */
1950 qir_set_emit_block(c, then_block);
1951 ntq_emit_cf_list(c, &if_stmt->then_list);
1952
1953 if (!empty_else_block) {
1954 /* Handle the end of the THEN block. First, all currently
1955 * active channels update their execute flags to point to
1956 * ENDIF
1957 */
1958 qir_SF(c, c->execute);
1959 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1960 qir_uniform_ui(c, after_block->index));
1961
1962 /* If everything points at ENDIF, then jump there immediately. */
1963 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
1964 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
1965 qir_link_blocks(c->cur_block, after_block);
1966 qir_link_blocks(c->cur_block, else_block);
1967
1968 qir_set_emit_block(c, else_block);
1969 ntq_activate_execute_for_block(c);
1970 ntq_emit_cf_list(c, &if_stmt->else_list);
1971 }
1972
1973 qir_link_blocks(c->cur_block, after_block);
1974
1975 qir_set_emit_block(c, after_block);
1976 if (was_top_level) {
1977 c->execute = c->undef;
1978 c->last_top_block = c->cur_block;
1979 } else {
1980 ntq_activate_execute_for_block(c);
1981 }
1982 }
1983
1984 static void
1985 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
1986 {
1987 struct qblock *jump_block;
1988 switch (jump->type) {
1989 case nir_jump_break:
1990 jump_block = c->loop_break_block;
1991 break;
1992 case nir_jump_continue:
1993 jump_block = c->loop_cont_block;
1994 break;
1995 default:
1996 unreachable("Unsupported jump type\n");
1997 }
1998
1999 qir_SF(c, c->execute);
2000 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
2001 qir_uniform_ui(c, jump_block->index));
2002
2003 /* Jump to the destination block if everyone has taken the jump. */
2004 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, jump_block->index)));
2005 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
2006 struct qblock *new_block = qir_new_block(c);
2007 qir_link_blocks(c->cur_block, jump_block);
2008 qir_link_blocks(c->cur_block, new_block);
2009 qir_set_emit_block(c, new_block);
2010 }
2011
2012 static void
2013 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
2014 {
2015 switch (instr->type) {
2016 case nir_instr_type_alu:
2017 ntq_emit_alu(c, nir_instr_as_alu(instr));
2018 break;
2019
2020 case nir_instr_type_intrinsic:
2021 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2022 break;
2023
2024 case nir_instr_type_load_const:
2025 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2026 break;
2027
2028 case nir_instr_type_ssa_undef:
2029 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2030 break;
2031
2032 case nir_instr_type_tex:
2033 ntq_emit_tex(c, nir_instr_as_tex(instr));
2034 break;
2035
2036 case nir_instr_type_jump:
2037 ntq_emit_jump(c, nir_instr_as_jump(instr));
2038 break;
2039
2040 default:
2041 fprintf(stderr, "Unknown NIR instr type: ");
2042 nir_print_instr(instr, stderr);
2043 fprintf(stderr, "\n");
2044 abort();
2045 }
2046 }
2047
2048 static void
2049 ntq_emit_block(struct vc4_compile *c, nir_block *block)
2050 {
2051 nir_foreach_instr(instr, block) {
2052 ntq_emit_instr(c, instr);
2053 }
2054 }
2055
2056 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
2057
2058 static void
2059 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
2060 {
2061 if (!c->vc4->screen->has_control_flow) {
2062 fprintf(stderr,
2063 "loop support requires updated kernel.\n");
2064 ntq_emit_cf_list(c, &loop->body);
2065 return;
2066 }
2067
2068 bool was_top_level = false;
2069 if (c->execute.file == QFILE_NULL) {
2070 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
2071 was_top_level = true;
2072 }
2073
2074 struct qblock *save_loop_cont_block = c->loop_cont_block;
2075 struct qblock *save_loop_break_block = c->loop_break_block;
2076
2077 c->loop_cont_block = qir_new_block(c);
2078 c->loop_break_block = qir_new_block(c);
2079
2080 qir_link_blocks(c->cur_block, c->loop_cont_block);
2081 qir_set_emit_block(c, c->loop_cont_block);
2082 ntq_activate_execute_for_block(c);
2083
2084 ntq_emit_cf_list(c, &loop->body);
2085
2086 /* If anything had explicitly continued, or is here at the end of the
2087 * loop, then we need to loop again. SF updates are masked by the
2088 * instruction's condition, so we can do the OR of the two conditions
2089 * within SF.
2090 */
2091 qir_SF(c, c->execute);
2092 struct qinst *cont_check =
2093 qir_SUB_dest(c,
2094 c->undef,
2095 c->execute,
2096 qir_uniform_ui(c, c->loop_cont_block->index));
2097 cont_check->cond = QPU_COND_ZC;
2098 cont_check->sf = true;
2099
2100 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
2101 qir_link_blocks(c->cur_block, c->loop_cont_block);
2102 qir_link_blocks(c->cur_block, c->loop_break_block);
2103
2104 qir_set_emit_block(c, c->loop_break_block);
2105 if (was_top_level) {
2106 c->execute = c->undef;
2107 c->last_top_block = c->cur_block;
2108 } else {
2109 ntq_activate_execute_for_block(c);
2110 }
2111
2112 c->loop_break_block = save_loop_break_block;
2113 c->loop_cont_block = save_loop_cont_block;
2114 }
2115
2116 static void
2117 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
2118 {
2119 fprintf(stderr, "FUNCTIONS not handled.\n");
2120 abort();
2121 }
2122
2123 static void
2124 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
2125 {
2126 foreach_list_typed(nir_cf_node, node, node, list) {
2127 switch (node->type) {
2128 case nir_cf_node_block:
2129 ntq_emit_block(c, nir_cf_node_as_block(node));
2130 break;
2131
2132 case nir_cf_node_if:
2133 ntq_emit_if(c, nir_cf_node_as_if(node));
2134 break;
2135
2136 case nir_cf_node_loop:
2137 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2138 break;
2139
2140 case nir_cf_node_function:
2141 ntq_emit_function(c, nir_cf_node_as_function(node));
2142 break;
2143
2144 default:
2145 fprintf(stderr, "Unknown NIR node type\n");
2146 abort();
2147 }
2148 }
2149 }
2150
2151 static void
2152 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
2153 {
2154 ntq_setup_registers(c, &impl->registers);
2155 ntq_emit_cf_list(c, &impl->body);
2156 }
2157
2158 static void
2159 nir_to_qir(struct vc4_compile *c)
2160 {
2161 if (c->stage == QSTAGE_FRAG && c->s->info.fs.uses_discard)
2162 c->discard = qir_MOV(c, qir_uniform_ui(c, 0));
2163
2164 ntq_setup_inputs(c);
2165 ntq_setup_outputs(c);
2166
2167 /* Find the main function and emit the body. */
2168 nir_foreach_function(function, c->s) {
2169 assert(strcmp(function->name, "main") == 0);
2170 assert(function->impl);
2171 ntq_emit_impl(c, function->impl);
2172 }
2173 }
2174
2175 static const nir_shader_compiler_options nir_options = {
2176 .lower_all_io_to_temps = true,
2177 .lower_extract_byte = true,
2178 .lower_extract_word = true,
2179 .lower_fdiv = true,
2180 .lower_ffma = true,
2181 .lower_flrp32 = true,
2182 .lower_fmod = true,
2183 .lower_fpow = true,
2184 .lower_fsat = true,
2185 .lower_fsqrt = true,
2186 .lower_ldexp = true,
2187 .lower_negate = true,
2188 .lower_rotate = true,
2189 .lower_to_scalar = true,
2190 .max_unroll_iterations = 32,
2191 };
2192
2193 const void *
2194 vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
2195 enum pipe_shader_ir ir,
2196 enum pipe_shader_type shader)
2197 {
2198 return &nir_options;
2199 }
2200
2201 static int
2202 count_nir_instrs(nir_shader *nir)
2203 {
2204 int count = 0;
2205 nir_foreach_function(function, nir) {
2206 if (!function->impl)
2207 continue;
2208 nir_foreach_block(block, function->impl) {
2209 nir_foreach_instr(instr, block)
2210 count++;
2211 }
2212 }
2213 return count;
2214 }
2215
2216 static struct vc4_compile *
2217 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
2218 struct vc4_key *key, bool fs_threaded)
2219 {
2220 struct vc4_compile *c = qir_compile_init();
2221
2222 c->vc4 = vc4;
2223 c->stage = stage;
2224 c->shader_state = &key->shader_state->base;
2225 c->program_id = key->shader_state->program_id;
2226 c->variant_id =
2227 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2228 c->fs_threaded = fs_threaded;
2229
2230 c->key = key;
2231 switch (stage) {
2232 case QSTAGE_FRAG:
2233 c->fs_key = (struct vc4_fs_key *)key;
2234 if (c->fs_key->is_points) {
2235 c->point_x = emit_fragment_varying(c, ~0, 0);
2236 c->point_y = emit_fragment_varying(c, ~0, 0);
2237 } else if (c->fs_key->is_lines) {
2238 c->line_x = emit_fragment_varying(c, ~0, 0);
2239 }
2240 break;
2241 case QSTAGE_VERT:
2242 c->vs_key = (struct vc4_vs_key *)key;
2243 break;
2244 case QSTAGE_COORD:
2245 c->vs_key = (struct vc4_vs_key *)key;
2246 break;
2247 }
2248
2249 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2250
2251 if (stage == QSTAGE_FRAG)
2252 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2253
2254 struct nir_lower_tex_options tex_options = {
2255 /* We would need to implement txs, but we don't want the
2256 * int/float conversions
2257 */
2258 .lower_rect = false,
2259
2260 .lower_txp = ~0,
2261
2262 /* Apply swizzles to all samplers. */
2263 .swizzle_result = ~0,
2264 };
2265
2266 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2267 * The format swizzling applies before sRGB decode, and
2268 * ARB_texture_swizzle is the last thing before returning the sample.
2269 */
2270 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2271 enum pipe_format format = c->key->tex[i].format;
2272
2273 if (!format)
2274 continue;
2275
2276 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2277
2278 for (int j = 0; j < 4; j++) {
2279 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2280
2281 if (arb_swiz <= 3) {
2282 tex_options.swizzles[i][j] =
2283 format_swizzle[arb_swiz];
2284 } else {
2285 tex_options.swizzles[i][j] = arb_swiz;
2286 }
2287 }
2288
2289 if (util_format_is_srgb(format))
2290 tex_options.lower_srgb |= (1 << i);
2291 }
2292
2293 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2294
2295 if (c->fs_key && c->fs_key->light_twoside)
2296 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2297
2298 if (c->vs_key && c->vs_key->clamp_color)
2299 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2300
2301 if (c->key->ucp_enables) {
2302 if (stage == QSTAGE_FRAG) {
2303 NIR_PASS_V(c->s, nir_lower_clip_fs,
2304 c->key->ucp_enables, false);
2305 } else {
2306 NIR_PASS_V(c->s, nir_lower_clip_vs,
2307 c->key->ucp_enables, false, false, NULL);
2308 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2309 nir_var_shader_out);
2310 }
2311 }
2312
2313 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2314 * which only handles a vec4 at a time. Similarly, VS output
2315 * scalarizing must happen after nir_lower_clip_vs.
2316 */
2317 if (c->stage == QSTAGE_FRAG)
2318 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2319 else
2320 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2321
2322 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2323 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2324 NIR_PASS_V(c->s, nir_lower_idiv);
2325
2326 vc4_optimize_nir(c->s);
2327
2328 /* Do late algebraic optimization to turn add(a, neg(b)) back into
2329 * subs, then the mandatory cleanup after algebraic. Note that it may
2330 * produce fnegs, and if so then we need to keep running to squash
2331 * fneg(fneg(a)).
2332 */
2333 bool more_late_algebraic = true;
2334 while (more_late_algebraic) {
2335 more_late_algebraic = false;
2336 NIR_PASS(more_late_algebraic, c->s, nir_opt_algebraic_late);
2337 NIR_PASS_V(c->s, nir_opt_constant_folding);
2338 NIR_PASS_V(c->s, nir_copy_prop);
2339 NIR_PASS_V(c->s, nir_opt_dce);
2340 NIR_PASS_V(c->s, nir_opt_cse);
2341 }
2342
2343 NIR_PASS_V(c->s, nir_lower_bool_to_int32);
2344
2345 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2346
2347 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2348 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2349 qir_get_stage_name(c->stage),
2350 c->program_id, c->variant_id,
2351 count_nir_instrs(c->s));
2352 }
2353
2354 if (vc4_debug & VC4_DEBUG_NIR) {
2355 fprintf(stderr, "%s prog %d/%d NIR:\n",
2356 qir_get_stage_name(c->stage),
2357 c->program_id, c->variant_id);
2358 nir_print_shader(c->s, stderr);
2359 }
2360
2361 nir_to_qir(c);
2362
2363 switch (stage) {
2364 case QSTAGE_FRAG:
2365 /* FS threading requires that the thread execute
2366 * QPU_SIG_LAST_THREAD_SWITCH exactly once before terminating
2367 * (with no other THRSW afterwards, obviously). If we didn't
2368 * fetch a texture at a top level block, this wouldn't be
2369 * true.
2370 */
2371 if (c->fs_threaded && !c->last_thrsw_at_top_level) {
2372 c->failed = true;
2373 return c;
2374 }
2375
2376 emit_frag_end(c);
2377 break;
2378 case QSTAGE_VERT:
2379 emit_vert_end(c,
2380 c->vs_key->fs_inputs->input_slots,
2381 c->vs_key->fs_inputs->num_inputs);
2382 break;
2383 case QSTAGE_COORD:
2384 emit_coord_end(c);
2385 break;
2386 }
2387
2388 if (vc4_debug & VC4_DEBUG_QIR) {
2389 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2390 qir_get_stage_name(c->stage),
2391 c->program_id, c->variant_id);
2392 qir_dump(c);
2393 fprintf(stderr, "\n");
2394 }
2395
2396 qir_optimize(c);
2397 qir_lower_uniforms(c);
2398
2399 qir_schedule_instructions(c);
2400 qir_emit_uniform_stream_resets(c);
2401
2402 if (vc4_debug & VC4_DEBUG_QIR) {
2403 fprintf(stderr, "%s prog %d/%d QIR:\n",
2404 qir_get_stage_name(c->stage),
2405 c->program_id, c->variant_id);
2406 qir_dump(c);
2407 fprintf(stderr, "\n");
2408 }
2409
2410 qir_reorder_uniforms(c);
2411 vc4_generate_code(vc4, c);
2412
2413 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2414 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2415 qir_get_stage_name(c->stage),
2416 c->program_id, c->variant_id,
2417 c->qpu_inst_count);
2418 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2419 qir_get_stage_name(c->stage),
2420 c->program_id, c->variant_id,
2421 c->num_uniforms);
2422 }
2423
2424 ralloc_free(c->s);
2425
2426 return c;
2427 }
2428
2429 static void *
2430 vc4_shader_state_create(struct pipe_context *pctx,
2431 const struct pipe_shader_state *cso)
2432 {
2433 struct vc4_context *vc4 = vc4_context(pctx);
2434 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2435 if (!so)
2436 return NULL;
2437
2438 so->program_id = vc4->next_uncompiled_program_id++;
2439
2440 nir_shader *s;
2441
2442 if (cso->type == PIPE_SHADER_IR_NIR) {
2443 /* The backend takes ownership of the NIR shader on state
2444 * creation.
2445 */
2446 s = cso->ir.nir;
2447 } else {
2448 assert(cso->type == PIPE_SHADER_IR_TGSI);
2449
2450 if (vc4_debug & VC4_DEBUG_TGSI) {
2451 fprintf(stderr, "prog %d TGSI:\n",
2452 so->program_id);
2453 tgsi_dump(cso->tokens, 0);
2454 fprintf(stderr, "\n");
2455 }
2456 s = tgsi_to_nir(cso->tokens, pctx->screen);
2457 }
2458
2459 if (s->info.stage == MESA_SHADER_VERTEX)
2460 NIR_PASS_V(s, nir_lower_point_size, 1.0f, 0.0f);
2461
2462 NIR_PASS_V(s, nir_lower_io, nir_var_all, type_size,
2463 (nir_lower_io_options)0);
2464
2465 NIR_PASS_V(s, nir_lower_regs_to_ssa);
2466 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2467
2468 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2469
2470 vc4_optimize_nir(s);
2471
2472 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp);
2473
2474 /* Garbage collect dead instructions */
2475 nir_sweep(s);
2476
2477 so->base.type = PIPE_SHADER_IR_NIR;
2478 so->base.ir.nir = s;
2479
2480 if (vc4_debug & VC4_DEBUG_NIR) {
2481 fprintf(stderr, "%s prog %d NIR:\n",
2482 gl_shader_stage_name(s->info.stage),
2483 so->program_id);
2484 nir_print_shader(s, stderr);
2485 fprintf(stderr, "\n");
2486 }
2487
2488 return so;
2489 }
2490
2491 static void
2492 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2493 struct vc4_compile *c)
2494 {
2495 int count = c->num_uniforms;
2496 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2497
2498 uinfo->count = count;
2499 uinfo->data = ralloc_array(shader, uint32_t, count);
2500 memcpy(uinfo->data, c->uniform_data,
2501 count * sizeof(*uinfo->data));
2502 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2503 memcpy(uinfo->contents, c->uniform_contents,
2504 count * sizeof(*uinfo->contents));
2505 uinfo->num_texture_samples = c->num_texture_samples;
2506
2507 vc4_set_shader_uniform_dirty_flags(shader);
2508 }
2509
2510 static void
2511 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2512 struct vc4_compiled_shader *shader)
2513 {
2514 struct vc4_fs_inputs inputs;
2515
2516 memset(&inputs, 0, sizeof(inputs));
2517 inputs.input_slots = ralloc_array(shader,
2518 struct vc4_varying_slot,
2519 c->num_input_slots);
2520
2521 bool input_live[c->num_input_slots];
2522
2523 memset(input_live, 0, sizeof(input_live));
2524 qir_for_each_inst_inorder(inst, c) {
2525 for (int i = 0; i < qir_get_nsrc(inst); i++) {
2526 if (inst->src[i].file == QFILE_VARY)
2527 input_live[inst->src[i].index] = true;
2528 }
2529 }
2530
2531 for (int i = 0; i < c->num_input_slots; i++) {
2532 struct vc4_varying_slot *slot = &c->input_slots[i];
2533
2534 if (!input_live[i])
2535 continue;
2536
2537 /* Skip non-VS-output inputs. */
2538 if (slot->slot == (uint8_t)~0)
2539 continue;
2540
2541 if (slot->slot == VARYING_SLOT_COL0 ||
2542 slot->slot == VARYING_SLOT_COL1 ||
2543 slot->slot == VARYING_SLOT_BFC0 ||
2544 slot->slot == VARYING_SLOT_BFC1) {
2545 shader->color_inputs |= (1 << inputs.num_inputs);
2546 }
2547
2548 inputs.input_slots[inputs.num_inputs] = *slot;
2549 inputs.num_inputs++;
2550 }
2551 shader->num_inputs = inputs.num_inputs;
2552
2553 /* Add our set of inputs to the set of all inputs seen. This way, we
2554 * can have a single pointer that identifies an FS inputs set,
2555 * allowing VS to avoid recompiling when the FS is recompiled (or a
2556 * new one is bound using separate shader objects) but the inputs
2557 * don't change.
2558 */
2559 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2560 if (entry) {
2561 shader->fs_inputs = entry->key;
2562 ralloc_free(inputs.input_slots);
2563 } else {
2564 struct vc4_fs_inputs *alloc_inputs;
2565
2566 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2567 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2568 ralloc_steal(alloc_inputs, inputs.input_slots);
2569 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2570
2571 shader->fs_inputs = alloc_inputs;
2572 }
2573 }
2574
2575 static struct vc4_compiled_shader *
2576 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2577 struct vc4_key *key)
2578 {
2579 struct hash_table *ht;
2580 uint32_t key_size;
2581 bool try_threading;
2582
2583 if (stage == QSTAGE_FRAG) {
2584 ht = vc4->fs_cache;
2585 key_size = sizeof(struct vc4_fs_key);
2586 try_threading = vc4->screen->has_threaded_fs;
2587 } else {
2588 ht = vc4->vs_cache;
2589 key_size = sizeof(struct vc4_vs_key);
2590 try_threading = false;
2591 }
2592
2593 struct vc4_compiled_shader *shader;
2594 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2595 if (entry)
2596 return entry->data;
2597
2598 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key, try_threading);
2599 /* If the FS failed to compile threaded, fall back to single threaded. */
2600 if (try_threading && c->failed) {
2601 qir_compile_destroy(c);
2602 c = vc4_shader_ntq(vc4, stage, key, false);
2603 }
2604
2605 shader = rzalloc(NULL, struct vc4_compiled_shader);
2606
2607 shader->program_id = vc4->next_compiled_program_id++;
2608 if (stage == QSTAGE_FRAG) {
2609 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2610
2611 /* Note: the temporary clone in c->s has been freed. */
2612 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2613 if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
2614 shader->disable_early_z = true;
2615 } else {
2616 shader->num_inputs = c->num_inputs;
2617
2618 shader->vattr_offsets[0] = 0;
2619 for (int i = 0; i < 8; i++) {
2620 shader->vattr_offsets[i + 1] =
2621 shader->vattr_offsets[i] + c->vattr_sizes[i];
2622
2623 if (c->vattr_sizes[i])
2624 shader->vattrs_live |= (1 << i);
2625 }
2626 }
2627
2628 shader->failed = c->failed;
2629 if (c->failed) {
2630 shader->failed = true;
2631 } else {
2632 copy_uniform_state_to_shader(shader, c);
2633 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2634 c->qpu_inst_count *
2635 sizeof(uint64_t));
2636 }
2637
2638 shader->fs_threaded = c->fs_threaded;
2639
2640 if ((vc4_debug & VC4_DEBUG_SHADERDB) && stage == QSTAGE_FRAG) {
2641 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d FS threads\n",
2642 qir_get_stage_name(c->stage),
2643 c->program_id, c->variant_id,
2644 1 + shader->fs_threaded);
2645 }
2646
2647 qir_compile_destroy(c);
2648
2649 struct vc4_key *dup_key;
2650 dup_key = rzalloc_size(shader, key_size); /* TODO: don't use rzalloc */
2651 memcpy(dup_key, key, key_size);
2652 _mesa_hash_table_insert(ht, dup_key, shader);
2653
2654 return shader;
2655 }
2656
2657 static void
2658 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2659 struct vc4_texture_stateobj *texstate)
2660 {
2661 for (int i = 0; i < texstate->num_textures; i++) {
2662 struct pipe_sampler_view *sampler = texstate->textures[i];
2663 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2664 struct pipe_sampler_state *sampler_state =
2665 texstate->samplers[i];
2666
2667 if (!sampler)
2668 continue;
2669
2670 key->tex[i].format = sampler->format;
2671 key->tex[i].swizzle[0] = sampler->swizzle_r;
2672 key->tex[i].swizzle[1] = sampler->swizzle_g;
2673 key->tex[i].swizzle[2] = sampler->swizzle_b;
2674 key->tex[i].swizzle[3] = sampler->swizzle_a;
2675
2676 if (sampler->texture->nr_samples > 1) {
2677 key->tex[i].msaa_width = sampler->texture->width0;
2678 key->tex[i].msaa_height = sampler->texture->height0;
2679 } else if (sampler){
2680 key->tex[i].compare_mode = sampler_state->compare_mode;
2681 key->tex[i].compare_func = sampler_state->compare_func;
2682 key->tex[i].wrap_s = sampler_state->wrap_s;
2683 key->tex[i].wrap_t = sampler_state->wrap_t;
2684 key->tex[i].force_first_level =
2685 vc4_sampler->force_first_level;
2686 }
2687 }
2688
2689 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2690 }
2691
2692 static void
2693 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2694 {
2695 struct vc4_job *job = vc4->job;
2696 struct vc4_fs_key local_key;
2697 struct vc4_fs_key *key = &local_key;
2698
2699 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2700 VC4_DIRTY_BLEND |
2701 VC4_DIRTY_FRAMEBUFFER |
2702 VC4_DIRTY_ZSA |
2703 VC4_DIRTY_RASTERIZER |
2704 VC4_DIRTY_SAMPLE_MASK |
2705 VC4_DIRTY_FRAGTEX |
2706 VC4_DIRTY_UNCOMPILED_FS |
2707 VC4_DIRTY_UBO_1_SIZE))) {
2708 return;
2709 }
2710
2711 memset(key, 0, sizeof(*key));
2712 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2713 key->base.shader_state = vc4->prog.bind_fs;
2714 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2715 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2716 prim_mode <= PIPE_PRIM_LINE_STRIP);
2717 key->blend = vc4->blend->rt[0];
2718 if (vc4->blend->logicop_enable) {
2719 key->logicop_func = vc4->blend->logicop_func;
2720 } else {
2721 key->logicop_func = PIPE_LOGICOP_COPY;
2722 }
2723 if (job->msaa) {
2724 key->msaa = vc4->rasterizer->base.multisample;
2725 key->sample_coverage = (vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2726 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2727 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2728 }
2729
2730 if (vc4->framebuffer.cbufs[0])
2731 key->color_format = vc4->framebuffer.cbufs[0]->format;
2732
2733 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2734 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2735 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2736 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2737 key->stencil_enabled);
2738 if (vc4->zsa->base.alpha.enabled)
2739 key->alpha_test_func = vc4->zsa->base.alpha.func;
2740 else
2741 key->alpha_test_func = COMPARE_FUNC_ALWAYS;
2742
2743 if (key->is_points) {
2744 key->point_sprite_mask =
2745 vc4->rasterizer->base.sprite_coord_enable;
2746 key->point_coord_upper_left =
2747 (vc4->rasterizer->base.sprite_coord_mode ==
2748 PIPE_SPRITE_COORD_UPPER_LEFT);
2749 }
2750
2751 key->ubo_1_size = vc4->constbuf[PIPE_SHADER_FRAGMENT].cb[1].buffer_size;
2752 key->light_twoside = vc4->rasterizer->base.light_twoside;
2753
2754 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2755 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2756 if (vc4->prog.fs == old_fs)
2757 return;
2758
2759 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2760
2761 if (vc4->rasterizer->base.flatshade &&
2762 (!old_fs || vc4->prog.fs->color_inputs != old_fs->color_inputs)) {
2763 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2764 }
2765
2766 if (!old_fs || vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2767 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2768 }
2769
2770 static void
2771 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2772 {
2773 struct vc4_vs_key local_key;
2774 struct vc4_vs_key *key = &local_key;
2775
2776 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2777 VC4_DIRTY_RASTERIZER |
2778 VC4_DIRTY_VERTTEX |
2779 VC4_DIRTY_VTXSTATE |
2780 VC4_DIRTY_UNCOMPILED_VS |
2781 VC4_DIRTY_FS_INPUTS))) {
2782 return;
2783 }
2784
2785 memset(key, 0, sizeof(*key));
2786 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2787 key->base.shader_state = vc4->prog.bind_vs;
2788 key->fs_inputs = vc4->prog.fs->fs_inputs;
2789 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2790
2791 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2792 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2793
2794 key->per_vertex_point_size =
2795 (prim_mode == PIPE_PRIM_POINTS &&
2796 vc4->rasterizer->base.point_size_per_vertex);
2797
2798 struct vc4_compiled_shader *vs =
2799 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2800 if (vs != vc4->prog.vs) {
2801 vc4->prog.vs = vs;
2802 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2803 }
2804
2805 key->is_coord = true;
2806 /* Coord shaders don't care what the FS inputs are. */
2807 key->fs_inputs = NULL;
2808 struct vc4_compiled_shader *cs =
2809 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2810 if (cs != vc4->prog.cs) {
2811 vc4->prog.cs = cs;
2812 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2813 }
2814 }
2815
2816 bool
2817 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2818 {
2819 vc4_update_compiled_fs(vc4, prim_mode);
2820 vc4_update_compiled_vs(vc4, prim_mode);
2821
2822 return !(vc4->prog.cs->failed ||
2823 vc4->prog.vs->failed ||
2824 vc4->prog.fs->failed);
2825 }
2826
2827 static uint32_t
2828 fs_cache_hash(const void *key)
2829 {
2830 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2831 }
2832
2833 static uint32_t
2834 vs_cache_hash(const void *key)
2835 {
2836 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2837 }
2838
2839 static bool
2840 fs_cache_compare(const void *key1, const void *key2)
2841 {
2842 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2843 }
2844
2845 static bool
2846 vs_cache_compare(const void *key1, const void *key2)
2847 {
2848 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2849 }
2850
2851 static uint32_t
2852 fs_inputs_hash(const void *key)
2853 {
2854 const struct vc4_fs_inputs *inputs = key;
2855
2856 return _mesa_hash_data(inputs->input_slots,
2857 sizeof(*inputs->input_slots) *
2858 inputs->num_inputs);
2859 }
2860
2861 static bool
2862 fs_inputs_compare(const void *key1, const void *key2)
2863 {
2864 const struct vc4_fs_inputs *inputs1 = key1;
2865 const struct vc4_fs_inputs *inputs2 = key2;
2866
2867 return (inputs1->num_inputs == inputs2->num_inputs &&
2868 memcmp(inputs1->input_slots,
2869 inputs2->input_slots,
2870 sizeof(*inputs1->input_slots) *
2871 inputs1->num_inputs) == 0);
2872 }
2873
2874 static void
2875 delete_from_cache_if_matches(struct hash_table *ht,
2876 struct vc4_compiled_shader **last_compile,
2877 struct hash_entry *entry,
2878 struct vc4_uncompiled_shader *so)
2879 {
2880 const struct vc4_key *key = entry->key;
2881
2882 if (key->shader_state == so) {
2883 struct vc4_compiled_shader *shader = entry->data;
2884 _mesa_hash_table_remove(ht, entry);
2885 vc4_bo_unreference(&shader->bo);
2886
2887 if (shader == *last_compile)
2888 *last_compile = NULL;
2889
2890 ralloc_free(shader);
2891 }
2892 }
2893
2894 static void
2895 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2896 {
2897 struct vc4_context *vc4 = vc4_context(pctx);
2898 struct vc4_uncompiled_shader *so = hwcso;
2899
2900 hash_table_foreach(vc4->fs_cache, entry) {
2901 delete_from_cache_if_matches(vc4->fs_cache, &vc4->prog.fs,
2902 entry, so);
2903 }
2904 hash_table_foreach(vc4->vs_cache, entry) {
2905 delete_from_cache_if_matches(vc4->vs_cache, &vc4->prog.vs,
2906 entry, so);
2907 }
2908
2909 ralloc_free(so->base.ir.nir);
2910 free(so);
2911 }
2912
2913 static void
2914 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2915 {
2916 struct vc4_context *vc4 = vc4_context(pctx);
2917 vc4->prog.bind_fs = hwcso;
2918 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2919 }
2920
2921 static void
2922 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2923 {
2924 struct vc4_context *vc4 = vc4_context(pctx);
2925 vc4->prog.bind_vs = hwcso;
2926 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2927 }
2928
2929 void
2930 vc4_program_init(struct pipe_context *pctx)
2931 {
2932 struct vc4_context *vc4 = vc4_context(pctx);
2933
2934 pctx->create_vs_state = vc4_shader_state_create;
2935 pctx->delete_vs_state = vc4_shader_state_delete;
2936
2937 pctx->create_fs_state = vc4_shader_state_create;
2938 pctx->delete_fs_state = vc4_shader_state_delete;
2939
2940 pctx->bind_fs_state = vc4_fp_state_bind;
2941 pctx->bind_vs_state = vc4_vp_state_bind;
2942
2943 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2944 fs_cache_compare);
2945 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2946 vs_cache_compare);
2947 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
2948 fs_inputs_compare);
2949 }
2950
2951 void
2952 vc4_program_fini(struct pipe_context *pctx)
2953 {
2954 struct vc4_context *vc4 = vc4_context(pctx);
2955
2956 hash_table_foreach(vc4->fs_cache, entry) {
2957 struct vc4_compiled_shader *shader = entry->data;
2958 vc4_bo_unreference(&shader->bo);
2959 ralloc_free(shader);
2960 _mesa_hash_table_remove(vc4->fs_cache, entry);
2961 }
2962
2963 hash_table_foreach(vc4->vs_cache, entry) {
2964 struct vc4_compiled_shader *shader = entry->data;
2965 vc4_bo_unreference(&shader->bo);
2966 ralloc_free(shader);
2967 _mesa_hash_table_remove(vc4->vs_cache, entry);
2968 }
2969 }