2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "util/u_format.h"
27 #include "util/u_hash.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "nir/tgsi_to_nir.h"
37 #include "vc4_context.h"
40 #include "mesa/state_tracker/st_glsl_types.h"
43 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
);
45 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
48 resize_qreg_array(struct vc4_compile
*c
,
53 if (*size
>= decl_size
)
56 uint32_t old_size
= *size
;
57 *size
= MAX2(*size
* 2, decl_size
);
58 *regs
= reralloc(c
, *regs
, struct qreg
, *size
);
60 fprintf(stderr
, "Malloc failure\n");
64 for (uint32_t i
= old_size
; i
< *size
; i
++)
65 (*regs
)[i
] = c
->undef
;
69 indirect_uniform_load(struct vc4_compile
*c
, nir_intrinsic_instr
*intr
)
71 struct qreg indirect_offset
= ntq_get_src(c
, intr
->src
[0], 0);
72 uint32_t offset
= nir_intrinsic_base(intr
);
73 struct vc4_compiler_ubo_range
*range
= NULL
;
75 for (i
= 0; i
< c
->num_uniform_ranges
; i
++) {
76 range
= &c
->ubo_ranges
[i
];
77 if (offset
>= range
->src_offset
&&
78 offset
< range
->src_offset
+ range
->size
) {
82 /* The driver-location-based offset always has to be within a declared
88 range
->dst_offset
= c
->next_ubo_dst_offset
;
89 c
->next_ubo_dst_offset
+= range
->size
;
93 offset
-= range
->src_offset
;
95 /* Adjust for where we stored the TGSI register base. */
96 indirect_offset
= qir_ADD(c
, indirect_offset
,
97 qir_uniform_ui(c
, (range
->dst_offset
+
100 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
101 indirect_offset
= qir_MAX(c
, indirect_offset
, qir_uniform_ui(c
, 0));
102 indirect_offset
= qir_MIN(c
, indirect_offset
,
103 qir_uniform_ui(c
, (range
->dst_offset
+
106 qir_TEX_DIRECT(c
, indirect_offset
, qir_uniform(c
, QUNIFORM_UBO_ADDR
, 0));
107 c
->num_texture_samples
++;
108 return qir_TEX_RESULT(c
);
112 vc4_nir_get_swizzled_channel(nir_builder
*b
, nir_ssa_def
**srcs
, int swiz
)
116 case PIPE_SWIZZLE_NONE
:
117 fprintf(stderr
, "warning: unknown swizzle\n");
120 return nir_imm_float(b
, 0.0);
122 return nir_imm_float(b
, 1.0);
132 ntq_init_ssa_def(struct vc4_compile
*c
, nir_ssa_def
*def
)
134 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
135 def
->num_components
);
136 _mesa_hash_table_insert(c
->def_ht
, def
, qregs
);
141 * This function is responsible for getting QIR results into the associated
142 * storage for a NIR instruction.
144 * If it's a NIR SSA def, then we just set the associated hash table entry to
147 * If it's a NIR reg, then we need to update the existing qreg assigned to the
148 * NIR destination with the incoming value. To do that without introducing
149 * new MOVs, we require that the incoming qreg either be a uniform, or be
150 * SSA-defined by the previous QIR instruction in the block and rewritable by
151 * this function. That lets us sneak ahead and insert the SF flag beforehand
152 * (knowing that the previous instruction doesn't depend on flags) and rewrite
153 * its destination to be the NIR reg's destination
156 ntq_store_dest(struct vc4_compile
*c
, nir_dest
*dest
, int chan
,
159 struct qinst
*last_inst
= NULL
;
160 if (!list_empty(&c
->cur_block
->instructions
))
161 last_inst
= (struct qinst
*)c
->cur_block
->instructions
.prev
;
163 assert(result
.file
== QFILE_UNIF
||
164 (result
.file
== QFILE_TEMP
&&
165 last_inst
&& last_inst
== c
->defs
[result
.index
]));
168 assert(chan
< dest
->ssa
.num_components
);
171 struct hash_entry
*entry
=
172 _mesa_hash_table_search(c
->def_ht
, &dest
->ssa
);
177 qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
179 qregs
[chan
] = result
;
181 nir_register
*reg
= dest
->reg
.reg
;
182 assert(dest
->reg
.base_offset
== 0);
183 assert(reg
->num_array_elems
== 0);
184 struct hash_entry
*entry
=
185 _mesa_hash_table_search(c
->def_ht
, reg
);
186 struct qreg
*qregs
= entry
->data
;
188 /* Insert a MOV if the source wasn't an SSA def in the
189 * previous instruction.
191 if (result
.file
== QFILE_UNIF
) {
192 result
= qir_MOV(c
, result
);
193 last_inst
= c
->defs
[result
.index
];
196 /* We know they're both temps, so just rewrite index. */
197 c
->defs
[last_inst
->dst
.index
] = NULL
;
198 last_inst
->dst
.index
= qregs
[chan
].index
;
200 /* If we're in control flow, then make this update of the reg
201 * conditional on the execution mask.
203 if (c
->execute
.file
!= QFILE_NULL
) {
204 last_inst
->dst
.index
= qregs
[chan
].index
;
206 /* Set the flags to the current exec mask. To insert
207 * the SF, we temporarily remove our SSA instruction.
209 list_del(&last_inst
->link
);
210 qir_SF(c
, c
->execute
);
211 list_addtail(&last_inst
->link
,
212 &c
->cur_block
->instructions
);
214 last_inst
->cond
= QPU_COND_ZS
;
215 last_inst
->cond_is_exec_mask
= true;
221 ntq_get_dest(struct vc4_compile
*c
, nir_dest
*dest
)
224 struct qreg
*qregs
= ntq_init_ssa_def(c
, &dest
->ssa
);
225 for (int i
= 0; i
< dest
->ssa
.num_components
; i
++)
229 nir_register
*reg
= dest
->reg
.reg
;
230 assert(dest
->reg
.base_offset
== 0);
231 assert(reg
->num_array_elems
== 0);
232 struct hash_entry
*entry
=
233 _mesa_hash_table_search(c
->def_ht
, reg
);
239 ntq_get_src(struct vc4_compile
*c
, nir_src src
, int i
)
241 struct hash_entry
*entry
;
243 entry
= _mesa_hash_table_search(c
->def_ht
, src
.ssa
);
244 assert(i
< src
.ssa
->num_components
);
246 nir_register
*reg
= src
.reg
.reg
;
247 entry
= _mesa_hash_table_search(c
->def_ht
, reg
);
248 assert(reg
->num_array_elems
== 0);
249 assert(src
.reg
.base_offset
== 0);
250 assert(i
< reg
->num_components
);
253 struct qreg
*qregs
= entry
->data
;
258 ntq_get_alu_src(struct vc4_compile
*c
, nir_alu_instr
*instr
,
261 assert(util_is_power_of_two(instr
->dest
.write_mask
));
262 unsigned chan
= ffs(instr
->dest
.write_mask
) - 1;
263 struct qreg r
= ntq_get_src(c
, instr
->src
[src
].src
,
264 instr
->src
[src
].swizzle
[chan
]);
266 assert(!instr
->src
[src
].abs
);
267 assert(!instr
->src
[src
].negate
);
272 static inline struct qreg
273 qir_SAT(struct vc4_compile
*c
, struct qreg val
)
276 qir_FMIN(c
, val
, qir_uniform_f(c
, 1.0)),
277 qir_uniform_f(c
, 0.0));
281 ntq_rcp(struct vc4_compile
*c
, struct qreg x
)
283 struct qreg r
= qir_RCP(c
, x
);
285 /* Apply a Newton-Raphson step to improve the accuracy. */
286 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
287 qir_uniform_f(c
, 2.0),
294 ntq_rsq(struct vc4_compile
*c
, struct qreg x
)
296 struct qreg r
= qir_RSQ(c
, x
);
298 /* Apply a Newton-Raphson step to improve the accuracy. */
299 r
= qir_FMUL(c
, r
, qir_FSUB(c
,
300 qir_uniform_f(c
, 1.5),
302 qir_uniform_f(c
, 0.5),
304 qir_FMUL(c
, r
, r
)))));
310 ntq_umul(struct vc4_compile
*c
, struct qreg src0
, struct qreg src1
)
312 struct qreg src0_hi
= qir_SHR(c
, src0
,
313 qir_uniform_ui(c
, 24));
314 struct qreg src1_hi
= qir_SHR(c
, src1
,
315 qir_uniform_ui(c
, 24));
317 struct qreg hilo
= qir_MUL24(c
, src0_hi
, src1
);
318 struct qreg lohi
= qir_MUL24(c
, src0
, src1_hi
);
319 struct qreg lolo
= qir_MUL24(c
, src0
, src1
);
321 return qir_ADD(c
, lolo
, qir_SHL(c
,
322 qir_ADD(c
, hilo
, lohi
),
323 qir_uniform_ui(c
, 24)));
327 ntq_scale_depth_texture(struct vc4_compile
*c
, struct qreg src
)
329 struct qreg depthf
= qir_ITOF(c
, qir_SHR(c
, src
,
330 qir_uniform_ui(c
, 8)));
331 return qir_FMUL(c
, depthf
, qir_uniform_f(c
, 1.0f
/0xffffff));
335 * Emits a lowered TXF_MS from an MSAA texture.
337 * The addressing math has been lowered in NIR, and now we just need to read
341 ntq_emit_txf(struct vc4_compile
*c
, nir_tex_instr
*instr
)
343 uint32_t tile_width
= 32;
344 uint32_t tile_height
= 32;
345 uint32_t tile_size
= (tile_height
* tile_width
*
346 VC4_MAX_SAMPLES
* sizeof(uint32_t));
348 unsigned unit
= instr
->texture_index
;
349 uint32_t w
= align(c
->key
->tex
[unit
].msaa_width
, tile_width
);
350 uint32_t w_tiles
= w
/ tile_width
;
351 uint32_t h
= align(c
->key
->tex
[unit
].msaa_height
, tile_height
);
352 uint32_t h_tiles
= h
/ tile_height
;
353 uint32_t size
= w_tiles
* h_tiles
* tile_size
;
356 assert(instr
->num_srcs
== 1);
357 assert(instr
->src
[0].src_type
== nir_tex_src_coord
);
358 addr
= ntq_get_src(c
, instr
->src
[0].src
, 0);
360 /* Perform the clamping required by kernel validation. */
361 addr
= qir_MAX(c
, addr
, qir_uniform_ui(c
, 0));
362 addr
= qir_MIN(c
, addr
, qir_uniform_ui(c
, size
- 4));
364 qir_TEX_DIRECT(c
, addr
, qir_uniform(c
, QUNIFORM_TEXTURE_MSAA_ADDR
, unit
));
366 struct qreg tex
= qir_TEX_RESULT(c
);
367 c
->num_texture_samples
++;
369 enum pipe_format format
= c
->key
->tex
[unit
].format
;
370 if (util_format_is_depth_or_stencil(format
)) {
371 struct qreg scaled
= ntq_scale_depth_texture(c
, tex
);
372 for (int i
= 0; i
< 4; i
++)
373 ntq_store_dest(c
, &instr
->dest
, i
, qir_MOV(c
, scaled
));
375 for (int i
= 0; i
< 4; i
++)
376 ntq_store_dest(c
, &instr
->dest
, i
,
377 qir_UNPACK_8_F(c
, tex
, i
));
382 ntq_emit_tex(struct vc4_compile
*c
, nir_tex_instr
*instr
)
384 struct qreg s
, t
, r
, lod
, compare
;
385 bool is_txb
= false, is_txl
= false;
386 unsigned unit
= instr
->texture_index
;
388 if (instr
->op
== nir_texop_txf
) {
389 ntq_emit_txf(c
, instr
);
393 for (unsigned i
= 0; i
< instr
->num_srcs
; i
++) {
394 switch (instr
->src
[i
].src_type
) {
395 case nir_tex_src_coord
:
396 s
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
397 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_1D
)
398 t
= qir_uniform_f(c
, 0.5);
400 t
= ntq_get_src(c
, instr
->src
[i
].src
, 1);
401 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
402 r
= ntq_get_src(c
, instr
->src
[i
].src
, 2);
404 case nir_tex_src_bias
:
405 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
408 case nir_tex_src_lod
:
409 lod
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
412 case nir_tex_src_comparitor
:
413 compare
= ntq_get_src(c
, instr
->src
[i
].src
, 0);
416 unreachable("unknown texture source");
420 if (c
->stage
!= QSTAGE_FRAG
&& !is_txl
) {
421 /* From the GLSL 1.20 spec:
423 * "If it is mip-mapped and running on the vertex shader,
424 * then the base texture is used."
427 lod
= qir_uniform_ui(c
, 0);
430 if (c
->key
->tex
[unit
].force_first_level
) {
431 lod
= qir_uniform(c
, QUNIFORM_TEXTURE_FIRST_LEVEL
, unit
);
436 struct qreg texture_u
[] = {
437 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P0
, unit
),
438 qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P1
, unit
),
439 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
440 qir_uniform(c
, QUNIFORM_CONSTANT
, 0),
442 uint32_t next_texture_u
= 0;
444 /* There is no native support for GL texture rectangle coordinates, so
445 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
448 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_RECT
) {
450 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_X
, unit
));
452 qir_uniform(c
, QUNIFORM_TEXRECT_SCALE_Y
, unit
));
455 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
|| is_txl
) {
456 texture_u
[2] = qir_uniform(c
, QUNIFORM_TEXTURE_CONFIG_P2
,
457 unit
| (is_txl
<< 16));
460 if (instr
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
) {
461 qir_TEX_R(c
, r
, texture_u
[next_texture_u
++]);
462 } else if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
463 c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
||
464 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP_TO_BORDER
||
465 c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
466 qir_TEX_R(c
, qir_uniform(c
, QUNIFORM_TEXTURE_BORDER_COLOR
, unit
),
467 texture_u
[next_texture_u
++]);
470 if (c
->key
->tex
[unit
].wrap_s
== PIPE_TEX_WRAP_CLAMP
) {
474 if (c
->key
->tex
[unit
].wrap_t
== PIPE_TEX_WRAP_CLAMP
) {
478 qir_TEX_T(c
, t
, texture_u
[next_texture_u
++]);
480 if (is_txl
|| is_txb
)
481 qir_TEX_B(c
, lod
, texture_u
[next_texture_u
++]);
483 qir_TEX_S(c
, s
, texture_u
[next_texture_u
++]);
485 c
->num_texture_samples
++;
486 struct qreg tex
= qir_TEX_RESULT(c
);
488 enum pipe_format format
= c
->key
->tex
[unit
].format
;
490 struct qreg
*dest
= ntq_get_dest(c
, &instr
->dest
);
491 if (util_format_is_depth_or_stencil(format
)) {
492 struct qreg normalized
= ntq_scale_depth_texture(c
, tex
);
493 struct qreg depth_output
;
495 struct qreg u0
= qir_uniform_f(c
, 0.0f
);
496 struct qreg u1
= qir_uniform_f(c
, 1.0f
);
497 if (c
->key
->tex
[unit
].compare_mode
) {
498 /* From the GL_ARB_shadow spec:
500 * "Let Dt (D subscript t) be the depth texture
501 * value, in the range [0, 1]. Let R be the
502 * interpolated texture coordinate clamped to the
505 compare
= qir_SAT(c
, compare
);
507 switch (c
->key
->tex
[unit
].compare_func
) {
508 case PIPE_FUNC_NEVER
:
509 depth_output
= qir_uniform_f(c
, 0.0f
);
511 case PIPE_FUNC_ALWAYS
:
514 case PIPE_FUNC_EQUAL
:
515 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
516 depth_output
= qir_SEL(c
, QPU_COND_ZS
, u1
, u0
);
518 case PIPE_FUNC_NOTEQUAL
:
519 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
520 depth_output
= qir_SEL(c
, QPU_COND_ZC
, u1
, u0
);
522 case PIPE_FUNC_GREATER
:
523 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
524 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
526 case PIPE_FUNC_GEQUAL
:
527 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
528 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
531 qir_SF(c
, qir_FSUB(c
, compare
, normalized
));
532 depth_output
= qir_SEL(c
, QPU_COND_NS
, u1
, u0
);
534 case PIPE_FUNC_LEQUAL
:
535 qir_SF(c
, qir_FSUB(c
, normalized
, compare
));
536 depth_output
= qir_SEL(c
, QPU_COND_NC
, u1
, u0
);
540 depth_output
= normalized
;
543 for (int i
= 0; i
< 4; i
++)
544 dest
[i
] = depth_output
;
546 for (int i
= 0; i
< 4; i
++)
547 dest
[i
] = qir_UNPACK_8_F(c
, tex
, i
);
552 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
556 ntq_ffract(struct vc4_compile
*c
, struct qreg src
)
558 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
559 struct qreg diff
= qir_FSUB(c
, src
, trunc
);
561 return qir_MOV(c
, qir_SEL(c
, QPU_COND_NS
,
562 qir_FADD(c
, diff
, qir_uniform_f(c
, 1.0)),
567 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
571 ntq_ffloor(struct vc4_compile
*c
, struct qreg src
)
573 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
575 /* This will be < 0 if we truncated and the truncation was of a value
576 * that was < 0 in the first place.
578 qir_SF(c
, qir_FSUB(c
, src
, trunc
));
580 return qir_MOV(c
, qir_SEL(c
, QPU_COND_NS
,
581 qir_FSUB(c
, trunc
, qir_uniform_f(c
, 1.0)),
586 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
590 ntq_fceil(struct vc4_compile
*c
, struct qreg src
)
592 struct qreg trunc
= qir_ITOF(c
, qir_FTOI(c
, src
));
594 /* This will be < 0 if we truncated and the truncation was of a value
595 * that was > 0 in the first place.
597 qir_SF(c
, qir_FSUB(c
, trunc
, src
));
599 return qir_MOV(c
, qir_SEL(c
, QPU_COND_NS
,
600 qir_FADD(c
, trunc
, qir_uniform_f(c
, 1.0)),
605 ntq_fsin(struct vc4_compile
*c
, struct qreg src
)
609 pow(2.0 * M_PI
, 3) / (3 * 2 * 1),
610 -pow(2.0 * M_PI
, 5) / (5 * 4 * 3 * 2 * 1),
611 pow(2.0 * M_PI
, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
612 -pow(2.0 * M_PI
, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
615 struct qreg scaled_x
=
618 qir_uniform_f(c
, 1.0 / (M_PI
* 2.0)));
620 struct qreg x
= qir_FADD(c
,
621 ntq_ffract(c
, scaled_x
),
622 qir_uniform_f(c
, -0.5));
623 struct qreg x2
= qir_FMUL(c
, x
, x
);
624 struct qreg sum
= qir_FMUL(c
, x
, qir_uniform_f(c
, coeff
[0]));
625 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
626 x
= qir_FMUL(c
, x
, x2
);
631 qir_uniform_f(c
, coeff
[i
])));
637 ntq_fcos(struct vc4_compile
*c
, struct qreg src
)
641 pow(2.0 * M_PI
, 2) / (2 * 1),
642 -pow(2.0 * M_PI
, 4) / (4 * 3 * 2 * 1),
643 pow(2.0 * M_PI
, 6) / (6 * 5 * 4 * 3 * 2 * 1),
644 -pow(2.0 * M_PI
, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
645 pow(2.0 * M_PI
, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
648 struct qreg scaled_x
=
650 qir_uniform_f(c
, 1.0f
/ (M_PI
* 2.0f
)));
651 struct qreg x_frac
= qir_FADD(c
,
652 ntq_ffract(c
, scaled_x
),
653 qir_uniform_f(c
, -0.5));
655 struct qreg sum
= qir_uniform_f(c
, coeff
[0]);
656 struct qreg x2
= qir_FMUL(c
, x_frac
, x_frac
);
657 struct qreg x
= x2
; /* Current x^2, x^4, or x^6 */
658 for (int i
= 1; i
< ARRAY_SIZE(coeff
); i
++) {
660 x
= qir_FMUL(c
, x
, x2
);
662 struct qreg mul
= qir_FMUL(c
,
664 qir_uniform_f(c
, coeff
[i
]));
668 sum
= qir_FADD(c
, sum
, mul
);
674 ntq_fsign(struct vc4_compile
*c
, struct qreg src
)
676 struct qreg t
= qir_get_temp(c
);
679 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 0.0));
680 qir_MOV_dest(c
, t
, qir_uniform_f(c
, 1.0))->cond
= QPU_COND_ZC
;
681 qir_MOV_dest(c
, t
, qir_uniform_f(c
, -1.0))->cond
= QPU_COND_NS
;
682 return qir_MOV(c
, t
);
686 emit_vertex_input(struct vc4_compile
*c
, int attr
)
688 enum pipe_format format
= c
->vs_key
->attr_formats
[attr
];
689 uint32_t attr_size
= util_format_get_blocksize(format
);
691 c
->vattr_sizes
[attr
] = align(attr_size
, 4);
692 for (int i
= 0; i
< align(attr_size
, 4) / 4; i
++) {
693 c
->inputs
[attr
* 4 + i
] =
694 qir_MOV(c
, qir_reg(QFILE_VPM
, attr
* 4 + i
));
700 emit_fragcoord_input(struct vc4_compile
*c
, int attr
)
702 c
->inputs
[attr
* 4 + 0] = qir_ITOF(c
, qir_reg(QFILE_FRAG_X
, 0));
703 c
->inputs
[attr
* 4 + 1] = qir_ITOF(c
, qir_reg(QFILE_FRAG_Y
, 0));
704 c
->inputs
[attr
* 4 + 2] =
706 qir_ITOF(c
, qir_FRAG_Z(c
)),
707 qir_uniform_f(c
, 1.0 / 0xffffff));
708 c
->inputs
[attr
* 4 + 3] = qir_RCP(c
, qir_FRAG_W(c
));
712 emit_fragment_varying(struct vc4_compile
*c
, gl_varying_slot slot
,
715 uint32_t i
= c
->num_input_slots
++;
721 if (c
->num_input_slots
>= c
->input_slots_array_size
) {
722 c
->input_slots_array_size
=
723 MAX2(4, c
->input_slots_array_size
* 2);
725 c
->input_slots
= reralloc(c
, c
->input_slots
,
726 struct vc4_varying_slot
,
727 c
->input_slots_array_size
);
730 c
->input_slots
[i
].slot
= slot
;
731 c
->input_slots
[i
].swizzle
= swizzle
;
733 return qir_VARY_ADD_C(c
, qir_FMUL(c
, vary
, qir_FRAG_W(c
)));
737 emit_fragment_input(struct vc4_compile
*c
, int attr
, gl_varying_slot slot
)
739 for (int i
= 0; i
< 4; i
++) {
740 c
->inputs
[attr
* 4 + i
] =
741 emit_fragment_varying(c
, slot
, i
);
747 add_output(struct vc4_compile
*c
,
748 uint32_t decl_offset
,
752 uint32_t old_array_size
= c
->outputs_array_size
;
753 resize_qreg_array(c
, &c
->outputs
, &c
->outputs_array_size
,
756 if (old_array_size
!= c
->outputs_array_size
) {
757 c
->output_slots
= reralloc(c
,
759 struct vc4_varying_slot
,
760 c
->outputs_array_size
);
763 c
->output_slots
[decl_offset
].slot
= slot
;
764 c
->output_slots
[decl_offset
].swizzle
= swizzle
;
768 declare_uniform_range(struct vc4_compile
*c
, uint32_t start
, uint32_t size
)
770 unsigned array_id
= c
->num_uniform_ranges
++;
771 if (array_id
>= c
->ubo_ranges_array_size
) {
772 c
->ubo_ranges_array_size
= MAX2(c
->ubo_ranges_array_size
* 2,
774 c
->ubo_ranges
= reralloc(c
, c
->ubo_ranges
,
775 struct vc4_compiler_ubo_range
,
776 c
->ubo_ranges_array_size
);
779 c
->ubo_ranges
[array_id
].dst_offset
= 0;
780 c
->ubo_ranges
[array_id
].src_offset
= start
;
781 c
->ubo_ranges
[array_id
].size
= size
;
782 c
->ubo_ranges
[array_id
].used
= false;
786 ntq_src_is_only_ssa_def_user(nir_src
*src
)
791 if (!list_empty(&src
->ssa
->if_uses
))
794 return (src
->ssa
->uses
.next
== &src
->use_link
&&
795 src
->ssa
->uses
.next
->next
== &src
->ssa
->uses
);
799 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
802 * However, as an optimization, it tries to find the instructions generating
803 * the sources to be packed and just emit the pack flag there, if possible.
806 ntq_emit_pack_unorm_4x8(struct vc4_compile
*c
, nir_alu_instr
*instr
)
808 struct qreg result
= qir_get_temp(c
);
809 struct nir_alu_instr
*vec4
= NULL
;
811 /* If packing from a vec4 op (as expected), identify it so that we can
812 * peek back at what generated its sources.
814 if (instr
->src
[0].src
.is_ssa
&&
815 instr
->src
[0].src
.ssa
->parent_instr
->type
== nir_instr_type_alu
&&
816 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
)->op
==
818 vec4
= nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
821 /* If the pack is replicating the same channel 4 times, use the 8888
822 * pack flag. This is common for blending using the alpha
825 if (instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[1] &&
826 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[2] &&
827 instr
->src
[0].swizzle
[0] == instr
->src
[0].swizzle
[3]) {
828 struct qreg rep
= ntq_get_src(c
,
830 instr
->src
[0].swizzle
[0]);
831 ntq_store_dest(c
, &instr
->dest
.dest
, 0, qir_PACK_8888_F(c
, rep
));
835 for (int i
= 0; i
< 4; i
++) {
836 int swiz
= instr
->src
[0].swizzle
[i
];
839 src
= ntq_get_src(c
, vec4
->src
[swiz
].src
,
840 vec4
->src
[swiz
].swizzle
[0]);
842 src
= ntq_get_src(c
, instr
->src
[0].src
, swiz
);
846 ntq_src_is_only_ssa_def_user(&vec4
->src
[swiz
].src
) &&
847 src
.file
== QFILE_TEMP
&&
848 c
->defs
[src
.index
] &&
849 qir_is_mul(c
->defs
[src
.index
]) &&
850 !c
->defs
[src
.index
]->dst
.pack
) {
851 struct qinst
*rewrite
= c
->defs
[src
.index
];
852 c
->defs
[src
.index
] = NULL
;
853 rewrite
->dst
= result
;
854 rewrite
->dst
.pack
= QPU_PACK_MUL_8A
+ i
;
858 qir_PACK_8_F(c
, result
, src
, i
);
861 ntq_store_dest(c
, &instr
->dest
.dest
, 0, qir_MOV(c
, result
));
864 /** Handles sign-extended bitfield extracts for 16 bits. */
866 ntq_emit_ibfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
869 assert(bits
.file
== QFILE_UNIF
&&
870 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
871 c
->uniform_data
[bits
.index
] == 16);
873 assert(offset
.file
== QFILE_UNIF
&&
874 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
875 int offset_bit
= c
->uniform_data
[offset
.index
];
876 assert(offset_bit
% 16 == 0);
878 return qir_UNPACK_16_I(c
, base
, offset_bit
/ 16);
881 /** Handles unsigned bitfield extracts for 8 bits. */
883 ntq_emit_ubfe(struct vc4_compile
*c
, struct qreg base
, struct qreg offset
,
886 assert(bits
.file
== QFILE_UNIF
&&
887 c
->uniform_contents
[bits
.index
] == QUNIFORM_CONSTANT
&&
888 c
->uniform_data
[bits
.index
] == 8);
890 assert(offset
.file
== QFILE_UNIF
&&
891 c
->uniform_contents
[offset
.index
] == QUNIFORM_CONSTANT
);
892 int offset_bit
= c
->uniform_data
[offset
.index
];
893 assert(offset_bit
% 8 == 0);
895 return qir_UNPACK_8_I(c
, base
, offset_bit
/ 8);
899 * If compare_instr is a valid comparison instruction, emits the
900 * compare_instr's comparison and returns the sel_instr's return value based
901 * on the compare_instr's result.
904 ntq_emit_comparison(struct vc4_compile
*c
, struct qreg
*dest
,
905 nir_alu_instr
*compare_instr
,
906 nir_alu_instr
*sel_instr
)
910 switch (compare_instr
->op
) {
936 struct qreg src0
= ntq_get_alu_src(c
, compare_instr
, 0);
937 struct qreg src1
= ntq_get_alu_src(c
, compare_instr
, 1);
939 unsigned unsized_type
=
940 nir_alu_type_get_base_type(nir_op_infos
[compare_instr
->op
].input_types
[0]);
941 if (unsized_type
== nir_type_float
)
942 qir_SF(c
, qir_FSUB(c
, src0
, src1
));
944 qir_SF(c
, qir_SUB(c
, src0
, src1
));
946 switch (sel_instr
->op
) {
951 *dest
= qir_SEL(c
, cond
,
952 qir_uniform_f(c
, 1.0), qir_uniform_f(c
, 0.0));
956 *dest
= qir_SEL(c
, cond
,
957 ntq_get_alu_src(c
, sel_instr
, 1),
958 ntq_get_alu_src(c
, sel_instr
, 2));
962 *dest
= qir_SEL(c
, cond
,
963 qir_uniform_ui(c
, ~0), qir_uniform_ui(c
, 0));
967 /* Make the temporary for nir_store_dest(). */
968 *dest
= qir_MOV(c
, *dest
);
974 * Attempts to fold a comparison generating a boolean result into the
975 * condition code for selecting between two values, instead of comparing the
976 * boolean result against 0 to generate the condition code.
978 static struct qreg
ntq_emit_bcsel(struct vc4_compile
*c
, nir_alu_instr
*instr
,
981 if (!instr
->src
[0].src
.is_ssa
)
983 if (instr
->src
[0].src
.ssa
->parent_instr
->type
!= nir_instr_type_alu
)
985 nir_alu_instr
*compare
=
986 nir_instr_as_alu(instr
->src
[0].src
.ssa
->parent_instr
);
991 if (ntq_emit_comparison(c
, &dest
, compare
, instr
))
996 return qir_MOV(c
, qir_SEL(c
, QPU_COND_NS
, src
[1], src
[2]));
1000 ntq_fddx(struct vc4_compile
*c
, struct qreg src
)
1002 /* Make sure that we have a bare temp to use for MUL rotation, so it
1003 * can be allocated to an accumulator.
1005 if (src
.pack
|| src
.file
!= QFILE_TEMP
)
1006 src
= qir_MOV(c
, src
);
1008 struct qreg from_left
= qir_ROT_MUL(c
, src
, 1);
1009 struct qreg from_right
= qir_ROT_MUL(c
, src
, 15);
1011 /* Distinguish left/right pixels of the quad. */
1012 qir_SF(c
, qir_AND(c
, qir_reg(QFILE_QPU_ELEMENT
, 0),
1013 qir_uniform_ui(c
, 1)));
1015 return qir_MOV(c
, qir_SEL(c
, QPU_COND_ZS
,
1016 qir_FSUB(c
, from_right
, src
),
1017 qir_FSUB(c
, src
, from_left
)));
1021 ntq_fddy(struct vc4_compile
*c
, struct qreg src
)
1023 if (src
.pack
|| src
.file
!= QFILE_TEMP
)
1024 src
= qir_MOV(c
, src
);
1026 struct qreg from_bottom
= qir_ROT_MUL(c
, src
, 2);
1027 struct qreg from_top
= qir_ROT_MUL(c
, src
, 14);
1029 /* Distinguish top/bottom pixels of the quad. */
1030 qir_SF(c
, qir_AND(c
,
1031 qir_reg(QFILE_QPU_ELEMENT
, 0),
1032 qir_uniform_ui(c
, 2)));
1034 return qir_MOV(c
, qir_SEL(c
, QPU_COND_ZS
,
1035 qir_FSUB(c
, from_top
, src
),
1036 qir_FSUB(c
, src
, from_bottom
)));
1040 ntq_emit_alu(struct vc4_compile
*c
, nir_alu_instr
*instr
)
1042 /* This should always be lowered to ALU operations for VC4. */
1043 assert(!instr
->dest
.saturate
);
1045 /* Vectors are special in that they have non-scalarized writemasks,
1046 * and just take the first swizzle channel for each argument in order
1047 * into each writemask channel.
1049 if (instr
->op
== nir_op_vec2
||
1050 instr
->op
== nir_op_vec3
||
1051 instr
->op
== nir_op_vec4
) {
1052 struct qreg srcs
[4];
1053 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1054 srcs
[i
] = ntq_get_src(c
, instr
->src
[i
].src
,
1055 instr
->src
[i
].swizzle
[0]);
1056 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++)
1057 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
1058 qir_MOV(c
, srcs
[i
]));
1062 if (instr
->op
== nir_op_pack_unorm_4x8
) {
1063 ntq_emit_pack_unorm_4x8(c
, instr
);
1067 if (instr
->op
== nir_op_unpack_unorm_4x8
) {
1068 struct qreg src
= ntq_get_src(c
, instr
->src
[0].src
,
1069 instr
->src
[0].swizzle
[0]);
1070 for (int i
= 0; i
< 4; i
++) {
1071 if (instr
->dest
.write_mask
& (1 << i
))
1072 ntq_store_dest(c
, &instr
->dest
.dest
, i
,
1073 qir_UNPACK_8_F(c
, src
, i
));
1078 /* General case: We can just grab the one used channel per src. */
1079 struct qreg src
[nir_op_infos
[instr
->op
].num_inputs
];
1080 for (int i
= 0; i
< nir_op_infos
[instr
->op
].num_inputs
; i
++) {
1081 src
[i
] = ntq_get_alu_src(c
, instr
, i
);
1086 switch (instr
->op
) {
1089 result
= qir_MOV(c
, src
[0]);
1092 result
= qir_FMUL(c
, src
[0], src
[1]);
1095 result
= qir_FADD(c
, src
[0], src
[1]);
1098 result
= qir_FSUB(c
, src
[0], src
[1]);
1101 result
= qir_FMIN(c
, src
[0], src
[1]);
1104 result
= qir_FMAX(c
, src
[0], src
[1]);
1109 result
= qir_FTOI(c
, src
[0]);
1113 result
= qir_ITOF(c
, src
[0]);
1116 result
= qir_AND(c
, src
[0], qir_uniform_f(c
, 1.0));
1119 result
= qir_AND(c
, src
[0], qir_uniform_ui(c
, 1));
1124 result
= qir_MOV(c
, qir_SEL(c
, QPU_COND_ZC
,
1125 qir_uniform_ui(c
, ~0),
1126 qir_uniform_ui(c
, 0)));
1130 result
= qir_ADD(c
, src
[0], src
[1]);
1133 result
= qir_SHR(c
, src
[0], src
[1]);
1136 result
= qir_SUB(c
, src
[0], src
[1]);
1139 result
= qir_ASR(c
, src
[0], src
[1]);
1142 result
= qir_SHL(c
, src
[0], src
[1]);
1145 result
= qir_MIN(c
, src
[0], src
[1]);
1148 result
= qir_MAX(c
, src
[0], src
[1]);
1151 result
= qir_AND(c
, src
[0], src
[1]);
1154 result
= qir_OR(c
, src
[0], src
[1]);
1157 result
= qir_XOR(c
, src
[0], src
[1]);
1160 result
= qir_NOT(c
, src
[0]);
1164 result
= ntq_umul(c
, src
[0], src
[1]);
1180 if (!ntq_emit_comparison(c
, &result
, instr
, instr
)) {
1181 fprintf(stderr
, "Bad comparison instruction\n");
1186 result
= ntq_emit_bcsel(c
, instr
, src
);
1190 result
= qir_MOV(c
, qir_SEL(c
, QPU_COND_ZC
, src
[1], src
[2]));
1194 result
= ntq_rcp(c
, src
[0]);
1197 result
= ntq_rsq(c
, src
[0]);
1200 result
= qir_EXP2(c
, src
[0]);
1203 result
= qir_LOG2(c
, src
[0]);
1207 result
= qir_ITOF(c
, qir_FTOI(c
, src
[0]));
1210 result
= ntq_fceil(c
, src
[0]);
1213 result
= ntq_ffract(c
, src
[0]);
1216 result
= ntq_ffloor(c
, src
[0]);
1220 result
= ntq_fsin(c
, src
[0]);
1223 result
= ntq_fcos(c
, src
[0]);
1227 result
= ntq_fsign(c
, src
[0]);
1231 result
= qir_FMAXABS(c
, src
[0], src
[0]);
1234 result
= qir_MAX(c
, src
[0],
1235 qir_SUB(c
, qir_uniform_ui(c
, 0), src
[0]));
1238 case nir_op_ibitfield_extract
:
1239 result
= ntq_emit_ibfe(c
, src
[0], src
[1], src
[2]);
1242 case nir_op_ubitfield_extract
:
1243 result
= ntq_emit_ubfe(c
, src
[0], src
[1], src
[2]);
1246 case nir_op_usadd_4x8
:
1247 result
= qir_V8ADDS(c
, src
[0], src
[1]);
1250 case nir_op_ussub_4x8
:
1251 result
= qir_V8SUBS(c
, src
[0], src
[1]);
1254 case nir_op_umin_4x8
:
1255 result
= qir_V8MIN(c
, src
[0], src
[1]);
1258 case nir_op_umax_4x8
:
1259 result
= qir_V8MAX(c
, src
[0], src
[1]);
1262 case nir_op_umul_unorm_4x8
:
1263 result
= qir_V8MULD(c
, src
[0], src
[1]);
1267 case nir_op_fddx_coarse
:
1268 case nir_op_fddx_fine
:
1269 result
= ntq_fddx(c
, src
[0]);
1273 case nir_op_fddy_coarse
:
1274 case nir_op_fddy_fine
:
1275 result
= ntq_fddy(c
, src
[0]);
1279 fprintf(stderr
, "unknown NIR ALU inst: ");
1280 nir_print_instr(&instr
->instr
, stderr
);
1281 fprintf(stderr
, "\n");
1285 /* We have a scalar result, so the instruction should only have a
1286 * single channel written to.
1288 assert(util_is_power_of_two(instr
->dest
.write_mask
));
1289 ntq_store_dest(c
, &instr
->dest
.dest
,
1290 ffs(instr
->dest
.write_mask
) - 1, result
);
1294 emit_frag_end(struct vc4_compile
*c
)
1297 if (c
->output_color_index
!= -1) {
1298 color
= c
->outputs
[c
->output_color_index
];
1300 color
= qir_uniform_ui(c
, 0);
1303 uint32_t discard_cond
= QPU_COND_ALWAYS
;
1304 if (c
->s
->info
->fs
.uses_discard
) {
1305 qir_SF(c
, c
->discard
);
1306 discard_cond
= QPU_COND_ZS
;
1309 if (c
->fs_key
->stencil_enabled
) {
1310 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1311 qir_uniform(c
, QUNIFORM_STENCIL
, 0));
1312 if (c
->fs_key
->stencil_twoside
) {
1313 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1314 qir_uniform(c
, QUNIFORM_STENCIL
, 1));
1316 if (c
->fs_key
->stencil_full_writemasks
) {
1317 qir_MOV_dest(c
, qir_reg(QFILE_TLB_STENCIL_SETUP
, 0),
1318 qir_uniform(c
, QUNIFORM_STENCIL
, 2));
1322 if (c
->output_sample_mask_index
!= -1) {
1323 qir_MS_MASK(c
, c
->outputs
[c
->output_sample_mask_index
]);
1326 if (c
->fs_key
->depth_enabled
) {
1327 if (c
->output_position_index
!= -1) {
1328 qir_FTOI_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1330 c
->outputs
[c
->output_position_index
],
1331 qir_uniform_f(c
, 0xffffff)))->cond
= discard_cond
;
1333 qir_MOV_dest(c
, qir_reg(QFILE_TLB_Z_WRITE
, 0),
1334 qir_FRAG_Z(c
))->cond
= discard_cond
;
1338 if (!c
->msaa_per_sample_output
) {
1339 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE
, 0),
1340 color
)->cond
= discard_cond
;
1342 for (int i
= 0; i
< VC4_MAX_SAMPLES
; i
++) {
1343 qir_MOV_dest(c
, qir_reg(QFILE_TLB_COLOR_WRITE_MS
, 0),
1344 c
->sample_colors
[i
])->cond
= discard_cond
;
1350 emit_scaled_viewport_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1352 struct qreg packed
= qir_get_temp(c
);
1354 for (int i
= 0; i
< 2; i
++) {
1356 qir_uniform(c
, QUNIFORM_VIEWPORT_X_SCALE
+ i
, 0);
1358 struct qreg packed_chan
= packed
;
1359 packed_chan
.pack
= QPU_PACK_A_16A
+ i
;
1361 qir_FTOI_dest(c
, packed_chan
,
1364 c
->outputs
[c
->output_position_index
+ i
],
1369 qir_VPM_WRITE(c
, packed
);
1373 emit_zs_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1375 struct qreg zscale
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_SCALE
, 0);
1376 struct qreg zoffset
= qir_uniform(c
, QUNIFORM_VIEWPORT_Z_OFFSET
, 0);
1378 qir_VPM_WRITE(c
, qir_FADD(c
, qir_FMUL(c
, qir_FMUL(c
,
1379 c
->outputs
[c
->output_position_index
+ 2],
1386 emit_rcp_wc_write(struct vc4_compile
*c
, struct qreg rcp_w
)
1388 qir_VPM_WRITE(c
, rcp_w
);
1392 emit_point_size_write(struct vc4_compile
*c
)
1394 struct qreg point_size
;
1396 if (c
->output_point_size_index
!= -1)
1397 point_size
= c
->outputs
[c
->output_point_size_index
];
1399 point_size
= qir_uniform_f(c
, 1.0);
1401 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1404 point_size
= qir_FMAX(c
, point_size
, qir_uniform_f(c
, .125));
1406 qir_VPM_WRITE(c
, point_size
);
1410 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1412 * The simulator insists that there be at least one vertex attribute, so
1413 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1414 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1415 * to consume it here.
1418 emit_stub_vpm_read(struct vc4_compile
*c
)
1423 c
->vattr_sizes
[0] = 4;
1424 (void)qir_MOV(c
, qir_reg(QFILE_VPM
, 0));
1429 emit_vert_end(struct vc4_compile
*c
,
1430 struct vc4_varying_slot
*fs_inputs
,
1431 uint32_t num_fs_inputs
)
1433 struct qreg rcp_w
= ntq_rcp(c
, c
->outputs
[c
->output_position_index
+ 3]);
1435 emit_stub_vpm_read(c
);
1437 emit_scaled_viewport_write(c
, rcp_w
);
1438 emit_zs_write(c
, rcp_w
);
1439 emit_rcp_wc_write(c
, rcp_w
);
1440 if (c
->vs_key
->per_vertex_point_size
)
1441 emit_point_size_write(c
);
1443 for (int i
= 0; i
< num_fs_inputs
; i
++) {
1444 struct vc4_varying_slot
*input
= &fs_inputs
[i
];
1447 for (j
= 0; j
< c
->num_outputs
; j
++) {
1448 struct vc4_varying_slot
*output
=
1449 &c
->output_slots
[j
];
1451 if (input
->slot
== output
->slot
&&
1452 input
->swizzle
== output
->swizzle
) {
1453 qir_VPM_WRITE(c
, c
->outputs
[j
]);
1457 /* Emit padding if we didn't find a declared VS output for
1460 if (j
== c
->num_outputs
)
1461 qir_VPM_WRITE(c
, qir_uniform_f(c
, 0.0));
1466 emit_coord_end(struct vc4_compile
*c
)
1468 struct qreg rcp_w
= qir_RCP(c
, c
->outputs
[c
->output_position_index
+ 3]);
1470 emit_stub_vpm_read(c
);
1472 for (int i
= 0; i
< 4; i
++)
1473 qir_VPM_WRITE(c
, c
->outputs
[c
->output_position_index
+ i
]);
1475 emit_scaled_viewport_write(c
, rcp_w
);
1476 emit_zs_write(c
, rcp_w
);
1477 emit_rcp_wc_write(c
, rcp_w
);
1478 if (c
->vs_key
->per_vertex_point_size
)
1479 emit_point_size_write(c
);
1483 vc4_optimize_nir(struct nir_shader
*s
)
1490 NIR_PASS_V(s
, nir_lower_vars_to_ssa
);
1491 NIR_PASS(progress
, s
, nir_lower_alu_to_scalar
);
1492 NIR_PASS(progress
, s
, nir_lower_phis_to_scalar
);
1493 NIR_PASS(progress
, s
, nir_copy_prop
);
1494 NIR_PASS(progress
, s
, nir_opt_remove_phis
);
1495 NIR_PASS(progress
, s
, nir_opt_dce
);
1496 NIR_PASS(progress
, s
, nir_opt_dead_cf
);
1497 NIR_PASS(progress
, s
, nir_opt_cse
);
1498 NIR_PASS(progress
, s
, nir_opt_peephole_select
, 8);
1499 NIR_PASS(progress
, s
, nir_opt_algebraic
);
1500 NIR_PASS(progress
, s
, nir_opt_constant_folding
);
1501 NIR_PASS(progress
, s
, nir_opt_undef
);
1506 driver_location_compare(const void *in_a
, const void *in_b
)
1508 const nir_variable
*const *a
= in_a
;
1509 const nir_variable
*const *b
= in_b
;
1511 return (*a
)->data
.driver_location
- (*b
)->data
.driver_location
;
1515 ntq_setup_inputs(struct vc4_compile
*c
)
1517 unsigned num_entries
= 0;
1518 nir_foreach_variable(var
, &c
->s
->inputs
)
1521 nir_variable
*vars
[num_entries
];
1524 nir_foreach_variable(var
, &c
->s
->inputs
)
1527 /* Sort the variables so that we emit the input setup in
1528 * driver_location order. This is required for VPM reads, whose data
1529 * is fetched into the VPM in driver_location (TGSI register index)
1532 qsort(&vars
, num_entries
, sizeof(*vars
), driver_location_compare
);
1534 for (unsigned i
= 0; i
< num_entries
; i
++) {
1535 nir_variable
*var
= vars
[i
];
1536 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1537 unsigned loc
= var
->data
.driver_location
;
1539 assert(array_len
== 1);
1541 resize_qreg_array(c
, &c
->inputs
, &c
->inputs_array_size
,
1544 if (c
->stage
== QSTAGE_FRAG
) {
1545 if (var
->data
.location
== VARYING_SLOT_POS
) {
1546 emit_fragcoord_input(c
, loc
);
1547 } else if (var
->data
.location
== VARYING_SLOT_PNTC
||
1548 (var
->data
.location
>= VARYING_SLOT_VAR0
&&
1549 (c
->fs_key
->point_sprite_mask
&
1550 (1 << (var
->data
.location
-
1551 VARYING_SLOT_VAR0
))))) {
1552 c
->inputs
[loc
* 4 + 0] = c
->point_x
;
1553 c
->inputs
[loc
* 4 + 1] = c
->point_y
;
1555 emit_fragment_input(c
, loc
, var
->data
.location
);
1558 emit_vertex_input(c
, loc
);
1564 ntq_setup_outputs(struct vc4_compile
*c
)
1566 nir_foreach_variable(var
, &c
->s
->outputs
) {
1567 unsigned array_len
= MAX2(glsl_get_length(var
->type
), 1);
1568 unsigned loc
= var
->data
.driver_location
* 4;
1570 assert(array_len
== 1);
1573 for (int i
= 0; i
< 4; i
++)
1574 add_output(c
, loc
+ i
, var
->data
.location
, i
);
1576 if (c
->stage
== QSTAGE_FRAG
) {
1577 switch (var
->data
.location
) {
1578 case FRAG_RESULT_COLOR
:
1579 case FRAG_RESULT_DATA0
:
1580 c
->output_color_index
= loc
;
1582 case FRAG_RESULT_DEPTH
:
1583 c
->output_position_index
= loc
;
1585 case FRAG_RESULT_SAMPLE_MASK
:
1586 c
->output_sample_mask_index
= loc
;
1590 switch (var
->data
.location
) {
1591 case VARYING_SLOT_POS
:
1592 c
->output_position_index
= loc
;
1594 case VARYING_SLOT_PSIZ
:
1595 c
->output_point_size_index
= loc
;
1603 ntq_setup_uniforms(struct vc4_compile
*c
)
1605 nir_foreach_variable(var
, &c
->s
->uniforms
) {
1606 uint32_t vec4_count
= st_glsl_type_size(var
->type
);
1607 unsigned vec4_size
= 4 * sizeof(float);
1609 declare_uniform_range(c
, var
->data
.driver_location
* vec4_size
,
1610 vec4_count
* vec4_size
);
1616 * Sets up the mapping from nir_register to struct qreg *.
1618 * Each nir_register gets a struct qreg per 32-bit component being stored.
1621 ntq_setup_registers(struct vc4_compile
*c
, struct exec_list
*list
)
1623 foreach_list_typed(nir_register
, nir_reg
, node
, list
) {
1624 unsigned array_len
= MAX2(nir_reg
->num_array_elems
, 1);
1625 struct qreg
*qregs
= ralloc_array(c
->def_ht
, struct qreg
,
1627 nir_reg
->num_components
);
1629 _mesa_hash_table_insert(c
->def_ht
, nir_reg
, qregs
);
1631 for (int i
= 0; i
< array_len
* nir_reg
->num_components
; i
++)
1632 qregs
[i
] = qir_get_temp(c
);
1637 ntq_emit_load_const(struct vc4_compile
*c
, nir_load_const_instr
*instr
)
1639 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1640 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1641 qregs
[i
] = qir_uniform_ui(c
, instr
->value
.u32
[i
]);
1643 _mesa_hash_table_insert(c
->def_ht
, &instr
->def
, qregs
);
1647 ntq_emit_ssa_undef(struct vc4_compile
*c
, nir_ssa_undef_instr
*instr
)
1649 struct qreg
*qregs
= ntq_init_ssa_def(c
, &instr
->def
);
1651 /* QIR needs there to be *some* value, so pick 0 (same as for
1652 * ntq_setup_registers().
1654 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1655 qregs
[i
] = qir_uniform_ui(c
, 0);
1659 ntq_emit_intrinsic(struct vc4_compile
*c
, nir_intrinsic_instr
*instr
)
1661 nir_const_value
*const_offset
;
1664 switch (instr
->intrinsic
) {
1665 case nir_intrinsic_load_uniform
:
1666 assert(instr
->num_components
== 1);
1667 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1669 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1670 assert(offset
% 4 == 0);
1671 /* We need dwords */
1672 offset
= offset
/ 4;
1673 ntq_store_dest(c
, &instr
->dest
, 0,
1674 qir_uniform(c
, QUNIFORM_UNIFORM
,
1677 ntq_store_dest(c
, &instr
->dest
, 0,
1678 indirect_uniform_load(c
, instr
));
1682 case nir_intrinsic_load_user_clip_plane
:
1683 for (int i
= 0; i
< instr
->num_components
; i
++) {
1684 ntq_store_dest(c
, &instr
->dest
, i
,
1685 qir_uniform(c
, QUNIFORM_USER_CLIP_PLANE
,
1686 nir_intrinsic_ucp_id(instr
) *
1691 case nir_intrinsic_load_blend_const_color_r_float
:
1692 case nir_intrinsic_load_blend_const_color_g_float
:
1693 case nir_intrinsic_load_blend_const_color_b_float
:
1694 case nir_intrinsic_load_blend_const_color_a_float
:
1695 ntq_store_dest(c
, &instr
->dest
, 0,
1696 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_X
+
1698 nir_intrinsic_load_blend_const_color_r_float
),
1702 case nir_intrinsic_load_blend_const_color_rgba8888_unorm
:
1703 ntq_store_dest(c
, &instr
->dest
, 0,
1704 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_RGBA
,
1708 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm
:
1709 ntq_store_dest(c
, &instr
->dest
, 0,
1710 qir_uniform(c
, QUNIFORM_BLEND_CONST_COLOR_AAAA
,
1714 case nir_intrinsic_load_alpha_ref_float
:
1715 ntq_store_dest(c
, &instr
->dest
, 0,
1716 qir_uniform(c
, QUNIFORM_ALPHA_REF
, 0));
1719 case nir_intrinsic_load_sample_mask_in
:
1720 ntq_store_dest(c
, &instr
->dest
, 0,
1721 qir_uniform(c
, QUNIFORM_SAMPLE_MASK
, 0));
1724 case nir_intrinsic_load_front_face
:
1725 /* The register contains 0 (front) or 1 (back), and we need to
1726 * turn it into a NIR bool where true means front.
1728 ntq_store_dest(c
, &instr
->dest
, 0,
1730 qir_uniform_ui(c
, -1),
1731 qir_reg(QFILE_FRAG_REV_FLAG
, 0)));
1734 case nir_intrinsic_load_input
:
1735 assert(instr
->num_components
== 1);
1736 const_offset
= nir_src_as_const_value(instr
->src
[0]);
1737 assert(const_offset
&& "vc4 doesn't support indirect inputs");
1738 if (c
->stage
== QSTAGE_FRAG
&&
1739 nir_intrinsic_base(instr
) >= VC4_NIR_TLB_COLOR_READ_INPUT
) {
1740 assert(const_offset
->u32
[0] == 0);
1741 /* Reads of the per-sample color need to be done in
1744 int sample_index
= (nir_intrinsic_base(instr
) -
1745 VC4_NIR_TLB_COLOR_READ_INPUT
);
1746 for (int i
= 0; i
<= sample_index
; i
++) {
1747 if (c
->color_reads
[i
].file
== QFILE_NULL
) {
1749 qir_TLB_COLOR_READ(c
);
1752 ntq_store_dest(c
, &instr
->dest
, 0,
1753 qir_MOV(c
, c
->color_reads
[sample_index
]));
1755 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1756 int comp
= nir_intrinsic_component(instr
);
1757 ntq_store_dest(c
, &instr
->dest
, 0,
1758 qir_MOV(c
, c
->inputs
[offset
* 4 + comp
]));
1762 case nir_intrinsic_store_output
:
1763 const_offset
= nir_src_as_const_value(instr
->src
[1]);
1764 assert(const_offset
&& "vc4 doesn't support indirect outputs");
1765 offset
= nir_intrinsic_base(instr
) + const_offset
->u32
[0];
1767 /* MSAA color outputs are the only case where we have an
1768 * output that's not lowered to being a store of a single 32
1771 if (c
->stage
== QSTAGE_FRAG
&& instr
->num_components
== 4) {
1772 assert(offset
== c
->output_color_index
);
1773 for (int i
= 0; i
< 4; i
++) {
1774 c
->sample_colors
[i
] =
1775 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0],
1779 offset
= offset
* 4 + nir_intrinsic_component(instr
);
1780 assert(instr
->num_components
== 1);
1781 c
->outputs
[offset
] =
1782 qir_MOV(c
, ntq_get_src(c
, instr
->src
[0], 0));
1783 c
->num_outputs
= MAX2(c
->num_outputs
, offset
+ 1);
1787 case nir_intrinsic_discard
:
1788 if (c
->execute
.file
!= QFILE_NULL
) {
1789 qir_SF(c
, c
->execute
);
1790 qir_MOV_cond(c
, QPU_COND_ZS
, c
->discard
,
1791 qir_uniform_ui(c
, ~0));
1793 qir_MOV_dest(c
, c
->discard
, qir_uniform_ui(c
, ~0));
1797 case nir_intrinsic_discard_if
: {
1798 /* true (~0) if we're discarding */
1799 struct qreg cond
= ntq_get_src(c
, instr
->src
[0], 0);
1801 if (c
->execute
.file
!= QFILE_NULL
) {
1802 /* execute == 0 means the channel is active. Invert
1803 * the condition so that we can use zero as "executing
1806 qir_SF(c
, qir_AND(c
, c
->execute
, qir_NOT(c
, cond
)));
1807 qir_MOV_cond(c
, QPU_COND_ZS
, c
->discard
, cond
);
1809 qir_OR_dest(c
, c
->discard
, c
->discard
,
1810 ntq_get_src(c
, instr
->src
[0], 0));
1817 fprintf(stderr
, "Unknown intrinsic: ");
1818 nir_print_instr(&instr
->instr
, stderr
);
1819 fprintf(stderr
, "\n");
1824 /* Clears (activates) the execute flags for any channels whose jump target
1825 * matches this block.
1828 ntq_activate_execute_for_block(struct vc4_compile
*c
)
1830 qir_SF(c
, qir_SUB(c
,
1832 qir_uniform_ui(c
, c
->cur_block
->index
)));
1833 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
, qir_uniform_ui(c
, 0));
1837 ntq_emit_if(struct vc4_compile
*c
, nir_if
*if_stmt
)
1839 if (!c
->vc4
->screen
->has_control_flow
) {
1841 "IF statement support requires updated kernel.\n");
1845 nir_block
*nir_else_block
= nir_if_first_else_block(if_stmt
);
1846 bool empty_else_block
=
1847 (nir_else_block
== nir_if_last_else_block(if_stmt
) &&
1848 exec_list_is_empty(&nir_else_block
->instr_list
));
1850 struct qblock
*then_block
= qir_new_block(c
);
1851 struct qblock
*after_block
= qir_new_block(c
);
1852 struct qblock
*else_block
;
1853 if (empty_else_block
)
1854 else_block
= after_block
;
1856 else_block
= qir_new_block(c
);
1858 bool was_top_level
= false;
1859 if (c
->execute
.file
== QFILE_NULL
) {
1860 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1861 was_top_level
= true;
1864 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1865 * 0) channels, and then update execute flags for those to point to
1870 ntq_get_src(c
, if_stmt
->condition
, 0)));
1871 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1872 qir_uniform_ui(c
, else_block
->index
));
1874 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1877 qir_SF(c
, c
->execute
);
1878 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZC
);
1879 qir_link_blocks(c
->cur_block
, else_block
);
1880 qir_link_blocks(c
->cur_block
, then_block
);
1882 /* Process the THEN block. */
1883 qir_set_emit_block(c
, then_block
);
1884 ntq_emit_cf_list(c
, &if_stmt
->then_list
);
1886 if (!empty_else_block
) {
1887 /* Handle the end of the THEN block. First, all currently
1888 * active channels update their execute flags to point to
1891 qir_SF(c
, c
->execute
);
1892 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1893 qir_uniform_ui(c
, after_block
->index
));
1895 /* If everything points at ENDIF, then jump there immediately. */
1896 qir_SF(c
, qir_SUB(c
, c
->execute
, qir_uniform_ui(c
, after_block
->index
)));
1897 qir_BRANCH(c
, QPU_COND_BRANCH_ALL_ZS
);
1898 qir_link_blocks(c
->cur_block
, after_block
);
1899 qir_link_blocks(c
->cur_block
, else_block
);
1901 qir_set_emit_block(c
, else_block
);
1902 ntq_activate_execute_for_block(c
);
1903 ntq_emit_cf_list(c
, &if_stmt
->else_list
);
1906 qir_link_blocks(c
->cur_block
, after_block
);
1908 qir_set_emit_block(c
, after_block
);
1910 c
->execute
= c
->undef
;
1912 ntq_activate_execute_for_block(c
);
1917 ntq_emit_jump(struct vc4_compile
*c
, nir_jump_instr
*jump
)
1919 switch (jump
->type
) {
1920 case nir_jump_break
:
1921 qir_SF(c
, c
->execute
);
1922 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1923 qir_uniform_ui(c
, c
->loop_break_block
->index
));
1926 case nir_jump_continue
:
1927 qir_SF(c
, c
->execute
);
1928 qir_MOV_cond(c
, QPU_COND_ZS
, c
->execute
,
1929 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
1932 case nir_jump_return
:
1933 unreachable("All returns shouold be lowered\n");
1938 ntq_emit_instr(struct vc4_compile
*c
, nir_instr
*instr
)
1940 switch (instr
->type
) {
1941 case nir_instr_type_alu
:
1942 ntq_emit_alu(c
, nir_instr_as_alu(instr
));
1945 case nir_instr_type_intrinsic
:
1946 ntq_emit_intrinsic(c
, nir_instr_as_intrinsic(instr
));
1949 case nir_instr_type_load_const
:
1950 ntq_emit_load_const(c
, nir_instr_as_load_const(instr
));
1953 case nir_instr_type_ssa_undef
:
1954 ntq_emit_ssa_undef(c
, nir_instr_as_ssa_undef(instr
));
1957 case nir_instr_type_tex
:
1958 ntq_emit_tex(c
, nir_instr_as_tex(instr
));
1961 case nir_instr_type_jump
:
1962 ntq_emit_jump(c
, nir_instr_as_jump(instr
));
1966 fprintf(stderr
, "Unknown NIR instr type: ");
1967 nir_print_instr(instr
, stderr
);
1968 fprintf(stderr
, "\n");
1974 ntq_emit_block(struct vc4_compile
*c
, nir_block
*block
)
1976 nir_foreach_instr(instr
, block
) {
1977 ntq_emit_instr(c
, instr
);
1981 static void ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
);
1984 ntq_emit_loop(struct vc4_compile
*c
, nir_loop
*loop
)
1986 if (!c
->vc4
->screen
->has_control_flow
) {
1988 "loop support requires updated kernel.\n");
1989 ntq_emit_cf_list(c
, &loop
->body
);
1993 bool was_top_level
= false;
1994 if (c
->execute
.file
== QFILE_NULL
) {
1995 c
->execute
= qir_MOV(c
, qir_uniform_ui(c
, 0));
1996 was_top_level
= true;
1999 struct qblock
*save_loop_cont_block
= c
->loop_cont_block
;
2000 struct qblock
*save_loop_break_block
= c
->loop_break_block
;
2002 c
->loop_cont_block
= qir_new_block(c
);
2003 c
->loop_break_block
= qir_new_block(c
);
2005 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2006 qir_set_emit_block(c
, c
->loop_cont_block
);
2007 ntq_activate_execute_for_block(c
);
2009 ntq_emit_cf_list(c
, &loop
->body
);
2011 /* If anything had explicitly continued, or is here at the end of the
2012 * loop, then we need to loop again. SF updates are masked by the
2013 * instruction's condition, so we can do the OR of the two conditions
2016 qir_SF(c
, c
->execute
);
2017 struct qinst
*cont_check
=
2021 qir_uniform_ui(c
, c
->loop_cont_block
->index
));
2022 cont_check
->cond
= QPU_COND_ZC
;
2023 cont_check
->sf
= true;
2025 qir_BRANCH(c
, QPU_COND_BRANCH_ANY_ZS
);
2026 qir_link_blocks(c
->cur_block
, c
->loop_cont_block
);
2027 qir_link_blocks(c
->cur_block
, c
->loop_break_block
);
2029 qir_set_emit_block(c
, c
->loop_break_block
);
2031 c
->execute
= c
->undef
;
2033 ntq_activate_execute_for_block(c
);
2035 c
->loop_break_block
= save_loop_break_block
;
2036 c
->loop_cont_block
= save_loop_cont_block
;
2040 ntq_emit_function(struct vc4_compile
*c
, nir_function_impl
*func
)
2042 fprintf(stderr
, "FUNCTIONS not handled.\n");
2047 ntq_emit_cf_list(struct vc4_compile
*c
, struct exec_list
*list
)
2049 foreach_list_typed(nir_cf_node
, node
, node
, list
) {
2050 switch (node
->type
) {
2051 case nir_cf_node_block
:
2052 ntq_emit_block(c
, nir_cf_node_as_block(node
));
2055 case nir_cf_node_if
:
2056 ntq_emit_if(c
, nir_cf_node_as_if(node
));
2059 case nir_cf_node_loop
:
2060 ntq_emit_loop(c
, nir_cf_node_as_loop(node
));
2063 case nir_cf_node_function
:
2064 ntq_emit_function(c
, nir_cf_node_as_function(node
));
2068 fprintf(stderr
, "Unknown NIR node type\n");
2075 ntq_emit_impl(struct vc4_compile
*c
, nir_function_impl
*impl
)
2077 ntq_setup_registers(c
, &impl
->registers
);
2078 ntq_emit_cf_list(c
, &impl
->body
);
2082 nir_to_qir(struct vc4_compile
*c
)
2084 if (c
->stage
== QSTAGE_FRAG
&& c
->s
->info
->fs
.uses_discard
)
2085 c
->discard
= qir_MOV(c
, qir_uniform_ui(c
, 0));
2087 ntq_setup_inputs(c
);
2088 ntq_setup_outputs(c
);
2089 ntq_setup_uniforms(c
);
2090 ntq_setup_registers(c
, &c
->s
->registers
);
2092 /* Find the main function and emit the body. */
2093 nir_foreach_function(function
, c
->s
) {
2094 assert(strcmp(function
->name
, "main") == 0);
2095 assert(function
->impl
);
2096 ntq_emit_impl(c
, function
->impl
);
2100 static const nir_shader_compiler_options nir_options
= {
2101 .lower_extract_byte
= true,
2102 .lower_extract_word
= true,
2104 .lower_flrp32
= true,
2107 .lower_fsqrt
= true,
2108 .lower_negate
= true,
2109 .native_integers
= true,
2113 vc4_screen_get_compiler_options(struct pipe_screen
*pscreen
,
2114 enum pipe_shader_ir ir
, unsigned shader
)
2116 return &nir_options
;
2120 count_nir_instrs(nir_shader
*nir
)
2123 nir_foreach_function(function
, nir
) {
2124 if (!function
->impl
)
2126 nir_foreach_block(block
, function
->impl
) {
2127 nir_foreach_instr(instr
, block
)
2134 static struct vc4_compile
*
2135 vc4_shader_ntq(struct vc4_context
*vc4
, enum qstage stage
,
2136 struct vc4_key
*key
)
2138 struct vc4_compile
*c
= qir_compile_init();
2142 c
->shader_state
= &key
->shader_state
->base
;
2143 c
->program_id
= key
->shader_state
->program_id
;
2145 p_atomic_inc_return(&key
->shader_state
->compiled_variant_count
);
2150 c
->fs_key
= (struct vc4_fs_key
*)key
;
2151 if (c
->fs_key
->is_points
) {
2152 c
->point_x
= emit_fragment_varying(c
, ~0, 0);
2153 c
->point_y
= emit_fragment_varying(c
, ~0, 0);
2154 } else if (c
->fs_key
->is_lines
) {
2155 c
->line_x
= emit_fragment_varying(c
, ~0, 0);
2159 c
->vs_key
= (struct vc4_vs_key
*)key
;
2162 c
->vs_key
= (struct vc4_vs_key
*)key
;
2166 c
->s
= nir_shader_clone(c
, key
->shader_state
->base
.ir
.nir
);
2168 if (stage
== QSTAGE_FRAG
)
2169 NIR_PASS_V(c
->s
, vc4_nir_lower_blend
, c
);
2171 struct nir_lower_tex_options tex_options
= {
2172 /* We would need to implement txs, but we don't want the
2173 * int/float conversions
2175 .lower_rect
= false,
2179 /* Apply swizzles to all samplers. */
2180 .swizzle_result
= ~0,
2183 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2184 * The format swizzling applies before sRGB decode, and
2185 * ARB_texture_swizzle is the last thing before returning the sample.
2187 for (int i
= 0; i
< ARRAY_SIZE(key
->tex
); i
++) {
2188 enum pipe_format format
= c
->key
->tex
[i
].format
;
2193 const uint8_t *format_swizzle
= vc4_get_format_swizzle(format
);
2195 for (int j
= 0; j
< 4; j
++) {
2196 uint8_t arb_swiz
= c
->key
->tex
[i
].swizzle
[j
];
2198 if (arb_swiz
<= 3) {
2199 tex_options
.swizzles
[i
][j
] =
2200 format_swizzle
[arb_swiz
];
2202 tex_options
.swizzles
[i
][j
] = arb_swiz
;
2206 if (util_format_is_srgb(format
))
2207 tex_options
.lower_srgb
|= (1 << i
);
2210 NIR_PASS_V(c
->s
, nir_lower_tex
, &tex_options
);
2212 if (c
->fs_key
&& c
->fs_key
->light_twoside
)
2213 NIR_PASS_V(c
->s
, nir_lower_two_sided_color
);
2215 if (c
->vs_key
&& c
->vs_key
->clamp_color
)
2216 NIR_PASS_V(c
->s
, nir_lower_clamp_color_outputs
);
2218 if (c
->key
->ucp_enables
) {
2219 if (stage
== QSTAGE_FRAG
) {
2220 NIR_PASS_V(c
->s
, nir_lower_clip_fs
, c
->key
->ucp_enables
);
2222 NIR_PASS_V(c
->s
, nir_lower_clip_vs
, c
->key
->ucp_enables
);
2223 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
,
2224 nir_var_shader_out
);
2228 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2229 * which only handles a vec4 at a time. Similarly, VS output
2230 * scalarizing must happen after nir_lower_clip_vs.
2232 if (c
->stage
== QSTAGE_FRAG
)
2233 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_in
);
2235 NIR_PASS_V(c
->s
, nir_lower_io_to_scalar
, nir_var_shader_out
);
2237 NIR_PASS_V(c
->s
, vc4_nir_lower_io
, c
);
2238 NIR_PASS_V(c
->s
, vc4_nir_lower_txf_ms
, c
);
2239 NIR_PASS_V(c
->s
, nir_lower_idiv
);
2241 vc4_optimize_nir(c
->s
);
2243 NIR_PASS_V(c
->s
, nir_convert_from_ssa
, true);
2245 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2246 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2247 qir_get_stage_name(c
->stage
),
2248 c
->program_id
, c
->variant_id
,
2249 count_nir_instrs(c
->s
));
2252 if (vc4_debug
& VC4_DEBUG_NIR
) {
2253 fprintf(stderr
, "%s prog %d/%d NIR:\n",
2254 qir_get_stage_name(c
->stage
),
2255 c
->program_id
, c
->variant_id
);
2256 nir_print_shader(c
->s
, stderr
);
2267 c
->vs_key
->fs_inputs
->input_slots
,
2268 c
->vs_key
->fs_inputs
->num_inputs
);
2275 if (vc4_debug
& VC4_DEBUG_QIR
) {
2276 fprintf(stderr
, "%s prog %d/%d pre-opt QIR:\n",
2277 qir_get_stage_name(c
->stage
),
2278 c
->program_id
, c
->variant_id
);
2280 fprintf(stderr
, "\n");
2284 qir_lower_uniforms(c
);
2286 qir_schedule_instructions(c
);
2287 qir_emit_uniform_stream_resets(c
);
2289 if (vc4_debug
& VC4_DEBUG_QIR
) {
2290 fprintf(stderr
, "%s prog %d/%d QIR:\n",
2291 qir_get_stage_name(c
->stage
),
2292 c
->program_id
, c
->variant_id
);
2294 fprintf(stderr
, "\n");
2297 qir_reorder_uniforms(c
);
2298 vc4_generate_code(vc4
, c
);
2300 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2301 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2302 qir_get_stage_name(c
->stage
),
2303 c
->program_id
, c
->variant_id
,
2305 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2306 qir_get_stage_name(c
->stage
),
2307 c
->program_id
, c
->variant_id
,
2317 vc4_shader_state_create(struct pipe_context
*pctx
,
2318 const struct pipe_shader_state
*cso
)
2320 struct vc4_context
*vc4
= vc4_context(pctx
);
2321 struct vc4_uncompiled_shader
*so
= CALLOC_STRUCT(vc4_uncompiled_shader
);
2325 so
->program_id
= vc4
->next_uncompiled_program_id
++;
2329 if (cso
->type
== PIPE_SHADER_IR_NIR
) {
2330 /* The backend takes ownership of the NIR shader on state
2335 assert(cso
->type
== PIPE_SHADER_IR_TGSI
);
2337 if (vc4_debug
& VC4_DEBUG_TGSI
) {
2338 fprintf(stderr
, "prog %d TGSI:\n",
2340 tgsi_dump(cso
->tokens
, 0);
2341 fprintf(stderr
, "\n");
2343 s
= tgsi_to_nir(cso
->tokens
, &nir_options
);
2346 NIR_PASS_V(s
, nir_opt_global_to_local
);
2347 NIR_PASS_V(s
, nir_convert_to_ssa
);
2348 NIR_PASS_V(s
, nir_normalize_cubemap_coords
);
2350 NIR_PASS_V(s
, nir_lower_load_const_to_scalar
);
2352 vc4_optimize_nir(s
);
2354 NIR_PASS_V(s
, nir_remove_dead_variables
, nir_var_local
);
2356 /* Garbage collect dead instructions */
2359 so
->base
.type
= PIPE_SHADER_IR_NIR
;
2360 so
->base
.ir
.nir
= s
;
2362 if (vc4_debug
& VC4_DEBUG_NIR
) {
2363 fprintf(stderr
, "%s prog %d NIR:\n",
2364 gl_shader_stage_name(s
->stage
),
2366 nir_print_shader(s
, stderr
);
2367 fprintf(stderr
, "\n");
2374 copy_uniform_state_to_shader(struct vc4_compiled_shader
*shader
,
2375 struct vc4_compile
*c
)
2377 int count
= c
->num_uniforms
;
2378 struct vc4_shader_uniform_info
*uinfo
= &shader
->uniforms
;
2380 uinfo
->count
= count
;
2381 uinfo
->data
= ralloc_array(shader
, uint32_t, count
);
2382 memcpy(uinfo
->data
, c
->uniform_data
,
2383 count
* sizeof(*uinfo
->data
));
2384 uinfo
->contents
= ralloc_array(shader
, enum quniform_contents
, count
);
2385 memcpy(uinfo
->contents
, c
->uniform_contents
,
2386 count
* sizeof(*uinfo
->contents
));
2387 uinfo
->num_texture_samples
= c
->num_texture_samples
;
2389 vc4_set_shader_uniform_dirty_flags(shader
);
2393 vc4_setup_compiled_fs_inputs(struct vc4_context
*vc4
, struct vc4_compile
*c
,
2394 struct vc4_compiled_shader
*shader
)
2396 struct vc4_fs_inputs inputs
;
2398 memset(&inputs
, 0, sizeof(inputs
));
2399 inputs
.input_slots
= ralloc_array(shader
,
2400 struct vc4_varying_slot
,
2401 c
->num_input_slots
);
2403 bool input_live
[c
->num_input_slots
];
2405 memset(input_live
, 0, sizeof(input_live
));
2406 qir_for_each_inst_inorder(inst
, c
) {
2407 for (int i
= 0; i
< qir_get_op_nsrc(inst
->op
); i
++) {
2408 if (inst
->src
[i
].file
== QFILE_VARY
)
2409 input_live
[inst
->src
[i
].index
] = true;
2413 for (int i
= 0; i
< c
->num_input_slots
; i
++) {
2414 struct vc4_varying_slot
*slot
= &c
->input_slots
[i
];
2419 /* Skip non-VS-output inputs. */
2420 if (slot
->slot
== (uint8_t)~0)
2423 if (slot
->slot
== VARYING_SLOT_COL0
||
2424 slot
->slot
== VARYING_SLOT_COL1
||
2425 slot
->slot
== VARYING_SLOT_BFC0
||
2426 slot
->slot
== VARYING_SLOT_BFC1
) {
2427 shader
->color_inputs
|= (1 << inputs
.num_inputs
);
2430 inputs
.input_slots
[inputs
.num_inputs
] = *slot
;
2431 inputs
.num_inputs
++;
2433 shader
->num_inputs
= inputs
.num_inputs
;
2435 /* Add our set of inputs to the set of all inputs seen. This way, we
2436 * can have a single pointer that identifies an FS inputs set,
2437 * allowing VS to avoid recompiling when the FS is recompiled (or a
2438 * new one is bound using separate shader objects) but the inputs
2441 struct set_entry
*entry
= _mesa_set_search(vc4
->fs_inputs_set
, &inputs
);
2443 shader
->fs_inputs
= entry
->key
;
2444 ralloc_free(inputs
.input_slots
);
2446 struct vc4_fs_inputs
*alloc_inputs
;
2448 alloc_inputs
= rzalloc(vc4
->fs_inputs_set
, struct vc4_fs_inputs
);
2449 memcpy(alloc_inputs
, &inputs
, sizeof(inputs
));
2450 ralloc_steal(alloc_inputs
, inputs
.input_slots
);
2451 _mesa_set_add(vc4
->fs_inputs_set
, alloc_inputs
);
2453 shader
->fs_inputs
= alloc_inputs
;
2457 static struct vc4_compiled_shader
*
2458 vc4_get_compiled_shader(struct vc4_context
*vc4
, enum qstage stage
,
2459 struct vc4_key
*key
)
2461 struct hash_table
*ht
;
2463 if (stage
== QSTAGE_FRAG
) {
2465 key_size
= sizeof(struct vc4_fs_key
);
2468 key_size
= sizeof(struct vc4_vs_key
);
2471 struct vc4_compiled_shader
*shader
;
2472 struct hash_entry
*entry
= _mesa_hash_table_search(ht
, key
);
2476 struct vc4_compile
*c
= vc4_shader_ntq(vc4
, stage
, key
);
2477 shader
= rzalloc(NULL
, struct vc4_compiled_shader
);
2479 shader
->program_id
= vc4
->next_compiled_program_id
++;
2480 if (stage
== QSTAGE_FRAG
) {
2481 vc4_setup_compiled_fs_inputs(vc4
, c
, shader
);
2483 /* Note: the temporary clone in c->s has been freed. */
2484 nir_shader
*orig_shader
= key
->shader_state
->base
.ir
.nir
;
2485 if (orig_shader
->info
->outputs_written
& (1 << FRAG_RESULT_DEPTH
))
2486 shader
->disable_early_z
= true;
2488 shader
->num_inputs
= c
->num_inputs
;
2490 shader
->vattr_offsets
[0] = 0;
2491 for (int i
= 0; i
< 8; i
++) {
2492 shader
->vattr_offsets
[i
+ 1] =
2493 shader
->vattr_offsets
[i
] + c
->vattr_sizes
[i
];
2495 if (c
->vattr_sizes
[i
])
2496 shader
->vattrs_live
|= (1 << i
);
2500 shader
->failed
= c
->failed
;
2502 shader
->failed
= true;
2504 copy_uniform_state_to_shader(shader
, c
);
2505 shader
->bo
= vc4_bo_alloc_shader(vc4
->screen
, c
->qpu_insts
,
2510 /* Copy the compiler UBO range state to the compiled shader, dropping
2511 * out arrays that were never referenced by an indirect load.
2513 * (Note that QIR dead code elimination of an array access still
2514 * leaves that array alive, though)
2516 if (c
->num_ubo_ranges
) {
2517 shader
->num_ubo_ranges
= c
->num_ubo_ranges
;
2518 shader
->ubo_ranges
= ralloc_array(shader
, struct vc4_ubo_range
,
2521 for (int i
= 0; i
< c
->num_uniform_ranges
; i
++) {
2522 struct vc4_compiler_ubo_range
*range
=
2527 shader
->ubo_ranges
[j
].dst_offset
= range
->dst_offset
;
2528 shader
->ubo_ranges
[j
].src_offset
= range
->src_offset
;
2529 shader
->ubo_ranges
[j
].size
= range
->size
;
2530 shader
->ubo_size
+= c
->ubo_ranges
[i
].size
;
2534 if (shader
->ubo_size
) {
2535 if (vc4_debug
& VC4_DEBUG_SHADERDB
) {
2536 fprintf(stderr
, "SHADER-DB: %s prog %d/%d: %d UBO uniforms\n",
2537 qir_get_stage_name(c
->stage
),
2538 c
->program_id
, c
->variant_id
,
2539 shader
->ubo_size
/ 4);
2543 qir_compile_destroy(c
);
2545 struct vc4_key
*dup_key
;
2546 dup_key
= rzalloc_size(shader
, key_size
); /* TODO: don't use rzalloc */
2547 memcpy(dup_key
, key
, key_size
);
2548 _mesa_hash_table_insert(ht
, dup_key
, shader
);
2554 vc4_setup_shared_key(struct vc4_context
*vc4
, struct vc4_key
*key
,
2555 struct vc4_texture_stateobj
*texstate
)
2557 for (int i
= 0; i
< texstate
->num_textures
; i
++) {
2558 struct pipe_sampler_view
*sampler
= texstate
->textures
[i
];
2559 struct vc4_sampler_view
*vc4_sampler
= vc4_sampler_view(sampler
);
2560 struct pipe_sampler_state
*sampler_state
=
2561 texstate
->samplers
[i
];
2566 key
->tex
[i
].format
= sampler
->format
;
2567 key
->tex
[i
].swizzle
[0] = sampler
->swizzle_r
;
2568 key
->tex
[i
].swizzle
[1] = sampler
->swizzle_g
;
2569 key
->tex
[i
].swizzle
[2] = sampler
->swizzle_b
;
2570 key
->tex
[i
].swizzle
[3] = sampler
->swizzle_a
;
2572 if (sampler
->texture
->nr_samples
> 1) {
2573 key
->tex
[i
].msaa_width
= sampler
->texture
->width0
;
2574 key
->tex
[i
].msaa_height
= sampler
->texture
->height0
;
2575 } else if (sampler
){
2576 key
->tex
[i
].compare_mode
= sampler_state
->compare_mode
;
2577 key
->tex
[i
].compare_func
= sampler_state
->compare_func
;
2578 key
->tex
[i
].wrap_s
= sampler_state
->wrap_s
;
2579 key
->tex
[i
].wrap_t
= sampler_state
->wrap_t
;
2580 key
->tex
[i
].force_first_level
=
2581 vc4_sampler
->force_first_level
;
2585 key
->ucp_enables
= vc4
->rasterizer
->base
.clip_plane_enable
;
2589 vc4_update_compiled_fs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2591 struct vc4_job
*job
= vc4
->job
;
2592 struct vc4_fs_key local_key
;
2593 struct vc4_fs_key
*key
= &local_key
;
2595 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2597 VC4_DIRTY_FRAMEBUFFER
|
2599 VC4_DIRTY_RASTERIZER
|
2600 VC4_DIRTY_SAMPLE_MASK
|
2602 VC4_DIRTY_UNCOMPILED_FS
))) {
2606 memset(key
, 0, sizeof(*key
));
2607 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->fragtex
);
2608 key
->base
.shader_state
= vc4
->prog
.bind_fs
;
2609 key
->is_points
= (prim_mode
== PIPE_PRIM_POINTS
);
2610 key
->is_lines
= (prim_mode
>= PIPE_PRIM_LINES
&&
2611 prim_mode
<= PIPE_PRIM_LINE_STRIP
);
2612 key
->blend
= vc4
->blend
->rt
[0];
2613 if (vc4
->blend
->logicop_enable
) {
2614 key
->logicop_func
= vc4
->blend
->logicop_func
;
2616 key
->logicop_func
= PIPE_LOGICOP_COPY
;
2619 key
->msaa
= vc4
->rasterizer
->base
.multisample
;
2620 key
->sample_coverage
= (vc4
->rasterizer
->base
.multisample
&&
2621 vc4
->sample_mask
!= (1 << VC4_MAX_SAMPLES
) - 1);
2622 key
->sample_alpha_to_coverage
= vc4
->blend
->alpha_to_coverage
;
2623 key
->sample_alpha_to_one
= vc4
->blend
->alpha_to_one
;
2626 if (vc4
->framebuffer
.cbufs
[0])
2627 key
->color_format
= vc4
->framebuffer
.cbufs
[0]->format
;
2629 key
->stencil_enabled
= vc4
->zsa
->stencil_uniforms
[0] != 0;
2630 key
->stencil_twoside
= vc4
->zsa
->stencil_uniforms
[1] != 0;
2631 key
->stencil_full_writemasks
= vc4
->zsa
->stencil_uniforms
[2] != 0;
2632 key
->depth_enabled
= (vc4
->zsa
->base
.depth
.enabled
||
2633 key
->stencil_enabled
);
2634 if (vc4
->zsa
->base
.alpha
.enabled
) {
2635 key
->alpha_test
= true;
2636 key
->alpha_test_func
= vc4
->zsa
->base
.alpha
.func
;
2639 if (key
->is_points
) {
2640 key
->point_sprite_mask
=
2641 vc4
->rasterizer
->base
.sprite_coord_enable
;
2642 key
->point_coord_upper_left
=
2643 (vc4
->rasterizer
->base
.sprite_coord_mode
==
2644 PIPE_SPRITE_COORD_UPPER_LEFT
);
2647 key
->light_twoside
= vc4
->rasterizer
->base
.light_twoside
;
2649 struct vc4_compiled_shader
*old_fs
= vc4
->prog
.fs
;
2650 vc4
->prog
.fs
= vc4_get_compiled_shader(vc4
, QSTAGE_FRAG
, &key
->base
);
2651 if (vc4
->prog
.fs
== old_fs
)
2654 vc4
->dirty
|= VC4_DIRTY_COMPILED_FS
;
2656 if (vc4
->rasterizer
->base
.flatshade
&&
2657 old_fs
&& vc4
->prog
.fs
->color_inputs
!= old_fs
->color_inputs
) {
2658 vc4
->dirty
|= VC4_DIRTY_FLAT_SHADE_FLAGS
;
2661 if (old_fs
&& vc4
->prog
.fs
->fs_inputs
!= old_fs
->fs_inputs
)
2662 vc4
->dirty
|= VC4_DIRTY_FS_INPUTS
;
2666 vc4_update_compiled_vs(struct vc4_context
*vc4
, uint8_t prim_mode
)
2668 struct vc4_vs_key local_key
;
2669 struct vc4_vs_key
*key
= &local_key
;
2671 if (!(vc4
->dirty
& (VC4_DIRTY_PRIM_MODE
|
2672 VC4_DIRTY_RASTERIZER
|
2674 VC4_DIRTY_VTXSTATE
|
2675 VC4_DIRTY_UNCOMPILED_VS
|
2676 VC4_DIRTY_FS_INPUTS
))) {
2680 memset(key
, 0, sizeof(*key
));
2681 vc4_setup_shared_key(vc4
, &key
->base
, &vc4
->verttex
);
2682 key
->base
.shader_state
= vc4
->prog
.bind_vs
;
2683 key
->fs_inputs
= vc4
->prog
.fs
->fs_inputs
;
2684 key
->clamp_color
= vc4
->rasterizer
->base
.clamp_vertex_color
;
2686 for (int i
= 0; i
< ARRAY_SIZE(key
->attr_formats
); i
++)
2687 key
->attr_formats
[i
] = vc4
->vtx
->pipe
[i
].src_format
;
2689 key
->per_vertex_point_size
=
2690 (prim_mode
== PIPE_PRIM_POINTS
&&
2691 vc4
->rasterizer
->base
.point_size_per_vertex
);
2693 struct vc4_compiled_shader
*vs
=
2694 vc4_get_compiled_shader(vc4
, QSTAGE_VERT
, &key
->base
);
2695 if (vs
!= vc4
->prog
.vs
) {
2697 vc4
->dirty
|= VC4_DIRTY_COMPILED_VS
;
2700 key
->is_coord
= true;
2701 /* Coord shaders don't care what the FS inputs are. */
2702 key
->fs_inputs
= NULL
;
2703 struct vc4_compiled_shader
*cs
=
2704 vc4_get_compiled_shader(vc4
, QSTAGE_COORD
, &key
->base
);
2705 if (cs
!= vc4
->prog
.cs
) {
2707 vc4
->dirty
|= VC4_DIRTY_COMPILED_CS
;
2712 vc4_update_compiled_shaders(struct vc4_context
*vc4
, uint8_t prim_mode
)
2714 vc4_update_compiled_fs(vc4
, prim_mode
);
2715 vc4_update_compiled_vs(vc4
, prim_mode
);
2717 return !(vc4
->prog
.cs
->failed
||
2718 vc4
->prog
.vs
->failed
||
2719 vc4
->prog
.fs
->failed
);
2723 fs_cache_hash(const void *key
)
2725 return _mesa_hash_data(key
, sizeof(struct vc4_fs_key
));
2729 vs_cache_hash(const void *key
)
2731 return _mesa_hash_data(key
, sizeof(struct vc4_vs_key
));
2735 fs_cache_compare(const void *key1
, const void *key2
)
2737 return memcmp(key1
, key2
, sizeof(struct vc4_fs_key
)) == 0;
2741 vs_cache_compare(const void *key1
, const void *key2
)
2743 return memcmp(key1
, key2
, sizeof(struct vc4_vs_key
)) == 0;
2747 fs_inputs_hash(const void *key
)
2749 const struct vc4_fs_inputs
*inputs
= key
;
2751 return _mesa_hash_data(inputs
->input_slots
,
2752 sizeof(*inputs
->input_slots
) *
2753 inputs
->num_inputs
);
2757 fs_inputs_compare(const void *key1
, const void *key2
)
2759 const struct vc4_fs_inputs
*inputs1
= key1
;
2760 const struct vc4_fs_inputs
*inputs2
= key2
;
2762 return (inputs1
->num_inputs
== inputs2
->num_inputs
&&
2763 memcmp(inputs1
->input_slots
,
2764 inputs2
->input_slots
,
2765 sizeof(*inputs1
->input_slots
) *
2766 inputs1
->num_inputs
) == 0);
2770 delete_from_cache_if_matches(struct hash_table
*ht
,
2771 struct hash_entry
*entry
,
2772 struct vc4_uncompiled_shader
*so
)
2774 const struct vc4_key
*key
= entry
->key
;
2776 if (key
->shader_state
== so
) {
2777 struct vc4_compiled_shader
*shader
= entry
->data
;
2778 _mesa_hash_table_remove(ht
, entry
);
2779 vc4_bo_unreference(&shader
->bo
);
2780 ralloc_free(shader
);
2785 vc4_shader_state_delete(struct pipe_context
*pctx
, void *hwcso
)
2787 struct vc4_context
*vc4
= vc4_context(pctx
);
2788 struct vc4_uncompiled_shader
*so
= hwcso
;
2790 struct hash_entry
*entry
;
2791 hash_table_foreach(vc4
->fs_cache
, entry
)
2792 delete_from_cache_if_matches(vc4
->fs_cache
, entry
, so
);
2793 hash_table_foreach(vc4
->vs_cache
, entry
)
2794 delete_from_cache_if_matches(vc4
->vs_cache
, entry
, so
);
2796 ralloc_free(so
->base
.ir
.nir
);
2801 vc4_fp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2803 struct vc4_context
*vc4
= vc4_context(pctx
);
2804 vc4
->prog
.bind_fs
= hwcso
;
2805 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_FS
;
2809 vc4_vp_state_bind(struct pipe_context
*pctx
, void *hwcso
)
2811 struct vc4_context
*vc4
= vc4_context(pctx
);
2812 vc4
->prog
.bind_vs
= hwcso
;
2813 vc4
->dirty
|= VC4_DIRTY_UNCOMPILED_VS
;
2817 vc4_program_init(struct pipe_context
*pctx
)
2819 struct vc4_context
*vc4
= vc4_context(pctx
);
2821 pctx
->create_vs_state
= vc4_shader_state_create
;
2822 pctx
->delete_vs_state
= vc4_shader_state_delete
;
2824 pctx
->create_fs_state
= vc4_shader_state_create
;
2825 pctx
->delete_fs_state
= vc4_shader_state_delete
;
2827 pctx
->bind_fs_state
= vc4_fp_state_bind
;
2828 pctx
->bind_vs_state
= vc4_vp_state_bind
;
2830 vc4
->fs_cache
= _mesa_hash_table_create(pctx
, fs_cache_hash
,
2832 vc4
->vs_cache
= _mesa_hash_table_create(pctx
, vs_cache_hash
,
2834 vc4
->fs_inputs_set
= _mesa_set_create(pctx
, fs_inputs_hash
,
2839 vc4_program_fini(struct pipe_context
*pctx
)
2841 struct vc4_context
*vc4
= vc4_context(pctx
);
2843 struct hash_entry
*entry
;
2844 hash_table_foreach(vc4
->fs_cache
, entry
) {
2845 struct vc4_compiled_shader
*shader
= entry
->data
;
2846 vc4_bo_unreference(&shader
->bo
);
2847 ralloc_free(shader
);
2848 _mesa_hash_table_remove(vc4
->fs_cache
, entry
);
2851 hash_table_foreach(vc4
->vs_cache
, entry
) {
2852 struct vc4_compiled_shader
*shader
= entry
->data
;
2853 vc4_bo_unreference(&shader
->bo
);
2854 ralloc_free(shader
);
2855 _mesa_hash_table_remove(vc4
->vs_cache
, entry
);