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nir: Add lower_rotate flag and set to true in all drivers
[mesa.git] / src / gallium / drivers / vc4 / vc4_program.c
1 /*
2 * Copyright (c) 2014 Scott Mansell
3 * Copyright © 2014 Broadcom
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
22 * IN THE SOFTWARE.
23 */
24
25 #include <inttypes.h>
26 #include "util/u_format.h"
27 #include "util/crc32.h"
28 #include "util/u_math.h"
29 #include "util/u_memory.h"
30 #include "util/ralloc.h"
31 #include "util/hash_table.h"
32 #include "tgsi/tgsi_dump.h"
33 #include "tgsi/tgsi_parse.h"
34 #include "compiler/nir/nir.h"
35 #include "compiler/nir/nir_builder.h"
36 #include "compiler/nir_types.h"
37 #include "nir/tgsi_to_nir.h"
38 #include "vc4_context.h"
39 #include "vc4_qpu.h"
40 #include "vc4_qir.h"
41
42 static struct qreg
43 ntq_get_src(struct vc4_compile *c, nir_src src, int i);
44 static void
45 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
46
47 static int
48 type_size(const struct glsl_type *type, bool bindless)
49 {
50 return glsl_count_attribute_slots(type, false);
51 }
52
53 static void
54 resize_qreg_array(struct vc4_compile *c,
55 struct qreg **regs,
56 uint32_t *size,
57 uint32_t decl_size)
58 {
59 if (*size >= decl_size)
60 return;
61
62 uint32_t old_size = *size;
63 *size = MAX2(*size * 2, decl_size);
64 *regs = reralloc(c, *regs, struct qreg, *size);
65 if (!*regs) {
66 fprintf(stderr, "Malloc failure\n");
67 abort();
68 }
69
70 for (uint32_t i = old_size; i < *size; i++)
71 (*regs)[i] = c->undef;
72 }
73
74 static void
75 ntq_emit_thrsw(struct vc4_compile *c)
76 {
77 if (!c->fs_threaded)
78 return;
79
80 /* Always thread switch after each texture operation for now.
81 *
82 * We could do better by batching a bunch of texture fetches up and
83 * then doing one thread switch and collecting all their results
84 * afterward.
85 */
86 qir_emit_nondef(c, qir_inst(QOP_THRSW, c->undef,
87 c->undef, c->undef));
88 c->last_thrsw_at_top_level = (c->execute.file == QFILE_NULL);
89 }
90
91 static struct qreg
92 indirect_uniform_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
93 {
94 struct qreg indirect_offset = ntq_get_src(c, intr->src[0], 0);
95
96 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
97 uint32_t range = nir_intrinsic_range(intr);
98 indirect_offset = qir_MAX(c, indirect_offset, qir_uniform_ui(c, 0));
99 indirect_offset = qir_MIN_NOIMM(c, indirect_offset,
100 qir_uniform_ui(c, range - 4));
101
102 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
103 indirect_offset,
104 qir_uniform(c, QUNIFORM_UBO0_ADDR,
105 nir_intrinsic_base(intr)));
106
107 c->num_texture_samples++;
108
109 ntq_emit_thrsw(c);
110
111 return qir_TEX_RESULT(c);
112 }
113
114 static struct qreg
115 vc4_ubo_load(struct vc4_compile *c, nir_intrinsic_instr *intr)
116 {
117 int buffer_index = nir_src_as_uint(intr->src[0]);
118 assert(buffer_index == 1);
119 assert(c->stage == QSTAGE_FRAG);
120
121 struct qreg offset = ntq_get_src(c, intr->src[1], 0);
122
123 /* Clamp to [0, array size). Note that MIN/MAX are signed. */
124 offset = qir_MAX(c, offset, qir_uniform_ui(c, 0));
125 offset = qir_MIN_NOIMM(c, offset,
126 qir_uniform_ui(c, c->fs_key->ubo_1_size - 4));
127
128 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
129 offset,
130 qir_uniform(c, QUNIFORM_UBO1_ADDR, 0));
131
132 c->num_texture_samples++;
133
134 ntq_emit_thrsw(c);
135
136 return qir_TEX_RESULT(c);
137 }
138
139 nir_ssa_def *
140 vc4_nir_get_swizzled_channel(nir_builder *b, nir_ssa_def **srcs, int swiz)
141 {
142 switch (swiz) {
143 default:
144 case PIPE_SWIZZLE_NONE:
145 fprintf(stderr, "warning: unknown swizzle\n");
146 /* FALLTHROUGH */
147 case PIPE_SWIZZLE_0:
148 return nir_imm_float(b, 0.0);
149 case PIPE_SWIZZLE_1:
150 return nir_imm_float(b, 1.0);
151 case PIPE_SWIZZLE_X:
152 case PIPE_SWIZZLE_Y:
153 case PIPE_SWIZZLE_Z:
154 case PIPE_SWIZZLE_W:
155 return srcs[swiz];
156 }
157 }
158
159 static struct qreg *
160 ntq_init_ssa_def(struct vc4_compile *c, nir_ssa_def *def)
161 {
162 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
163 def->num_components);
164 _mesa_hash_table_insert(c->def_ht, def, qregs);
165 return qregs;
166 }
167
168 /**
169 * This function is responsible for getting QIR results into the associated
170 * storage for a NIR instruction.
171 *
172 * If it's a NIR SSA def, then we just set the associated hash table entry to
173 * the new result.
174 *
175 * If it's a NIR reg, then we need to update the existing qreg assigned to the
176 * NIR destination with the incoming value. To do that without introducing
177 * new MOVs, we require that the incoming qreg either be a uniform, or be
178 * SSA-defined by the previous QIR instruction in the block and rewritable by
179 * this function. That lets us sneak ahead and insert the SF flag beforehand
180 * (knowing that the previous instruction doesn't depend on flags) and rewrite
181 * its destination to be the NIR reg's destination
182 */
183 static void
184 ntq_store_dest(struct vc4_compile *c, nir_dest *dest, int chan,
185 struct qreg result)
186 {
187 struct qinst *last_inst = NULL;
188 if (!list_empty(&c->cur_block->instructions))
189 last_inst = (struct qinst *)c->cur_block->instructions.prev;
190
191 assert(result.file == QFILE_UNIF ||
192 (result.file == QFILE_TEMP &&
193 last_inst && last_inst == c->defs[result.index]));
194
195 if (dest->is_ssa) {
196 assert(chan < dest->ssa.num_components);
197
198 struct qreg *qregs;
199 struct hash_entry *entry =
200 _mesa_hash_table_search(c->def_ht, &dest->ssa);
201
202 if (entry)
203 qregs = entry->data;
204 else
205 qregs = ntq_init_ssa_def(c, &dest->ssa);
206
207 qregs[chan] = result;
208 } else {
209 nir_register *reg = dest->reg.reg;
210 assert(dest->reg.base_offset == 0);
211 assert(reg->num_array_elems == 0);
212 struct hash_entry *entry =
213 _mesa_hash_table_search(c->def_ht, reg);
214 struct qreg *qregs = entry->data;
215
216 /* Insert a MOV if the source wasn't an SSA def in the
217 * previous instruction.
218 */
219 if (result.file == QFILE_UNIF) {
220 result = qir_MOV(c, result);
221 last_inst = c->defs[result.index];
222 }
223
224 /* We know they're both temps, so just rewrite index. */
225 c->defs[last_inst->dst.index] = NULL;
226 last_inst->dst.index = qregs[chan].index;
227
228 /* If we're in control flow, then make this update of the reg
229 * conditional on the execution mask.
230 */
231 if (c->execute.file != QFILE_NULL) {
232 last_inst->dst.index = qregs[chan].index;
233
234 /* Set the flags to the current exec mask. To insert
235 * the SF, we temporarily remove our SSA instruction.
236 */
237 list_del(&last_inst->link);
238 qir_SF(c, c->execute);
239 list_addtail(&last_inst->link,
240 &c->cur_block->instructions);
241
242 last_inst->cond = QPU_COND_ZS;
243 last_inst->cond_is_exec_mask = true;
244 }
245 }
246 }
247
248 static struct qreg *
249 ntq_get_dest(struct vc4_compile *c, nir_dest *dest)
250 {
251 if (dest->is_ssa) {
252 struct qreg *qregs = ntq_init_ssa_def(c, &dest->ssa);
253 for (int i = 0; i < dest->ssa.num_components; i++)
254 qregs[i] = c->undef;
255 return qregs;
256 } else {
257 nir_register *reg = dest->reg.reg;
258 assert(dest->reg.base_offset == 0);
259 assert(reg->num_array_elems == 0);
260 struct hash_entry *entry =
261 _mesa_hash_table_search(c->def_ht, reg);
262 return entry->data;
263 }
264 }
265
266 static struct qreg
267 ntq_get_src(struct vc4_compile *c, nir_src src, int i)
268 {
269 struct hash_entry *entry;
270 if (src.is_ssa) {
271 entry = _mesa_hash_table_search(c->def_ht, src.ssa);
272 assert(i < src.ssa->num_components);
273 } else {
274 nir_register *reg = src.reg.reg;
275 entry = _mesa_hash_table_search(c->def_ht, reg);
276 assert(reg->num_array_elems == 0);
277 assert(src.reg.base_offset == 0);
278 assert(i < reg->num_components);
279 }
280
281 struct qreg *qregs = entry->data;
282 return qregs[i];
283 }
284
285 static struct qreg
286 ntq_get_alu_src(struct vc4_compile *c, nir_alu_instr *instr,
287 unsigned src)
288 {
289 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
290 unsigned chan = ffs(instr->dest.write_mask) - 1;
291 struct qreg r = ntq_get_src(c, instr->src[src].src,
292 instr->src[src].swizzle[chan]);
293
294 assert(!instr->src[src].abs);
295 assert(!instr->src[src].negate);
296
297 return r;
298 };
299
300 static inline struct qreg
301 qir_SAT(struct vc4_compile *c, struct qreg val)
302 {
303 return qir_FMAX(c,
304 qir_FMIN(c, val, qir_uniform_f(c, 1.0)),
305 qir_uniform_f(c, 0.0));
306 }
307
308 static struct qreg
309 ntq_rcp(struct vc4_compile *c, struct qreg x)
310 {
311 struct qreg r = qir_RCP(c, x);
312
313 /* Apply a Newton-Raphson step to improve the accuracy. */
314 r = qir_FMUL(c, r, qir_FSUB(c,
315 qir_uniform_f(c, 2.0),
316 qir_FMUL(c, x, r)));
317
318 return r;
319 }
320
321 static struct qreg
322 ntq_rsq(struct vc4_compile *c, struct qreg x)
323 {
324 struct qreg r = qir_RSQ(c, x);
325
326 /* Apply a Newton-Raphson step to improve the accuracy. */
327 r = qir_FMUL(c, r, qir_FSUB(c,
328 qir_uniform_f(c, 1.5),
329 qir_FMUL(c,
330 qir_uniform_f(c, 0.5),
331 qir_FMUL(c, x,
332 qir_FMUL(c, r, r)))));
333
334 return r;
335 }
336
337 static struct qreg
338 ntq_umul(struct vc4_compile *c, struct qreg src0, struct qreg src1)
339 {
340 struct qreg src0_hi = qir_SHR(c, src0,
341 qir_uniform_ui(c, 24));
342 struct qreg src1_hi = qir_SHR(c, src1,
343 qir_uniform_ui(c, 24));
344
345 struct qreg hilo = qir_MUL24(c, src0_hi, src1);
346 struct qreg lohi = qir_MUL24(c, src0, src1_hi);
347 struct qreg lolo = qir_MUL24(c, src0, src1);
348
349 return qir_ADD(c, lolo, qir_SHL(c,
350 qir_ADD(c, hilo, lohi),
351 qir_uniform_ui(c, 24)));
352 }
353
354 static struct qreg
355 ntq_scale_depth_texture(struct vc4_compile *c, struct qreg src)
356 {
357 struct qreg depthf = qir_ITOF(c, qir_SHR(c, src,
358 qir_uniform_ui(c, 8)));
359 return qir_FMUL(c, depthf, qir_uniform_f(c, 1.0f/0xffffff));
360 }
361
362 /**
363 * Emits a lowered TXF_MS from an MSAA texture.
364 *
365 * The addressing math has been lowered in NIR, and now we just need to read
366 * it like a UBO.
367 */
368 static void
369 ntq_emit_txf(struct vc4_compile *c, nir_tex_instr *instr)
370 {
371 uint32_t tile_width = 32;
372 uint32_t tile_height = 32;
373 uint32_t tile_size = (tile_height * tile_width *
374 VC4_MAX_SAMPLES * sizeof(uint32_t));
375
376 unsigned unit = instr->texture_index;
377 uint32_t w = align(c->key->tex[unit].msaa_width, tile_width);
378 uint32_t w_tiles = w / tile_width;
379 uint32_t h = align(c->key->tex[unit].msaa_height, tile_height);
380 uint32_t h_tiles = h / tile_height;
381 uint32_t size = w_tiles * h_tiles * tile_size;
382
383 struct qreg addr;
384 assert(instr->num_srcs == 1);
385 assert(instr->src[0].src_type == nir_tex_src_coord);
386 addr = ntq_get_src(c, instr->src[0].src, 0);
387
388 /* Perform the clamping required by kernel validation. */
389 addr = qir_MAX(c, addr, qir_uniform_ui(c, 0));
390 addr = qir_MIN_NOIMM(c, addr, qir_uniform_ui(c, size - 4));
391
392 qir_ADD_dest(c, qir_reg(QFILE_TEX_S_DIRECT, 0),
393 addr, qir_uniform(c, QUNIFORM_TEXTURE_MSAA_ADDR, unit));
394
395 ntq_emit_thrsw(c);
396
397 struct qreg tex = qir_TEX_RESULT(c);
398 c->num_texture_samples++;
399
400 enum pipe_format format = c->key->tex[unit].format;
401 if (util_format_is_depth_or_stencil(format)) {
402 struct qreg scaled = ntq_scale_depth_texture(c, tex);
403 for (int i = 0; i < 4; i++)
404 ntq_store_dest(c, &instr->dest, i, qir_MOV(c, scaled));
405 } else {
406 for (int i = 0; i < 4; i++)
407 ntq_store_dest(c, &instr->dest, i,
408 qir_UNPACK_8_F(c, tex, i));
409 }
410 }
411
412 static void
413 ntq_emit_tex(struct vc4_compile *c, nir_tex_instr *instr)
414 {
415 struct qreg s, t, r, lod, compare;
416 bool is_txb = false, is_txl = false;
417 unsigned unit = instr->texture_index;
418
419 if (instr->op == nir_texop_txf) {
420 ntq_emit_txf(c, instr);
421 return;
422 }
423
424 for (unsigned i = 0; i < instr->num_srcs; i++) {
425 switch (instr->src[i].src_type) {
426 case nir_tex_src_coord:
427 s = ntq_get_src(c, instr->src[i].src, 0);
428 if (instr->sampler_dim == GLSL_SAMPLER_DIM_1D)
429 t = qir_uniform_f(c, 0.5);
430 else
431 t = ntq_get_src(c, instr->src[i].src, 1);
432 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
433 r = ntq_get_src(c, instr->src[i].src, 2);
434 break;
435 case nir_tex_src_bias:
436 lod = ntq_get_src(c, instr->src[i].src, 0);
437 is_txb = true;
438 break;
439 case nir_tex_src_lod:
440 lod = ntq_get_src(c, instr->src[i].src, 0);
441 is_txl = true;
442 break;
443 case nir_tex_src_comparator:
444 compare = ntq_get_src(c, instr->src[i].src, 0);
445 break;
446 default:
447 unreachable("unknown texture source");
448 }
449 }
450
451 if (c->stage != QSTAGE_FRAG && !is_txl) {
452 /* From the GLSL 1.20 spec:
453 *
454 * "If it is mip-mapped and running on the vertex shader,
455 * then the base texture is used."
456 */
457 is_txl = true;
458 lod = qir_uniform_ui(c, 0);
459 }
460
461 if (c->key->tex[unit].force_first_level) {
462 lod = qir_uniform(c, QUNIFORM_TEXTURE_FIRST_LEVEL, unit);
463 is_txl = true;
464 is_txb = false;
465 }
466
467 struct qreg texture_u[] = {
468 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P0, unit),
469 qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P1, unit),
470 qir_uniform(c, QUNIFORM_CONSTANT, 0),
471 qir_uniform(c, QUNIFORM_CONSTANT, 0),
472 };
473 uint32_t next_texture_u = 0;
474
475 /* There is no native support for GL texture rectangle coordinates, so
476 * we have to rescale from ([0, width], [0, height]) to ([0, 1], [0,
477 * 1]).
478 */
479 if (instr->sampler_dim == GLSL_SAMPLER_DIM_RECT) {
480 s = qir_FMUL(c, s,
481 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_X, unit));
482 t = qir_FMUL(c, t,
483 qir_uniform(c, QUNIFORM_TEXRECT_SCALE_Y, unit));
484 }
485
486 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE || is_txl) {
487 texture_u[2] = qir_uniform(c, QUNIFORM_TEXTURE_CONFIG_P2,
488 unit | (is_txl << 16));
489 }
490
491 struct qinst *tmu;
492 if (instr->sampler_dim == GLSL_SAMPLER_DIM_CUBE) {
493 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0), r);
494 tmu->src[qir_get_tex_uniform_src(tmu)] =
495 texture_u[next_texture_u++];
496 } else if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
497 c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP ||
498 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP_TO_BORDER ||
499 c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
500 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_R, 0),
501 qir_uniform(c, QUNIFORM_TEXTURE_BORDER_COLOR,
502 unit));
503 tmu->src[qir_get_tex_uniform_src(tmu)] =
504 texture_u[next_texture_u++];
505 }
506
507 if (c->key->tex[unit].wrap_s == PIPE_TEX_WRAP_CLAMP) {
508 s = qir_SAT(c, s);
509 }
510
511 if (c->key->tex[unit].wrap_t == PIPE_TEX_WRAP_CLAMP) {
512 t = qir_SAT(c, t);
513 }
514
515 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_T, 0), t);
516 tmu->src[qir_get_tex_uniform_src(tmu)] =
517 texture_u[next_texture_u++];
518
519 if (is_txl || is_txb) {
520 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_B, 0), lod);
521 tmu->src[qir_get_tex_uniform_src(tmu)] =
522 texture_u[next_texture_u++];
523 }
524
525 tmu = qir_MOV_dest(c, qir_reg(QFILE_TEX_S, 0), s);
526 tmu->src[qir_get_tex_uniform_src(tmu)] = texture_u[next_texture_u++];
527
528 c->num_texture_samples++;
529
530 ntq_emit_thrsw(c);
531
532 struct qreg tex = qir_TEX_RESULT(c);
533
534 enum pipe_format format = c->key->tex[unit].format;
535
536 struct qreg *dest = ntq_get_dest(c, &instr->dest);
537 if (util_format_is_depth_or_stencil(format)) {
538 struct qreg normalized = ntq_scale_depth_texture(c, tex);
539 struct qreg depth_output;
540
541 struct qreg u0 = qir_uniform_f(c, 0.0f);
542 struct qreg u1 = qir_uniform_f(c, 1.0f);
543 if (c->key->tex[unit].compare_mode) {
544 /* From the GL_ARB_shadow spec:
545 *
546 * "Let Dt (D subscript t) be the depth texture
547 * value, in the range [0, 1]. Let R be the
548 * interpolated texture coordinate clamped to the
549 * range [0, 1]."
550 */
551 compare = qir_SAT(c, compare);
552
553 switch (c->key->tex[unit].compare_func) {
554 case PIPE_FUNC_NEVER:
555 depth_output = qir_uniform_f(c, 0.0f);
556 break;
557 case PIPE_FUNC_ALWAYS:
558 depth_output = u1;
559 break;
560 case PIPE_FUNC_EQUAL:
561 qir_SF(c, qir_FSUB(c, compare, normalized));
562 depth_output = qir_SEL(c, QPU_COND_ZS, u1, u0);
563 break;
564 case PIPE_FUNC_NOTEQUAL:
565 qir_SF(c, qir_FSUB(c, compare, normalized));
566 depth_output = qir_SEL(c, QPU_COND_ZC, u1, u0);
567 break;
568 case PIPE_FUNC_GREATER:
569 qir_SF(c, qir_FSUB(c, compare, normalized));
570 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
571 break;
572 case PIPE_FUNC_GEQUAL:
573 qir_SF(c, qir_FSUB(c, normalized, compare));
574 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
575 break;
576 case PIPE_FUNC_LESS:
577 qir_SF(c, qir_FSUB(c, compare, normalized));
578 depth_output = qir_SEL(c, QPU_COND_NS, u1, u0);
579 break;
580 case PIPE_FUNC_LEQUAL:
581 qir_SF(c, qir_FSUB(c, normalized, compare));
582 depth_output = qir_SEL(c, QPU_COND_NC, u1, u0);
583 break;
584 }
585 } else {
586 depth_output = normalized;
587 }
588
589 for (int i = 0; i < 4; i++)
590 dest[i] = depth_output;
591 } else {
592 for (int i = 0; i < 4; i++)
593 dest[i] = qir_UNPACK_8_F(c, tex, i);
594 }
595 }
596
597 /**
598 * Computes x - floor(x), which is tricky because our FTOI truncates (rounds
599 * to zero).
600 */
601 static struct qreg
602 ntq_ffract(struct vc4_compile *c, struct qreg src)
603 {
604 struct qreg trunc = qir_ITOF(c, qir_FTOI(c, src));
605 struct qreg diff = qir_FSUB(c, src, trunc);
606 qir_SF(c, diff);
607
608 qir_FADD_dest(c, diff,
609 diff, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
610
611 return qir_MOV(c, diff);
612 }
613
614 /**
615 * Computes floor(x), which is tricky because our FTOI truncates (rounds to
616 * zero).
617 */
618 static struct qreg
619 ntq_ffloor(struct vc4_compile *c, struct qreg src)
620 {
621 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
622
623 /* This will be < 0 if we truncated and the truncation was of a value
624 * that was < 0 in the first place.
625 */
626 qir_SF(c, qir_FSUB(c, src, result));
627
628 struct qinst *sub = qir_FSUB_dest(c, result,
629 result, qir_uniform_f(c, 1.0));
630 sub->cond = QPU_COND_NS;
631
632 return qir_MOV(c, result);
633 }
634
635 /**
636 * Computes ceil(x), which is tricky because our FTOI truncates (rounds to
637 * zero).
638 */
639 static struct qreg
640 ntq_fceil(struct vc4_compile *c, struct qreg src)
641 {
642 struct qreg result = qir_ITOF(c, qir_FTOI(c, src));
643
644 /* This will be < 0 if we truncated and the truncation was of a value
645 * that was > 0 in the first place.
646 */
647 qir_SF(c, qir_FSUB(c, result, src));
648
649 qir_FADD_dest(c, result,
650 result, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
651
652 return qir_MOV(c, result);
653 }
654
655 static struct qreg
656 ntq_shrink_sincos_input_range(struct vc4_compile *c, struct qreg x)
657 {
658 /* Since we're using a Taylor approximation, we want to have a small
659 * number of coefficients and take advantage of sin/cos repeating
660 * every 2pi. We keep our x as close to 0 as we can, since the series
661 * will be less accurate as |x| increases. (Also, be careful of
662 * shifting the input x value to be tricky with sin/cos relations,
663 * because getting accurate values for x==0 is very important for SDL
664 * rendering)
665 */
666 struct qreg scaled_x =
667 qir_FMUL(c, x,
668 qir_uniform_f(c, 1.0f / (M_PI * 2.0f)));
669 /* Note: FTOI truncates toward 0. */
670 struct qreg x_frac = qir_FSUB(c, scaled_x,
671 qir_ITOF(c, qir_FTOI(c, scaled_x)));
672 /* Map [0.5, 1] to [-0.5, 0] */
673 qir_SF(c, qir_FSUB(c, x_frac, qir_uniform_f(c, 0.5)));
674 qir_FSUB_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NC;
675 /* Map [-1, -0.5] to [0, 0.5] */
676 qir_SF(c, qir_FADD(c, x_frac, qir_uniform_f(c, 0.5)));
677 qir_FADD_dest(c, x_frac, x_frac, qir_uniform_f(c, 1.0))->cond = QPU_COND_NS;
678
679 return x_frac;
680 }
681
682 static struct qreg
683 ntq_fsin(struct vc4_compile *c, struct qreg src)
684 {
685 float coeff[] = {
686 2.0 * M_PI,
687 -pow(2.0 * M_PI, 3) / (3 * 2 * 1),
688 pow(2.0 * M_PI, 5) / (5 * 4 * 3 * 2 * 1),
689 -pow(2.0 * M_PI, 7) / (7 * 6 * 5 * 4 * 3 * 2 * 1),
690 pow(2.0 * M_PI, 9) / (9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
691 };
692
693 struct qreg x = ntq_shrink_sincos_input_range(c, src);
694 struct qreg x2 = qir_FMUL(c, x, x);
695 struct qreg sum = qir_FMUL(c, x, qir_uniform_f(c, coeff[0]));
696 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
697 x = qir_FMUL(c, x, x2);
698 sum = qir_FADD(c,
699 sum,
700 qir_FMUL(c,
701 x,
702 qir_uniform_f(c, coeff[i])));
703 }
704 return sum;
705 }
706
707 static struct qreg
708 ntq_fcos(struct vc4_compile *c, struct qreg src)
709 {
710 float coeff[] = {
711 1.0f,
712 -pow(2.0 * M_PI, 2) / (2 * 1),
713 pow(2.0 * M_PI, 4) / (4 * 3 * 2 * 1),
714 -pow(2.0 * M_PI, 6) / (6 * 5 * 4 * 3 * 2 * 1),
715 pow(2.0 * M_PI, 8) / (8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
716 -pow(2.0 * M_PI, 10) / (10 * 9 * 8 * 7 * 6 * 5 * 4 * 3 * 2 * 1),
717 };
718
719 struct qreg x_frac = ntq_shrink_sincos_input_range(c, src);
720 struct qreg sum = qir_uniform_f(c, coeff[0]);
721 struct qreg x2 = qir_FMUL(c, x_frac, x_frac);
722 struct qreg x = x2; /* Current x^2, x^4, or x^6 */
723 for (int i = 1; i < ARRAY_SIZE(coeff); i++) {
724 if (i != 1)
725 x = qir_FMUL(c, x, x2);
726
727 sum = qir_FADD(c, qir_FMUL(c,
728 x,
729 qir_uniform_f(c, coeff[i])),
730 sum);
731 }
732 return sum;
733 }
734
735 static struct qreg
736 ntq_fsign(struct vc4_compile *c, struct qreg src)
737 {
738 struct qreg t = qir_get_temp(c);
739
740 qir_SF(c, src);
741 qir_MOV_dest(c, t, qir_uniform_f(c, 0.0));
742 qir_MOV_dest(c, t, qir_uniform_f(c, 1.0))->cond = QPU_COND_ZC;
743 qir_MOV_dest(c, t, qir_uniform_f(c, -1.0))->cond = QPU_COND_NS;
744 return qir_MOV(c, t);
745 }
746
747 static void
748 emit_vertex_input(struct vc4_compile *c, int attr)
749 {
750 enum pipe_format format = c->vs_key->attr_formats[attr];
751 uint32_t attr_size = util_format_get_blocksize(format);
752
753 c->vattr_sizes[attr] = align(attr_size, 4);
754 for (int i = 0; i < align(attr_size, 4) / 4; i++) {
755 c->inputs[attr * 4 + i] =
756 qir_MOV(c, qir_reg(QFILE_VPM, attr * 4 + i));
757 c->num_inputs++;
758 }
759 }
760
761 static void
762 emit_fragcoord_input(struct vc4_compile *c, int attr)
763 {
764 c->inputs[attr * 4 + 0] = qir_ITOF(c, qir_reg(QFILE_FRAG_X, 0));
765 c->inputs[attr * 4 + 1] = qir_ITOF(c, qir_reg(QFILE_FRAG_Y, 0));
766 c->inputs[attr * 4 + 2] =
767 qir_FMUL(c,
768 qir_ITOF(c, qir_FRAG_Z(c)),
769 qir_uniform_f(c, 1.0 / 0xffffff));
770 c->inputs[attr * 4 + 3] = qir_RCP(c, qir_FRAG_W(c));
771 }
772
773 static struct qreg
774 emit_fragment_varying(struct vc4_compile *c, gl_varying_slot slot,
775 uint8_t swizzle)
776 {
777 uint32_t i = c->num_input_slots++;
778 struct qreg vary = {
779 QFILE_VARY,
780 i
781 };
782
783 if (c->num_input_slots >= c->input_slots_array_size) {
784 c->input_slots_array_size =
785 MAX2(4, c->input_slots_array_size * 2);
786
787 c->input_slots = reralloc(c, c->input_slots,
788 struct vc4_varying_slot,
789 c->input_slots_array_size);
790 }
791
792 c->input_slots[i].slot = slot;
793 c->input_slots[i].swizzle = swizzle;
794
795 return qir_VARY_ADD_C(c, qir_FMUL(c, vary, qir_FRAG_W(c)));
796 }
797
798 static void
799 emit_fragment_input(struct vc4_compile *c, int attr, gl_varying_slot slot)
800 {
801 for (int i = 0; i < 4; i++) {
802 c->inputs[attr * 4 + i] =
803 emit_fragment_varying(c, slot, i);
804 c->num_inputs++;
805 }
806 }
807
808 static void
809 add_output(struct vc4_compile *c,
810 uint32_t decl_offset,
811 uint8_t slot,
812 uint8_t swizzle)
813 {
814 uint32_t old_array_size = c->outputs_array_size;
815 resize_qreg_array(c, &c->outputs, &c->outputs_array_size,
816 decl_offset + 1);
817
818 if (old_array_size != c->outputs_array_size) {
819 c->output_slots = reralloc(c,
820 c->output_slots,
821 struct vc4_varying_slot,
822 c->outputs_array_size);
823 }
824
825 c->output_slots[decl_offset].slot = slot;
826 c->output_slots[decl_offset].swizzle = swizzle;
827 }
828
829 static bool
830 ntq_src_is_only_ssa_def_user(nir_src *src)
831 {
832 if (!src->is_ssa)
833 return false;
834
835 if (!list_empty(&src->ssa->if_uses))
836 return false;
837
838 return (src->ssa->uses.next == &src->use_link &&
839 src->ssa->uses.next->next == &src->ssa->uses);
840 }
841
842 /**
843 * In general, emits a nir_pack_unorm_4x8 as a series of MOVs with the pack
844 * bit set.
845 *
846 * However, as an optimization, it tries to find the instructions generating
847 * the sources to be packed and just emit the pack flag there, if possible.
848 */
849 static void
850 ntq_emit_pack_unorm_4x8(struct vc4_compile *c, nir_alu_instr *instr)
851 {
852 struct qreg result = qir_get_temp(c);
853 struct nir_alu_instr *vec4 = NULL;
854
855 /* If packing from a vec4 op (as expected), identify it so that we can
856 * peek back at what generated its sources.
857 */
858 if (instr->src[0].src.is_ssa &&
859 instr->src[0].src.ssa->parent_instr->type == nir_instr_type_alu &&
860 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr)->op ==
861 nir_op_vec4) {
862 vec4 = nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
863 }
864
865 /* If the pack is replicating the same channel 4 times, use the 8888
866 * pack flag. This is common for blending using the alpha
867 * channel.
868 */
869 if (instr->src[0].swizzle[0] == instr->src[0].swizzle[1] &&
870 instr->src[0].swizzle[0] == instr->src[0].swizzle[2] &&
871 instr->src[0].swizzle[0] == instr->src[0].swizzle[3]) {
872 struct qreg rep = ntq_get_src(c,
873 instr->src[0].src,
874 instr->src[0].swizzle[0]);
875 ntq_store_dest(c, &instr->dest.dest, 0, qir_PACK_8888_F(c, rep));
876 return;
877 }
878
879 for (int i = 0; i < 4; i++) {
880 int swiz = instr->src[0].swizzle[i];
881 struct qreg src;
882 if (vec4) {
883 src = ntq_get_src(c, vec4->src[swiz].src,
884 vec4->src[swiz].swizzle[0]);
885 } else {
886 src = ntq_get_src(c, instr->src[0].src, swiz);
887 }
888
889 if (vec4 &&
890 ntq_src_is_only_ssa_def_user(&vec4->src[swiz].src) &&
891 src.file == QFILE_TEMP &&
892 c->defs[src.index] &&
893 qir_is_mul(c->defs[src.index]) &&
894 !c->defs[src.index]->dst.pack) {
895 struct qinst *rewrite = c->defs[src.index];
896 c->defs[src.index] = NULL;
897 rewrite->dst = result;
898 rewrite->dst.pack = QPU_PACK_MUL_8A + i;
899 continue;
900 }
901
902 qir_PACK_8_F(c, result, src, i);
903 }
904
905 ntq_store_dest(c, &instr->dest.dest, 0, qir_MOV(c, result));
906 }
907
908 /** Handles sign-extended bitfield extracts for 16 bits. */
909 static struct qreg
910 ntq_emit_ibfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
911 struct qreg bits)
912 {
913 assert(bits.file == QFILE_UNIF &&
914 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
915 c->uniform_data[bits.index] == 16);
916
917 assert(offset.file == QFILE_UNIF &&
918 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
919 int offset_bit = c->uniform_data[offset.index];
920 assert(offset_bit % 16 == 0);
921
922 return qir_UNPACK_16_I(c, base, offset_bit / 16);
923 }
924
925 /** Handles unsigned bitfield extracts for 8 bits. */
926 static struct qreg
927 ntq_emit_ubfe(struct vc4_compile *c, struct qreg base, struct qreg offset,
928 struct qreg bits)
929 {
930 assert(bits.file == QFILE_UNIF &&
931 c->uniform_contents[bits.index] == QUNIFORM_CONSTANT &&
932 c->uniform_data[bits.index] == 8);
933
934 assert(offset.file == QFILE_UNIF &&
935 c->uniform_contents[offset.index] == QUNIFORM_CONSTANT);
936 int offset_bit = c->uniform_data[offset.index];
937 assert(offset_bit % 8 == 0);
938
939 return qir_UNPACK_8_I(c, base, offset_bit / 8);
940 }
941
942 /**
943 * If compare_instr is a valid comparison instruction, emits the
944 * compare_instr's comparison and returns the sel_instr's return value based
945 * on the compare_instr's result.
946 */
947 static bool
948 ntq_emit_comparison(struct vc4_compile *c, struct qreg *dest,
949 nir_alu_instr *compare_instr,
950 nir_alu_instr *sel_instr)
951 {
952 enum qpu_cond cond;
953
954 switch (compare_instr->op) {
955 case nir_op_feq32:
956 case nir_op_ieq32:
957 case nir_op_seq:
958 cond = QPU_COND_ZS;
959 break;
960 case nir_op_fne32:
961 case nir_op_ine32:
962 case nir_op_sne:
963 cond = QPU_COND_ZC;
964 break;
965 case nir_op_fge32:
966 case nir_op_ige32:
967 case nir_op_uge32:
968 case nir_op_sge:
969 cond = QPU_COND_NC;
970 break;
971 case nir_op_flt32:
972 case nir_op_ilt32:
973 case nir_op_slt:
974 cond = QPU_COND_NS;
975 break;
976 default:
977 return false;
978 }
979
980 struct qreg src0 = ntq_get_alu_src(c, compare_instr, 0);
981 struct qreg src1 = ntq_get_alu_src(c, compare_instr, 1);
982
983 unsigned unsized_type =
984 nir_alu_type_get_base_type(nir_op_infos[compare_instr->op].input_types[0]);
985 if (unsized_type == nir_type_float)
986 qir_SF(c, qir_FSUB(c, src0, src1));
987 else
988 qir_SF(c, qir_SUB(c, src0, src1));
989
990 switch (sel_instr->op) {
991 case nir_op_seq:
992 case nir_op_sne:
993 case nir_op_sge:
994 case nir_op_slt:
995 *dest = qir_SEL(c, cond,
996 qir_uniform_f(c, 1.0), qir_uniform_f(c, 0.0));
997 break;
998
999 case nir_op_b32csel:
1000 *dest = qir_SEL(c, cond,
1001 ntq_get_alu_src(c, sel_instr, 1),
1002 ntq_get_alu_src(c, sel_instr, 2));
1003 break;
1004
1005 default:
1006 *dest = qir_SEL(c, cond,
1007 qir_uniform_ui(c, ~0), qir_uniform_ui(c, 0));
1008 break;
1009 }
1010
1011 /* Make the temporary for nir_store_dest(). */
1012 *dest = qir_MOV(c, *dest);
1013
1014 return true;
1015 }
1016
1017 /**
1018 * Attempts to fold a comparison generating a boolean result into the
1019 * condition code for selecting between two values, instead of comparing the
1020 * boolean result against 0 to generate the condition code.
1021 */
1022 static struct qreg ntq_emit_bcsel(struct vc4_compile *c, nir_alu_instr *instr,
1023 struct qreg *src)
1024 {
1025 if (!instr->src[0].src.is_ssa)
1026 goto out;
1027 if (instr->src[0].src.ssa->parent_instr->type != nir_instr_type_alu)
1028 goto out;
1029 nir_alu_instr *compare =
1030 nir_instr_as_alu(instr->src[0].src.ssa->parent_instr);
1031 if (!compare)
1032 goto out;
1033
1034 struct qreg dest;
1035 if (ntq_emit_comparison(c, &dest, compare, instr))
1036 return dest;
1037
1038 out:
1039 qir_SF(c, src[0]);
1040 return qir_MOV(c, qir_SEL(c, QPU_COND_NS, src[1], src[2]));
1041 }
1042
1043 static struct qreg
1044 ntq_fddx(struct vc4_compile *c, struct qreg src)
1045 {
1046 /* Make sure that we have a bare temp to use for MUL rotation, so it
1047 * can be allocated to an accumulator.
1048 */
1049 if (src.pack || src.file != QFILE_TEMP)
1050 src = qir_MOV(c, src);
1051
1052 struct qreg from_left = qir_ROT_MUL(c, src, 1);
1053 struct qreg from_right = qir_ROT_MUL(c, src, 15);
1054
1055 /* Distinguish left/right pixels of the quad. */
1056 qir_SF(c, qir_AND(c, qir_reg(QFILE_QPU_ELEMENT, 0),
1057 qir_uniform_ui(c, 1)));
1058
1059 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1060 qir_FSUB(c, from_right, src),
1061 qir_FSUB(c, src, from_left)));
1062 }
1063
1064 static struct qreg
1065 ntq_fddy(struct vc4_compile *c, struct qreg src)
1066 {
1067 if (src.pack || src.file != QFILE_TEMP)
1068 src = qir_MOV(c, src);
1069
1070 struct qreg from_bottom = qir_ROT_MUL(c, src, 2);
1071 struct qreg from_top = qir_ROT_MUL(c, src, 14);
1072
1073 /* Distinguish top/bottom pixels of the quad. */
1074 qir_SF(c, qir_AND(c,
1075 qir_reg(QFILE_QPU_ELEMENT, 0),
1076 qir_uniform_ui(c, 2)));
1077
1078 return qir_MOV(c, qir_SEL(c, QPU_COND_ZS,
1079 qir_FSUB(c, from_top, src),
1080 qir_FSUB(c, src, from_bottom)));
1081 }
1082
1083 static void
1084 ntq_emit_alu(struct vc4_compile *c, nir_alu_instr *instr)
1085 {
1086 /* This should always be lowered to ALU operations for VC4. */
1087 assert(!instr->dest.saturate);
1088
1089 /* Vectors are special in that they have non-scalarized writemasks,
1090 * and just take the first swizzle channel for each argument in order
1091 * into each writemask channel.
1092 */
1093 if (instr->op == nir_op_vec2 ||
1094 instr->op == nir_op_vec3 ||
1095 instr->op == nir_op_vec4) {
1096 struct qreg srcs[4];
1097 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1098 srcs[i] = ntq_get_src(c, instr->src[i].src,
1099 instr->src[i].swizzle[0]);
1100 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++)
1101 ntq_store_dest(c, &instr->dest.dest, i,
1102 qir_MOV(c, srcs[i]));
1103 return;
1104 }
1105
1106 if (instr->op == nir_op_pack_unorm_4x8) {
1107 ntq_emit_pack_unorm_4x8(c, instr);
1108 return;
1109 }
1110
1111 if (instr->op == nir_op_unpack_unorm_4x8) {
1112 struct qreg src = ntq_get_src(c, instr->src[0].src,
1113 instr->src[0].swizzle[0]);
1114 for (int i = 0; i < 4; i++) {
1115 if (instr->dest.write_mask & (1 << i))
1116 ntq_store_dest(c, &instr->dest.dest, i,
1117 qir_UNPACK_8_F(c, src, i));
1118 }
1119 return;
1120 }
1121
1122 /* General case: We can just grab the one used channel per src. */
1123 struct qreg src[nir_op_infos[instr->op].num_inputs];
1124 for (int i = 0; i < nir_op_infos[instr->op].num_inputs; i++) {
1125 src[i] = ntq_get_alu_src(c, instr, i);
1126 }
1127
1128 struct qreg result;
1129
1130 switch (instr->op) {
1131 case nir_op_mov:
1132 result = qir_MOV(c, src[0]);
1133 break;
1134 case nir_op_fmul:
1135 result = qir_FMUL(c, src[0], src[1]);
1136 break;
1137 case nir_op_fadd:
1138 result = qir_FADD(c, src[0], src[1]);
1139 break;
1140 case nir_op_fsub:
1141 result = qir_FSUB(c, src[0], src[1]);
1142 break;
1143 case nir_op_fmin:
1144 result = qir_FMIN(c, src[0], src[1]);
1145 break;
1146 case nir_op_fmax:
1147 result = qir_FMAX(c, src[0], src[1]);
1148 break;
1149
1150 case nir_op_f2i32:
1151 case nir_op_f2u32:
1152 result = qir_FTOI(c, src[0]);
1153 break;
1154 case nir_op_i2f32:
1155 case nir_op_u2f32:
1156 result = qir_ITOF(c, src[0]);
1157 break;
1158 case nir_op_b2f32:
1159 result = qir_AND(c, src[0], qir_uniform_f(c, 1.0));
1160 break;
1161 case nir_op_b2i32:
1162 result = qir_AND(c, src[0], qir_uniform_ui(c, 1));
1163 break;
1164 case nir_op_i2b32:
1165 case nir_op_f2b32:
1166 qir_SF(c, src[0]);
1167 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC,
1168 qir_uniform_ui(c, ~0),
1169 qir_uniform_ui(c, 0)));
1170 break;
1171
1172 case nir_op_iadd:
1173 result = qir_ADD(c, src[0], src[1]);
1174 break;
1175 case nir_op_ushr:
1176 result = qir_SHR(c, src[0], src[1]);
1177 break;
1178 case nir_op_isub:
1179 result = qir_SUB(c, src[0], src[1]);
1180 break;
1181 case nir_op_ishr:
1182 result = qir_ASR(c, src[0], src[1]);
1183 break;
1184 case nir_op_ishl:
1185 result = qir_SHL(c, src[0], src[1]);
1186 break;
1187 case nir_op_imin:
1188 result = qir_MIN(c, src[0], src[1]);
1189 break;
1190 case nir_op_imax:
1191 result = qir_MAX(c, src[0], src[1]);
1192 break;
1193 case nir_op_iand:
1194 result = qir_AND(c, src[0], src[1]);
1195 break;
1196 case nir_op_ior:
1197 result = qir_OR(c, src[0], src[1]);
1198 break;
1199 case nir_op_ixor:
1200 result = qir_XOR(c, src[0], src[1]);
1201 break;
1202 case nir_op_inot:
1203 result = qir_NOT(c, src[0]);
1204 break;
1205
1206 case nir_op_imul:
1207 result = ntq_umul(c, src[0], src[1]);
1208 break;
1209
1210 case nir_op_seq:
1211 case nir_op_sne:
1212 case nir_op_sge:
1213 case nir_op_slt:
1214 case nir_op_feq32:
1215 case nir_op_fne32:
1216 case nir_op_fge32:
1217 case nir_op_flt32:
1218 case nir_op_ieq32:
1219 case nir_op_ine32:
1220 case nir_op_ige32:
1221 case nir_op_uge32:
1222 case nir_op_ilt32:
1223 if (!ntq_emit_comparison(c, &result, instr, instr)) {
1224 fprintf(stderr, "Bad comparison instruction\n");
1225 }
1226 break;
1227
1228 case nir_op_b32csel:
1229 result = ntq_emit_bcsel(c, instr, src);
1230 break;
1231 case nir_op_fcsel:
1232 qir_SF(c, src[0]);
1233 result = qir_MOV(c, qir_SEL(c, QPU_COND_ZC, src[1], src[2]));
1234 break;
1235
1236 case nir_op_frcp:
1237 result = ntq_rcp(c, src[0]);
1238 break;
1239 case nir_op_frsq:
1240 result = ntq_rsq(c, src[0]);
1241 break;
1242 case nir_op_fexp2:
1243 result = qir_EXP2(c, src[0]);
1244 break;
1245 case nir_op_flog2:
1246 result = qir_LOG2(c, src[0]);
1247 break;
1248
1249 case nir_op_ftrunc:
1250 result = qir_ITOF(c, qir_FTOI(c, src[0]));
1251 break;
1252 case nir_op_fceil:
1253 result = ntq_fceil(c, src[0]);
1254 break;
1255 case nir_op_ffract:
1256 result = ntq_ffract(c, src[0]);
1257 break;
1258 case nir_op_ffloor:
1259 result = ntq_ffloor(c, src[0]);
1260 break;
1261
1262 case nir_op_fsin:
1263 result = ntq_fsin(c, src[0]);
1264 break;
1265 case nir_op_fcos:
1266 result = ntq_fcos(c, src[0]);
1267 break;
1268
1269 case nir_op_fsign:
1270 result = ntq_fsign(c, src[0]);
1271 break;
1272
1273 case nir_op_fabs:
1274 result = qir_FMAXABS(c, src[0], src[0]);
1275 break;
1276 case nir_op_iabs:
1277 result = qir_MAX(c, src[0],
1278 qir_SUB(c, qir_uniform_ui(c, 0), src[0]));
1279 break;
1280
1281 case nir_op_ibitfield_extract:
1282 result = ntq_emit_ibfe(c, src[0], src[1], src[2]);
1283 break;
1284
1285 case nir_op_ubitfield_extract:
1286 result = ntq_emit_ubfe(c, src[0], src[1], src[2]);
1287 break;
1288
1289 case nir_op_usadd_4x8:
1290 result = qir_V8ADDS(c, src[0], src[1]);
1291 break;
1292
1293 case nir_op_ussub_4x8:
1294 result = qir_V8SUBS(c, src[0], src[1]);
1295 break;
1296
1297 case nir_op_umin_4x8:
1298 result = qir_V8MIN(c, src[0], src[1]);
1299 break;
1300
1301 case nir_op_umax_4x8:
1302 result = qir_V8MAX(c, src[0], src[1]);
1303 break;
1304
1305 case nir_op_umul_unorm_4x8:
1306 result = qir_V8MULD(c, src[0], src[1]);
1307 break;
1308
1309 case nir_op_fddx:
1310 case nir_op_fddx_coarse:
1311 case nir_op_fddx_fine:
1312 result = ntq_fddx(c, src[0]);
1313 break;
1314
1315 case nir_op_fddy:
1316 case nir_op_fddy_coarse:
1317 case nir_op_fddy_fine:
1318 result = ntq_fddy(c, src[0]);
1319 break;
1320
1321 default:
1322 fprintf(stderr, "unknown NIR ALU inst: ");
1323 nir_print_instr(&instr->instr, stderr);
1324 fprintf(stderr, "\n");
1325 abort();
1326 }
1327
1328 /* We have a scalar result, so the instruction should only have a
1329 * single channel written to.
1330 */
1331 assert(util_is_power_of_two_or_zero(instr->dest.write_mask));
1332 ntq_store_dest(c, &instr->dest.dest,
1333 ffs(instr->dest.write_mask) - 1, result);
1334 }
1335
1336 static void
1337 emit_frag_end(struct vc4_compile *c)
1338 {
1339 struct qreg color;
1340 if (c->output_color_index != -1) {
1341 color = c->outputs[c->output_color_index];
1342 } else {
1343 color = qir_uniform_ui(c, 0);
1344 }
1345
1346 uint32_t discard_cond = QPU_COND_ALWAYS;
1347 if (c->s->info.fs.uses_discard) {
1348 qir_SF(c, c->discard);
1349 discard_cond = QPU_COND_ZS;
1350 }
1351
1352 if (c->fs_key->stencil_enabled) {
1353 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1354 qir_uniform(c, QUNIFORM_STENCIL, 0));
1355 if (c->fs_key->stencil_twoside) {
1356 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1357 qir_uniform(c, QUNIFORM_STENCIL, 1));
1358 }
1359 if (c->fs_key->stencil_full_writemasks) {
1360 qir_MOV_dest(c, qir_reg(QFILE_TLB_STENCIL_SETUP, 0),
1361 qir_uniform(c, QUNIFORM_STENCIL, 2));
1362 }
1363 }
1364
1365 if (c->output_sample_mask_index != -1) {
1366 qir_MS_MASK(c, c->outputs[c->output_sample_mask_index]);
1367 }
1368
1369 if (c->fs_key->depth_enabled) {
1370 if (c->output_position_index != -1) {
1371 qir_FTOI_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1372 qir_FMUL(c,
1373 c->outputs[c->output_position_index],
1374 qir_uniform_f(c, 0xffffff)))->cond = discard_cond;
1375 } else {
1376 qir_MOV_dest(c, qir_reg(QFILE_TLB_Z_WRITE, 0),
1377 qir_FRAG_Z(c))->cond = discard_cond;
1378 }
1379 }
1380
1381 if (!c->msaa_per_sample_output) {
1382 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE, 0),
1383 color)->cond = discard_cond;
1384 } else {
1385 for (int i = 0; i < VC4_MAX_SAMPLES; i++) {
1386 qir_MOV_dest(c, qir_reg(QFILE_TLB_COLOR_WRITE_MS, 0),
1387 c->sample_colors[i])->cond = discard_cond;
1388 }
1389 }
1390 }
1391
1392 static void
1393 emit_scaled_viewport_write(struct vc4_compile *c, struct qreg rcp_w)
1394 {
1395 struct qreg packed = qir_get_temp(c);
1396
1397 for (int i = 0; i < 2; i++) {
1398 struct qreg scale =
1399 qir_uniform(c, QUNIFORM_VIEWPORT_X_SCALE + i, 0);
1400
1401 struct qreg packed_chan = packed;
1402 packed_chan.pack = QPU_PACK_A_16A + i;
1403
1404 qir_FTOI_dest(c, packed_chan,
1405 qir_FMUL(c,
1406 qir_FMUL(c,
1407 c->outputs[c->output_position_index + i],
1408 scale),
1409 rcp_w));
1410 }
1411
1412 qir_VPM_WRITE(c, packed);
1413 }
1414
1415 static void
1416 emit_zs_write(struct vc4_compile *c, struct qreg rcp_w)
1417 {
1418 struct qreg zscale = qir_uniform(c, QUNIFORM_VIEWPORT_Z_SCALE, 0);
1419 struct qreg zoffset = qir_uniform(c, QUNIFORM_VIEWPORT_Z_OFFSET, 0);
1420
1421 qir_VPM_WRITE(c, qir_FADD(c, qir_FMUL(c, qir_FMUL(c,
1422 c->outputs[c->output_position_index + 2],
1423 zscale),
1424 rcp_w),
1425 zoffset));
1426 }
1427
1428 static void
1429 emit_rcp_wc_write(struct vc4_compile *c, struct qreg rcp_w)
1430 {
1431 qir_VPM_WRITE(c, rcp_w);
1432 }
1433
1434 static void
1435 emit_point_size_write(struct vc4_compile *c)
1436 {
1437 struct qreg point_size;
1438
1439 if (c->output_point_size_index != -1)
1440 point_size = c->outputs[c->output_point_size_index];
1441 else
1442 point_size = qir_uniform_f(c, 1.0);
1443
1444 /* Workaround: HW-2726 PTB does not handle zero-size points (BCM2835,
1445 * BCM21553).
1446 */
1447 point_size = qir_FMAX(c, point_size, qir_uniform_f(c, .125));
1448
1449 qir_VPM_WRITE(c, point_size);
1450 }
1451
1452 /**
1453 * Emits a VPM read of the stub vertex attribute set up by vc4_draw.c.
1454 *
1455 * The simulator insists that there be at least one vertex attribute, so
1456 * vc4_draw.c will emit one if it wouldn't have otherwise. The simulator also
1457 * insists that all vertex attributes loaded get read by the VS/CS, so we have
1458 * to consume it here.
1459 */
1460 static void
1461 emit_stub_vpm_read(struct vc4_compile *c)
1462 {
1463 if (c->num_inputs)
1464 return;
1465
1466 c->vattr_sizes[0] = 4;
1467 (void)qir_MOV(c, qir_reg(QFILE_VPM, 0));
1468 c->num_inputs++;
1469 }
1470
1471 static void
1472 emit_vert_end(struct vc4_compile *c,
1473 struct vc4_varying_slot *fs_inputs,
1474 uint32_t num_fs_inputs)
1475 {
1476 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1477
1478 emit_stub_vpm_read(c);
1479
1480 emit_scaled_viewport_write(c, rcp_w);
1481 emit_zs_write(c, rcp_w);
1482 emit_rcp_wc_write(c, rcp_w);
1483 if (c->vs_key->per_vertex_point_size)
1484 emit_point_size_write(c);
1485
1486 for (int i = 0; i < num_fs_inputs; i++) {
1487 struct vc4_varying_slot *input = &fs_inputs[i];
1488 int j;
1489
1490 for (j = 0; j < c->num_outputs; j++) {
1491 struct vc4_varying_slot *output =
1492 &c->output_slots[j];
1493
1494 if (input->slot == output->slot &&
1495 input->swizzle == output->swizzle) {
1496 qir_VPM_WRITE(c, c->outputs[j]);
1497 break;
1498 }
1499 }
1500 /* Emit padding if we didn't find a declared VS output for
1501 * this FS input.
1502 */
1503 if (j == c->num_outputs)
1504 qir_VPM_WRITE(c, qir_uniform_f(c, 0.0));
1505 }
1506 }
1507
1508 static void
1509 emit_coord_end(struct vc4_compile *c)
1510 {
1511 struct qreg rcp_w = ntq_rcp(c, c->outputs[c->output_position_index + 3]);
1512
1513 emit_stub_vpm_read(c);
1514
1515 for (int i = 0; i < 4; i++)
1516 qir_VPM_WRITE(c, c->outputs[c->output_position_index + i]);
1517
1518 emit_scaled_viewport_write(c, rcp_w);
1519 emit_zs_write(c, rcp_w);
1520 emit_rcp_wc_write(c, rcp_w);
1521 if (c->vs_key->per_vertex_point_size)
1522 emit_point_size_write(c);
1523 }
1524
1525 static void
1526 vc4_optimize_nir(struct nir_shader *s)
1527 {
1528 bool progress;
1529 unsigned lower_flrp =
1530 (s->options->lower_flrp16 ? 16 : 0) |
1531 (s->options->lower_flrp32 ? 32 : 0) |
1532 (s->options->lower_flrp64 ? 64 : 0);
1533
1534 do {
1535 progress = false;
1536
1537 NIR_PASS_V(s, nir_lower_vars_to_ssa);
1538 NIR_PASS(progress, s, nir_lower_alu_to_scalar, NULL);
1539 NIR_PASS(progress, s, nir_lower_phis_to_scalar);
1540 NIR_PASS(progress, s, nir_copy_prop);
1541 NIR_PASS(progress, s, nir_opt_remove_phis);
1542 NIR_PASS(progress, s, nir_opt_dce);
1543 NIR_PASS(progress, s, nir_opt_dead_cf);
1544 NIR_PASS(progress, s, nir_opt_cse);
1545 NIR_PASS(progress, s, nir_opt_peephole_select, 8, true, true);
1546 NIR_PASS(progress, s, nir_opt_algebraic);
1547 NIR_PASS(progress, s, nir_opt_constant_folding);
1548 if (lower_flrp != 0) {
1549 bool lower_flrp_progress = false;
1550
1551 NIR_PASS(lower_flrp_progress, s, nir_lower_flrp,
1552 lower_flrp,
1553 false /* always_precise */,
1554 s->options->lower_ffma);
1555 if (lower_flrp_progress) {
1556 NIR_PASS(progress, s, nir_opt_constant_folding);
1557 progress = true;
1558 }
1559
1560 /* Nothing should rematerialize any flrps, so we only
1561 * need to do this lowering once.
1562 */
1563 lower_flrp = 0;
1564 }
1565
1566 NIR_PASS(progress, s, nir_opt_undef);
1567 NIR_PASS(progress, s, nir_opt_loop_unroll,
1568 nir_var_shader_in |
1569 nir_var_shader_out |
1570 nir_var_function_temp);
1571 } while (progress);
1572 }
1573
1574 static int
1575 driver_location_compare(const void *in_a, const void *in_b)
1576 {
1577 const nir_variable *const *a = in_a;
1578 const nir_variable *const *b = in_b;
1579
1580 return (*a)->data.driver_location - (*b)->data.driver_location;
1581 }
1582
1583 static void
1584 ntq_setup_inputs(struct vc4_compile *c)
1585 {
1586 unsigned num_entries = 0;
1587 nir_foreach_variable(var, &c->s->inputs)
1588 num_entries++;
1589
1590 nir_variable *vars[num_entries];
1591
1592 unsigned i = 0;
1593 nir_foreach_variable(var, &c->s->inputs)
1594 vars[i++] = var;
1595
1596 /* Sort the variables so that we emit the input setup in
1597 * driver_location order. This is required for VPM reads, whose data
1598 * is fetched into the VPM in driver_location (TGSI register index)
1599 * order.
1600 */
1601 qsort(&vars, num_entries, sizeof(*vars), driver_location_compare);
1602
1603 for (unsigned i = 0; i < num_entries; i++) {
1604 nir_variable *var = vars[i];
1605 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1606 unsigned loc = var->data.driver_location;
1607
1608 assert(array_len == 1);
1609 (void)array_len;
1610 resize_qreg_array(c, &c->inputs, &c->inputs_array_size,
1611 (loc + 1) * 4);
1612
1613 if (c->stage == QSTAGE_FRAG) {
1614 if (var->data.location == VARYING_SLOT_POS) {
1615 emit_fragcoord_input(c, loc);
1616 } else if (var->data.location == VARYING_SLOT_PNTC ||
1617 (var->data.location >= VARYING_SLOT_VAR0 &&
1618 (c->fs_key->point_sprite_mask &
1619 (1 << (var->data.location -
1620 VARYING_SLOT_VAR0))))) {
1621 c->inputs[loc * 4 + 0] = c->point_x;
1622 c->inputs[loc * 4 + 1] = c->point_y;
1623 } else {
1624 emit_fragment_input(c, loc, var->data.location);
1625 }
1626 } else {
1627 emit_vertex_input(c, loc);
1628 }
1629 }
1630 }
1631
1632 static void
1633 ntq_setup_outputs(struct vc4_compile *c)
1634 {
1635 nir_foreach_variable(var, &c->s->outputs) {
1636 unsigned array_len = MAX2(glsl_get_length(var->type), 1);
1637 unsigned loc = var->data.driver_location * 4;
1638
1639 assert(array_len == 1);
1640 (void)array_len;
1641
1642 for (int i = 0; i < 4; i++)
1643 add_output(c, loc + i, var->data.location, i);
1644
1645 if (c->stage == QSTAGE_FRAG) {
1646 switch (var->data.location) {
1647 case FRAG_RESULT_COLOR:
1648 case FRAG_RESULT_DATA0:
1649 c->output_color_index = loc;
1650 break;
1651 case FRAG_RESULT_DEPTH:
1652 c->output_position_index = loc;
1653 break;
1654 case FRAG_RESULT_SAMPLE_MASK:
1655 c->output_sample_mask_index = loc;
1656 break;
1657 }
1658 } else {
1659 switch (var->data.location) {
1660 case VARYING_SLOT_POS:
1661 c->output_position_index = loc;
1662 break;
1663 case VARYING_SLOT_PSIZ:
1664 c->output_point_size_index = loc;
1665 break;
1666 }
1667 }
1668 }
1669 }
1670
1671 /**
1672 * Sets up the mapping from nir_register to struct qreg *.
1673 *
1674 * Each nir_register gets a struct qreg per 32-bit component being stored.
1675 */
1676 static void
1677 ntq_setup_registers(struct vc4_compile *c, struct exec_list *list)
1678 {
1679 foreach_list_typed(nir_register, nir_reg, node, list) {
1680 unsigned array_len = MAX2(nir_reg->num_array_elems, 1);
1681 struct qreg *qregs = ralloc_array(c->def_ht, struct qreg,
1682 array_len *
1683 nir_reg->num_components);
1684
1685 _mesa_hash_table_insert(c->def_ht, nir_reg, qregs);
1686
1687 for (int i = 0; i < array_len * nir_reg->num_components; i++)
1688 qregs[i] = qir_get_temp(c);
1689 }
1690 }
1691
1692 static void
1693 ntq_emit_load_const(struct vc4_compile *c, nir_load_const_instr *instr)
1694 {
1695 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1696 for (int i = 0; i < instr->def.num_components; i++)
1697 qregs[i] = qir_uniform_ui(c, instr->value[i].u32);
1698
1699 _mesa_hash_table_insert(c->def_ht, &instr->def, qregs);
1700 }
1701
1702 static void
1703 ntq_emit_ssa_undef(struct vc4_compile *c, nir_ssa_undef_instr *instr)
1704 {
1705 struct qreg *qregs = ntq_init_ssa_def(c, &instr->def);
1706
1707 /* QIR needs there to be *some* value, so pick 0 (same as for
1708 * ntq_setup_registers().
1709 */
1710 for (int i = 0; i < instr->def.num_components; i++)
1711 qregs[i] = qir_uniform_ui(c, 0);
1712 }
1713
1714 static void
1715 ntq_emit_color_read(struct vc4_compile *c, nir_intrinsic_instr *instr)
1716 {
1717 assert(nir_src_as_uint(instr->src[0]) == 0);
1718
1719 /* Reads of the per-sample color need to be done in
1720 * order.
1721 */
1722 int sample_index = (nir_intrinsic_base(instr) -
1723 VC4_NIR_TLB_COLOR_READ_INPUT);
1724 for (int i = 0; i <= sample_index; i++) {
1725 if (c->color_reads[i].file == QFILE_NULL) {
1726 c->color_reads[i] =
1727 qir_TLB_COLOR_READ(c);
1728 }
1729 }
1730 ntq_store_dest(c, &instr->dest, 0,
1731 qir_MOV(c, c->color_reads[sample_index]));
1732 }
1733
1734 static void
1735 ntq_emit_load_input(struct vc4_compile *c, nir_intrinsic_instr *instr)
1736 {
1737 assert(instr->num_components == 1);
1738 assert(nir_src_is_const(instr->src[0]) &&
1739 "vc4 doesn't support indirect inputs");
1740
1741 if (c->stage == QSTAGE_FRAG &&
1742 nir_intrinsic_base(instr) >= VC4_NIR_TLB_COLOR_READ_INPUT) {
1743 ntq_emit_color_read(c, instr);
1744 return;
1745 }
1746
1747 uint32_t offset = nir_intrinsic_base(instr) +
1748 nir_src_as_uint(instr->src[0]);
1749 int comp = nir_intrinsic_component(instr);
1750 ntq_store_dest(c, &instr->dest, 0,
1751 qir_MOV(c, c->inputs[offset * 4 + comp]));
1752 }
1753
1754 static void
1755 ntq_emit_intrinsic(struct vc4_compile *c, nir_intrinsic_instr *instr)
1756 {
1757 unsigned offset;
1758
1759 switch (instr->intrinsic) {
1760 case nir_intrinsic_load_uniform:
1761 assert(instr->num_components == 1);
1762 if (nir_src_is_const(instr->src[0])) {
1763 offset = nir_intrinsic_base(instr) +
1764 nir_src_as_uint(instr->src[0]);
1765 assert(offset % 4 == 0);
1766 /* We need dwords */
1767 offset = offset / 4;
1768 ntq_store_dest(c, &instr->dest, 0,
1769 qir_uniform(c, QUNIFORM_UNIFORM,
1770 offset));
1771 } else {
1772 ntq_store_dest(c, &instr->dest, 0,
1773 indirect_uniform_load(c, instr));
1774 }
1775 break;
1776
1777 case nir_intrinsic_load_ubo:
1778 assert(instr->num_components == 1);
1779 ntq_store_dest(c, &instr->dest, 0, vc4_ubo_load(c, instr));
1780 break;
1781
1782 case nir_intrinsic_load_user_clip_plane:
1783 for (int i = 0; i < instr->num_components; i++) {
1784 ntq_store_dest(c, &instr->dest, i,
1785 qir_uniform(c, QUNIFORM_USER_CLIP_PLANE,
1786 nir_intrinsic_ucp_id(instr) *
1787 4 + i));
1788 }
1789 break;
1790
1791 case nir_intrinsic_load_blend_const_color_r_float:
1792 case nir_intrinsic_load_blend_const_color_g_float:
1793 case nir_intrinsic_load_blend_const_color_b_float:
1794 case nir_intrinsic_load_blend_const_color_a_float:
1795 ntq_store_dest(c, &instr->dest, 0,
1796 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_X +
1797 (instr->intrinsic -
1798 nir_intrinsic_load_blend_const_color_r_float),
1799 0));
1800 break;
1801
1802 case nir_intrinsic_load_blend_const_color_rgba8888_unorm:
1803 ntq_store_dest(c, &instr->dest, 0,
1804 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_RGBA,
1805 0));
1806 break;
1807
1808 case nir_intrinsic_load_blend_const_color_aaaa8888_unorm:
1809 ntq_store_dest(c, &instr->dest, 0,
1810 qir_uniform(c, QUNIFORM_BLEND_CONST_COLOR_AAAA,
1811 0));
1812 break;
1813
1814 case nir_intrinsic_load_alpha_ref_float:
1815 ntq_store_dest(c, &instr->dest, 0,
1816 qir_uniform(c, QUNIFORM_ALPHA_REF, 0));
1817 break;
1818
1819 case nir_intrinsic_load_sample_mask_in:
1820 ntq_store_dest(c, &instr->dest, 0,
1821 qir_uniform(c, QUNIFORM_SAMPLE_MASK, 0));
1822 break;
1823
1824 case nir_intrinsic_load_front_face:
1825 /* The register contains 0 (front) or 1 (back), and we need to
1826 * turn it into a NIR bool where true means front.
1827 */
1828 ntq_store_dest(c, &instr->dest, 0,
1829 qir_ADD(c,
1830 qir_uniform_ui(c, -1),
1831 qir_reg(QFILE_FRAG_REV_FLAG, 0)));
1832 break;
1833
1834 case nir_intrinsic_load_input:
1835 ntq_emit_load_input(c, instr);
1836 break;
1837
1838 case nir_intrinsic_store_output:
1839 assert(nir_src_is_const(instr->src[1]) &&
1840 "vc4 doesn't support indirect outputs");
1841 offset = nir_intrinsic_base(instr) +
1842 nir_src_as_uint(instr->src[1]);
1843
1844 /* MSAA color outputs are the only case where we have an
1845 * output that's not lowered to being a store of a single 32
1846 * bit value.
1847 */
1848 if (c->stage == QSTAGE_FRAG && instr->num_components == 4) {
1849 assert(offset == c->output_color_index);
1850 for (int i = 0; i < 4; i++) {
1851 c->sample_colors[i] =
1852 qir_MOV(c, ntq_get_src(c, instr->src[0],
1853 i));
1854 }
1855 } else {
1856 offset = offset * 4 + nir_intrinsic_component(instr);
1857 assert(instr->num_components == 1);
1858 c->outputs[offset] =
1859 qir_MOV(c, ntq_get_src(c, instr->src[0], 0));
1860 c->num_outputs = MAX2(c->num_outputs, offset + 1);
1861 }
1862 break;
1863
1864 case nir_intrinsic_discard:
1865 if (c->execute.file != QFILE_NULL) {
1866 qir_SF(c, c->execute);
1867 qir_MOV_cond(c, QPU_COND_ZS, c->discard,
1868 qir_uniform_ui(c, ~0));
1869 } else {
1870 qir_MOV_dest(c, c->discard, qir_uniform_ui(c, ~0));
1871 }
1872 break;
1873
1874 case nir_intrinsic_discard_if: {
1875 /* true (~0) if we're discarding */
1876 struct qreg cond = ntq_get_src(c, instr->src[0], 0);
1877
1878 if (c->execute.file != QFILE_NULL) {
1879 /* execute == 0 means the channel is active. Invert
1880 * the condition so that we can use zero as "executing
1881 * and discarding."
1882 */
1883 qir_SF(c, qir_AND(c, c->execute, qir_NOT(c, cond)));
1884 qir_MOV_cond(c, QPU_COND_ZS, c->discard, cond);
1885 } else {
1886 qir_OR_dest(c, c->discard, c->discard,
1887 ntq_get_src(c, instr->src[0], 0));
1888 }
1889
1890 break;
1891 }
1892
1893 default:
1894 fprintf(stderr, "Unknown intrinsic: ");
1895 nir_print_instr(&instr->instr, stderr);
1896 fprintf(stderr, "\n");
1897 break;
1898 }
1899 }
1900
1901 /* Clears (activates) the execute flags for any channels whose jump target
1902 * matches this block.
1903 */
1904 static void
1905 ntq_activate_execute_for_block(struct vc4_compile *c)
1906 {
1907 qir_SF(c, qir_SUB(c,
1908 c->execute,
1909 qir_uniform_ui(c, c->cur_block->index)));
1910 qir_MOV_cond(c, QPU_COND_ZS, c->execute, qir_uniform_ui(c, 0));
1911 }
1912
1913 static void
1914 ntq_emit_if(struct vc4_compile *c, nir_if *if_stmt)
1915 {
1916 if (!c->vc4->screen->has_control_flow) {
1917 fprintf(stderr,
1918 "IF statement support requires updated kernel.\n");
1919 return;
1920 }
1921
1922 nir_block *nir_else_block = nir_if_first_else_block(if_stmt);
1923 bool empty_else_block =
1924 (nir_else_block == nir_if_last_else_block(if_stmt) &&
1925 exec_list_is_empty(&nir_else_block->instr_list));
1926
1927 struct qblock *then_block = qir_new_block(c);
1928 struct qblock *after_block = qir_new_block(c);
1929 struct qblock *else_block;
1930 if (empty_else_block)
1931 else_block = after_block;
1932 else
1933 else_block = qir_new_block(c);
1934
1935 bool was_top_level = false;
1936 if (c->execute.file == QFILE_NULL) {
1937 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
1938 was_top_level = true;
1939 }
1940
1941 /* Set ZS for executing (execute == 0) and jumping (if->condition ==
1942 * 0) channels, and then update execute flags for those to point to
1943 * the ELSE block.
1944 */
1945 qir_SF(c, qir_OR(c,
1946 c->execute,
1947 ntq_get_src(c, if_stmt->condition, 0)));
1948 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1949 qir_uniform_ui(c, else_block->index));
1950
1951 /* Jump to ELSE if nothing is active for THEN, otherwise fall
1952 * through.
1953 */
1954 qir_SF(c, c->execute);
1955 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZC);
1956 qir_link_blocks(c->cur_block, else_block);
1957 qir_link_blocks(c->cur_block, then_block);
1958
1959 /* Process the THEN block. */
1960 qir_set_emit_block(c, then_block);
1961 ntq_emit_cf_list(c, &if_stmt->then_list);
1962
1963 if (!empty_else_block) {
1964 /* Handle the end of the THEN block. First, all currently
1965 * active channels update their execute flags to point to
1966 * ENDIF
1967 */
1968 qir_SF(c, c->execute);
1969 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
1970 qir_uniform_ui(c, after_block->index));
1971
1972 /* If everything points at ENDIF, then jump there immediately. */
1973 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, after_block->index)));
1974 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
1975 qir_link_blocks(c->cur_block, after_block);
1976 qir_link_blocks(c->cur_block, else_block);
1977
1978 qir_set_emit_block(c, else_block);
1979 ntq_activate_execute_for_block(c);
1980 ntq_emit_cf_list(c, &if_stmt->else_list);
1981 }
1982
1983 qir_link_blocks(c->cur_block, after_block);
1984
1985 qir_set_emit_block(c, after_block);
1986 if (was_top_level) {
1987 c->execute = c->undef;
1988 c->last_top_block = c->cur_block;
1989 } else {
1990 ntq_activate_execute_for_block(c);
1991 }
1992 }
1993
1994 static void
1995 ntq_emit_jump(struct vc4_compile *c, nir_jump_instr *jump)
1996 {
1997 struct qblock *jump_block;
1998 switch (jump->type) {
1999 case nir_jump_break:
2000 jump_block = c->loop_break_block;
2001 break;
2002 case nir_jump_continue:
2003 jump_block = c->loop_cont_block;
2004 break;
2005 default:
2006 unreachable("Unsupported jump type\n");
2007 }
2008
2009 qir_SF(c, c->execute);
2010 qir_MOV_cond(c, QPU_COND_ZS, c->execute,
2011 qir_uniform_ui(c, jump_block->index));
2012
2013 /* Jump to the destination block if everyone has taken the jump. */
2014 qir_SF(c, qir_SUB(c, c->execute, qir_uniform_ui(c, jump_block->index)));
2015 qir_BRANCH(c, QPU_COND_BRANCH_ALL_ZS);
2016 struct qblock *new_block = qir_new_block(c);
2017 qir_link_blocks(c->cur_block, jump_block);
2018 qir_link_blocks(c->cur_block, new_block);
2019 qir_set_emit_block(c, new_block);
2020 }
2021
2022 static void
2023 ntq_emit_instr(struct vc4_compile *c, nir_instr *instr)
2024 {
2025 switch (instr->type) {
2026 case nir_instr_type_alu:
2027 ntq_emit_alu(c, nir_instr_as_alu(instr));
2028 break;
2029
2030 case nir_instr_type_intrinsic:
2031 ntq_emit_intrinsic(c, nir_instr_as_intrinsic(instr));
2032 break;
2033
2034 case nir_instr_type_load_const:
2035 ntq_emit_load_const(c, nir_instr_as_load_const(instr));
2036 break;
2037
2038 case nir_instr_type_ssa_undef:
2039 ntq_emit_ssa_undef(c, nir_instr_as_ssa_undef(instr));
2040 break;
2041
2042 case nir_instr_type_tex:
2043 ntq_emit_tex(c, nir_instr_as_tex(instr));
2044 break;
2045
2046 case nir_instr_type_jump:
2047 ntq_emit_jump(c, nir_instr_as_jump(instr));
2048 break;
2049
2050 default:
2051 fprintf(stderr, "Unknown NIR instr type: ");
2052 nir_print_instr(instr, stderr);
2053 fprintf(stderr, "\n");
2054 abort();
2055 }
2056 }
2057
2058 static void
2059 ntq_emit_block(struct vc4_compile *c, nir_block *block)
2060 {
2061 nir_foreach_instr(instr, block) {
2062 ntq_emit_instr(c, instr);
2063 }
2064 }
2065
2066 static void ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list);
2067
2068 static void
2069 ntq_emit_loop(struct vc4_compile *c, nir_loop *loop)
2070 {
2071 if (!c->vc4->screen->has_control_flow) {
2072 fprintf(stderr,
2073 "loop support requires updated kernel.\n");
2074 ntq_emit_cf_list(c, &loop->body);
2075 return;
2076 }
2077
2078 bool was_top_level = false;
2079 if (c->execute.file == QFILE_NULL) {
2080 c->execute = qir_MOV(c, qir_uniform_ui(c, 0));
2081 was_top_level = true;
2082 }
2083
2084 struct qblock *save_loop_cont_block = c->loop_cont_block;
2085 struct qblock *save_loop_break_block = c->loop_break_block;
2086
2087 c->loop_cont_block = qir_new_block(c);
2088 c->loop_break_block = qir_new_block(c);
2089
2090 qir_link_blocks(c->cur_block, c->loop_cont_block);
2091 qir_set_emit_block(c, c->loop_cont_block);
2092 ntq_activate_execute_for_block(c);
2093
2094 ntq_emit_cf_list(c, &loop->body);
2095
2096 /* If anything had explicitly continued, or is here at the end of the
2097 * loop, then we need to loop again. SF updates are masked by the
2098 * instruction's condition, so we can do the OR of the two conditions
2099 * within SF.
2100 */
2101 qir_SF(c, c->execute);
2102 struct qinst *cont_check =
2103 qir_SUB_dest(c,
2104 c->undef,
2105 c->execute,
2106 qir_uniform_ui(c, c->loop_cont_block->index));
2107 cont_check->cond = QPU_COND_ZC;
2108 cont_check->sf = true;
2109
2110 qir_BRANCH(c, QPU_COND_BRANCH_ANY_ZS);
2111 qir_link_blocks(c->cur_block, c->loop_cont_block);
2112 qir_link_blocks(c->cur_block, c->loop_break_block);
2113
2114 qir_set_emit_block(c, c->loop_break_block);
2115 if (was_top_level) {
2116 c->execute = c->undef;
2117 c->last_top_block = c->cur_block;
2118 } else {
2119 ntq_activate_execute_for_block(c);
2120 }
2121
2122 c->loop_break_block = save_loop_break_block;
2123 c->loop_cont_block = save_loop_cont_block;
2124 }
2125
2126 static void
2127 ntq_emit_function(struct vc4_compile *c, nir_function_impl *func)
2128 {
2129 fprintf(stderr, "FUNCTIONS not handled.\n");
2130 abort();
2131 }
2132
2133 static void
2134 ntq_emit_cf_list(struct vc4_compile *c, struct exec_list *list)
2135 {
2136 foreach_list_typed(nir_cf_node, node, node, list) {
2137 switch (node->type) {
2138 case nir_cf_node_block:
2139 ntq_emit_block(c, nir_cf_node_as_block(node));
2140 break;
2141
2142 case nir_cf_node_if:
2143 ntq_emit_if(c, nir_cf_node_as_if(node));
2144 break;
2145
2146 case nir_cf_node_loop:
2147 ntq_emit_loop(c, nir_cf_node_as_loop(node));
2148 break;
2149
2150 case nir_cf_node_function:
2151 ntq_emit_function(c, nir_cf_node_as_function(node));
2152 break;
2153
2154 default:
2155 fprintf(stderr, "Unknown NIR node type\n");
2156 abort();
2157 }
2158 }
2159 }
2160
2161 static void
2162 ntq_emit_impl(struct vc4_compile *c, nir_function_impl *impl)
2163 {
2164 ntq_setup_registers(c, &impl->registers);
2165 ntq_emit_cf_list(c, &impl->body);
2166 }
2167
2168 static void
2169 nir_to_qir(struct vc4_compile *c)
2170 {
2171 if (c->stage == QSTAGE_FRAG && c->s->info.fs.uses_discard)
2172 c->discard = qir_MOV(c, qir_uniform_ui(c, 0));
2173
2174 ntq_setup_inputs(c);
2175 ntq_setup_outputs(c);
2176
2177 /* Find the main function and emit the body. */
2178 nir_foreach_function(function, c->s) {
2179 assert(strcmp(function->name, "main") == 0);
2180 assert(function->impl);
2181 ntq_emit_impl(c, function->impl);
2182 }
2183 }
2184
2185 static const nir_shader_compiler_options nir_options = {
2186 .lower_all_io_to_temps = true,
2187 .lower_extract_byte = true,
2188 .lower_extract_word = true,
2189 .lower_fdiv = true,
2190 .lower_ffma = true,
2191 .lower_flrp32 = true,
2192 .lower_fmod = true,
2193 .lower_fpow = true,
2194 .lower_fsat = true,
2195 .lower_fsqrt = true,
2196 .lower_ldexp = true,
2197 .lower_negate = true,
2198 .lower_rotate = true,
2199 .max_unroll_iterations = 32,
2200 };
2201
2202 const void *
2203 vc4_screen_get_compiler_options(struct pipe_screen *pscreen,
2204 enum pipe_shader_ir ir,
2205 enum pipe_shader_type shader)
2206 {
2207 return &nir_options;
2208 }
2209
2210 static int
2211 count_nir_instrs(nir_shader *nir)
2212 {
2213 int count = 0;
2214 nir_foreach_function(function, nir) {
2215 if (!function->impl)
2216 continue;
2217 nir_foreach_block(block, function->impl) {
2218 nir_foreach_instr(instr, block)
2219 count++;
2220 }
2221 }
2222 return count;
2223 }
2224
2225 static struct vc4_compile *
2226 vc4_shader_ntq(struct vc4_context *vc4, enum qstage stage,
2227 struct vc4_key *key, bool fs_threaded)
2228 {
2229 struct vc4_compile *c = qir_compile_init();
2230
2231 c->vc4 = vc4;
2232 c->stage = stage;
2233 c->shader_state = &key->shader_state->base;
2234 c->program_id = key->shader_state->program_id;
2235 c->variant_id =
2236 p_atomic_inc_return(&key->shader_state->compiled_variant_count);
2237 c->fs_threaded = fs_threaded;
2238
2239 c->key = key;
2240 switch (stage) {
2241 case QSTAGE_FRAG:
2242 c->fs_key = (struct vc4_fs_key *)key;
2243 if (c->fs_key->is_points) {
2244 c->point_x = emit_fragment_varying(c, ~0, 0);
2245 c->point_y = emit_fragment_varying(c, ~0, 0);
2246 } else if (c->fs_key->is_lines) {
2247 c->line_x = emit_fragment_varying(c, ~0, 0);
2248 }
2249 break;
2250 case QSTAGE_VERT:
2251 c->vs_key = (struct vc4_vs_key *)key;
2252 break;
2253 case QSTAGE_COORD:
2254 c->vs_key = (struct vc4_vs_key *)key;
2255 break;
2256 }
2257
2258 c->s = nir_shader_clone(c, key->shader_state->base.ir.nir);
2259
2260 if (stage == QSTAGE_FRAG) {
2261 if (c->fs_key->alpha_test_func != COMPARE_FUNC_ALWAYS) {
2262 NIR_PASS_V(c->s, nir_lower_alpha_test,
2263 c->fs_key->alpha_test_func,
2264 c->fs_key->sample_alpha_to_one &&
2265 c->fs_key->msaa);
2266 }
2267 NIR_PASS_V(c->s, vc4_nir_lower_blend, c);
2268 }
2269
2270 struct nir_lower_tex_options tex_options = {
2271 /* We would need to implement txs, but we don't want the
2272 * int/float conversions
2273 */
2274 .lower_rect = false,
2275
2276 .lower_txp = ~0,
2277
2278 /* Apply swizzles to all samplers. */
2279 .swizzle_result = ~0,
2280 };
2281
2282 /* Lower the format swizzle and ARB_texture_swizzle-style swizzle.
2283 * The format swizzling applies before sRGB decode, and
2284 * ARB_texture_swizzle is the last thing before returning the sample.
2285 */
2286 for (int i = 0; i < ARRAY_SIZE(key->tex); i++) {
2287 enum pipe_format format = c->key->tex[i].format;
2288
2289 if (!format)
2290 continue;
2291
2292 const uint8_t *format_swizzle = vc4_get_format_swizzle(format);
2293
2294 for (int j = 0; j < 4; j++) {
2295 uint8_t arb_swiz = c->key->tex[i].swizzle[j];
2296
2297 if (arb_swiz <= 3) {
2298 tex_options.swizzles[i][j] =
2299 format_swizzle[arb_swiz];
2300 } else {
2301 tex_options.swizzles[i][j] = arb_swiz;
2302 }
2303 }
2304
2305 if (util_format_is_srgb(format))
2306 tex_options.lower_srgb |= (1 << i);
2307 }
2308
2309 NIR_PASS_V(c->s, nir_lower_tex, &tex_options);
2310
2311 if (c->fs_key && c->fs_key->light_twoside)
2312 NIR_PASS_V(c->s, nir_lower_two_sided_color);
2313
2314 if (c->vs_key && c->vs_key->clamp_color)
2315 NIR_PASS_V(c->s, nir_lower_clamp_color_outputs);
2316
2317 if (c->key->ucp_enables) {
2318 if (stage == QSTAGE_FRAG) {
2319 NIR_PASS_V(c->s, nir_lower_clip_fs, c->key->ucp_enables);
2320 } else {
2321 NIR_PASS_V(c->s, nir_lower_clip_vs,
2322 c->key->ucp_enables, false);
2323 NIR_PASS_V(c->s, nir_lower_io_to_scalar,
2324 nir_var_shader_out);
2325 }
2326 }
2327
2328 /* FS input scalarizing must happen after nir_lower_two_sided_color,
2329 * which only handles a vec4 at a time. Similarly, VS output
2330 * scalarizing must happen after nir_lower_clip_vs.
2331 */
2332 if (c->stage == QSTAGE_FRAG)
2333 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_in);
2334 else
2335 NIR_PASS_V(c->s, nir_lower_io_to_scalar, nir_var_shader_out);
2336
2337 NIR_PASS_V(c->s, vc4_nir_lower_io, c);
2338 NIR_PASS_V(c->s, vc4_nir_lower_txf_ms, c);
2339 NIR_PASS_V(c->s, nir_lower_idiv);
2340
2341 vc4_optimize_nir(c->s);
2342
2343 NIR_PASS_V(c->s, nir_lower_bool_to_int32);
2344
2345 NIR_PASS_V(c->s, nir_convert_from_ssa, true);
2346
2347 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2348 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d NIR instructions\n",
2349 qir_get_stage_name(c->stage),
2350 c->program_id, c->variant_id,
2351 count_nir_instrs(c->s));
2352 }
2353
2354 if (vc4_debug & VC4_DEBUG_NIR) {
2355 fprintf(stderr, "%s prog %d/%d NIR:\n",
2356 qir_get_stage_name(c->stage),
2357 c->program_id, c->variant_id);
2358 nir_print_shader(c->s, stderr);
2359 }
2360
2361 nir_to_qir(c);
2362
2363 switch (stage) {
2364 case QSTAGE_FRAG:
2365 /* FS threading requires that the thread execute
2366 * QPU_SIG_LAST_THREAD_SWITCH exactly once before terminating
2367 * (with no other THRSW afterwards, obviously). If we didn't
2368 * fetch a texture at a top level block, this wouldn't be
2369 * true.
2370 */
2371 if (c->fs_threaded && !c->last_thrsw_at_top_level) {
2372 c->failed = true;
2373 return c;
2374 }
2375
2376 emit_frag_end(c);
2377 break;
2378 case QSTAGE_VERT:
2379 emit_vert_end(c,
2380 c->vs_key->fs_inputs->input_slots,
2381 c->vs_key->fs_inputs->num_inputs);
2382 break;
2383 case QSTAGE_COORD:
2384 emit_coord_end(c);
2385 break;
2386 }
2387
2388 if (vc4_debug & VC4_DEBUG_QIR) {
2389 fprintf(stderr, "%s prog %d/%d pre-opt QIR:\n",
2390 qir_get_stage_name(c->stage),
2391 c->program_id, c->variant_id);
2392 qir_dump(c);
2393 fprintf(stderr, "\n");
2394 }
2395
2396 qir_optimize(c);
2397 qir_lower_uniforms(c);
2398
2399 qir_schedule_instructions(c);
2400 qir_emit_uniform_stream_resets(c);
2401
2402 if (vc4_debug & VC4_DEBUG_QIR) {
2403 fprintf(stderr, "%s prog %d/%d QIR:\n",
2404 qir_get_stage_name(c->stage),
2405 c->program_id, c->variant_id);
2406 qir_dump(c);
2407 fprintf(stderr, "\n");
2408 }
2409
2410 qir_reorder_uniforms(c);
2411 vc4_generate_code(vc4, c);
2412
2413 if (vc4_debug & VC4_DEBUG_SHADERDB) {
2414 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d instructions\n",
2415 qir_get_stage_name(c->stage),
2416 c->program_id, c->variant_id,
2417 c->qpu_inst_count);
2418 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d uniforms\n",
2419 qir_get_stage_name(c->stage),
2420 c->program_id, c->variant_id,
2421 c->num_uniforms);
2422 }
2423
2424 ralloc_free(c->s);
2425
2426 return c;
2427 }
2428
2429 static void *
2430 vc4_shader_state_create(struct pipe_context *pctx,
2431 const struct pipe_shader_state *cso)
2432 {
2433 struct vc4_context *vc4 = vc4_context(pctx);
2434 struct vc4_uncompiled_shader *so = CALLOC_STRUCT(vc4_uncompiled_shader);
2435 if (!so)
2436 return NULL;
2437
2438 so->program_id = vc4->next_uncompiled_program_id++;
2439
2440 nir_shader *s;
2441
2442 if (cso->type == PIPE_SHADER_IR_NIR) {
2443 /* The backend takes ownership of the NIR shader on state
2444 * creation.
2445 */
2446 s = cso->ir.nir;
2447 } else {
2448 assert(cso->type == PIPE_SHADER_IR_TGSI);
2449
2450 if (vc4_debug & VC4_DEBUG_TGSI) {
2451 fprintf(stderr, "prog %d TGSI:\n",
2452 so->program_id);
2453 tgsi_dump(cso->tokens, 0);
2454 fprintf(stderr, "\n");
2455 }
2456 s = tgsi_to_nir(cso->tokens, pctx->screen);
2457 }
2458
2459 NIR_PASS_V(s, nir_lower_io, nir_var_all, type_size,
2460 (nir_lower_io_options)0);
2461
2462 NIR_PASS_V(s, nir_lower_regs_to_ssa);
2463 NIR_PASS_V(s, nir_normalize_cubemap_coords);
2464
2465 NIR_PASS_V(s, nir_lower_load_const_to_scalar);
2466
2467 vc4_optimize_nir(s);
2468
2469 NIR_PASS_V(s, nir_remove_dead_variables, nir_var_function_temp);
2470
2471 /* Garbage collect dead instructions */
2472 nir_sweep(s);
2473
2474 so->base.type = PIPE_SHADER_IR_NIR;
2475 so->base.ir.nir = s;
2476
2477 if (vc4_debug & VC4_DEBUG_NIR) {
2478 fprintf(stderr, "%s prog %d NIR:\n",
2479 gl_shader_stage_name(s->info.stage),
2480 so->program_id);
2481 nir_print_shader(s, stderr);
2482 fprintf(stderr, "\n");
2483 }
2484
2485 return so;
2486 }
2487
2488 static void
2489 copy_uniform_state_to_shader(struct vc4_compiled_shader *shader,
2490 struct vc4_compile *c)
2491 {
2492 int count = c->num_uniforms;
2493 struct vc4_shader_uniform_info *uinfo = &shader->uniforms;
2494
2495 uinfo->count = count;
2496 uinfo->data = ralloc_array(shader, uint32_t, count);
2497 memcpy(uinfo->data, c->uniform_data,
2498 count * sizeof(*uinfo->data));
2499 uinfo->contents = ralloc_array(shader, enum quniform_contents, count);
2500 memcpy(uinfo->contents, c->uniform_contents,
2501 count * sizeof(*uinfo->contents));
2502 uinfo->num_texture_samples = c->num_texture_samples;
2503
2504 vc4_set_shader_uniform_dirty_flags(shader);
2505 }
2506
2507 static void
2508 vc4_setup_compiled_fs_inputs(struct vc4_context *vc4, struct vc4_compile *c,
2509 struct vc4_compiled_shader *shader)
2510 {
2511 struct vc4_fs_inputs inputs;
2512
2513 memset(&inputs, 0, sizeof(inputs));
2514 inputs.input_slots = ralloc_array(shader,
2515 struct vc4_varying_slot,
2516 c->num_input_slots);
2517
2518 bool input_live[c->num_input_slots];
2519
2520 memset(input_live, 0, sizeof(input_live));
2521 qir_for_each_inst_inorder(inst, c) {
2522 for (int i = 0; i < qir_get_nsrc(inst); i++) {
2523 if (inst->src[i].file == QFILE_VARY)
2524 input_live[inst->src[i].index] = true;
2525 }
2526 }
2527
2528 for (int i = 0; i < c->num_input_slots; i++) {
2529 struct vc4_varying_slot *slot = &c->input_slots[i];
2530
2531 if (!input_live[i])
2532 continue;
2533
2534 /* Skip non-VS-output inputs. */
2535 if (slot->slot == (uint8_t)~0)
2536 continue;
2537
2538 if (slot->slot == VARYING_SLOT_COL0 ||
2539 slot->slot == VARYING_SLOT_COL1 ||
2540 slot->slot == VARYING_SLOT_BFC0 ||
2541 slot->slot == VARYING_SLOT_BFC1) {
2542 shader->color_inputs |= (1 << inputs.num_inputs);
2543 }
2544
2545 inputs.input_slots[inputs.num_inputs] = *slot;
2546 inputs.num_inputs++;
2547 }
2548 shader->num_inputs = inputs.num_inputs;
2549
2550 /* Add our set of inputs to the set of all inputs seen. This way, we
2551 * can have a single pointer that identifies an FS inputs set,
2552 * allowing VS to avoid recompiling when the FS is recompiled (or a
2553 * new one is bound using separate shader objects) but the inputs
2554 * don't change.
2555 */
2556 struct set_entry *entry = _mesa_set_search(vc4->fs_inputs_set, &inputs);
2557 if (entry) {
2558 shader->fs_inputs = entry->key;
2559 ralloc_free(inputs.input_slots);
2560 } else {
2561 struct vc4_fs_inputs *alloc_inputs;
2562
2563 alloc_inputs = rzalloc(vc4->fs_inputs_set, struct vc4_fs_inputs);
2564 memcpy(alloc_inputs, &inputs, sizeof(inputs));
2565 ralloc_steal(alloc_inputs, inputs.input_slots);
2566 _mesa_set_add(vc4->fs_inputs_set, alloc_inputs);
2567
2568 shader->fs_inputs = alloc_inputs;
2569 }
2570 }
2571
2572 static struct vc4_compiled_shader *
2573 vc4_get_compiled_shader(struct vc4_context *vc4, enum qstage stage,
2574 struct vc4_key *key)
2575 {
2576 struct hash_table *ht;
2577 uint32_t key_size;
2578 bool try_threading;
2579
2580 if (stage == QSTAGE_FRAG) {
2581 ht = vc4->fs_cache;
2582 key_size = sizeof(struct vc4_fs_key);
2583 try_threading = vc4->screen->has_threaded_fs;
2584 } else {
2585 ht = vc4->vs_cache;
2586 key_size = sizeof(struct vc4_vs_key);
2587 try_threading = false;
2588 }
2589
2590 struct vc4_compiled_shader *shader;
2591 struct hash_entry *entry = _mesa_hash_table_search(ht, key);
2592 if (entry)
2593 return entry->data;
2594
2595 struct vc4_compile *c = vc4_shader_ntq(vc4, stage, key, try_threading);
2596 /* If the FS failed to compile threaded, fall back to single threaded. */
2597 if (try_threading && c->failed) {
2598 qir_compile_destroy(c);
2599 c = vc4_shader_ntq(vc4, stage, key, false);
2600 }
2601
2602 shader = rzalloc(NULL, struct vc4_compiled_shader);
2603
2604 shader->program_id = vc4->next_compiled_program_id++;
2605 if (stage == QSTAGE_FRAG) {
2606 vc4_setup_compiled_fs_inputs(vc4, c, shader);
2607
2608 /* Note: the temporary clone in c->s has been freed. */
2609 nir_shader *orig_shader = key->shader_state->base.ir.nir;
2610 if (orig_shader->info.outputs_written & (1 << FRAG_RESULT_DEPTH))
2611 shader->disable_early_z = true;
2612 } else {
2613 shader->num_inputs = c->num_inputs;
2614
2615 shader->vattr_offsets[0] = 0;
2616 for (int i = 0; i < 8; i++) {
2617 shader->vattr_offsets[i + 1] =
2618 shader->vattr_offsets[i] + c->vattr_sizes[i];
2619
2620 if (c->vattr_sizes[i])
2621 shader->vattrs_live |= (1 << i);
2622 }
2623 }
2624
2625 shader->failed = c->failed;
2626 if (c->failed) {
2627 shader->failed = true;
2628 } else {
2629 copy_uniform_state_to_shader(shader, c);
2630 shader->bo = vc4_bo_alloc_shader(vc4->screen, c->qpu_insts,
2631 c->qpu_inst_count *
2632 sizeof(uint64_t));
2633 }
2634
2635 shader->fs_threaded = c->fs_threaded;
2636
2637 if ((vc4_debug & VC4_DEBUG_SHADERDB) && stage == QSTAGE_FRAG) {
2638 fprintf(stderr, "SHADER-DB: %s prog %d/%d: %d FS threads\n",
2639 qir_get_stage_name(c->stage),
2640 c->program_id, c->variant_id,
2641 1 + shader->fs_threaded);
2642 }
2643
2644 qir_compile_destroy(c);
2645
2646 struct vc4_key *dup_key;
2647 dup_key = rzalloc_size(shader, key_size); /* TODO: don't use rzalloc */
2648 memcpy(dup_key, key, key_size);
2649 _mesa_hash_table_insert(ht, dup_key, shader);
2650
2651 return shader;
2652 }
2653
2654 static void
2655 vc4_setup_shared_key(struct vc4_context *vc4, struct vc4_key *key,
2656 struct vc4_texture_stateobj *texstate)
2657 {
2658 for (int i = 0; i < texstate->num_textures; i++) {
2659 struct pipe_sampler_view *sampler = texstate->textures[i];
2660 struct vc4_sampler_view *vc4_sampler = vc4_sampler_view(sampler);
2661 struct pipe_sampler_state *sampler_state =
2662 texstate->samplers[i];
2663
2664 if (!sampler)
2665 continue;
2666
2667 key->tex[i].format = sampler->format;
2668 key->tex[i].swizzle[0] = sampler->swizzle_r;
2669 key->tex[i].swizzle[1] = sampler->swizzle_g;
2670 key->tex[i].swizzle[2] = sampler->swizzle_b;
2671 key->tex[i].swizzle[3] = sampler->swizzle_a;
2672
2673 if (sampler->texture->nr_samples > 1) {
2674 key->tex[i].msaa_width = sampler->texture->width0;
2675 key->tex[i].msaa_height = sampler->texture->height0;
2676 } else if (sampler){
2677 key->tex[i].compare_mode = sampler_state->compare_mode;
2678 key->tex[i].compare_func = sampler_state->compare_func;
2679 key->tex[i].wrap_s = sampler_state->wrap_s;
2680 key->tex[i].wrap_t = sampler_state->wrap_t;
2681 key->tex[i].force_first_level =
2682 vc4_sampler->force_first_level;
2683 }
2684 }
2685
2686 key->ucp_enables = vc4->rasterizer->base.clip_plane_enable;
2687 }
2688
2689 static void
2690 vc4_update_compiled_fs(struct vc4_context *vc4, uint8_t prim_mode)
2691 {
2692 struct vc4_job *job = vc4->job;
2693 struct vc4_fs_key local_key;
2694 struct vc4_fs_key *key = &local_key;
2695
2696 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2697 VC4_DIRTY_BLEND |
2698 VC4_DIRTY_FRAMEBUFFER |
2699 VC4_DIRTY_ZSA |
2700 VC4_DIRTY_RASTERIZER |
2701 VC4_DIRTY_SAMPLE_MASK |
2702 VC4_DIRTY_FRAGTEX |
2703 VC4_DIRTY_UNCOMPILED_FS |
2704 VC4_DIRTY_UBO_1_SIZE))) {
2705 return;
2706 }
2707
2708 memset(key, 0, sizeof(*key));
2709 vc4_setup_shared_key(vc4, &key->base, &vc4->fragtex);
2710 key->base.shader_state = vc4->prog.bind_fs;
2711 key->is_points = (prim_mode == PIPE_PRIM_POINTS);
2712 key->is_lines = (prim_mode >= PIPE_PRIM_LINES &&
2713 prim_mode <= PIPE_PRIM_LINE_STRIP);
2714 key->blend = vc4->blend->rt[0];
2715 if (vc4->blend->logicop_enable) {
2716 key->logicop_func = vc4->blend->logicop_func;
2717 } else {
2718 key->logicop_func = PIPE_LOGICOP_COPY;
2719 }
2720 if (job->msaa) {
2721 key->msaa = vc4->rasterizer->base.multisample;
2722 key->sample_coverage = (vc4->sample_mask != (1 << VC4_MAX_SAMPLES) - 1);
2723 key->sample_alpha_to_coverage = vc4->blend->alpha_to_coverage;
2724 key->sample_alpha_to_one = vc4->blend->alpha_to_one;
2725 }
2726
2727 if (vc4->framebuffer.cbufs[0])
2728 key->color_format = vc4->framebuffer.cbufs[0]->format;
2729
2730 key->stencil_enabled = vc4->zsa->stencil_uniforms[0] != 0;
2731 key->stencil_twoside = vc4->zsa->stencil_uniforms[1] != 0;
2732 key->stencil_full_writemasks = vc4->zsa->stencil_uniforms[2] != 0;
2733 key->depth_enabled = (vc4->zsa->base.depth.enabled ||
2734 key->stencil_enabled);
2735 if (vc4->zsa->base.alpha.enabled)
2736 key->alpha_test_func = vc4->zsa->base.alpha.func;
2737 else
2738 key->alpha_test_func = COMPARE_FUNC_ALWAYS;
2739
2740 if (key->is_points) {
2741 key->point_sprite_mask =
2742 vc4->rasterizer->base.sprite_coord_enable;
2743 key->point_coord_upper_left =
2744 (vc4->rasterizer->base.sprite_coord_mode ==
2745 PIPE_SPRITE_COORD_UPPER_LEFT);
2746 }
2747
2748 key->ubo_1_size = vc4->constbuf[PIPE_SHADER_FRAGMENT].cb[1].buffer_size;
2749 key->light_twoside = vc4->rasterizer->base.light_twoside;
2750
2751 struct vc4_compiled_shader *old_fs = vc4->prog.fs;
2752 vc4->prog.fs = vc4_get_compiled_shader(vc4, QSTAGE_FRAG, &key->base);
2753 if (vc4->prog.fs == old_fs)
2754 return;
2755
2756 vc4->dirty |= VC4_DIRTY_COMPILED_FS;
2757
2758 if (vc4->rasterizer->base.flatshade &&
2759 (!old_fs || vc4->prog.fs->color_inputs != old_fs->color_inputs)) {
2760 vc4->dirty |= VC4_DIRTY_FLAT_SHADE_FLAGS;
2761 }
2762
2763 if (!old_fs || vc4->prog.fs->fs_inputs != old_fs->fs_inputs)
2764 vc4->dirty |= VC4_DIRTY_FS_INPUTS;
2765 }
2766
2767 static void
2768 vc4_update_compiled_vs(struct vc4_context *vc4, uint8_t prim_mode)
2769 {
2770 struct vc4_vs_key local_key;
2771 struct vc4_vs_key *key = &local_key;
2772
2773 if (!(vc4->dirty & (VC4_DIRTY_PRIM_MODE |
2774 VC4_DIRTY_RASTERIZER |
2775 VC4_DIRTY_VERTTEX |
2776 VC4_DIRTY_VTXSTATE |
2777 VC4_DIRTY_UNCOMPILED_VS |
2778 VC4_DIRTY_FS_INPUTS))) {
2779 return;
2780 }
2781
2782 memset(key, 0, sizeof(*key));
2783 vc4_setup_shared_key(vc4, &key->base, &vc4->verttex);
2784 key->base.shader_state = vc4->prog.bind_vs;
2785 key->fs_inputs = vc4->prog.fs->fs_inputs;
2786 key->clamp_color = vc4->rasterizer->base.clamp_vertex_color;
2787
2788 for (int i = 0; i < ARRAY_SIZE(key->attr_formats); i++)
2789 key->attr_formats[i] = vc4->vtx->pipe[i].src_format;
2790
2791 key->per_vertex_point_size =
2792 (prim_mode == PIPE_PRIM_POINTS &&
2793 vc4->rasterizer->base.point_size_per_vertex);
2794
2795 struct vc4_compiled_shader *vs =
2796 vc4_get_compiled_shader(vc4, QSTAGE_VERT, &key->base);
2797 if (vs != vc4->prog.vs) {
2798 vc4->prog.vs = vs;
2799 vc4->dirty |= VC4_DIRTY_COMPILED_VS;
2800 }
2801
2802 key->is_coord = true;
2803 /* Coord shaders don't care what the FS inputs are. */
2804 key->fs_inputs = NULL;
2805 struct vc4_compiled_shader *cs =
2806 vc4_get_compiled_shader(vc4, QSTAGE_COORD, &key->base);
2807 if (cs != vc4->prog.cs) {
2808 vc4->prog.cs = cs;
2809 vc4->dirty |= VC4_DIRTY_COMPILED_CS;
2810 }
2811 }
2812
2813 bool
2814 vc4_update_compiled_shaders(struct vc4_context *vc4, uint8_t prim_mode)
2815 {
2816 vc4_update_compiled_fs(vc4, prim_mode);
2817 vc4_update_compiled_vs(vc4, prim_mode);
2818
2819 return !(vc4->prog.cs->failed ||
2820 vc4->prog.vs->failed ||
2821 vc4->prog.fs->failed);
2822 }
2823
2824 static uint32_t
2825 fs_cache_hash(const void *key)
2826 {
2827 return _mesa_hash_data(key, sizeof(struct vc4_fs_key));
2828 }
2829
2830 static uint32_t
2831 vs_cache_hash(const void *key)
2832 {
2833 return _mesa_hash_data(key, sizeof(struct vc4_vs_key));
2834 }
2835
2836 static bool
2837 fs_cache_compare(const void *key1, const void *key2)
2838 {
2839 return memcmp(key1, key2, sizeof(struct vc4_fs_key)) == 0;
2840 }
2841
2842 static bool
2843 vs_cache_compare(const void *key1, const void *key2)
2844 {
2845 return memcmp(key1, key2, sizeof(struct vc4_vs_key)) == 0;
2846 }
2847
2848 static uint32_t
2849 fs_inputs_hash(const void *key)
2850 {
2851 const struct vc4_fs_inputs *inputs = key;
2852
2853 return _mesa_hash_data(inputs->input_slots,
2854 sizeof(*inputs->input_slots) *
2855 inputs->num_inputs);
2856 }
2857
2858 static bool
2859 fs_inputs_compare(const void *key1, const void *key2)
2860 {
2861 const struct vc4_fs_inputs *inputs1 = key1;
2862 const struct vc4_fs_inputs *inputs2 = key2;
2863
2864 return (inputs1->num_inputs == inputs2->num_inputs &&
2865 memcmp(inputs1->input_slots,
2866 inputs2->input_slots,
2867 sizeof(*inputs1->input_slots) *
2868 inputs1->num_inputs) == 0);
2869 }
2870
2871 static void
2872 delete_from_cache_if_matches(struct hash_table *ht,
2873 struct vc4_compiled_shader **last_compile,
2874 struct hash_entry *entry,
2875 struct vc4_uncompiled_shader *so)
2876 {
2877 const struct vc4_key *key = entry->key;
2878
2879 if (key->shader_state == so) {
2880 struct vc4_compiled_shader *shader = entry->data;
2881 _mesa_hash_table_remove(ht, entry);
2882 vc4_bo_unreference(&shader->bo);
2883
2884 if (shader == *last_compile)
2885 *last_compile = NULL;
2886
2887 ralloc_free(shader);
2888 }
2889 }
2890
2891 static void
2892 vc4_shader_state_delete(struct pipe_context *pctx, void *hwcso)
2893 {
2894 struct vc4_context *vc4 = vc4_context(pctx);
2895 struct vc4_uncompiled_shader *so = hwcso;
2896
2897 hash_table_foreach(vc4->fs_cache, entry) {
2898 delete_from_cache_if_matches(vc4->fs_cache, &vc4->prog.fs,
2899 entry, so);
2900 }
2901 hash_table_foreach(vc4->vs_cache, entry) {
2902 delete_from_cache_if_matches(vc4->vs_cache, &vc4->prog.vs,
2903 entry, so);
2904 }
2905
2906 ralloc_free(so->base.ir.nir);
2907 free(so);
2908 }
2909
2910 static void
2911 vc4_fp_state_bind(struct pipe_context *pctx, void *hwcso)
2912 {
2913 struct vc4_context *vc4 = vc4_context(pctx);
2914 vc4->prog.bind_fs = hwcso;
2915 vc4->dirty |= VC4_DIRTY_UNCOMPILED_FS;
2916 }
2917
2918 static void
2919 vc4_vp_state_bind(struct pipe_context *pctx, void *hwcso)
2920 {
2921 struct vc4_context *vc4 = vc4_context(pctx);
2922 vc4->prog.bind_vs = hwcso;
2923 vc4->dirty |= VC4_DIRTY_UNCOMPILED_VS;
2924 }
2925
2926 void
2927 vc4_program_init(struct pipe_context *pctx)
2928 {
2929 struct vc4_context *vc4 = vc4_context(pctx);
2930
2931 pctx->create_vs_state = vc4_shader_state_create;
2932 pctx->delete_vs_state = vc4_shader_state_delete;
2933
2934 pctx->create_fs_state = vc4_shader_state_create;
2935 pctx->delete_fs_state = vc4_shader_state_delete;
2936
2937 pctx->bind_fs_state = vc4_fp_state_bind;
2938 pctx->bind_vs_state = vc4_vp_state_bind;
2939
2940 vc4->fs_cache = _mesa_hash_table_create(pctx, fs_cache_hash,
2941 fs_cache_compare);
2942 vc4->vs_cache = _mesa_hash_table_create(pctx, vs_cache_hash,
2943 vs_cache_compare);
2944 vc4->fs_inputs_set = _mesa_set_create(pctx, fs_inputs_hash,
2945 fs_inputs_compare);
2946 }
2947
2948 void
2949 vc4_program_fini(struct pipe_context *pctx)
2950 {
2951 struct vc4_context *vc4 = vc4_context(pctx);
2952
2953 hash_table_foreach(vc4->fs_cache, entry) {
2954 struct vc4_compiled_shader *shader = entry->data;
2955 vc4_bo_unreference(&shader->bo);
2956 ralloc_free(shader);
2957 _mesa_hash_table_remove(vc4->fs_cache, entry);
2958 }
2959
2960 hash_table_foreach(vc4->vs_cache, entry) {
2961 struct vc4_compiled_shader *shader = entry->data;
2962 vc4_bo_unreference(&shader->bo);
2963 ralloc_free(shader);
2964 _mesa_hash_table_remove(vc4->vs_cache, entry);
2965 }
2966 }